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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2ff693534f8sm3391917a91.17.2025.03.07.10.56.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 10:56:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org Subject: [PATCH 01/16] include/exec: Split out exec/cpu-interrupt.h Date: Fri, 7 Mar 2025 10:56:30 -0800 Message-ID: <20250307185645.970034-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307185645.970034-1-richard.henderson@linaro.org> References: <20250307185645.970034-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Some of these bits are actually common to all cpus; while the reset have common reservations for target-specific usage. While generic code cannot know what the target-specific usage is, common code can know what to do with the bits, e.g. single-step. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé --- include/exec/cpu-all.h | 53 +-------------------------- include/exec/cpu-interrupt.h | 70 ++++++++++++++++++++++++++++++++++++ include/exec/poison.h | 13 ------- 3 files changed, 71 insertions(+), 65 deletions(-) create mode 100644 include/exec/cpu-interrupt.h diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 8f7aebb088..9e6724097c 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -21,6 +21,7 @@ #include "exec/page-protection.h" #include "exec/cpu-common.h" +#include "exec/cpu-interrupt.h" #include "exec/memory.h" #include "exec/tswap.h" #include "hw/core/cpu.h" @@ -109,58 +110,6 @@ static inline void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val CPUArchState *cpu_copy(CPUArchState *env); -/* Flags for use in ENV->INTERRUPT_PENDING. - - The numbers assigned here are non-sequential in order to preserve - binary compatibility with the vmstate dump. Bit 0 (0x0001) was - previously used for CPU_INTERRUPT_EXIT, and is cleared when loading - the vmstate dump. */ - -/* External hardware interrupt pending. This is typically used for - interrupts from devices. */ -#define CPU_INTERRUPT_HARD 0x0002 - -/* Exit the current TB. This is typically used when some system-level device - makes some change to the memory mapping. E.g. the a20 line change. */ -#define CPU_INTERRUPT_EXITTB 0x0004 - -/* Halt the CPU. */ -#define CPU_INTERRUPT_HALT 0x0020 - -/* Debug event pending. */ -#define CPU_INTERRUPT_DEBUG 0x0080 - -/* Reset signal. */ -#define CPU_INTERRUPT_RESET 0x0400 - -/* Several target-specific external hardware interrupts. Each target/cpu.h - should define proper names based on these defines. */ -#define CPU_INTERRUPT_TGT_EXT_0 0x0008 -#define CPU_INTERRUPT_TGT_EXT_1 0x0010 -#define CPU_INTERRUPT_TGT_EXT_2 0x0040 -#define CPU_INTERRUPT_TGT_EXT_3 0x0200 -#define CPU_INTERRUPT_TGT_EXT_4 0x1000 - -/* Several target-specific internal interrupts. These differ from the - preceding target-specific interrupts in that they are intended to - originate from within the cpu itself, typically in response to some - instruction being executed. These, therefore, are not masked while - single-stepping within the debugger. */ -#define CPU_INTERRUPT_TGT_INT_0 0x0100 -#define CPU_INTERRUPT_TGT_INT_1 0x0800 -#define CPU_INTERRUPT_TGT_INT_2 0x2000 - -/* First unused bit: 0x4000. */ - -/* The set of all bits that should be masked when single-stepping. */ -#define CPU_INTERRUPT_SSTEP_MASK \ - (CPU_INTERRUPT_HARD \ - | CPU_INTERRUPT_TGT_EXT_0 \ - | CPU_INTERRUPT_TGT_EXT_1 \ - | CPU_INTERRUPT_TGT_EXT_2 \ - | CPU_INTERRUPT_TGT_EXT_3 \ - | CPU_INTERRUPT_TGT_EXT_4) - #include "cpu.h" #ifdef CONFIG_USER_ONLY diff --git a/include/exec/cpu-interrupt.h b/include/exec/cpu-interrupt.h new file mode 100644 index 0000000000..40715193ca --- /dev/null +++ b/include/exec/cpu-interrupt.h @@ -0,0 +1,70 @@ +/* + * Flags for use with cpu_interrupt() + * + * Copyright (c) 2003 Fabrice Bellard + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#ifndef CPU_INTERRUPT_H +#define CPU_INTERRUPT_H + +/* + * The numbers assigned here are non-sequential in order to preserve binary + * compatibility with the vmstate dump. Bit 0 (0x0001) was previously used + * for CPU_INTERRUPT_EXIT, and is cleared when loading the vmstate dump. + */ + +/* + * External hardware interrupt pending. + * This is typically used for interrupts from devices. + */ +#define CPU_INTERRUPT_HARD 0x0002 + +/* + * Exit the current TB. This is typically used when some system-level device + * makes some change to the memory mapping. E.g. the a20 line change. + */ +#define CPU_INTERRUPT_EXITTB 0x0004 + +/* Halt the CPU. */ +#define CPU_INTERRUPT_HALT 0x0020 + +/* Debug event pending. */ +#define CPU_INTERRUPT_DEBUG 0x0080 + +/* Reset signal. */ +#define CPU_INTERRUPT_RESET 0x0400 + +/* + * Several target-specific external hardware interrupts. Each target/cpu.h + * should define proper names based on these defines. + */ +#define CPU_INTERRUPT_TGT_EXT_0 0x0008 +#define CPU_INTERRUPT_TGT_EXT_1 0x0010 +#define CPU_INTERRUPT_TGT_EXT_2 0x0040 +#define CPU_INTERRUPT_TGT_EXT_3 0x0200 +#define CPU_INTERRUPT_TGT_EXT_4 0x1000 + +/* + * Several target-specific internal interrupts. These differ from the + * preceding target-specific interrupts in that they are intended to + * originate from within the cpu itself, typically in response to some + * instruction being executed. These, therefore, are not masked while + * single-stepping within the debugger. + */ +#define CPU_INTERRUPT_TGT_INT_0 0x0100 +#define CPU_INTERRUPT_TGT_INT_1 0x0800 +#define CPU_INTERRUPT_TGT_INT_2 0x2000 + +/* First unused bit: 0x4000. */ + +/* The set of all bits that should be masked when single-stepping. */ +#define CPU_INTERRUPT_SSTEP_MASK \ + (CPU_INTERRUPT_HARD \ + | CPU_INTERRUPT_TGT_EXT_0 \ + | CPU_INTERRUPT_TGT_EXT_1 \ + | CPU_INTERRUPT_TGT_EXT_2 \ + | CPU_INTERRUPT_TGT_EXT_3 \ + | CPU_INTERRUPT_TGT_EXT_4) + +#endif /* CPU_INTERRUPT_H */ diff --git a/include/exec/poison.h b/include/exec/poison.h index 35721366d7..8ed04b3108 100644 --- a/include/exec/poison.h +++ b/include/exec/poison.h @@ -46,19 +46,6 @@ #pragma GCC poison TARGET_PHYS_ADDR_SPACE_BITS -#pragma GCC poison CPU_INTERRUPT_HARD -#pragma GCC poison CPU_INTERRUPT_EXITTB -#pragma GCC poison CPU_INTERRUPT_HALT -#pragma GCC poison CPU_INTERRUPT_DEBUG -#pragma GCC poison CPU_INTERRUPT_TGT_EXT_0 -#pragma GCC poison CPU_INTERRUPT_TGT_EXT_1 -#pragma GCC poison CPU_INTERRUPT_TGT_EXT_2 -#pragma GCC poison CPU_INTERRUPT_TGT_EXT_3 -#pragma GCC poison CPU_INTERRUPT_TGT_EXT_4 -#pragma GCC poison CPU_INTERRUPT_TGT_INT_0 -#pragma GCC poison CPU_INTERRUPT_TGT_INT_1 -#pragma GCC poison CPU_INTERRUPT_TGT_INT_2 - #pragma GCC poison CONFIG_ALPHA_DIS #pragma GCC poison CONFIG_HPPA_DIS #pragma GCC poison CONFIG_I386_DIS From patchwork Fri Mar 7 18:56:31 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 871248 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp916254wri; Fri, 7 Mar 2025 10:59:52 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXHMxmWfZpZNbnJLMAwu+rJU/VJExikIf7RFdsmURX6ivMUg4IWJIbBSlMBmnsLAA9+63npqw==@linaro.org X-Google-Smtp-Source: AGHT+IFTOanmDr4P00uqV4q9XZ+LmGIb9WNr8BrrUFM1JZK9YZUU885QQnJU3HGP69wQ8G/O/90X X-Received: by 2002:ac8:7d4d:0:b0:474:db2f:bd32 with SMTP id d75a77b69052e-4761194ab17mr59461341cf.38.1741373992152; Fri, 07 Mar 2025 10:59:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741373992; cv=none; d=google.com; s=arc-20240605; b=LoLZd5ZfhdYvms9xkaQs1/alIgHDQB0VhqQJqVimwB+J0vMA6VFLgHN5OI5hTVgFQf Q2SC8zi+NDDlmQLeKZR0fqd1FkRCgx2Mnrd6mxp3NtaniOLcnsEZVzzMtBt7hwFYZ/4a qPog/q6wFsqYtmhCCGwd1RI96gaBLKlHGbgSrb3NuGRZ0nz3x/h7udNjvc/MCVkm+Qc4 kTS41iK7ARiBxVBfBzc/0VZAFdKQsdZkmvCrqfdctctB6n02r1roHJ/lToD7YvjWeUd/ am0F21nBWxPqIFJ7L7d3v5UIeGRvJWtG7NiLFMROBxWFmp7/+uO2cFRgZzs722YyGXM2 0DqA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Vo9EUeboH3pwKtes0Z0Mb9EvndFByljrwhTfKec7eDo=; fh=ycigHkwOPieh2u5PmcA89sNk/qPD1ZkdDlL8Mchfvw8=; b=YoCiDN4E4mxMZTcM/mHA6dTBICJ170i9VVZGW6Q1upMhGjcNFK+/IHNh5Wxjisb2K3 r75kDVi/RpZmjsd6h1MhmbZatPdnXE1r/1vULgtipYb+3nIvkxRS3z3zp3NFYSBJYjxC OqwMidKEeuewfsg/WSIbVXqES/CNUm/vHNs+JHpWQBC9l/4i9Lbkp+AvNfKXZOT4gVTv K/AeeqYAOpKeT5DeapqjzBxjKGIfDdF2zwrhBT3ynLi4McJg8T6UftA3N3Cesdqqvh3L HICATEDerqzASvTGDQq5Xa7kBY39XTLbfmue8h+RpjkWDfCG7cupNPzppSXYOC03f8A6 6pdQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="nhFj/IK3"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2ff693534f8sm3391917a91.17.2025.03.07.10.56.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 10:56:49 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org Subject: [PATCH 02/16] accel/tcg: Compile watchpoint.c once Date: Fri, 7 Mar 2025 10:56:31 -0800 Message-ID: <20250307185645.970034-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307185645.970034-1-richard.henderson@linaro.org> References: <20250307185645.970034-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Move tb_check_watchpoint declaration from tb-internal.h, which is still target-specific, to internal-common.h, which isn't. Otherwise, all that is required to build watchpoint.c once is to include the new exec/cpu-interrupt.h instead of exec/exec-all.h. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé --- accel/tcg/internal-common.h | 2 ++ accel/tcg/tb-internal.h | 2 -- accel/tcg/watchpoint.c | 5 ++--- accel/tcg/meson.build | 2 +- 4 files changed, 5 insertions(+), 6 deletions(-) diff --git a/accel/tcg/internal-common.h b/accel/tcg/internal-common.h index 7ef620d963..9b6ab3a8cc 100644 --- a/accel/tcg/internal-common.h +++ b/accel/tcg/internal-common.h @@ -72,4 +72,6 @@ void tcg_exec_unrealizefn(CPUState *cpu); /* current cflags for hashing/comparison */ uint32_t curr_cflags(CPUState *cpu); +void tb_check_watchpoint(CPUState *cpu, uintptr_t retaddr); + #endif diff --git a/accel/tcg/tb-internal.h b/accel/tcg/tb-internal.h index abd423fcf5..62a59a5307 100644 --- a/accel/tcg/tb-internal.h +++ b/accel/tcg/tb-internal.h @@ -75,6 +75,4 @@ void tb_invalidate_phys_range_fast(ram_addr_t ram_addr, bool tb_invalidate_phys_page_unwind(tb_page_addr_t addr, uintptr_t pc); -void tb_check_watchpoint(CPUState *cpu, uintptr_t retaddr); - #endif diff --git a/accel/tcg/watchpoint.c b/accel/tcg/watchpoint.c index 40112b2b2e..ba8c9859cf 100644 --- a/accel/tcg/watchpoint.c +++ b/accel/tcg/watchpoint.c @@ -19,11 +19,10 @@ #include "qemu/osdep.h" #include "qemu/main-loop.h" -#include "qemu/error-report.h" -#include "exec/exec-all.h" +#include "exec/breakpoint.h" +#include "exec/cpu-interrupt.h" #include "exec/page-protection.h" #include "exec/translation-block.h" -#include "tb-internal.h" #include "system/tcg.h" #include "system/replay.h" #include "accel/tcg/cpu-ops.h" diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index 69f4808ac4..979ce90eb0 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -20,7 +20,6 @@ specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_specific_ss) specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files( 'cputlb.c', - 'watchpoint.c', 'tcg-accel-ops.c', 'tcg-accel-ops-mttcg.c', 'tcg-accel-ops-icount.c', @@ -30,4 +29,5 @@ specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files( system_ss.add(when: ['CONFIG_TCG'], if_true: files( 'icount-common.c', 'monitor.c', + 'watchpoint.c', )) From patchwork Fri Mar 7 18:56:32 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 871238 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp915810wri; Fri, 7 Mar 2025 10:58:33 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCV7HNcq7Y7sqCWVEBgivPgI06Ro0IkTh8e9FK0Q9xjgAYvStfaGU3W9K/njK6KBQZkgjG842g==@linaro.org X-Google-Smtp-Source: AGHT+IE5Whq59riZBCZykfVoAhjKg78zInzG/CV6Qzn3WMq1/Dpd0Y290BhGtnBOKR73uqOdVbBG X-Received: by 2002:ad4:5ae8:0:b0:6e4:41b3:497e with SMTP id 6a1803df08f44-6e9006cc1f6mr47290786d6.40.1741373913595; Fri, 07 Mar 2025 10:58:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741373913; cv=none; d=google.com; s=arc-20240605; b=YcsIcSB+q2VbZQO5FaysHmhY6kkReBZtEW+RgsD9wMwcE44QLxoLmCWQIP8txBfy4w 93o5nIOJWUppGUFkuTfGwX2Hk40jRjC+dZjFMU/eDJva0vGxGoHP4Ws9eePwU8MUDpye yhL8V4cKLM3IPkwjBOTqViXrplx/XLNzVV9tD+id72t+ntfpr4XqXL1P6UaQilSkfEo+ +8geXqG5vyDtTi4GUXAELQgWyq33vT+tD0aXFUzErczOa1zK630yUy9x7NH10jXpPCgs 8sLvDCZw3+7W0sWXv0cp/Vtg8x/aDaJXqaYLu9Yu+utrGnWBpD2KODYNtoqqgVNJ7Tsm P1ng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=k6rq6CIIqovi+rqTbWr+nZgRpCqEfphmlSslf2GR3LU=; fh=qKKfiElUquWdkyrWxyzPwUbXApIM0f/sdIVQxneHhZM=; b=PnUSpgFVE1nxkJf/el9oZq20YjF648pWv4fY2DlFD6bVHsJZTkR77T4QhwbIKBk6/V WcgeD7XSNOTgGbmWQ40OCF2z7PQZHU/W9zWci39OSIBe9SKz2QlNDIsnliIu3NaecsHc NMUMir8ybpJxynEyW+6582XKp/uBOmnv2Nsd5A/nVS1E6Vez1Tb2me0Z+wtLL1ofjSLr sl/ibmkb527bp8nJUJWsPLA07uqy7P4cYoMUAWUI2C88EiimGRemcydB+PBfPjHFTpNf nCtp3iInHTuKOJeG9z6cKKMNIOiaTjtu5kJx9tg3ruWJMC6Wam1MiUGKzydwLsktGb0g 2TGg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ApNry4HT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2ff693534f8sm3391917a91.17.2025.03.07.10.56.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 10:56:49 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, Pierrick Bouvier Subject: [PATCH 03/16] exec: Declare tlb_reset_dirty*() in 'exec/cputlb.h' Date: Fri, 7 Mar 2025 10:56:32 -0800 Message-ID: <20250307185645.970034-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307185645.970034-1-richard.henderson@linaro.org> References: <20250307185645.970034-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Message-ID: <20241114011310.3615-14-philmd@linaro.org> Signed-off-by: Richard Henderson --- include/exec/cputlb.h | 7 +++++++ include/exec/exec-all.h | 3 --- include/exec/ram_addr.h | 1 + system/physmem.c | 1 + 4 files changed, 9 insertions(+), 3 deletions(-) diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index ef18642a32..6cac7d530f 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -32,4 +32,11 @@ void tlb_unprotect_code(ram_addr_t ram_addr); #endif /* CONFIG_TCG */ +#ifndef CONFIG_USER_ONLY + +void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length); +void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length); + +#endif + #endif diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 8eb0df48f9..f24256fb5e 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -486,9 +486,6 @@ static inline tb_page_addr_t get_page_addr_code(CPUArchState *env, #if !defined(CONFIG_USER_ONLY) -void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length); -void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length); - MemoryRegionSection * address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr, hwaddr *xlat, hwaddr *plen, diff --git a/include/exec/ram_addr.h b/include/exec/ram_addr.h index 94bb3ccbe4..3d8df4edf1 100644 --- a/include/exec/ram_addr.h +++ b/include/exec/ram_addr.h @@ -23,6 +23,7 @@ #include "cpu.h" #include "system/xen.h" #include "system/tcg.h" +#include "exec/cputlb.h" #include "exec/ramlist.h" #include "exec/ramblock.h" #include "exec/exec-all.h" diff --git a/system/physmem.c b/system/physmem.c index 8c1736f84e..a6af555f4b 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -32,6 +32,7 @@ #endif /* CONFIG_TCG */ #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/target_page.h" #include "exec/translation-block.h" From patchwork Fri Mar 7 18:56:33 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 871234 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp915580wri; Fri, 7 Mar 2025 10:57:50 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVIGIvpW5bjSZrFZHsNsDzKYnWNRPLCBt7nLyVTE4lROr5Jf0DkS469YTv5psHTfxtpK4Batw==@linaro.org X-Google-Smtp-Source: AGHT+IGspUseayqRs2oBf0wLb8WGE/o/F/+InOGkF8vIOvbCG4xHPAElfP8QLD9zZur0yWlvjSBO X-Received: by 2002:ad4:5f85:0:b0:6e8:f598:f9ee with SMTP id 6a1803df08f44-6e9006f1c5fmr62836926d6.38.1741373870453; Fri, 07 Mar 2025 10:57:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741373870; cv=none; d=google.com; s=arc-20240605; b=WYb5HTpOyXkmxPbUZZArPbDec3fytcZRDnWjTz3cjJYc553PxC5azfgiy12EDRUZpx zQzkkTK0K4bOvnwmO24/0a4MVycwRjFp0ojs0MvRmH8vMRMTl4OGFQiwK4GxyC0YwJaq 0rK9Ffuhzma/Af77ECwcqEgVzgUk/NuqM89FyCKxn3hkltkzEEDbrB9KSUqQNtg5PeAM XtMtLtuwPL0CvIM/tU5bS4CrXOR4shqSc2aHCNXk+3N6GmdoyplIkoj8V7Oj9lTNK338 LxOsy/DPGwGeRnMdD08oGRgNopvNrH9KFUBz45g4azQPnQFawKaSpkxa0k1dDy02REY3 9gWQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=SzyDViup58ROLXi9a5eLqmvAZgtt4FP4fwTvGjoaRo8=; fh=qKKfiElUquWdkyrWxyzPwUbXApIM0f/sdIVQxneHhZM=; b=OkATDkY0finuL6ALkWgTMOHXQu2VKmaDYur+JeRajbU4uEgCZpl0QdEwJbr+kK+Opj ga3a5zYncyk0w4qDLrEVJ5DGVu1YAIyaMOfqzf2QDVCcawUBZc6HZAZ5IZf/u/wpIeiO WAC9cMweQk2IqscGZSHznqbIwzWxz2Xy8zPVu+dZnBL2dEOZUQ/Q1irr9NPIhzk9q477 jcb8XgiTINbwSFuRtdPRobfOcHYCuirI3gxRjGkogWDbpnFllNfNZMdrxhdsD05TDAfc G63a8Zf+HwDNncD3mPh3TP/bSXJUMS3ySEigSwZ3P+9voh5OQoSuA3W8Kv3bP4avLSPe osfw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="DywH/P87"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2ff693534f8sm3391917a91.17.2025.03.07.10.56.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 10:56:50 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, Pierrick Bouvier Subject: [PATCH 04/16] exec: Declare tlb_set_page_full() in 'exec/cputlb.h' Date: Fri, 7 Mar 2025 10:56:33 -0800 Message-ID: <20250307185645.970034-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307185645.970034-1-richard.henderson@linaro.org> References: <20250307185645.970034-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20241114011310.3615-16-philmd@linaro.org> --- include/exec/cputlb.h | 23 +++++++++++++++++++++++ include/exec/exec-all.h | 22 ---------------------- target/sparc/mmu_helper.c | 2 +- 3 files changed, 24 insertions(+), 23 deletions(-) diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index 6cac7d530f..733ef012d1 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -21,6 +21,7 @@ #define CPUTLB_H #include "exec/cpu-common.h" +#include "exec/vaddr.h" #ifdef CONFIG_TCG @@ -39,4 +40,26 @@ void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length); #endif +/** + * tlb_set_page_full: + * @cpu: CPU context + * @mmu_idx: mmu index of the tlb to modify + * @addr: virtual address of the entry to add + * @full: the details of the tlb entry + * + * Add an entry to @cpu tlb index @mmu_idx. All of the fields of + * @full must be filled, except for xlat_section, and constitute + * the complete description of the translated page. + * + * This is generally called by the target tlb_fill function after + * having performed a successful page table walk to find the physical + * address and attributes for the translation. + * + * At most one entry for a given virtual address is permitted. Only a + * single TARGET_PAGE_SIZE region is mapped; @full->lg_page_size is only + * used by tlb_flush_page. + */ +void tlb_set_page_full(CPUState *cpu, int mmu_idx, vaddr addr, + CPUTLBEntryFull *full); + #endif diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index f24256fb5e..f43c67366b 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -156,28 +156,6 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap, unsigned bits); -/** - * tlb_set_page_full: - * @cpu: CPU context - * @mmu_idx: mmu index of the tlb to modify - * @addr: virtual address of the entry to add - * @full: the details of the tlb entry - * - * Add an entry to @cpu tlb index @mmu_idx. All of the fields of - * @full must be filled, except for xlat_section, and constitute - * the complete description of the translated page. - * - * This is generally called by the target tlb_fill function after - * having performed a successful page table walk to find the physical - * address and attributes for the translation. - * - * At most one entry for a given virtual address is permitted. Only a - * single TARGET_PAGE_SIZE region is mapped; @full->lg_page_size is only - * used by tlb_flush_page. - */ -void tlb_set_page_full(CPUState *cpu, int mmu_idx, vaddr addr, - CPUTLBEntryFull *full); - /** * tlb_set_page_with_attrs: * @cpu: CPU to add this TLB entry for diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 9ff06026b8..7548d01777 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "qemu/qemu-print.h" #include "trace.h" From patchwork Fri Mar 7 18:56:34 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 871244 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp916076wri; Fri, 7 Mar 2025 10:59:22 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWEBQPE4XOnyNqHkaJ36DQ1bz6O0qYMzP5Fr6S9knTpp4pSmPZiUOI0cJ9utKb4MAVlwmOQAg==@linaro.org X-Google-Smtp-Source: AGHT+IERDfZQe/7G1B8ozwvrl/5yIifA6ZtG8AWt/C+nu3mQKtYC1nTDG5XfLo674J8+hha0x+0z X-Received: by 2002:a05:620a:2607:b0:7c0:b24c:c3c8 with SMTP id af79cd13be357-7c4e617ac54mr597416785a.42.1741373961760; Fri, 07 Mar 2025 10:59:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741373961; cv=none; d=google.com; s=arc-20240605; b=L06zaZ8CRqf6PLoNHV9JEEvFbdV1z1//3TgQnbo1DZSuI2SdooPk7kgf9M8HSlz53R mChQs78gObVDJtKrIi/xltus4zz50Eizdek//8PxLkcQVcNChlllqJnanZc1E6GX7DQY rB35E6sX9SU64h81KVeLpwM0hxYr0CM1QHzaeWewSidsJGEnwef5JBxFY3lEpe/WL5v7 Z39Uam+ijfizQwgK2qhd8xaEYfaANJEW4BUe2j8Vs7oRcC1RiTRPxz3nafKndEi+C2te 8E0ksX9cRy424ODczXNPtfu7vecpEvZmR7msNK+RWsARI2MauOPnrwd43J2VoRmFJpkz p/SQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=OZUhu3BnFzDT2DJGeBZFOFqKQQp7EogeXchL7RAMkqI=; fh=qKKfiElUquWdkyrWxyzPwUbXApIM0f/sdIVQxneHhZM=; b=M6lyM5YN76bw00xPZBObgsXDkdmkilcTrBqNWTyKsIp1Zu4k8/f8QeQsgp4axzGPLW REHIJRzoakW5wGek15tJ5mIskWg/mCcyAsfdKA9yQLLsiC1xXuCll1jC4nSe4CReu0N/ EtEfLG0rB0EAzn6pFxx0UMafJEkhI6SVBnbWu20HssxRw3jmnRJVw4JV74PBFuYZ6+xm wUCVQEmIVIU3LeE8+4Bb0pgk7fMzgAitpgVWlV72EvbDvlSBU61rK4AIl8dFLp21iexY 5rkM0qmDSZUiYuDHo8T0MMriWXwP3ol7RZy+lszi1sGl3fkoWfvk/8bqhSh4LAk+kEjU tofQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TjFxp62l; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2ff693534f8sm3391917a91.17.2025.03.07.10.56.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 10:56:51 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, Pierrick Bouvier Subject: [PATCH 05/16] exec: Declare tlb_set_page_with_attrs() in 'exec/cputlb.h' Date: Fri, 7 Mar 2025 10:56:34 -0800 Message-ID: <20250307185645.970034-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307185645.970034-1-richard.henderson@linaro.org> References: <20250307185645.970034-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20241114011310.3615-17-philmd@linaro.org> --- include/exec/cputlb.h | 28 ++++++++++++++++++++++++++++ include/exec/exec-all.h | 25 ------------------------- target/i386/tcg/system/excp_helper.c | 2 +- target/microblaze/helper.c | 2 +- 4 files changed, 30 insertions(+), 27 deletions(-) diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index 733ef012d1..56dd05a148 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -21,6 +21,8 @@ #define CPUTLB_H #include "exec/cpu-common.h" +#include "exec/hwaddr.h" +#include "exec/memattrs.h" #include "exec/vaddr.h" #ifdef CONFIG_TCG @@ -62,4 +64,30 @@ void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length); void tlb_set_page_full(CPUState *cpu, int mmu_idx, vaddr addr, CPUTLBEntryFull *full); +/** + * tlb_set_page_with_attrs: + * @cpu: CPU to add this TLB entry for + * @addr: virtual address of page to add entry for + * @paddr: physical address of the page + * @attrs: memory transaction attributes + * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits) + * @mmu_idx: MMU index to insert TLB entry for + * @size: size of the page in bytes + * + * Add an entry to this CPU's TLB (a mapping from virtual address + * @addr to physical address @paddr) with the specified memory + * transaction attributes. This is generally called by the target CPU + * specific code after it has been called through the tlb_fill() + * entry point and performed a successful page table walk to find + * the physical address and attributes for the virtual address + * which provoked the TLB miss. + * + * At most one entry for a given virtual address is permitted. Only a + * single TARGET_PAGE_SIZE region is mapped; the supplied @size is only + * used by tlb_flush_page. + */ +void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr, + hwaddr paddr, MemTxAttrs attrs, + int prot, int mmu_idx, vaddr size); + #endif diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index f43c67366b..62d6300752 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -156,31 +156,6 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap, unsigned bits); -/** - * tlb_set_page_with_attrs: - * @cpu: CPU to add this TLB entry for - * @addr: virtual address of page to add entry for - * @paddr: physical address of the page - * @attrs: memory transaction attributes - * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits) - * @mmu_idx: MMU index to insert TLB entry for - * @size: size of the page in bytes - * - * Add an entry to this CPU's TLB (a mapping from virtual address - * @addr to physical address @paddr) with the specified memory - * transaction attributes. This is generally called by the target CPU - * specific code after it has been called through the tlb_fill() - * entry point and performed a successful page table walk to find - * the physical address and attributes for the virtual address - * which provoked the TLB miss. - * - * At most one entry for a given virtual address is permitted. Only a - * single TARGET_PAGE_SIZE region is mapped; the supplied @size is only - * used by tlb_flush_page. - */ -void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr, - hwaddr paddr, MemTxAttrs attrs, - int prot, int mmu_idx, vaddr size); /* tlb_set_page: * * This function is equivalent to calling tlb_set_page_with_attrs() diff --git a/target/i386/tcg/system/excp_helper.c b/target/i386/tcg/system/excp_helper.c index 864e3140e3..6876329de2 100644 --- a/target/i386/tcg/system/excp_helper.c +++ b/target/i386/tcg/system/excp_helper.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/cpu_ldst.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "tcg/helper-tcg.h" diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 5d3259ce31..27fc929bee 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "qemu/host-utils.h" #include "exec/log.h" From patchwork Fri Mar 7 18:56:35 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 871243 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp916002wri; Fri, 7 Mar 2025 10:59:09 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUhWVAab4Q57KMpQKxxq+gNb821KIFUoLGjERQtvsXFsi6Abjhk7pVF6LtUFjVN2UdcIzrNjg==@linaro.org X-Google-Smtp-Source: AGHT+IFwiNCQ6C72UGMFnChbc/7q9OfLtKzaCgaMUla1jWZ7/AS7Zc/w57wcJ4R9t12aANn8lkVf X-Received: by 2002:a05:620a:2813:b0:7c0:7c49:a435 with SMTP id af79cd13be357-7c4e61b8decmr753908485a.52.1741373949185; Fri, 07 Mar 2025 10:59:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741373949; cv=none; d=google.com; s=arc-20240605; b=k0xWx0WWoG12IsxywtkubXlz7joRjJcjvZn/26WkCckumIT1lRkMKb3zMdL5EEnv69 6x6ppJc28y6M45TSMZqJU566cOnKRbssyTX+rg6T4BRAE5eHTYdlrHKH+MNpVxPD4aKF i1B9d0xVuGIxI7Uo0ermgj/ZCd6PJ96UgmcvAitQo3PuaUmWFYpm+ewk8TO0WQK89pVm QO+qUfP65Es+7PneJtNBCNdpGTseYEnEP5vByE1QIZ5dtrgyiuRLI0H4i6gYFCeK1BzA OMHy8UPNrvMZFKyu3ZbgpXjRMBJt1X8AhERFy9H/Xg+4alY2raIum1ckSIbyKNDjkegt EFBg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=4u5PBwHEPecUaxrqA3yTEFMGllvxnHxvoZEJcDTq3Zs=; fh=qKKfiElUquWdkyrWxyzPwUbXApIM0f/sdIVQxneHhZM=; b=CeQAguPOwreo28Lkmv42tWun+1oZ91dRAkYITu2n8QIn6+haHSXHdf4a3Zh8TZf7dk G3PY5arTAcSZQvv6hum2Oa5xnie/9H0JEn2BHoWc0+9RG/7SNFnwNOh/o//hIEHYcyKG JaCQoXd0dFhIkTZWphy8pq0zbIAsyN/P5FhCgnSDr3PNygeBCVMj/VsmswqN7FGI5ipB eO+erVMxPHRe9ybldNgp782R6foOwMavYmBGGTh1dQwIVhoWF9+rXo/zFi1MAjTJFgcV 5ch3Zxzd8DSx1cc3gEnQ67/H7MdbQBaSQqBG2gkc69RaG/BjKquV9SVq4E/sZUxTM/jr DJlw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=a4iDSzYS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2ff693534f8sm3391917a91.17.2025.03.07.10.56.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 10:56:52 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, Pierrick Bouvier Subject: [PATCH 06/16] exec: Declare tlb_set_page() in 'exec/cputlb.h' Date: Fri, 7 Mar 2025 10:56:35 -0800 Message-ID: <20250307185645.970034-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307185645.970034-1-richard.henderson@linaro.org> References: <20250307185645.970034-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20241114011310.3615-18-philmd@linaro.org> --- include/exec/cputlb.h | 11 +++++++++++ include/exec/exec-all.h | 9 --------- target/alpha/helper.c | 2 +- target/avr/helper.c | 2 +- target/loongarch/tcg/tlb_helper.c | 1 + target/m68k/helper.c | 1 + target/mips/tcg/system/tlb_helper.c | 1 + target/openrisc/mmu.c | 2 +- target/ppc/mmu_helper.c | 1 + target/riscv/cpu_helper.c | 1 + target/rx/cpu.c | 2 +- target/s390x/tcg/excp_helper.c | 1 + target/sh4/helper.c | 1 + target/tricore/helper.c | 2 +- target/xtensa/helper.c | 2 +- 15 files changed, 24 insertions(+), 15 deletions(-) diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index 56dd05a148..cdfaf17403 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -90,4 +90,15 @@ void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr, hwaddr paddr, MemTxAttrs attrs, int prot, int mmu_idx, vaddr size); +/** + * tlb_set_page: + * + * This function is equivalent to calling tlb_set_page_with_attrs() + * with an @attrs argument of MEMTXATTRS_UNSPECIFIED. It's provided + * as a convenience for CPUs which don't use memory transaction attributes. + */ +void tlb_set_page(CPUState *cpu, vaddr addr, + hwaddr paddr, int prot, + int mmu_idx, vaddr size); + #endif diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 62d6300752..a3aa8448d0 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -156,15 +156,6 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap, unsigned bits); -/* tlb_set_page: - * - * This function is equivalent to calling tlb_set_page_with_attrs() - * with an @attrs argument of MEMTXATTRS_UNSPECIFIED. It's provided - * as a convenience for CPUs which don't use memory transaction attributes. - */ -void tlb_set_page(CPUState *cpu, vaddr addr, - hwaddr paddr, int prot, - int mmu_idx, vaddr size); #else static inline void tlb_flush_page(CPUState *cpu, vaddr addr) { diff --git a/target/alpha/helper.c b/target/alpha/helper.c index 2f1000c99f..57cefcba14 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "fpu/softfloat-types.h" #include "exec/helper-proto.h" diff --git a/target/avr/helper.c b/target/avr/helper.c index 9ea6870e44..3412312ad5 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -23,7 +23,7 @@ #include "qemu/error-report.h" #include "cpu.h" #include "accel/tcg/cpu-ops.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/cpu_ldst.h" #include "exec/address-spaces.h" diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c index a323606e5a..f6b63c7224 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -12,6 +12,7 @@ #include "cpu.h" #include "internals.h" #include "exec/helper-proto.h" +#include "exec/cputlb.h" #include "exec/exec-all.h" #include "exec/page-protection.h" #include "exec/cpu_ldst.h" diff --git a/target/m68k/helper.c b/target/m68k/helper.c index beefeb7069..0bf574830f 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" +#include "exec/cputlb.h" #include "exec/exec-all.h" #include "exec/page-protection.h" #include "exec/gdbstub.h" diff --git a/target/mips/tcg/system/tlb_helper.c b/target/mips/tcg/system/tlb_helper.c index e98bb95951..ca4d6b27bc 100644 --- a/target/mips/tcg/system/tlb_helper.c +++ b/target/mips/tcg/system/tlb_helper.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "internal.h" +#include "exec/cputlb.h" #include "exec/exec-all.h" #include "exec/page-protection.h" #include "exec/cpu_ldst.h" diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index c632d5230b..47ac783c52 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -21,7 +21,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "gdbstub/helpers.h" #include "qemu/host-utils.h" diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index a802bc9c62..ad9ba8294c 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -24,6 +24,7 @@ #include "kvm_ppc.h" #include "mmu-hash64.h" #include "mmu-hash32.h" +#include "exec/cputlb.h" #include "exec/exec-all.h" #include "exec/page-protection.h" #include "exec/log.h" diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 34092f372d..6c4391d96b 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -23,6 +23,7 @@ #include "cpu.h" #include "internals.h" #include "pmu.h" +#include "exec/cputlb.h" #include "exec/exec-all.h" #include "exec/page-protection.h" #include "instmap.h" diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 1c40c8977e..f01e069a90 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -21,7 +21,7 @@ #include "qapi/error.h" #include "cpu.h" #include "migration/vmstate.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/translation-block.h" #include "hw/loader.h" diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c index 4c0b692c9e..f969850f87 100644 --- a/target/s390x/tcg/excp_helper.c +++ b/target/s390x/tcg/excp_helper.c @@ -22,6 +22,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/helper-proto.h" +#include "exec/cputlb.h" #include "exec/exec-all.h" #include "s390x-internal.h" #include "tcg_s390x.h" diff --git a/target/sh4/helper.c b/target/sh4/helper.c index b8774e046e..7567e6c8b6 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" +#include "exec/cputlb.h" #include "exec/exec-all.h" #include "exec/page-protection.h" #include "exec/log.h" diff --git a/target/tricore/helper.c b/target/tricore/helper.c index 9898752eb0..a64412e6bd 100644 --- a/target/tricore/helper.c +++ b/target/tricore/helper.c @@ -19,7 +19,7 @@ #include "qemu/log.h" #include "hw/registerfields.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "fpu/softfloat-helpers.h" #include "qemu/qemu-print.h" diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index f64699b116..4824b97e37 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -28,7 +28,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2ff693534f8sm3391917a91.17.2025.03.07.10.56.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 10:56:52 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, Pierrick Bouvier Subject: [PATCH 07/16] exec: Declare tlb_hit*() in 'exec/cputlb.h' Date: Fri, 7 Mar 2025 10:56:36 -0800 Message-ID: <20250307185645.970034-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307185645.970034-1-richard.henderson@linaro.org> References: <20250307185645.970034-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20241114011310.3615-20-philmd@linaro.org> --- include/exec/cpu-all.h | 23 ----------------------- accel/tcg/cputlb.c | 23 +++++++++++++++++++++++ 2 files changed, 23 insertions(+), 23 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 9e6724097c..8cd6c00cf8 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -179,29 +179,6 @@ static inline int cpu_mmu_index(CPUState *cs, bool ifetch) /* The two sets of flags must not overlap. */ QEMU_BUILD_BUG_ON(TLB_FLAGS_MASK & TLB_SLOW_FLAGS_MASK); -/** - * tlb_hit_page: return true if page aligned @addr is a hit against the - * TLB entry @tlb_addr - * - * @addr: virtual address to test (must be page aligned) - * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value) - */ -static inline bool tlb_hit_page(uint64_t tlb_addr, vaddr addr) -{ - return addr == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK)); -} - -/** - * tlb_hit: return true if @addr is a hit against the TLB entry @tlb_addr - * - * @addr: virtual address to test (need not be page aligned) - * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value) - */ -static inline bool tlb_hit(uint64_t tlb_addr, vaddr addr) -{ - return tlb_hit_page(tlb_addr, addr & TARGET_PAGE_MASK); -} - #endif /* !CONFIG_USER_ONLY */ /* Validate correct placement of CPUArchState. */ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index c8761683a0..fb22048876 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1201,6 +1201,29 @@ void tlb_set_page(CPUState *cpu, vaddr addr, prot, mmu_idx, size); } +/** + * tlb_hit_page: return true if page aligned @addr is a hit against the + * TLB entry @tlb_addr + * + * @addr: virtual address to test (must be page aligned) + * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value) + */ +static inline bool tlb_hit_page(uint64_t tlb_addr, vaddr addr) +{ + return addr == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK)); +} + +/** + * tlb_hit: return true if @addr is a hit against the TLB entry @tlb_addr + * + * @addr: virtual address to test (need not be page aligned) + * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value) + */ +static inline bool tlb_hit(uint64_t tlb_addr, vaddr addr) +{ + return tlb_hit_page(tlb_addr, addr & TARGET_PAGE_MASK); +} + /* * Note: tlb_fill_align() can trigger a resize of the TLB. * This means that all of the caller's prior references to the TLB table From patchwork Fri Mar 7 18:56:37 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 871245 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp916171wri; Fri, 7 Mar 2025 10:59:39 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUHKWPLS/Zc65ndgbLIxIv4P2sSYvPMsbMngMOWV1G0cD9b1esSSd6s0ldRtseXW3w+gy1Vyg==@linaro.org X-Google-Smtp-Source: AGHT+IH75nAZ4B3aA9mDQbr5CFJSD7FR0S802pitKZspzXYlezmkyNMmDBFoeX14bqVNcHtpB/gp X-Received: by 2002:ac8:7d55:0:b0:474:fc08:5527 with SMTP id d75a77b69052e-476109820abmr64081731cf.19.1741373979375; Fri, 07 Mar 2025 10:59:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741373979; cv=none; d=google.com; s=arc-20240605; b=QXHh6bNSZiYjh0b+WRTWKzveY4wZj4T8v6lNOlYak6b9lDTk66cgJ35BVh0uMaEAzR divuuBV46vEZITv72jooi2T4GTFvWyDhTaidjdK3dzBww2I11lduCQFTSDFmXfcI6/Oi PYu+0HnSxUKY330IrUDRmbuwo4LIeSnTilA2JKhdhZjSTlvIY17NmRAV7y3bog5KSRrU 3NUiTB5aJ2kNESET4asF8sedX8izdGXNQs0lInrtwMUg+P1qut2V/DatH2EbLXMwJozy KKXCE9xWWbPEpRI9JQ744PT7UhIZGVvIpf3SBbs4TzN/zEsGVD6JVYzf6ruMCUt867eM 5yGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=+PiHnQ+1q+MwLFjoc0q+vLnYcSz+0aCBgyfQrhPwFSE=; fh=qKKfiElUquWdkyrWxyzPwUbXApIM0f/sdIVQxneHhZM=; b=cjUJT311G9n89cghnsrfCnnkDQYiWzVkBRqyFxLnVN1MX2QUESUxlcVMdMb1PBPuYg eJYbwvNcKnYt4m72O1ErfNhws19z5qiIIpew9OxVuqFyKlV7QIVFPJqtjplcLiwtFeYq Jo4caYNJJn4ZZYEmBMtlUqSohYsKjDfqn/wbT+WtzL729QSMwgzpTNm8lm2JiD+Ou2VL 52M5ShRY+XVujZ2mKoFF+2wDb0SRPwibx7DobRvtUStVzZkv0soVeKmHcYE/wZKRqPLo GLp5Z2s7EvUnEepRaQiknMVs8yufmNVKgMq8i09XX3WVAi+sAI//R3es/wJmOzaLUnwo MWeA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="q0Awfi/0"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2ff693534f8sm3391917a91.17.2025.03.07.10.56.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 10:56:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, Pierrick Bouvier Subject: [PATCH 08/16] exec: Declare tlb_flush*() in 'exec/cputlb.h' Date: Fri, 7 Mar 2025 10:56:37 -0800 Message-ID: <20250307185645.970034-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307185645.970034-1-richard.henderson@linaro.org> References: <20250307185645.970034-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Pierrick Bouvier Message-ID: <20241114011310.3615-19-philmd@linaro.org> Signed-off-by: Richard Henderson --- include/exec/cputlb.h | 200 +++++++++++++++++++++++++-- include/exec/exec-all.h | 184 ------------------------ accel/tcg/tcg-accel-ops.c | 2 +- cpu-target.c | 1 + hw/intc/armv7m_nvic.c | 2 +- hw/ppc/spapr_nested.c | 1 + hw/sh4/sh7750.c | 1 + system/watchpoint.c | 3 +- target/alpha/sys_helper.c | 2 +- target/arm/helper.c | 1 + target/arm/tcg/tlb-insns.c | 2 +- target/hppa/mem_helper.c | 1 + target/i386/helper.c | 2 +- target/i386/machine.c | 2 +- target/i386/tcg/fpu_helper.c | 2 +- target/i386/tcg/misc_helper.c | 2 +- target/i386/tcg/system/misc_helper.c | 2 +- target/i386/tcg/system/svm_helper.c | 2 +- target/loongarch/tcg/csr_helper.c | 2 +- target/microblaze/mmu.c | 2 +- target/mips/system/cp0.c | 2 +- target/mips/tcg/system/cp0_helper.c | 2 +- target/openrisc/sys_helper.c | 1 + target/ppc/helper_regs.c | 2 +- target/ppc/misc_helper.c | 1 + target/riscv/csr.c | 1 + target/riscv/op_helper.c | 1 + target/riscv/pmp.c | 2 +- target/s390x/gdbstub.c | 2 +- target/s390x/sigp.c | 1 + target/s390x/tcg/mem_helper.c | 1 + target/s390x/tcg/misc_helper.c | 1 + target/sparc/ldst_helper.c | 1 + target/xtensa/mmu_helper.c | 1 + 34 files changed, 224 insertions(+), 211 deletions(-) diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index cdfaf17403..8125f6809c 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -25,21 +25,14 @@ #include "exec/memattrs.h" #include "exec/vaddr.h" -#ifdef CONFIG_TCG - -#if !defined(CONFIG_USER_ONLY) -/* cputlb.c */ +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) void tlb_protect_code(ram_addr_t ram_addr); void tlb_unprotect_code(ram_addr_t ram_addr); #endif -#endif /* CONFIG_TCG */ - #ifndef CONFIG_USER_ONLY - void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length); void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length); - #endif /** @@ -101,4 +94,193 @@ void tlb_set_page(CPUState *cpu, vaddr addr, hwaddr paddr, int prot, int mmu_idx, vaddr size); -#endif +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) +/** + * tlb_flush_page: + * @cpu: CPU whose TLB should be flushed + * @addr: virtual address of page to be flushed + * + * Flush one page from the TLB of the specified CPU, for all + * MMU indexes. + */ +void tlb_flush_page(CPUState *cpu, vaddr addr); + +/** + * tlb_flush_page_all_cpus_synced: + * @cpu: src CPU of the flush + * @addr: virtual address of page to be flushed + * + * Flush one page from the TLB of all CPUs, for all + * MMU indexes. + * + * When this function returns, no CPUs will subsequently perform + * translations using the flushed TLBs. + */ +void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr addr); + +/** + * tlb_flush: + * @cpu: CPU whose TLB should be flushed + * + * Flush the entire TLB for the specified CPU. Most CPU architectures + * allow the implementation to drop entries from the TLB at any time + * so this is generally safe. If more selective flushing is required + * use one of the other functions for efficiency. + */ +void tlb_flush(CPUState *cpu); + +/** + * tlb_flush_all_cpus_synced: + * @cpu: src CPU of the flush + * + * Flush the entire TLB for all CPUs, for all MMU indexes. + * + * When this function returns, no CPUs will subsequently perform + * translations using the flushed TLBs. + */ +void tlb_flush_all_cpus_synced(CPUState *src_cpu); + +/** + * tlb_flush_page_by_mmuidx: + * @cpu: CPU whose TLB should be flushed + * @addr: virtual address of page to be flushed + * @idxmap: bitmap of MMU indexes to flush + * + * Flush one page from the TLB of the specified CPU, for the specified + * MMU indexes. + */ +void tlb_flush_page_by_mmuidx(CPUState *cpu, vaddr addr, + uint16_t idxmap); + +/** + * tlb_flush_page_by_mmuidx_all_cpus_synced: + * @cpu: Originating CPU of the flush + * @addr: virtual address of page to be flushed + * @idxmap: bitmap of MMU indexes to flush + * + * Flush one page from the TLB of all CPUs, for the specified + * MMU indexes. + * + * When this function returns, no CPUs will subsequently perform + * translations using the flushed TLBs. + */ +void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr, + uint16_t idxmap); + +/** + * tlb_flush_by_mmuidx: + * @cpu: CPU whose TLB should be flushed + * @wait: If true ensure synchronisation by exiting the cpu_loop + * @idxmap: bitmap of MMU indexes to flush + * + * Flush all entries from the TLB of the specified CPU, for the specified + * MMU indexes. + */ +void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap); + +/** + * tlb_flush_by_mmuidx_all_cpus_synced: + * @cpu: Originating CPU of the flush + * @idxmap: bitmap of MMU indexes to flush + * + * Flush all entries from the TLB of all CPUs, for the specified + * MMU indexes. + * + * When this function returns, no CPUs will subsequently perform + * translations using the flushed TLBs. + */ +void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap); + +/** + * tlb_flush_page_bits_by_mmuidx + * @cpu: CPU whose TLB should be flushed + * @addr: virtual address of page to be flushed + * @idxmap: bitmap of mmu indexes to flush + * @bits: number of significant bits in address + * + * Similar to tlb_flush_page_mask, but with a bitmap of indexes. + */ +void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, vaddr addr, + uint16_t idxmap, unsigned bits); + +/* Similarly, with broadcast and syncing. */ +void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr, + uint16_t idxmap, + unsigned bits); + +/** + * tlb_flush_range_by_mmuidx + * @cpu: CPU whose TLB should be flushed + * @addr: virtual address of the start of the range to be flushed + * @len: length of range to be flushed + * @idxmap: bitmap of mmu indexes to flush + * @bits: number of significant bits in address + * + * For each mmuidx in @idxmap, flush all pages within [@addr,@addr+@len), + * comparing only the low @bits worth of each virtual page. + */ +void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr, + vaddr len, uint16_t idxmap, + unsigned bits); + +/* Similarly, with broadcast and syncing. */ +void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, + vaddr addr, + vaddr len, + uint16_t idxmap, + unsigned bits); +#else +static inline void tlb_flush_page(CPUState *cpu, vaddr addr) +{ +} +static inline void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr addr) +{ +} +static inline void tlb_flush(CPUState *cpu) +{ +} +static inline void tlb_flush_all_cpus_synced(CPUState *src_cpu) +{ +} +static inline void tlb_flush_page_by_mmuidx(CPUState *cpu, + vaddr addr, uint16_t idxmap) +{ +} + +static inline void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap) +{ +} +static inline void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, + vaddr addr, + uint16_t idxmap) +{ +} +static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, + uint16_t idxmap) +{ +} +static inline void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, + vaddr addr, + uint16_t idxmap, + unsigned bits) +{ +} +static inline void +tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr, + uint16_t idxmap, unsigned bits) +{ +} +static inline void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr, + vaddr len, uint16_t idxmap, + unsigned bits) +{ +} +static inline void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, + vaddr addr, + vaddr len, + uint16_t idxmap, + unsigned bits) +{ +} +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ +#endif /* CPUTLB_H */ diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index a3aa8448d0..a758b7a843 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -27,190 +27,6 @@ #include "exec/mmu-access-type.h" #include "exec/translation-block.h" -#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) -/* cputlb.c */ -/** - * tlb_flush_page: - * @cpu: CPU whose TLB should be flushed - * @addr: virtual address of page to be flushed - * - * Flush one page from the TLB of the specified CPU, for all - * MMU indexes. - */ -void tlb_flush_page(CPUState *cpu, vaddr addr); -/** - * tlb_flush_page_all_cpus_synced: - * @cpu: src CPU of the flush - * @addr: virtual address of page to be flushed - * - * Flush one page from the TLB of all CPUs, for all - * MMU indexes. - * - * When this function returns, no CPUs will subsequently perform - * translations using the flushed TLBs. - */ -void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr addr); -/** - * tlb_flush: - * @cpu: CPU whose TLB should be flushed - * - * Flush the entire TLB for the specified CPU. Most CPU architectures - * allow the implementation to drop entries from the TLB at any time - * so this is generally safe. If more selective flushing is required - * use one of the other functions for efficiency. - */ -void tlb_flush(CPUState *cpu); -/** - * tlb_flush_all_cpus_synced: - * @cpu: src CPU of the flush - * - * Flush the entire TLB for all CPUs, for all MMU indexes. - * - * When this function returns, no CPUs will subsequently perform - * translations using the flushed TLBs. - */ -void tlb_flush_all_cpus_synced(CPUState *src_cpu); -/** - * tlb_flush_page_by_mmuidx: - * @cpu: CPU whose TLB should be flushed - * @addr: virtual address of page to be flushed - * @idxmap: bitmap of MMU indexes to flush - * - * Flush one page from the TLB of the specified CPU, for the specified - * MMU indexes. - */ -void tlb_flush_page_by_mmuidx(CPUState *cpu, vaddr addr, - uint16_t idxmap); -/** - * tlb_flush_page_by_mmuidx_all_cpus_synced: - * @cpu: Originating CPU of the flush - * @addr: virtual address of page to be flushed - * @idxmap: bitmap of MMU indexes to flush - * - * Flush one page from the TLB of all CPUs, for the specified - * MMU indexes. - * - * When this function returns, no CPUs will subsequently perform - * translations using the flushed TLBs. - */ -void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr, - uint16_t idxmap); -/** - * tlb_flush_by_mmuidx: - * @cpu: CPU whose TLB should be flushed - * @wait: If true ensure synchronisation by exiting the cpu_loop - * @idxmap: bitmap of MMU indexes to flush - * - * Flush all entries from the TLB of the specified CPU, for the specified - * MMU indexes. - */ -void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap); -/** - * tlb_flush_by_mmuidx_all_cpus_synced: - * @cpu: Originating CPU of the flush - * @idxmap: bitmap of MMU indexes to flush - * - * Flush all entries from the TLB of all CPUs, for the specified - * MMU indexes. - * - * When this function returns, no CPUs will subsequently perform - * translations using the flushed TLBs. - */ -void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap); - -/** - * tlb_flush_page_bits_by_mmuidx - * @cpu: CPU whose TLB should be flushed - * @addr: virtual address of page to be flushed - * @idxmap: bitmap of mmu indexes to flush - * @bits: number of significant bits in address - * - * Similar to tlb_flush_page_mask, but with a bitmap of indexes. - */ -void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, vaddr addr, - uint16_t idxmap, unsigned bits); - -/* Similarly, with broadcast and syncing. */ -void tlb_flush_page_bits_by_mmuidx_all_cpus_synced - (CPUState *cpu, vaddr addr, uint16_t idxmap, unsigned bits); - -/** - * tlb_flush_range_by_mmuidx - * @cpu: CPU whose TLB should be flushed - * @addr: virtual address of the start of the range to be flushed - * @len: length of range to be flushed - * @idxmap: bitmap of mmu indexes to flush - * @bits: number of significant bits in address - * - * For each mmuidx in @idxmap, flush all pages within [@addr,@addr+@len), - * comparing only the low @bits worth of each virtual page. - */ -void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr, - vaddr len, uint16_t idxmap, - unsigned bits); - -/* Similarly, with broadcast and syncing. */ -void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, - vaddr addr, - vaddr len, - uint16_t idxmap, - unsigned bits); - -#else -static inline void tlb_flush_page(CPUState *cpu, vaddr addr) -{ -} -static inline void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr addr) -{ -} -static inline void tlb_flush(CPUState *cpu) -{ -} -static inline void tlb_flush_all_cpus_synced(CPUState *src_cpu) -{ -} -static inline void tlb_flush_page_by_mmuidx(CPUState *cpu, - vaddr addr, uint16_t idxmap) -{ -} - -static inline void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap) -{ -} -static inline void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, - vaddr addr, - uint16_t idxmap) -{ -} -static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, - uint16_t idxmap) -{ -} -static inline void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, - vaddr addr, - uint16_t idxmap, - unsigned bits) -{ -} -static inline void -tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr, - uint16_t idxmap, unsigned bits) -{ -} -static inline void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr, - vaddr len, uint16_t idxmap, - unsigned bits) -{ -} -static inline void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, - vaddr addr, - vaddr len, - uint16_t idxmap, - unsigned bits) -{ -} -#endif - #if defined(CONFIG_TCG) /** diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index 132c5d1461..53e580d128 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -33,7 +33,7 @@ #include "qemu/main-loop.h" #include "qemu/guest-random.h" #include "qemu/timer.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/hwaddr.h" #include "exec/tb-flush.h" #include "exec/translation-block.h" diff --git a/cpu-target.c b/cpu-target.c index 5aa6c4b0c6..b6e66d5ac0 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -31,6 +31,7 @@ #include "exec/tswap.h" #include "exec/replay-core.h" #include "exec/cpu-common.h" +#include "exec/cputlb.h" #include "exec/exec-all.h" #include "exec/tb-flush.h" #include "exec/log.h" diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 5fd0760982..7212c87c68 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -22,7 +22,7 @@ #include "system/runstate.h" #include "target/arm/cpu.h" #include "target/arm/cpu-features.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/memop.h" #include "qemu/log.h" #include "qemu/module.h" diff --git a/hw/ppc/spapr_nested.c b/hw/ppc/spapr_nested.c index 7def8eb73b..23958c6383 100644 --- a/hw/ppc/spapr_nested.c +++ b/hw/ppc/spapr_nested.c @@ -1,6 +1,7 @@ #include "qemu/osdep.h" #include "qemu/cutils.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "helper_regs.h" #include "hw/ppc/ppc.h" #include "hw/ppc/spapr.h" diff --git a/hw/sh4/sh7750.c b/hw/sh4/sh7750.c index 8892eaddcb..6faf0e3ca8 100644 --- a/hw/sh4/sh7750.c +++ b/hw/sh4/sh7750.c @@ -36,6 +36,7 @@ #include "hw/sh4/sh_intc.h" #include "hw/timer/tmu012.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "trace.h" typedef struct SH7750State { diff --git a/system/watchpoint.c b/system/watchpoint.c index 2aa2a9ea63..08dbd8483d 100644 --- a/system/watchpoint.c +++ b/system/watchpoint.c @@ -19,7 +19,8 @@ #include "qemu/osdep.h" #include "qemu/error-report.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" +#include "exec/target_page.h" #include "hw/core/cpu.h" /* Add a watchpoint. */ diff --git a/target/alpha/sys_helper.c b/target/alpha/sys_helper.c index 54ee93f34c..51e3254428 100644 --- a/target/alpha/sys_helper.c +++ b/target/alpha/sys_helper.c @@ -19,7 +19,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/tb-flush.h" #include "exec/helper-proto.h" #include "system/runstate.h" diff --git a/target/arm/helper.c b/target/arm/helper.c index 71dead7241..e786c8df5f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -18,6 +18,7 @@ #include "qemu/timer.h" #include "qemu/bitops.h" #include "qemu/qemu-print.h" +#include "exec/cputlb.h" #include "exec/exec-all.h" #include "exec/translation-block.h" #include "hw/irq.h" diff --git a/target/arm/tcg/tlb-insns.c b/target/arm/tcg/tlb-insns.c index fadc61a76e..630a481f0f 100644 --- a/target/arm/tcg/tlb-insns.c +++ b/target/arm/tcg/tlb-insns.c @@ -7,7 +7,7 @@ */ #include "qemu/osdep.h" #include "qemu/log.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "cpu.h" #include "internals.h" #include "cpu-features.h" diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 304f0b61e2..fb1d93ef1f 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -21,6 +21,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/helper-proto.h" #include "hw/core/cpu.h" diff --git a/target/i386/helper.c b/target/i386/helper.c index 3bc15fba6e..c07b1b16ea 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "qapi/qapi-events-run-state.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/translation-block.h" #include "system/runstate.h" #ifndef CONFIG_USER_ONLY diff --git a/target/i386/machine.c b/target/i386/machine.c index d9d4f25d1a..70f632a36f 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -1,6 +1,6 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "hw/isa/isa.h" #include "migration/cpu.h" #include "kvm/hyperv.h" diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index 4858ae9a5f..c1184ca219 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -21,7 +21,7 @@ #include #include "cpu.h" #include "tcg-cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" #include "fpu/softfloat.h" diff --git a/target/i386/tcg/misc_helper.c b/target/i386/tcg/misc_helper.c index ed4cda8001..2b5f092a23 100644 --- a/target/i386/tcg/misc_helper.c +++ b/target/i386/tcg/misc_helper.c @@ -21,7 +21,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "helper-tcg.h" /* diff --git a/target/i386/tcg/system/misc_helper.c b/target/i386/tcg/system/misc_helper.c index c9c4d42f84..ce18c75b9f 100644 --- a/target/i386/tcg/system/misc_helper.c +++ b/target/i386/tcg/system/misc_helper.c @@ -23,7 +23,7 @@ #include "exec/helper-proto.h" #include "exec/cpu_ldst.h" #include "exec/address-spaces.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "tcg/helper-tcg.h" #include "hw/i386/apic.h" diff --git a/target/i386/tcg/system/svm_helper.c b/target/i386/tcg/system/svm_helper.c index 5f95b5227b..f9982b72d1 100644 --- a/target/i386/tcg/system/svm_helper.c +++ b/target/i386/tcg/system/svm_helper.c @@ -21,7 +21,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/cpu_ldst.h" #include "tcg/helper-tcg.h" diff --git a/target/loongarch/tcg/csr_helper.c b/target/loongarch/tcg/csr_helper.c index 6c95be9910..84f7ff25f6 100644 --- a/target/loongarch/tcg/csr_helper.c +++ b/target/loongarch/tcg/csr_helper.c @@ -12,7 +12,7 @@ #include "internals.h" #include "qemu/host-utils.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/cpu_ldst.h" #include "hw/irq.h" #include "cpu-csr.h" diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c index 2423ac6172..f8587d5ac4 100644 --- a/target/microblaze/mmu.c +++ b/target/microblaze/mmu.c @@ -21,7 +21,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" static unsigned int tlb_decode_size(unsigned int f) diff --git a/target/mips/system/cp0.c b/target/mips/system/cp0.c index bae37f515b..ff7d3db00c 100644 --- a/target/mips/system/cp0.c +++ b/target/mips/system/cp0.c @@ -21,7 +21,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "internal.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" /* Called for updates to CP0_Status. */ void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc) diff --git a/target/mips/tcg/system/cp0_helper.c b/target/mips/tcg/system/cp0_helper.c index 79a5c833ce..01a07a169f 100644 --- a/target/mips/tcg/system/cp0_helper.c +++ b/target/mips/tcg/system/cp0_helper.c @@ -27,7 +27,7 @@ #include "internal.h" #include "qemu/host-utils.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" /* SMP helpers. */ diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 77567afba4..21bc137ccc 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/helper-proto.h" #include "exception.h" #ifndef CONFIG_USER_ONLY diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index 3ad4273c16..f211bc9830 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "qemu/main-loop.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "system/kvm.h" #include "system/tcg.h" #include "helper_regs.h" diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c index f0ca80153b..e379da6010 100644 --- a/target/ppc/misc_helper.c +++ b/target/ppc/misc_helper.c @@ -21,6 +21,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/helper-proto.h" #include "qemu/error-report.h" #include "qemu/main-loop.h" diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 0ebcca4597..49566d3c08 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -25,6 +25,7 @@ #include "pmu.h" #include "time_helper.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/tb-flush.h" #include "system/cpu-timers.h" #include "qemu/guest-random.h" diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index f156bfab12..0d4220ba93 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "internals.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" #include "trace.h" diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 85ab270dad..b0841d44f4 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -24,7 +24,7 @@ #include "qapi/error.h" #include "cpu.h" #include "trace.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" static bool pmp_write_cfg(CPURISCVState *env, uint32_t addr_index, diff --git a/target/s390x/gdbstub.c b/target/s390x/gdbstub.c index 6879430adc..6bca376f2b 100644 --- a/target/s390x/gdbstub.c +++ b/target/s390x/gdbstub.c @@ -21,7 +21,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "s390x-internal.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/gdbstub.h" #include "gdbstub/helpers.h" #include "qemu/bitops.h" diff --git a/target/s390x/sigp.c b/target/s390x/sigp.c index cf53b23291..6a4d9c5081 100644 --- a/target/s390x/sigp.c +++ b/target/s390x/sigp.c @@ -15,6 +15,7 @@ #include "system/hw_accel.h" #include "system/runstate.h" #include "exec/address-spaces.h" +#include "exec/cputlb.h" #include "exec/exec-all.h" #include "system/tcg.h" #include "trace.h" diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index ea9fa64d6b..8187b917ba 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -26,6 +26,7 @@ #include "exec/helper-proto.h" #include "exec/cpu-common.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/cpu_ldst.h" #include "accel/tcg/cpu-ops.h" diff --git a/target/s390x/tcg/misc_helper.c b/target/s390x/tcg/misc_helper.c index 0245451472..31266aeda4 100644 --- a/target/s390x/tcg/misc_helper.c +++ b/target/s390x/tcg/misc_helper.c @@ -27,6 +27,7 @@ #include "exec/helper-proto.h" #include "qemu/timer.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/cpu_ldst.h" #include "qapi/error.h" #include "tcg_s390x.h" diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 4c54e45655..b559afc9a9 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -24,6 +24,7 @@ #include "tcg/tcg.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/cpu_ldst.h" #ifdef CONFIG_USER_ONLY diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c index 29b84d5dbf..63be741a42 100644 --- a/target/xtensa/mmu_helper.c +++ b/target/xtensa/mmu_helper.c @@ -32,6 +32,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "qemu/host-utils.h" +#include "exec/cputlb.h" #include "exec/exec-all.h" #include "exec/page-protection.h" From patchwork Fri Mar 7 18:56:38 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 871239 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp915835wri; Fri, 7 Mar 2025 10:58:37 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVSwHykOvc9/PA5ty11oAeQtIdiXK+1Plfb17H/KawO4FbRIeSt3IsRApaSdtJr0D2vi7QUqg==@linaro.org X-Google-Smtp-Source: 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2ff693534f8sm3391917a91.17.2025.03.07.10.56.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 10:56:54 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org Subject: [PATCH 09/16] system: Build watchpoint.c once Date: Fri, 7 Mar 2025 10:56:38 -0800 Message-ID: <20250307185645.970034-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307185645.970034-1-richard.henderson@linaro.org> References: <20250307185645.970034-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Now that watchpoint.c uses cputlb.h instead of exec-all.h, it can be built once. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé --- system/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/system/meson.build b/system/meson.build index 4952f4b2c7..c83d80fa24 100644 --- a/system/meson.build +++ b/system/meson.build @@ -3,7 +3,6 @@ specific_ss.add(when: 'CONFIG_SYSTEM_ONLY', if_true: [files( 'ioport.c', 'memory.c', 'physmem.c', - 'watchpoint.c', )]) system_ss.add(files( @@ -24,6 +23,7 @@ system_ss.add(files( 'runstate.c', 'tpm-hmp-cmds.c', 'vl.c', + 'watchpoint.c', ), sdl, libpmem, libdaxctl) if have_tpm From patchwork Fri Mar 7 18:56:39 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 871235 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp915641wri; Fri, 7 Mar 2025 10:58:07 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUSH600O+IjAJOP7LkRHdjL8ijdVclPEG49czGKwktoG3o15gbTfNGQibESExTMF3lHOjDIFA==@linaro.org X-Google-Smtp-Source: AGHT+IHr4BXJWE1LZQ3dRS25H5U3CZLp+BtCkj7IZaBwKZe8LE5JocRAJr+QDCNhm9h8EQvaOZ8s X-Received: by 2002:ac8:5f93:0:b0:474:e756:fd14 with SMTP id d75a77b69052e-476119503b2mr46542751cf.42.1741373887424; Fri, 07 Mar 2025 10:58:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741373887; cv=none; d=google.com; s=arc-20240605; b=DakcKmAXZpIHrk3MesN/7rMomV5O5PpTxjc/UEIcPld5XTKLMIRRPBQXkOE6SF2vi9 hBGX6Pj0VqFr0vlTp5q2cre7aeWb1vT1HtGS5hO+uTidtMkKf8fFb9kJRs3vNdQJpaXr RhjL+H2f934vGekIGbSrJGldntsujqu2eVBXNJ0S/2qMDV/mpUzg5thc7sabbi/eoEjR NEaGSCdCn7ZNpcGGVcKAuCjvDgx7Ah/cb1SmxqHfXT6yk6rgzWa09JxWzCmP1G7TeWQZ Js5jxESa2IYyO2gtR0NidoLl0zf1b6G02bF9j75be5xiZxw1xltH87add8sb2xrNfJDy PJWA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=YJaPAtjiKCI7xNvYK1z8ajXotpby2ndW32q1olZ40bI=; fh=ycigHkwOPieh2u5PmcA89sNk/qPD1ZkdDlL8Mchfvw8=; b=cxRKejbtqn79pi4mEQqQacfDcaGtAO0/fHXx8NdQnlsTWyYlOT/AxTOb0UMylJs62u 0tJtBIk2od92XUSK2IV85662OEqcYjlwAID1pCRx1OdkO6+Kj0sQZ3jpd5suMa0v3Ozv xzNEUT5okJJUnyd2KgfwnbZCWZYF6rtDUxU3XoPTFL6PyYy+pi3SD04Vt/BQd+BvsE96 FQrLkRwBjSPWpQJ/PU4oKqRZLSY3BnF9SRcuRng6yb7vBeg6/AcxMDvo2CbdHM//SYZe UwAFEsCMH2I6F94gVwqsP5dhB65n3NpNMgXw8rxdOlT77V5mljvnqswVYwKEWNxGpVfE L0cA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LKy+LO5A; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2ff693534f8sm3391917a91.17.2025.03.07.10.56.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 10:56:54 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org Subject: [PATCH 10/16] accel/tcg: Build tcg-accel-ops.c once Date: Fri, 7 Mar 2025 10:56:39 -0800 Message-ID: <20250307185645.970034-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307185645.970034-1-richard.henderson@linaro.org> References: <20250307185645.970034-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Now that tcg-accel-ops.c uses cputlb.h instead of exec-all.h, it can be built once. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- accel/tcg/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index 979ce90eb0..70ada21f42 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -20,7 +20,6 @@ specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_specific_ss) specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files( 'cputlb.c', - 'tcg-accel-ops.c', 'tcg-accel-ops-mttcg.c', 'tcg-accel-ops-icount.c', 'tcg-accel-ops-rr.c', @@ -29,5 +28,6 @@ specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files( system_ss.add(when: ['CONFIG_TCG'], if_true: files( 'icount-common.c', 'monitor.c', + 'tcg-accel-ops.c', 'watchpoint.c', )) From patchwork Fri Mar 7 18:56:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 871236 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp915773wri; Fri, 7 Mar 2025 10:58:28 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVURdbWgaO1WkwoBMxRZLyB25AW/jCTtLqlUvEKridJhgTxQjauIDBWOMbilLGlVErDPGAnIw==@linaro.org X-Google-Smtp-Source: AGHT+IFbjtvxlz8pG4mYN6vaFKIgTm2KUTjpaARkCMyuw3L3TKbWQvN0GrfCysTF/HX6K/+K0yK3 X-Received: by 2002:ad4:4eed:0:b0:6e8:9bcd:bba6 with SMTP id 6a1803df08f44-6e9005d49bemr71649886d6.7.1741373908271; Fri, 07 Mar 2025 10:58:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741373908; cv=none; d=google.com; s=arc-20240605; b=ITQJuP+NAJkhIuVFFX25uq32WKOzPDh5WCyY3Fhm/wrdazFOidY33lofuEXUu3zuiw k4hxbeqKknY6cAKPazDqJqeZfDpDg+NgkL9bGp6nOvyJOal/Bo79HfBUd9BXxsWnrI/i sZm1YXFIn4l3mY4Ok4wfsMz17LPS+qEz6+RV8N+oVD8TZ8Rdox26fhGNvLU2xKifrxGj eEWrEmipr0H2fjtvXu/jzRlhu+4tIY9gvIe847U+vNmqcl9jIuXCYiZsyJu+PryUnW53 3lhPFTAB7Qvlw0zda0Co+slDcGkymT+TTe2K+iyD4D0rla+G+BWRQOa3shrK9SDIDBng aXsg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=yvub9wKD2OmaGYjgLz+dO6qQURDfWdRF4qq4HxWTWTw=; fh=ycigHkwOPieh2u5PmcA89sNk/qPD1ZkdDlL8Mchfvw8=; b=JiRoQ8SO9MAUijAvs8TqCTMnxTD4oze4SJ0r0MnqSXBBFrbRMgeFygDbAOD8a6e5dP wK7lqd6Hp8JvgKhSxHqcELvBXVxdYe/TZqy5fl2cgty19aMI25sk/oHXFcYBDZWdlhit e0waVJoKSKr92k/NMmQDmM+HHaZsJ8VdydWDIjnz0cUhzLnBTE+yjCxBUZpuBaSOgHen S0hFRLmdRIPO2hR41wOnaNtbLRm+Ut3NqQiUp13bBMXZoYLAYfMAm/kahN1dcfgdJ3mj xF37bUHXhJsE3ZINeYMZYPwUd+slO2eN7mhjBXgeSIZWKh8yb4bGtpBPer6c6KcCDBeZ RY5w==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="jv/2R72y"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2ff693534f8sm3391917a91.17.2025.03.07.10.56.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 10:56:55 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org Subject: [PATCH 11/16] accel/tcg: Build tcg-accel-ops-icount.c once Date: Fri, 7 Mar 2025 10:56:40 -0800 Message-ID: <20250307185645.970034-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307185645.970034-1-richard.henderson@linaro.org> References: <20250307185645.970034-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org All that is required is to avoid including exec-all.h. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- accel/tcg/tcg-accel-ops-icount.c | 2 +- accel/tcg/meson.build | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/accel/tcg/tcg-accel-ops-icount.c b/accel/tcg/tcg-accel-ops-icount.c index d6b472a0b0..27cf1044c7 100644 --- a/accel/tcg/tcg-accel-ops-icount.c +++ b/accel/tcg/tcg-accel-ops-icount.c @@ -28,7 +28,7 @@ #include "system/cpu-timers.h" #include "qemu/main-loop.h" #include "qemu/guest-random.h" -#include "exec/exec-all.h" +#include "hw/core/cpu.h" #include "tcg-accel-ops.h" #include "tcg-accel-ops-icount.h" diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index 70ada21f42..891b724eb6 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -21,7 +21,6 @@ specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_specific_ss) specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files( 'cputlb.c', 'tcg-accel-ops-mttcg.c', - 'tcg-accel-ops-icount.c', 'tcg-accel-ops-rr.c', )) @@ -29,5 +28,6 @@ system_ss.add(when: ['CONFIG_TCG'], if_true: files( 'icount-common.c', 'monitor.c', 'tcg-accel-ops.c', + 'tcg-accel-ops-icount.c', 'watchpoint.c', )) From patchwork Fri Mar 7 18:56:41 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 871242 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp916001wri; Fri, 7 Mar 2025 10:59:09 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCU6aR0PVVrHGOu4rjSY4EOy4LtrzUiESwJbAbazQ/aqIF8Q7QgPncpJFhIOPeCZxOD4MdbnOQ==@linaro.org X-Google-Smtp-Source: AGHT+IGPVtM0Svkeva0oGhp1Epu6lGMnKaLkLKp7U5WNRCfNPXbin2NGcuKh4qeTtBzZ85rEQtFi X-Received: by 2002:a05:620a:8001:b0:7c3:bc90:a472 with SMTP id af79cd13be357-7c4e1668962mr723427085a.9.1741373949063; Fri, 07 Mar 2025 10:59:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741373949; cv=none; d=google.com; s=arc-20240605; b=QEQZ+37KcnU17vywpTT6c8rUWOcpR5B3w4VnqQJIiLQOc13/D6BnZqnWt5Wnve+l4R Ox/4gCJXPiNkKQMl6KISLNwhBo8YyWPvc6rz3v311vgFkXMFlnQXsQ21ynHiusnB/jaV fxXaxJ2rr9+lIksry5tdslXRaL92yGKeoTqOu7cQBK+/Y0GHRBWjYyiPnrMjILTHmqtd ndrJM5BzXpyUFe1jTNrkwls6SGY6wmKs6P5JCv0AcGAylCqBk1Iyc+WW9aQZrADZ9S6u eFrrX/7hUoqOQAvS4N9c+QALXbXv/d16YiStlqPRiIRUeQcoBdO2ZZMrZJHF57ZgFoF6 zvdA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=8xGAU/49OeEOOEzt+6b6VcCQ4H44QO9LUOBmF2tDbf4=; fh=ycigHkwOPieh2u5PmcA89sNk/qPD1ZkdDlL8Mchfvw8=; b=AinG7tiWXHhXPayRbPthVCZfioMcKLU+oDV+Q4QkUWG1t+QkADriZhcrTSOFIg14BE euI/6kryfrhaaCT0eZzUigKBl67Xq0J9FaM6TWIt3Y7DDT2D/QvaIqhkzaoxSmGhsfzN QldGmQaqvJIPW2UsczFjcC/hZgRdehIEbwHqQ0BiG0TjbE5xI2/tYmxxW68H83Z37em0 TotUnuGd1CeDL3bWUsaIJjA0aetjRQKtHp8URtV4ijJ3/hrpoj9KzTVdlCgIK8Vi+QHs E5nc1h7qu1aaqALayaNNtpaGV6yFgWflXQjXNMLS5b9zW56nI+Bu3p3SkzL16gxqLOzn eJcw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Pvry11wz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2ff693534f8sm3391917a91.17.2025.03.07.10.56.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 10:56:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org Subject: [PATCH 12/16] accel/tcg: Build tcg-accel-ops-rr.c once Date: Fri, 7 Mar 2025 10:56:41 -0800 Message-ID: <20250307185645.970034-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307185645.970034-1-richard.henderson@linaro.org> References: <20250307185645.970034-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org All that is required is to use cpu-common.h instead of exec-all.h. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- accel/tcg/tcg-accel-ops-rr.c | 2 +- accel/tcg/meson.build | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/accel/tcg/tcg-accel-ops-rr.c b/accel/tcg/tcg-accel-ops-rr.c index 028b385af9..f62cf24e1d 100644 --- a/accel/tcg/tcg-accel-ops-rr.c +++ b/accel/tcg/tcg-accel-ops-rr.c @@ -31,7 +31,7 @@ #include "qemu/main-loop.h" #include "qemu/notify.h" #include "qemu/guest-random.h" -#include "exec/exec-all.h" +#include "exec/cpu-common.h" #include "tcg/startup.h" #include "tcg-accel-ops.h" #include "tcg-accel-ops-rr.h" diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index 891b724eb6..87c1394b62 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -21,7 +21,6 @@ specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_specific_ss) specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files( 'cputlb.c', 'tcg-accel-ops-mttcg.c', - 'tcg-accel-ops-rr.c', )) system_ss.add(when: ['CONFIG_TCG'], if_true: files( @@ -29,5 +28,6 @@ system_ss.add(when: ['CONFIG_TCG'], if_true: files( 'monitor.c', 'tcg-accel-ops.c', 'tcg-accel-ops-icount.c', + 'tcg-accel-ops-rr.c', 'watchpoint.c', )) From patchwork Fri Mar 7 18:56:42 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 871237 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp915804wri; Fri, 7 Mar 2025 10:58:33 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVxbMeSSlrhzFGU0cNSmdnTKUzeZAp1NEoKXd7WQQ//KNT+frMa1i4kRAYZTqUr3DYh4XHnPA==@linaro.org X-Google-Smtp-Source: AGHT+IGEyMzAcZPBJU8/EaF32m1pNw683uwQ3XX2H/DHw+je60Rp53uFn4esN/SCKeqyhvX88Aq5 X-Received: by 2002:a05:622a:1993:b0:472:12f1:ba4a with SMTP id d75a77b69052e-4761095065emr63346841cf.4.1741373913004; Fri, 07 Mar 2025 10:58:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741373912; cv=none; d=google.com; s=arc-20240605; b=A6wnpewfceaB0TnoR/smrhDSD+3pw5S6qLozhov+ywJu8lcoLWEakv5SWxDRb6z4G+ io5bPcnXrgkod5wOU5jcRnkT8hL2dYJlkaTeL8Einx/4xFI+bK0k8g1hSIHN49iDooPL d6DM9vI86dSxfkj4NlhfuP9qE+fKzzRlXuLSyUmjgPfr6TK+4yxnppVgXxAEicda3BPj HwSH0giyQo0MtPX5F25hQtpoq/0SjgDEvP+70D3EjLIN5DJymkVioa1q+SrzAztpmQiO VSv65nHS+VH2Rmi/c7sjDj+pxnmT4EAJSmfQTfgasphxFFXphDNSaWGa448ux6vWs9pX R30Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=+0vlhP+/ciA3q59qQifyZ8D/3OKhNe8zch9jvXIoi5A=; fh=ycigHkwOPieh2u5PmcA89sNk/qPD1ZkdDlL8Mchfvw8=; b=BXqAA6uz5ydKchZqd4WquT4wMeK6f0X2VS8HVtE4r2N5b0ZughaCxZNmococBZBTwa GCIBNoNvxoeYQUsPfJmp3zUZ69kXHMjrX4LKvE9kvGlMdEuDmlyiv8HL/KGggCh7+t9n W7C1bf3ZzKi9fZwTA9mNXCrb5Xe4LEUuLEoJbt4xWgii5BDg3xii6mDMdnWuC1RtUyn5 exS7eIUyitMFv040JBtphTXFlG6xeX7wiEdpgSvlJLP2Iv0zF9pFwUlR9zspY8/PpBjc bQQcf48NLihs9cVRlzcwEQUmgCVkTKlfXBu2R0hvb7YD/zRz6kAxidP7bYTkoNr8YtAH 8IiA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="w7D/qhWZ"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2ff693534f8sm3391917a91.17.2025.03.07.10.56.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 10:56:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org Subject: [PATCH 13/16] accel/tcg: Build tcg-accel-ops-mttcg.c once Date: Fri, 7 Mar 2025 10:56:42 -0800 Message-ID: <20250307185645.970034-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307185645.970034-1-richard.henderson@linaro.org> References: <20250307185645.970034-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org All that is required is to avoid including exec-all.h. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- accel/tcg/tcg-accel-ops-mttcg.c | 1 - accel/tcg/meson.build | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/accel/tcg/tcg-accel-ops-mttcg.c b/accel/tcg/tcg-accel-ops-mttcg.c index ba7cf6819d..bdcc385ae9 100644 --- a/accel/tcg/tcg-accel-ops-mttcg.c +++ b/accel/tcg/tcg-accel-ops-mttcg.c @@ -30,7 +30,6 @@ #include "qemu/main-loop.h" #include "qemu/notify.h" #include "qemu/guest-random.h" -#include "exec/exec-all.h" #include "hw/boards.h" #include "tcg/startup.h" #include "tcg-accel-ops.h" diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index 87c1394b62..81fb25da5c 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -20,7 +20,6 @@ specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_specific_ss) specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files( 'cputlb.c', - 'tcg-accel-ops-mttcg.c', )) system_ss.add(when: ['CONFIG_TCG'], if_true: files( @@ -28,6 +27,7 @@ system_ss.add(when: ['CONFIG_TCG'], if_true: files( 'monitor.c', 'tcg-accel-ops.c', 'tcg-accel-ops-icount.c', + 'tcg-accel-ops-mttcg.c', 'tcg-accel-ops-rr.c', 'watchpoint.c', )) From patchwork Fri Mar 7 18:56:43 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 871233 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp915537wri; Fri, 7 Mar 2025 10:57:42 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWHMj/xwlr1JJ8gsKGPSooKJWxLUhA5xZ54k841qao+MOZI5HVTHQ5uIimd1ND3mx6qYeNd+A==@linaro.org X-Google-Smtp-Source: AGHT+IGERcLY1bE0Wezct7rU/UYn/Ueqkve4VQYLqSom+CeySG3nh59UwE3/HeWtVYotueo4Ozs6 X-Received: by 2002:ac8:7fcd:0:b0:474:fb51:b58f with SMTP id d75a77b69052e-476109b34c4mr64587191cf.30.1741373862136; Fri, 07 Mar 2025 10:57:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741373862; cv=none; d=google.com; s=arc-20240605; b=GEvJhy0Jfqs2vTRq0Nfro86ztyjIHmsD3Ry1Qy0ygGOCgqfL7nGGIba0Il7BSxWbY2 UbscL4XLIK5mdrE93jOcxT40B6DEmHJ3/9TJti1QLJShp2dHZnK+U1hhV6A/4vpHHMw+ pikD+W44lcQQyLz5YYswU4Eo6++ZjtV+V8Zu8FkJi9xc3ATlTNiW7A388y5XOe4pt6+1 0ojtaHhj58FZBBDf2yWAZhHRPfd49cy69qBsxu54HWug1K/jVBE4W3xqnbTr/ZOmf4S9 dh8S0gW5nFWFUkl3MXXSfgBNEczZRjFWscrWJxXbZyLBsG7y6Nc7W1ECkD7HyBQYXSzj jEiw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=RytMCD0LlZ8TULuAO+TyiQ/M0TGfjDPA2CE/B7x8fYg=; fh=ycigHkwOPieh2u5PmcA89sNk/qPD1ZkdDlL8Mchfvw8=; b=Ws2G0yc96eOIjn2DXxGrdPAqOB8OoYaBhnaNV3BbvGGNWqlr6D/Q9npSzuDq134pzz wCam/P43nCrZA7PrnG4xdujx+Sw31+z+UF7JjdABZ/fAnJ/7IVVcgqE7odAqYIP3IP9P uuV+PpP96M5yQqF5umpAncFzw48f0eFNCzR8Xnp7iXTd/fnuWh10j5Yeh5cEGiCoMC/y TrOMGSIJdol5nePm6EYelsFqsBvMHsBJzyUeTs4BCV+nJuDcgVjhT6aC6D6cjq0Wy5sS S/HXL7+ydVteVo+M18KUOq0u7bdgknACsESS+OZRtpgcDP+lkcp5YBQRpDz6LDzwMYmz z4ug==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eRjIM7YL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2ff693534f8sm3391917a91.17.2025.03.07.10.56.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 10:56:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org Subject: [PATCH 14/16] include/exec: Split out helper-getpc.h Date: Fri, 7 Mar 2025 10:56:43 -0800 Message-ID: <20250307185645.970034-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307185645.970034-1-richard.henderson@linaro.org> References: <20250307185645.970034-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Split out GETPC and GETPC_ADJ to a target-independent header. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé --- include/exec/exec-all.h | 19 +------------------ include/exec/helper-getpc.h | 31 +++++++++++++++++++++++++++++++ 2 files changed, 32 insertions(+), 18 deletions(-) create mode 100644 include/exec/helper-getpc.h diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index a758b7a843..22a99ca502 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -26,6 +26,7 @@ #endif #include "exec/mmu-access-type.h" #include "exec/translation-block.h" +#include "exec/helper-getpc.h" #if defined(CONFIG_TCG) @@ -177,24 +178,6 @@ void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr); void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t last); void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr); -/* GETPC is the true target of the return instruction that we'll execute. */ -#if defined(CONFIG_TCG_INTERPRETER) -extern __thread uintptr_t tci_tb_ptr; -# define GETPC() tci_tb_ptr -#else -# define GETPC() \ - ((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0))) -#endif - -/* The true return address will often point to a host insn that is part of - the next translated guest insn. Adjust the address backward to point to - the middle of the call insn. Subtracting one would do the job except for - several compressed mode architectures (arm, mips) which set the low bit - to indicate the compressed mode; subtracting two works around that. It - is also the case that there are no host isas that contain a call insn - smaller than 4 bytes, so we don't worry about special-casing this. */ -#define GETPC_ADJ 2 - #if !defined(CONFIG_USER_ONLY) /** diff --git a/include/exec/helper-getpc.h b/include/exec/helper-getpc.h new file mode 100644 index 0000000000..1c8bd72c11 --- /dev/null +++ b/include/exec/helper-getpc.h @@ -0,0 +1,31 @@ +/* + * Get host pc for helper unwinding. + * + * Copyright (c) 2003 Fabrice Bellard + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#ifndef HELPER_GETPC_H +#define HELPER_GETPC_H + +/* GETPC is the true target of the return instruction that we'll execute. */ +#if defined(CONFIG_TCG_INTERPRETER) +extern __thread uintptr_t tci_tb_ptr; +# define GETPC() tci_tb_ptr +#else +# define GETPC() \ + ((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0))) +#endif + +/* + * The true return address will often point to a host insn that is part of + * the next translated guest insn. Adjust the address backward to point to + * the middle of the call insn. Subtracting one would do the job except for + * several compressed mode architectures (arm, mips) which set the low bit + * to indicate the compressed mode; subtracting two works around that. It + * is also the case that there are no host isas that contain a call insn + * smaller than 4 bytes, so we don't worry about special-casing this. + */ +#define GETPC_ADJ 2 + +#endif /* HELPER_GETPC_H */ From patchwork Fri Mar 7 18:56:44 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 871241 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp915860wri; Fri, 7 Mar 2025 10:58:40 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVTF9VZC0gt8B+jLuswF0oyGDQJODQiQfMR0uCP87Fiexj91gMeI+MWxwujU97aar8cA7acNg==@linaro.org X-Google-Smtp-Source: AGHT+IEIbez92pM/aO1N4zAeNM8zKLZ0ilb4ZDrn6bXFg7HVMocPibLjYSOu+YdWPGNLw0amCbBN X-Received: by 2002:a05:6214:daa:b0:6e6:6686:afcf with SMTP id 6a1803df08f44-6e9005b668fmr57154296d6.4.1741373919983; Fri, 07 Mar 2025 10:58:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741373919; cv=none; d=google.com; s=arc-20240605; b=IAwi3LJ94G+/2zTTAExAXxKnOvvCxUyXdmL8VeXFpC1caqau4dUlIadIipqIGXKhmY UHNddkc2akXBSHF0C+rM6D6U0PDG492QM2YbWAN77OfjZ+bHkD/MU/Qpn1FKvfhh4uwv VJfJhb+GlGoouCPFvP/4Gw+Lq4lC+tWmaKJRQleU2DE8OCd4hhRWHWoPWrpvLCxRD1mU GznQlhxxVMC/PAMwY2dogNyCgE8MRUrcimW1YOpYJqciOJuCCPQqYgeTVSiCRgbPZ9f/ H1jeG+OLJrQUQVF6x7Wwbv5ppSORQWtY84SX2Vje91ye2SshnuBv0ybMHETPK+m0Vzue Gwug== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=b/kc5PC1uGwC95AZ8XXvOvpXwja1rKXIUn6SjN0F6p4=; fh=ycigHkwOPieh2u5PmcA89sNk/qPD1ZkdDlL8Mchfvw8=; b=RJYhmypUIeuBS+YgxctXWGMbro0wupudNFXswptYq0oV8ofeZHqB7k0PlmyPJBKZvD RxKI7w9paFGGQGB6lhTLWH5W5u3kz4D/hleq1R2vj9UNHjesIX0kqE3oLTRAqNdlYK/R +d7zy/7VdhSJa3nzerThr7L3l8DDG0dCs4SZDdYizZdw5nLPdM/QGCEQLjAVToZv1udf sOs3ezvLyBf4w58p/OT2Wwtbjs/YdC/tB4Nw6AZasJcp30+kD2XWOTLt7FJ4zH58W3QL TZzIcfq5AtzHB9h1PrHFlPsnMYB+geHNNTIge9y2S/vveV6tsVdTBDq745ytXIo6wlYw RacA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HdBxbeRA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2ff693534f8sm3391917a91.17.2025.03.07.10.56.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 10:56:58 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org Subject: [PATCH 15/16] accel/tcg: Build tcg-runtime.c once Date: Fri, 7 Mar 2025 10:56:44 -0800 Message-ID: <20250307185645.970034-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307185645.970034-1-richard.henderson@linaro.org> References: <20250307185645.970034-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- accel/tcg/tcg-runtime.c | 8 ++------ accel/tcg/meson.build | 2 +- 2 files changed, 3 insertions(+), 7 deletions(-) diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c index 9fa539ad3d..72c4c6bd31 100644 --- a/accel/tcg/tcg-runtime.c +++ b/accel/tcg/tcg-runtime.c @@ -23,13 +23,9 @@ */ #include "qemu/osdep.h" #include "qemu/host-utils.h" -#include "cpu.h" +#include "exec/cpu-common.h" #include "exec/helper-proto-common.h" -#include "exec/cpu_ldst.h" -#include "exec/exec-all.h" -#include "disas/disas.h" -#include "exec/log.h" -#include "tcg/tcg.h" +#include "exec/helper-getpc.h" #define HELPER_H "accel/tcg/tcg-runtime.h" #include "exec/helper-info.c.inc" diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index 81fb25da5c..411fe28dea 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -1,5 +1,6 @@ common_ss.add(when: 'CONFIG_TCG', if_true: files( 'cpu-exec-common.c', + 'tcg-runtime.c', )) tcg_specific_ss = ss.source_set() tcg_specific_ss.add(files( @@ -7,7 +8,6 @@ tcg_specific_ss.add(files( 'cpu-exec.c', 'tb-maint.c', 'tcg-runtime-gvec.c', - 'tcg-runtime.c', 'translate-all.c', 'translator.c', )) From patchwork Fri Mar 7 18:56:45 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 871240 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp915844wri; Fri, 7 Mar 2025 10:58:38 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUKlC+XUM2Tr27LgvHuiWCGvglaVK0BQ/nSFGotdKTxAnI2LAIr7u0L38zRPow+wK8rWihx6w==@linaro.org X-Google-Smtp-Source: AGHT+IHzcSOarhxoTiW5THQp2x0+9EIJWnNisj47UwBcllekf2nMCa5973AyOgTgzFjUNVRM4UJD X-Received: by 2002:a05:620a:2722:b0:7c3:ccf5:363e with SMTP id af79cd13be357-7c4e1684a84mr662418985a.13.1741373918424; Fri, 07 Mar 2025 10:58:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741373918; cv=none; d=google.com; s=arc-20240605; b=G5fIZcnCCJ6Dz2aghwuvNTh6lirQXWD9tgVQM/G9W8F3NwDcwSov7nUlvI/AProGQN EgM30aZHoOEhsDn3R5m8PGH7BrzoVa78+XzksZY4vnNFg4LUT9kRnpNvAWa/XUvIa8LA r0YPgYEewvUs9OzQwEhnlzc74uTl+8SV/4ZtcCLwfISzfa/1rB7UMya/cRT7DgHmr5F+ moqgF4ZaJ3yviimf4xQUXK4sCqhigJrv27ZqNeivXS8/OUdaScNBc8DK5OXUdqMRYOAr 0ImjUyvnJa+EQhE8OWyMdgbymXwiFIw1zrEgMMFj77vAUO9Xs/NgE0obBpMA7VAPTzBj FRPw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=U6baNnWHy0ZHd5ntn8fAFXTjSBc8gCrPqSjCFJWFWZE=; fh=ycigHkwOPieh2u5PmcA89sNk/qPD1ZkdDlL8Mchfvw8=; b=lY2cvwq4VVNFeSuELny7OZ6ZlZ5QpbTvMk4z2xtp7i3Sw8mjBwxkjzi5tXvV4XX0Rm BKghH9cbqWdG/zpuAm/rhkNNJU6KWd/SMGffceEYkpZobZ7LhsrYPIlAogvSTLTX5zE1 MWV9HXtrLRenzLQyDCQMtM2SL9SMj45DbREBqow9amcSqnf+g8aE5sPM2Mi3jgvruwkK eLRCT1kxuawgaREmOl6WoOxIBR3Tx6jSwSsaKTTrsD/mgvW5g8eTimQ09y9DUKpHrqIL FGFKCWtQRfDDXWvPat+3uFJWDJVelMVpAl7ZTZLqN3j5YcmNHJeHpEpvJtN8bj7+osr1 xwNA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=i0Dn61+w; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2ff693534f8sm3391917a91.17.2025.03.07.10.56.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 10:56:58 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org Subject: [PATCH 16/16] accel/tcg: Build tcg-runtime-gvec.c once Date: Fri, 7 Mar 2025 10:56:45 -0800 Message-ID: <20250307185645.970034-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307185645.970034-1-richard.henderson@linaro.org> References: <20250307185645.970034-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé --- accel/tcg/tcg-runtime-gvec.c | 1 - accel/tcg/meson.build | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c index afca89baa1..ff927c5dd8 100644 --- a/accel/tcg/tcg-runtime-gvec.c +++ b/accel/tcg/tcg-runtime-gvec.c @@ -19,7 +19,6 @@ #include "qemu/osdep.h" #include "qemu/host-utils.h" -#include "cpu.h" #include "exec/helper-proto-common.h" #include "tcg/tcg-gvec-desc.h" diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index 411fe28dea..38ff227eb0 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -1,13 +1,13 @@ common_ss.add(when: 'CONFIG_TCG', if_true: files( 'cpu-exec-common.c', 'tcg-runtime.c', + 'tcg-runtime-gvec.c', )) tcg_specific_ss = ss.source_set() tcg_specific_ss.add(files( 'tcg-all.c', 'cpu-exec.c', 'tb-maint.c', - 'tcg-runtime-gvec.c', 'translate-all.c', 'translator.c', ))