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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912c1037b4sm9653479f8f.92.2025.03.08.11.02.36 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 08 Mar 2025 11:02:36 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: BALATON Zoltan , qemu-devel@nongnu.org Cc: Bernhard Beschow , Peter Maydell , qemu-ppc@nongnu.org, Andrey Smirnov , Jean-Christophe Dubois , Bin Meng , qemu-arm@nongnu.org, qemu-block@nongnu.org, Guenter Roeck , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v3 01/12] hw/sd/sdhci: Remove need for SDHCIState::vendor field Date: Sat, 8 Mar 2025 20:02:19 +0100 Message-ID: <20250308190230.7508-2-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250308190230.7508-1-philmd@linaro.org> References: <20250308190230.7508-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org All instances of TYPE_IMX_USDHC set vendor=SDHCI_VENDOR_IMX. No need to special-case it. Signed-off-by: Philippe Mathieu-Daudé --- hw/sd/sdhci-internal.h | 1 - include/hw/sd/sdhci.h | 4 ---- hw/arm/fsl-imx25.c | 2 -- hw/arm/fsl-imx6.c | 2 -- hw/arm/fsl-imx6ul.c | 2 -- hw/arm/fsl-imx7.c | 2 -- hw/arm/fsl-imx8mp.c | 2 -- hw/sd/sdhci.c | 14 ++++---------- 8 files changed, 4 insertions(+), 25 deletions(-) diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h index 9f768c418e0..9072b06bdde 100644 --- a/hw/sd/sdhci-internal.h +++ b/hw/sd/sdhci-internal.h @@ -311,7 +311,6 @@ extern const VMStateDescription sdhci_vmstate; DEFINE_PROP_UINT8("endianness", _state, endianness, DEVICE_LITTLE_ENDIAN), \ DEFINE_PROP_UINT8("sd-spec-version", _state, sd_spec_version, 2), \ DEFINE_PROP_UINT8("uhs", _state, uhs_mode, UHS_NOT_SUPPORTED), \ - DEFINE_PROP_UINT8("vendor", _state, vendor, SDHCI_VENDOR_NONE), \ \ /* Capabilities registers provide information on supported * features of this specific host controller implementation */ \ diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h index 38c08e28598..48247e9a20f 100644 --- a/include/hw/sd/sdhci.h +++ b/include/hw/sd/sdhci.h @@ -99,7 +99,6 @@ struct SDHCIState { uint8_t endianness; uint8_t sd_spec_version; uint8_t uhs_mode; - uint8_t vendor; /* For vendor specific functionality */ /* * Write Protect pin default active low for detecting SD card * to be protected. Set wp_inverted to invert the signal. @@ -108,9 +107,6 @@ struct SDHCIState { }; typedef struct SDHCIState SDHCIState; -#define SDHCI_VENDOR_NONE 0 -#define SDHCI_VENDOR_IMX 1 - /* * Controller does not provide transfer-complete interrupt when not * busy. diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c index 5359a6d8d3b..02214ca1a1c 100644 --- a/hw/arm/fsl-imx25.c +++ b/hw/arm/fsl-imx25.c @@ -243,8 +243,6 @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp) &error_abort); object_property_set_uint(OBJECT(&s->esdhc[i]), "capareg", IMX25_ESDHC_CAPABILITIES, &error_abort); - object_property_set_uint(OBJECT(&s->esdhc[i]), "vendor", - SDHCI_VENDOR_IMX, &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->esdhc[i]), errp)) { return; } diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c index dc86338b3a5..a114dc0d63d 100644 --- a/hw/arm/fsl-imx6.c +++ b/hw/arm/fsl-imx6.c @@ -327,8 +327,6 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp) &error_abort); object_property_set_uint(OBJECT(&s->esdhc[i]), "capareg", IMX6_ESDHC_CAPABILITIES, &error_abort); - object_property_set_uint(OBJECT(&s->esdhc[i]), "vendor", - SDHCI_VENDOR_IMX, &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->esdhc[i]), errp)) { return; } diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c index 34c4aa15cd0..ce8d3ef535f 100644 --- a/hw/arm/fsl-imx6ul.c +++ b/hw/arm/fsl-imx6ul.c @@ -531,8 +531,6 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) FSL_IMX6UL_USDHC2_IRQ, }; - object_property_set_uint(OBJECT(&s->usdhc[i]), "vendor", - SDHCI_VENDOR_IMX, &error_abort); sysbus_realize(SYS_BUS_DEVICE(&s->usdhc[i]), &error_abort); sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0, diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c index 3374018cde0..ed1f10bca26 100644 --- a/hw/arm/fsl-imx7.c +++ b/hw/arm/fsl-imx7.c @@ -471,8 +471,6 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) FSL_IMX7_USDHC3_IRQ, }; - object_property_set_uint(OBJECT(&s->usdhc[i]), "vendor", - SDHCI_VENDOR_IMX, &error_abort); sysbus_realize(SYS_BUS_DEVICE(&s->usdhc[i]), &error_abort); sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0, diff --git a/hw/arm/fsl-imx8mp.c b/hw/arm/fsl-imx8mp.c index 1ea98e14635..c3f6da63220 100644 --- a/hw/arm/fsl-imx8mp.c +++ b/hw/arm/fsl-imx8mp.c @@ -524,8 +524,6 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error **errp) { fsl_imx8mp_memmap[FSL_IMX8MP_USDHC3].addr, FSL_IMX8MP_USDHC3_IRQ }, }; - object_property_set_uint(OBJECT(&s->usdhc[i]), "vendor", - SDHCI_VENDOR_IMX, &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->usdhc[i]), errp)) { return; } diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 1f45a77566c..149b748cbee 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -1731,16 +1731,10 @@ usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) case USDHC_VENDOR_SPEC: s->vendor_spec = value; - switch (s->vendor) { - case SDHCI_VENDOR_IMX: - if (value & USDHC_IMX_FRC_SDCLK_ON) { - s->prnsts &= ~SDHC_IMX_CLOCK_GATE_OFF; - } else { - s->prnsts |= SDHC_IMX_CLOCK_GATE_OFF; - } - break; - default: - break; + if (value & USDHC_IMX_FRC_SDCLK_ON) { + s->prnsts &= ~SDHC_IMX_CLOCK_GATE_OFF; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ce9f2d081sm27971865e9.21.2025.03.08.11.02.41 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 08 Mar 2025 11:02:41 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: BALATON Zoltan , qemu-devel@nongnu.org Cc: Bernhard Beschow , Peter Maydell , qemu-ppc@nongnu.org, Andrey Smirnov , Jean-Christophe Dubois , Bin Meng , qemu-arm@nongnu.org, qemu-block@nongnu.org, Guenter Roeck , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v3 02/12] hw/sd/sdhci: Introduce SDHCIClass stub Date: Sat, 8 Mar 2025 20:02:20 +0100 Message-ID: <20250308190230.7508-3-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250308190230.7508-1-philmd@linaro.org> References: <20250308190230.7508-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philmd@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org TYPE_SYSBUS_SDHCI is a bit odd because it uses an union to work with both SysBus / PCI parent. As this is not a normal use, introduce SDHCIClass in its own commit. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/sd/sdhci.h | 9 +++++++++ hw/sd/sdhci.c | 1 + 2 files changed, 10 insertions(+) diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h index 48247e9a20f..c4b20db3877 100644 --- a/include/hw/sd/sdhci.h +++ b/include/hw/sd/sdhci.h @@ -107,6 +107,13 @@ struct SDHCIState { }; typedef struct SDHCIState SDHCIState; +typedef struct SDHCIClass { + union { + PCIDeviceClass pci_parent_class; + SysBusDeviceClass sbd_parent_class; + }; +} SDHCIClass; + /* * Controller does not provide transfer-complete interrupt when not * busy. @@ -123,6 +130,8 @@ DECLARE_INSTANCE_CHECKER(SDHCIState, PCI_SDHCI, #define TYPE_SYSBUS_SDHCI "generic-sdhci" DECLARE_INSTANCE_CHECKER(SDHCIState, SYSBUS_SDHCI, TYPE_SYSBUS_SDHCI) +DECLARE_CLASS_CHECKERS(SDHCIClass, SYSBUS_SDHCI, + TYPE_SYSBUS_SDHCI) #define TYPE_IMX_USDHC "imx-usdhc" diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 149b748cbee..4917a9b3632 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -1960,6 +1960,7 @@ static const TypeInfo sdhci_types[] = { .instance_size = sizeof(SDHCIState), .instance_init = sdhci_sysbus_init, .instance_finalize = sdhci_sysbus_finalize, + .class_size = sizeof(SDHCIClass), .class_init = sdhci_sysbus_class_init, }, { From patchwork Sat Mar 8 19:02:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 871541 Delivered-To: patch@linaro.org Received: by 2002:a5d:64ce:0:b0:38f:210b:807b with SMTP id f14csp288145wri; Sat, 8 Mar 2025 11:04:36 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCX2h5Nm+oJtNR3rj/kms+W7Q34p5B9dk4/cLrQ75MZTcHfeNb46GsL3/8FAAv5yluYMtE1mfQ==@linaro.org X-Google-Smtp-Source: AGHT+IHSu2ejjE8wyra3TQ8z0/eeVl2Ol4MStg4NAosCLiQ8tWWQbzT330V2PuMRxkipltOMCoOc X-Received: by 2002:a05:620a:8708:b0:7c5:4a3a:bc12 with SMTP id af79cd13be357-7c54a3abfcbmr52174785a.32.1741460676672; Sat, 08 Mar 2025 11:04:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741460676; cv=none; d=google.com; s=arc-20240605; b=ATZs23tVs44QZ6rO/SMfxrYNx/hP9sF06obTJjYHOCX4vyOlnzXYFYmhgSZv2Maufs yB+rM6riRo1qz3g6zB6D5pwcefS6ut3Q9ImWspGCQiF6uEsvAuOnn9S3vT5vzjnGjDng ESaGksY+dwhtKcf736E1UUsvxZWdcTZ6BBFygPWX2ETnd5//iD+oEJ6ABXPTSubwsXT9 dPkkvC6VBk/ct8/iDSllCYKDNaVDDARXTBBv6hEqP3FztRCUbJ/uqKhMUa6ZCq6Mof0o m3oLP5H0AFB6nBLdK9Drze+cLwq1Kv81gG/ozRr9Yulf+lvjVpw9mroT3nnPb/J2/GT5 zNRQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=B/DAOjgGSbt8R5XFJfa90IfAIHW3vg/xwsnsSI4jCJ0=; fh=p5YyE5a19mk6wUBSlKlN3rVwpom6bC98YTWjv5ecz3E=; b=ALLqQ8Og3Af42DBDaTSPtyjwrxNkcypcQaKkXOmDhzSuVrM1ugxhfkXkULrVc0mFKQ UZVBhkEHu+Yvy8A1EYK38kiBZ3MpHS8LyvXrfpQVaQjjS14fPtHvhYxZ/5VcScsj01Sw ZckGVVmMtjPNQmGN971EUVBvqzduLq+iUYMcO2wmSK1iUrmeqYXxsXnK2Sq1A6dgnxXR aE1tEetVYNqdiseqmL6tONSvMps1ye/Nt9rco2qkqfBBsF2IwD1TSEu2sJhOxOzHEMNu rzBfADTDBke7+LoHYXgrQYrmfBBS1mQd5YAQq5cb62ULRnfIJjA6Eo7G+r0QgcWUWtsE wVQw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Te9HZ4CF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912c019557sm9889830f8f.50.2025.03.08.11.02.46 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 08 Mar 2025 11:02:46 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: BALATON Zoltan , qemu-devel@nongnu.org Cc: Bernhard Beschow , Peter Maydell , qemu-ppc@nongnu.org, Andrey Smirnov , Jean-Christophe Dubois , Bin Meng , qemu-arm@nongnu.org, qemu-block@nongnu.org, Guenter Roeck , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v3 03/12] hw/sd/sdhci: Make quirks a class property Date: Sat, 8 Mar 2025 20:02:21 +0100 Message-ID: <20250308190230.7508-4-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250308190230.7508-1-philmd@linaro.org> References: <20250308190230.7508-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org All TYPE_IMX_USDHC instances use the quirk: move it to the class layer. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/sd/sdhci.h | 3 ++- hw/sd/sdhci.c | 15 +++++++++++++-- 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h index c4b20db3877..0616ce3aa59 100644 --- a/include/hw/sd/sdhci.h +++ b/include/hw/sd/sdhci.h @@ -95,7 +95,6 @@ struct SDHCIState { /* Configurable properties */ bool pending_insert_quirk; /* Quirk for Raspberry Pi card insert int */ - uint32_t quirks; uint8_t endianness; uint8_t sd_spec_version; uint8_t uhs_mode; @@ -112,6 +111,8 @@ typedef struct SDHCIClass { PCIDeviceClass pci_parent_class; SysBusDeviceClass sbd_parent_class; }; + + uint32_t quirks; } SDHCIClass; /* diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 4917a9b3632..2b7eb11a14a 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -345,6 +345,8 @@ static void sdhci_send_command(SDHCIState *s) rlen = sdbus_do_command(&s->sdbus, &request, response); if (s->cmdreg & SDHC_CMD_RESPONSE) { + SDHCIClass *sc = SYSBUS_SDHCI_GET_CLASS(s); + if (rlen == 4) { s->rspreg[0] = ldl_be_p(response); s->rspreg[1] = s->rspreg[2] = s->rspreg[3] = 0; @@ -366,7 +368,7 @@ static void sdhci_send_command(SDHCIState *s) } } - if (!(s->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) && + if (!(sc->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) && (s->norintstsen & SDHC_NISEN_TRSCMP) && (s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY) { s->norintsts |= SDHC_NIS_TRSCMP; @@ -1886,7 +1888,15 @@ static void imx_usdhc_init(Object *obj) SDHCIState *s = SYSBUS_SDHCI(obj); s->io_ops = &usdhc_mmio_ops; - s->quirks = SDHCI_QUIRK_NO_BUSY_IRQ; +} + +static void imx_usdhc_class_init(ObjectClass *oc, void *data) +{ + SDHCIClass *sc = SYSBUS_SDHCI_CLASS(oc); + + sc->quirks = SDHCI_QUIRK_NO_BUSY_IRQ; + + sdhci_common_class_init(oc, data); } /* --- qdev Samsung s3c --- */ @@ -1967,6 +1977,7 @@ static const TypeInfo sdhci_types[] = { .name = TYPE_IMX_USDHC, .parent = TYPE_SYSBUS_SDHCI, .instance_init = imx_usdhc_init, + .class_init = imx_usdhc_class_init, }, { .name = TYPE_S3C_SDHCI, From patchwork Sat Mar 8 19:02:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 871538 Delivered-To: patch@linaro.org Received: by 2002:a5d:64ce:0:b0:38f:210b:807b with SMTP id f14csp287822wri; Sat, 8 Mar 2025 11:03:53 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVqC6oT1sPJq8CJmHfohluXoESz2RkQ7YQXB1/pv4PigFUzlm7F0nfCahygl+PdiFxBG2pXVA==@linaro.org X-Google-Smtp-Source: AGHT+IH12CaSNhkh50odaBwAoyiRsf+XBQ1KWz80Qr/3TP5pIkZsEHr0URhl1L86zFnLYN7drWJs X-Received: by 2002:ad4:5c6c:0:b0:6e6:656f:3c34 with SMTP id 6a1803df08f44-6e90061fd83mr77970926d6.12.1741460633130; Sat, 08 Mar 2025 11:03:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741460633; cv=none; d=google.com; s=arc-20240605; b=ZWKq6pU+KfpjEacJ6L+pa6hIo53s03nWXWvCJ63oFRMrfPLhWPkXuXTJSpT2mAqHZQ z9aIVcpnYw+YkO58PlX6YcfmcjtT374s3togoeF5rJSTaLgjbGrI7IsDnDb1kR82G+Ia jVk8mVp6X46ry/PeVj2eZFt6UUFCqBW5sVVjhrIG3fhOpItqGvU04w47s3GLmaVq+k0w fN2msDtZwN9plT9i4DRbCn1RRqXsBmUrGDS5q5GlsuvAdyTePA9lRiobB2z72QZU3Hxq uW6HdPR9gJYFciSWp1Jm4CqiJo4TOlxS+ef5+XAfw33m6/VFvDKfm9ckMbuWTlFJPPuD OCTw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=rwn/2OdTxyJUqPr5de1XSt+8TC9K6iNWTaYptctiUL8=; fh=aBJIV5iYpP6DX4rTm+06v5Y/SbvvxejhBQiX54kb5S0=; b=Ihw6zlOCudpGBFA6nsRT1huYLu+bMBnEMz2oBj1RbI8JJu6n5c/s4BY75sgiJUeJdn r2iq89Jv7Z2kXf/6bdM64bwKXVhaARDsxst20Au0pFnwPxOXQ27TnZO3npricSYRVifm L1dWWzE5fU9vUQbxReNYrltHma/IUOHGRu52MQce9XSVgPrwCZalLJkINRMNBkH54wZD EyQeI5zTM8P6r1/JbrRIkcLZNFdmIKU87OpAlxD/5v8ekdsd8kTCevRXX7eeRTEudMLF qIbKMb+tG63tU1CuFZHNk4fppjczdKNyZhRimWKRDQughJLKEZJ1I7zCazsZfmq5FVDH E8kg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uFpRKjcP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bd41c7cc7sm128352975e9.0.2025.03.08.11.02.50 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 08 Mar 2025 11:02:51 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: BALATON Zoltan , qemu-devel@nongnu.org Cc: Bernhard Beschow , Peter Maydell , qemu-ppc@nongnu.org, Andrey Smirnov , Jean-Christophe Dubois , Bin Meng , qemu-arm@nongnu.org, qemu-block@nongnu.org, Guenter Roeck , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v3 04/12] hw/sd/sdhci: Make I/O region size a class property Date: Sat, 8 Mar 2025 20:02:22 +0100 Message-ID: <20250308190230.7508-5-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250308190230.7508-1-philmd@linaro.org> References: <20250308190230.7508-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Be ready to have SDHC implementations to cover a wider I/O address range. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/sd/sdhci.h | 1 + hw/sd/sdhci.c | 9 +++++++-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h index 0616ce3aa59..2709a7a69d5 100644 --- a/include/hw/sd/sdhci.h +++ b/include/hw/sd/sdhci.h @@ -113,6 +113,7 @@ typedef struct SDHCIClass { }; uint32_t quirks; + uint64_t iomem_size; } SDHCIClass; /* diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 2b7eb11a14a..59d506cafa3 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -1443,6 +1443,7 @@ void sdhci_uninitfn(SDHCIState *s) void sdhci_common_realize(SDHCIState *s, Error **errp) { ERRP_GUARD(); + SDHCIClass *sc = SYSBUS_SDHCI_GET_CLASS(s); switch (s->endianness) { case DEVICE_LITTLE_ENDIAN: @@ -1468,8 +1469,9 @@ void sdhci_common_realize(SDHCIState *s, Error **errp) s->buf_maxsz = sdhci_get_fifolen(s); s->fifo_buffer = g_malloc0(s->buf_maxsz); - memory_region_init_io(&s->iomem, OBJECT(s), s->io_ops, s, "sdhci", - SDHC_REGISTERS_MAP_SIZE); + assert(sc->iomem_size >= SDHC_REGISTERS_MAP_SIZE); + memory_region_init_io(&s->iomem, OBJECT(s), s->io_ops, s, + object_get_typename(OBJECT(s)), sc->iomem_size); } void sdhci_common_unrealize(SDHCIState *s) @@ -1621,11 +1623,14 @@ static void sdhci_sysbus_unrealize(DeviceState *dev) static void sdhci_sysbus_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); + SDHCIClass *sc = SYSBUS_SDHCI_CLASS(klass); device_class_set_props(dc, sdhci_sysbus_properties); dc->realize = sdhci_sysbus_realize; dc->unrealize = sdhci_sysbus_unrealize; + sc->iomem_size = SDHC_REGISTERS_MAP_SIZE; + sdhci_common_class_init(klass, data); } From patchwork Sat Mar 8 19:02:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 871544 Delivered-To: patch@linaro.org Received: by 2002:a5d:64ce:0:b0:38f:210b:807b with SMTP id f14csp288581wri; Sat, 8 Mar 2025 11:05:55 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXSa5ujLHgLnhZrVhJgmZPhC8ZTRWe82KRGihOY8mQsyNbajwPHPtaR48G9XILKSvvmHGxeTg==@linaro.org X-Google-Smtp-Source: AGHT+IHFKAR8//RY+/xVBjy83+zzFPrsm0eOV9T6hNk8m/2yiq56FXoYmwKIeyNvvB0wjzIASQlx X-Received: by 2002:a05:6214:21af:b0:6e8:fee2:aae7 with SMTP id 6a1803df08f44-6e90069839amr75523336d6.39.1741460755476; Sat, 08 Mar 2025 11:05:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741460755; cv=none; d=google.com; s=arc-20240605; b=XF62wwRNHfxqsLhatj3bxDy+KP9dzvOQnfrUA69JqLjBvXJLRIeeE5e4Sd/XPVKMHd JT3c2V5IL58bXtKQlye27anx/WFpL7YoaWco6D04nRRPNsNeWEAlQvsaxdczZkYuF1RR 5zka+lyk9RCRhh8uKvXhC2/wHmw+wQVDpuanPNCKoGXP+43bHDfsy5MxGcXe2s+IwuEK 4lyufP2Z7F61B5fcSNEBn3RdxklL7Y4jqmHToUZuf84bMUySFbvN79/AhsLTSdMQshPl rkrpVRVw8tcbiFMB3cZjFC+NlJiP5a9BYB2TE1cBnieRP2BRJcgTyD18DYkTw4bCzx45 ZA+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=akRNzOoRRyY/xSKhmyVeI+5UU9kBXMKW6nWI01FbvUE=; fh=a4SM3OxvDN+gnpAfcKP2s8WzvmDBldOQFSzrHUHe6E8=; b=XFL06Q5FaXD0to/qBCWa2G40DqsL8M9X6nULpt42GFeJLaCKCH+5wK9XT7yvYfKkP1 l6/m1yosnIYGzAzMlD5HUVg56DySjoEsgc4pk3Sdhus4Wkkn6wP3sKtm7pdCN489NfFR l6vIHUZK8Q2kJX7IYu1P3wVgw+lSNCSQbdTo5nytj7Xmvl/r1DXL/PLsYj1u0berH20p j2WCLgRKZhJHqAfpxtMC+DW9a/w3heTTdE/UkaCDxb39QllPGNvHQtMQZY/euPuDKyhv soEv6qPw4mhbMdFRbrcqbNQz+U9UVLJnJJ5SZQigVERaRvYwoO6E8XWIGrhrnI1gfeh3 AUTQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NVv+e3ws; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912c103aa5sm9698256f8f.94.2025.03.08.11.02.55 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 08 Mar 2025 11:02:56 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: BALATON Zoltan , qemu-devel@nongnu.org Cc: Bernhard Beschow , Peter Maydell , qemu-ppc@nongnu.org, Andrey Smirnov , Jean-Christophe Dubois , Bin Meng , qemu-arm@nongnu.org, qemu-block@nongnu.org, Guenter Roeck , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v3 05/12] hw/sd/sdhci: Enforce little endianness on PCI devices Date: Sat, 8 Mar 2025 20:02:23 +0100 Message-ID: <20250308190230.7508-6-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250308190230.7508-1-philmd@linaro.org> References: <20250308190230.7508-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philmd@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This is the default, but better be safe than sorry. Signed-off-by: Philippe Mathieu-Daudé --- hw/sd/sdhci-pci.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/sd/sdhci-pci.c b/hw/sd/sdhci-pci.c index 5268c0dee50..5f82178a76f 100644 --- a/hw/sd/sdhci-pci.c +++ b/hw/sd/sdhci-pci.c @@ -32,6 +32,7 @@ static void sdhci_pci_realize(PCIDevice *dev, Error **errp) SDHCIState *s = PCI_SDHCI(dev); sdhci_initfn(s); + qdev_prop_set_uint8(DEVICE(dev), "endianness", DEVICE_LITTLE_ENDIAN); sdhci_common_realize(s, errp); if (*errp) { return; From patchwork Sat Mar 8 19:02:24 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 871545 Delivered-To: patch@linaro.org Received: by 2002:a5d:64ce:0:b0:38f:210b:807b with SMTP id f14csp288585wri; Sat, 8 Mar 2025 11:05:56 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWaYB1EMIZgCwK5ghDwl673qb3CchBeXFtHvFGwtLgxiZISq/IS0opRSyWGC35LGIaKMSyy7g==@linaro.org X-Google-Smtp-Source: AGHT+IFZ6ATbHtbno1sNKspx9LQRj5xw3i8lzrAwI667+z/aBxBOhXpFDdMAN6JT4xgNuUC8hpWg X-Received: by 2002:a05:6214:da9:b0:6e6:5d61:4f01 with SMTP id 6a1803df08f44-6e900601587mr111423866d6.8.1741460756734; Sat, 08 Mar 2025 11:05:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741460756; cv=none; d=google.com; s=arc-20240605; b=cJUo9yYDwdns2mVpqaV2iKSsNhxZxr4NCh/UEqnzQ1UNU0lbLHy0XP5eVto2JlKDXi vgLXh/BxtCbfwxOeCy9gkLdoyttIl+AlH7QyM3cdP+apJdvZhPT0rASx3yoqje2F7kMk Jz6S2WeWdBAkUtuDKbseDvIOivgSMRFf5Mdmr9UEaATY1waGX6Ii61nwdcOMX/rzpSwf bCP0W1xIqPQJoG2ug5/bz8z3k8ai7gDBTZF+AR7t2y3yN5IY2cv1kL3muTyWhCaX6qig U0JkaUTJEedKyjmpub98k3Zza77KZAzidUZFDTRn6k0mPv5Kt5zn5UR27LfQSo1cc3Ua Kj4g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Tnj+mTi8s7/bMf+Ney6NYzMHgEQnS0OOPbvhz438H5o=; fh=NN/egyNAVKO45cELaDOD2pyXBt7CM4PpQem6qkTM8Gk=; b=Y/p0gsqGhAWXzy0yrWvN0qaiV4Nw4LYmSCJ+jbHBFuolDy/LTm1G7aYxQg2Dysz7di UQOYe7StpK9N6cIePA7//jRyY9FwpVaFYXm8DL8kWViJkgXDih6yG8Uvr4QscdgkhpKv 7FrtBz/26owsK5WTzZzyZgkxGbtQBe2svmAdIW/F6NCvwCzt1xWi1CM+0Y+57Davu6bs kxPC5kVNweoLpu9l6AiV+BMrjH177VdIHBUgQkBnByBMdBvLduly8fXE5FUNSPo5XrPh HEwhbSRVWjHmfgQH6BwKQ1MS4F70kvM+pbYZK8Uhxx9SR4j6kMErnl73vrrDqzacG7W0 zGIQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Q6Reit88; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ce9f2d081sm27980775e9.21.2025.03.08.11.03.00 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 08 Mar 2025 11:03:00 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: BALATON Zoltan , qemu-devel@nongnu.org Cc: Bernhard Beschow , Peter Maydell , qemu-ppc@nongnu.org, Andrey Smirnov , Jean-Christophe Dubois , Bin Meng , qemu-arm@nongnu.org, qemu-block@nongnu.org, Guenter Roeck , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v3 06/12] hw/sd/sdhci: Allow SDHCI classes to register their own MemoryRegionOps Date: Sat, 8 Mar 2025 20:02:24 +0100 Message-ID: <20250308190230.7508-7-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250308190230.7508-1-philmd@linaro.org> References: <20250308190230.7508-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Add MemoryRegionOps as a class property. For now it is only used by TYPE_IMX_USDHC. Otherwise the default remains in little endian. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/sd/sdhci.h | 1 + hw/sd/sdhci.c | 22 ++++++++-------------- 2 files changed, 9 insertions(+), 14 deletions(-) diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h index 2709a7a69d5..60a0442c805 100644 --- a/include/hw/sd/sdhci.h +++ b/include/hw/sd/sdhci.h @@ -112,6 +112,7 @@ typedef struct SDHCIClass { SysBusDeviceClass sbd_parent_class; }; + const MemoryRegionOps *io_ops; uint32_t quirks; uint64_t iomem_size; } SDHCIClass; diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 59d506cafa3..d87a7bb45a4 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -1427,8 +1427,6 @@ void sdhci_initfn(SDHCIState *s) sdhci_raise_insertion_irq, s); s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_data_transfer, s); - - s->io_ops = &sdhci_mmio_le_ops; } void sdhci_uninitfn(SDHCIState *s) @@ -1445,6 +1443,7 @@ void sdhci_common_realize(SDHCIState *s, Error **errp) ERRP_GUARD(); SDHCIClass *sc = SYSBUS_SDHCI_GET_CLASS(s); + s->io_ops = sc->io_ops ?: &sdhci_mmio_le_ops; switch (s->endianness) { case DEVICE_LITTLE_ENDIAN: /* s->io_ops is little endian by default */ @@ -1888,17 +1887,11 @@ static const MemoryRegionOps usdhc_mmio_ops = { .endianness = DEVICE_LITTLE_ENDIAN, }; -static void imx_usdhc_init(Object *obj) -{ - SDHCIState *s = SYSBUS_SDHCI(obj); - - s->io_ops = &usdhc_mmio_ops; -} - static void imx_usdhc_class_init(ObjectClass *oc, void *data) { SDHCIClass *sc = SYSBUS_SDHCI_CLASS(oc); + sc->io_ops = &usdhc_mmio_ops; sc->quirks = SDHCI_QUIRK_NO_BUSY_IRQ; sdhci_common_class_init(oc, data); @@ -1955,11 +1948,13 @@ static const MemoryRegionOps sdhci_s3c_mmio_ops = { .endianness = DEVICE_LITTLE_ENDIAN, }; -static void sdhci_s3c_init(Object *obj) +static void sdhci_s3c_class_init(ObjectClass *oc, void *data) { - SDHCIState *s = SYSBUS_SDHCI(obj); + SDHCIClass *sc = SYSBUS_SDHCI_CLASS(oc); - s->io_ops = &sdhci_s3c_mmio_ops; + sc->io_ops = &sdhci_s3c_mmio_ops; + + sdhci_common_class_init(oc, data); } static const TypeInfo sdhci_types[] = { @@ -1981,13 +1976,12 @@ static const TypeInfo sdhci_types[] = { { .name = TYPE_IMX_USDHC, .parent = TYPE_SYSBUS_SDHCI, - .instance_init = imx_usdhc_init, .class_init = imx_usdhc_class_init, }, { .name = TYPE_S3C_SDHCI, .parent = TYPE_SYSBUS_SDHCI, - .instance_init = sdhci_s3c_init, + .class_init = sdhci_s3c_class_init, }, }; From patchwork Sat Mar 8 19:02:25 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 871546 Delivered-To: patch@linaro.org Received: by 2002:a5d:64ce:0:b0:38f:210b:807b with SMTP id f14csp288592wri; Sat, 8 Mar 2025 11:05:57 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCU5nolf1Ms/kEuiGfqtgzqV4dKP3wfr8mZeK4E9wtojJ8OCW/mQ3SN+I7psUGVo76x5uTDKoA==@linaro.org X-Google-Smtp-Source: AGHT+IGJqOFobd9CwE6YXf57N0soWvLL5d2nyFYqHecP0Divc4xqhhMJ4b5jsP8mKZBILW1Wm4zX X-Received: by 2002:a05:622a:58b:b0:474:e664:691f with SMTP id d75a77b69052e-47618b02419mr128607851cf.39.1741460757588; Sat, 08 Mar 2025 11:05:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741460757; cv=none; d=google.com; s=arc-20240605; b=JLOYWI9uPjbddvQbLH72ntBStvJg3wZAAk5ScioncJektoUlhlHrUdVtuFigWVlmBX 51wRIlth1vnII2iu3Ijh4E4jG8GizXeE4Prz297/SoM1PCJMwRDPn5imSmowYJH5WH3n +W0IOAN/1epkVay03EfPbzffv6VLk98npLPQPLGfCYI6FUS55quwuTWfih51XRBM8Lh3 qOCKAWYuWN3RGtxiNqdK132oFkcmViN5ZktOr5DckrO/WN6CtlwXYniYq2bgWHwDbJ7K aYImVr0ecGGjB5znCWHv5RZAa17q1+gLO9hTqgmgo6Rhl6OvQKVaLZvfeWi04APJsIKN qWpQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=74sWG9go8/U3pCHdLat3DJreQSt1Fc2X0U97u54k3uc=; fh=mIdlPJRCApO1KQhGB9jm3TfKuhxkvueDvY4K47gOYEY=; b=FyNblQae7yCW2Bocm+fVJmBNGF4rwVam6P385RvjWdh4SZPy1te2Of41s21Qfghtyr 4gtkKe4604FF1tPU8c2mp3wdtX6uHwRP0ZVCHtUmIBhShJgP7wZf9lQXfUmOJWJW6B48 nwNVi3mjFZGnY27C5fNLQIJQuUDwG/hCw380wlVGY9Ju1JwCpz6rDSTz2RBbR5XKNV+g ARd41pwrgRadomaa1igX/5axeW/Gq8EMRboKOoN/h+Vj744XAQ1QFMJCxulOCnSDYr4+ VNqJ67xPg0kEBVyszqBgReYYnXVcJIyUiMUjxlY2tPsYXMgR6Pb5Fcc6XB3LJZjN3TRg nZag==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gkeA2RAP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43cec8e1596sm17687745e9.31.2025.03.08.11.03.05 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 08 Mar 2025 11:03:05 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: BALATON Zoltan , qemu-devel@nongnu.org Cc: Bernhard Beschow , Peter Maydell , qemu-ppc@nongnu.org, Andrey Smirnov , Jean-Christophe Dubois , Bin Meng , qemu-arm@nongnu.org, qemu-block@nongnu.org, Guenter Roeck , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v3 07/12] hw/sd/sdhci: Simplify MemoryRegionOps endianness check Date: Sat, 8 Mar 2025 20:02:25 +0100 Message-ID: <20250308190230.7508-8-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250308190230.7508-1-philmd@linaro.org> References: <20250308190230.7508-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org While little endianness is the default, ome controllers might be only implemented in big endianness. Signed-off-by: Philippe Mathieu-Daudé --- hw/sd/sdhci.c | 18 ++++-------------- 1 file changed, 4 insertions(+), 14 deletions(-) diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index d87a7bb45a4..d115e88c4b9 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -1443,20 +1443,10 @@ void sdhci_common_realize(SDHCIState *s, Error **errp) ERRP_GUARD(); SDHCIClass *sc = SYSBUS_SDHCI_GET_CLASS(s); - s->io_ops = sc->io_ops ?: &sdhci_mmio_le_ops; - switch (s->endianness) { - case DEVICE_LITTLE_ENDIAN: - /* s->io_ops is little endian by default */ - break; - case DEVICE_BIG_ENDIAN: - if (s->io_ops != &sdhci_mmio_le_ops) { - error_setg(errp, "SD controller doesn't support big endianness"); - return; - } - s->io_ops = &sdhci_mmio_be_ops; - break; - default: - error_setg(errp, "Incorrect endianness"); + s->io_ops = sc->io_ops ?: (s->endianness == DEVICE_BIG_ENDIAN ? + &sdhci_mmio_be_ops : &sdhci_mmio_le_ops); + if (s->io_ops->endianness != s->endianness) { + error_setg(errp, "Invalid endianness for SD controller"); return; } From patchwork Sat Mar 8 19:02:26 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 871547 Delivered-To: patch@linaro.org Received: by 2002:a5d:64ce:0:b0:38f:210b:807b with SMTP id f14csp288599wri; Sat, 8 Mar 2025 11:05:59 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWgOz4syXgBTuOLOByqpPrpOW3IJ2DUteMjMNnPUV9BkyIQwJLYc7FVpyOrxZ1AYMPP/1h6bg==@linaro.org X-Google-Smtp-Source: AGHT+IGPkeFL7P7Sgmnn8/0+kTwiNc3Mctqm3JyfqEgBZBSNURX1HCWZ44hYSldNbyzmn1+LeAqF X-Received: by 2002:a05:620a:6846:b0:7c5:47c6:b880 with SMTP id af79cd13be357-7c547c6bb5amr245393085a.2.1741460759154; Sat, 08 Mar 2025 11:05:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741460759; cv=none; d=google.com; s=arc-20240605; b=IWyeF9omUAFk1k7oo1n8kmX5HunPdE1jbZC3wJK8FrkiEUXkC6ae5HlQ6z4vMiAUWt eCU3GRB4SjfYNd69GqC0vGaCEWewJfJ5khN1grmPFo23NtQY3J1LexGA0znty8hte4j1 tBpiKW76409wDeuvHDKNrd1TijTJIDfrq9wkLwoAHl8j6JWl4cx2WVPjcaEgxSnveArH EhF3w55qRsKN35Gv5d4FqUM2UOUcOpyu9EDBxZbOYEtijJH1e6mHzwLKi+u87bkBShmd jgVmJ9XktB8hkq8464YXeCVcSKzPw0iRkYU31xo2CDOX/4h/Uk48bXJXbr6Um2j4gj0j UT+Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=EY3LDQvhSY1UJUDBZWJ0oLgNLpHwNcu9pDPeUp1WnOo=; fh=rXud+P/kBdoeDNfWRGrYQS83AMS6eoxCwqcP+WjSMuI=; b=SeZkpA674dTKkQqwTFvLSRVM7QUXtZMd0IPg20KMchhYKs7wzQUlMdWlx7sdmXdmvc ZaOBVcXLl+uLoA3ZnV4ZNvfk9sJjMGoywaEpLND/nw9zelqL9jqfV1LEyV6meTywEw5K gopdX8YduXaAYsSbXNRoWMhQwEWfSmPPmsWYGvrUrmBVXQMhp/VBxpeSTg9PFbEHgcEo 7zUoYnpq8Dmwt/+19mjfrpmnMJI9TbIJSkPGTc3izM4FXUbGE1x4ICnTpGcqtXek9CSB ohEbmFXP/HmaHp7TKJM5M2Td3lO0JbxK+HPPZ7a/SaWoceuK4vq2j2Thd2W8Cm5/zPd4 WUBQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oeSFy2Fd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bd426c56esm127609315e9.8.2025.03.08.11.03.10 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 08 Mar 2025 11:03:10 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: BALATON Zoltan , qemu-devel@nongnu.org Cc: Bernhard Beschow , Peter Maydell , qemu-ppc@nongnu.org, Andrey Smirnov , Jean-Christophe Dubois , Bin Meng , qemu-arm@nongnu.org, qemu-block@nongnu.org, Guenter Roeck , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v3 08/12] hw/sd/sdhci: Unify default MemoryRegionOps Date: Sat, 8 Mar 2025 20:02:26 +0100 Message-ID: <20250308190230.7508-9-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250308190230.7508-1-philmd@linaro.org> References: <20250308190230.7508-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philmd@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Note, sdhci_mmio_le_ops[] was missing .impl.access_size = 4. Signed-off-by: Philippe Mathieu-Daudé --- hw/sd/sdhci.c | 41 ++++++++++++++++------------------------- 1 file changed, 16 insertions(+), 25 deletions(-) diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index d115e88c4b9..15e6976220f 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -1372,30 +1372,22 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) value >> shift, value >> shift); } -static const MemoryRegionOps sdhci_mmio_le_ops = { - .read = sdhci_read, - .write = sdhci_write, - .valid = { - .min_access_size = 1, - .max_access_size = 4, - .unaligned = false +static const MemoryRegionOps sdhci_mmio_ops[2] = { + [0 ... 1] = { + .read = sdhci_read, + .write = sdhci_write, + .impl = { + .min_access_size = 4, + .max_access_size = 4, + }, + .valid = { + .min_access_size = 1, + .max_access_size = 4, + .unaligned = false + }, }, - .endianness = DEVICE_LITTLE_ENDIAN, -}; - -static const MemoryRegionOps sdhci_mmio_be_ops = { - .read = sdhci_read, - .write = sdhci_write, - .impl = { - .min_access_size = 4, - .max_access_size = 4, - }, - .valid = { - .min_access_size = 1, - .max_access_size = 4, - .unaligned = false - }, - .endianness = DEVICE_BIG_ENDIAN, + [0].endianness = DEVICE_LITTLE_ENDIAN, + [1].endianness = DEVICE_BIG_ENDIAN, }; static void sdhci_init_readonly_registers(SDHCIState *s, Error **errp) @@ -1443,8 +1435,7 @@ void sdhci_common_realize(SDHCIState *s, Error **errp) ERRP_GUARD(); SDHCIClass *sc = SYSBUS_SDHCI_GET_CLASS(s); - s->io_ops = sc->io_ops ?: (s->endianness == DEVICE_BIG_ENDIAN ? - &sdhci_mmio_be_ops : &sdhci_mmio_le_ops); + s->io_ops = sc->io_ops ?: &sdhci_mmio_ops[s->endianness == DEVICE_BIG_ENDIAN]; if (s->io_ops->endianness != s->endianness) { error_setg(errp, "Invalid endianness for SD controller"); return; From patchwork Sat Mar 8 19:02:27 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 871539 Delivered-To: patch@linaro.org Received: by 2002:a5d:64ce:0:b0:38f:210b:807b with SMTP id f14csp288045wri; Sat, 8 Mar 2025 11:04:23 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXutRWIeI/+5+bRIyu+RwXC1jPCB+YuqNkjKlaA8a9tsG/EBDJB1/GJkisXnfJwRlv1MTryxw==@linaro.org X-Google-Smtp-Source: AGHT+IGuvvhsRRsZ3q/F6qkhHebiXOHbB48RiV2nFwekaAO0DBOzssPp5EgZCjERDOkgUnx+88zA X-Received: by 2002:a05:620a:2b4d:b0:7c5:48bc:8c77 with SMTP id af79cd13be357-7c548bc8f36mr182436785a.12.1741460663117; Sat, 08 Mar 2025 11:04:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741460663; cv=none; d=google.com; s=arc-20240605; b=dXq3g4Rl9WvzQMuTd6lGR45I5sNTp9AtT+LJuyo/JTkjl+0gZWg0fjDUeWX2ZD7WBh 0aq9zmjJAEkjJcw/7aJArq7xrtQh66a2LzyGGla64ME+jC+wKIiL/p0j6S795AJxs0tk p2Tx9+FjGsmmT3Ye8kpKHJYF04jYFo/e0+6rdVNxNK3rj9/mCfeakqHDYnBzIZnymICp tkYccGFFg9HYIM0Pl2VY+JYMVwVRjX1aGdv/4OUbJSe5U1h2VfbozmNBAK0VWocXDltn c+kDTGorHitDPyuIiyUfT/RQF/KjO4U18TRJ/2ePsDzvFE/ZYqQ9Dou3o6IfLt/EFirq cG2Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=pF2WPF4xppL7qEVeYgXT9lZoDPpMUXtxJ+GDygppA/w=; fh=K3sxxABndW/ZUCY8ERQZzm7PKH+FKLDRRYN7V4K3ZS0=; b=gqPDi+PsZPsd/rrctnI6Mcb0+qMoCZOZxdKwjol4cEKbwRzD+cu6kJXsD5biZpKwty kk5l3pvRjhydViIeCFOnWSEyss01JXZ0USBzxXPQM8BK3JvcfXhpjHQo1Y9SiYaU/e+x Gn2VKrsZyXMGZvwipjuVcdYVSDoOrcXTccT87F2mE7bH1ulf9PfWHN6vdcW945ulilcy tIsdxHhPkxy25KFHsJYzILzJ8Nlvmc/XAwtGPHx05VnhKjYN0XD03EB16tgfl0iGIKb8 5Ff+jbmJ+gOVT10Go5W4I4CIaNRr0PQrYRkRy1Di24Mt3/UqzKirJCU+Bi3mJ2QBBHLN ggZg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Cj9MSuMZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ce8a493d0sm30603875e9.1.2025.03.08.11.03.14 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 08 Mar 2025 11:03:15 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: BALATON Zoltan , qemu-devel@nongnu.org Cc: Bernhard Beschow , Peter Maydell , qemu-ppc@nongnu.org, Andrey Smirnov , Jean-Christophe Dubois , Bin Meng , qemu-arm@nongnu.org, qemu-block@nongnu.org, Guenter Roeck , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v3 09/12] hw/sd/sdhci: Add SDHCIClass::ro::capareg field Date: Sat, 8 Mar 2025 20:02:27 +0100 Message-ID: <20250308190230.7508-10-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250308190230.7508-1-philmd@linaro.org> References: <20250308190230.7508-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Capability register is read-only. Since we allow instances to clear/set extra bits, log when read-only bits normally set by hardware are cleared at board level. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/sd/sdhci.h | 5 +++++ hw/sd/sdhci.c | 6 ++++++ 2 files changed, 11 insertions(+) diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h index 60a0442c805..53aef17ad34 100644 --- a/include/hw/sd/sdhci.h +++ b/include/hw/sd/sdhci.h @@ -115,6 +115,11 @@ typedef struct SDHCIClass { const MemoryRegionOps *io_ops; uint32_t quirks; uint64_t iomem_size; + + /* Read-only registers */ + struct { + uint64_t capareg; + } ro; } SDHCIClass; /* diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 15e6976220f..f08918587ef 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -73,6 +73,7 @@ static bool sdhci_check_capab_freq_range(SDHCIState *s, const char *desc, static void sdhci_check_capareg(SDHCIState *s, Error **errp) { + SDHCIClass *sc = SYSBUS_SDHCI_GET_CLASS(s); uint64_t msk = s->capareg; uint32_t val; bool y; @@ -208,6 +209,11 @@ static void sdhci_check_capareg(SDHCIState *s, Error **errp) qemu_log_mask(LOG_UNIMP, "SDHCI: unknown CAPAB mask: 0x%016" PRIx64 "\n", msk); } + msk = sc->ro.capareg & ~s->capareg; + if (msk) { + qemu_log_mask(LOG_UNIMP, + "SDHCI: ignored CAPAB mask: 0x%016" PRIx64 "\n", msk); + } } static uint8_t sdhci_slotint(SDHCIState *s) From patchwork Sat Mar 8 19:02:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 871548 Delivered-To: patch@linaro.org Received: by 2002:a5d:64ce:0:b0:38f:210b:807b with SMTP id f14csp288608wri; Sat, 8 Mar 2025 11:06:01 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVp39L0/xVB1fy+w0DKlAqGLe0YZP9Horx+6B8tU75RIqyT/Fw94Bm910R0G47BU/4KFOwk4A==@linaro.org X-Google-Smtp-Source: AGHT+IHLQ1cGWmHd60qgciRfyGe03KIuvQsYievQiCvtUyATMSPWf+vyT7Qu67Ez/frqxXKEBBHG X-Received: by 2002:ad4:5c85:0:b0:6e8:9053:825e with SMTP id 6a1803df08f44-6e907d3e8a5mr56039156d6.17.1741460761067; Sat, 08 Mar 2025 11:06:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741460761; cv=none; d=google.com; s=arc-20240605; b=ib8kJd2neCEhdhPaNO8bnucappI+hRd1aWVfgjmUCcUoBzta4SS6KNRWNvagmeFvc4 Rp6hvYJQRlNGKOQuu4ixEnzBIiz2RL3NKczbnKt36+U0rTBBMYlCj1a3Hmp+KeuT3bz+ QnWRemf9Iw24Gvk5aQ2k+qA9HRnloyV395FIwXxK2KMjZf3SBg+WogTWQo3dXvvpu6xQ TZRlbDnUm1dVGUeZ7BzDFwVK4Z+g7bJNikIdlNiloDl7edGbJZ8Ju3GVHwAuegW/Xpui +QJX/pkxDVAIOkRehPaxji6sRaWLNkD6CBhyMpPHNi5kbDFmeOPzlKqZa9zw5fEPw6F3 m9yg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=DdQ356KPyw7Fp0a97T7o8FXWBighqGS1ZACq8XsdKoI=; fh=DQeT9fudDz+IIygbsJG/iebcOKjuB+tigP/J4h4VeBA=; b=Im5kKC6NtrdAUXqVNp70xzWGw789+xwLyyxRk/NzM0Ho2EWuzHh94zO+i2kRWSTHEQ 9KLiJChQHV3Ye1HvtoJ2f5QVuWJ23gXNFqRt96f7L3vH6EwESWo3DzRntwW2EIR8m2n1 xdJdAXScWYPOasmy4Bn51VLySWgUB1YCcoXk5KCyvtYWApVLe+6ewvft0fXTQtLJZizI RSkBaOBdtuALJsxh/+YwUy2EwHUeuiiVepLC/eDVsvWEOAcaoi0HQz+E5crueI8crFNr CAhoha196Lzr1jp4eU36ieg3moYkdYRu4YrfjaGEWpxsP1A1meoiATvfY/uOs5E0h7p+ utiQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=THyi2zKK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912c10437dsm9772819f8f.99.2025.03.08.11.03.19 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 08 Mar 2025 11:03:20 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: BALATON Zoltan , qemu-devel@nongnu.org Cc: Bernhard Beschow , Peter Maydell , qemu-ppc@nongnu.org, Andrey Smirnov , Jean-Christophe Dubois , Bin Meng , qemu-arm@nongnu.org, qemu-block@nongnu.org, Guenter Roeck , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v3 10/12] hw/sd/sdhci: Allow SDHCI classes to have different register reset values Date: Sat, 8 Mar 2025 20:02:28 +0100 Message-ID: <20250308190230.7508-11-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250308190230.7508-1-philmd@linaro.org> References: <20250308190230.7508-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org For the registers which are not zeroed at reset, allow the different implementations to set particular reset values. Remove the misleading values commented in sdhci-internal.h. Signed-off-by: Philippe Mathieu-Daudé --- hw/sd/sdhci-internal.h | 24 ++++++++++++------------ include/hw/sd/sdhci.h | 20 ++++++++++++++++++++ hw/sd/sdhci.c | 14 ++++++++++++++ 3 files changed, 46 insertions(+), 12 deletions(-) diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h index 9072b06bdde..d99a8493db2 100644 --- a/hw/sd/sdhci-internal.h +++ b/hw/sd/sdhci-internal.h @@ -70,7 +70,7 @@ /* R/W Buffer Data Register 0x0 */ #define SDHC_BDATA 0x20 -/* R/ROC Present State Register 0x000A0000 */ +/* R/ROC Present State Register */ #define SDHC_PRNSTS 0x24 #define SDHC_CMD_INHIBIT 0x00000001 #define SDHC_DATA_INHIBIT 0x00000002 @@ -88,7 +88,7 @@ FIELD(SDHC_PRNSTS, CMD_LVL, 24, 1); #define TRANSFERRING_DATA(x) \ ((x) & (SDHC_DOING_READ | SDHC_DOING_WRITE)) -/* R/W Host control Register 0x0 */ +/* R/W Host control Register */ #define SDHC_HOSTCTL 0x28 #define SDHC_CTRL_LED 0x01 #define SDHC_CTRL_DATATRANSFERWIDTH 0x02 /* SD mode only */ @@ -104,17 +104,17 @@ FIELD(SDHC_PRNSTS, CMD_LVL, 24, 1); #define SDHC_CTRL_CDTEST_INS 0x40 #define SDHC_CTRL_CDTEST_EN 0x80 -/* R/W Power Control Register 0x0 */ +/* R/W Power Control Register */ #define SDHC_PWRCON 0x29 #define SDHC_POWER_ON (1 << 0) FIELD(SDHC_PWRCON, BUS_VOLTAGE, 1, 3); -/* R/W Block Gap Control Register 0x0 */ +/* R/W Block Gap Control Register */ #define SDHC_BLKGAP 0x2A #define SDHC_STOP_AT_GAP_REQ 0x01 #define SDHC_CONTINUE_REQ 0x02 -/* R/W WakeUp Control Register 0x0 */ +/* R/W WakeUp Control Register */ #define SDHC_WAKCON 0x2B #define SDHC_WKUP_ON_INS (1 << 1) #define SDHC_WKUP_ON_RMV (1 << 2) @@ -128,17 +128,17 @@ FIELD(SDHC_PWRCON, BUS_VOLTAGE, 1, 3); #define SDHC_CLOCK_IS_ON(x) \ (((x) & SDHC_CLOCK_CHK_MASK) == SDHC_CLOCK_CHK_MASK) -/* R/W Timeout Control Register 0x0 */ +/* R/W Timeout Control Register */ #define SDHC_TIMEOUTCON 0x2E FIELD(SDHC_TIMEOUTCON, COUNTER, 0, 4); -/* R/W Software Reset Register 0x0 */ +/* R/W Software Reset Register */ #define SDHC_SWRST 0x2F #define SDHC_RESET_ALL 0x01 #define SDHC_RESET_CMD 0x02 #define SDHC_RESET_DATA 0x04 -/* ROC/RW1C Normal Interrupt Status Register 0x0 */ +/* ROC/RW1C Normal Interrupt Status Register */ #define SDHC_NORINTSTS 0x30 #define SDHC_NIS_ERR 0x8000 #define SDHC_NIS_CMDCMP 0x0001 @@ -151,7 +151,7 @@ FIELD(SDHC_TIMEOUTCON, COUNTER, 0, 4); #define SDHC_NIS_REMOVE 0x0080 #define SDHC_NIS_CARDINT 0x0100 -/* ROC/RW1C Error Interrupt Status Register 0x0 */ +/* ROC/RW1C Error Interrupt Status Register */ #define SDHC_ERRINTSTS 0x32 #define SDHC_EIS_CMDTIMEOUT 0x0001 #define SDHC_EIS_BLKGAP 0x0004 @@ -159,7 +159,7 @@ FIELD(SDHC_TIMEOUTCON, COUNTER, 0, 4); #define SDHC_EIS_CMD12ERR 0x0100 #define SDHC_EIS_ADMAERR 0x0200 -/* R/W Normal Interrupt Status Enable Register 0x0 */ +/* R/W Normal Interrupt Status Enable Register */ #define SDHC_NORINTSTSEN 0x34 #define SDHC_NISEN_CMDCMP 0x0001 #define SDHC_NISEN_TRSCMP 0x0002 @@ -170,7 +170,7 @@ FIELD(SDHC_TIMEOUTCON, COUNTER, 0, 4); #define SDHC_NISEN_REMOVE 0x0080 #define SDHC_NISEN_CARDINT 0x0100 -/* R/W Error Interrupt Status Enable Register 0x0 */ +/* R/W Error Interrupt Status Enable Register */ #define SDHC_ERRINTSTSEN 0x36 #define SDHC_EISEN_CMDTIMEOUT 0x0001 #define SDHC_EISEN_BLKGAP 0x0004 @@ -205,7 +205,7 @@ FIELD(SDHC_HOSTCTL2, VERSION4, 12, 1); /* since v4 */ FIELD(SDHC_HOSTCTL2, ASYNC_INT, 14, 1); FIELD(SDHC_HOSTCTL2, PRESET_ENA, 15, 1); -/* HWInit Capabilities Register 0x05E80080 */ +/* HWInit Capabilities Register */ #define SDHC_CAPAB 0x40 FIELD(SDHC_CAPAB, TOCLKFREQ, 0, 6); FIELD(SDHC_CAPAB, TOUNIT, 7, 1); diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h index 53aef17ad34..e24392eb10d 100644 --- a/include/hw/sd/sdhci.h +++ b/include/hw/sd/sdhci.h @@ -116,6 +116,26 @@ typedef struct SDHCIClass { uint32_t quirks; uint64_t iomem_size; + /* Default reset values */ + struct { + uint32_t sdmasysad; + + uint16_t blksize; + uint16_t blkcnt; + + uint32_t prnsts; + + uint8_t hostctl1; + uint8_t pwrcon; + uint8_t blkgap; + uint8_t wakcon; + + uint16_t clkcon; + uint8_t timeoutcon; + + uint16_t norintstsen; + uint16_t errintstsen; + } reset; /* Read-only registers */ struct { uint64_t capareg; diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index f08918587ef..cda608f8ec2 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -294,6 +294,7 @@ static void sdhci_set_readonly(DeviceState *dev, bool level) static void sdhci_reset(SDHCIState *s) { + SDHCIClass *sc = SYSBUS_SDHCI_GET_CLASS(s); DeviceState *dev = DEVICE(s); timer_del(s->insert_timer); @@ -306,6 +307,19 @@ static void sdhci_reset(SDHCIState *s) */ memset(&s->sdmasysad, 0, (uintptr_t)&s->capareg - (uintptr_t)&s->sdmasysad); + s->sdmasysad = sc->reset.sdmasysad; + s->blksize = sc->reset.blksize; + s->blkcnt = sc->reset.blkcnt; + s->prnsts = sc->reset.prnsts; + s->hostctl1 = sc->reset.hostctl1; + s->pwrcon = sc->reset.pwrcon; + s->blkgap = sc->reset.blkgap; + s->wakcon = sc->reset.wakcon; + s->clkcon = sc->reset.clkcon; + s->timeoutcon = sc->reset.timeoutcon; + s->norintstsen = sc->reset.norintstsen; + s->errintstsen = sc->reset.errintstsen; + /* Reset other state based on current card insertion/readonly status */ sdhci_set_inserted(dev, sdbus_get_inserted(&s->sdbus)); sdhci_set_readonly(dev, sdbus_get_readonly(&s->sdbus)); From patchwork Sat Mar 8 19:02:29 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 871543 Delivered-To: patch@linaro.org Received: by 2002:a5d:64ce:0:b0:38f:210b:807b with SMTP id f14csp288485wri; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bd4292b06sm121601615e9.14.2025.03.08.11.03.24 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 08 Mar 2025 11:03:25 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: BALATON Zoltan , qemu-devel@nongnu.org Cc: Bernhard Beschow , Peter Maydell , qemu-ppc@nongnu.org, Andrey Smirnov , Jean-Christophe Dubois , Bin Meng , qemu-arm@nongnu.org, qemu-block@nongnu.org, Guenter Roeck , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v3 11/12] hw/sd/sdhci: Implement Freescale eSDHC as TYPE_FSL_ESDHC Date: Sat, 8 Mar 2025 20:02:29 +0100 Message-ID: <20250308190230.7508-12-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250308190230.7508-1-philmd@linaro.org> References: <20250308190230.7508-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Per the MPC8569E reference manual, its SDHC I/O range is 4KiB wide, mapped in big endian order, and it only accepts 32-bit aligned access. Set the default register reset values. Reported-by: BALATON Zoltan Signed-off-by: Philippe Mathieu-Daudé --- include/hw/sd/sdhci.h | 2 ++ hw/sd/sdhci.c | 37 ++++++++++++++++++++++++++++++++++++- 2 files changed, 38 insertions(+), 1 deletion(-) diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h index e24392eb10d..0e9d3b10d1b 100644 --- a/include/hw/sd/sdhci.h +++ b/include/hw/sd/sdhci.h @@ -161,6 +161,8 @@ DECLARE_INSTANCE_CHECKER(SDHCIState, SYSBUS_SDHCI, DECLARE_CLASS_CHECKERS(SDHCIClass, SYSBUS_SDHCI, TYPE_SYSBUS_SDHCI) +#define TYPE_FSL_ESDHC "fsl-esdhc" + #define TYPE_IMX_USDHC "imx-usdhc" #define TYPE_S3C_SDHCI "s3c-sdhci" diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index cda608f8ec2..a78cff40fb1 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -1644,7 +1644,37 @@ static void sdhci_bus_class_init(ObjectClass *klass, void *data) sbc->set_readonly = sdhci_set_readonly; } -/* --- qdev i.MX eSDHC --- */ +/* --- Freescale eSDHC (MPC8569ERM Rev.2 from 06/2011) --- */ + +static const MemoryRegionOps fsl_esdhc_mmio_ops = { + .read = sdhci_read, + .write = sdhci_write, + .valid = { + .min_access_size = 4, + .unaligned = false + }, + .endianness = DEVICE_BIG_ENDIAN, +}; + +static void fsl_esdhc_class_init(ObjectClass *oc, void *data) +{ + SDHCIClass *sc = SYSBUS_SDHCI_CLASS(oc); + + sc->iomem_size = 0x1000; + sc->io_ops = &fsl_esdhc_mmio_ops; + sc->ro.capareg = 0x01e30000; + sc->reset.sdmasysad = 8; + sc->reset.blkcnt = 8; + sc->reset.prnsts = 0xff800000; + sc->reset.hostctl1 = 0x20; /* Endian mode (address-invariant) */ + sc->reset.clkcon = 0x8000; + sc->reset.norintstsen = 0x013f; + sc->reset.errintstsen = 0x117f; + + sdhci_common_class_init(oc, data); +} + +/* --- qdev i.MX uSDHC --- */ #define USDHC_MIX_CTRL 0x48 @@ -1974,6 +2004,11 @@ static const TypeInfo sdhci_types[] = { .class_size = sizeof(SDHCIClass), .class_init = sdhci_sysbus_class_init, }, + { + .name = TYPE_FSL_ESDHC, + .parent = TYPE_SYSBUS_SDHCI, + .class_init = fsl_esdhc_class_init, + }, { .name = TYPE_IMX_USDHC, .parent = TYPE_SYSBUS_SDHCI, From patchwork Sat Mar 8 19:02:30 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 871549 Delivered-To: patch@linaro.org Received: by 2002:a5d:64ce:0:b0:38f:210b:807b with SMTP id f14csp288703wri; Sat, 8 Mar 2025 11:06:16 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCW0dWLYGAeGICq1GcRNDcB1w0QEsfUVWAAQchQ4Pv9d+PTZFYuQ+rP0uMhJh9RXojWXHtmqYg==@linaro.org X-Google-Smtp-Source: AGHT+IFoyXN0fn7/bUiVtmvD3WXQ27iG+lfsq2893/uOurBohvJ0C6jdnGeAgHPY3IoXy3F/4Fbd X-Received: by 2002:a05:620a:271a:b0:7c5:4088:e48c with SMTP id af79cd13be357-7c54088e708mr364892485a.29.1741460775979; Sat, 08 Mar 2025 11:06:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741460775; cv=none; d=google.com; s=arc-20240605; b=O82UnLq+PRua5xIBNonqX+SuLRobn9jHOsc4fpLjpMYx10faQw5WmkEs2ksdAWNRkR gS5tKPAAOJQE3RI6NpJ4aqC3ZNfVbTzO/X+z7wMnhEz3U5muCZiQMGA5WLxvmWzzuWVk TYsKdU0RokKsd0FWRUwzz7UuLS3IJc39R63DuUGLRfFOsV7ybpqlFah8yXIiGFiieccA kxyZm0Rt8yew1QcMeTPzHQLzJQKgUjv7IIFtEAoAEsnHZmRfqckuEsbBY8sqIyf3Inhu dzkaLxYSuJNjiEIBDZnUb33vHFEul86JFki/+YtUTQOomXJooAk1Gy6bb5/b4aBynyDf 1CAg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=NQvf9YM7B8m3c5YxTAHSd6W3rVOYDlZhVENkZCcVArU=; fh=rtb8kQzvJW93g1QjjEeht+qVbY3D4F7gvoTzSSlnIQI=; b=GrdTY6915IkS+xO24EvwMDR5KizJ40iTCOHleg1ZRSo9/Nj+uBYICJxpu8aqVBsDfn SdibQOaP4pIFOFrcvOI8MxAAqkPG1lBbqUlMYZi5yCk35i3rwJbA8QaDzQAHZJvr82Y2 iS6DeQMhLmyKgELsb4RRS9uOqOp48WyImDuggJrgszSiwJCuAqZtaxMKkz82jvnawptJ HRQe/0eiamlUvYDC8HKKk5480eVHQOxpvdWCHr5tV8NpNEqJe2tqx+qM7EGoaoCSEuYv 2eVIh0O1We0QuMVRr3CQTtjRx/mNyozz16dQpXpleIZ4k0tuxUycmCVQqoxtaxg4jImp OUgQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ns7w44Lp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43cef25f075sm8657555e9.28.2025.03.08.11.03.30 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 08 Mar 2025 11:03:31 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: BALATON Zoltan , qemu-devel@nongnu.org Cc: Bernhard Beschow , Peter Maydell , qemu-ppc@nongnu.org, Andrey Smirnov , Jean-Christophe Dubois , Bin Meng , qemu-arm@nongnu.org, qemu-block@nongnu.org, Guenter Roeck , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v3 12/12] hw/ppc/e500: Replace generic SDHCI by Freescale eSDHC Date: Sat, 8 Mar 2025 20:02:30 +0100 Message-ID: <20250308190230.7508-13-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250308190230.7508-1-philmd@linaro.org> References: <20250308190230.7508-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org As Zoltan reported, some U-Boot versions seem to expect correctly initialized registers before expecting interrupts. Now than we have a proper Freescale eSDHC implementation, use it. Reported-by: BALATON Zoltan Signed-off-by: Philippe Mathieu-Daudé --- hw/ppc/e500.c | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index fe8b9f79621..e69551ccdb3 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -1027,20 +1027,12 @@ void ppce500_init(MachineState *machine) /* eSDHC */ if (pmc->has_esdhc) { - dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE); - qdev_prop_set_string(dev, "name", "esdhc"); - qdev_prop_set_uint64(dev, "size", MPC85XX_ESDHC_REGS_SIZE); - s = SYS_BUS_DEVICE(dev); - sysbus_realize_and_unref(s, &error_fatal); - memory_region_add_subregion(ccsr_addr_space, MPC85XX_ESDHC_REGS_OFFSET, - sysbus_mmio_get_region(s, 0)); - /* * Compatible with: * - SD Host Controller Specification Version 2.0 Part A2 * (See MPC8569E Reference Manual) */ - dev = qdev_new(TYPE_SYSBUS_SDHCI); + dev = qdev_new(TYPE_FSL_ESDHC); qdev_prop_set_uint8(dev, "sd-spec-version", 2); qdev_prop_set_uint8(dev, "endianness", DEVICE_BIG_ENDIAN); s = SYS_BUS_DEVICE(dev);