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[93.34.90.129]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-3912bee262esm11867536f8f.0.2025.03.09.06.30.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Mar 2025 06:30:39 -0700 (PDT) From: Christian Marangi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Christian Marangi , Vinod Koul , Kishon Vijay Abraham I , Matthias Brugger , AngeloGioacchino Del Regno , Greg Kroah-Hartman , Lorenzo Bianconi , Daniel Danzberger , Arnd Bergmann , Linus Walleij , Nikita Shubin , Guo Ren , Yangyu Chen , Ben Hutchings , Felix Fietkau , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-usb@vger.kernel.org, upstream@airoha.com Subject: [PATCH 01/13] clk: en7523: convert driver to regmap API Date: Sun, 9 Mar 2025 14:29:32 +0100 Message-ID: <20250309132959.19045-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250309132959.19045-1-ansuelsmth@gmail.com> References: <20250309132959.19045-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Convert driver to regmap API, in preparation for support of Airoha AN7583 as the SCU will be an MFD and the regmap will be provided in the parent node. Also Airoha EN7581 benefits from this in preparation of USB support that required checking and configuring SCU SSR bits. While at it also cleanup some register mask and use bitfield macro. Signed-off-by: Christian Marangi --- drivers/clk/clk-en7523.c | 137 ++++++++++++++++++++++----------------- 1 file changed, 76 insertions(+), 61 deletions(-) diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index 15bbdeb60b8e..314e7450313f 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only +#include #include #include #include @@ -34,6 +35,7 @@ #define REG_RESET_CONTROL_PCIE2 BIT(26) /* EN7581 */ #define REG_NP_SCU_PCIC 0x88 +#define REG_PCIE_CTRL GENMASK(7, 0) #define REG_NP_SCU_SSTR 0x9c #define REG_PCIE_XSI0_SEL_MASK GENMASK(14, 13) #define REG_PCIE_XSI1_SEL_MASK GENMASK(12, 11) @@ -63,14 +65,14 @@ struct en_clk_desc { }; struct en_clk_gate { - void __iomem *base; + struct regmap *map; struct clk_hw hw; }; struct en_rst_data { const u16 *bank_ofs; const u16 *idx_map; - void __iomem *base; + struct regmap *map; struct reset_controller_dev rcdev; }; @@ -388,44 +390,44 @@ static u32 en7523_get_div(const struct en_clk_desc *desc, u32 val) static int en7523_pci_is_enabled(struct clk_hw *hw) { struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); + u32 val; - return !!(readl(cg->base + REG_PCI_CONTROL) & REG_PCI_CONTROL_REFCLK_EN1); + regmap_read(cg->map, REG_PCI_CONTROL, &val); + return !!(val & REG_PCI_CONTROL_REFCLK_EN1); } static int en7523_pci_prepare(struct clk_hw *hw) { struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); - void __iomem *np_base = cg->base; - u32 val, mask; + struct regmap *map = cg->map; + u32 mask; /* Need to pull device low before reset */ - val = readl(np_base + REG_PCI_CONTROL); - val &= ~(REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT); - writel(val, np_base + REG_PCI_CONTROL); + regmap_clear_bits(map, REG_PCI_CONTROL, + REG_PCI_CONTROL_PERSTOUT1 | + REG_PCI_CONTROL_PERSTOUT); usleep_range(1000, 2000); /* Enable PCIe port 1 */ - val |= REG_PCI_CONTROL_REFCLK_EN1; - writel(val, np_base + REG_PCI_CONTROL); + regmap_set_bits(map, REG_PCI_CONTROL, + REG_PCI_CONTROL_REFCLK_EN1); usleep_range(1000, 2000); /* Reset to default */ - val = readl(np_base + REG_RESET_CONTROL1); mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 | REG_RESET_CONTROL_PCIEHB; - writel(val & ~mask, np_base + REG_RESET_CONTROL1); + regmap_clear_bits(map, REG_RESET_CONTROL1, mask); usleep_range(1000, 2000); - writel(val | mask, np_base + REG_RESET_CONTROL1); + regmap_set_bits(map, REG_RESET_CONTROL1, mask); msleep(100); - writel(val & ~mask, np_base + REG_RESET_CONTROL1); + regmap_clear_bits(map, REG_RESET_CONTROL1, mask); usleep_range(5000, 10000); /* Release device */ mask = REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT; - val = readl(np_base + REG_PCI_CONTROL); - writel(val & ~mask, np_base + REG_PCI_CONTROL); + regmap_clear_bits(map, REG_PCI_CONTROL, mask); usleep_range(1000, 2000); - writel(val | mask, np_base + REG_PCI_CONTROL); + regmap_set_bits(map, REG_PCI_CONTROL, mask); msleep(250); return 0; @@ -434,16 +436,13 @@ static int en7523_pci_prepare(struct clk_hw *hw) static void en7523_pci_unprepare(struct clk_hw *hw) { struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); - void __iomem *np_base = cg->base; - u32 val; + struct regmap *map = cg->map; - val = readl(np_base + REG_PCI_CONTROL); - val &= ~REG_PCI_CONTROL_REFCLK_EN1; - writel(val, np_base + REG_PCI_CONTROL); + regmap_clear_bits(map, REG_PCI_CONTROL, REG_PCI_CONTROL_REFCLK_EN1); } static struct clk_hw *en7523_register_pcie_clk(struct device *dev, - void __iomem *np_base) + struct regmap *clk_map) { const struct en_clk_soc_data *soc_data = device_get_match_data(dev); struct clk_init_data init = { @@ -456,7 +455,7 @@ static struct clk_hw *en7523_register_pcie_clk(struct device *dev, if (!cg) return NULL; - cg->base = np_base; + cg->map = clk_map; cg->hw.init = &init; if (init.ops->unprepare) @@ -474,21 +473,20 @@ static int en7581_pci_is_enabled(struct clk_hw *hw) u32 val, mask; mask = REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1; - val = readl(cg->base + REG_PCI_CONTROL); + regmap_read(cg->map, REG_PCI_CONTROL, &val); return (val & mask) == mask; } static int en7581_pci_enable(struct clk_hw *hw) { struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); - void __iomem *np_base = cg->base; - u32 val, mask; + struct regmap *map = cg->map; + u32 mask; mask = REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1 | REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT2 | REG_PCI_CONTROL_PERSTOUT; - val = readl(np_base + REG_PCI_CONTROL); - writel(val | mask, np_base + REG_PCI_CONTROL); + regmap_set_bits(map, REG_PCI_CONTROL, mask); return 0; } @@ -496,19 +494,18 @@ static int en7581_pci_enable(struct clk_hw *hw) static void en7581_pci_disable(struct clk_hw *hw) { struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); - void __iomem *np_base = cg->base; - u32 val, mask; + struct regmap *map = cg->map; + u32 mask; mask = REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1 | REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT2 | REG_PCI_CONTROL_PERSTOUT; - val = readl(np_base + REG_PCI_CONTROL); - writel(val & ~mask, np_base + REG_PCI_CONTROL); + regmap_clear_bits(map, REG_PCI_CONTROL, mask); usleep_range(1000, 2000); } static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data, - void __iomem *base, void __iomem *np_base) + struct regmap *map, struct regmap *clk_map) { struct clk_hw *hw; u32 rate; @@ -517,10 +514,12 @@ static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_dat for (i = 0; i < ARRAY_SIZE(en7523_base_clks); i++) { const struct en_clk_desc *desc = &en7523_base_clks[i]; u32 reg = desc->div_reg ? desc->div_reg : desc->base_reg; - u32 val = readl(base + desc->base_reg); + u32 val; + + regmap_read(map, desc->base_reg, &val); rate = en7523_get_base_rate(desc, val); - val = readl(base + reg); + regmap_read(map, reg, &val); rate /= en7523_get_div(desc, val); hw = clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate); @@ -533,30 +532,47 @@ static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_dat clk_data->hws[desc->id] = hw; } - hw = en7523_register_pcie_clk(dev, np_base); + hw = en7523_register_pcie_clk(dev, clk_map); clk_data->hws[EN7523_CLK_PCIE] = hw; } +static const struct regmap_config en7523_clk_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, +}; + static int en7523_clk_hw_init(struct platform_device *pdev, struct clk_hw_onecell_data *clk_data) { void __iomem *base, *np_base; + struct regmap *map, *clk_map; base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) return PTR_ERR(base); + map = devm_regmap_init_mmio(&pdev->dev, base, + &en7523_clk_regmap_config); + if (IS_ERR(map)) + return PTR_ERR(map); + np_base = devm_platform_ioremap_resource(pdev, 1); if (IS_ERR(np_base)) return PTR_ERR(np_base); - en7523_register_clocks(&pdev->dev, clk_data, base, np_base); + clk_map = devm_regmap_init_mmio(&pdev->dev, np_base, + &en7523_clk_regmap_config); + if (IS_ERR(clk_map)) + return PTR_ERR(clk_map); + + en7523_register_clocks(&pdev->dev, clk_data, map, clk_map); return 0; } static void en7581_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data, - struct regmap *map, void __iomem *base) + struct regmap *map, struct regmap *clk_map) { struct clk_hw *hw; u32 rate; @@ -593,7 +609,7 @@ static void en7581_register_clocks(struct device *dev, struct clk_hw_onecell_dat clk_data->hws[desc->id] = hw; } - hw = en7523_register_pcie_clk(dev, base); + hw = en7523_register_pcie_clk(dev, clk_map); clk_data->hws[EN7523_CLK_PCIE] = hw; } @@ -601,15 +617,10 @@ static int en7523_reset_update(struct reset_controller_dev *rcdev, unsigned long id, bool assert) { struct en_rst_data *rst_data = container_of(rcdev, struct en_rst_data, rcdev); - void __iomem *addr = rst_data->base + rst_data->bank_ofs[id / RST_NR_PER_BANK]; - u32 val; + u32 addr = rst_data->bank_ofs[id / RST_NR_PER_BANK]; - val = readl(addr); - if (assert) - val |= BIT(id % RST_NR_PER_BANK); - else - val &= ~BIT(id % RST_NR_PER_BANK); - writel(val, addr); + regmap_update_bits(rst_data->map, addr, BIT(id % RST_NR_PER_BANK), + assert ? BIT(id % RST_NR_PER_BANK) : 0); return 0; } @@ -630,9 +641,11 @@ static int en7523_reset_status(struct reset_controller_dev *rcdev, unsigned long id) { struct en_rst_data *rst_data = container_of(rcdev, struct en_rst_data, rcdev); - void __iomem *addr = rst_data->base + rst_data->bank_ofs[id / RST_NR_PER_BANK]; + u32 addr = rst_data->bank_ofs[id / RST_NR_PER_BANK]; + u32 val; - return !!(readl(addr) & BIT(id % RST_NR_PER_BANK)); + regmap_read(rst_data->map, addr, &val); + return !!(val & BIT(id % RST_NR_PER_BANK)); } static int en7523_reset_xlate(struct reset_controller_dev *rcdev, @@ -652,7 +665,7 @@ static const struct reset_control_ops en7581_reset_ops = { .status = en7523_reset_status, }; -static int en7581_reset_register(struct device *dev, void __iomem *base) +static int en7581_reset_register(struct device *dev, struct regmap *map) { struct en_rst_data *rst_data; @@ -662,7 +675,7 @@ static int en7581_reset_register(struct device *dev, void __iomem *base) rst_data->bank_ofs = en7581_rst_ofs; rst_data->idx_map = en7581_rst_map; - rst_data->base = base; + rst_data->map = map; rst_data->rcdev.nr_resets = ARRAY_SIZE(en7581_rst_map); rst_data->rcdev.of_xlate = en7523_reset_xlate; @@ -678,9 +691,8 @@ static int en7581_reset_register(struct device *dev, void __iomem *base) static int en7581_clk_hw_init(struct platform_device *pdev, struct clk_hw_onecell_data *clk_data) { - struct regmap *map; + struct regmap *map, *clk_map; void __iomem *base; - u32 val; map = syscon_regmap_lookup_by_compatible("airoha,en7581-chip-scu"); if (IS_ERR(map)) @@ -690,15 +702,18 @@ static int en7581_clk_hw_init(struct platform_device *pdev, if (IS_ERR(base)) return PTR_ERR(base); - en7581_register_clocks(&pdev->dev, clk_data, map, base); + clk_map = devm_regmap_init_mmio(&pdev->dev, base, &en7523_clk_regmap_config); + if (IS_ERR(clk_map)) + return PTR_ERR(clk_map); + + en7581_register_clocks(&pdev->dev, clk_data, map, clk_map); - val = readl(base + REG_NP_SCU_SSTR); - val &= ~(REG_PCIE_XSI0_SEL_MASK | REG_PCIE_XSI1_SEL_MASK); - writel(val, base + REG_NP_SCU_SSTR); - val = readl(base + REG_NP_SCU_PCIC); - writel(val | 3, base + REG_NP_SCU_PCIC); + regmap_clear_bits(clk_map, REG_NP_SCU_SSTR, + REG_PCIE_XSI0_SEL_MASK | REG_PCIE_XSI1_SEL_MASK); + regmap_update_bits(clk_map, REG_NP_SCU_PCIC, REG_PCIE_CTRL, + FIELD_PREP(REG_PCIE_CTRL, 3)); - return en7581_reset_register(&pdev->dev, base); + return en7581_reset_register(&pdev->dev, clk_map); } static int en7523_clk_probe(struct platform_device *pdev) From patchwork Sun Mar 9 13:29:34 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 872122 Received: from mail-wr1-f47.google.com (mail-wr1-f47.google.com [209.85.221.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AD9391DDA0E; Sun, 9 Mar 2025 13:30:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[93.34.90.129]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-3912bee262esm11867536f8f.0.2025.03.09.06.30.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Mar 2025 06:30:42 -0700 (PDT) From: Christian Marangi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Christian Marangi , Vinod Koul , Kishon Vijay Abraham I , Matthias Brugger , AngeloGioacchino Del Regno , Greg Kroah-Hartman , Lorenzo Bianconi , Daniel Danzberger , Arnd Bergmann , Linus Walleij , Nikita Shubin , Guo Ren , Yangyu Chen , Ben Hutchings , Felix Fietkau , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-usb@vger.kernel.org, upstream@airoha.com Subject: [PATCH 03/13] dt-bindings: soc: airoha: add SCU SSR Serdes port binding Date: Sun, 9 Mar 2025 14:29:34 +0100 Message-ID: <20250309132959.19045-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250309132959.19045-1-ansuelsmth@gmail.com> References: <20250309132959.19045-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add Airoha AN7581 SCU SSR Serdes port binding to define what mode is supported by each Serdes port. These special binding are needed to identify and provide the port mode from any user driver. These modes are mutually exclusive and driver needs to correctly validate the current mode for the Serdes port in use. Signed-off-by: Christian Marangi --- MAINTAINERS | 6 ++++++ include/dt-bindings/soc/airoha,scu-ssr.h | 24 ++++++++++++++++++++++++ 2 files changed, 30 insertions(+) create mode 100644 include/dt-bindings/soc/airoha,scu-ssr.h diff --git a/MAINTAINERS b/MAINTAINERS index 3eee238c2ea2..d3125268d63f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -736,6 +736,12 @@ F: Documentation/devicetree/bindings/phy/airoha,en7581-pcie-phy.yaml F: drivers/phy/phy-airoha-pcie-regs.h F: drivers/phy/phy-airoha-pcie.c +AIROHA SCU SSR DRIVER +M: Christian Marangi +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Maintained +F: include/dt-bindings/soc/airoha,scu-ssr.h + AIROHA SPI SNFI DRIVER M: Lorenzo Bianconi M: Ray Liu diff --git a/include/dt-bindings/soc/airoha,scu-ssr.h b/include/dt-bindings/soc/airoha,scu-ssr.h new file mode 100644 index 000000000000..b14457c10d77 --- /dev/null +++ b/include/dt-bindings/soc/airoha,scu-ssr.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef __DT_BINDINGS_AIROHA_SCU_SSR_H +#define __DT_BINDINGS_AIROHA_SCU_SSR_H + +/* WiFi1 port can be PCIe0 2 line, PCIe0 1 line or Ethernet (USXGMII/HSGMII) */ +#define AIROHA_SCU_SSR_WIFI1_PCIE0_2LINE 0 +#define AIROHA_SCU_SSR_WIFI1_PCIE0 1 +#define AIROHA_SCU_SSR_WIFI1_ETHERNET 2 + +/* WiFi2 port can be PCIe0 2 line, PCIe1 1 line or Ethernet (USXGMII/HSGMII) */ +#define AIROHA_SCU_SSR_WIFI2_PCIE0_2LINE 0 +#define AIROHA_SCU_SSR_WIFI2_PCIE1 1 +#define AIROHA_SCU_SSR_WIFI2_ETHERNET 2 + +/* USB1 port can be USB 3.0 port or Ethernet (HSGMII) */ +#define AIROHA_SCU_SSR_USB1_USB 0 +#define AIROHA_SCU_SSR_USB1_ETHERNET 1 + +/* USB2 port can be USB 3.0 port or PCIe2 1 line */ +#define AIROHA_SCU_SSR_USB2_USB 0 +#define AIROHA_SCU_SSR_USB2_PCIE2 1 + +#endif /* __DT_BINDINGS_AIROHA_SCU_SSR_H */ From patchwork Sun Mar 9 13:29:36 2025 Content-Type: text/plain; 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[93.34.90.129]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-3912bee262esm11867536f8f.0.2025.03.09.06.30.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Mar 2025 06:30:45 -0700 (PDT) From: Christian Marangi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Christian Marangi , Vinod Koul , Kishon Vijay Abraham I , Matthias Brugger , AngeloGioacchino Del Regno , Greg Kroah-Hartman , Lorenzo Bianconi , Daniel Danzberger , Arnd Bergmann , Linus Walleij , Nikita Shubin , Guo Ren , Yangyu Chen , Ben Hutchings , Felix Fietkau , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-usb@vger.kernel.org, upstream@airoha.com Subject: [PATCH 05/13] dt-bindings: mfd: add Documentation for Airoha EN7581 SCU Date: Sun, 9 Mar 2025 14:29:36 +0100 Message-ID: <20250309132959.19045-6-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250309132959.19045-1-ansuelsmth@gmail.com> References: <20250309132959.19045-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add Documentation for Airoha EN7581 SCU. Airoha EN7581 SoC expose registers to control miscellaneous pheriperals via the SCU (System Controller Unit). Example of these pheriperals are reset-controller, clock-controller, PCIe line speed controller and bits to configure different Serdes ports for USB or Ethernet usage. Signed-off-by: Christian Marangi --- .../mfd/airoha,en7581-scu-sysctl.yaml | 68 +++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/airoha,en7581-scu-sysctl.yaml diff --git a/Documentation/devicetree/bindings/mfd/airoha,en7581-scu-sysctl.yaml b/Documentation/devicetree/bindings/mfd/airoha,en7581-scu-sysctl.yaml new file mode 100644 index 000000000000..d7dc66f912c1 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/airoha,en7581-scu-sysctl.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/airoha,en7581-scu-sysctl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha EN7581 SCU (System Controller Unit) + +maintainers: + - Christian Marangi + +description: + Airoha EN7581 SoC expose registers to control miscellaneous + pheriperals via the SCU (System Controller Unit). + + Example of these pheriperals are reset-controller, clock-controller, + PCIe line speed controller and bits to configure different Serdes ports + for USB or Ethernet usage. + +properties: + compatible: + items: + - const: airoha,en7581-scu-sysctl + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + clock-controller: + type: object + $ref: /schemas/clock/airoha,en7523-scu.yaml + description: + Child node definition for EN7581 Clock controller + + system-controller: + type: object + $ref: /schemas/soc/airoha/airoha,an7581-scu-ssr.yaml + description: + Child node definition for EN7581 System Status Register + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + + system-controller@1fb00000 { + compatible = "airoha,en7581-scu-sysctl", "syscon", "simple-mfd"; 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[93.34.90.129]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-3912bee262esm11867536f8f.0.2025.03.09.06.30.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Mar 2025 06:30:49 -0700 (PDT) From: Christian Marangi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Christian Marangi , Vinod Koul , Kishon Vijay Abraham I , Matthias Brugger , AngeloGioacchino Del Regno , Greg Kroah-Hartman , Lorenzo Bianconi , Daniel Danzberger , Arnd Bergmann , Linus Walleij , Nikita Shubin , Guo Ren , Yangyu Chen , Ben Hutchings , Felix Fietkau , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-usb@vger.kernel.org, upstream@airoha.com Subject: [PATCH 07/13] clk: en7523: support getting regmap from parent node for EN7581 Date: Sun, 9 Mar 2025 14:29:38 +0100 Message-ID: <20250309132959.19045-8-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250309132959.19045-1-ansuelsmth@gmail.com> References: <20250309132959.19045-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add support for getting clock regmap from parent node for Airoha EN7581. This is needed to support new implementation with SCU (System Controller Unit) as an MFD and clock-controller node as a child node of it. In such implementation the register regmap is provided as a syscon from the parent node. Signed-off-by: Christian Marangi --- drivers/clk/clk-en7523.c | 25 ++++++++++++++++--------- 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index 2a74bc8fed24..29cb7ccea29a 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -665,6 +665,7 @@ static int en7581_clk_hw_init(struct platform_device *pdev, const struct en_clk_soc_data *soc_data, struct clk_hw_onecell_data *clk_data) { + struct device *dev = &pdev->dev; struct regmap *map, *clk_map; void __iomem *base; @@ -672,22 +673,28 @@ static int en7581_clk_hw_init(struct platform_device *pdev, if (IS_ERR(map)) return PTR_ERR(map); - base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - clk_map = devm_regmap_init_mmio(&pdev->dev, base, &en7523_clk_regmap_config); - if (IS_ERR(clk_map)) - return PTR_ERR(clk_map); + if (of_property_present(dev->of_node, "reg")) { + base = devm_platform_ioremap_resource(pdev, 0); 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[93.34.90.129]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-3912bee262esm11867536f8f.0.2025.03.09.06.30.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Mar 2025 06:30:52 -0700 (PDT) From: Christian Marangi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Christian Marangi , Vinod Koul , Kishon Vijay Abraham I , Matthias Brugger , AngeloGioacchino Del Regno , Greg Kroah-Hartman , Lorenzo Bianconi , Daniel Danzberger , Arnd Bergmann , Linus Walleij , Nikita Shubin , Guo Ren , Yangyu Chen , Ben Hutchings , Felix Fietkau , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-usb@vger.kernel.org, upstream@airoha.com Subject: [PATCH 09/13] dt-bindings: phy: Add documentation for Airoha AN7581 USB PHY Date: Sun, 9 Mar 2025 14:29:40 +0100 Message-ID: <20250309132959.19045-10-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250309132959.19045-1-ansuelsmth@gmail.com> References: <20250309132959.19045-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add documentation for Airoha AN7581 USB PHY that describe the USB PHY for the USB controller. Airoha AN7581 SoC support a maximum of 2 USB port. The USB 2.0 mode is always supported. The USB 3.0 mode is optional and depends on the Serdes mode currently configured on the system for the USB port. If USB 3.0 node is defined, then airoha,scu-ssr property is required for Serdes mode validation. Signed-off-by: Christian Marangi --- .../bindings/phy/airoha,an7581-usb-phy.yaml | 106 ++++++++++++++++++ MAINTAINERS | 6 + 2 files changed, 112 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/airoha,an7581-usb-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/airoha,an7581-usb-phy.yaml b/Documentation/devicetree/bindings/phy/airoha,an7581-usb-phy.yaml new file mode 100644 index 000000000000..39127cfb63a7 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/airoha,an7581-usb-phy.yaml @@ -0,0 +1,106 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/airoha,an7581-usb-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha AN7581 SoC USB PHY + +maintainers: + - Christian Marangi + +description: > + The Airoha AN7581 SoC USB PHY describes the USB PHY for the USB controller. + + Airoha AN7581 SoC support a maximum of 2 USB port. The USB 2.0 mode is + always supported. The USB 3.0 mode is optional and depends on the Serdes + mode currently configured on the system for the USB port. If USB 3.0 node + is defined, then airoha,scu-ssr property is required for Serdes mode + validation. + +properties: + compatible: + const: airoha,an7581-usb-phy + + reg: + maxItems: 1 + + airoha,port-id: + description: Describe the physical port this USB PHY refer to. A dedicated + osciallator is used for each port for the USB 2.0 Slew Rate calibration. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + airoha,scu-ssr: + description: Phandle to the SCU SSR node for USB 3.0 Serdes mode validation. + $ref: /schemas/types.yaml#/definitions/phandle + + usb2-phy: + type: object + + properties: + '#phy-cells': + const: 1 + + required: + - '#phy-cells' + + additionalProperties: false + + usb3-phy: + type: object + + properties: + '#phy-cells': + const: 1 + + required: + - '#phy-cells' + + additionalProperties: false + +required: + - compatible + - reg + - airoha,port-id + - usb2-phy + +if: + required: + - usb3-phy +then: + required: + - airoha,scu-ssr + +additionalProperties: false + +examples: + - | + phy@1fac0000 { + compatible = "airoha,an7581-usb-phy"; + reg = <0x1fac0000 0x10000>; + + airoha,port-id = <0>; + airoha,scu-ssr = <&scu_ssr>; + + usb0_u2: usb2-phy { + #phy-cells = <1>; + }; + + usb0_u3: usb3-phy { + #phy-cells = <1>; + }; + }; + + - | + phy@1fae0000 { + compatible = "airoha,an7581-usb-phy"; + reg = <0x1fae0000 0x10000>; + + airoha,port-id = <1>; + + usb1_u2: usb2-phy { + #phy-cells = <1>; + }; + }; + diff --git a/MAINTAINERS b/MAINTAINERS index fe34c80b8d52..c2dd385e9165 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -753,6 +753,12 @@ S: Maintained F: Documentation/devicetree/bindings/spi/airoha,en7581-snand.yaml F: drivers/spi/spi-airoha-snfi.c +AIROHA USB PHY DRIVER +M: Christian Marangi +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Maintained +F: Documentation/devicetree/bindings/phy/airoha,an7581-usb-phy.yam + AIRSPY MEDIA DRIVER L: linux-media@vger.kernel.org S: Orphan From patchwork Sun Mar 9 13:29:42 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 872118 Received: from mail-wr1-f47.google.com (mail-wr1-f47.google.com [209.85.221.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D57C11F4CA1; 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[93.34.90.129]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-3912bee262esm11867536f8f.0.2025.03.09.06.30.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Mar 2025 06:30:55 -0700 (PDT) From: Christian Marangi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Christian Marangi , Vinod Koul , Kishon Vijay Abraham I , Matthias Brugger , AngeloGioacchino Del Regno , Greg Kroah-Hartman , Lorenzo Bianconi , Daniel Danzberger , Arnd Bergmann , Linus Walleij , Nikita Shubin , Guo Ren , Yangyu Chen , Ben Hutchings , Felix Fietkau , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-usb@vger.kernel.org, upstream@airoha.com Subject: [PATCH 11/13] usb: host: add ARCH_AIROHA in XHCI MTK dependency Date: Sun, 9 Mar 2025 14:29:42 +0100 Message-ID: <20250309132959.19045-12-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250309132959.19045-1-ansuelsmth@gmail.com> References: <20250309132959.19045-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Airoha SoC use the same register map a logic of the Mediatek xHCI driver, hence add it to the dependency list to permit compilation also on this ARCH. Signed-off-by: Christian Marangi --- drivers/usb/host/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index d011d6c753ed..9d8626f36ca6 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -71,7 +71,7 @@ config USB_XHCI_HISTB config USB_XHCI_MTK tristate "xHCI support for MediaTek SoCs" select MFD_SYSCON - depends on (MIPS && SOC_MT7621) || ARCH_MEDIATEK || COMPILE_TEST + depends on (MIPS && SOC_MT7621) || ARCH_MEDIATEK || ARCH_AIROHA || COMPILE_TEST help Say 'Y' to enable the support for the xHCI host controller found in MediaTek SoCs. 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[93.34.90.129]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-3912bee262esm11867536f8f.0.2025.03.09.06.30.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Mar 2025 06:30:58 -0700 (PDT) From: Christian Marangi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Christian Marangi , Vinod Koul , Kishon Vijay Abraham I , Matthias Brugger , AngeloGioacchino Del Regno , Greg Kroah-Hartman , Lorenzo Bianconi , Daniel Danzberger , Arnd Bergmann , Linus Walleij , Nikita Shubin , Guo Ren , Yangyu Chen , Ben Hutchings , Felix Fietkau , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-usb@vger.kernel.org, upstream@airoha.com Subject: [PATCH 13/13] arm64: dts: airoha: en7581: add USB and SCU SSR nodes Date: Sun, 9 Mar 2025 14:29:44 +0100 Message-ID: <20250309132959.19045-14-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250309132959.19045-1-ansuelsmth@gmail.com> References: <20250309132959.19045-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add SCU SSR and USB nodes required for USB support of Airoha EN7581. SCU SSR node is required to read and configure the current Serdes mode of the USB PHYs. Signed-off-by: Christian Marangi --- arch/arm64/boot/dts/airoha/en7581.dtsi | 61 ++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/arch/arm64/boot/dts/airoha/en7581.dtsi b/arch/arm64/boot/dts/airoha/en7581.dtsi index dfc12fa99748..5975da11ace0 100644 --- a/arch/arm64/boot/dts/airoha/en7581.dtsi +++ b/arch/arm64/boot/dts/airoha/en7581.dtsi @@ -3,6 +3,7 @@ #include #include #include +#include #include / { @@ -183,6 +184,10 @@ scuclk: clock-controller { #clock-cells = <1>; #reset-cells = <1>; }; + + scu_ssr: system-controller { + compatible = "airoha,an7581-scu-ssr"; + }; }; uart1: serial@1fbf0000 { @@ -200,6 +205,62 @@ rng@1faa1000 { interrupts = ; }; + usb0: usb@1fab0000 { + compatible = "mediatek,mtk-xhci"; + reg = <0x0 0x1fab0000 0x0 0x3e00>, + <0x0 0x1fab3e00 0x0 0x100>; + reg-names = "mac", "ippc"; + interrupts = ; + + phys = <&usb0_u2 PHY_TYPE_USB2>, <&usb0_u3 PHY_TYPE_USB3>; + + status = "disabled"; + }; + + phy@1fac0000 { + compatible = "airoha,an7581-usb-phy"; + reg = <0x0 0x1fac0000 0x0 0x10000>; + + airoha,port-id = <0>; + airoha,scu-ssr = <&scu_ssr>; + + usb0_u2: usb2-phy { + #phy-cells = <1>; + }; + + usb0_u3: usb3-phy { + #phy-cells = <1>; + }; + }; + + usb1: usb@1fad0000 { + compatible = "mediatek,mtk-xhci"; + reg = <0x0 0x1fad0000 0x0 0x3e00>, + <0x0 0x1fad3e00 0x0 0x100>; + reg-names = "mac", "ippc"; + interrupts = ; + + phys = <&usb1_u2 PHY_TYPE_USB2>, <&usb0_u3 PHY_TYPE_USB3>; + + status = "disabled"; + }; + + phy@1fae0000 { + compatible = "airoha,an7581-usb-phy"; + reg = <0x0 0x1fae0000 0x0 0x10000>; + + airoha,port-id = <1>; + airoha,scu-ssr = <&scu_ssr>; + + usb1_u2: usb2-phy { + #phy-cells = <1>; + }; + + usb1_u3: usb3-phy { + #phy-cells = <1>; + }; + }; + system-controller@1fbf0200 { compatible = "airoha,en7581-gpio-sysctl", "syscon", "simple-mfd";