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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-395cb7eb93csm5437923f8f.86.2025.03.14.06.16.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Mar 2025 06:16:39 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/17] target/arm: Move A32_BANKED_REG_{GET, SET} macros to cpregs.h Date: Fri, 14 Mar 2025 13:16:21 +0000 Message-ID: <20250314131637.371866-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250314131637.371866-1-peter.maydell@linaro.org> References: <20250314131637.371866-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The A32_BANKED_REG_{GET,SET} macros are only used inside target/arm; move their definitions to cpregs.h. There's no need to have them defined in all the code that includes cpu.h. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpregs.h | 28 ++++++++++++++++++++++++++++ target/arm/cpu.h | 27 --------------------------- 2 files changed, 28 insertions(+), 27 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 52377c6eb50..2183de8eda6 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -1157,4 +1157,32 @@ static inline bool arm_cpreg_traps_in_nv(const ARMCPRegInfo *ri) return ri->opc1 == 4 || ri->opc1 == 5; } +/* Macros for accessing a specified CP register bank */ +#define A32_BANKED_REG_GET(_env, _regname, _secure) \ + ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) + +#define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ + do { \ + if (_secure) { \ + (_env)->cp15._regname##_s = (_val); \ + } else { \ + (_env)->cp15._regname##_ns = (_val); \ + } \ + } while (0) + +/* + * Macros for automatically accessing a specific CP register bank depending on + * the current secure state of the system. These macros are not intended for + * supporting instruction translation reads/writes as these are dependent + * solely on the SCR.NS bit and not the mode. + */ +#define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ + A32_BANKED_REG_GET((_env), _regname, \ + (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) + +#define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ + A32_BANKED_REG_SET((_env), _regname, \ + (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ + (_val)) + #endif /* TARGET_ARM_CPREGS_H */ diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8f52380c88c..15d3a79b0af 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2684,33 +2684,6 @@ static inline bool access_secure_reg(CPUARMState *env) return ret; } -/* Macros for accessing a specified CP register bank */ -#define A32_BANKED_REG_GET(_env, _regname, _secure) \ - ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) - -#define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ - do { \ - if (_secure) { \ - (_env)->cp15._regname##_s = (_val); \ - } else { \ - (_env)->cp15._regname##_ns = (_val); \ - } \ - } while (0) - -/* Macros for automatically accessing a specific CP register bank depending on - * the current secure state of the system. These macros are not intended for - * supporting instruction translation reads/writes as these are dependent - * solely on the SCR.NS bit and not the mode. - */ -#define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ - A32_BANKED_REG_GET((_env), _regname, \ - (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) - -#define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ - A32_BANKED_REG_SET((_env), _regname, \ - (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ - (_val)) - uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, uint32_t cur_el, bool secure); From patchwork Fri Mar 14 13:16:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 873443 Delivered-To: patch@linaro.org Received: by 2002:a5d:4308:0:b0:38f:210b:807b with SMTP id h8csp702633wrq; Fri, 14 Mar 2025 06:18:42 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWH11bRZtE4PRlxFroqvy2sPLg8xrTxZQOdgT+VfG+BxItp+x7EPE4/v7PKocD3/3IpbXVL5g==@linaro.org X-Google-Smtp-Source: AGHT+IHvIZ91fTPwdKas1ejoQk7QqKMd2gwb18IkVOADTNDnFfzTESVsrhZwj1AQUbuBLd90ukvT X-Received: by 2002:a05:622a:95:b0:476:8595:fa09 with SMTP id d75a77b69052e-476c81c331cmr26136771cf.40.1741958321938; Fri, 14 Mar 2025 06:18:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1741958321; cv=none; d=google.com; s=arc-20240605; b=kfi1eWL7rbDaLR/RE2x1CmHmwz43WRMKjsU1sPC1Yr4ARxnMzssyY063CViThqntC2 Nvm2+squV8ku/hmB/s0ZjA0I95wBcuEXfE8Cfh2n1fb9L+5HcdTK7sHMxVvR5p9937wy vJOmK+Q00rIxpdY1MnPxLMp+WfSpKrUKowadb8SZtThx6t94AraCdHh0Y7xjBRtofJYF ks+ccbbukwFH4VkWnZCLm3jYwGk1WhqHjswE2IDRMmVn5p/FNHkAXNcogS2Hc+03Jhd7 AL4J9kFkspLlIiazRxEAaVUbNDztxG17lwbc+gWWQf5EoH77zaXYYulhCFledARPWM6n eP/A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=fHuKfDxA2I3IuqcU9csI6nL0wPvBFIcds8Iwt3qt8Yw=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=UiPdcJu4tg7O9hsiWBJ3pw5TLGRd8s8Mve/ya+1ShkFFtcRWxfAmvRK6EeSg+trSRH jmUc8Fn0sctVd2qWBUGRFVFa+aAdTfExFdL7tRzE40kWYjFzsT6fFD7YQ3KbsLdFDNHH vsUdbrmHCw37YviY9hlIjAD2JS7PMtRvz0EudUpR0d08qfHz3RWZ0ciVBsAzhqRAGjtW 1ru6pqn3Ogtd3W8iNG0QtmWxQLuwD/VrBe/8wVpp6/WABJsrY6HD91ITLUFEYzGo7zeB ZpZdKfSOk5tVMN7W6+/mYwO4L2ApNRbpJgXe5DUwCXdO8mjL93f4jac44Ua0ddavgFOU +sQA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rQAzfUs2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-395cb7eb93csm5437923f8f.86.2025.03.14.06.16.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Mar 2025 06:16:40 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/17] target/arm: Un-inline access_secure_reg() Date: Fri, 14 Mar 2025 13:16:22 +0000 Message-ID: <20250314131637.371866-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250314131637.371866-1-peter.maydell@linaro.org> References: <20250314131637.371866-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We would like to move arm_el_is_aa64() to internals.h; however, it is used by access_secure_reg(). Make that function not be inline, so that it can stay in cpu.h. access_secure_reg() is used only in two places: * in hflags.c * in the user-mode arm emulators, to decide whether to store the TLS value in the secure or non-secure banked field The second of these is not on a super-hot path that would care about the inlining (and incidentally will always use the NS banked field because our user-mode CPUs never set ARM_FEATURE_EL3); put the definition of access_secure_reg() in hflags.c, near its only use inside target/arm. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 12 +++--------- target/arm/tcg/hflags.c | 9 +++++++++ 2 files changed, 12 insertions(+), 9 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 15d3a79b0af..12d2706f2b5 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2668,21 +2668,15 @@ static inline bool arm_el_is_aa64(CPUARMState *env, int el) return aa64; } -/* Function for determining whether guest cp register reads and writes should +/* + * Function for determining whether guest cp register reads and writes should * access the secure or non-secure bank of a cp register. When EL3 is * operating in AArch32 state, the NS-bit determines whether the secure * instance of a cp register should be used. When EL3 is AArch64 (or if * it doesn't exist at all) then there is no register banking, and all * accesses are to the non-secure version. */ -static inline bool access_secure_reg(CPUARMState *env) -{ - bool ret = (arm_feature(env, ARM_FEATURE_EL3) && - !arm_el_is_aa64(env, 3) && - !(env->cp15.scr_el3 & SCR_NS)); - - return ret; -} +bool access_secure_reg(CPUARMState *env); uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, uint32_t cur_el, bool secure); diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c index 9e6a1869f94..8d79b8b7ae1 100644 --- a/target/arm/tcg/hflags.c +++ b/target/arm/tcg/hflags.c @@ -63,6 +63,15 @@ static bool aprofile_require_alignment(CPUARMState *env, int el, uint64_t sctlr) #endif } +bool access_secure_reg(CPUARMState *env) +{ + bool ret = (arm_feature(env, ARM_FEATURE_EL3) && + !arm_el_is_aa64(env, 3) && + !(env->cp15.scr_el3 & SCR_NS)); + + return ret; +} + static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el, ARMMMUIdx mmu_idx, CPUARMTBFlags flags) From patchwork Fri Mar 14 13:16:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 873436 Delivered-To: patch@linaro.org Received: by 2002:a5d:4308:0:b0:38f:210b:807b with SMTP id h8csp702078wrq; Fri, 14 Mar 2025 06:17:40 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXsepDgAaPK16R6/0BCa7vIE5gU5Ads/xLOseKCyWFXSlBuLUWaxJmJxD/N8iZBi4jD8rcGcA==@linaro.org X-Google-Smtp-Source: AGHT+IHMJbV2LVXFJh7634hR8Iqetr7sUM+vD33ruHngKRiys1lG6XH2dOm8zAG4qLFJbWaW1QL4 X-Received: by 2002:ac8:5ad3:0:b0:476:add4:d2ac with SMTP id d75a77b69052e-476c813104amr21993851cf.7.1741958260173; Fri, 14 Mar 2025 06:17:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1741958260; cv=none; d=google.com; s=arc-20240605; b=B4jQ4oukRPk2xXXoLhyY1EgEJLcZQhyEJUcnm/R3fBIaL5dh0ECPcLwq83p/aBHcSQ Ed/ANzO9z3DQvMgYkrP8k0ZO6iToY5dZTfr7ixQhlk6FWjz1yjYc9p4APBuklejhCVJC 1cIVsCtO5wX5dfZEJMNJr2vKWtZMu747GUeXTU/LxT4yiaA0FrQ/VTe9x6B5eivQd8wD 0PNr8rSm35t9+32J5eArKq7LlgN7sYSyOFl5xcQgHYQhtCyw9cJt11fG8R0MqAVcNhOP C1CKQGp1SQl9rR8A5nZ67VfAZGgwv1kvkOv4lvl52V+iyrfzyyx1dI2r/ba3OjKOHoKt 5AVQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=6J/9ANglDaXRI5YIXs5GXgTFWRT7etnt/oN9SrKqW4s=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=C50KUdxuyKdOCg0KexO4fM0Jju2T0Fh5vAkqgkYWL6QToZN6nO8xDVSKo6ANKtUe06 MKaJKjIWZRkTQ9+bXDuGAxk13X3eYosTHZDkmolGMNoCL4lV2z0qZdywncoj4mHxZdin +z0CiS6bb1bNbDBgt6vmv7XzkjFacAd670mFN2pD59cxpJaSJpsL9n9mc7mNkGcyz+fS VdxLAbB6/TOKZddkn84A2EM32XPlgp2Ehw0nBwTUnDpgD8tzxAblFpwXlp3r+g5yZ9a8 smvWV7WwyL5r4MUC/JyZLuTBCfZIEqa1qa9hk01TZSLtic0NT9GNAO9zLHENjM721J0j PUEA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NaBsHhaA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-395cb7eb93csm5437923f8f.86.2025.03.14.06.16.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Mar 2025 06:16:42 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/17] linux-user/aarch64: Remove unused get/put_user macros Date: Fri, 14 Mar 2025 13:16:23 +0000 Message-ID: <20250314131637.371866-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250314131637.371866-1-peter.maydell@linaro.org> References: <20250314131637.371866-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org At the top of linux-user/aarch64/cpu_loop.c we define a set of macros for reading and writing data and code words, but we never use these macros. Delete them. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- linux-user/aarch64/cpu_loop.c | 48 ----------------------------------- 1 file changed, 48 deletions(-) diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index c5d8a483a3f..fea43cefa6b 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -27,54 +27,6 @@ #include "target/arm/syndrome.h" #include "target/arm/cpu-features.h" -#define get_user_code_u32(x, gaddr, env) \ - ({ abi_long __r = get_user_u32((x), (gaddr)); \ - if (!__r && bswap_code(arm_sctlr_b(env))) { \ - (x) = bswap32(x); \ - } \ - __r; \ - }) - -#define get_user_code_u16(x, gaddr, env) \ - ({ abi_long __r = get_user_u16((x), (gaddr)); \ - if (!__r && bswap_code(arm_sctlr_b(env))) { \ - (x) = bswap16(x); \ - } \ - __r; \ - }) - -#define get_user_data_u32(x, gaddr, env) \ - ({ abi_long __r = get_user_u32((x), (gaddr)); \ - if (!__r && arm_cpu_bswap_data(env)) { \ - (x) = bswap32(x); \ - } \ - __r; \ - }) - -#define get_user_data_u16(x, gaddr, env) \ - ({ abi_long __r = get_user_u16((x), (gaddr)); \ - if (!__r && arm_cpu_bswap_data(env)) { \ - (x) = bswap16(x); \ - } \ - __r; \ - }) - -#define put_user_data_u32(x, gaddr, env) \ - ({ typeof(x) __x = (x); \ - if (arm_cpu_bswap_data(env)) { \ - __x = bswap32(__x); \ - } \ - put_user_u32(__x, (gaddr)); \ - }) - -#define put_user_data_u16(x, gaddr, env) \ - ({ typeof(x) __x = (x); \ - if (arm_cpu_bswap_data(env)) { \ - __x = bswap16(__x); \ - } \ - put_user_u16(__x, (gaddr)); \ - }) - /* AArch64 main loop */ void cpu_loop(CPUARMState *env) { From patchwork Fri Mar 14 13:16:24 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 873440 Delivered-To: patch@linaro.org Received: by 2002:a5d:4308:0:b0:38f:210b:807b with SMTP id h8csp702339wrq; Fri, 14 Mar 2025 06:18:10 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXX7TsLwFJP9wSpjDbsS7C4oE3k8l4h4s3WoqGGAQGRjOKpFC0HlfLKrZf572MW7rNUVU0j3w==@linaro.org X-Google-Smtp-Source: AGHT+IF+oZoMKSUlajSNM1IHOqUw5783SPWv23hZ83olO8nW1tZOeOtXgZ0ltYUIt2ySQyW7M33d X-Received: by 2002:ac8:5954:0:b0:472:bbb:1bab with SMTP id d75a77b69052e-476c8145813mr31005971cf.24.1741958289926; Fri, 14 Mar 2025 06:18:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1741958289; cv=none; d=google.com; s=arc-20240605; b=DZ9RW574Bsth8aMFroBjS/sm/H+JT0jM+4Bcd4GEsX3qiHdSh397JSQg7Rk4HxVdcb L8R5Jrdn4T2F1czfAHXAOViWq6Wqx41BA7KQYTAjKpBRGzAtLWZ8q/to8qHJTsSWSC9U FMIQMdM4Gsutht0rJ1I9BrqY3fjvP8cTo7wrGOMpLUFdHxg5zawmySNI/Iw+mnn0PgQz 87AFshcjYZ+v7D5+FUdSBrShizH5wsOUbrD1bpPpqSvdxgA+q+N7O4eh71eeNotqB5+s w91j+GzQpU2Xt07f+Y8SZvXrrpp1QOw/r7lyo8PF/Kpwb/+ZKzpEz9NFZGP2hF5VIuQm Pv4g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=5P8dI0LglzsFCzU+xe5Ql8suIL1Ju80i0bFOQatlqoo=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=dolYZ7ethwGJ0oO1E9qd4dX6AhhiBjvf+eijUhK3ygwJblifxW3VFsDYqUpkHGKZuX m/5DFSH2dpQUSeCxUvQxB4+rLR5bdqMCzYu8Xxvqtyh9loojcYUKjjJ+27h2ABkYyujG fHMfzZ8AWSZxgfp5+PwsF6UE/EpWBp4xjor/4EKv+RwRJADsgGOcDa8+qGXg4KkeQmEt gzOtYHgLBmCxem0dJSoEwBHIH8A0h38nY2H2G7johNdFgPLmF0qKZZG92QJcMACd76Xw yC2jc/Zt34w5gB3UndsTSF7XVAdsvZfDyUPb8Vyo+YQA97V7Txv1zTUT550h62Ga3U4s yNgQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CQrpiDW8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-395cb7eb93csm5437923f8f.86.2025.03.14.06.16.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Mar 2025 06:16:43 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/17] linux-user/arm: Remove unused get_put_user macros Date: Fri, 14 Mar 2025 13:16:24 +0000 Message-ID: <20250314131637.371866-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250314131637.371866-1-peter.maydell@linaro.org> References: <20250314131637.371866-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In linux-user/arm/cpu_loop.c we define a full set of get/put macros for both code and data (since the endianness handling is different between the two). However the only one we actually use is get_user_code_u32(). Remove the rest. We leave a comment noting how data-side accesses should be handled for big-endian, because that's a subtle point and we just removed the macros that were effectively documenting it. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- linux-user/arm/cpu_loop.c | 43 ++++----------------------------------- 1 file changed, 4 insertions(+), 39 deletions(-) diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index 10d8561f9b9..7416e3216ea 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -36,45 +36,10 @@ __r; \ }) -#define get_user_code_u16(x, gaddr, env) \ - ({ abi_long __r = get_user_u16((x), (gaddr)); \ - if (!__r && bswap_code(arm_sctlr_b(env))) { \ - (x) = bswap16(x); \ - } \ - __r; \ - }) - -#define get_user_data_u32(x, gaddr, env) \ - ({ abi_long __r = get_user_u32((x), (gaddr)); \ - if (!__r && arm_cpu_bswap_data(env)) { \ - (x) = bswap32(x); \ - } \ - __r; \ - }) - -#define get_user_data_u16(x, gaddr, env) \ - ({ abi_long __r = get_user_u16((x), (gaddr)); \ - if (!__r && arm_cpu_bswap_data(env)) { \ - (x) = bswap16(x); \ - } \ - __r; \ - }) - -#define put_user_data_u32(x, gaddr, env) \ - ({ typeof(x) __x = (x); \ - if (arm_cpu_bswap_data(env)) { \ - __x = bswap32(__x); \ - } \ - put_user_u32(__x, (gaddr)); \ - }) - -#define put_user_data_u16(x, gaddr, env) \ - ({ typeof(x) __x = (x); \ - if (arm_cpu_bswap_data(env)) { \ - __x = bswap16(__x); \ - } \ - put_user_u16(__x, (gaddr)); \ - }) +/* + * Note that if we need to do data accesses here, they should do a + * bswap if arm_cpu_bswap_data() returns true. + */ /* * Similar to code in accel/tcg/user-exec.c, but outside the execution loop. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-395cb7eb93csm5437923f8f.86.2025.03.14.06.16.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Mar 2025 06:16:44 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/17] target/arm: Move arm_cpu_data_is_big_endian() etc to internals.h Date: Fri, 14 Mar 2025 13:16:25 +0000 Message-ID: <20250314131637.371866-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250314131637.371866-1-peter.maydell@linaro.org> References: <20250314131637.371866-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The arm_cpu_data_is_big_endian() and related functions are now used only in target/arm; they can be moved to internals.h. The motivation here is that we would like to move arm_current_el() to internals.h. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 48 ------------------------------------------ target/arm/internals.h | 48 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+), 48 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 12d2706f2b5..8a59f705167 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3032,47 +3032,6 @@ static inline bool arm_sctlr_b(CPUARMState *env) uint64_t arm_sctlr(CPUARMState *env, int el); -static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env, - bool sctlr_b) -{ -#ifdef CONFIG_USER_ONLY - /* - * In system mode, BE32 is modelled in line with the - * architecture (as word-invariant big-endianness), where loads - * and stores are done little endian but from addresses which - * are adjusted by XORing with the appropriate constant. So the - * endianness to use for the raw data access is not affected by - * SCTLR.B. - * In user mode, however, we model BE32 as byte-invariant - * big-endianness (because user-only code cannot tell the - * difference), and so we need to use a data access endianness - * that depends on SCTLR.B. - */ - if (sctlr_b) { - return true; - } -#endif - /* In 32bit endianness is determined by looking at CPSR's E bit */ - return env->uncached_cpsr & CPSR_E; -} - -static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr) -{ - return sctlr & (el ? SCTLR_EE : SCTLR_E0E); -} - -/* Return true if the processor is in big-endian mode. */ -static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) -{ - if (!is_a64(env)) { - return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env)); - } else { - int cur_el = arm_current_el(env); - uint64_t sctlr = arm_sctlr(env, cur_el); - return arm_cpu_data_is_big_endian_a64(cur_el, sctlr); - } -} - #include "exec/cpu-all.h" /* @@ -3258,13 +3217,6 @@ static inline bool bswap_code(bool sctlr_b) #endif } -#ifdef CONFIG_USER_ONLY -static inline bool arm_cpu_bswap_data(CPUARMState *env) -{ - return TARGET_BIG_ENDIAN ^ arm_cpu_data_is_big_endian(env); -} -#endif - void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc, uint64_t *cs_base, uint32_t *flags); diff --git a/target/arm/internals.h b/target/arm/internals.h index bb962389192..c2c59e60309 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -392,6 +392,54 @@ static inline FloatRoundMode arm_rmode_to_sf(ARMFPRounding rmode) return arm_rmode_to_sf_map[rmode]; } +static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env, + bool sctlr_b) +{ +#ifdef CONFIG_USER_ONLY + /* + * In system mode, BE32 is modelled in line with the + * architecture (as word-invariant big-endianness), where loads + * and stores are done little endian but from addresses which + * are adjusted by XORing with the appropriate constant. So the + * endianness to use for the raw data access is not affected by + * SCTLR.B. + * In user mode, however, we model BE32 as byte-invariant + * big-endianness (because user-only code cannot tell the + * difference), and so we need to use a data access endianness + * that depends on SCTLR.B. + */ + if (sctlr_b) { + return true; + } +#endif + /* In 32bit endianness is determined by looking at CPSR's E bit */ + return env->uncached_cpsr & CPSR_E; +} + +static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr) +{ + return sctlr & (el ? SCTLR_EE : SCTLR_E0E); +} + +/* Return true if the processor is in big-endian mode. */ +static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) +{ + if (!is_a64(env)) { + return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env)); + } else { + int cur_el = arm_current_el(env); + uint64_t sctlr = arm_sctlr(env, cur_el); + return arm_cpu_data_is_big_endian_a64(cur_el, sctlr); + } +} + +#ifdef CONFIG_USER_ONLY +static inline bool arm_cpu_bswap_data(CPUARMState *env) +{ + return TARGET_BIG_ENDIAN ^ arm_cpu_data_is_big_endian(env); +} +#endif + static inline void aarch64_save_sp(CPUARMState *env, int el) { if (env->pstate & PSTATE_SP) { From patchwork Fri Mar 14 13:16:26 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 873437 Delivered-To: patch@linaro.org Received: by 2002:a5d:4308:0:b0:38f:210b:807b with SMTP id h8csp702190wrq; Fri, 14 Mar 2025 06:17:52 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUIikLs/ckQtszgzmZuCzx9UdtewUAKNCYgmEtjsSjf73eEf9WUMB5ApZNzjyw4z2DxX7LOCg==@linaro.org X-Google-Smtp-Source: AGHT+IEXXQPqkCwFrIQbU9FoJBG/O+W8i9DK1JnOKkGP7FuI8/J5ak5rVlruOolCvBwpbk9yZ8G8 X-Received: by 2002:a05:622a:15c6:b0:476:a895:7e87 with SMTP id d75a77b69052e-476c81e9075mr32989811cf.48.1741958272588; Fri, 14 Mar 2025 06:17:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1741958272; cv=none; d=google.com; s=arc-20240605; b=UjbFhlgCfVRD/TQuzu2isqmok8OTiGE54n/wZ110IMrlaMmVdEYWY0odHd80AcIwKZ jw4IJgh7BxIrWBTGI19IJljY+5YXmd4D1NfnSWuR/kf2BSQCVKoZABNKOr/su+yktAbv on3W0zpA8UP0ijJVb3k6G3kxkQwcOmFbmcbutO7oyEXnhhkC92BfksOayjmYMcGfAtiZ CPUyp6CmyblNYzDMJ22o4qey0fKeHIMEoWHTN4w253JZCgzYwvuyO08hwrttxrSNH95X 1DQ9t4YV+pCSiOAfbJOXEQgfJX8uEC1aQiCvARvgpLVasrABiqBTLWbriyZjW+/d90AU vbrQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=JoCJlJB7bw5C9PTN/h6RLrq6shwMf+RftAhK7d1SWBw=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=FpPN1lu+yx66x4da8ReYeklBkdrHx81p9EfA7DU4VyEkFayankPd2cKlxwiyQeeczD Ho2WxO5NsQMpYi3FLeCT3c19nNnU4N8Yy6l8sLki6ZZiPZjALQFTXVjA2HbTk9kGJrWy nOXiv4RF8kaDkQPRclPUTg/WhMFV5/mAeOSik0tNPVPB8PuyT7eKTi2wUQdMZH9QjVK9 gAsuG8r20NEJYgeBM+fI2kSClKs8Hfouvgefygpmr2KyXHdoeiAY/AK0D3+uWn8z/bbm vea2ytQJ9wIMOeaIBwEJK1+HLDnVRqwOCgqd35B5B25Cw6ug2pCMvXmDE6oBnDclilaa nf3Q==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tDIob5J2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-395cb7eb93csm5437923f8f.86.2025.03.14.06.16.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Mar 2025 06:16:45 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/17] target/arm: Move arm_current_el() and arm_el_is_aa64() to internals.h Date: Fri, 14 Mar 2025 13:16:26 +0000 Message-ID: <20250314131637.371866-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250314131637.371866-1-peter.maydell@linaro.org> References: <20250314131637.371866-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The functions arm_current_el() and arm_el_is_aa64() are used only in target/arm and in hw/intc/arm_gicv3_cpuif.c. They're functions that query internal state of the CPU. Move them out of cpu.h and into internals.h. This means we need to include internals.h in arm_gicv3_cpuif.c, but this is justifiable because that file is implementing the GICv3 CPU interface, which really is part of the CPU proper; we just ended up implementing it in code in hw/intc/ for historical reasons. The motivation for this move is that we'd like to change arm_el_is_aa64() to add a condition that uses cpu_isar_feature(); but we don't want to include cpu-features.h in cpu.h. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 66 -------------------------------------- target/arm/internals.h | 67 +++++++++++++++++++++++++++++++++++++++ hw/intc/arm_gicv3_cpuif.c | 1 + target/arm/arch_dump.c | 1 + 4 files changed, 69 insertions(+), 66 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8a59f705167..a8177c6c2e8 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2635,39 +2635,6 @@ uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, ARMSecuritySpace space); uint64_t arm_hcr_el2_eff(CPUARMState *env); uint64_t arm_hcrx_el2_eff(CPUARMState *env); -/* Return true if the specified exception level is running in AArch64 state. */ -static inline bool arm_el_is_aa64(CPUARMState *env, int el) -{ - /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, - * and if we're not in EL0 then the state of EL0 isn't well defined.) - */ - assert(el >= 1 && el <= 3); - bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); - - /* The highest exception level is always at the maximum supported - * register width, and then lower levels have a register width controlled - * by bits in the SCR or HCR registers. - */ - if (el == 3) { - return aa64; - } - - if (arm_feature(env, ARM_FEATURE_EL3) && - ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) { - aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); - } - - if (el == 2) { - return aa64; - } - - if (arm_is_el2_enabled(env)) { - aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); - } - - return aa64; -} - /* * Function for determining whether guest cp register reads and writes should * access the secure or non-secure bank of a cp register. When EL3 is @@ -2699,39 +2666,6 @@ static inline bool arm_v7m_is_handler_mode(CPUARMState *env) return env->v7m.exception != 0; } -/* Return the current Exception Level (as per ARMv8; note that this differs - * from the ARMv7 Privilege Level). - */ -static inline int arm_current_el(CPUARMState *env) -{ - if (arm_feature(env, ARM_FEATURE_M)) { - return arm_v7m_is_handler_mode(env) || - !(env->v7m.control[env->v7m.secure] & 1); - } - - if (is_a64(env)) { - return extract32(env->pstate, 2, 2); - } - - switch (env->uncached_cpsr & 0x1f) { - case ARM_CPU_MODE_USR: - return 0; - case ARM_CPU_MODE_HYP: - return 2; - case ARM_CPU_MODE_MON: - return 3; - default: - if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { - /* If EL3 is 32-bit then all secure privileged modes run in - * EL3 - */ - return 3; - } - - return 1; - } -} - /** * write_list_to_cpustate * @cpu: ARMCPU diff --git a/target/arm/internals.h b/target/arm/internals.h index c2c59e60309..d161a3e396b 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -392,6 +392,73 @@ static inline FloatRoundMode arm_rmode_to_sf(ARMFPRounding rmode) return arm_rmode_to_sf_map[rmode]; } +/* Return true if the specified exception level is running in AArch64 state. */ +static inline bool arm_el_is_aa64(CPUARMState *env, int el) +{ + /* + * This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, + * and if we're not in EL0 then the state of EL0 isn't well defined.) + */ + assert(el >= 1 && el <= 3); + bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); + + /* + * The highest exception level is always at the maximum supported + * register width, and then lower levels have a register width controlled + * by bits in the SCR or HCR registers. + */ + if (el == 3) { + return aa64; + } + + if (arm_feature(env, ARM_FEATURE_EL3) && + ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) { + aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); + } + + if (el == 2) { + return aa64; + } + + if (arm_is_el2_enabled(env)) { + aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); + } + + return aa64; +} + +/* + * Return the current Exception Level (as per ARMv8; note that this differs + * from the ARMv7 Privilege Level). + */ +static inline int arm_current_el(CPUARMState *env) +{ + if (arm_feature(env, ARM_FEATURE_M)) { + return arm_v7m_is_handler_mode(env) || + !(env->v7m.control[env->v7m.secure] & 1); + } + + if (is_a64(env)) { + return extract32(env->pstate, 2, 2); + } + + switch (env->uncached_cpsr & 0x1f) { + case ARM_CPU_MODE_USR: + return 0; + case ARM_CPU_MODE_HYP: + return 2; + case ARM_CPU_MODE_MON: + return 3; + default: + if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { + /* If EL3 is 32-bit then all secure privileged modes run in EL3 */ + return 3; + } + + return 1; + } +} + static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env, bool sctlr_b) { diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 7f1d071c198..de37465bc87 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "target/arm/cpregs.h" #include "target/arm/cpu-features.h" +#include "target/arm/internals.h" #include "system/tcg.h" #include "system/qtest.h" diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c index 5c943dc27b5..c40df4e7fd7 100644 --- a/target/arm/arch_dump.c +++ b/target/arm/arch_dump.c @@ -23,6 +23,7 @@ #include "elf.h" #include "system/dump.h" #include "cpu-features.h" +#include "internals.h" /* struct user_pt_regs from arch/arm64/include/uapi/asm/ptrace.h */ struct aarch64_user_regs { From patchwork Fri Mar 14 13:16:27 2025 Content-Type: text/plain; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-395cb7eb93csm5437923f8f.86.2025.03.14.06.16.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Mar 2025 06:16:46 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/17] target/arm: SCR_EL3.RW should be treated as 1 if EL2 doesn't support AArch32 Date: Fri, 14 Mar 2025 13:16:27 +0000 Message-ID: <20250314131637.371866-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250314131637.371866-1-peter.maydell@linaro.org> References: <20250314131637.371866-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The definition of SCR_EL3.RW says that its effective value is 1 if: - EL2 is implemented and does not support AArch32, and SCR_EL3.NS is 1 - the effective value of SCR_EL3.{EEL2,NS} is {1,0} (i.e. we are Secure and Secure EL2 is disabled) We implement the second of these in arm_el_is_aa64(), but forgot the first. Provide a new function arm_scr_rw_eff() to return the effective value of SCR_EL3.RW, and use it in arm_el_is_aa64() and the other places that currently look directly at the bit value. (scr_write() enforces that the RW bit is RAO/WI if neither EL1 nor EL2 have AArch32 support, but if EL1 does but EL2 does not then the bit must still be writeable.) This will mean that if code at EL3 attempts to perform an exception return to AArch32 EL2 when EL2 is AArch64-only we will correctly handle this as an illegal exception return: it will be caught by the "return to an EL which is configured for a different register width" check in HELPER(exception_return). We do already have some CPU types which don't implement AArch32 above EL0, so this is technically a bug; it doesn't seem worth backporting to stable because no sensible guest code will be deliberately attempting to set the RW bit to a value corresponding to an unimplemented execution state and then checking that we did the right thing. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/internals.h | 26 +++++++++++++++++++++++--- target/arm/helper.c | 4 ++-- 2 files changed, 25 insertions(+), 5 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index d161a3e396b..28585c07555 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -392,6 +392,27 @@ static inline FloatRoundMode arm_rmode_to_sf(ARMFPRounding rmode) return arm_rmode_to_sf_map[rmode]; } +/* Return the effective value of SCR_EL3.RW */ +static inline bool arm_scr_rw_eff(CPUARMState *env) +{ + /* + * SCR_EL3.RW has an effective value of 1 if: + * - we are NS and EL2 is implemented but doesn't support AArch32 + * - we are S and EL2 is enabled (in which case it must be AArch64) + */ + ARMCPU *cpu = env_archcpu(env); + + if (env->cp15.scr_el3 & SCR_RW) { + return true; + } + if (env->cp15.scr_el3 & SCR_NS) { + return arm_feature(env, ARM_FEATURE_EL2) && + !cpu_isar_feature(aa64_aa32_el2, cpu); + } else { + return env->cp15.scr_el3 & SCR_EEL2; + } +} + /* Return true if the specified exception level is running in AArch64 state. */ static inline bool arm_el_is_aa64(CPUARMState *env, int el) { @@ -411,9 +432,8 @@ static inline bool arm_el_is_aa64(CPUARMState *env, int el) return aa64; } - if (arm_feature(env, ARM_FEATURE_EL3) && - ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) { - aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); + if (arm_feature(env, ARM_FEATURE_EL3)) { + aa64 = aa64 && arm_scr_rw_eff(env); } if (el == 2) { diff --git a/target/arm/helper.c b/target/arm/helper.c index f0ead22937b..3df7d5347cb 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9818,7 +9818,7 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, uint64_t hcr_el2; if (arm_feature(env, ARM_FEATURE_EL3)) { - rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW); + rw = arm_scr_rw_eff(env); } else { /* * Either EL2 is the highest EL (and so the EL2 register width @@ -10627,7 +10627,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) switch (new_el) { case 3: - is_aa64 = (env->cp15.scr_el3 & SCR_RW) != 0; + is_aa64 = arm_scr_rw_eff(env); break; case 2: hcr = arm_hcr_el2_eff(env); From patchwork Fri Mar 14 13:16:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 873447 Delivered-To: patch@linaro.org Received: by 2002:a5d:4308:0:b0:38f:210b:807b with SMTP id h8csp703033wrq; Fri, 14 Mar 2025 06:19:29 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUWqHMClAbcshxieEL295EEkzvc+n7kQxBbW46gvBL7SKY7furzLvLK2t8xX8XaCu6q1iizHA==@linaro.org X-Google-Smtp-Source: AGHT+IE0U+KsrrmkR+MVVicQok0sTc3KDBPB3t/DIuVdvC+IE71Qq7eT3ISQqbO8PTpRvjkMV6MQ X-Received: by 2002:ac8:5787:0:b0:476:b1aa:6e19 with SMTP id d75a77b69052e-476c81c3659mr33265641cf.37.1741958369247; Fri, 14 Mar 2025 06:19:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1741958369; cv=none; d=google.com; s=arc-20240605; b=fcITbCuSSRSxsM9txuzUYzIhRvCuSo8z7Tok2T2PHMymy9dAAL64Q8m0q+PuCJNt9i V+XcgcfEj8Ug+/tzW95CabB+lqR1s+3Kx64X429B/dYiHrBQjXoZKmBTQTj78+vUM/a0 UfX6bxP+1geclAylbnmq3Oi1BHUTq/qX5v19y/rg53UX/iGATcco5T/yGgxmsa05jOXB 8vuV3i39/C93H9uEil+nZX/MKgGZwGNe8VQnbJ2hUsvGfzzc/geoVVRiXMM3NtKzvOw5 fHWFbH8P/ZCktlZ9UfboF+l764eUJQRdoQagLRDHMW/2Yl/V46Zb9r0XJyFyOUOaJJVq lSMA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=UHA95dpymGqv9/OSGqYWddDTp72SBRI3UEcR8U6Ysio=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=RgEFqKizFyNk8aDsgaXYbgbR7SQHIc1Z+cscS3i61bfn+3kpEONChoryScdo2pn+uL Vqxs8prBbMfnHfQAb/gZRkqprhoWVK1l+gBFuJza8smeUyYRD0RRy8vXamm9zJ5niWZO b8gmelJfh7HEOhfwzaZpJh/Si2OU3DVpQ8n6vobAOTG+02BPCjI0ELjmJZ6KeqeJyTzT xJPwxwz/enTJ0M1XzCVZea6jFrIugHMpsu3h6Mdk3g6LdQoQqTNOUd28unPP/B+VxjqP 13T4kWXvWyYUxi+64bz8zlNxj/UFYceCsd7wsvkNnIt/oUaA2XHp1Sbp2ovtpZ4t5n5s pAUA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mkp7yCX2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-395cb7eb93csm5437923f8f.86.2025.03.14.06.16.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Mar 2025 06:16:47 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/17] target/arm: HCR_EL2.RW should be RAO/WI if EL1 doesn't support AArch32 Date: Fri, 14 Mar 2025 13:16:28 +0000 Message-ID: <20250314131637.371866-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250314131637.371866-1-peter.maydell@linaro.org> References: <20250314131637.371866-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When EL1 doesn't support AArch32, the HCR_EL2.RW bit is supposed to be RAO/WI. Enforce the RAO/WI behaviour. Note that we handle "reset value should honour RES1 bits" in the same way that SCR_EL3 does, via a reset function. We do already have some CPU types which don't implement AArch32 above EL0, so this is technically a bug; it doesn't seem worth backporting to stable because no sensible guest code will be deliberately attempting to set the RW bit to a value corresponding to an unimplemented execution state and then checking that we did the right thing. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 3df7d5347cb..bb445e30cd1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5326,6 +5326,11 @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask) /* Clear RES0 bits. */ value &= valid_mask; + /* RW is RAO/WI if EL1 is AArch64 only */ + if (!cpu_isar_feature(aa64_aa32_el1, cpu)) { + value |= HCR_RW; + } + /* * These bits change the MMU setup: * HCR_VM enables stage 2 translation @@ -5383,6 +5388,12 @@ static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri, do_hcr_write(env, value, MAKE_64BIT_MASK(32, 32)); } +static void hcr_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + /* hcr_write will set the RES1 bits on an AArch64-only CPU */ + hcr_write(env, ri, 0); +} + /* * Return the effective value of HCR_EL2, at the given security state. * Bits that are not included here: @@ -5618,6 +5629,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), .nv2_redirect_offset = 0x78, + .resetfn = hcr_reset, .writefn = hcr_write, .raw_writefn = raw_write }, { .name = "HCR", .state = ARM_CP_STATE_AA32, .type = ARM_CP_ALIAS | ARM_CP_IO, From patchwork Fri Mar 14 13:16:29 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 873442 Delivered-To: patch@linaro.org Received: by 2002:a5d:4308:0:b0:38f:210b:807b with SMTP id h8csp702622wrq; Fri, 14 Mar 2025 06:18:41 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXU3RFPQSq5iScoo8Qz/6Y97k9blfzE8tpDQEnGqG+x8qp6MwMpd9OHtGQDR2OMUdSExm22lA==@linaro.org X-Google-Smtp-Source: AGHT+IEskbKLKOFjE8XaCccTbLJ6XhnWlovZFZFVDtS86m/XrvrYeMnioTpdAtn+HbMnXljXRiGX X-Received: by 2002:a05:622a:1910:b0:476:98d6:13ff with SMTP id d75a77b69052e-476c81c351dmr39594941cf.33.1741958320849; Fri, 14 Mar 2025 06:18:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1741958320; cv=none; d=google.com; s=arc-20240605; b=lYqbeJEJq/lJSNp9XKoiDZyGjgCzaeQVZQYMd4qIO5fAjhM+3r1UdzYvDnDalreQNx OCrnoP/SjsjhpGpFduS6oFPabWFETSjaEw6BAolkGmTPi1QQ90UJntWu/E4fPmoOy1Xt v07MJq4nrv8jayf+jhxvuF75skrqcZoNztQOFrA6mstzjQT4XKjo/oyiyD8otbu92/Ym Bz6TZ9wG+5DWWs/8iy+tB/6VZjxspColT/0sGJZwRA9ihEwAdjB05l9gZ/P6hg1N8RoM U1btczuwiYzoJuChPFtiYA9ZS4uibt84q27En5axaCD00AG7qSyoxdPBD/aJoX4vGTXJ CNiQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=DvXgBHhDfQDJ4cRYmWkhbN70Za6+ZucTF502DMfe7mw=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=GHIifCcXEQumJsiT0FKvl6EThynnqx9E3eFP1PXO3e43gp7vNowZyZ6NgE4+jJiByX BdYQj/MkwKM8VY2BhVh+sXlPQmedrCC4lD0/znlL1EDGSdZLmt0gqrnYtXlFfHzvS/cf ALab8VR2ppsYH2uEXMQeUe7DIjOwrhWJvHjP41lZoquVQUAkJEM1H7kQ4m3dJfzpLAa2 6GtTN9oaxv5uBdNGCqaeLdl8EOiF0zq/7APIbdEbmgvdb18we7r596BTkka3A2kt4tib sdh0xAK+5HF9EIdbR74z+y3/9J4CG5Ad61XtxIxULJZB4WOxQgFezCvquHhagClobuKL hP0A==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IvCwQhSM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-395cb7eb93csm5437923f8f.86.2025.03.14.06.16.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Mar 2025 06:16:48 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/17] target/arm: Add cpu local variable to exception_return helper Date: Fri, 14 Mar 2025 13:16:29 +0000 Message-ID: <20250314131637.371866-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250314131637.371866-1-peter.maydell@linaro.org> References: <20250314131637.371866-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We already call env_archcpu() multiple times within the exception_return helper function, and we're about to want to add another use of the ARMCPU pointer. Add a local variable cpu so we can call env_archcpu() just once. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/helper-a64.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index 32f0647ca4f..e2bdf07833d 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -631,6 +631,7 @@ static void cpsr_write_from_spsr_elx(CPUARMState *env, void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) { + ARMCPU *cpu = env_archcpu(env); int cur_el = arm_current_el(env); unsigned int spsr_idx = aarch64_banked_spsr_index(cur_el); uint32_t spsr = env->banked_spsr[spsr_idx]; @@ -682,7 +683,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) } bql_lock(); - arm_call_pre_el_change_hook(env_archcpu(env)); + arm_call_pre_el_change_hook(cpu); bql_unlock(); if (!return_to_aa64) { @@ -710,7 +711,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) int tbii; env->aarch64 = true; - spsr &= aarch64_pstate_valid_mask(&env_archcpu(env)->isar); + spsr &= aarch64_pstate_valid_mask(&cpu->isar); pstate_write(env, spsr); if (!arm_singlestep_active(env)) { env->pstate &= ~PSTATE_SS; @@ -749,7 +750,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) aarch64_sve_change_el(env, cur_el, new_el, return_to_aa64); bql_lock(); - arm_call_el_change_hook(env_archcpu(env)); + arm_call_el_change_hook(cpu); bql_unlock(); return; From patchwork Fri Mar 14 13:16:30 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 873445 Delivered-To: patch@linaro.org Received: by 2002:a5d:4308:0:b0:38f:210b:807b with SMTP id h8csp702774wrq; Fri, 14 Mar 2025 06:18:59 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUvkbb8xjw2gylM42Ie89yK842qJn5a07jR+TgoW8d3IHSAQk26KH/fIGzrwVy2uN0Of4RXiQ==@linaro.org X-Google-Smtp-Source: AGHT+IG3bMJf3wnhFTthe2+w5tKx58RIHm18EySPtctV8CVap0LVUKhPXscIe5EFpGhdBOirS79F X-Received: by 2002:a05:622a:50d:b0:476:a03b:96ec with SMTP id d75a77b69052e-476c81d1da6mr35154251cf.32.1741958339009; Fri, 14 Mar 2025 06:18:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1741958339; cv=none; d=google.com; s=arc-20240605; b=Q7z27RczAvBlPDHUd6NbDfq+KQMY1IGNMJmreNNEjvfyD+cEG1Ain0iWJEbN4eR7aW glG72eqpmBSvBMr+7rMWbOohojtSjFNT+c/7I5+R+P0SQfoZ6y+sY0ODs1VJbhmLnUxf MQAoGo1hnv4Y1wl8bG5A0EuT8LqAV6FbMxexOhc7DE23tB6dH5ZL6YEZbcsZ7mHr1WZi fbV3lrKknUysl0ZgCBylGt8SSaPFep5Gt7FaZq+jG8RphhPJxMZA2aISzBO6pEiaog2C 39YAz+ZXy62WBJlYQBIHlaC/udtNcnRWrSzxxEhKAthJ8BNcj2JEb7tgWvFyDM+fLggt kyYw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=uuNgLNZaj6en9G9psqN457RUFRID5SO7T7BkCrfJY3g=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=EdEE7KqaskDrZRhX15mvmukPaQmdnJFt+A+I9XfwCGRgeY1DbG149yNnAZOzm+n+ac u6EcAqDYfQoEPGhtzyzBbWo63KYhVtY5XeHvUi7QjY/vvzi+oO9BPeVbyH79G7JBW8/T /UqkIVwY9Efhbh7vK6K1AHpqA6cXDu+9OBlzD1ygbvifnh84aqVCQ+xB3WWO26EFFBCU OqUYYf0I7fp87zPgkuMj4oy2fE+ceNyMjKIwUdWvXZ324xHve7W67qtDaDH/XAgZoeUy LieD8q+4npL5A2ct6d1xOi36jUhtOs0r/Gd6XPVb+72RnonsAd5mhV4zkt6sjbzRcSJ+ DU6Q==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=o8R2UbED; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-395cb7eb93csm5437923f8f.86.2025.03.14.06.16.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Mar 2025 06:16:49 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/17] target/arm: Forbid return to AArch32 when CPU is AArch64-only Date: Fri, 14 Mar 2025 13:16:30 +0000 Message-ID: <20250314131637.371866-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250314131637.371866-1-peter.maydell@linaro.org> References: <20250314131637.371866-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In the Arm ARM, rule R_TYTWB states that returning to AArch32 is an illegal exception return if: * AArch32 is not supported at any exception level * the target EL is configured for AArch64 via SCR_EL3.RW or HCR_EL2.RW or via CPU state at reset We check the second of these, but not the first (which can only be relevant for the case of a return to EL0, because if AArch32 is not supported at one of the higher ELs then the RW bits will have an effective value of 1 and the the "configured for AArch64" condition will hold also). Add the missing condition. Although this is technically a bug (because we have one AArch64-only CPU: a64fx) it isn't worth backporting to stable because no sensible guest code will deliberately try to return to a nonexistent execution state to check that it gets an illegal exception return. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/helper-a64.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index e2bdf07833d..9244848efed 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -678,6 +678,11 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) goto illegal_return; } + if (!return_to_aa64 && !cpu_isar_feature(aa64_aa32, cpu)) { + /* Return to AArch32 when CPU is AArch64-only */ + goto illegal_return; + } + if (new_el == 1 && (arm_hcr_el2_eff(env) & HCR_TGE)) { goto illegal_return; } From patchwork Fri Mar 14 13:16:31 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 873448 Delivered-To: patch@linaro.org Received: by 2002:a5d:4308:0:b0:38f:210b:807b with SMTP id h8csp703709wrq; Fri, 14 Mar 2025 06:20:52 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVfMNsNRVEuny/jM8AuOqJTHsDGKN2/buSkmHM42XEb3A7cBLI5JOElaMH4nEDHL0P/Q5DFTA==@linaro.org X-Google-Smtp-Source: AGHT+IHc0lzNzpyfwzftflLGQ5DFOpbpwfFtyFETh2VzitJCMy/airIOeyAlScYl0r6iMTv+hJQ1 X-Received: by 2002:a05:620a:2729:b0:7c5:4daa:2511 with SMTP id af79cd13be357-7c57c92004bmr318962285a.52.1741958451770; Fri, 14 Mar 2025 06:20:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1741958451; cv=none; d=google.com; s=arc-20240605; b=FiUpt78KBVet32HRB1WUXrkSbOmQ163Pv0b9Hf5sptT63PCDKQzqV8S2Y23TB9V1qt hW8iiKSjV+kUV+fZWrlcmQJdJsTdnVYV44gu8PDHQ2+k8lbIuZe/yOp3vWgd6k7Chmza iXDzQsF0k+G0XK4Bw6LTFEZW1DhhvyqilgVw6ajBECg3LDOx90XvCKpCQeol0TAWjs+m 2Vpk/XH+WgklOH3YTkaD7d/hoC/cFXEfYPVK6ykj+mJDiMEJVlVgzjkMlIEle8s4JqGD qrpipRWxpHAvMoaBiWro4CtSrawjfF2glB3baBUWDzEe7jIm/i9Q+f+AwxZOcm3zPqcN bt/g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Wd7g6oeMHVWi/J7kwV0qC+uPDbfRdDe//+DBMn4lERc=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=PJzuloNsxx0Nz/NC5qWTl3yzoUpEiJezzGsnTChYXexG8tgDPMyR4jO/WjiOld39vv hyhXTN5Jeb2LvohwYxj+5f83jYlWuUuFPa9rhtYHSqhCCaDuM5CNMxe6m5/xMaGoXWDn FeIiJ3af3hxN2Q86kL02RxL/VGGLyDltyVKi5Uc7jtkk6tifBzYGK4NstHRqPvxP89tf riHVi6XJ7SqGnlIuKOwHNffhOVthWdxWiom7YTFoFZlCdTbVFvFa03nXS1S0USo2JUKU ILpEHReLPWGs3k8L89fn+wOiZmjCYZN1llJVb/BEQaCHrUThbBZu053UZUW5navzogfq B5tw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=t7cYPOAZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-395cb7eb93csm5437923f8f.86.2025.03.14.06.16.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Mar 2025 06:16:49 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/17] MAINTAINERS: Fix status for Arm boards I "maintain" Date: Fri, 14 Mar 2025 13:16:31 +0000 Message-ID: <20250314131637.371866-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250314131637.371866-1-peter.maydell@linaro.org> References: <20250314131637.371866-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org I'm down as the only listed maintainer for quite a lot of Arm SoC and board types. In some cases this is only as the "maintainer of last resort" and I'm not in practice doing anything beyond patch review and the odd bit of tidyup. Move these entries in MAINTAINERS from "Maintained" to "Odd Fixes", to better represent reality. Entries for other boards and SoCs where I do more actively care (or where there is a listed co-maintainer) remain as they are. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-id: 20250307152838.3226398-1-peter.maydell@linaro.org --- MAINTAINERS | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 31b395fdfad..8f470a1c9b7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -786,7 +786,7 @@ F: docs/system/arm/kzm.rst Integrator CP M: Peter Maydell L: qemu-arm@nongnu.org -S: Maintained +S: Odd Fixes F: hw/arm/integratorcp.c F: hw/misc/arm_integrator_debug.c F: include/hw/misc/arm_integrator_debug.h @@ -867,7 +867,7 @@ F: docs/system/arm/mps2.rst Musca M: Peter Maydell L: qemu-arm@nongnu.org -S: Maintained +S: Odd Fixes F: hw/arm/musca.c F: docs/system/arm/musca.rst @@ -915,7 +915,7 @@ F: tests/functional/test_aarch64_raspi4.py Real View M: Peter Maydell L: qemu-arm@nongnu.org -S: Maintained +S: Odd Fixes F: hw/arm/realview* F: hw/cpu/realview_mpcore.c F: hw/intc/realview_gic.c @@ -965,7 +965,7 @@ F: tests/functional/test_arm_collie.py Stellaris M: Peter Maydell L: qemu-arm@nongnu.org -S: Maintained +S: Odd Fixes F: hw/*/stellaris* F: hw/display/ssd03* F: include/hw/input/gamepad.h @@ -995,7 +995,7 @@ F: docs/system/arm/stm32.rst Versatile Express M: Peter Maydell L: qemu-arm@nongnu.org -S: Maintained +S: Odd Fixes F: hw/arm/vexpress.c F: hw/display/sii9022.c F: docs/system/arm/vexpress.rst @@ -1004,7 +1004,7 @@ F: tests/functional/test_arm_vexpress.py Versatile PB M: Peter Maydell L: qemu-arm@nongnu.org -S: Maintained +S: Odd Fixes F: hw/*/versatile* F: hw/i2c/arm_sbcon_i2c.c F: include/hw/i2c/arm_sbcon_i2c.h @@ -2003,7 +2003,7 @@ F: include/hw/hyperv/vmbus*.h OMAP M: Peter Maydell L: qemu-arm@nongnu.org -S: Maintained +S: Odd Fixes F: hw/*/omap* F: include/hw/arm/omap.h F: docs/system/arm/sx1.rst From patchwork Fri Mar 14 13:16:33 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 873444 Delivered-To: patch@linaro.org Received: by 2002:a5d:4308:0:b0:38f:210b:807b with SMTP id h8csp702651wrq; Fri, 14 Mar 2025 06:18:45 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXSVS6UvAZUTxKn750z4yqykwtgmzzmhS9tSnRG5bP3GLx/kJDvrk5J7stYp0XRGjSbAcADrQ==@linaro.org X-Google-Smtp-Source: AGHT+IGG9KTVgDv9Zh6q9P904TE05zUjiXwVlP2VAJOaQ70uJml+rLs9sg63b9Ofyx520drhFsKW X-Received: by 2002:a05:620a:40ce:b0:7c5:7a03:8467 with SMTP id af79cd13be357-7c57c9237eemr326894985a.55.1741958324855; Fri, 14 Mar 2025 06:18:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1741958324; cv=none; d=google.com; s=arc-20240605; b=R9xFCObAVIPVO7aHN5WVkKgAfGdSMQJ6NZkaXbZzDIvZfeg0G6fBBjvDrKBjSzfqqh CeT6jJNlgMyJxwLqLPnxG20P7Ki5Kj8n3hajxAjPv3ns0hINIVjtPncui/sjp3kKm6Nq tuOWzsSL5Woex5NsAVojE6v/Hi4Yplf6FL8by9C2RkzdiLkgYZxIhcCNZvgheowlSz3y ec3Y3b7nJ+2mlzl53+/ENE5Y+Wf5PTUxNpORTYbGMpPqC8QCOG5axDW4kGkpFPa/nlPW jvySUUJ1b2gHAd4qj3aUAw5YWNLWmCqlKMT+m0gBVNPkpDE6MlqH9CMnOtAz8KgVqpn2 Dq4A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ASyllHmufnMu1BxhqQoVFXG0Ckh8C1+NGqucyyEdqU4=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=Snv1OnUiLQojuouPlqn6iOdZH5h30+du/Ro2Esr11osQQwbghIXKSmT+SI5C+qHTVV LYND16Pn+elEy5L7e+7ICnUt0589bGRSvdryJek6upzABCJhZJTzQPl72h7x6yJ02ey5 yDfDXds0t2ffmABDdPyiXIiOkbi0jyAltX6Fcrj9PNF52ndTuAFtO7WPnGCC7HutQsuZ JD3/czUw4veW4ntY/VOZIXxPfPyVKUBBcfeNeSFalAX5sZ21KF+aFMPQXsFU4NuFPNqw NZH0G0x/gt6nUThlirdUWuQNrr6WtRLN+dsEUkJRAo3WLGByfmhDZCmowTQ/nNlzWhwT RMhg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rn+qzDJP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-395cb7eb93csm5437923f8f.86.2025.03.14.06.16.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Mar 2025 06:16:51 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/17] Revert "hw/char/pl011: Warn when using disabled receiver" Date: Fri, 14 Mar 2025 13:16:33 +0000 Message-ID: <20250314131637.371866-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250314131637.371866-1-peter.maydell@linaro.org> References: <20250314131637.371866-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Paolo Bonzini The guest does not control whether characters are sent on the UART. Sending them before the guest happens to boot will now result in a "guest error" log entry that is only because of timing, even if the guest _would_ later setup the receiver correctly. This reverts the bulk of commit abf2b6a028670bd2890bb3aee7e103fe53e4b0df, and instead adds a comment about why we don't check the enable bits. Cc: Philippe Mathieu-Daudé Cc: Peter Maydell Signed-off-by: Paolo Bonzini Message-id: 20250311153717.206129-1-pbonzini@redhat.com [PMM: expanded comment] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/char/pl011.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/hw/char/pl011.c b/hw/char/pl011.c index 23a9db8c57c..0e9ec1301d3 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -490,16 +490,17 @@ static int pl011_can_receive(void *opaque) unsigned fifo_depth = pl011_get_fifo_depth(s); unsigned fifo_available = fifo_depth - s->read_count; - if (!(s->cr & CR_UARTEN)) { - qemu_log_mask(LOG_GUEST_ERROR, - "PL011 receiving data on disabled UART\n"); - } - if (!(s->cr & CR_RXE)) { - qemu_log_mask(LOG_GUEST_ERROR, - "PL011 receiving data on disabled RX UART\n"); - } - trace_pl011_can_receive(s->lcr, s->read_count, fifo_depth, fifo_available); + /* + * In theory we should check the UART and RX enable bits here and + * return 0 if they are not set (so the guest can't receive data + * until you have enabled the UART). In practice we suspect there + * is at least some guest code out there which has been tested only + * on QEMU and which never bothers to enable the UART because we + * historically never enforced that. So we effectively keep the + * UART continuously enabled regardless of the enable bits. + */ + trace_pl011_can_receive(s->lcr, s->read_count, fifo_depth, fifo_available); return fifo_available; } From patchwork Fri Mar 14 13:16:34 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 873438 Delivered-To: patch@linaro.org Received: by 2002:a5d:4308:0:b0:38f:210b:807b with SMTP id h8csp702195wrq; Fri, 14 Mar 2025 06:17:53 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUceawNGfR5m5uV2Q4ZFCKwZGn7aj3Sv4Tk0yHITpzD+sbLjvKn8TXouDvImMxM59PEwgAYBQ==@linaro.org X-Google-Smtp-Source: AGHT+IERfguhH3iH1kGrv/Zi1Tr1H2JJorr67pEjMmvTqqg6VtWEl3xobRI4lRXgDn07Ce/SZNfj X-Received: by 2002:a05:6214:258d:b0:6d4:1ea3:981d with SMTP id 6a1803df08f44-6eaeab38f55mr26977506d6.43.1741958272879; Fri, 14 Mar 2025 06:17:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1741958272; cv=none; d=google.com; s=arc-20240605; b=CfjC2Feb0J31xgK0ETVdKEynDDwd3Xn57xLYEhHhDJuMF+Qo9r0oHl9otoK3DBwGmw Hy/WQG3763w35MkKs0E3nU8hJDbObCJ58qZys1GmaKStrJa7+eQ5P8TXgENCZ14qIIA4 riBi3h9xT7Sl8PJSzHK5iYsLucVGOvvyznoV5b95E9NzN6qNLcwz4AQVwFHVrCF4Ew82 HK5Zlv55xNQ76h7ESsgChA8+ZMNp3s2/9bBAK2KpUnXAUFh5ii8G4DExMfYkRwn/3zoZ b/cs0K++7IdCcq/wRwTzPXGAxw7oxVKTqmYrj+rmGy9mKrRFIIKxofIjrIPVjg9dSKKj qkzA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=IOqXwb1Gpfc1XLtrVTEu1MEyCUJmn6mHT6hEbN78jvs=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=UcJxrCKXAAw2YypJm9UWqiY2ctFykLOt01jlAqlHtMU5mBWGKPK3i5aNnucwXeGuQh we7NNL5/kMMunbJPJRhNA3QsklOk+qjgv7f1zKbRZUZ3PJ4tW7W8ueHEW/lEMiaGXgDq XwRBHFCUMHh0mZdhbceSTG4ZrcFoL8z058KC1To89RNn6VGCgtdKwdrd9LJlYJjlqRYU 4sAALlIUmXC6ZbDZHW1B3BE5xRtIvJwceJdPFWZGKU79b7e+7uXr9XOSzUz20IG4L/93 MtXVDqWJC46IvWfVQFIOa6GgjDf+i7UtqaMiJU9MYnJJh3628+dj8TCzazl2Qor98ll/ OeyQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pmzhFSEA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-395cb7eb93csm5437923f8f.86.2025.03.14.06.16.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Mar 2025 06:16:52 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/17] util/cacheflush: Make first DSB unconditional on aarch64 Date: Fri, 14 Mar 2025 13:16:34 +0000 Message-ID: <20250314131637.371866-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250314131637.371866-1-peter.maydell@linaro.org> References: <20250314131637.371866-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Joe Komlodi On ARM hosts with CTR_EL0.DIC and CTR_EL0.IDC set, this would only cause an ISB to be executed during cache maintenance, which could lead to QEMU executing TBs containing garbage instructions. This seems to be because the ISB finishes executing instructions and flushes the pipeline, but the ISB doesn't guarantee that writes from the executed instructions are committed. If a small enough TB is created, it's possible that the writes setting up the TB aren't committed by the time the TB is executed. This function is intended to be a port of the gcc implementation (https://github.com/gcc-mirror/gcc/blob/85b46d0795ac76bc192cb8f88b646a647acf98c1/libgcc/config/aarch64/sync-cache.c#L67) which makes the first DSB unconditional, so we can fix the synchronization issue by doing that as well. Cc: qemu-stable@nongnu.org Fixes: 664a79735e4deb1 ("util: Specialize flush_idcache_range for aarch64") Signed-off-by: Joe Komlodi Message-id: 20250310203622.1827940-2-komlodi@google.com Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- util/cacheflush.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/util/cacheflush.c b/util/cacheflush.c index a08906155a9..1d12899a392 100644 --- a/util/cacheflush.c +++ b/util/cacheflush.c @@ -279,9 +279,11 @@ void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len) for (p = rw & -dcache_lsize; p < rw + len; p += dcache_lsize) { asm volatile("dc\tcvau, %0" : : "r" (p) : "memory"); } - asm volatile("dsb\tish" : : : "memory"); } + /* DSB unconditionally to ensure any outstanding writes are committed. */ + asm volatile("dsb\tish" : : : "memory"); + /* * If CTR_EL0.DIC is enabled, Instruction cache cleaning to the Point * of Unification is not required for instruction to data coherence. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-395cb7eb93csm5437923f8f.86.2025.03.14.06.16.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Mar 2025 06:16:53 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/17] target/arm: Make DisasContext.{fp, sve}_access_checked tristate Date: Fri, 14 Mar 2025 13:16:35 +0000 Message-ID: <20250314131637.371866-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250314131637.371866-1-peter.maydell@linaro.org> References: <20250314131637.371866-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson The check for fp_excp_el in assert_fp_access_checked is incorrect. For SME, with StreamingMode enabled, the access is really against the streaming mode vectors, and access to the normal fp registers is allowed to be disabled. C.f. sme_enabled_check. Convert sve_access_checked to match, even though we don't currently check the exception state. Cc: qemu-stable@nongnu.org Fixes: 3d74825f4d6 ("target/arm: Add SME enablement checks") Signed-off-by: Richard Henderson Message-id: 20250307190415.982049-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/tcg/translate-a64.h | 2 +- target/arm/tcg/translate.h | 10 +++++++--- target/arm/tcg/translate-a64.c | 17 +++++++++-------- 3 files changed, 17 insertions(+), 12 deletions(-) diff --git a/target/arm/tcg/translate-a64.h b/target/arm/tcg/translate-a64.h index 7d3b59ccd96..b2420f59ebe 100644 --- a/target/arm/tcg/translate-a64.h +++ b/target/arm/tcg/translate-a64.h @@ -65,7 +65,7 @@ TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write, static inline void assert_fp_access_checked(DisasContext *s) { #ifdef CONFIG_DEBUG_TCG - if (unlikely(!s->fp_access_checked || s->fp_excp_el)) { + if (unlikely(s->fp_access_checked <= 0)) { fprintf(stderr, "target-arm: FP access check missing for " "instruction 0x%08x\n", s->insn); abort(); diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index f8dc2f0d4bb..53e485d28ac 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -92,15 +92,19 @@ typedef struct DisasContext { bool aarch64; bool thumb; bool lse2; - /* Because unallocated encodings generate different exception syndrome + /* + * Because unallocated encodings generate different exception syndrome * information from traps due to FP being disabled, we can't do a single * "is fp access disabled" check at a high level in the decode tree. * To help in catching bugs where the access check was forgotten in some * code path, we set this flag when the access check is done, and assert * that it is set at the point where we actually touch the FP regs. + * 0: not checked, + * 1: checked, access ok + * -1: checked, access denied */ - bool fp_access_checked; - bool sve_access_checked; + int8_t fp_access_checked; + int8_t sve_access_checked; /* ARMv8 single-step state (this is distinct from the QEMU gdbstub * single-step support). */ diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 8bef391bb03..48e0ac75b11 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -1381,14 +1381,14 @@ static bool fp_access_check_only(DisasContext *s) { if (s->fp_excp_el) { assert(!s->fp_access_checked); - s->fp_access_checked = true; + s->fp_access_checked = -1; gen_exception_insn_el(s, 0, EXCP_UDEF, syn_fp_access_trap(1, 0xe, false, 0), s->fp_excp_el); return false; } - s->fp_access_checked = true; + s->fp_access_checked = 1; return true; } @@ -1465,13 +1465,13 @@ bool sve_access_check(DisasContext *s) syn_sve_access_trap(), s->sve_excp_el); goto fail_exit; } - s->sve_access_checked = true; + s->sve_access_checked = 1; return fp_access_check(s); fail_exit: /* Assert that we only raise one exception per instruction. */ assert(!s->sve_access_checked); - s->sve_access_checked = true; + s->sve_access_checked = -1; return false; } @@ -1500,8 +1500,9 @@ bool sme_enabled_check(DisasContext *s) * sme_excp_el by itself for cpregs access checks. */ if (!s->fp_excp_el || s->sme_excp_el < s->fp_excp_el) { - s->fp_access_checked = true; - return sme_access_check(s); + bool ret = sme_access_check(s); + s->fp_access_checked = (ret ? 1 : -1); + return ret; } return fp_access_check_only(s); } @@ -10257,8 +10258,8 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) s->insn = insn; s->base.pc_next = pc + 4; - s->fp_access_checked = false; - s->sve_access_checked = false; + s->fp_access_checked = 0; + s->sve_access_checked = 0; if (s->pstate_il) { /* From patchwork Fri Mar 14 13:16:36 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 873450 Delivered-To: patch@linaro.org Received: by 2002:a5d:4308:0:b0:38f:210b:807b with SMTP id h8csp704163wrq; Fri, 14 Mar 2025 06:21:39 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXiUjWcuNub1E6B2UYBEFWwJARSQpz+5j8M6lrUiE9K23v8qVwnkAH1GKRSaflv/uiilKMKHg==@linaro.org X-Google-Smtp-Source: AGHT+IH2HfKijrMTkdz5lZXR4D7s8x0LbRlclUnrBSqOaWAPZaR8o5Eb5OTw3XfuI3XuZeE/0VHh X-Received: by 2002:a0c:f747:0:b0:6e8:f445:3578 with SMTP id 6a1803df08f44-6eaea9961b5mr29491246d6.2.1741958499464; Fri, 14 Mar 2025 06:21:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1741958499; cv=none; d=google.com; s=arc-20240605; b=eBSgFWnApsQdhMvl+LV1MjANVUCJmcyBSd5SsDacewO1EbfvQQq5sjk3EmXj2Phs1A tIHbmpNcb9xkNuWKbxAQdndt9FV2IrMkaqkd+khnXvhpeql1qNNKjlxbjVcFTCKqd5mp HTbWdjZmC5roNJ2LCDYZ3N421zIMaKL/mngSKNPtZ7HJ59U/14ld2Q86J9oIzg0mH3JD UXmUEuGFKmQM+6TkdEp7s8lemXipW2WRu2/Ujx8UMEBGhEYGDKYPzlRhg5KU5PObWp29 o6M1vHwr9HSciLBk35NZ623U1nb2lCvCHZwsjG9RvfCvYzXEB7laSTGKn0Qp9xfZld6I gnpw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=qF7NqSa5lV0sZZKHA8ojvh+EUzwVOc8Mo3QSd+ZWM7U=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=SwLAt4r3BXfq2m3+PcjZ3b4O4x8PltZSxlHyGq/RccpwCZYpMdrz3Qu3A4dA26q1dz mBJhHpIvD8rnDLdKc76MiGShZJwBv1HAq5JDQOgPG6o/UYq18spCk/ra9bDjIrAB03+a oFlXiswC2u2+Hrp72ZRxP6pNaTi5nedlL8m+A6K+7ewKOJ3Ziu5x9YcVLNkY3c/Tw97y O4sUA0HeMaX9U6TtI38JPa7+LUZiIG7xLFqC4l2fMi/yijBucbdSGtyeKA3OvVYch6bZ zapfP4qOs1ZUJTXecH3FgQtoimDrmMZslaUbiTLF38SrmIsoVKRQ7p/A7Ek1p+iZ5UXA RAyQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Z5GLj+Rb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-395cb7eb93csm5437923f8f.86.2025.03.14.06.16.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Mar 2025 06:16:54 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/17] target/arm: Simplify pstate_sm check in sve_access_check Date: Fri, 14 Mar 2025 13:16:36 +0000 Message-ID: <20250314131637.371866-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250314131637.371866-1-peter.maydell@linaro.org> References: <20250314131637.371866-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson In StreamingMode, fp_access_checked is handled already. We cannot fall through to fp_access_check lest we fall foul of the double-check assertion. Cc: qemu-stable@nongnu.org Fixes: 285b1d5fcef ("target/arm: Handle SME in sve_access_check") Signed-off-by: Richard Henderson Message-id: 20250307190415.982049-3-richard.henderson@linaro.org Reviewed-by: Peter Maydell [PMM: move declaration of 'ret' to top of block] Signed-off-by: Peter Maydell --- target/arm/tcg/translate-a64.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 48e0ac75b11..39014325df1 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -1456,23 +1456,23 @@ static int fp_access_check_vector_hsd(DisasContext *s, bool is_q, MemOp esz) bool sve_access_check(DisasContext *s) { if (s->pstate_sm || !dc_isar_feature(aa64_sve, s)) { + bool ret; + assert(dc_isar_feature(aa64_sme, s)); - if (!sme_sm_enabled_check(s)) { - goto fail_exit; - } - } else if (s->sve_excp_el) { + ret = sme_sm_enabled_check(s); + s->sve_access_checked = (ret ? 1 : -1); + return ret; + } + if (s->sve_excp_el) { + /* Assert that we only raise one exception per instruction. */ + assert(!s->sve_access_checked); gen_exception_insn_el(s, 0, EXCP_UDEF, syn_sve_access_trap(), s->sve_excp_el); - goto fail_exit; + s->sve_access_checked = -1; + return false; } s->sve_access_checked = 1; return fp_access_check(s); - - fail_exit: - /* Assert that we only raise one exception per instruction. */ - assert(!s->sve_access_checked); - s->sve_access_checked = -1; - return false; } /* From patchwork Fri Mar 14 13:16:37 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 873449 Delivered-To: patch@linaro.org Received: by 2002:a5d:4308:0:b0:38f:210b:807b with SMTP id h8csp704090wrq; Fri, 14 Mar 2025 06:21:33 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCW+eL9Z4YVUeDRM76Xbbkqb3YlpG+O5drSiV4WIZEC1I/R71VKz7Jo11B6Dx8+4v3Zf3j+iEA==@linaro.org X-Google-Smtp-Source: AGHT+IEla5zBLG7FZMhb9YvAMM2gnUjgt0xLcSeQrvYYHUprTSgTRDXVsoVxQ1f/u+i6N9Av23QT X-Received: by 2002:a05:622a:1aa4:b0:476:903a:b7f1 with SMTP id d75a77b69052e-476c811ee00mr42896351cf.11.1741958492811; Fri, 14 Mar 2025 06:21:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1741958492; cv=none; d=google.com; s=arc-20240605; b=OmmHQA/nIHEenCRvutsbR+UbHVz1rr0Dl01NA26OtFZRCWeVpF6mCMCqyUzlx6Lffe GFQxSVO1qgpqZxpTrHtbawddxV+rRP+71bxuDHoPotfQrNSKCrnVfXfYTI9TAJPpRhC6 A2xXn35yjLfBUfl4dATobCQ0tC8e2A8POJa2qJd8XAmLVSkwSMl8/ABOxkiz42mfq9fC zrXrzQODrRZJkhO9RXCn3fACEa1oLA0/Tjz6awAWPG8XEWYDDrUD7cUycC61998vppRA RGSfQAWUrDdAxAUBok3w5fZcEbpx8hFGzSqox0LOnTsvfHv4+4BXfrh/mhwPU8P2u+Tj 4tmA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=/05C1vvU/DoLYE8zWXHa7Rwl5AjnIHXhCOg3oKo2xKA=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=XV+ouAXJmRVmKNeEdlH6LdYAPCCet7knUyP3Sf5To8BgBSOQaV+MW7oK41g+jOBSvF pMrdQjT7fyPh0BMM31bHuGYvIWUP6LPzR5qvOPvRz9H4wchdIaLJYnZOEdjBCsgurWFx uLI9IqOqyz6EkG+xs9ELgPAoYkQX898UqVmbYvz2qImkrlQ2oFU6xEE9JdeRfRI3NH96 PTUIR094Xw1dnH8UlmnNIHU3SiORlVMFOFtPlX2FpGyX6v8dPbnzSTfgHy76un6ICKMz MGaO+Z6Cs4P4YDvM4fdN21xI3IR3NXddwdfbs1/6yRTLOEJR+AoJmyAiIH2mofZx03wu /GrQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Fn5iP6eh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-395cb7eb93csm5437923f8f.86.2025.03.14.06.16.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Mar 2025 06:16:56 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/17] meson.build: Set RUST_BACKTRACE for all tests Date: Fri, 14 Mar 2025 13:16:37 +0000 Message-ID: <20250314131637.371866-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250314131637.371866-1-peter.maydell@linaro.org> References: <20250314131637.371866-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We want to capture potential Rust backtraces on panics in our test logs, which isn't Rust's default behaviour. Set RUST_BACKTRACE=1 in the add_test_setup environments, so that all our tests get run with this environment variable set. This makes the setting of that variable in the gitlab CI template redundant, so we can remove it. Signed-off-by: Peter Maydell Reviewed-by: Daniel P. Berrangé Reviewed-by: Philippe Mathieu-Daudé Message-id: 20250310102950.3752908-1-peter.maydell@linaro.org --- meson.build | 9 ++++++--- .gitlab-ci.d/buildtest-template.yml | 1 - 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/meson.build b/meson.build index 2f43fd81bf4..7f75256acf9 100644 --- a/meson.build +++ b/meson.build @@ -5,9 +5,12 @@ project('qemu', ['c'], meson_version: '>=1.5.0', meson.add_devenv({ 'MESON_BUILD_ROOT' : meson.project_build_root() }) -add_test_setup('quick', exclude_suites: ['slow', 'thorough'], is_default: true) -add_test_setup('slow', exclude_suites: ['thorough'], env: ['G_TEST_SLOW=1', 'SPEED=slow']) -add_test_setup('thorough', env: ['G_TEST_SLOW=1', 'SPEED=thorough']) +add_test_setup('quick', exclude_suites: ['slow', 'thorough'], is_default: true, + env: ['RUST_BACKTRACE=1']) +add_test_setup('slow', exclude_suites: ['thorough'], + env: ['G_TEST_SLOW=1', 'SPEED=slow', 'RUST_BACKTRACE=1']) +add_test_setup('thorough', + env: ['G_TEST_SLOW=1', 'SPEED=thorough', 'RUST_BACKTRACE=1']) meson.add_postconf_script(find_program('scripts/symlink-install-tree.py')) diff --git a/.gitlab-ci.d/buildtest-template.yml b/.gitlab-ci.d/buildtest-template.yml index 4cc19239319..39da7698b09 100644 --- a/.gitlab-ci.d/buildtest-template.yml +++ b/.gitlab-ci.d/buildtest-template.yml @@ -63,7 +63,6 @@ stage: test image: $CI_REGISTRY_IMAGE/qemu/$IMAGE:$QEMU_CI_CONTAINER_TAG script: - - export RUST_BACKTRACE=1 - source scripts/ci/gitlab-ci-section - section_start buildenv "Setting up to run tests" - scripts/git-submodule.sh update roms/SLOF