From patchwork Wed Mar 26 14:39:32 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 876387 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CC0001F3FD9; Wed, 26 Mar 2025 14:40:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743000003; cv=none; b=UO+98zPAVIl2ppo1VI9eeAyJSEhkN5DUDHZc/Hm5Vtu7NY4yqQY76cAXhR8+F/Mu6VXOuLASVSO+AO+5GQ9P/uuSJY7kOgtAci0YoJmEfsq+nSWln59MNXDuLgCcDT3sCDowZm2z7O5vP6KbB12qH/rgoiftdUVxMHEa96q1Wfs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743000003; c=relaxed/simple; bh=MjetRzEw9atYbiZV33wWHMWx8SJT7X1CSDA/az7euos=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=IAo7jPVKI5YIczPHMPezjv9mP+8N/HwD23ZafXh/8neSAqoa8P4SxtQ6MENJJfchgmZ9Wwcr7JPAUYkxHMr7tcuzN+h4DLysXG6Ht1jXvFeqYtlzomn3C7rHhXsNQeEWez5Q9SaAqn71+SLrQvNsNKiE+LXaF6qaTODn8HnjfWs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=eoIGKs4B; arc=none smtp.client-ip=209.85.128.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="eoIGKs4B" Received: by mail-wm1-f47.google.com with SMTP id 5b1f17b1804b1-43cfebc343dso53476935e9.2; Wed, 26 Mar 2025 07:40:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1743000000; x=1743604800; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PmNfwSAKSGPZhhRnskxRS7VGBq4lfQUQS0GhmNutj3I=; b=eoIGKs4Bz5/nEYqk9/jb4H4S5rbL16Wt8vx/ud7g+6q+E+kIbakJgIV173a5x+BiQC md95VF83pPdn2cMmuoCMTN0DIMxwMKnTP0GX00sEwc/Bnih+ucpL4D6cIKJDdzRjngl1 AXeEYlWEw1IrfLqMbmLcA4CslxgRsAhlTBVubxboHTG/l6XBvJvOF8c9EaXO4eJgYIaJ gka4KYgPx5Id7k+PM14fT9dlgusQjSN86mxBnOKRWy4jqVRVkLpdETZ2c5T3QKnu+cwy W6ur6wLCP+fRY+gaaYOjgJwCMMpMUpNDTvtEnxUUr/jDM4QAI3RcVX73PDaXhzg9Jv7l ehjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743000000; x=1743604800; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PmNfwSAKSGPZhhRnskxRS7VGBq4lfQUQS0GhmNutj3I=; b=HPfSK0sZCnk7dN6GJwKj8GPmUE9SBgEzBJVQfmRQAnb7v66zWKAOBALL2JqNuFDedi zF8kizRPi8vVVye31zy6de4Rn1Zvf0DL2XPGpPaz4Im6oqMaCVeDX+C4+GdUrlzfPWJY DFfWLtk77HnVp9vY1T0Sy/OCQFDP0NYAG40Gck5XeK5FI97UhiPqhbI+kJ0ZlnUJuxTJ syVc+MJEdxCFYXu/cJJhZi9BDSSj7Ajz/T6pAPN7REh79ZOKkvrg8XmBZhID+zg1G2Ky elrAUVkM7tlzY3zaiVYbgwXXc2/+whsnxtenxHV/uzclIRU2ifodsuQIcX8JmjwkeEWH kAaw== X-Forwarded-Encrypted: i=1; AJvYcCUJovPw0D0lNlMsVyhbaAgoAo9dPf/1JMAbXojkobtddbpClZ0xvUfCUVRi40EkC+Rt4QPnsCEqn/5o@vger.kernel.org, AJvYcCUVVZBb4OzelyXq1vk9oW7embGV1zHEMIA5vN3UsSnbXgRTuUj71TFKscKqHzEQr9S2agom7X9RsVjbh2fc@vger.kernel.org, AJvYcCUX4r+2x+WJ81ucjuR8J9ZJVu7Kv248q772dj+//stHYwfgruw+RIz1UZDYjZwPsltcsgVf34uRy3i7@vger.kernel.org, AJvYcCWFHHKnXfljuKb3W0fy3VUm/kHJzyGvIteFKeL5qykDeIAguOpsFE/+Ui7TcWf18qzT4gnii6GpuTnc@vger.kernel.org, AJvYcCXDlBhzXTE057sX3g3+2ubjpyn5xSB5BBhjZ0quPsmFZFXjVz35VRfEhQW2mdIbFvJ73WdB4M2XwFX0yY7r@vger.kernel.org, AJvYcCXKJWyuQbQprPVpbhWeWR+AiPwPuETdq18snS73hq/Ww/pBed7blFzXDw5YY8vCUsP53PiwBH6h72NrPg==@vger.kernel.org X-Gm-Message-State: AOJu0Ywq3yTz6TrbhREg/CZ7ngKcwPwj8hMwOmOo8g8OsLUoPWRnIY4p llc3mTPBiRv4vCrGGeChHM2XeJU7xWawMKtfpdDXlXcYjRfCfgqU X-Gm-Gg: ASbGncuOKbaJks0clplkd7Xw2dN2DWu5A95pIpC7z7qLpt9EV+z5VPdpNWTlqtopQi6 DecXN8pb9xkpI58S78m0qcI+kNh0+7o8aubJ2dqIGAzCewz9tMYq1mEROCGEQJSfqlMuGiTL+a3 pz7G5Yc8pvjI32g0H+Vb5ocYrHX8dly9IR0yqoxZTtKxZ3WEtBfI+i6tavpYZwr4FQX4M77q0rG n4t3t+YM2khPn+7kvFuHysF/HoE2nLI15qwOrt7B7bQj/1wJobw3DA4cxoqj47dIYy2VRny8r3l BktPmtSTSivRGHPZ8/0ABCWTXYU7q32mazyGTj6ozQlbfnRamwTPN9Zt5kaI4lRj0F0l X-Google-Smtp-Source: AGHT+IFW4brLWtC9uniriyV99C+jcMPdP/8oJA+VeJMpM/RrrFNh6VS98vM0nsOkR0ZMiWAoC4oFKA== X-Received: by 2002:a05:600c:3c9a:b0:43c:f4b3:b094 with SMTP id 5b1f17b1804b1-43d509e189bmr202063825e9.6.1742999999885; Wed, 26 Mar 2025 07:39:59 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:e63e:b0d:9aa3:d18d]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d82efe9b4sm3891885e9.20.2025.03.26.07.39.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Mar 2025 07:39:59 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ulf Hansson , Linus Walleij , Greg Kroah-Hartman , Jiri Slaby , Magnus Damm , Catalin Marinas , Will Deacon , Wolfram Sang Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 02/15] dt-bindings: soc: renesas: Document RZ/V2N EVK board Date: Wed, 26 Mar 2025 14:39:32 +0000 Message-ID: <20250326143945.82142-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250326143945.82142-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250326143945.82142-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Add "renesas,rzv2n-evk" which targets the Renesas RZ/V2N ("R9A09G056") EVK board. Signed-off-by: Lad Prabhakar --- Documentation/devicetree/bindings/soc/renesas/renesas.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml index 3e61ce372a57..3e3987c9a82e 100644 --- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml @@ -553,6 +553,8 @@ properties: - description: RZ/V2N (R9A09G056) items: + - enum: + - renesas,rzv2n-evk # RZ/V2N EVK - enum: - renesas,r9a09g056n41 # RZ/V2N - renesas,r9a09g056n42 # RZ/V2N with Mali-G31 support From patchwork Wed Mar 26 14:39:34 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 876386 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 15E121F4275; Wed, 26 Mar 2025 14:40:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743000005; cv=none; b=YxI1MrKs9Qg7y09tkOQfiOBhZJqUZFHplQuqEevfnGc7SPENS/pA5pdIiS/2pFO1Om8TgmDfk3H8z9HwmcfQHCgQkkUD2LyX/qU/ENa9ZBW+g1dfxpLZSIZPelx5I9K5giKem8pSdiXHXFrl5TGpcQOKkEXlKjlDuDjxmGDRizs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743000005; c=relaxed/simple; bh=dUEpjLswo6O1sHM/kRMnODxM6mYbltNZtsN1kqKu8Cg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fLUbanqY8boyodCjPqdEFe4aYpBRAjAJTFe4fdtuByayjem878K1ZeFkkYZ934xwMxWmQ/dRgh53J0tjkpmqApvYMCl0/aYFQiJcdFKiGmzgwGMdR4D3iLCU4Igq3ABsyweNVGdPRf9W9Gc4dAeAOS+q8K503w2ipC/2Z2MJGS8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=krbFBxrW; arc=none smtp.client-ip=209.85.128.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="krbFBxrW" Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-43cf06eabdaso64498855e9.2; Wed, 26 Mar 2025 07:40:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1743000002; x=1743604802; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sAi2z0HFAw6yQz/HIvwLQqMf3Ner8YYOCdSxAbTT0TY=; b=krbFBxrWs21TjmFjbdAxsejou4KCqLFXamjs0ODGnU5h2Na5rSvqrITw/UYOrG8eUe UaTtPkYrga5hKMxRpd1Od9YBJpv6IO5PK6PuwYUbKqX2wrnYMhnQS0LUOpzC4raQl4fH plY9dJ8gowJZ+q72LV1uQCMnq7DMvpOhP0xPmeY31szOGOjUE2BbZsk9yEN9+Abo4ItT 0bD45UjRohiAWvvaJHi5CZ+ijLdpBjPCPIcWMQZjsRcV6EPrtmz6K+0iepOdZZhKfif9 Q2Bx6Fb4UZWxdHLMTbGWSLu5UYoxuCL6gDakaq0HPG9RhxWjjYsiqS4MrvOE1090A9nQ lbMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743000002; x=1743604802; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sAi2z0HFAw6yQz/HIvwLQqMf3Ner8YYOCdSxAbTT0TY=; b=KAnKTyQuqF8KV++DyMOwaYz0SKQsNlxQr1jogHkPvrND32N9GMT41/45s0FcbR3Tsm 9x2cgg2kxMVjyd/gfqVW4y4RAoJ4PG3v5kSC2aP8ju0n0yOVJ5db8TB7OTjqTkO004MB 76rNeuCvmEnIRFxMq9K4iFr5pEBl38VkMxjbQrsthdtIdCCDTZvLXzPpv7qW542NWO7h bHCPDWMcuDegKVc/JvmHmqEVPSUdladvsAkbt6rmlmQrb9a6/C26sTraRMW/wGLzOaKz GfcAIPRvsn3xGwyOCSjJvW3PcvdUdHKFYfywIxvUSG0Y54s62EfiCxTt5hFhInmCTXHc xKjg== X-Forwarded-Encrypted: i=1; AJvYcCUp8e3WQ+psFUiOeSTYRPouIyLkcvVScbbWjGgyIQgqb/CCbi8hhXPZXj3xSKW3dNWRh1xvil+2Fu4H@vger.kernel.org, AJvYcCV09wYZOrB6YOIr+aTNbeeXVUiluswDBOuqo56dk8Lnv+xowHqv6j+7LJyY16RnhZ48QEJcEUE6k7akpCaI@vger.kernel.org, AJvYcCV1AHuHSEx+mB9CJJDOj+VlkwICKVjLB49M2enpUKR/WNanlT1qIOJp9WfyTdbb8Gq6DvFj4USvYqlmqE5A@vger.kernel.org, AJvYcCVnww2gvqgaFNRRkdBApY5aZImJDT5Wo4JJNDWObaBsuM9k8K8CTdhaFcgp6O7ejYgdovV3E+MchsOBGA==@vger.kernel.org, AJvYcCWS4qqrzY7+VF2fZIo5mcm99Y0AIxQiHeodQsijhSCkgDrix3rfej/2ZiuV3CYoetG71kE7EmSs7ngO@vger.kernel.org, AJvYcCX4ZDX0w7jNjS494fnH2/GJntXmr7B2zafJOk80a6DghQFpnZyGBV4ifVZg0AysphWNyYv7jounNCWl@vger.kernel.org X-Gm-Message-State: AOJu0YwBMcrT81o7Im2UuVDiSV9ZpBchePJjuNUETwUjOAairESqTsC/ SbflRFMLz3XevsWctFNM3yGlL48doJKdkKZF4bUbsJkHuEUpZvgY X-Gm-Gg: ASbGncu+aqqTzgtrL+BeV9q6+GkgHK8vnCFZbXntFUe2T6AMgQoYpcBnKZChHgDTm+c ADJQz7YeQ4jRYTfqj5Q5fWrvOpFSorS1uolfn5jKUw2d1LVJnpqlLxsQg5Y7QIL/sLCosX/LtZs PEHNV+6VE08kqj4HJl5hg286hrvDu43O4Drj8fKi+zOPEbSHMKeK5zWfCiVesHEHuZCOd03V7h3 qIkqQFy/Au4dMjmzRRrCPNQATKDnK6WJCKBPxpz+A/shfXtQeBTM4OWa3UHuIw0JEDPS/E7hjod TKSDIWpigFxEMidCyQa9klbCVfPeF2v8CJkHvPNp44hX3Or3GfcRL5CcfMW6l7mawsLkYMtJrOV 5UxQ= X-Google-Smtp-Source: AGHT+IFZ6nLqJWKZ14xhUWYOlK3y85b3j/TwiAL0mkfZ4vDmpuUVradIQ80XoUndBnn5voQ7NeEBmQ== X-Received: by 2002:a5d:6da9:0:b0:391:3915:cffb with SMTP id ffacd0b85a97d-3997f93643dmr19265750f8f.43.1743000002228; Wed, 26 Mar 2025 07:40:02 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:e63e:b0d:9aa3:d18d]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d82efe9b4sm3891885e9.20.2025.03.26.07.40.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Mar 2025 07:40:01 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ulf Hansson , Linus Walleij , Greg Kroah-Hartman , Jiri Slaby , Magnus Damm , Catalin Marinas , Will Deacon , Wolfram Sang Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 04/15] dt-bindings: soc: renesas: Document SYS for RZ/V2N SoC Date: Wed, 26 Mar 2025 14:39:34 +0000 Message-ID: <20250326143945.82142-5-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250326143945.82142-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250326143945.82142-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Add the RZ/V2N (R9A09G056) variant to the existing RZ/V2H(P) System Controller (SYS) binding, as both IPs are very similar. However, they have different SoC IDs, and the RZ/V2N does not have PCIE1 configuration registers, unlike the RZ/V2H(P) SYS IP. To handle these differences, introduce a new compatible string `renesas,r9a09g056-sys`. Signed-off-by: Lad Prabhakar Acked-by: Rob Herring (Arm) --- .../devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml index e0f7503a9f35..c41dcaea568a 100644 --- a/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml @@ -25,6 +25,7 @@ properties: items: - enum: - renesas,r9a09g047-sys # RZ/G3E + - renesas,r9a09g056-sys # RZ/V2N - renesas,r9a09g057-sys # RZ/V2H reg: From patchwork Wed Mar 26 14:39:36 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 876385 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C72A71F5423; Wed, 26 Mar 2025 14:40:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743000008; cv=none; b=HwG5XfDlZ3+0d5/5KxR9eF3aKoJl4UyukhOdi8WkN2hLFoo+mfow083rwMWCXuMMyooSZnku1P+GWiUl/02e+TSyEOSjTnc+zptjSD9HvcDu+sYv7iimYxOsy/5BU5hbqZgZC2p8brEG7+YD14kuWyM1ozWAipFnSfhnRrA8AnM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743000008; c=relaxed/simple; bh=CBjahAx4C/1ROi+dFt27DdZY43Juz4Iuu0Iih0QWN8s=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=rvCd3K7WiXOLgkhm1OaHIAgtKnz7icnePaw/6aL1aAgeJAZzW2oUWejpVbUqVQEu2zIGDpvIfFDMWM2T5hcHOdxZw4tzqqrMqTETgeSgsqrG0HlP07OIHD9g3v1gcIX2myvfXK6Ys2ZuIbMphSEPmOblaCFyrwqlg5F8atRd6I8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=K5N0hj2m; arc=none smtp.client-ip=209.85.128.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="K5N0hj2m" Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-43cf05f0c3eso45183595e9.0; Wed, 26 Mar 2025 07:40:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1743000005; x=1743604805; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JBeXjQIPHX/DPtw6MHzZgLXu1uaUvVTtJA5pM8jD9SU=; b=K5N0hj2mafa+G++tAyEbG/IJYwqK8fSUPP5IlSHTjASYVyh90co7pJ39HK1iinC52+ 6D1WO2km6ixPDmKvu/x0iPoWQ8LH4rxYvNIXBFYQABEp5vZy/5wn0AEdWhO1nFwLnZmH u8vRvgzz99ztbKXYj/tQM3X4td56i5li8xCyIZ9N+fZOnYEVPPkH4MQoMZdMRaSU8Lln sK2LM4JV5X48jD1p6ljARG7uyOhw/Z/dPXH3eS+FvfCro2kvDHq+dOIWw6f6wk4AuOR+ PP5Vc4ILT4S4LLi2hlYdEGicpTh3S9/HlrsJXcYIXBjNmb6uOL87KEG2C+MHPWKktHTE en6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743000005; x=1743604805; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JBeXjQIPHX/DPtw6MHzZgLXu1uaUvVTtJA5pM8jD9SU=; b=EhOQiAo+zOT5niYCSorW/b6kDL4aXVfbXC9xFggR4cKgu7Qk7q1IQBWCLz60vcmpkl ocLnZZ3tBOjck/aXp648q8Ranhmk3O3WDBnKcGs3cqZZreYh1puiWzYItdTkt0pxqKHK o45fX91TM0IExTM6ZVnDCM+YgxdJqLzabBaXlEpRnr1ZnHJvYls3p/6KervDEo0bwg/u C2g15bwPqsbgAfCXjeT31EIaNuve9d5gEq9VLjj3FVziyI4H2zPPcjAS+E17W+tkAoQw DzsRC1XP0YvJ1i2XbHEEW4t9NbAPDI0eF8QIzs53CXIQCvTa4Tw104A1aQR5QtgNc0Cu P21Q== X-Forwarded-Encrypted: i=1; AJvYcCU930iiavgSEtmDuPbRhxKqRhVvZb3z75ct2XWD3/kyts1o0AoYtjUViejinA/5Hm39D/6R+cIMFk2Pgz1M@vger.kernel.org, AJvYcCUHE3RAI4LaWQ4i4zRIgZWpwMDJGAFufGzxTO3BSWwfLVbkvfeF1Jce5wkm1kdHTCQPu35Nf8oY7rdK@vger.kernel.org, AJvYcCUPI6BmjzYuwRsdgOJlqrkFBS9NZfh0OHFlJ5b3AARLflQvZuLSKN9NM+wUQ8z8GJLEe8NUgA2/m5//@vger.kernel.org, AJvYcCVVTaQUboYm1isIre/sFU/aHN9NXhngeycvHJnQPlMhsNGqAexAjR4iPSWhI94OSiYtXXvG+GDIQBk/C6LO@vger.kernel.org, AJvYcCWUb5MQwiiOVlvkj2uUL8+tX79qE8vKgE0qiKUcg1dgLRmTUTVPTNTN8VSp2TwqOt4kKVem+o0usG12@vger.kernel.org, AJvYcCX0sqxSHxTES24NIZ3Siryw7y19Re0MJPeyP0AJJgihvkuRJAdp+agRKdCNJYGuGxCF/+BRWwSCtXsltQ==@vger.kernel.org X-Gm-Message-State: AOJu0YwRcRs9j4mSQGuvdTgECNkq8tNRlUw+nPvL6q9yrvdvj1/M9rKc h1ub+duayc6naND4FmoEHtLY8li0LONQQnzDu2xAnRHi+AHPO77i X-Gm-Gg: ASbGncusm52mF1/z3MVn5d1eY2luM0DoezjuGhcusMSKk+iqz7niLxum6kytbb+B4tc 96Uyb5FvkwjPont09WCRLiw+OmaCfwT68Kt7+fw7MpHnACBoPdAi0Ux5KsTG7O7FMq62v7uoM8s d8tTebaliHV+mFilKpr2dg4pQ3n6cljy4f/IpzEmAGfQ39NKRIcfHau/xMvuOrRR5CRKJ5UdWTT mb7x1yYxOcOTSeXkc3vddKgjrpsAn4WrFm5l9XsvCcce7QDpE9Ne3hjkKg1pUOe9OI+Om4dDWYa vCRIPWqaF6u0OlDVo9+sk64MsESYtTBSmBi9LTXmGTZWJ/bWuSanTl+Mr43pn9ImSQCp X-Google-Smtp-Source: AGHT+IHGBMJEO8+R7DqUEz8hzHGBbhkdsO5wRHl9G7dczHcBO14XnWfcboERE9FalZfCBAPnpCJUfQ== X-Received: by 2002:a5d:59ae:0:b0:38f:503a:d93f with SMTP id ffacd0b85a97d-3997f9336f0mr21916870f8f.40.1743000004776; Wed, 26 Mar 2025 07:40:04 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:e63e:b0d:9aa3:d18d]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d82efe9b4sm3891885e9.20.2025.03.26.07.40.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Mar 2025 07:40:04 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ulf Hansson , Linus Walleij , Greg Kroah-Hartman , Jiri Slaby , Magnus Damm , Catalin Marinas , Will Deacon , Wolfram Sang Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 06/15] dt-bindings: serial: renesas: Document RZ/V2N SCIF Date: Wed, 26 Mar 2025 14:39:36 +0000 Message-ID: <20250326143945.82142-7-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250326143945.82142-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250326143945.82142-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Document SCIF bindings for the Renesas RZ/V2N (a.k.a R9A09G056) SoC. The SCIF interface in Renesas RZ/V2N is identical to the one available in RZ/V2H(P), so `renesas,scif-r9a09g057` will be used as a fallback, allowing reuse of the existing driver without modifications. Signed-off-by: Lad Prabhakar Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/serial/renesas,scif.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/serial/renesas,scif.yaml b/Documentation/devicetree/bindings/serial/renesas,scif.yaml index 8e82999e6acb..24819b204ebf 100644 --- a/Documentation/devicetree/bindings/serial/renesas,scif.yaml +++ b/Documentation/devicetree/bindings/serial/renesas,scif.yaml @@ -86,6 +86,7 @@ properties: - items: - enum: - renesas,scif-r9a09g047 # RZ/G3E + - renesas,scif-r9a09g056 # RZ/V2N - const: renesas,scif-r9a09g057 # RZ/V2H fallback reg: From patchwork Wed Mar 26 14:39:38 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 876384 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 88C751F7545; Wed, 26 Mar 2025 14:40:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743000011; cv=none; b=Ur78w6MJKT3pXIUZHG06uyrvsXBai8QoknXpVoXqbkyMJdahM7s8J/b48PwtmKMyYhmVpz8kNHFNIpphdKDbpO3vUyuXZbVGqXuB0oaNcgpSqBURr2Qr9cIc/g0tDYqDj8s9WtjLYY6eq9TYk9+H24LQTq+OjUEIFaH4BdFCLXQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743000011; c=relaxed/simple; bh=3kQzsMrakU+78qwTYSDqzRTtgKZamrZgIc8SOH2DHtc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=RzRj2WejwBI4IfeihN8cqofDfBdRkBmOPcvycY+63gaR32RCnHnrPS1R/e76PESR4kfMRJo2x6LnPb2mBYQJB3IcH3XdcW77cnEYp+b5gZPy0xCfzqdTfoGHbdZvvX6brpuTc3NV8dkOQkT3IaNdm2rY4Sfg781lsO43VkMpoL0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=lKkLRPIp; arc=none smtp.client-ip=209.85.128.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="lKkLRPIp" Received: by mail-wm1-f42.google.com with SMTP id 5b1f17b1804b1-4393dc02b78so50713065e9.3; Wed, 26 Mar 2025 07:40:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1743000008; x=1743604808; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Do+c2jt3ez/mwsIBzhfn197DCYpfGLyk5Y7H1RPahPg=; b=lKkLRPIpXTYr+G8vvMEi0WSvGOZqwCiYXGvpAPcs1n+4Ftc8oe5LNJY2sfmmTLoXTL eGUnPRBefrEe+37vTio/8acAZ0vYYIskEP2wiEeZZLCHebfz82oFChQ+EWnRHFv8b0Lk 7VspsCRl9tGe/oUFKh25v/dGfqkx97OfJFxLVu7yDniH6ZFTz+ZxigNTrM9jkahZthNB 6KHLhPeb9TDYxUEZ7ewsClLC8SnFtiqDSVdnR66K7GVOir28v+pJW9yxSxIKCpVPX7Xj 4h6P8qe1L+6jZ+AkcPeexWRotB/1ovtIZF/7z5rds0uenypytUVClzlAiEV7p2UpGGQe ay/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743000008; x=1743604808; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Do+c2jt3ez/mwsIBzhfn197DCYpfGLyk5Y7H1RPahPg=; b=DYJbK/Lz89F10S7QPVwGKTBsEKHiDuzEUGOcboDrxjwVTFo0YjfwasUPEnmf0o1YPc Tz9Bief1AXzV5fTXdu0/jiSm3zPv4CVDBMAcPeyPUlnV37/mG8jhwlPBw8G+9i9m9bfz OqNMdUrzqCc1F/S/0/0v/rtmA81rBYZwDNko9QT81zdqYSvpyrUPtZyoqdTf/4wt+aiT mu9naUuow0YZDF391AWThklhNWEXa9Ds5ZWUvUrbsaxyOm15SaZJ5ZQWY46+pyPWCUN3 tQksAhyj5FfhfFsr7PEvx0PLT4zry0LtdrBVf6ay3RvuMiuBxsHQ1i0mTSrAKs9AFlgv pEvw== X-Forwarded-Encrypted: i=1; AJvYcCU/NnbViYMbqBJs+PKK9LJl3JNA9zsxzcs+014YGhW4eAWF2MAjv+trA7hJHYe1UsOX/TmUWqitZhiO@vger.kernel.org, AJvYcCUqMhhJLrGd88KZWWnQRd/mjcj0V//YL1yfOtQiYNEcSlyLg74dYYccbKLT2MkWGha7fJmrIAVt7CHexZ3f@vger.kernel.org, AJvYcCUvGFoAT0RrIeQnKZBaosbQaovd4vsDmMJ4dkW1X5T3lXvjB8KGxt1MojGm/JdIkH5tEqHAvumwPJbkPA==@vger.kernel.org, AJvYcCWjiuuquqAFsiJ0ai58jtFDdAIeoeNJctznOv3ghM6EfXL1gFbpB9/R7KVwKprZszyVECOdabW6Wtmx@vger.kernel.org, AJvYcCXDxZYhVdyxk1DUgPulBYezbBLU1X1AyL5/6QJkFTJg6SjYg43HCcndPzPybWmAET+HT2/iI0CGO2F/hRvm@vger.kernel.org, AJvYcCXOb5/cW161KnFqBhihemyaI5X37BtJcqZPx5dxCVnqaAKD/79zFgWXt9Dm0fRw2YYeb0JEAc6Ujy5f@vger.kernel.org X-Gm-Message-State: AOJu0Yw3wMWn79/Nhmv3U4LXztDShOvRkpg3Lewv8gT/C+6bNMN/754+ O0ioQBXvts4w80FXJmPN58BDfLitktt7cNhHfh2tER6KSLCXBP4F X-Gm-Gg: ASbGncvQXqQdvcEipydVNr7hkSzFoUkRF0FIEXjuRTsVBepLv5Zd4lhCSMYM9U+PR+O qc0fFwi/S+Hug647CA59JTtCc708+AhbBXDZsqZu4L8IVA1TLe011pzYQ2c20ByuRrOy2zsGgwk z++wRFDaYCOSvxHbzc80z/aGfu7D24i88YT24K8fFqmNT2bxAN6dVmVVT8U+Ka4LatFPqPsZDLS MhrZVU2JlrQewfNNwo7vlY1F059NXVI65PiMDnfsHqmuVl7yL7gCQnwGNdGmgzAXkdneBJHHiMi O7cXhUIX8q2gFfbwdXYLwecj8NvVXy+m55gEBznoxT6NxOuU5+s3d29AlGAgeKx6NQV2 X-Google-Smtp-Source: AGHT+IH7yjSccBFCk7mQThkh+BIzoRh/WlJjnbk5vOyrqffw/vRJDSY1aH3bAENm+vJkBJ73vzMiWw== X-Received: by 2002:a05:600c:4584:b0:43b:cc42:c54f with SMTP id 5b1f17b1804b1-43d509f433amr208304605e9.14.1743000007409; Wed, 26 Mar 2025 07:40:07 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:e63e:b0d:9aa3:d18d]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d82efe9b4sm3891885e9.20.2025.03.26.07.40.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Mar 2025 07:40:06 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ulf Hansson , Linus Walleij , Greg Kroah-Hartman , Jiri Slaby , Magnus Damm , Catalin Marinas , Will Deacon , Wolfram Sang Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 08/15] dt-bindings: clock: renesas: Document RZ/V2N SoC CPG Date: Wed, 26 Mar 2025 14:39:38 +0000 Message-ID: <20250326143945.82142-9-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250326143945.82142-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250326143945.82142-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Document the device tree bindings for the Renesas RZ/V2N (R9A09G056) SoC Clock Pulse Generator (CPG). Update `renesas,rzv2h-cpg.yaml` to include the compatible string for RZ/V2N SoC and adjust the title and description accordingly. Additionally, introduce `renesas,r9a09g056-cpg.h` to define core clock constants for the RZ/V2N SoC. Note the existing RZ/V2H(P) family-specific clock driver will be reused for this SoC. Signed-off-by: Lad Prabhakar Acked-by: Rob Herring (Arm) --- .../bindings/clock/renesas,rzv2h-cpg.yaml | 5 ++-- .../dt-bindings/clock/renesas,r9a09g056-cpg.h | 24 +++++++++++++++++++ 2 files changed, 27 insertions(+), 2 deletions(-) create mode 100644 include/dt-bindings/clock/renesas,r9a09g056-cpg.h diff --git a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml index c3fe76abd549..f261445bf341 100644 --- a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml @@ -4,13 +4,13 @@ $id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Renesas RZ/{G3E,V2H(P)} Clock Pulse Generator (CPG) +title: Renesas RZ/{G3E,V2H(P),V2N} Clock Pulse Generator (CPG) maintainers: - Lad Prabhakar description: - On Renesas RZ/{G3E,V2H(P)} SoCs, the CPG (Clock Pulse Generator) handles + On Renesas RZ/{G3E,V2H(P),V2N} SoCs, the CPG (Clock Pulse Generator) handles generation and control of clock signals for the IP modules, generation and control of resets, and control over booting, low power consumption and power supply domains. @@ -19,6 +19,7 @@ properties: compatible: enum: - renesas,r9a09g047-cpg # RZ/G3E + - renesas,r9a09g056-cpg # RZ/V2N - renesas,r9a09g057-cpg # RZ/V2H reg: diff --git a/include/dt-bindings/clock/renesas,r9a09g056-cpg.h b/include/dt-bindings/clock/renesas,r9a09g056-cpg.h new file mode 100644 index 000000000000..f4905b27f8d9 --- /dev/null +++ b/include/dt-bindings/clock/renesas,r9a09g056-cpg.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G056_CPG_H__ +#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G056_CPG_H__ + +#include + +/* Core Clock list */ +#define R9A09G056_SYS_0_PCLK 0 +#define R9A09G056_CA55_0_CORE_CLK0 1 +#define R9A09G056_CA55_0_CORE_CLK1 2 +#define R9A09G056_CA55_0_CORE_CLK2 3 +#define R9A09G056_CA55_0_CORE_CLK3 4 +#define R9A09G056_CA55_0_PERIPHCLK 5 +#define R9A09G056_CM33_CLK0 6 +#define R9A09G056_CST_0_SWCLKTCK 7 +#define R9A09G056_IOTOP_0_SHCLK 8 +#define R9A09G056_USB2_0_CLK_CORE0 9 +#define R9A09G056_GBETH_0_CLK_PTP_REF_I 10 +#define R9A09G056_GBETH_1_CLK_PTP_REF_I 11 + +#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G056_CPG_H__ */ From patchwork Wed Mar 26 14:39:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 876383 Received: from mail-wr1-f45.google.com (mail-wr1-f45.google.com [209.85.221.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2020E1F3BB4; Wed, 26 Mar 2025 14:40:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743000014; cv=none; b=MW+FuABdOV7+3S7ymzBow1ci8phNrF4ubx162aVOUNcnXYN1OajH7Pk8GXiSZYp8GpIDmdMlPcniMPluCVG2z0HzFYofq39kCyQY4NnvkglEKfXCRVR4i+xvQCsr2BNcbZV0kfumLISPZMug8RKnPNr2xQMtM1mACUs4TV7Z3Qk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743000014; c=relaxed/simple; bh=CrSZzbNupfiCxBmSg0vAgeWQUShwmv4joaP4OfGWSHQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=oeRaD6jEsRbPBAQ3pnNQFYNTt/c4dxNdbrgLXVV2qzGw5GFuFoMxgWF2QDM9lHainMqOkYfCUwbdTI7SvvdBa5elHXgd1/pVkpaRDAGyqIy4wT2LbVBlGlbbBGXH5QKpexzTvER7Nyw5I0bCpN+CFBxz1AKQis2hMlFfFX9zwI8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=bs6VsrTP; arc=none smtp.client-ip=209.85.221.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="bs6VsrTP" Received: by mail-wr1-f45.google.com with SMTP id ffacd0b85a97d-3912e96c8e8so3885372f8f.2; Wed, 26 Mar 2025 07:40:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1743000010; x=1743604810; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GUzZZKdRA/nrtwrVMsRSl600s/LtFe+i4gqc1g40AFI=; b=bs6VsrTP0dXbZ2PaV3Tj+KTvuOZjUUcObQbpRrOUuXIOErDSFnR4DUZUo45gXJ3I3+ q0HZuoBhhCBtw1ZGAJGRyg/F4y0lD2StpmuhA2wNSstM8rJsZNZOMY2A/rL/nyXRmzHH WvpBVnsav89DsJ7vCaKjSphw+Sb8DO3iDHrfIvEK/XJlOfJOzUF+LL9lqgLojD46Kef1 Xzy/pWSED4VkbjMZwdt64RWbDwoXqlz7AWOUrGHFcu3wmZgWhRrt1kHFJ2nK7e8Uu3gY 7XVbNAj4jOMU3yjbtXR3Aeo3TpPpbgy6ABrLsYxvBVpJ01ZHND7pdVchref12XrVGVaY kHpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743000010; x=1743604810; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GUzZZKdRA/nrtwrVMsRSl600s/LtFe+i4gqc1g40AFI=; b=q+kaLIpfyqWah8Zm9a6khl/OohJWkFFwL4sOn1ikxDKCU9BxFgCVEUfI3fpMYf9m/A +Q4gVAopCtuDrwmRbDXI74w5FT6eSaA8NyenqwpCmjw13ve2omYTFlzNRueTxw2wCMhT S9ojncWsJtWpN2FNO50SPUCHjXQRvijaBvyvSy2Wl3DPuJ+wcxD0QyCi5rH8BhYLnR5d a9JLw7zu7FEdgBboPIarO1m8SsqUAK3OxLkFIu3vM6iL5eQM46789CI5ntfihI1oQ4Hp 2joJt0utJtwxvCHxiCzKFgF9aRbmjjZoQNBdwljTINgUMa1hjgzyJsw2S1clb6u8c0xn AWJQ== X-Forwarded-Encrypted: i=1; AJvYcCUMJU0zokb4dKweppXCJ2stGu3oyhQCakorIMiEMko1R45Hmnf5iSeptVIcFRxSgG0gYvLl8xzYUcx4@vger.kernel.org, AJvYcCUgpocFkzvtPpeEWsc3cZKJuV54vtwh0FaWdOSAVEEKJ2IMrZSqgex0J8h8a9xGZDmp+SZajvsonvab3Q==@vger.kernel.org, AJvYcCUl3tysNYaGx7x0HpKK61A2YVQbZxIxZeg8d3PvFQKqtt+a2+3FZF50m8FJyJVhkjG7oME7ZlWWToEOT4Gw@vger.kernel.org, AJvYcCV3qx8O39SdGCKms3s6dvHnNrbEBP4WmtwvyiXWvWhkA+weTtOCjmnYw1Gfu0UmCVzX5xwiMWp6KtaT@vger.kernel.org, AJvYcCVtwH7AeZL/amDR0Lk64Ff8rt1z+tWg4L3SLBPJ9EMo9ehkwM84NxsQApuHoN15UMEtPq2WsqBEI/uh@vger.kernel.org, AJvYcCWPJOoJX6f/zOWteXMQepOz55jc+Y+rHj4po7zPLFLPgj+I4U1woJUox5W/uKLePtedpEYI+/pNGdWxTy7j@vger.kernel.org X-Gm-Message-State: AOJu0Yxw/fT+NXr32rl+bhelOTCsXK1AFPPyxluX81oc7qDIOJi8/p8m 3kscamr/hE/sIgjzOMvvDB0x+D+Ukfipkwm30GLzV4LWrNQ7Hjwl X-Gm-Gg: ASbGncvg833qlsHlL1TfqjPFoQb151b4wDNAsRO3yn8JfloSthdF7+xIPf/hbyScpc+ D89TTVIlv2jewOnUftvAdAcxzACcdO2V+40tzJDfvNnL3hveVDCcOM238Aa8BSlYdid7AARjxVw 015da1kY2gH1Gvc+h0nVQMAtuuwHYCg1FBle+tgUwtI4hcqwFD+RrWRO7IRhXvivV+4jzQbUGv5 7MWfUPjAXa+zkbr7ZlGfMB7FK3T6WVrfjLXcM2hhlKj6lwsVlbCVaQqKWR1CHmQPldPrkMZuLnU lAUKo3PmGzf5rE1BRqUX6vsmG/5yzDL8lI8IhH3+XeX/4MrIkFKcvuNL5drNZ2GtV+1r X-Google-Smtp-Source: AGHT+IFEK+jlhPNvUrwlDVkGSbJqrzn40ggqtTSLr7IlAExJnoyHZvyqsCwFub0v2F1dz21J46ontg== X-Received: by 2002:a05:6000:2cd:b0:390:eacd:7009 with SMTP id ffacd0b85a97d-3997f92d09bmr17718923f8f.42.1743000010107; Wed, 26 Mar 2025 07:40:10 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:e63e:b0d:9aa3:d18d]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d82efe9b4sm3891885e9.20.2025.03.26.07.40.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Mar 2025 07:40:09 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ulf Hansson , Linus Walleij , Greg Kroah-Hartman , Jiri Slaby , Magnus Damm , Catalin Marinas , Will Deacon , Wolfram Sang Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 10/15] clk: renesas: rzv2h: Add support for RZ/V2N SoC Date: Wed, 26 Mar 2025 14:39:40 +0000 Message-ID: <20250326143945.82142-11-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250326143945.82142-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250326143945.82142-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar The clock structure for RZ/V2N is almost identical to RZ/V2H(P) SoC with less IP blocks compared to RZ/V2H(P). For eg: CRU2/3 are present only on the RZ/V2H(P) SoC. Add minimal clock and reset entries required to boot the Renesas RZ/V2N EVK and binds it with the RZ/V2H CPG family driver. Signed-off-by: Lad Prabhakar --- drivers/clk/renesas/Kconfig | 5 + drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/r9a09g056-cpg.c | 152 ++++++++++++++++++++++++++++ drivers/clk/renesas/rzv2h-cpg.c | 6 ++ drivers/clk/renesas/rzv2h-cpg.h | 1 + 5 files changed, 165 insertions(+) create mode 100644 drivers/clk/renesas/r9a09g056-cpg.c diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 5a4bc3f94d49..50c20119d12a 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -41,6 +41,7 @@ config CLK_RENESAS select CLK_R9A08G045 if ARCH_R9A08G045 select CLK_R9A09G011 if ARCH_R9A09G011 select CLK_R9A09G047 if ARCH_R9A09G047 + select CLK_R9A09G056 if ARCH_R9A09G056 select CLK_R9A09G057 if ARCH_R9A09G057 select CLK_SH73A0 if ARCH_SH73A0 @@ -199,6 +200,10 @@ config CLK_R9A09G047 bool "RZ/G3E clock support" if COMPILE_TEST select CLK_RZV2H +config CLK_R9A09G056 + bool "RZ/V2N clock support" if COMPILE_TEST + select CLK_RZV2H + config CLK_R9A09G057 bool "RZ/V2H(P) clock support" if COMPILE_TEST select CLK_RZV2H diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index 2d6e746939c4..f9075bca6e95 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -38,6 +38,7 @@ obj-$(CONFIG_CLK_R9A07G054) += r9a07g044-cpg.o obj-$(CONFIG_CLK_R9A08G045) += r9a08g045-cpg.o obj-$(CONFIG_CLK_R9A09G011) += r9a09g011-cpg.o obj-$(CONFIG_CLK_R9A09G047) += r9a09g047-cpg.o +obj-$(CONFIG_CLK_R9A09G056) += r9a09g056-cpg.o obj-$(CONFIG_CLK_R9A09G057) += r9a09g057-cpg.o obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o diff --git a/drivers/clk/renesas/r9a09g056-cpg.c b/drivers/clk/renesas/r9a09g056-cpg.c new file mode 100644 index 000000000000..e2712a25c43a --- /dev/null +++ b/drivers/clk/renesas/r9a09g056-cpg.c @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Renesas RZ/V2N CPG driver + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +#include +#include +#include +#include + +#include + +#include "rzv2h-cpg.h" + +enum clk_ids { + /* Core Clock Outputs exported to DT */ + LAST_DT_CORE_CLK = R9A09G056_GBETH_1_CLK_PTP_REF_I, + + /* External Input Clocks */ + CLK_AUDIO_EXTAL, + CLK_RTXIN, + CLK_QEXTAL, + + /* PLL Clocks */ + CLK_PLLCM33, + CLK_PLLCLN, + CLK_PLLDTY, + CLK_PLLCA55, + + /* Internal Core Clocks */ + CLK_PLLCM33_DIV16, + CLK_PLLCLN_DIV2, + CLK_PLLCLN_DIV8, + CLK_PLLDTY_ACPU, + CLK_PLLDTY_ACPU_DIV4, + + /* Module Clocks */ + MOD_CLK_BASE, +}; + +static const struct clk_div_table dtable_1_8[] = { + {0, 1}, + {1, 2}, + {2, 4}, + {3, 8}, + {0, 0}, +}; + +static const struct clk_div_table dtable_2_64[] = { + {0, 2}, + {1, 4}, + {2, 8}, + {3, 16}, + {4, 64}, + {0, 0}, +}; + +static const struct cpg_core_clk r9a09g056_core_clks[] __initconst = { + /* External Clock Inputs */ + DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL), + DEF_INPUT("rtxin", CLK_RTXIN), + DEF_INPUT("qextal", CLK_QEXTAL), + + /* PLL Clocks */ + DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3), + DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3), + DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3), + DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55), + + /* Internal Core Clocks */ + DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16), + + DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2), + DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8), + + DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64), + DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4), + + /* Core Clocks */ + DEF_FIXED("sys_0_pclk", R9A09G056_SYS_0_PCLK, CLK_QEXTAL, 1, 1), + DEF_DDIV("ca55_0_coreclk0", R9A09G056_CA55_0_CORE_CLK0, CLK_PLLCA55, + CDDIV1_DIVCTL0, dtable_1_8), + DEF_DDIV("ca55_0_coreclk1", R9A09G056_CA55_0_CORE_CLK1, CLK_PLLCA55, + CDDIV1_DIVCTL1, dtable_1_8), + DEF_DDIV("ca55_0_coreclk2", R9A09G056_CA55_0_CORE_CLK2, CLK_PLLCA55, + CDDIV1_DIVCTL2, dtable_1_8), + DEF_DDIV("ca55_0_coreclk3", R9A09G056_CA55_0_CORE_CLK3, CLK_PLLCA55, + CDDIV1_DIVCTL3, dtable_1_8), + DEF_FIXED("iotop_0_shclk", R9A09G056_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1), +}; + +static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = { + DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19, + BUS_MSTOP(3, BIT(5))), + DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15, + BUS_MSTOP(3, BIT(14))), + DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3, + BUS_MSTOP(8, BIT(2))), + DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4, + BUS_MSTOP(8, BIT(2))), + DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5, + BUS_MSTOP(8, BIT(2))), + DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6, + BUS_MSTOP(8, BIT(2))), + DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7, + BUS_MSTOP(8, BIT(3))), + DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8, + BUS_MSTOP(8, BIT(3))), + DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9, + BUS_MSTOP(8, BIT(3))), + DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10, + BUS_MSTOP(8, BIT(3))), + DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11, + BUS_MSTOP(8, BIT(4))), + DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12, + BUS_MSTOP(8, BIT(4))), + DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13, + BUS_MSTOP(8, BIT(4))), + DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14, + BUS_MSTOP(8, BIT(4))), +}; + +static const struct rzv2h_reset r9a09g056_resets[] __initconst = { + DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */ + DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */ + DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */ + DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */ + DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */ + DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */ + DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */ +}; + +const struct rzv2h_cpg_info r9a09g056_cpg_info __initconst = { + /* Core Clocks */ + .core_clks = r9a09g056_core_clks, + .num_core_clks = ARRAY_SIZE(r9a09g056_core_clks), + .last_dt_core_clk = LAST_DT_CORE_CLK, + .num_total_core_clks = MOD_CLK_BASE, + + /* Module Clocks */ + .mod_clks = r9a09g056_mod_clks, + .num_mod_clks = ARRAY_SIZE(r9a09g056_mod_clks), + .num_hw_mod_clks = 25 * 16, + + /* Resets */ + .resets = r9a09g056_resets, + .num_resets = ARRAY_SIZE(r9a09g056_resets), + + .num_mstop_bits = 192, +}; diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c index 88ab26a077ae..34a3145d72eb 100644 --- a/drivers/clk/renesas/rzv2h-cpg.c +++ b/drivers/clk/renesas/rzv2h-cpg.c @@ -1373,6 +1373,12 @@ static const struct of_device_id rzv2h_cpg_match[] = { .data = &r9a09g047_cpg_info, }, #endif +#ifdef CONFIG_CLK_R9A09G056 + { + .compatible = "renesas,r9a09g056-cpg", + .data = &r9a09g056_cpg_info, + }, +#endif #ifdef CONFIG_CLK_R9A09G057 { .compatible = "renesas,r9a09g057-cpg", diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h index a7aa1da181e5..8a2466f10deb 100644 --- a/drivers/clk/renesas/rzv2h-cpg.h +++ b/drivers/clk/renesas/rzv2h-cpg.h @@ -326,6 +326,7 @@ struct rzv2h_cpg_info { }; extern const struct rzv2h_cpg_info r9a09g047_cpg_info; +extern const struct rzv2h_cpg_info r9a09g056_cpg_info; extern const struct rzv2h_cpg_info r9a09g057_cpg_info; #endif /* __RENESAS_RZV2H_CPG_H__ */ From patchwork Wed Mar 26 14:39:42 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 876382 Received: from mail-wr1-f53.google.com (mail-wr1-f53.google.com [209.85.221.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C80CD1FBC89; Wed, 26 Mar 2025 14:40:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743000017; cv=none; b=hwrb+Itr1r4l2f4slfIeJQ5GAMDCZVSFFCnGUn5eQFw0tfaF9J/ctUod8ScpT5FvP8wYLmwRD/INaOCovYDI0RuY3avbAJMlESTfYJ0iT5rdhHhCJDHH5uxskwAD/ec7dZT48amsc1B3ZQ0Uq1Mogfzz4OhtReOZmnvnlBwndQE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743000017; c=relaxed/simple; bh=o5hgzM4VQ5OJeGEXkCVX1VygAU/9FrnkB/FemZCGrts=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qtrCEzQE65i6gFvseZ9Ls0IsgKbpAyDBrW8iGahqVCHNH+8HJokQ+mm1PIgq8uHnTRG+fVhgzg8LBPRZDYUDMd3TNzyuZb9DJQmFA20I8zTQm7O4nrC86uwJXMmSg7HLxhixLUglayjGX/my3VnXAmD/jTNqlswGqeX5ivMbcrM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=OP/gs54w; arc=none smtp.client-ip=209.85.221.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="OP/gs54w" Received: by mail-wr1-f53.google.com with SMTP id ffacd0b85a97d-39ac56756f6so2712934f8f.2; Wed, 26 Mar 2025 07:40:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1743000013; x=1743604813; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=C6hfLsSuXXkQW+oQprMpqK3KHzdpSf8DxnzIWa6RWKI=; b=OP/gs54w5Z1Z+soZcS12XJrcEM2ELQGu9DScYlalcvnIIlyeEfGDycOsi+SY0JLPNB YBuJo5q583QX/GSzCwH25hqtF7YBO2CQMiYMmkGWr0lRFeGBbiYmCae4qR032R3MI/m+ VDsZRY2X9OCP7HjUPuXxKZRJ9TRw1atH+NkcLVZNms1TjqFbizVzWc1hU67tmocJrHTD bdxtsnCooijKIOUIUk29fl3Vn6DJpecdMKka8esIjRYcuiONS2hcgF9cJlvvKeMD03lz i6rh71+e1xBJXdt5kph21eSVxb4X+NJPhEUun53eUtUUc0RKL+x4TZS+/kyhYRKFXatj HwDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743000013; x=1743604813; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=C6hfLsSuXXkQW+oQprMpqK3KHzdpSf8DxnzIWa6RWKI=; b=F7isUU8tjSUpF7dk3HSblhCjJAzq9SRlBhOvcckb4UNJYNpjcvNTTg4CGD+1SPvTp7 LLX1imvFi07saTld5u7rQXQwY67dVGXL6WPOp3tq6Mfd6INDenzMbOq+rNkS0QuMyRfA NU7UUQuLSihWq6rV+pb67GTbirChdmktAl9PFjB+Yw0Wl2GWnSv3/BX/A+9YesU7hCSY qLToi+f3a5Qi6vbNwGZbtc5sJGybUpn2O13LYpBj59ym0tme+kmP1HWFCd5kPzXQ1Ln3 WZH//96uUi9nbwSsghxj976WDqxa7U97He+Eb859Cm2KQwSR7rF7c481kBJd/CIcd5RO +CRw== X-Forwarded-Encrypted: i=1; AJvYcCUFKatmHLXoL6rEA6LaJ02qkHNU3aiM/QWfIw5lKVL/5MluEMGqNnsU8+8iuwRm2MQjkkYc+k5xtr7yV2FX@vger.kernel.org, AJvYcCV1nhF/1s03PozkmImGgzN6HTZYGAv74McNUVhCYGAkdRtCm3ciCVQ1OKDMIMt+D7TA6A9GHA9fn5MA@vger.kernel.org, AJvYcCVVS4RI7++P55el0xyOewPdlUrOeTLP6phZI9F4cEMlynNVtBtCtCfoOE0O5S9yzzsAiuwnbkqBgwMe@vger.kernel.org, AJvYcCVkKuEsLrYLW7LM5b492kta3ix8CK+KsSjlNU/BWaxn4u7DUHfdpOYhY3F9T8UpA/qLtP62b6nHJBfijQ==@vger.kernel.org, AJvYcCWXTZWYPUOdq0pdURqDH75HLwsOi++RtnstSwnbUNm7Ekf3GSqBXhvv6Tt4OSa01+3Av5zzF55HXnbF@vger.kernel.org, AJvYcCXzIMsMVMwD7p7kEOH7Lg6OlHHrgWL6b+YIsxe5j2ViLDB8eeNOYI/cS1JN/KCdWcYj3qjgmZewrJ7yfbJU@vger.kernel.org X-Gm-Message-State: AOJu0YxzueyocH0Vs/sAnK6B+vQIUYRZwPfxjaa7NwM+U6v6PoYqsFTe OrxeDh71SBIdm32Yw3A4RuzYQvcnaoWvTkV4joULxUJLC4ZcDAi7 X-Gm-Gg: ASbGncvKp9eS9Pz4/GEsKZrzaAoj3U3Fm4LmFOLEK7r56TOTPpRUquR4Mw0nSclqrqX BC5fqyUcoyRf/rqYxcgzPMeHTuB26DThwtYNrxrkIStb3tUS1ScZ7tIziumuMdzjLw7BHy7IYqn xwT7cB+ngNbRMt6ea1bb6ncG57hia60xxpPH5xOlnrB7KSbcyz2TNALDHN2RwiKsyTvztqSJlw9 lAD0MDf97h6l0b+8dafT7Z9KjCwQilxMA6TxOm9iQvXsAyMs++Q9uTzGKbku/qgbBnAdoOifH1C bqhxoxd3aEWzzYJzemvthVnf7uQxGBG+0BE9cjh+MlfYuJmMxHJT2WmcFhfsjsrJhIuY X-Google-Smtp-Source: AGHT+IE4qtcNDA9+68gnJpQW7sH+JjJZJUZhlD6D7jXeTF/bWc027ggNQ2cK9NDwA9P5cuQE+xB1mA== X-Received: by 2002:a05:6000:2cd:b0:390:fc5a:91c8 with SMTP id ffacd0b85a97d-3997f940ec2mr19210115f8f.53.1743000012657; Wed, 26 Mar 2025 07:40:12 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:e63e:b0d:9aa3:d18d]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d82efe9b4sm3891885e9.20.2025.03.26.07.40.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Mar 2025 07:40:11 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ulf Hansson , Linus Walleij , Greg Kroah-Hartman , Jiri Slaby , Magnus Damm , Catalin Marinas , Will Deacon , Wolfram Sang Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 12/15] pinctrl: renesas: rzg2l: Add support for RZ/V2N SoC Date: Wed, 26 Mar 2025 14:39:42 +0000 Message-ID: <20250326143945.82142-13-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250326143945.82142-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250326143945.82142-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Add pinctrl support for the Renesas RZ/V2N SoC by reusing the existing RZ/V2H(P) pin configuration data. The PFC block is nearly identical, with the only difference being the absence of `PCIE1_RSTOUTB` on RZ/V2N. To accommodate this, move the `PCIE1_RSTOUTB` entry to the end of the `rzv2h_dedicated_pins` array and set `.n_dedicated_pins` to `ARRAY_SIZE(rzv2h_dedicated_pins) - 1` in the RZ/V2N OF data. Signed-off-by: Lad Prabhakar --- drivers/pinctrl/renesas/Kconfig | 1 + drivers/pinctrl/renesas/pinctrl-rzg2l.c | 36 ++++++++++++++++++++++++- 2 files changed, 36 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig index 3c18d908b21e..e16034fc1bbf 100644 --- a/drivers/pinctrl/renesas/Kconfig +++ b/drivers/pinctrl/renesas/Kconfig @@ -42,6 +42,7 @@ config PINCTRL_RENESAS select PINCTRL_RZG2L if ARCH_RZG2L select PINCTRL_RZV2M if ARCH_R9A09G011 select PINCTRL_RZG2L if ARCH_R9A09G047 + select PINCTRL_RZG2L if ARCH_R9A09G056 select PINCTRL_RZG2L if ARCH_R9A09G057 select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203 select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264 diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index c72e250f4a15..ae5e040f3276 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -2304,7 +2304,6 @@ static struct rzg2l_dedicated_configs rzv2h_dedicated_pins[] = { { "SD1DAT3", RZG2L_SINGLE_PIN_PACK(0xc, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) }, { "PCIE0_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, - { "PCIE1_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, { "ET0_MDIO", RZG2L_SINGLE_PIN_PACK(0xf, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) }, { "ET0_MDC", RZG2L_SINGLE_PIN_PACK(0xf, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | @@ -2359,6 +2358,14 @@ static struct rzg2l_dedicated_configs rzv2h_dedicated_pins[] = { { "ET1_RXD1", RZG2L_SINGLE_PIN_PACK(0x14, 5, (PIN_CFG_PUPD)) }, { "ET1_RXD2", RZG2L_SINGLE_PIN_PACK(0x14, 6, (PIN_CFG_PUPD)) }, { "ET1_RXD3", RZG2L_SINGLE_PIN_PACK(0x14, 7, (PIN_CFG_PUPD)) }, + + /* + * This pin is only available on the RZ/V2H(P) SoC and not on the RZ/V2N. + * Since this array is shared with the RZ/V2N SoC, this entry should be placed + * at the end. This ensures that on the RZ/V2N, we can set + * `.n_dedicated_pins = ARRAY_SIZE(rzv2h_dedicated_pins) - 1,`. + */ + { "PCIE1_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, }; static struct rzg2l_dedicated_configs rzg3e_dedicated_pins[] = { @@ -3349,6 +3356,29 @@ static struct rzg2l_pinctrl_data r9a09g047_data = { .bias_param_to_hw = &rzv2h_bias_param_to_hw, }; +static struct rzg2l_pinctrl_data r9a09g056_data = { + .port_pins = rzv2h_gpio_names, + .port_pin_configs = r9a09g057_gpio_configs, + .n_ports = ARRAY_SIZE(r9a09g057_gpio_configs), + .dedicated_pins = rzv2h_dedicated_pins, + .n_port_pins = ARRAY_SIZE(r9a09g057_gpio_configs) * RZG2L_PINS_PER_PORT, + .n_dedicated_pins = ARRAY_SIZE(rzv2h_dedicated_pins) - 1, + .hwcfg = &rzv2h_hwcfg, + .variable_pin_cfg = r9a09g057_variable_pin_cfg, + .n_variable_pin_cfg = ARRAY_SIZE(r9a09g057_variable_pin_cfg), + .num_custom_params = ARRAY_SIZE(renesas_rzv2h_custom_bindings), + .custom_params = renesas_rzv2h_custom_bindings, +#ifdef CONFIG_DEBUG_FS + .custom_conf_items = renesas_rzv2h_conf_items, +#endif + .pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock, + .pmc_writeb = &rzv2h_pmc_writeb, + .oen_read = &rzv2h_oen_read, + .oen_write = &rzv2h_oen_write, + .hw_to_bias_param = &rzv2h_hw_to_bias_param, + .bias_param_to_hw = &rzv2h_bias_param_to_hw, +}; + static struct rzg2l_pinctrl_data r9a09g057_data = { .port_pins = rzv2h_gpio_names, .port_pin_configs = r9a09g057_gpio_configs, @@ -3389,6 +3419,10 @@ static const struct of_device_id rzg2l_pinctrl_of_table[] = { .compatible = "renesas,r9a09g047-pinctrl", .data = &r9a09g047_data, }, + { + .compatible = "renesas,r9a09g056-pinctrl", + .data = &r9a09g056_data, + }, { .compatible = "renesas,r9a09g057-pinctrl", .data = &r9a09g057_data, From patchwork Wed Mar 26 14:39:44 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 876381 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 097ED1F8691; Wed, 26 Mar 2025 14:40:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743000019; cv=none; b=cart78fDpDWYtJzxASrdCWQZ4/e/B9EWQRtDdef9WxVJGZSGnSlMyhYVwnMrC0QcZUbWgodWJWzMj23icoUKJQL2mF5QHYyfYRn1k2pAdPVXss0O2i+jktvTXR1tLZc+yespy+nV4AHB5jDEDfDC3Qxlg95xM8fbOcUZUh0NMig= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743000019; c=relaxed/simple; bh=yj4XgRWZOKauWmIoJXTfEovmOX248fvaF8O5Xtl9w6E=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=NcQ0ghwF/dE1FaIKTGz2Ct5WE5EJRCweGKk31/i6WC6Us9tqrZKEJr0TaLHIZ6x25QwwE9G52p5A3ReUDw7V1Q0CxGMhl0RAOvNPQBKwew3CfNJ0Ul3DrdfadsX7WHIuF9a7lxhVEhqTRRd7ZtQpXN5AYe0QdMwXb/xeRzLIWqk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=AlfbrqVh; arc=none smtp.client-ip=209.85.128.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="AlfbrqVh" Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-43948021a45so61938805e9.1; Wed, 26 Mar 2025 07:40:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1743000015; x=1743604815; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Q5rclYPCoX+9XsQVXAGD6Zpg/jR52MIrAxSZcU/YUac=; b=AlfbrqVhCJRTmdXh85FNiymaefQ/KzCMctxqSMdI9yBARlXYWyqgqdJ8aISg3TwXHd cWiWDvL5e1la/Uy4qgzbj3OqUCTKLE6gG4UKpdr+a2Phy3D2QYUFnv/SNi1UqYlw6lMY qVV8Aw0UrUEI6NPFJ1JuCj9LLNO+IySDVnlkeVS3u5nHV4zaQr+ii+qv9ONFIMBZx902 x2hVPNdJCh8HlFth3/QlWAYvK/Cbz/MlTj/OUGpaSAQr5PK8Y6faDfav32jlEgJJ0qYo 1Z5ZAGvrczhDaWWE0DIODOFS74jwMWNrhpE3y+t66ENQ1oLMoAxDtdZA9aoJxqYmQ0ld 667Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743000015; x=1743604815; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Q5rclYPCoX+9XsQVXAGD6Zpg/jR52MIrAxSZcU/YUac=; b=Em8fHeCwH+wxcNnUgwpZLP1rLOyNIROkETxNQvbLNUYA9Cq/gzfcH2DsX2Nw6f9xmQ zW+Jja3FlmFxu3jY/pyveuBLCalX/+W9O8PMRN+N2gdaRxceQn3EtvHhUXfZYRIJpgdK jfiGgJ73DwbcKuABR47JZRn7sbVLfcwzcKeLVTlE/shTjKlDKt5lCflNdKgc1R9R1pf7 MM+KPyduooI7uKflCbpyBU9mgQ2hhXTZLzpZI5kqRzlXv0w2QZwe05OqwJsjbPpwV5qk U8/OJ3WLNrv/jiRz80c4lYeaxF8mCW1tZOKy+FKFgQizUZZ81VeYGTHQMfsQlIkpStdY HGfQ== X-Forwarded-Encrypted: i=1; AJvYcCUoYWFIsisDfP3SHek0qcOXslIWYYosfmjsHlDUsHh2C7MLlO+deYJVWPBd/h8v7Ay87CkEJcaUmE5M@vger.kernel.org, AJvYcCVBljg52AwKAyvs/qYw9IkqN/mGNQJ96H6sgSqffd37eqiY7HLL9knBjvbcY6Ut4ut3yWP/jXVrnVK+H5Av@vger.kernel.org, AJvYcCVMGJ2obCCWrygjHVYQe35nGVteC7IlH8m+JRpjFqeYl4lG8lOmYh7yhLgAB4WmjzvZ9erA8Q0Ucr2A0OOg@vger.kernel.org, AJvYcCWj0XmcyYi3s3i0+I7F7yqKpvRfJBmWG+Tv0VhP4vqPYx8Dk3Jx30xHYB70byg/k2tqdGFBF21pf7AEaA==@vger.kernel.org, AJvYcCX1QRbGgYKIrcO3d7v2AzE4abToy1uH62SoM0XAQARA9F6xywHzWjGBTOVB9Tav/EHbBnndRextEcq+@vger.kernel.org, AJvYcCXlHPh64PVfiy2lbHqFsrInKKNurXPo5HgbUuyVYtM9MmXDPg+pZCuQJWLYCEnveHJC7w26oIdjAhOX@vger.kernel.org X-Gm-Message-State: AOJu0YzqUyjvslrdPdSrnX0GrfWMcSx2WGmFelOqLgyzq9pxwVYJJIQl 32Hp1Zn/82uQJtfr+wMMpX6GAR4/lQAnsUiXh0MIFupqxEV7WEj3 X-Gm-Gg: ASbGncsp/k5RMkmpYT7m7x/AJE5EjteeA0tl3mg1JK0TGCWJ9HjWURi3W1r25j1exPa 9cMaqwcVOHKvYbcYgX6vHu8fol90jh62k7lMTLdadF/YEZqznoPNl8KSehDupTp/tMDldBWkQzx MA8Vt9cal3Om4wUBxK2C5yCbObNUzNmQ53HtIVJnEZ0EBXRzj4PoLhN8CDfGGxV58mXzFrm+quF kY4/EzNBi8Jt7UL09L+fYsgLGX2WvpNuepV0mJOHD/YSJ3/dwWMOQEVFhuXUeTef/goZo+GSnX6 N45IEutkOk6XyZhfj1TDg8bHCd1nKfszL83Y5xTrgHtd2k2fK5+Kgdd2ZY3IDsgsFcQS X-Google-Smtp-Source: AGHT+IGRAy9yfwG6d2+eXVQeNxaGO7gg1l8K/+riQ2OdyGmO/wZrf70Io0vAaYCnsynf3rjsoKhCJg== X-Received: by 2002:a05:600c:5742:b0:43c:e70d:44f0 with SMTP id 5b1f17b1804b1-43d510fff60mr149245365e9.19.1743000015128; Wed, 26 Mar 2025 07:40:15 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:e63e:b0d:9aa3:d18d]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d82efe9b4sm3891885e9.20.2025.03.26.07.40.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Mar 2025 07:40:14 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ulf Hansson , Linus Walleij , Greg Kroah-Hartman , Jiri Slaby , Magnus Damm , Catalin Marinas , Will Deacon , Wolfram Sang Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 14/15] arm64: dts: renesas: Add initial device tree for RZ/V2N EVK Date: Wed, 26 Mar 2025 14:39:44 +0000 Message-ID: <20250326143945.82142-15-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250326143945.82142-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250326143945.82142-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Add the initial device tree for the Renesas RZ/V2N EVK board, based on the R9A09G056N48 SoC. Enable basic board functionality, including: - Memory mapping (reserve the first 128MB for the secure area) - Clock inputs (QEXTAL, RTXIN, AUDIO_EXTAL) - PINCTRL configurations for peripherals - Serial console (SCIF) - SDHI1 with power control and UHS modes Update the Makefile to include the new DTB. Signed-off-by: Lad Prabhakar --- arch/arm64/boot/dts/renesas/Makefile | 2 + .../dts/renesas/r9a09g056n48-rzv2n-evk.dts | 115 ++++++++++++++++++ 2 files changed, 117 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index d25e665ee4bf..d8a8d7ca4c58 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -152,6 +152,8 @@ dtb-$(CONFIG_ARCH_R9A09G011) += r9a09g011-v2mevk2.dtb dtb-$(CONFIG_ARCH_R9A09G047) += r9a09g047e57-smarc.dtb +dtb-$(CONFIG_ARCH_R9A09G056) += r9a09g056n48-rzv2n-evk.dtb + dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h44-rzv2h-evk.dtb dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h48-kakip.dtb diff --git a/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts new file mode 100644 index 000000000000..aee4748a7618 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/V2N EVK board + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +/dts-v1/; + +#include +#include +#include "r9a09g056.dtsi" + +/ { + model = "Renesas RZ/V2N EVK Board based on r9a09g056n48"; + compatible = "renesas,rzv2n-evk", "renesas,r9a09g056n48", "renesas,r9a09g056"; + + aliases { + mmc1 = &sdhi1; + serial0 = &scif; + }; + + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial0:115200n8"; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x1 0xf8000000>; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vqmmc_sdhi1: regulator-vqmmc-sdhi1 { + compatible = "regulator-gpio"; + regulator-name = "SDHI1 VqmmC"; + gpios = <&pinctrl RZV2N_GPIO(A, 2) GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios-states = <0>; + states = <3300000 0>, <1800000 1>; + }; +}; + +&audio_extal_clk { + clock-frequency = <22579200>; +}; + +&pinctrl { + scif_pins: scif { + pins = "SCIF_TXD", "SCIF_RXD"; + renesas,output-impedance = <1>; + }; + + sd1-pwr-en-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "sd1_pwr_en"; + }; + + sdhi1_pins: sd1 { + sd1_dat_cmd { + pins = "SD1DAT0", "SD1DAT1", "SD1DAT2", "SD1DAT3", "SD1CMD"; + input-enable; + renesas,output-impedance = <3>; + slew-rate = <0>; + }; + + sd1_clk { + pins = "SD1CLK"; + renesas,output-impedance = <3>; + slew-rate = <0>; + }; + + sd1_cd { + pinmux = ; /* SD1_CD */ + }; + }; +}; + +&qextal_clk { + clock-frequency = <24000000>; +}; + +&rtxin_clk { + clock-frequency = <32768>; +}; + +&scif { + pinctrl-0 = <&scif_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sdhi1 { + pinctrl-0 = <&sdhi1_pins>; + pinctrl-1 = <&sdhi1_pins>; + pinctrl-names = "default", "state_uhs"; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <&vqmmc_sdhi1>; + bus-width = <4>; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +};