From patchwork Wed Mar 26 15:35:34 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Wanner X-Patchwork-Id: 876650 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A7C81F3BB6; Wed, 26 Mar 2025 15:36:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743003398; cv=none; b=DUR9Ex6FvyZXyZiBGlADRvmQYkHc68KNA4uPL1KiwNcMd2fzpotz9/CsBfmN6w67qhLZ7puNzIWHDW8j1POTofp6MiwjXclXWGz8YlMkbMTfcTSURKk51hVE8nyn8t+cqK7FAH2KTTams1WHp1q+DA0dn5WPJNr9NSLm2/Xppfs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743003398; c=relaxed/simple; bh=y6zBcUQgWavANG8NsuRsZDucUUdJh5SHXwtzFjn3t3c=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=RbSO0b737ftAR+dBJLDedsUY4yzPrBoAjXfd845XDeBI5kksTDVLAG9dSV6cWL5fxxneWyk8pzAIwNDc6b3qmTQ65JmHK1T85BeznMdWervbRA3tBTXrIIhL1cZCa9mFDBx0pkg2uHBRN7Z2KA9TZIX7APyyYlZ+tOVAXISvbzg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=s7lLJnGl; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="s7lLJnGl" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1743003397; x=1774539397; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=y6zBcUQgWavANG8NsuRsZDucUUdJh5SHXwtzFjn3t3c=; b=s7lLJnGlFQAUWQuKogbfkKdEXNC/FuQIZK7WFEPQSHFZPKxrthktx7p/ YVvTS6ZpNfkVD5SpybSOu+NKM7HEvztfA+3CLq7IfCeKvGeuMDhD+dOVh HXun0mCIRmfJKjmQA6sM7CAwpvl/17cf7JMSWjs1p8WjFlc0NURHlMCCv wRPq5mpgRQKsxe6oClue/1Glh36vxz3ltkz8PkXH6pP4gRYM2+X6qOs6V CUZUVR/JV+ypFEd3OjO9M4fR2JNiW9dX/HXb0JJhQMMGy5uEaK6Y4MPST JUR7698aHaWJ3aYNmu5sigP8PTcyVsIwnwka/I8fh08mhXer2NUiOC5m+ g==; X-CSE-ConnectionGUID: NRxSiTFnT3ucBnaYj7CaZg== X-CSE-MsgGUID: nwryJGrFR6W9xwUv1FaEAg== X-IronPort-AV: E=Sophos;i="6.14,278,1736838000"; d="scan'208";a="44096097" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 26 Mar 2025 08:36:29 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Wed, 26 Mar 2025 08:35:50 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Wed, 26 Mar 2025 08:35:50 -0700 From: To: , , , , , , , , CC: , , , , , Ryan Wanner Subject: [PATCH v4 01/11] dt-bindings: sram: Add microchip,sama7d65-sram Date: Wed, 26 Mar 2025 08:35:34 -0700 Message-ID: <35015e91dfd7d2240d05160a75cdd6dc4f4e6e79.1742936082.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ryan Wanner Add microchip,sama7d65-sram compatibility to DT binding documentation. Signed-off-by: Ryan Wanner Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/sram/sram.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/sram/sram.yaml b/Documentation/devicetree/bindings/sram/sram.yaml index 7c1337e159f2..3071c5075ee4 100644 --- a/Documentation/devicetree/bindings/sram/sram.yaml +++ b/Documentation/devicetree/bindings/sram/sram.yaml @@ -31,6 +31,7 @@ properties: - amlogic,meson-gxbb-sram - arm,juno-sram-ns - atmel,sama5d2-securam + - microchip,sama7d65-securam - nvidia,tegra186-sysram - nvidia,tegra194-sysram - nvidia,tegra234-sysram From patchwork Wed Mar 26 15:35:35 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Wanner X-Patchwork-Id: 876434 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AFE291F4184; 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X-CSE-ConnectionGUID: NRxSiTFnT3ucBnaYj7CaZg== X-CSE-MsgGUID: rr3bYGrkS0erqMBYCgToHg== X-IronPort-AV: E=Sophos;i="6.14,278,1736838000"; d="scan'208";a="44096098" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 26 Mar 2025 08:36:29 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Wed, 26 Mar 2025 08:35:50 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Wed, 26 Mar 2025 08:35:50 -0700 From: To: , , , , , , , , CC: , , , , , Ryan Wanner Subject: [PATCH v4 02/11] dt-bindings: power: reset: atmel, sama5d2-shdwc: Add microchip,sama7d65-shdwc Date: Wed, 26 Mar 2025 08:35:35 -0700 Message-ID: <24666308604d3eb9f2b8c64d4a466c6fd77120e9.1742936082.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ryan Wanner Add SAMA7D65 SHDWC compatible to DT bindings documentation Signed-off-by: Ryan Wanner Acked-by: Rob Herring (Arm) --- .../devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml b/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml index 0735ceb7c103..9c34249b2d6d 100644 --- a/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml +++ b/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml @@ -16,6 +16,11 @@ description: | properties: compatible: oneOf: + - items: + - enum: + - microchip,sama7d65-shdwc + - const: microchip,sama7g5-shdwc + - const: syscon - items: - const: microchip,sama7g5-shdwc - const: syscon From patchwork Wed Mar 26 15:35:36 2025 Content-Type: text/plain; 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Wed, 26 Mar 2025 08:35:51 -0700 From: To: , , , , , , , , CC: , , , , , Ryan Wanner , Krzysztof Kozlowski Subject: [PATCH v4 03/11] dt-bindings: reset: atmel,at91sam9260-reset: add microchip,sama7d65-rstc Date: Wed, 26 Mar 2025 08:35:36 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ryan Wanner Add SAMA7D65 RSTC compatible to DT bindings documentation. The sama7d65-rstc is compatible with the sama7g5-rstc. Signed-off-by: Ryan Wanner Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/reset/atmel,at91sam9260-reset.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml index 98465d26949e..a2ab7f8a11f8 100644 --- a/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml +++ b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml @@ -23,6 +23,9 @@ properties: - atmel,sama5d3-rstc - microchip,sam9x60-rstc - microchip,sama7g5-rstc + - items: + - const: microchip,sama7d65-rstc + - const: microchip,sama7g5-rstc - items: - const: atmel,sama5d3-rstc - const: atmel,at91sam9g45-rstc From patchwork Wed Mar 26 15:35:37 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Wanner X-Patchwork-Id: 876433 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 803DE1F4716; Wed, 26 Mar 2025 15:36:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743003401; cv=none; b=W8Oac5Jnd5mx1bIEP+OPL54mnxn39YluEYCyyOYtemfvCifYxGHoERoNFgUsAcQlOEZ88il5nMxP/ogKjN7z/YRJ7u/BcIj9ptdpYy3ScHJ9xXqnx4MwY4eW2/S8CiXbYsm8V+4RSaVS+Ph+z5ez7IiC0VpcQ5wJsk6cqffK/c4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743003401; c=relaxed/simple; bh=lRUUsu68yjl48Dfc+/ph2mpUFrsqqJQ0TwHXN3jGP6Y=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=QmPV4hXapFi0wBo3bpvvNg2vbEhMW5kUiSKQr5WxzFWI8xaCv2qipFuetZKqq49w0Ks2+/qdF+pDQLgR3uBxDCA/Cvs5yjNl0WVbqZKeXD03/ek1eBFUWPQI8972MwXUzvZdazTTYsWT5Tv2rvwA1VF+yOPkAzDebEt17BuRE3k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=cIlCiZi0; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="cIlCiZi0" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1743003399; x=1774539399; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lRUUsu68yjl48Dfc+/ph2mpUFrsqqJQ0TwHXN3jGP6Y=; b=cIlCiZi00Dgx/BykbB/MRVjod+CWCbsaue0EL8yZjHpherq9ogsGWdB3 gZS9CQzi3dzDmjfc0F9yKopkHIIObyyWip0LYzkxbjLSHKgXGdN8xuGEo lgYpfBEyUCWKXaM/2ZIdHgYdlwfmsFWv7YthG3/Jp7AqrTufDW1SVWDx7 3MxuYhb9hjJVVC/8JBtTN6WsL03iKndDcLX2k74Q35FZg25R5+lNkrkWk K8gESey2r95sq/nglPywif4PzmkmGOmeEyNj1MQeWsfc5ZjS6Uj9zeUqh I7v1uB3DMpoZMCgOxfh9rLxdRSaxek4pMcuunbESVuCbMfml6/bRfGlXw g==; X-CSE-ConnectionGUID: NRxSiTFnT3ucBnaYj7CaZg== X-CSE-MsgGUID: TYQz+qm7RzimNv1S2hPivA== X-IronPort-AV: E=Sophos;i="6.14,278,1736838000"; d="scan'208";a="44096101" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 26 Mar 2025 08:36:30 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Wed, 26 Mar 2025 08:35:51 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Wed, 26 Mar 2025 08:35:51 -0700 From: To: , , , , , , , , CC: , , , , , Ryan Wanner Subject: [PATCH v4 04/11] dt-bindings: rtc: at91rm9200: add microchip,sama7d65-rtc Date: Wed, 26 Mar 2025 08:35:37 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ryan Wanner Add SAMA7D65 RTC compatible to DT bindings documentation. Signed-off-by: Ryan Wanner Acked-by: Rob Herring (Arm) --- .../devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml index c8bb2eef442d..7c5b13caa40b 100644 --- a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml @@ -23,7 +23,9 @@ properties: - microchip,sam9x60-rtc - microchip,sama7g5-rtc - items: - - const: microchip,sam9x7-rtc + - enum: + - microchip,sam9x7-rtc + - microchip,sama7d65-rtc - const: microchip,sam9x60-rtc reg: From patchwork Wed Mar 26 15:35:38 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Wanner X-Patchwork-Id: 876648 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D46D41F4736; Wed, 26 Mar 2025 15:36:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743003401; cv=none; b=q9AlToLa465arOwT4u6mrj7p2PqrdSsT3y0A/GcnhgtcWjDSvF4OCse1tunTanYPhPmGO2URZlt9sSjeXISXZ63NtGepwRl5IHvfnR5s1nAS1b7vW0ZRFB+cxzfawmdWv1IsjHi12K8wyD4+wV02/gkGPWqoJWxTTwWQTDcsy4s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743003401; c=relaxed/simple; bh=P0+FQOoZAZDGBeJjjiJS1++QSiAMr7ZQoLAUMUlSI2E=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=PjCEqdicwSRjYwJWyEuj0VUK19HCMs17iPdJdZOnwEqRd07DUkdJMSmavvzre17/lBa/68FjqXbRVSKnbbkBQ7HImkFgRzW7StYwlxFTH6TlHY6PedZaCKBnpmZDroFLlMTSjVjkSmBQsV6qd3DwCRSrd7eAlspz1mceFN+lxwE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=JsesEFF+; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="JsesEFF+" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1743003399; x=1774539399; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=P0+FQOoZAZDGBeJjjiJS1++QSiAMr7ZQoLAUMUlSI2E=; b=JsesEFF+EfFz6TtugH95a4wnS+BB40ZNLmLRgb2HtmqW4w42KvgDDDHX wCA+mItlg5qleSRoBwYwC60R+wLi7acEG/uAB0+OHSxtVrxw9eSO7/hfc +vaY3LeRIXEw7+PDBXVxiioRC+g1g1FnKFL3EbqjWhopbyGJVrwNdNDXS Sd8tIzXp6u/TY08sw3PmJS/GvPaNcvdsxBG4R9y/Xv/mgfa+ZdKFl4JN/ EGQTSN4ICMPCF6cX2W3AmQuuW8AznHoIvAuGvMJRnR4qcQlidfIJGNHWT mhmp4zIPkAx4G2I96+BkKV4+zck10QAELZBsdhbHQqYTU9iX4+afsRV9r A==; X-CSE-ConnectionGUID: NRxSiTFnT3ucBnaYj7CaZg== X-CSE-MsgGUID: 2WjqQwB5TPyGcK53n9hLgg== X-IronPort-AV: E=Sophos;i="6.14,278,1736838000"; d="scan'208";a="44096103" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 26 Mar 2025 08:36:30 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Wed, 26 Mar 2025 08:35:51 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Wed, 26 Mar 2025 08:35:51 -0700 From: To: , , , , , , , , CC: , , , , , Ryan Wanner Subject: [PATCH v4 05/11] dt-bindings: at91rm9260-rtt: add microchip,sama7d65-rtt Date: Wed, 26 Mar 2025 08:35:38 -0700 Message-ID: <183474a65377f4030360166a5f2659af7323e82b.1742936082.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ryan Wanner Add SAMA7D65 RTT compatible to DT bindings documentation. Signed-off-by: Ryan Wanner Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml b/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml index a7f6c1d1a08a..9c9b981fe38b 100644 --- a/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml +++ b/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml @@ -22,6 +22,7 @@ properties: - enum: - microchip,sam9x60-rtt - microchip,sam9x7-rtt + - microchip,sama7d65-rtt - const: atmel,at91sam9260-rtt - items: - const: microchip,sama7g5-rtt From patchwork Wed Mar 26 15:35:39 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Wanner X-Patchwork-Id: 876432 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 004AB1F540F; Wed, 26 Mar 2025 15:36:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743003402; cv=none; b=ZVMUguWz/NvHw/tqr1eInr4cofAOnf+oXoLsQ1TFNAeJfp5aC2Q8BtqoqfRGuj/TVIsU6qYFmC+vnWLjruaWuGsbFOTAdRYUUBmAa2kFhNKT0qeXkdW/BZC3wiCq8ga9Ra6stnMrAbixEpuVfdXlSilnoR+xiOCCcoPsWgTTbyk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743003402; c=relaxed/simple; bh=xkIKAcxmvRMr0isI4ttyqqzXZUNUbkxbL/xiHHpkAg8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=HHHAu/FzZSG8imDDUnGxcxlKK1Td8MZ40Zw8TVa6TiJR8Loo9IKtBhWtxFoOKiyXMBdUXq+FD/AkKDCa5Mt4hn5tNKf+DOR5MFng3uJbKe336WTSSxlZKbk6ugjQ6c7YJS90teGzjrHuldSU5Aq2cdXJEGUAPC5ueIW79U43ZOU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=moeGxVw8; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="moeGxVw8" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1743003400; x=1774539400; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xkIKAcxmvRMr0isI4ttyqqzXZUNUbkxbL/xiHHpkAg8=; b=moeGxVw86o3cv3CQ8w8nv6zcOxlwMLiGa7lbWAYQtc7lMJFz8ueF1Y0/ 3cFFRhOkr95CHh8mmzCQQ7ZJYZeseF9N3mhkBzDwhxpQtxfvKdQ+VpuVQ SaEi63AJuS7mjyOb2d3LhO55xcSyVOwt8wiczHY4uTII/uy1oTx2jZWio HEKRtqbbnqUOPi+Z0AxrEf5TjE3BtKwvmznTcciAdjjSjjoQZKogffA+s 2DJSAnOLVkXUVPmCmyGF/GudHwjshS8SDr0biR3Ktz23weh1c3DSLdzUz TRblArpRfCB23MVLwfwaPOYsyTKQc/s9x9LdjVB70ZlqX6U1uKmGBx0ev g==; X-CSE-ConnectionGUID: NRxSiTFnT3ucBnaYj7CaZg== X-CSE-MsgGUID: hBcQ+YvkQV+0ElpMLixFdQ== X-IronPort-AV: E=Sophos;i="6.14,278,1736838000"; d="scan'208";a="44096105" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 26 Mar 2025 08:36:31 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Wed, 26 Mar 2025 08:35:51 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Wed, 26 Mar 2025 08:35:51 -0700 From: To: , , , , , , , , CC: , , , , , Ryan Wanner Subject: [PATCH v4 06/11] dt-bindings: mfd: atmel: Add microchip, sama7d65-gpbr Date: Wed, 26 Mar 2025 08:35:39 -0700 Message-ID: <57a9f2ef94005bc7bb450fe073fb594fe7d5c2e1.1742936082.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ryan Wanner Add SAMA7D65 GPBR compatible to DT bindings documentation. Signed-off-by: Ryan Wanner Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/mfd/atmel,at91sam9260-gpbr.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/atmel,at91sam9260-gpbr.yaml b/Documentation/devicetree/bindings/mfd/atmel,at91sam9260-gpbr.yaml index f805545aa62a..f6f47999c6c1 100644 --- a/Documentation/devicetree/bindings/mfd/atmel,at91sam9260-gpbr.yaml +++ b/Documentation/devicetree/bindings/mfd/atmel,at91sam9260-gpbr.yaml @@ -19,6 +19,7 @@ properties: - items: - enum: - atmel,at91sam9260-gpbr + - microchip,sama7d65-gpbr - const: syscon - items: - enum: From patchwork Wed Mar 26 15:35:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Wanner X-Patchwork-Id: 876647 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 45F261F5616; Wed, 26 Mar 2025 15:36:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743003402; cv=none; b=CRreL5g1T/vvtEn3xT0yCQRKO7MqueWmFLcyeNgabkKSnbFO+rGdup/TiRDQP6nHjtAlVAlJ2lgqM8eergL1IfG+ueDcMISlILjtJr6CBAtiDucRT+wM7juNXMlcrqEJsz/o5lbZ0JGcjlQFQosgJ7rr/Z6Zspzz9JO1S7XjqL0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743003402; c=relaxed/simple; bh=szVEnhvPvUBlfCtyjfvV2jfNXNmn2KFpzc9sZGjFHCQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=sTTHNTRaTAWqDdFwYB1Snp3mlAJMKQxmNl4rO1RicGMCYGYXE646ZLfozwFlXYxux4RX0RQBogdZUDFOEQlynR/km69TdiF8+Vwbs4Mm1M5k/WslHc7IHly4IUy3oBOZbdFHdTwPP4uvBwl65Pq1OpZFrLgsjZvgNpR/MFUSIhc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=PgYiOqCi; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="PgYiOqCi" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1743003401; x=1774539401; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=szVEnhvPvUBlfCtyjfvV2jfNXNmn2KFpzc9sZGjFHCQ=; b=PgYiOqCiGZyjsvXZ8RxJkwn1lFHmHRCyZttotNJQmd5QmpVtQufIlQAo BXyUsGdxUBpyHRSBcZryfKvrGcilIoQr/pwA3Uu2Mr3fbFmDrT0UjsFZL oGCzfPsiLZ2mq7qbX49emaMwBYAuHhipeUEW2NdD0vBUYQJ5gas90YBvS MAZb/a5hnnwrAVdtenTOV6jZ6NaU2/DOKLlmHKE0fHtRoqH4SZ1kzQLSC ow69R/IrHXNXv8pmkSvarAw8sCJQ3hiokDvvmVrqYq57w5ZVw8ZMuCCNo LYqaMsXpjpPxCifbOR+Zz7Rii3R/ZaqIBIDo6feYSZUUTBnkqYjYb9/HC A==; X-CSE-ConnectionGUID: NRxSiTFnT3ucBnaYj7CaZg== X-CSE-MsgGUID: nc1Hn/qqQNGMW2FQWcbFQQ== X-IronPort-AV: E=Sophos;i="6.14,278,1736838000"; d="scan'208";a="44096107" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 26 Mar 2025 08:36:32 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Wed, 26 Mar 2025 08:35:51 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Wed, 26 Mar 2025 08:35:51 -0700 From: To: , , , , , , , , CC: , , , , , Ryan Wanner Subject: [PATCH v4 07/11] dt-bindings: mfd: syscon: atmel,sama5d2-secumod: convert to yaml Date: Wed, 26 Mar 2025 08:35:40 -0700 Message-ID: <271b23440f79bfad3e902689a9f4b240ab43eb28.1742936082.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ryan Wanner Convert Microchip AT91 secumod to YAML format. Signed-off-by: Ryan Wanner --- .../bindings/arm/atmel,sama5d2-secumod.yaml | 48 +++++++++++++++++++ .../devicetree/bindings/arm/atmel-sysregs.txt | 25 ---------- 2 files changed, 48 insertions(+), 25 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/atmel,sama5d2-secumod.yaml diff --git a/Documentation/devicetree/bindings/arm/atmel,sama5d2-secumod.yaml b/Documentation/devicetree/bindings/arm/atmel,sama5d2-secumod.yaml new file mode 100644 index 000000000000..6edeb320220f --- /dev/null +++ b/Documentation/devicetree/bindings/arm/atmel,sama5d2-secumod.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/atmel,sama5d2-secumod.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip AT91 Security Module (SECUMOD) + +maintainers: + - Nicolas Ferre + +description: + The Security Module also offers the PIOBU pins which can be used as GPIO pins. + Note that they maintain their voltage during Backup/Self-refresh. + +properties: + compatible: + oneOf: + - items: + - const: atmel,sama5d2-secumod + - const: syscon + - items: + - enum: + - microchip,sama7g5-secumod + - const: atmel,sama5d2-secumod + - const: syscon + reg: + maxItems: 1 + + gpio-controller: true + + "#gpio-cells": + const: 2 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + secumod@fc040000 { + compatible = "atmel,sama5d2-secumod", "syscon"; + reg = <0xfc040000 0x100>; + gpio-controller; + #gpio-cells = <2>; + }; diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt index d3821f651e72..5ce54f9befe6 100644 --- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt +++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt @@ -46,28 +46,3 @@ Examples: reg = <0xffffe800 0x200>; }; -Security Module (SECUMOD) - -The Security Module macrocell provides all necessary secure functions to avoid -voltage, temperature, frequency and mechanical attacks on the chip. It also -embeds secure memories that can be scrambled. - -The Security Module also offers the PIOBU pins which can be used as GPIO pins. -Note that they maintain their voltage during Backup/Self-refresh. - -required properties: -- compatible: Should be "atmel,-secumod", "syscon". - can be "sama5d2". -- reg: Should contain registers location and length -- gpio-controller: Marks the port as GPIO controller. -- #gpio-cells: There are 2. The pin number is the - first, the second represents additional - parameters such as GPIO_ACTIVE_HIGH/LOW. - - - secumod@fc040000 { - compatible = "atmel,sama5d2-secumod", "syscon"; - reg = <0xfc040000 0x100>; - gpio-controller; - #gpio-cells = <2>; - }; From patchwork Wed Mar 26 15:35:41 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Wanner X-Patchwork-Id: 876431 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8CF2F1F5845; Wed, 26 Mar 2025 15:36:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743003403; cv=none; b=C0mGL4gDu4QZOQqIARdIn29r10NIMyKZnsVtdSATRngPqBGeoUhg+8H8zU9JJxWxb2XqzgVQGYUJv4begozSimp5Q48PWqJ2ZY1DaadXSi6AgzWqOv4ohh0FI/+Ku2itpBYtH6JGVjQVjqX4add+o/HtD3LnK2qky2E5hzOFdGA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743003403; c=relaxed/simple; bh=toMNQd4avKTFMnab9oaQtpEAy0iSa3Y/1sjDr01cM84=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=UkEnPXMw7CkoaM7X/uJLeqoY7rF6HZD/4+5sKKRPfd4SaLnTJUN35gAPPSFsEOMsd0DlnU1zxeYEWZPBL0qKkAzhHKDTzoJ93oPPtACu8kmBVDs9TkLKOmuN1rtg2zA7TjPVYQ0e7boGN5l1QwYlLo+X+fyl6CabpsdSYfjiweA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=1CNWLpmQ; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="1CNWLpmQ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1743003401; x=1774539401; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=toMNQd4avKTFMnab9oaQtpEAy0iSa3Y/1sjDr01cM84=; b=1CNWLpmQIyQVLEdCymY4eTU1HXfihFaalyoqquGK7fxe6w9b3E8lBXse H8MGZ8PO0ThSokO+LHy5btgLPVuCAuyC7BOuMHovOXqDBZqbscuxeu//c YyR0G/W46047GrSguP7LZBE4rQYp/YyFrvDQPbB9HqyyVTN1KL2iWQwpQ yLeXhN6UOicfYLTUW96Nv2rolJDMq1j0+PreMcyAkDY079QSsexRLTVth SA21blDV5zDICPTsFtsnCMXqzopgQIZiPM037RyQGPQCVmdlvJSw++inO 0mAlOEmLJkfHbw1mXYmtzZUYEXiFl+8eG9ayeUWeqbxw1bUiuv2srepF5 g==; X-CSE-ConnectionGUID: NRxSiTFnT3ucBnaYj7CaZg== X-CSE-MsgGUID: C3tCCdPASgia4Ox6w0hD5w== X-IronPort-AV: E=Sophos;i="6.14,278,1736838000"; d="scan'208";a="44096108" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 26 Mar 2025 08:36:32 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Wed, 26 Mar 2025 08:35:51 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Wed, 26 Mar 2025 08:35:51 -0700 From: To: , , , , , , , , CC: , , , , , Ryan Wanner Subject: [PATCH v4 08/11] dt-bindings: mfd: syscon: add microchip,sama7d65-secumod Date: Wed, 26 Mar 2025 08:35:41 -0700 Message-ID: <7248bb9d4ed491b178072b09830d6d68fde7b872.1742936082.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ryan Wanner Add SAMA7D65 SECUMOD compatible string to DT bindings documentation. Signed-off-by: Ryan Wanner Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/atmel,sama5d2-secumod.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/atmel,sama5d2-secumod.yaml b/Documentation/devicetree/bindings/arm/atmel,sama5d2-secumod.yaml index 6edeb320220f..2f3e8722443b 100644 --- a/Documentation/devicetree/bindings/arm/atmel,sama5d2-secumod.yaml +++ b/Documentation/devicetree/bindings/arm/atmel,sama5d2-secumod.yaml @@ -21,6 +21,7 @@ properties: - const: syscon - items: - enum: + - microchip,sama7d65-secumod - microchip,sama7g5-secumod - const: atmel,sama5d2-secumod - const: syscon From patchwork Wed Mar 26 15:35:42 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Wanner X-Patchwork-Id: 876646 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A83181F78F2; Wed, 26 Mar 2025 15:36:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743003404; cv=none; b=fcbFXuRidgnp5XJoeaGjY96GrHBzVpvs47T9JQ44wpEtaOKppqm6FkZ9GmPZSA2hcBIcQIOTFJovS699V8xgnh+MwZv7/OPqy+uVri8QZfxwyYGxGdoYUSCw9+APTwBxkJprbagY4hHLeuF5Ja8/A9MGHg2hWby1ybZDtW8WDA0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743003404; c=relaxed/simple; bh=BNmi5f64ZyoDoOV4MWGFQZk1PJoI5qBvg1EBNPuzEmg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ZBipY/Osbb09104d2YXs+DEfn3iT3xQ5BBj0/C74W3Tt8LVem4PN7EmVumPB7bcvayuwy02IKa/OQnj4ifwE1OfQAVshH+vmOkr/ZtMVGfkHli6hpyYCtOPuosNUYSn1j5AszPLZ2RVJPyLS48JOW0aFSZUDqg4QkHFCC0FDX+0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=Xxi7jqLP; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="Xxi7jqLP" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1743003402; x=1774539402; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BNmi5f64ZyoDoOV4MWGFQZk1PJoI5qBvg1EBNPuzEmg=; b=Xxi7jqLP2Kq/t4L2G+VAGxs9ak6ml7NbxCiJEeh1eF7C+YUgrVD2b7fh aw7ZShEani4tJ2TDwCCFywr63muvebLFW7b5Or/6PY/2mizlpiLDslPDr Plf1lXLgh4uVLYw91fYnAsNl65IM3nK13yphu+NM55TKa6whMzLT5god0 cF7uEQmYKjWxaHugFXt1e30YkRiPEeaHoZ5sW+aARLuWJGVl+F81MxBmM HuFvrs8ZueR3wqq2K6s46hB1ZGB2qFE51thFqJE+QG4XXEanRb0UPBabU nyhaJxUGTUgguYrM5rqKQzKfVXe884X2pBm+XGxoeyvoXLWBDTkV6bjfr g==; X-CSE-ConnectionGUID: NRxSiTFnT3ucBnaYj7CaZg== X-CSE-MsgGUID: f9DUSKXSTSaAuvdcfD2xCQ== X-IronPort-AV: E=Sophos;i="6.14,278,1736838000"; d="scan'208";a="44096112" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 26 Mar 2025 08:36:33 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Wed, 26 Mar 2025 08:35:52 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Wed, 26 Mar 2025 08:35:52 -0700 From: To: , , , , , , , , CC: , , , , , Ryan Wanner Subject: [PATCH v4 09/11] ARM: dts: microchip: sama7d65: Add SRAM and DRAM components support Date: Wed, 26 Mar 2025 08:35:42 -0700 Message-ID: <96c1240e8d77d7a4dad6291220e65b4b708db616.1742936082.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ryan Wanner Add SRAM, secumod, UDDRC, and DDR3phy to enable support for low power modes. Signed-off-by: Ryan Wanner --- arch/arm/boot/dts/microchip/sama7d65.dtsi | 35 +++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi index b6710ccd4c36..7d71e7326e3a 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -47,6 +47,14 @@ slow_xtal: clock-slowxtal { }; }; + ns_sram: sram@100000 { + compatible = "mmio-sram"; + reg = <0x100000 0x20000>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + }; + soc { compatible = "simple-bus"; ranges; @@ -58,6 +66,23 @@ sfrbu: sfr@e0008000 { reg = <0xe0008000 0x20>; }; + securam: sram@e0000800 { + compatible = "microchip,sama7d65-securam", "atmel,sama5d2-securam", "mmio-sram"; + reg = <0xe0000800 0x4000>; + ranges = <0 0xe0000800 0x4000>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 17>; + #address-cells = <1>; + #size-cells = <1>; + no-memory-wc; + }; + + secumod: secumod@e0004000 { + compatible = "microchip,sama7d65-secumod", "atmel,sama5d2-secumod", "syscon"; + reg = <0xe0004000 0x4000>; + gpio-controller; + #gpio-cells = <2>; + }; + pioa: pinctrl@e0014000 { compatible = "microchip,sama7d65-pinctrl", "microchip,sama7g5-pinctrl"; reg = <0xe0014000 0x800>; @@ -227,6 +252,16 @@ i2c10: i2c@600 { }; }; + uddrc: uddrc@e3800000 { + compatible = "microchip,sama7d65-uddrc", "microchip,sama7g5-uddrc"; + reg = <0xe3800000 0x4000>; + }; + + ddr3phy: ddr3phy@e3804000 { + compatible = "microchip,sama7d65-ddr3phy", "microchip,sama7g5-ddr3phy"; + reg = <0xe3804000 0x1000>; + }; + gic: interrupt-controller@e8c11000 { compatible = "arm,cortex-a7-gic"; reg = <0xe8c11000 0x1000>, From patchwork Wed Mar 26 15:35:43 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Wanner X-Patchwork-Id: 876430 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 15B771F8721; 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X-CSE-ConnectionGUID: NRxSiTFnT3ucBnaYj7CaZg== X-CSE-MsgGUID: 1gufScu5RJGEEVRHYn0edQ== X-IronPort-AV: E=Sophos;i="6.14,278,1736838000"; d="scan'208";a="44096115" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 26 Mar 2025 08:36:33 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Wed, 26 Mar 2025 08:35:52 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Wed, 26 Mar 2025 08:35:52 -0700 From: To: , , , , , , , , CC: , , , , , Ryan Wanner Subject: [PATCH v4 10/11] ARM: dts: microchip: sama7d65: Add RTT and GPBR Support for sama7d65 SoC Date: Wed, 26 Mar 2025 08:35:43 -0700 Message-ID: <0a6ac5965a4422e82768579ee5a0540bcf15fa5b.1742936082.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ryan Wanner Add RTT support for SAMA7D65 SoC. The GPBR is added so the SoC is able to store the RTT time data. Signed-off-by: Ryan Wanner --- arch/arm/boot/dts/microchip/sama7d65.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi index 7d71e7326e3a..59b43a633aef 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -132,6 +132,13 @@ shdwc: poweroff@e001d200 { status = "disabled"; }; + rtt: rtc@e001d300 { + compatible = "microchip,sama7d65-rtt", "atmel,at91sam9260-rtt"; + reg = <0xe001d300 0x30>; + interrupts = ; + clocks = <&clk32k 0>; + }; + clk32k: clock-controller@e001d500 { compatible = "microchip,sama7d65-sckc", "microchip,sam9x60-sckc"; reg = <0xe001d500 0x4>; @@ -146,6 +153,11 @@ rtc: rtc@e001d800 { clocks = <&clk32k 1>; }; + gpbr: syscon@e001d700 { + compatible = "microchip,sama7d65-gpbr", "syscon"; + reg = <0xe001d700 0x48>; + }; + chipid@e0020000 { compatible = "microchip,sama7d65-chipid"; reg = <0xe0020000 0x8>; From patchwork Wed Mar 26 15:35:44 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Wanner X-Patchwork-Id: 876645 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4D9231F891C; Wed, 26 Mar 2025 15:36:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743003405; cv=none; b=ja4KcBl35AJV9SRm3PC3UQHIB5CPQqjZfoP0zQ+rsvGst9w70zJ/v8iaqePhC0zZbw2QL6u3GUMKmFIEr8xdOtXQaxEeJlkGd+jNNKKYAgVl2Zl3Sntg+L9vE6+968ywG0ievm7hGoU3fOh6plUX4W45SWN8gR2Grz/BRfI/55Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743003405; c=relaxed/simple; bh=cp3KlP5kz8uShLGylSzqchQUQS7t4AEaR6YGK7e5dDw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=bWdbxrEugj/QmEECjRjhJArkyXWdksVYRWic6nC5JkMyOyY01ihQHvo6b+TelxiO+RomQuob3dn8oHLBb0OyCoXsg1o3jLHLpX0U4iKyIAuxWWyvg1wboARwsMXujw/EuLJvcgcmAkJkuWi0b1bzxWONYhSpwc+9v/eJjRZ5ZX4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=dHRwYjUI; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="dHRwYjUI" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1743003403; x=1774539403; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cp3KlP5kz8uShLGylSzqchQUQS7t4AEaR6YGK7e5dDw=; b=dHRwYjUIxI4EQ8n9z1Oxj7oDFkEQndeCH6g04XRifCjB4FMabvGJ1cGt Y9X0DeIpGwbj0MKMEpxcIgqDsVANvu0zVA6T0tpox6//k4K+CfJJDOmzX sTWXAmMP3rn3WHBUp6LfMO4Uv/MIcReuNat2p8czPe8brsFYDu5s26vVC HyZz4RtmJxBpVx0F3qkhKFwxGPoNAPj+zYA19JwaTwlG5DXsH1QRKJIrT uWuRxDWBgHtfmh65KpU5grOchln+ZOU2ybss51060Y8+8urvIFZzibCC4 fPsm9mjxoQK1+67XtKwvucBqntT2dscuNOZYQxxYsngR7GByiOIWntcJ9 g==; X-CSE-ConnectionGUID: NRxSiTFnT3ucBnaYj7CaZg== X-CSE-MsgGUID: yVJD9QDcSWChedzT1e/Itg== X-IronPort-AV: E=Sophos;i="6.14,278,1736838000"; d="scan'208";a="44096117" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 26 Mar 2025 08:36:33 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Wed, 26 Mar 2025 08:35:52 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Wed, 26 Mar 2025 08:35:52 -0700 From: To: , , , , , , , , CC: , , , , , Ryan Wanner Subject: [PATCH v4 11/11] ARM: dts: microchip: sama7d65: Add RTT timer to curiosity board Date: Wed, 26 Mar 2025 08:35:44 -0700 Message-ID: <314561e3237b84d3764bd1dc9967f852ee452c30.1742936082.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ryan Wanner Add RTT timer with backup register for SAMA7D65_Curiosity board. Signed-off-by: Ryan Wanner --- arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts b/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts index 30fdc4f55a3b..3105fe1766c3 100644 --- a/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts +++ b/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts @@ -141,6 +141,10 @@ pinctrl_uart6_default: uart6-default { }; }; +&rtt { + atmel,rtt-rtc-time-reg = <&gpbr 0x0>; +}; + &sdmmc1 { bus-width = <4>; pinctrl-names = "default";