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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c0b79e33asm12254361f8f.66.2025.03.31.12.48.27 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 31 Mar 2025 12:48:28 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell , Richard Henderson Subject: [PULL 01/23] hw/arm/armv7m: Expose and access System Control Space as little endian Date: Mon, 31 Mar 2025 21:47:59 +0200 Message-ID: <20250331194822.77309-2-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250331194822.77309-1-philmd@linaro.org> References: <20250331194822.77309-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We only build ARM system emulators using little endianness, so the MO_TE definition always expands to MO_LE, and DEVICE_TARGET_ENDIAN to DEVICE_LITTLE_ENDIAN. Replace the definitions by their expanded value, making it closer to the Armv7-M Architecture Reference Manual (ARM DDI 0403E) description: The System Control Space (SCS, address range 0xE000E000 to 0xE000EFFF) is a memory-mapped 4KB address space that provides 32-bit registers for configuration, status reporting and control. All accesses to the SCS are little endian. Fixes: d5d680cacc ("memory: Access MemoryRegion with endianness") Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson Message-Id: <20250312104821.1012-1-philmd@linaro.org> --- hw/arm/armv7m.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index 98a69846119..64009174b97 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -140,7 +140,7 @@ static MemTxResult v7m_sysreg_ns_write(void *opaque, hwaddr addr, /* S accesses to the alias act like NS accesses to the real region */ attrs.secure = 0; return memory_region_dispatch_write(mr, addr, value, - size_memop(size) | MO_TE, attrs); + size_memop(size) | MO_LE, attrs); } else { /* NS attrs are RAZ/WI for privileged, and BusFault for user */ if (attrs.user) { @@ -160,7 +160,7 @@ static MemTxResult v7m_sysreg_ns_read(void *opaque, hwaddr addr, /* S accesses to the alias act like NS accesses to the real region */ attrs.secure = 0; return memory_region_dispatch_read(mr, addr, data, - size_memop(size) | MO_TE, attrs); + size_memop(size) | MO_LE, attrs); } else { /* NS attrs are RAZ/WI for privileged, and BusFault for user */ if (attrs.user) { @@ -174,7 +174,7 @@ static MemTxResult v7m_sysreg_ns_read(void *opaque, hwaddr addr, static const MemoryRegionOps v7m_sysreg_ns_ops = { .read_with_attrs = v7m_sysreg_ns_read, .write_with_attrs = v7m_sysreg_ns_write, - .endianness = DEVICE_NATIVE_ENDIAN, + .endianness = DEVICE_LITTLE_ENDIAN, }; static MemTxResult v7m_systick_write(void *opaque, hwaddr addr, @@ -187,7 +187,7 @@ static MemTxResult v7m_systick_write(void *opaque, hwaddr addr, /* Direct the access to the correct systick */ mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]), 0); return memory_region_dispatch_write(mr, addr, value, - size_memop(size) | MO_TE, attrs); + size_memop(size) | MO_LE, attrs); } static MemTxResult v7m_systick_read(void *opaque, hwaddr addr, @@ -199,14 +199,14 @@ static MemTxResult v7m_systick_read(void *opaque, hwaddr addr, /* Direct the access to the correct systick */ mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]), 0); - return memory_region_dispatch_read(mr, addr, data, size_memop(size) | MO_TE, - attrs); + return memory_region_dispatch_read(mr, addr, data, + size_memop(size) | MO_LE, attrs); } static const MemoryRegionOps v7m_systick_ops = { .read_with_attrs = v7m_systick_read, .write_with_attrs = v7m_systick_write, - .endianness = DEVICE_NATIVE_ENDIAN, + .endianness = DEVICE_LITTLE_ENDIAN, }; /* From patchwork Mon Mar 31 19:48:00 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877307 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp1924516wrs; Mon, 31 Mar 2025 12:50:16 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVy61Nd8DauP3+GeFkjkgbcCkcGbt1vX34jg3WFrNuCjtGrQps2rcfaraBy4Klze9s1MX5XRQ==@linaro.org X-Google-Smtp-Source: AGHT+IGzULhLNa1sRjDmNKbkP4/JPueUSm331HnIzPaRJ105FIpwuX2AQNtIimAGQXllyqQopd4c X-Received: by 2002:a05:622a:11c8:b0:476:909b:8287 with SMTP id d75a77b69052e-477ed7f361amr202506101cf.20.1743450616451; Mon, 31 Mar 2025 12:50:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743450616; cv=none; d=google.com; s=arc-20240605; b=gHgMwwBQOxgM3xAKxlFquHRMs/sSNj9dlG+N6kyBFzMae6mzA/WTbvyla2xqPTSQcB cOwvt5vKN1KhTbFClWYuyhjK7uRW7RqcXN4HbsCd5OV13koHX8cMh/iObmr5VUGyoF/F STVzDqNxEd1RP2vIRbbtHZBjMExR19F0fzT9uhzi1oCKmoDLMxcn+nvxClDHV6nckRD7 AmE40ts7gYeDQ4GDoSc7e95OMGgy+js3us8xyP0++/mupLJoLQF1NdmweAIc7/ClX7I9 cbYWDhOzQmPiyGyzEs6Cqh21bt1/gOaMB3gfEvxlhW6uedHBG6AQkFv3utqkgaxxkDB9 UZOA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=dNjcGIacRf9GBqLFNdn+7xavPFEAK8T6dq58lm39+Ws=; fh=dYlV9XAIaLAMfpbgN6aNSnDem32RGofjQqKa/8GDpMk=; b=OhSasuVBYMsCNhDagm2lv/mjV4Ir3RmusMs7a7XO6q1OK1lX/LdGcO0pat5dY8p9LC QKO7daYU2xED5WNwomtlBpWWeFhRWf3+L6YFeWYL1IgHelYg8iG4FXfZstcAda0JYW+4 zVWpqQEbiWfSx/+DVuFjQsAMszn7Ki50PV3izwAq2kb/ExyuHlufGJPeCDHes/q+yVo8 dfJl1kZ0eO7YPL54mIHLtSgkGhagiW4q8+zFr+/lnhm/YayvGWyfA6jcKPNfYaGgGHGl Vxa+kpzR1ZJKJeqWmJVr8KwkMS2HneD80IZrRcca7bJx6wOYgGSjWMY7uBJXI8nQKcWH CChA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=M2xNUzbS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d90000a09sm130314525e9.35.2025.03.31.12.48.32 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 31 Mar 2025 12:48:32 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bernhard Beschow , Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PULL 02/23] hw/arm/imx8mp-evk: Fix reference count of SoC object Date: Mon, 31 Mar 2025 21:48:00 +0200 Message-ID: <20250331194822.77309-3-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250331194822.77309-1-philmd@linaro.org> References: <20250331194822.77309-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Bernhard Beschow TYPE_FSL_IMX8MP is created using object_new(), so must be realized with qdev_realize_and_unref() to keep the reference counting intact. Fixes: a4eefc69b237 "hw/arm: Add i.MX 8M Plus EVK board" Signed-off-by: Bernhard Beschow Reviewed-by: Peter Maydell Message-ID: <20250318205709.28862-2-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/imx8mp-evk.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/imx8mp-evk.c b/hw/arm/imx8mp-evk.c index e1a7892fd7c..e1a21e52f96 100644 --- a/hw/arm/imx8mp-evk.c +++ b/hw/arm/imx8mp-evk.c @@ -37,7 +37,7 @@ static void imx8mp_evk_init(MachineState *machine) s = FSL_IMX8MP(object_new(TYPE_FSL_IMX8MP)); object_property_add_child(OBJECT(machine), "soc", OBJECT(s)); object_property_set_uint(OBJECT(s), "fec1-phy-num", 1, &error_fatal); - qdev_realize(DEVICE(s), NULL, &error_fatal); + qdev_realize_and_unref(DEVICE(s), NULL, &error_fatal); memory_region_add_subregion(get_system_memory(), FSL_IMX8MP_RAM_START, machine->ram); From patchwork Mon Mar 31 19:48:01 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877325 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp1925830wrs; Mon, 31 Mar 2025 12:54:37 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWEV4Cbbr2YRsAeYD2fCpjdNV2rGveUpwN22Y1SPr/3e3KAHY+96l/YLztDJjR9vnIobcwRjA==@linaro.org X-Google-Smtp-Source: AGHT+IFJZXjFOLxPBMgFa7cqnLzq9XiqDjaB2KO9u4qa/T5muRbCbFzVIP5aWoZJ1dk6z7UzyViq X-Received: by 2002:ac8:5d16:0:b0:476:a90b:986b with SMTP id d75a77b69052e-477e4ba968cmr176000991cf.28.1743450877553; Mon, 31 Mar 2025 12:54:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743450877; cv=none; d=google.com; s=arc-20240605; b=GY2VYGAJRinddaXhCVynesiRyfj9RP416uqZ//3TPw85Phf5AojC8X8Zf4IJX9LA5a XZ8SgCG8TvrMqhDSBJqgwL9RSfvpn3t02Mho60zveNypuzmIEB71mt5IKUAUijrbUKsu +Pgf6bfUDzqlG3PdcCIi2V0kXIJXOH0UlN6/Ta91f2OMBDm5g+vm33MKjk/jKa1+++BE tm1+vPLyg/A5srMt1xyHpnY4I1H3NhW35Hk5ylDtTVR82xOIOsR8tlsNGjaainLAGlYd 26zH57tbDINQ/SmUKIfPU48caIn4/OHczGJAYSxVHS64DY5pJyCWZseRxShO/FEQuozO Yo6Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=txTiE4d1NZi9r9wcwRp40Op4LBLauweOXwjfQZIQKOA=; fh=5H1BVusQPb9ajb8BeXJICkdOZU2JfzUhwvN62Tsp+O0=; b=Qe5gvK4n9pcvyu0A+/dmgzo0Tt38Da4+eYzX/Aw0W2ra82DYldhd6UYnMfnov5rFcW H7vngdTei0aJU7dvwhBqxjqGqTjRyiLbXV4upKpuOfYI08BJwaQfHR7a1TBeEw0bzCe8 5xW7rrnuQ2p2VU9V8mq4647nCwQTcccZWs5GfTyWMRvCPvn/DSDPNzYCVRJcLTKQFfoy X1M76ikZx7PK89BK3ljEC1ZQtXbpdarq9Ms6D4je+uUqyT7qtduauumPkWJiAl0U/RfG 9rK0T5mC2Uee+fINq34y/uJVX4e1lfsiktuPEALXaq7anV6mZ/ScWy6NkE4UXh5EGqd/ w9WA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yoj4gDzz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c0b658b5dsm11970208f8f.3.2025.03.31.12.48.37 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 31 Mar 2025 12:48:38 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bernhard Beschow , Thomas Huth , Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PULL 03/23] hw/arm/fsl-imx8mp: Derive struct FslImx8mpState from TYPE_SYS_BUS_DEVICE Date: Mon, 31 Mar 2025 21:48:01 +0200 Message-ID: <20250331194822.77309-4-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250331194822.77309-1-philmd@linaro.org> References: <20250331194822.77309-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Bernhard Beschow Deriving from TYPE_SYS_BUS_DEVICE fixes the SoC object to be reset upon machine reset. It also makes the SoC implementation not user-creatable which can trigger the following crash: $ ./qemu-system-aarch64 -M virt -device fsl-imx8mp ** ERROR:../../devel/qemu/tcg/tcg.c:1006:tcg_register_thread: assertion failed: (n < tcg_max_ctxs) Bail out! ERROR:../../devel/qemu/tcg/tcg.c:1006:tcg_register_thread: assertion failed: (n < tcg_max_ctxs) Aborted (core dumped) Fixes: a4eefc69b237 "hw/arm: Add i.MX 8M Plus EVK board" Reported-by: Thomas Huth Suggested-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Signed-off-by: Bernhard Beschow Message-ID: <20250318205709.28862-3-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- include/hw/arm/fsl-imx8mp.h | 3 ++- hw/arm/fsl-imx8mp.c | 2 +- hw/arm/imx8mp-evk.c | 2 +- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/include/hw/arm/fsl-imx8mp.h b/include/hw/arm/fsl-imx8mp.h index bc97fc416eb..22fdc0d67c2 100644 --- a/include/hw/arm/fsl-imx8mp.h +++ b/include/hw/arm/fsl-imx8mp.h @@ -26,6 +26,7 @@ #include "hw/timer/imx_gpt.h" #include "hw/usb/hcd-dwc3.h" #include "hw/watchdog/wdt_imx2.h" +#include "hw/sysbus.h" #include "qom/object.h" #include "qemu/units.h" @@ -49,7 +50,7 @@ enum FslImx8mpConfiguration { }; struct FslImx8mpState { - DeviceState parent_obj; + SysBusDevice parent_obj; ARMCPU cpu[FSL_IMX8MP_NUM_CPUS]; GICv3State gic; diff --git a/hw/arm/fsl-imx8mp.c b/hw/arm/fsl-imx8mp.c index c3f6da63220..82edf61082a 100644 --- a/hw/arm/fsl-imx8mp.c +++ b/hw/arm/fsl-imx8mp.c @@ -702,7 +702,7 @@ static void fsl_imx8mp_class_init(ObjectClass *oc, void *data) static const TypeInfo fsl_imx8mp_types[] = { { .name = TYPE_FSL_IMX8MP, - .parent = TYPE_DEVICE, + .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(FslImx8mpState), .instance_init = fsl_imx8mp_init, .class_init = fsl_imx8mp_class_init, diff --git a/hw/arm/imx8mp-evk.c b/hw/arm/imx8mp-evk.c index e1a21e52f96..f17d5db466d 100644 --- a/hw/arm/imx8mp-evk.c +++ b/hw/arm/imx8mp-evk.c @@ -37,7 +37,7 @@ static void imx8mp_evk_init(MachineState *machine) s = FSL_IMX8MP(object_new(TYPE_FSL_IMX8MP)); object_property_add_child(OBJECT(machine), "soc", OBJECT(s)); object_property_set_uint(OBJECT(s), "fec1-phy-num", 1, &error_fatal); - qdev_realize_and_unref(DEVICE(s), NULL, &error_fatal); + sysbus_realize_and_unref(SYS_BUS_DEVICE(s), &error_fatal); memory_region_add_subregion(get_system_memory(), FSL_IMX8MP_RAM_START, machine->ram); From patchwork Mon Mar 31 19:48:02 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877322 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp1925663wrs; Mon, 31 Mar 2025 12:54:05 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVswVwHy3WpVzN8BrocTqZcZNe9za8uGFeI8FClfThuNfTVSOVcux1CH7eUlcAFqqD+ek2IhA==@linaro.org X-Google-Smtp-Source: AGHT+IHhlhkVk9xpRxR4fur0vZriSsZILRjAV/JXWtttHLA+6HmdDdwEw+Lppgr7VQRYaPmSHJvX X-Received: by 2002:ad4:5c69:0:b0:6e8:ddf6:d122 with SMTP id 6a1803df08f44-6eed5f88e25mr181658766d6.3.1743450844907; Mon, 31 Mar 2025 12:54:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743450844; cv=none; d=google.com; s=arc-20240605; b=jHSMPFgC9klGeVxHcdt27FLfhiJO2WS7nXNUhzviaswvdmJYmM7QmDnt/q6Fd433sP P3/9vj4anP7jxleeY3+2YuPWZMJ1oQ7HrinedzOcAfZ/Xmw/yxnex1l8xdKAuHN+6qMj XrOSwxv6KFBuIigj6HnNgOJ5Yj59DnRQZRH02tQ+3IlEuRxoCjOzsI0RNnaN3knIwTJV F71rfzQra9xQGpfipVo3qjeq7ftxbkNuliiip4t6M0R6g/UUXbFvkliKlxyBfeEsyz9R qtoJ7dkLrL7wC0I8nb+zng775vuFc4pk4DgZIMQ/QLrTB3yyZo2+vabrHCKSUvgRAEdv W/SQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=olSuf49HOKgWluGh/CcNrZxy5tYywYETl9l4VOkHGws=; fh=dYlV9XAIaLAMfpbgN6aNSnDem32RGofjQqKa/8GDpMk=; b=lwcyRP9YDlhC0SvBfien6JMZKdcCpaCddbtLyjZi4690lKJJl5TIzS/wfy1FAy9pWJ 1BA95Py6mSuHe2wHKDdR394KJbCZCb3rovzUPdSSfvbpXmaClaov8zzIFmuS8Fa/EVba NH50IJ0TaBH2WwT+g8ygx3afg2Wum8FqTWwvOrh2ndw2mu5PpRIvhG6l1Wq9YJN/dcJU ezmQS3h4OZbVC0OeViFzoGTWezk43PkRU3SkEwVHbm3RPM+NQWM3Uu0b+BA6neFPYGix 43uDPpqKMqWbpHEAucnkfLBJ5Otz+xmvJZ9Kg2Qwg2wVG9UBIgFa5C6vwgWZf4D03eVe 4gcA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BZG4ra6K; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c1845e66esm6049263f8f.18.2025.03.31.12.48.42 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 31 Mar 2025 12:48:43 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bernhard Beschow , Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PULL 04/23] hw/arm/fsl-imx8mp: Remove unused define Date: Mon, 31 Mar 2025 21:48:02 +0200 Message-ID: <20250331194822.77309-5-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250331194822.77309-1-philmd@linaro.org> References: <20250331194822.77309-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Bernhard Beschow The SoC has three SPI controllers, not four. Remove the extra define of an SPI IRQ. Fixes: 06908a84f036 "hw/arm/fsl-imx8mp: Add SPI controllers" Reviewed-by: Peter Maydell Signed-off-by: Bernhard Beschow Message-ID: <20250318205709.28862-4-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- include/hw/arm/fsl-imx8mp.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/hw/arm/fsl-imx8mp.h b/include/hw/arm/fsl-imx8mp.h index 22fdc0d67c2..d016f7d3371 100644 --- a/include/hw/arm/fsl-imx8mp.h +++ b/include/hw/arm/fsl-imx8mp.h @@ -238,7 +238,6 @@ enum FslImx8mpIrqs { FSL_IMX8MP_ECSPI1_IRQ = 31, FSL_IMX8MP_ECSPI2_IRQ = 32, FSL_IMX8MP_ECSPI3_IRQ = 33, - FSL_IMX8MP_ECSPI4_IRQ = 34, FSL_IMX8MP_I2C1_IRQ = 35, FSL_IMX8MP_I2C2_IRQ = 36, From patchwork Mon Mar 31 19:48:03 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877314 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp1925146wrs; Mon, 31 Mar 2025 12:52:21 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCX5wrzK/hA2F9w2OcTMhizTT/m5OFW+/8IdwkYf43NGvgU+gdHcViLRr7WyYvWvTA0oxRCWXg==@linaro.org X-Google-Smtp-Source: AGHT+IFU/TDBzlhe6pJvMBhG+05MhuwKBeREmdXfo2ZF2kSds22GreHgMxYtxL1p3csbTc+63DBN X-Received: by 2002:a05:620a:2995:b0:7c5:3c69:2bd2 with SMTP id af79cd13be357-7c629490126mr1532970985a.13.1743450741681; Mon, 31 Mar 2025 12:52:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743450741; cv=none; d=google.com; s=arc-20240605; b=iEIfIYBQt44jCHGacb4WS/+9nI4mS9wyBNuCoweiLXRTlUiKFlSM0ckJe5NWGnyDj3 KqDTyVh4vlHx4VHffPaDjIiGfJMvXEWtdzBSr3rB2OfJfRRXZHPGhxn4TfFlKvfiVjVI lWlg7sK0tl50IngB9DN03aWTscbitUn2DV7Ob4CpZ568hTs+6wzssRqO4PMRvH3n5JYl bvXX/mKnoom/4sIa/jS3wzSXOWumKlOnWvTvk7v0ywPABjbz7umHc/bYS8Gfs3Rn2HMU hnm8OPG/nBBAJ9yMRvXpfk+NFLcaIYLPAMwZMA3BuNsNh5nhhBEJZutf6FkGelDt0Ebi k9rQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=bjfZMqY7kEtNVcowX1vqYv9wJwb4LYxFTdGWnR4E878=; fh=ewablq11zO+WL7X4n3MMOCnLV8HxPJyS9XF5ZM+AHaM=; b=cXsSP5Dr2wydsZBJkTPrvNmaKbVTEFljIUMCgh4zaengvv9lv0dxrZUeLSrS4x4nwm dGwmFU0e+5WVf9Id/VOFUcwUc6hLogu8YRvpw+NF8ufk+FfT9VV5msBl2yP2sOgXMuNT m2UtNjY+RNBf+XKLpboXnLtv6xYKd/UnSgfsIBW8A6V47FcyKB6imDkQRFOJTFR+YeAs 8Xoegl46/ZoMS+1COgI+vYd3X/MJZwVorwOhtMxVfTg4NwWJIs2uN27RJvbTEyjWI/Bx 9EAWQErKYfo7bJ0WZzQAi+0N7TcDnjbhZHtRfw2c9ab8jCjYWYlhiBxLDz2yvXHu8HY2 gG5A==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="zY/r19jO"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c0b79e393sm12252633f8f.72.2025.03.31.12.48.47 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 31 Mar 2025 12:48:47 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PULL 05/23] hw/core/cpu: Use size_t for memory_rw_debug len argument Date: Mon, 31 Mar 2025 21:48:03 +0200 Message-ID: <20250331194822.77309-6-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250331194822.77309-1-philmd@linaro.org> References: <20250331194822.77309-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Match the prototype of cpu_memory_rw_debug(). Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-Id: <20250325224403.4011975-4-richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé --- include/hw/core/cpu.h | 2 +- target/sparc/cpu.h | 2 +- target/sparc/mmu_helper.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 5d11d26556a..abd8764e834 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -154,7 +154,7 @@ struct CPUClass { int (*mmu_index)(CPUState *cpu, bool ifetch); int (*memory_rw_debug)(CPUState *cpu, vaddr addr, - uint8_t *buf, int len, bool is_write); + uint8_t *buf, size_t len, bool is_write); void (*dump_state)(CPUState *cpu, FILE *, int flags); void (*query_cpu_fast)(CPUState *cpu, CpuInfoFast *value); int64_t (*get_arch_id)(CPUState *cpu); diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 462bcb6c0e6..68f8c21e7cb 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -604,7 +604,7 @@ void dump_mmu(CPUSPARCState *env); #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) int sparc_cpu_memory_rw_debug(CPUState *cpu, vaddr addr, - uint8_t *buf, int len, bool is_write); + uint8_t *buf, size_t len, bool is_write); #endif /* translate.c */ diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 7548d01777c..3821cd91ec7 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -389,7 +389,7 @@ void dump_mmu(CPUSPARCState *env) * that the sparc ABI is followed. */ int sparc_cpu_memory_rw_debug(CPUState *cs, vaddr address, - uint8_t *buf, int len, bool is_write) + uint8_t *buf, size_t len, bool is_write) { CPUSPARCState *env = cpu_env(cs); target_ulong addr = address; From patchwork Mon Mar 31 19:48:04 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877311 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp1924663wrs; Mon, 31 Mar 2025 12:50:49 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVhoEEOxBl8hkTxOt0ja/1B7qrxLu+VdspydPzB6cIS6wX8P38S4z89CVjDOhiiZSHGumr7gg==@linaro.org X-Google-Smtp-Source: AGHT+IHRfEXMlwt5uHtYyF58dgCF8fJ64K+hqUD0aZUKrThMKQT1y9WRDhewTf32RH8yZFYCG1ss X-Received: by 2002:a05:6214:c41:b0:6e8:ffb6:2f8e with SMTP id 6a1803df08f44-6eef5ed4b7emr4361316d6.32.1743450648788; Mon, 31 Mar 2025 12:50:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743450648; cv=none; d=google.com; s=arc-20240605; b=Ha4V59jKwxsNSqCIzDMobVOf565pUqfwKO1tRyb8zzF99pb9Xyx4xY+0vUgXWdMumP Btblasgw/Is3I1JsCg6KocxdXDXJq1y+WhxyoA5d4LlzmmjGpz8NAHH/sPraNYHRm56+ o3a1O7uJlnKX4lJFYbn2XBR4LUibGtZkgmff90UCajeRsYYnWeXgpvxY6zcUbjw+kkcv XqgLsQLNG/JtQ2Qnypdtsv3a6VeBe7JkhgpJ8BcrPJ2Su1W9zBsyAv716vf0dl7OkMqp QF/0s7cEuxXA/fmToxZ68XZuajs0c32Skl/aHQksdolCQheFzLCr6zt3tvv8JTf6Y6x9 QKEw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=e/pv1g6SQzEtfRxwgUUw5mriOJrSVBq7ehEQgs2d4yE=; fh=7gZvlf5c4KqY17UefY3VLfTm+bVDxskXHVg/jnbpAaM=; b=TjClcJOv+melG+9dy+RlmwGzfv2O1+PmcVzy2Ruf9f5HrbRXM2GcTKWATCJqw4l9Nx t3VOnIvGd6lXAxnjpeTlboj7ygBLoJbZetAan2AoNUNjA+lYwjryVv/5Joz2ZrX6DmDX OHSm6oN1/eYnemaCLjs7JCCMY3IkbuLDGuFf0nWDn6vqC59i1swElXSLu4sCPhPk+GIk azNPmRzrSrCWUzNvovUweyrWMQL3z0Sn1cmxP4RsxT+G+CBYDtS103/nMMY/U9pNbIG9 PQTOsRH/0E21zf+YKj9qp9zORR+4yjq83RoryvOc7fszJu2IjY3waoltaZfocv7btiK6 73wA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pLHJFmGR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d90000a09sm130321915e9.35.2025.03.31.12.48.52 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 31 Mar 2025 12:48:52 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Thomas Huth Subject: [PULL 06/23] hw/block/m25p80: Categorize and add description Date: Mon, 31 Mar 2025 21:48:04 +0200 Message-ID: <20250331194822.77309-7-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250331194822.77309-1-philmd@linaro.org> References: <20250331194822.77309-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Message-Id: <20250325224310.8785-3-philmd@linaro.org> --- hw/block/m25p80.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index b84c6afb327..0887c103e4f 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c @@ -1870,7 +1870,9 @@ static void m25p80_class_init(ObjectClass *klass, void *data) dc->vmsd = &vmstate_m25p80; device_class_set_props(dc, m25p80_properties); device_class_set_legacy_reset(dc, m25p80_reset); + set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); mc->pi = data; + dc->desc = "Serial Flash"; } static const TypeInfo m25p80_info = { From patchwork Mon Mar 31 19:48:05 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877305 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp1924334wrs; Mon, 31 Mar 2025 12:49:44 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVdfBW/xxahibDVQT85aiXSwUfG0q9XAS0izWD7hYzhjPLHGP1Mk7vHDgfmWEaH7Dp9omUeaQ==@linaro.org X-Google-Smtp-Source: AGHT+IHh+KfbHM/uJCGAZiIU4RsnE1uiS0hOTiuvY0Q3q0SLI5VWuivE/8yu7PVZ4N9nbWA2w/7a X-Received: by 2002:a05:620a:2941:b0:7c5:9a09:cb73 with SMTP id af79cd13be357-7c6865eaf10mr1288441285a.23.1743450584477; Mon, 31 Mar 2025 12:49:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743450584; cv=none; d=google.com; s=arc-20240605; b=UA+ICGJ7yAzF783t+7hQwYr6duYt7vDnjtmF0ERgKPEjh1oIw9AZttgPpcTQ+P3/5h mQ8cQptDYFlUjkyv4LnMuxIku/Kc5CWLPspfQbpBxmUc886jJ2TFJCDSQrbIPsc3EjOc 2zddjr16tiNewqkTE1LWwQ9zPGrdCfahuarCsndugPD+6Pm64LEiv/BwBOe9JNxOBsGz W07SZ7uvb46fTON4kLAIxDkiH8N2a0FxRoYw9WhfEToDPKzjydAmgX0m9sfjKzas/qYv dYTMfroZtuVXWH6Z25KWYBGew58UKmMC46/E/diO3tXf2zmgA4RuzvGDa/7hkEWVcpLc YIgQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Ia8Kw97DGhP1r9MtPxxlIU481UcVxEFaeD8v9v4GxU4=; fh=7gZvlf5c4KqY17UefY3VLfTm+bVDxskXHVg/jnbpAaM=; b=ZkDYKECwzd5EZZ+0VUPGhT2ylyrEIilLWTgs6//CBUfkU2p+xD1rimMM7AFT8TLXNr cCt0U7z2OyT2eIROVOoYJxMxy8pK7FGuLmE/gqeOYtJxsR29gey4duy24qNhD2Ac5yiw 28JoJgClX98XwjwYd4xUyRPPawXV9ytWJ7Z1c4R8vAob6NcQblgGVN45OaZpAt+tNlzL YgG6VowC46WaAbOp1Octdo8T6iGedYyCrkf5G/FAb0vjMRaqDwCNBcWxMvJF/WyFA+dN dEzS1Y8W71IU5TlSfdgVMJnxQzZKDN0R8VQl75jhsuG3qmx2eZjduUGJZtEIyyb7QVDZ 4Xtw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=o0Y2MlNh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ea8df934esm263705e9.2.2025.03.31.12.48.56 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 31 Mar 2025 12:48:57 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Thomas Huth Subject: [PULL 07/23] hw/display/dm163: Add description Date: Mon, 31 Mar 2025 21:48:05 +0200 Message-ID: <20250331194822.77309-8-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250331194822.77309-1-philmd@linaro.org> References: <20250331194822.77309-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Message-Id: <20250325224310.8785-4-philmd@linaro.org> --- hw/display/dm163.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/display/dm163.c b/hw/display/dm163.c index 75a91f62bd3..f6f0ec0c632 100644 --- a/hw/display/dm163.c +++ b/hw/display/dm163.c @@ -330,7 +330,7 @@ static void dm163_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); ResettableClass *rc = RESETTABLE_CLASS(klass); - dc->desc = "DM163"; + dc->desc = "DM163 8x3-channel constant current LED driver"; dc->vmsd = &vmstate_dm163; dc->realize = dm163_realize; rc->phases.hold = dm163_reset_hold; From patchwork Mon Mar 31 19:48:06 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877327 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp1925945wrs; Mon, 31 Mar 2025 12:55:03 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXo3kJpPFII7u/vBmH8ajbptZQGsV0mabU/aOBXQwCH+9nJxCm4Wk/XUQjAxvNjbfcxsLeJwg==@linaro.org X-Google-Smtp-Source: AGHT+IFu/lL9V4Vbvb7w2epl8Lkpn00T6WlNUCXryXWGJwYToExX4+gGpGcYb/rBgTZq4wtoMMjT X-Received: by 2002:ac8:5890:0:b0:476:977c:2eb0 with SMTP id d75a77b69052e-478f6ca6021mr3861481cf.30.1743450902896; Mon, 31 Mar 2025 12:55:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743450902; cv=none; d=google.com; s=arc-20240605; b=G2lTdSVRBwQUBetDEOaUto/ru8Sv8/meq/ZvrstEdI6icRU+PVA7snA8nQ4vslgtT4 rsA8So3vUiAn1w/KMYhqQGkH2h4p1/FdxothvKJvLPJ6/bn//2wm+DQCmfKWzJYf8hCv hyNKDUKsluHH7y5cyD7tIr+Yfurjwn9UBNfM3rbotgRjtyyfHFlE06MzJPRjtuJ/HUFd 39biHahKKz0xBV96qw6qZ3vU4unkyIoc08KKEb9FMa1a1cZxI+s7CwhAVGMpxkV2xyg/ x6SyI2tpBLqV4TvC8WOWlc/A4hggADWXl9bSt+LhvHOD4fUd8b+/4WyeS1YB4cvm1PTZ k40Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=bDZSaGy5ysIeynjvE+nHvYblpD0ykj+qs33uCPj2VTM=; fh=7gZvlf5c4KqY17UefY3VLfTm+bVDxskXHVg/jnbpAaM=; b=CDgcFmwXcliRLMLoe1V3RJk/9MLfIKbOOD2cNBrXovCP72Rcaf++iGvXbwHWFy+tTU ggSxNj+C2z6kOHTzv1ZVqNEO2x/kofY3DTetKPJEH7y6VthX1svugjhR3Nj2WrWUV36u X+og9kHKRzwgunLuaxP+8ZuP2Tmk+btBFCMtIRzzWqtL2x6HPe1bq//UFZ3StD+mBule ceOK0fVlZ58YSOwP+pXDvCtqdFVs2mLkhAaO3QOq9o/rCk+c9NFcvSNonVQtl3XjG1re DvNrxGES5Argjt+Yf/w+2vsLRayQFn1zBILMcDAeWCjeWqB6+iu0Ek+3Ia42GUQE7P6e PZQw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OOf16HQY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c0b658ac5sm11851493f8f.1.2025.03.31.12.49.01 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 31 Mar 2025 12:49:01 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Thomas Huth Subject: [PULL 08/23] hw/dma/i82374: Categorize and add description Date: Mon, 31 Mar 2025 21:48:06 +0200 Message-ID: <20250331194822.77309-9-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250331194822.77309-1-philmd@linaro.org> References: <20250331194822.77309-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philmd@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Message-Id: <20250325224310.8785-5-philmd@linaro.org> --- hw/dma/i82374.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/dma/i82374.c b/hw/dma/i82374.c index 9652d47adcd..0bf69ef399b 100644 --- a/hw/dma/i82374.c +++ b/hw/dma/i82374.c @@ -150,6 +150,8 @@ static void i82374_class_init(ObjectClass *klass, void *data) dc->realize = i82374_realize; dc->vmsd = &vmstate_i82374; device_class_set_props(dc, i82374_properties); + dc->desc = "Intel 82374 DMA controller"; + set_bit(DEVICE_CATEGORY_MISC, dc->categories); } static const TypeInfo i82374_info = { From patchwork Mon Mar 31 19:48:07 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877309 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp1924556wrs; Mon, 31 Mar 2025 12:50:25 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVreSOs/nl8UyQ3URPMAhyUSYLoILVppswPpaE6sqOFfRlcorBlm9sFHhqqKsien1RR608gcw==@linaro.org X-Google-Smtp-Source: AGHT+IEWRPEUI6wAB1d4kr5F+6JPBHCvRYl/QmU1R2DnVzfjJC32RHUdo6JsP79rpxDx89TUpcB3 X-Received: by 2002:a05:620a:40d1:b0:7c5:95e6:62c9 with SMTP id af79cd13be357-7c62b589288mr1476289885a.29.1743450625020; Mon, 31 Mar 2025 12:50:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743450625; cv=none; d=google.com; s=arc-20240605; b=Q9U4GolqtXoeFiBK7sNKnf7NjAbgXfB2I5PN/wJJPqAr7JkNRXIzlKbiHdPpbmPe/m /CJljhW0r/WMf8+w6Sx3/26KodKkl4ALkfA9QKwKqcH1dA1SRB6clikAzjsJkWbF6n/w /vfk+UqNQqfmlZT6bP7SgESQhZ88tyR/uokOpkB9GSeAPkyjZIivYXWe2pGb5WDEjmTT V/2jIwnTc7u8Dy9Mok9cR9oDdwL21649UHr+Fo7ERK4BkkbgFrX5JHVQfrnTtkOQBpaK XS+1wvp/8pTA/pZe8RbJbqB6KeLXUfrn7PQt1ZGFmRkgTu++ZiQsI2ywn6T7pQ2r1bmt 2Few== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=CGSB9mapXUSE8SJ3Sr9SkrYPIF47w1Iq0wn1bPdtMLw=; fh=qi6M7+758Hm8qfC4GxHVnK55oMKkCiFOk69X0Z7vtIs=; b=d9xY9JGyhW5EHMDhA8GMme/TnxrcvkRSN0Gcob81sEXjKCG27ayoVyTh9KHn4IsPCg 2Iw2wHJkP3q51wH/eOoUlG+7r3mZYR0M1gloGWo99GDVtxMaNhYW9dRpJ70jFCK0Igja DCbXKP23L/Wven8+VArqejG9Lkl/t/9ZnM/nSfcBAwEgGppwug8NpEnQAbEHO07dJVKe vj/856InXiyAdL6+aI87fhbdLCCFuWmdIGrb8RO6n0sAQVwmajHUIfIeBjTRy4coOYDp NBn3uaQ9zSBBU+Hr83rU2bffc7Q1F8oOaO7gxYv2cEQ2h5PILce0MZQpd2hkMNckf2hf S3sQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DU+zAT9q; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c0b79e0d1sm12080196f8f.70.2025.03.31.12.49.06 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 31 Mar 2025 12:49:07 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 09/23] hw/mips: Mark the "mipssim" machine as deprecated Date: Mon, 31 Mar 2025 21:48:07 +0200 Message-ID: <20250331194822.77309-10-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250331194822.77309-1-philmd@linaro.org> References: <20250331194822.77309-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=philmd@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Thomas Huth We are not aware of anybody still using this machine, support for it has been withdrawn from the Linux kernel (i.e. there also won't be any future development anymore), and we are not aware of any binaries online that could be used for regression testing to avoid that the machine bitrots ... thus let's mark it as deprecated now. Signed-off-by: Thomas Huth Acked-by: Philippe Mathieu-Daudé Message-ID: <20250121103655.1285596-1-thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé --- docs/about/deprecated.rst | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst index e2b4f077d45..76291fdfd62 100644 --- a/docs/about/deprecated.rst +++ b/docs/about/deprecated.rst @@ -292,6 +292,19 @@ Big-Endian variants of MicroBlaze ``petalogix-ml605`` and ``xlnx-zynqmp-pmu`` ma Both ``petalogix-ml605`` and ``xlnx-zynqmp-pmu`` were added for little endian CPUs. Big endian support is not tested. +Mips ``mipssim`` machine (since 10.0) +''''''''''''''''''''''''''''''''''''' + +Linux dropped support for this virtual machine type in kernel v3.7, and +there does not seem to be anybody around who is still using this board +in QEMU: Most former MIPS-related people are working on other architectures +in their everyday job nowadays, and we are also not aware of anybody still +using old binaries with this board (i.e. there is also no binary available +online to check that this board did not completely bitrot yet). It is +recommended to use another MIPS machine for future MIPS code development +instead. + + Backend options --------------- From patchwork Mon Mar 31 19:48:08 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877308 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp1924517wrs; Mon, 31 Mar 2025 12:50:17 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUm7UiShaOlO7xQ/cJHAOnYGrvrvOmCdNApPEsZjIXqnZ46oFaAiiWn2LJCFi0Fwk03gyJ9IQ==@linaro.org X-Google-Smtp-Source: AGHT+IGLFgkF5UgRtmmgoZKoLHi9Xl0YimW614ha92KTV1K8+iL7CxEWSYUogAJ8UAmSohJK5s2g X-Received: by 2002:a05:622a:5c6:b0:476:fdaf:2177 with SMTP id d75a77b69052e-477ed815415mr159906241cf.28.1743450616773; Mon, 31 Mar 2025 12:50:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743450616; cv=none; d=google.com; s=arc-20240605; b=WB3DrYfa5EpqOZ+dg6DuscV4GHVLsr4WOkSwmTRh/pvl8SRHroDEt/ntFWNSLYYCrM OqLbC7kyEKLH0OBuETCMRrBv/UPPQbcsigOvtTFKi0+WqxlWMxwM2iHxj0fyyJPRYlZ8 /JbMt3Jzgl/BlOSmCebZ9Ll1jY1qYkGnhbTIiHEWBS4egrIKDc5BF3HpfdSSol2ispKr uJdZRyXE3lvHLEIyImITrTPFROd+jsdP5W3VXFhsSDOLUiFJk9kOtRLXoPSK+bcuk/3Q kzyz0aYLmndW3Kh8gUOmlCKgr1O8c3mjiZRB3P61QY4UDWRfpiMc07CUDEkUQcRdlPl6 4YLw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=mD0e9eaGkTJvGMcL9mwV8iKKrD2iOxihpH1h0trc4fc=; fh=CuDR88IkCRVAmhVijyFIzsCrLmYav7EhtIQjJa+plQU=; b=hZUNxS6FY2EQcv6tqmy3jPA0qws9TGMNKuwkLN55Nu3BzwwxafDMOYO4oPZ+fYXu2z NrQcFDWE/h7lqK0SziqRCNIMC/fK63+hb23dyRdYpYEXrJx1J20HD/DRSKFIZwknwpXo yYQMwh4c78nzqchl3/M3wRAUk/DrpwrX/6xl4YMtLewdM9mNVo9UXfIwUlcfhRVtPea+ PXWMQu8yi0m/EsRHSBEMIs69m5nLs6MJX5bEkqNkYcr93PXmdKptTCjqtGGTWRdSeIKI lVDLqIGxpgAY9RegrfqVICbMprGsdasNIhBTZNxmhnmkHeeXf5xaV0yVTv/lgugSrjrs G8uw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ei8XRNFE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c0b79e097sm11895081f8f.80.2025.03.31.12.49.12 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 31 Mar 2025 12:49:12 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Heinrich Schuchardt , qemu-stable@nongnu.org, Frederik Du Toit Lotter , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 10/23] hw/rtc/goldfish: keep time offset when resetting Date: Mon, 31 Mar 2025 21:48:08 +0200 Message-ID: <20250331194822.77309-11-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250331194822.77309-1-philmd@linaro.org> References: <20250331194822.77309-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Heinrich Schuchardt Currently resetting the leads to resynchronizing the Goldfish RTC with the system clock of the host. In real hardware an RTC reset would not change the wall time. Other RTCs like pl031 do not show this behavior. Move the synchronization of the RTC with the system clock to the instance realization. Cc: qemu-stable@nongnu.org Reported-by: Frederik Du Toit Lotter Fixes: 9a5b40b8427 ("hw: rtc: Add Goldfish RTC device") Signed-off-by: Heinrich Schuchardt Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20250321221248.17764-1-heinrich.schuchardt@canonical.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/rtc/goldfish_rtc.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/hw/rtc/goldfish_rtc.c b/hw/rtc/goldfish_rtc.c index 0f1b53e0e4d..d83cc264814 100644 --- a/hw/rtc/goldfish_rtc.c +++ b/hw/rtc/goldfish_rtc.c @@ -239,15 +239,8 @@ static const VMStateDescription goldfish_rtc_vmstate = { static void goldfish_rtc_reset(DeviceState *dev) { GoldfishRTCState *s = GOLDFISH_RTC(dev); - struct tm tm; timer_del(s->timer); - - qemu_get_timedate(&tm, 0); - s->tick_offset = mktimegm(&tm); - s->tick_offset *= NANOSECONDS_PER_SECOND; - s->tick_offset -= qemu_clock_get_ns(rtc_clock); - s->tick_offset_vmstate = 0; s->alarm_next = 0; s->alarm_running = 0; s->irq_pending = 0; @@ -258,6 +251,7 @@ static void goldfish_rtc_realize(DeviceState *d, Error **errp) { SysBusDevice *dev = SYS_BUS_DEVICE(d); GoldfishRTCState *s = GOLDFISH_RTC(d); + struct tm tm; memory_region_init_io(&s->iomem, OBJECT(s), &goldfish_rtc_ops[s->big_endian], s, @@ -267,6 +261,11 @@ static void goldfish_rtc_realize(DeviceState *d, Error **errp) sysbus_init_irq(dev, &s->irq); s->timer = timer_new_ns(rtc_clock, goldfish_rtc_interrupt, s); + + qemu_get_timedate(&tm, 0); + s->tick_offset = mktimegm(&tm); + s->tick_offset *= NANOSECONDS_PER_SECOND; + s->tick_offset -= qemu_clock_get_ns(rtc_clock); } static const Property goldfish_rtc_properties[] = { From patchwork Mon Mar 31 19:48:09 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877306 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp1924487wrs; Mon, 31 Mar 2025 12:50:11 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUVKmS+NA76jkg2MxdXC5J4PwRN3bXPJsInrj0/eI/H/4BVlIXVAkfi3q2Mf2UvOB9Cv0HPFw==@linaro.org X-Google-Smtp-Source: AGHT+IGz8Oq5icb3cqtI74gl8Ref7S8qXpqbcuqJ5kSyA8EjY0+KgjzWnJFrlxrOv08Yb7N7DgAy X-Received: by 2002:a05:6214:21cb:b0:6e8:86d3:be73 with SMTP id 6a1803df08f44-6eed62b3586mr202729826d6.37.1743450611686; Mon, 31 Mar 2025 12:50:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743450611; cv=none; d=google.com; s=arc-20240605; b=UZOxPRQ/gn8NueB9loWg+M7Nd45bEgmTE8Pbw8yHbO9BJDGQcb5XzJLD9KXDzVHp3i AA7MT7OoNBnuYtm/0mcrKIJ732fRNX3JKk50ooUdaAdi9+rNejoinz3funvimQ/4Cxsi dWMGAL34fk/9knd+13LeRw2UfTWFbm5feGJwc4ZLhfXcQ4RoR/YD2NAdE2Pt7A0GqHam l/B3tzogS+m0hLS2zm9dmdmuKQmNkBUHHbWQuT694CQzmwUyXR5LMT63VIqtza/5+kCP 8nySW2is/OcothqukYRXurXTLIFTivNBtOVC+02F3NGMzIVlVWL8lqfueGxh6V5dyQLu xa0A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=j17i4NSW+jisbn3eQFtLedISxNwsl/F0+zMCrogQ6BQ=; fh=7gZvlf5c4KqY17UefY3VLfTm+bVDxskXHVg/jnbpAaM=; b=d6ODIe/6iT7YbkA0nwKhbdqgtSlYIVPpJhQVS9vMgYiCIlQlT3HFGc9houTF6F2Z+q RKRaHiam58BDRaKk1RKyqnmTJQpF5PsiowTPKwwRDTSnaHkQdWOmfLrJj1DXIHONNXC/ TdfvJKzO3eeMJXzwrW8RZRikjy9jCrE3GVUDvDHKiZCpOme0W2uwreCz05FTYcnaLXmL F5efStYT54nKK487W57/HHK2v6XUClazdhg8J/6cOKbpkyraAypYmqmeUe/5ITyfw9yo X7ynXTwUA5ilExFLQKs0HRPGIpBVwt33VP5hNCLz43XggMAjiRJQxZTj1snSOnzoDrL1 nRLA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AbjQKg4I; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Message-Id: <20250325224310.8785-9-philmd@linaro.org> --- hw/misc/bcm2835_cprman.c | 8 ++++++++ hw/misc/npcm_clk.c | 6 ++++++ hw/misc/stm32l4x5_rcc.c | 4 ++++ 3 files changed, 18 insertions(+) diff --git a/hw/misc/bcm2835_cprman.c b/hw/misc/bcm2835_cprman.c index aa14cd931f5..0c4d4b7de50 100644 --- a/hw/misc/bcm2835_cprman.c +++ b/hw/misc/bcm2835_cprman.c @@ -137,6 +137,8 @@ static void pll_class_init(ObjectClass *klass, void *data) device_class_set_legacy_reset(dc, pll_reset); dc->vmsd = &pll_vmstate; + /* Reason: Part of BCM2835CprmanState component */ + dc->user_creatable = false; } static const TypeInfo cprman_pll_info = { @@ -241,6 +243,8 @@ static void pll_channel_class_init(ObjectClass *klass, void *data) device_class_set_legacy_reset(dc, pll_channel_reset); dc->vmsd = &pll_channel_vmstate; + /* Reason: Part of BCM2835CprmanState component */ + dc->user_creatable = false; } static const TypeInfo cprman_pll_channel_info = { @@ -362,6 +366,8 @@ static void clock_mux_class_init(ObjectClass *klass, void *data) device_class_set_legacy_reset(dc, clock_mux_reset); dc->vmsd = &clock_mux_vmstate; + /* Reason: Part of BCM2835CprmanState component */ + dc->user_creatable = false; } static const TypeInfo cprman_clock_mux_info = { @@ -416,6 +422,8 @@ static void dsi0hsck_mux_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); dc->vmsd = &dsi0hsck_mux_vmstate; + /* Reason: Part of BCM2835CprmanState component */ + dc->user_creatable = false; } static const TypeInfo cprman_dsi0hsck_mux_info = { diff --git a/hw/misc/npcm_clk.c b/hw/misc/npcm_clk.c index 0e85974cf96..b6a893ffb22 100644 --- a/hw/misc/npcm_clk.c +++ b/hw/misc/npcm_clk.c @@ -1108,6 +1108,8 @@ static void npcm7xx_clk_pll_class_init(ObjectClass *klass, void *data) dc->desc = "NPCM7xx Clock PLL Module"; dc->vmsd = &vmstate_npcm7xx_clk_pll; + /* Reason: Part of NPCMCLKState component */ + dc->user_creatable = false; } static void npcm7xx_clk_sel_class_init(ObjectClass *klass, void *data) @@ -1116,6 +1118,8 @@ static void npcm7xx_clk_sel_class_init(ObjectClass *klass, void *data) dc->desc = "NPCM7xx Clock SEL Module"; dc->vmsd = &vmstate_npcm7xx_clk_sel; + /* Reason: Part of NPCMCLKState component */ + dc->user_creatable = false; } static void npcm7xx_clk_divider_class_init(ObjectClass *klass, void *data) @@ -1124,6 +1128,8 @@ static void npcm7xx_clk_divider_class_init(ObjectClass *klass, void *data) dc->desc = "NPCM7xx Clock Divider Module"; dc->vmsd = &vmstate_npcm7xx_clk_divider; + /* Reason: Part of NPCMCLKState component */ + dc->user_creatable = false; } static void npcm_clk_class_init(ObjectClass *klass, void *data) diff --git a/hw/misc/stm32l4x5_rcc.c b/hw/misc/stm32l4x5_rcc.c index fd8466dff34..158b743cae7 100644 --- a/hw/misc/stm32l4x5_rcc.c +++ b/hw/misc/stm32l4x5_rcc.c @@ -150,6 +150,8 @@ static void clock_mux_class_init(ObjectClass *klass, void *data) rc->phases.hold = clock_mux_reset_hold; rc->phases.exit = clock_mux_reset_exit; dc->vmsd = &clock_mux_vmstate; + /* Reason: Part of Stm32l4x5RccState component */ + dc->user_creatable = false; } static void clock_mux_set_enable(RccClockMuxState *mux, bool enabled) @@ -302,6 +304,8 @@ static void pll_class_init(ObjectClass *klass, void *data) rc->phases.hold = pll_reset_hold; rc->phases.exit = pll_reset_exit; dc->vmsd = &pll_vmstate; + /* Reason: Part of Stm32l4x5RccState component */ + dc->user_creatable = false; } static void pll_set_vco_multiplier(RccPllState *pll, uint32_t vco_multiplier) From patchwork Mon Mar 31 19:48:10 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877324 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp1925786wrs; Mon, 31 Mar 2025 12:54:31 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCV1eU95vN1l0JCpl1WKM4Mcv7pJtA7uotqIa+gndY4ymlE6KUsJhRvMZUBv9jRriUdzBz9ZwQ==@linaro.org X-Google-Smtp-Source: AGHT+IEtkOKGoKdgrI8a4J5dWiAPNzHP/LzpMTF0OeVYhVr4dQmngyfYs7cD3vAQiKwB3pq1kM3Y X-Received: by 2002:ac8:5a8c:0:b0:477:e17:6b01 with SMTP id d75a77b69052e-477ed76d819mr170695701cf.43.1743450870820; Mon, 31 Mar 2025 12:54:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743450870; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d8fba4c29sm136189505e9.5.2025.03.31.12.49.21 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 31 Mar 2025 12:49:22 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Thomas Huth Subject: [PULL 12/23] hw/nvram/xlnx-efuse: Do not expose as user-creatable Date: Mon, 31 Mar 2025 21:48:10 +0200 Message-ID: <20250331194822.77309-13-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250331194822.77309-1-philmd@linaro.org> References: <20250331194822.77309-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This device is part of SoC components thus can not be created manually. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Message-Id: <20250325224310.8785-10-philmd@linaro.org> --- hw/nvram/xlnx-efuse.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/nvram/xlnx-efuse.c b/hw/nvram/xlnx-efuse.c index 29e7dd539ec..176e88fcd17 100644 --- a/hw/nvram/xlnx-efuse.c +++ b/hw/nvram/xlnx-efuse.c @@ -280,6 +280,8 @@ static void efuse_class_init(ObjectClass *klass, void *data) dc->realize = efuse_realize; device_class_set_props(dc, efuse_properties); + /* Reason: Part of Xilinx SoC */ + dc->user_creatable = false; } static const TypeInfo efuse_info = { From patchwork Mon Mar 31 19:48:11 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877326 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp1925943wrs; Mon, 31 Mar 2025 12:55:02 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUwcb1l2/p/9H1IVrcKRAwmj9e7IpOFsGRozww9uAnfLpVKVpTFwINpI26nDZc7CJrRHvkftg==@linaro.org X-Google-Smtp-Source: AGHT+IF3J3Ll5WKvtkgei+qRoUCvaHp85hSej7MjIDUaim+sxVmT4xvd00qVBPLDBtso9378cHhx X-Received: by 2002:a05:622a:3d1:b0:474:f9f2:ecb with SMTP id d75a77b69052e-477b3b2e63bmr157405051cf.18.1743450902525; Mon, 31 Mar 2025 12:55:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743450902; cv=none; d=google.com; s=arc-20240605; b=VGkb2VnJVDyFqYEpTtetMvQHFk+9IFG5PciszVdD9kKNx4rLSZfPc3EkByzMIUVjUa gEzSrKSUPd6EShrKFxx2/KIryFdp8ZqCmuP8eLPr+BSLqhHMNt9ADQaaZfD6p0yG0g0f fdvgbnO9s8nlJ+v46BNPAp/36slk6XI+zzqF1WZpttnFaKDbJwwhQ0SQZTY8q+vFs+y9 7wseGcR0w0LUgX6AzMEzq80JCatrh9igxkGGZnhXdB25Z+bKtjVqNO/IOzV3DVTrYbV0 upkJ2SgLk3Y5yzsYndWlEwomUBDSv/tePKGOFJ6GYE9l+lbsF6KqmFV6bybPNzYBmp9u p9Pg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=RLKl/DQ934NXDgHaUVfID1TPnM6HcvqoUZCXZk9DXsw=; fh=zcm/1bqbrGHO6NKP0tsyG5WZy2lDY0265psB6xmkf9c=; b=Ne/8gckhs4NvgPKJoUNOma9+lG3g1Z+iUKAIgewLrRGThuRBKV6ngELgdwzfzvcGKW 1A2L5HaXC2eZaIGimi8bAUPmwd3a+fBFeYTSA+9l+0DxGQ6gPDWLt2PZRR1+Ud5bxP8k iaIIgaMkdENC+LHxzuMx2g0JQnDUfxcUZqONlXa2XTrIxoMtxMTGSvhQU4ooGKX0/O4m tFYzpxJB/A+Iln/KaOfjYsp1uVDXPu9GyjpaK/Ckgc+22JuqnyK5uG6ARS0QVG1YEptV hUw88+HyGbiLdNRACMFZwyZDTqzsAQhwp4tpc+NLnS+u1ZeiII+yQisbXKuuOSM4lcPW zN3A==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Lb2Dmhyc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d8fccfd9bsm132177175e9.20.2025.03.31.12.49.27 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 31 Mar 2025 12:49:28 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Zheng Huang , Zheng Huang , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PULL 13/23] hw/scsi/lsi53c895a: fix memory leak in lsi_scsi_realize() Date: Mon, 31 Mar 2025 21:48:11 +0200 Message-ID: <20250331194822.77309-14-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250331194822.77309-1-philmd@linaro.org> References: <20250331194822.77309-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Zheng Huang Address a memory leak bug in the usages of timer_del(). The issue arises from the incorrect use of the ambiguous timer API timer_del(), which does not free the timer object. The LeakSanitizer report this issue during fuzzing. The correct API timer_free() freed the timer object instead. ================================================================= ==2586273==ERROR: LeakSanitizer: detected memory leaks Direct leak of 48 byte(s) in 1 object(s) allocated from: #0 0x55f2afd89879 in calloc /llvm-project/compiler-rt/lib/asan/asan_malloc_linux.cpp:75:3 #1 0x7f443b93ac50 in g_malloc0 (/lib/x86_64-linux-gnu/libglib-2.0.so.0+0x5ec50) #2 0x55f2b053962e in timer_new include/qemu/timer.h:542:12 #3 0x55f2b0514771 in timer_new_us include/qemu/timer.h:582:12 #4 0x55f2b0514288 in lsi_scsi_realize hw/scsi/lsi53c895a.c:2350:24 #5 0x55f2b0452d26 in pci_qdev_realize hw/pci/pci.c:2174:9 Signed-off-by: Zheng Huang Reviewed-by: Philippe Mathieu-Daudé Message-ID: <73cd69f9-ff9b-4cd4-b8aa-265f9d6067b9@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/scsi/lsi53c895a.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/scsi/lsi53c895a.c b/hw/scsi/lsi53c895a.c index d85e384ad63..6689ebba25b 100644 --- a/hw/scsi/lsi53c895a.c +++ b/hw/scsi/lsi53c895a.c @@ -2372,7 +2372,7 @@ static void lsi_scsi_exit(PCIDevice *dev) LSIState *s = LSI53C895A(dev); address_space_destroy(&s->pci_io_as); - timer_del(s->scripts_timer); + timer_free(s->scripts_timer); } static void lsi_class_init(ObjectClass *klass, void *data) From patchwork Mon Mar 31 19:48:12 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877310 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp1924655wrs; Mon, 31 Mar 2025 12:50:46 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWbrFHPv5LztqnoRWlqpZ7EEA3T+xuLUoRRvsbgnxtaPxwFxoUTZq1wLo9Q6/JxoERWz0Ep4g==@linaro.org X-Google-Smtp-Source: AGHT+IH63IuJYVXlFyhrQKQ0N30pjDLP/TlhPra3DqWM4F99+z2Guvz5fiLPKKbHdY6Logfn9cI8 X-Received: by 2002:ad4:5cc4:0:b0:6ea:d033:2853 with SMTP id 6a1803df08f44-6eed5fbdb2emr201926336d6.16.1743450645936; Mon, 31 Mar 2025 12:50:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743450645; cv=none; d=google.com; s=arc-20240605; b=PZWeqNqdbp0Zpd7C8lrm3hs6YDgP/b8dJynkfrcW8etlopyA3TXjULuKD96G80bJkJ 9gkJHrOZkxFK16oJHvim9GZhDWiO6jvXU+hKSQyda1Ua+ylOhCyDKquxcjklJGwsTUy9 uDz1CDuuChBHDljzKJWfhW0YgKbfVUieDzLdI5zALN9/fjaxELEhO/hpHwrdfnZ7wqI5 zl8bjX1e+AAFc69s93UBNm7G6HBfONXi1QurZ+JUUwbZtuwB5VGTdp/owjghP8nS62AL pd6CGrOkQqfcuSHfzxCNKliDXLVEds1FPCl55+1+tgOLvZaP1kI9lL/Xr77f3NhWnqyv J+Tg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=QeP6jQz4X7+XY7FtN/BipVDSziqVvseYgaJ7e11b81k=; fh=Mr6c/jhUA2Q0gNGTec1GqUPc9FasSQuEMQM5wTAf3/4=; b=NeRGN6dhfnPaDR/MZ2RDXOIcXt0ntn0jjR95SCtgZNRlSeGTftRCm2GjiaQ02OJ7PE rkToHyCBrObY49yg8aaJ326t+Zl9LWJ/C1CdaVq6BDQcjLh5XdNb4owU1NXnNH7RkmLc 3pPVR4DUIGZ/b9tmMHCPREk05uJ4WVt1TbBWHjgFi8ErlZ2JmqZDf+5WEUng97WFrTSk 9CCFigO8F8w+u4HMFO3Flb6b0bYC2/u2pb7oUmjVFya1EHCJWLiuKZ3SRGGt0xn7k3+3 30zgrEBxahqy9PQLi+xO97wjfptCHPZUAzGwOM8nUDcbOyrFOJ6LzXEMYgnAmccFM2xa WZ5w==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xV5mj+FB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d82efdff2sm174620815e9.17.2025.03.31.12.49.32 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 31 Mar 2025 12:49:32 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Zheng Huang , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PULL 14/23] hw/sd/sdhci: free irq on exit Date: Mon, 31 Mar 2025 21:48:12 +0200 Message-ID: <20250331194822.77309-15-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250331194822.77309-1-philmd@linaro.org> References: <20250331194822.77309-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Zheng Huang Fix a memory leak bug in sdhci_pci_realize() due to s->irq not being freed in sdhci_pci_exit(). Signed-off-by: Zheng Huang Reviewed-by: Philippe Mathieu-Daudé Message-ID: <09ddf42b-a6db-42d5-954b-148d09d8d6cc@gmail.com> [PMD: Moved qemu_free_irq() call before sdhci_common_unrealize()] Signed-off-by: Philippe Mathieu-Daudé --- hw/sd/sdhci-pci.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/sd/sdhci-pci.c b/hw/sd/sdhci-pci.c index 5268c0dee50..bca149e8113 100644 --- a/hw/sd/sdhci-pci.c +++ b/hw/sd/sdhci-pci.c @@ -18,6 +18,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu/module.h" +#include "hw/irq.h" #include "hw/qdev-properties.h" #include "hw/sd/sdhci.h" #include "sdhci-internal.h" @@ -48,6 +49,7 @@ static void sdhci_pci_exit(PCIDevice *dev) { SDHCIState *s = PCI_SDHCI(dev); + qemu_free_irq(s->irq); sdhci_common_unrealize(s); sdhci_uninitfn(s); } From patchwork Mon Mar 31 19:48:13 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877321 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp1925626wrs; Mon, 31 Mar 2025 12:53:58 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUgFweUdVOQ2TvbbW6C9k2kr8IUYTahUgKn0OluM9fNwmST9FBQaa7u2AfgFWuGD6qzmedo2g==@linaro.org X-Google-Smtp-Source: AGHT+IFfgKGnwE/IawfF3R18iNHCELKg2e7kbtZNhBjG4tc/jN+giAne/NiZZDeq2dFtEBZVlXZK X-Received: by 2002:a05:622a:1a01:b0:475:39:9d35 with SMTP id d75a77b69052e-477ed725415mr170462681cf.14.1743450837870; Mon, 31 Mar 2025 12:53:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743450837; cv=none; d=google.com; s=arc-20240605; b=etcZWkCDFgvSmrY+5a4LihTX0TgExfScgi9cLCCdgbKTFNTwuKQu0y9BXP/idkixi9 Gt4HOHOvuzJwZm3R1WvDPjbg6AuaQANRPdO1u1JL22edtrvhyZ4eOJSXoMEPaaazK1dj KzM7n7VFWEqJYT6+QVnD7OqyDNyT4QKiL0A+JRJqIZK3JE5TqM6qRo3LqS2dTktPO+Eh hEmFSDojyJxutcxeGJE9KBRU4b6EvwpUQGcuTM5TXuzSJf8XB2bxQpjYTKUz3vwIdWgr SftjJKeFdslSMrURyio0BFazDWz/40lkIgDe1v+zrXFvIJv3Uo1dQCij5NMyB7QC0ymP Gv7A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=e7DpG1j0l2crn6m64hQcn/HA4bp5z0J1QxJNTGXkaR0=; fh=M7P9NUqbYSEXpavpopumMcTtmiNjnqUOLm3DLKliSfE=; b=huZYWcQFjNJZ1GVv5Yw5yH2VkmhicZKi70tQ4jVPsd9b0pqJh9lgrouCh9s6Ez72os 2tuSbOEH9UY8QYW5I3np8a3EvUtbr2lEXs2/wIdqKk0I+xujsJDtMsOC9O+mpkBgKHUB pdNW03KXfkeYgg7+Wl0vNnWtUGT1Zj3bHh81HReLP2yWIJ2h9jgXoexexl3MF8gYbq8O O3sYiLDd64UV5d10LXiam15A1JFUr9RZPbpOvNFRq3u7h5tN6iSTZvqr1vYBCRyKbpQE 0+hWue7dAGP7Fz0MxuL4JwUFtpwN+oXBaPZBTVZH1VKhBl2ejz+XZAUTJrHVWd2tTKXn E2Dg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zlZWvxTq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c0b663860sm12251119f8f.39.2025.03.31.12.49.37 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 31 Mar 2025 12:49:37 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Chung-Yi Chen , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PULL 15/23] hw/char/bcm2835_aux: Fix incorrect interrupt ID when RX disabled Date: Mon, 31 Mar 2025 21:48:13 +0200 Message-ID: <20250331194822.77309-16-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250331194822.77309-1-philmd@linaro.org> References: <20250331194822.77309-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philmd@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Chung-Yi Chen Fix a misconfiguration issue in the read implementation of the AUX_MU_IIR_REG register. This issue can lead to a transmit interrupt being incorrectly interpreted as a receive interrupt when the receive interrupt is disabled and the receive FIFO holds valid bytes. The AUX_MU_IIR_REG register (interrupt ID bits [2:1]) indicates the status of mini UART interrupts: - 00: No interrupts - 01: Transmit FIFO is empty - 10: Receive FIFO is not empty - 11: When the transmit interrupt is enabled and the receive interrupt is disabled, the original code incorrectly sets the interrupt ID bits. Specifically: 1. Transmit FIFO empty, receive FIFO empty - Expected 0b01, returned 0b01 (correct) 2. Transmit FIFO empty, receive FIFO not empty - Expected 0b01, returned 0b10 (incorrect) In the second case, the code sets the interrupt ID to 0b10 (receive FIFO is not empty) even if the receive interrupt is disabled. To fix this, the patch adds additional condition for setting the interrupt ID bits to also check if the receive interrupt is enabled. Reference: BCM2835 ARM Peripherals, page 13. Available on https://datasheets.raspberrypi.com/bcm2835/bcm2835-peripherals.pdf Fixes: 97398d900ca ("bcm2835_aux: add emulation of BCM2835 AUX (aka UART1) block") Signed-off-by: Chung-Yi Chen Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20250328123725.94176-1-yeechen0207@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/char/bcm2835_aux.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/char/bcm2835_aux.c b/hw/char/bcm2835_aux.c index c6e7eccf7dd..9b073fc3308 100644 --- a/hw/char/bcm2835_aux.c +++ b/hw/char/bcm2835_aux.c @@ -98,7 +98,7 @@ static uint64_t bcm2835_aux_read(void *opaque, hwaddr offset, unsigned size) * interrupts are active, besides that this cannot occur. At * present, we choose to prioritise the rx interrupt, since * the tx fifo is always empty. */ - if (s->read_count != 0) { + if ((s->iir & RX_INT) && s->read_count != 0) { res |= 0x4; } else { res |= 0x2; From patchwork Mon Mar 31 19:48:14 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877320 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp1925417wrs; Mon, 31 Mar 2025 12:53:19 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVVGkoEbmRdXdmGOZbCpF/aX07oIxCXIxowb8S1jqp3m57QNAxT1iWIYPK3nOPMytS/dDUdTg==@linaro.org X-Google-Smtp-Source: AGHT+IG5YWyu8O/Vu2Q7ZLJgh+78C0Zyy1yOwucH91x4ViR6ztaRMSw6c/zGu4QlYs0j5GlW9BBk X-Received: by 2002:a05:6214:c42:b0:6ea:d69c:a247 with SMTP id 6a1803df08f44-6eed5f50084mr167444986d6.4.1743450798890; Mon, 31 Mar 2025 12:53:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743450798; cv=none; d=google.com; s=arc-20240605; b=QZr78R7XNGVW5zp9gbXaW0B6dT4lOV/Hh3Y5HOdLgumDBCA0h6rayJT01SA364iaTl mMVSwoBLN6s9+IN79RLKopu71t6/5eRfd2btfHS5qz2d5NARkeVpXNgWXij+XcrTGqr2 BhScYaUgMIAe7kaC1GMa5CVR06flH7DhlQxFVpiY9/9AHPvJU1AKFPJzCTKCFQStNvvi CciVmtBCI2NG2slkKkL344YrDuXQjBWwI7Fq5tnMGkK8sTQJjINs5LrAis/5OzoEtj8/ lwkXGWcJgAuUnr4VV1amhKlYWHNHgIiuYa93TwyAY0sdEsU3FaG3zYGNiwB874J90tbP ibFA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=5/jd9HigZUkvZ9mYhgB2s1hOlVQphymlZOIUStujzjg=; fh=Mr6c/jhUA2Q0gNGTec1GqUPc9FasSQuEMQM5wTAf3/4=; b=CFzBhKzkBENG5bVI+Nno99Px/8DZerhIQC3TIWKTXKkRnV/18SZgCbrwzzVQK6Kypg 6lBppfcwcHXyF6NE29urToYcgskXlAxHtEfTCLl6tbaxDrguStK78zlrJOHmUlw1+9Dy qWGQp5kqeqZH5TiEsdYN6okSeKlpQobjDrr4STaRIcBoO6QkDiUfmo+OC35OmooNcKHH ZQHmgJtpe45GpyrYAk24DZRpHnA5kO+MGOQvVZZI/3YRBlqYPFy4FeKZ2u8Ydy9X95kN zFAS/+MVDgkBnaF17runWvl0GuYE2zo6+/Q8Usk7NYsqxU5hj1InPQFzipNf4p79/bqa njNg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vjBGSYea; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d830f59d0sm173771505e9.28.2025.03.31.12.49.41 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 31 Mar 2025 12:49:42 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Zheng Huang , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PULL 16/23] hw/ufs: free irq on exit Date: Mon, 31 Mar 2025 21:48:14 +0200 Message-ID: <20250331194822.77309-17-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250331194822.77309-1-philmd@linaro.org> References: <20250331194822.77309-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Zheng Huang Fix a memory leak bug in ufs_init_pci() due to u->irq not being freed in ufs_exit(). Signed-off-by: Zheng Huang Reviewed-by: Philippe Mathieu-Daudé Message-ID: <43ceb427-87aa-44ee-9007-dbaecc499bba@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/ufs/ufs.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/ufs/ufs.c b/hw/ufs/ufs.c index 857de6e9c2c..ee13edacd8f 100644 --- a/hw/ufs/ufs.c +++ b/hw/ufs/ufs.c @@ -25,6 +25,7 @@ #include "qapi/error.h" #include "migration/vmstate.h" #include "scsi/constants.h" +#include "hw/irq.h" #include "trace.h" #include "ufs.h" @@ -1808,6 +1809,8 @@ static void ufs_exit(PCIDevice *pci_dev) { UfsHc *u = UFS(pci_dev); + qemu_free_irq(u->irq); + qemu_bh_delete(u->doorbell_bh); qemu_bh_delete(u->complete_bh); From patchwork Mon Mar 31 19:48:15 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877318 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp1925261wrs; Mon, 31 Mar 2025 12:52:49 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCW5Abb2Q+0MAqBk+E0A1TdQ/aUxWx1ByfAjjcqqo8VVibytTUGAvAcZpKxydH1mpO2Nq7dVBA==@linaro.org X-Google-Smtp-Source: AGHT+IGzsDQXHYPM5ACoaJHr9VP1IzzY31Cfem1e+mGphVX41jq6Yww+ZY+aGXfXvRCFELWhkSuy X-Received: by 2002:ad4:5be1:0:b0:6ed:18cd:956d with SMTP id 6a1803df08f44-6eed52ae2e3mr134272106d6.22.1743450769509; Mon, 31 Mar 2025 12:52:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743450769; cv=none; d=google.com; s=arc-20240605; b=S9DpbH0dv+LMc1aJbHkb3zFx/8y+JM8BQqsPeGkuQ8tALTZfdeXtjOKL10QFKRXo0h WmJOm2wVPQMbAOVUyYTd4LU061RYjMssNyQ3GjwmdjaoJTT8IU8p7U/JUeq2aLxGkgk8 ZcVU54CCSieqn9BO1Zx9NPkrNg6okhkZI28wWAyZC3e4rIVKvBzHwfkeAfuQlb440tEe cBpEoSIRUCerR/IIyzD6Yq+7112MZPSVRR7ZdANyoad13EhprTyKx30kcAMBvY9Wi7SI uCoofxSqzqzZDarAKeen+GxbDSAsaQe+Plaxu1N+KAm5GQWNoDi5rZMGyiHBQEphLqs9 Efvg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=b1rAoFw8FyG6NwD6es9o9iWAe5ykbL1RM+kN37mtk4M=; fh=SFQJZlSNGrWndJs4/Lr+qm/IkbooSywCPRBGPoWMeYY=; b=i7ZuXsZIK+W27oAHzWO8CkouaQUZxSF00Qfqn+1Rptda91+KjNIUpj2lX273DTkbyi DJmnwx26l3MVPTdQB0EHA4KdddFF9O7bD7JhUnGsRPkIKd4ERUwd9xyI5t15yrczylLQ vpGHV7pogtCRDOsgROVXFeivqCzSrG83I/xDaqFBSotplCTNJk7djDatt3umcUtLM/IT 9LM5obPo2Alupitmr1/U/VnsIOZ7XSRTQg2wxyvxyhi+yys6BH/HYV3xBn+lmcklQiM6 ZhzyvuuJFsuQobNOS+cE+F6eHJTbdp2bE0hV6GdQTXmpaRrF86TaNS8O3AdfFlxPJm2/ Rxrg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hJ4u3E6u; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d8fbc10f7sm132920615e9.14.2025.03.31.12.49.46 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 31 Mar 2025 12:49:46 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , qemu-stable@nongnu.org, Joey , Gustavo Romero Subject: [PULL 17/23] hw/pci-host/designware: Fix ATU_UPPER_TARGET register access Date: Mon, 31 Mar 2025 21:48:15 +0200 Message-ID: <20250331194822.77309-18-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250331194822.77309-1-philmd@linaro.org> References: <20250331194822.77309-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Fix copy/paste error writing to the ATU_UPPER_TARGET register, we want to update the upper 32 bits. Cc: qemu-stable@nongnu.org Reported-by: Joey Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2861 Fixes: d64e5eabc4c ("pci: Add support for Designware IP block") Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Gustavo Romero Message-Id: <20250331152041.74533-2-philmd@linaro.org> --- hw/pci-host/designware.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c index c07740bfaa4..5598d18f478 100644 --- a/hw/pci-host/designware.c +++ b/hw/pci-host/designware.c @@ -371,7 +371,7 @@ static void designware_pcie_root_config_write(PCIDevice *d, uint32_t address, case DESIGNWARE_PCIE_ATU_UPPER_TARGET: viewport->target &= 0x00000000FFFFFFFFULL; - viewport->target |= val; + viewport->target |= (uint64_t)val << 32; break; case DESIGNWARE_PCIE_ATU_LIMIT: From patchwork Mon Mar 31 19:48:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877319 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp1925304wrs; Mon, 31 Mar 2025 12:52:56 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXVcNjNptPx1l6DniRJaaJpWwNgKPQKO48fkP9SqCms2x1s0ObvoHZ/zGjVzpGcM531K6YQag==@linaro.org X-Google-Smtp-Source: AGHT+IGAb4P5M8idXQDtR1TPlSgiVOwUfap/i+KfV5knBWQ4Wgl+ek8bA7dCGwywhXqeLd/OvWrU X-Received: by 2002:a05:622a:493:b0:476:6a3d:de2e with SMTP id d75a77b69052e-477e4b1f5cemr174772141cf.14.1743450776385; Mon, 31 Mar 2025 12:52:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743450776; cv=none; d=google.com; s=arc-20240605; b=RKxJeBAFG+wHlD09dpEhAnQgF0m0cKlcZuNUreZfWDLOm/IfvjxHwCIGWJNTobTzgp 9TLP79BVxoSeKmLo4/NbofnXTFDINoTTLHgo7joFBYqugBeXL3hypjzmMPthaJJPLjNn JjzaW+41D8fOmkWgb9Gouec4KiM58x3/KJsHTYmOCUi98zjvfQXXZBpGMIIUmZg7F58G yHsyxtCY9tT/5wMv2paoHWdiTSNbzoB8Yio90MJjBTkdvmUhOnjhcafe1SJEFXCFWZ7i r+B7wMiv37KEM2pHUddcIfOu1VWXSXk8U78XSkGe3QHTZ8lgECcS+qxGxZesUlsbwJ6K nQjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=edC8SjUvZyJ+hQNsoUTkUYXPs+9FX/UDXWtKI6uhvY4=; fh=qtn8prgQtzf5IzCNvLChUZDElvNECP6ej9YfjQeBz3I=; b=Uzf0YjUh62xAwNnlGGAuB6qOLiy55aVklqqQjnvkzfnSbYZM6q4i97U36M/6aHR2i3 p0kpX8FLjl/nkzXOYrfs6s2cHkpGODxMnzjQDeInlxqCMtAauo/KjSeI2lMh1OPdmOme 5CkgThHnuC/V4QHWsrGGNzufiam3iRHNLGiHnSA7OrSCUFK7I+2pLxcPcCwPCuVeuEi3 vbGtzyJanKiO2biRonie8nfjnu9V1iay4oA9vjg1rlsrclOL5XgyW+t5Mzzr9JI65jjz 39CQkMCNI/kYgKKzK+tER6O6063KvH7QDbem7ghhtwHUX1sgCcw4etWTEVwtsQnAiAgp U4fg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Djqi1Tsi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c0b6589e4sm12269140f8f.10.2025.03.31.12.49.52 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 31 Mar 2025 12:49:52 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 18/23] target/hppa: Remove duplicated CPU_RESOLVING_TYPE definition Date: Mon, 31 Mar 2025 21:48:16 +0200 Message-ID: <20250331194822.77309-19-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250331194822.77309-1-philmd@linaro.org> References: <20250331194822.77309-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The CPU_RESOLVING_TYPE definition was added in commit 0dacec874fa ("cpu: add CPU_RESOLVING_TYPE macro"), but then added again in commit d3ae32d4d20. Remove the duplication. Fixes: d3ae32d4d20 ("target/hppa: Implement cpu_list") Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250321184200.4329-1-philmd@linaro.org> --- target/hppa/cpu.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 7be4a1d3800..8b36642b591 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -391,6 +391,4 @@ void hppa_cpu_alarm_timer(void *); #endif G_NORETURN void hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t ra); -#define CPU_RESOLVING_TYPE TYPE_HPPA_CPU - #endif /* HPPA_CPU_H */ From patchwork Mon Mar 31 19:48:17 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877315 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp1925151wrs; Mon, 31 Mar 2025 12:52:22 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVz+LMLv0BDjosZM+IaRtvl8Feo0ScSM4fIupXwCK6UB07M3CMlT7W5RcI6iRoglH7DKzbCag==@linaro.org X-Google-Smtp-Source: AGHT+IHGRZmxvvlKm570ow5B4j0nGB28U6wns9tFoBBrFJbjf1mrZCC80dNjrGL9WeMskzLBw15O X-Received: by 2002:a05:6214:246a:b0:6ec:f76f:64fa with SMTP id 6a1803df08f44-6eed62b2fafmr151616126d6.44.1743450742463; Mon, 31 Mar 2025 12:52:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743450742; cv=none; d=google.com; s=arc-20240605; b=d5S/npVXFgLXJXlRFqJTT2kDFj6RuZC87J7kpEfPQOuvmf2yr3QfKtWtEb8YB5MFVS ViIJblFCadeOHYW/isPoRc8Dv4aAQUS9s7nuSq6gED6d7XwZ9jaL24o8UgvpC2aR2CiI h6WBeIYKoF5GS/bXqUtBvSAR9xVAw/BoLIkFiV3CetTAUQCQrxt2Qw7G3fiTiH9AO9CZ hLeJ4BOmotGhtD1leknNMC60hwNOG7QZUv36i5G/LjtDScoiRCCN9r+Y80aYC6wDf3CY J17XW2/r984nvaZXBjAyXTAOSHGSyDJRfzZh7uqTJ/5lAb3VzxriZJWZEAsmN5W799US hq6w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=uHP3dfOw1csrD92NzXd1LjCikF/T0hdIj+cLpHi1vWc=; fh=A391M27ZpOOOjOEZUcfhOCTum1WDSzuONptj5OeBBHQ=; b=bFUFnuoR8TVIP5ZH8TnRu3+EEtw0Vpvz9eSULa4j8NqlUwuAfX+v6niRndjXSpGXSy BSXQFftNzLQjwFnqUOMYfw+P7yLWxjQAIpfRysHjvFsrKLw1ahAmEz11a9MWjKWt9pip AU4xxIoaCpZHT9rtfIGD/St9PESEJ7QaIyhLtAWNHMXK+eotOadv5sIp4e/Nb7+Gjbz8 7y+bUWOd4JG0W51Q+ogxuqL9/QNezhEIE255TP+DyE+Ae9W0VAFiaL+DhiKf9vr2gdJF IOooTUguFGX1F+A0os14n4MPq6rwZnLBsaVhqf6Hik8+uRgAq2aazv6x4FlaXZ8kI+Ii /8Sw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ihDOYyvF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d8314bbf1sm172587425e9.38.2025.03.31.12.49.56 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 31 Mar 2025 12:49:57 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , qemu-stable@nongnu.org, Pierrick Bouvier , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?q?Daud=C3=A9?= Subject: [PULL 19/23] target/avr: Fix buffer read in avr_print_insn Date: Mon, 31 Mar 2025 21:48:17 +0200 Message-ID: <20250331194822.77309-20-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250331194822.77309-1-philmd@linaro.org> References: <20250331194822.77309-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=philmd@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Do not unconditionally attempt to read 4 bytes, as there may only be 2 bytes remaining in the translator cache. Cc: qemu-stable@nongnu.org Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20250325224403.4011975-2-richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé --- target/avr/disas.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/target/avr/disas.c b/target/avr/disas.c index b7689e8d7cd..d341030174f 100644 --- a/target/avr/disas.c +++ b/target/avr/disas.c @@ -68,28 +68,35 @@ static bool decode_insn(DisasContext *ctx, uint16_t insn); int avr_print_insn(bfd_vma addr, disassemble_info *info) { - DisasContext ctx; + DisasContext ctx = { info }; DisasContext *pctx = &ctx; bfd_byte buffer[4]; uint16_t insn; int status; - ctx.info = info; - - status = info->read_memory_func(addr, buffer, 4, info); + status = info->read_memory_func(addr, buffer, 2, info); if (status != 0) { info->memory_error_func(status, addr, info); return -1; } insn = bfd_getl16(buffer); - ctx.next_word = bfd_getl16(buffer + 2); - ctx.next_word_used = false; + + status = info->read_memory_func(addr + 2, buffer + 2, 2, info); + if (status == 0) { + ctx.next_word = bfd_getl16(buffer + 2); + } if (!decode_insn(&ctx, insn)) { output(".db", "0x%02x, 0x%02x", buffer[0], buffer[1]); } - return ctx.next_word_used ? 4 : 2; + if (!ctx.next_word_used) { + return 2; + } else if (status == 0) { + return 4; + } + info->memory_error_func(status, addr + 2, info); + return -1; } From patchwork Mon Mar 31 19:48:18 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877316 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp1925205wrs; Mon, 31 Mar 2025 12:52:35 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVrbZB6TUZnHp8chlOMs+iteyDpTy3VWxG3L/GFaO8TtLbEeo9+u/xxIEb4AblmMV4IlxhuyQ==@linaro.org X-Google-Smtp-Source: AGHT+IHkjSE0Rj1R4/Kk50fc3lmUlsX5V18q3fQb0zvGL10VzBGyjvoaR9mrWuku8ox6xQxyAXk9 X-Received: by 2002:ac8:7f4e:0:b0:476:91f1:9de with SMTP id d75a77b69052e-477ed779a95mr152013571cf.47.1743450755499; Mon, 31 Mar 2025 12:52:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743450755; cv=none; d=google.com; s=arc-20240605; b=isAxnwht7szi8PzgQb+AWTiTd+WiQVYVn41X44xPLTQr/o3OAKGfA6dMlt/1433B39 ChP93i2/BzPEFR9QsyGaLS+Sd0p/Q00KIZuDSeNVkT6+IXxIVRO+z1rKag4SxXjh33IM XhH3L/E/Uu9g4pexumY8rlAGZzETtorR9Mz1a12tQ/EdgWEFF5RRoElmjVvC68ohkY3q P84jbB/KJ9imzgqUQb7Z2r24g+ILiCuxNem2yLzB9twT5DFfaIYqssU4emjf9JdpA8Fb EjPIcRva7UaooWC5DRSNgIiTCM3Fp7AMgaA4buCp/0WwcjwR3QhZj+ePGUQE0a6seViN 9ulg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=p5ZHjqmLDaEsy6AfHhvBBwdmYQrv+nX9DlxuV6Wd4ws=; fh=9mf0vysE9zakV+W0G6dN6dP2REB1+nKjFcuNzcYicC4=; b=j8My7aLTmU40yVwZraz2NDb3VLT0SEZMiW4Cdsq2d3kNLjcxKJJowvMLNZ8s+e01un HnpEeSFN2PIIW+MlaOfNwhmncKLWE9p7yuj1MiZ9IWkTRhsSmA/n9TSBV3avvYinJY0s sCYdX57eQJvdS+6a6dqebjTqlFIUg1ZpG4y4SSCVgjKrm6YFdTcfMqpRHr8RLklv9wwH mqEsCvk/kPEG/HaH5PDDAtjOsMAZz2sZjISl/WMLytJc/1TGB7N6gifsBYs/Q/903p6D ekcBzRbC2sCdO5OQOFioaHV020DTYCrjev4c6O8PNMFGNWaUcILdH5CY5w7IakAouPVi B2lQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CrKa71OC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d8314f5c6sm179823485e9.40.2025.03.31.12.50.02 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 31 Mar 2025 12:50:03 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?C?= =?utf-8?q?l=C3=A9ment_Chigot?= Subject: [PULL 20/23] target/sparc: Log unimplemented ASI load/store accesses Date: Mon, 31 Mar 2025 21:48:18 +0200 Message-ID: <20250331194822.77309-21-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250331194822.77309-1-philmd@linaro.org> References: <20250331194822.77309-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When the cache-controller feature is not implemented, log potential ASI access as unimplemented. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Clément Chigot Message-Id: <20250325123927.74939-4-philmd@linaro.org> --- target/sparc/ldst_helper.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index b559afc9a94..45882e25db1 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -600,6 +600,9 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, case 0x0C: /* Leon3 Date Cache config */ if (env->def.features & CPU_FEATURE_CACHE_CTRL) { ret = leon3_cache_control_ld(env, addr, size); + } else { + qemu_log_mask(LOG_UNIMP, "0x" TARGET_FMT_lx ": unimplemented" + " address, size: %d\n", addr, size); } break; case 0x01c00a00: /* MXCC control register */ @@ -816,6 +819,9 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, case 0x0C: /* Leon3 Date Cache config */ if (env->def.features & CPU_FEATURE_CACHE_CTRL) { leon3_cache_control_st(env, addr, val, size); + } else { + qemu_log_mask(LOG_UNIMP, "0x" TARGET_FMT_lx ": unimplemented" + " address, size: %d\n", addr, size); } break; From patchwork Mon Mar 31 19:48:19 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877323 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp1925776wrs; Mon, 31 Mar 2025 12:54:29 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXMb7IMHsQ6W+73CEJ4uZS01mrk+sd2TRfmV1Kxw408sQ1eRFtbRac33vI6iW58NUF9YAqtmA==@linaro.org X-Google-Smtp-Source: AGHT+IFYwse363faSTMCpr1SIb0YatBJZa0pVlUIfYDIoxunEn5yqt3q4fEUx7cJ3mBZqfr+B7Ss X-Received: by 2002:a05:620a:4043:b0:7c5:4949:23ea with SMTP id af79cd13be357-7c6908cf495mr1391920285a.47.1743450869410; Mon, 31 Mar 2025 12:54:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743450869; cv=none; d=google.com; s=arc-20240605; b=dDnrrqCO9F2lxLmpEnJo3cb88u1I5+ySf+rwzpva5g+aTEyWpedKL7+2s+d/3yb7Fq TTDFLve+zvX9g6xkPgcnQeQqI5Jc9CO/RZfXU4hUZAqcQCH8yX+cveN35cfSzveSOKFc Buen9nPDG+VdfhMxFznozN1zBmuvnR0VpokgR8Pjnyv8GdeApWr2MVIdUUBUNTRGrBRt tgSjCvJm6LdMNRIq0yUQ2FVQ7CdLvO9uX+Vx4d9YgzRWT7yUv5R0BEQ+t3a6JK7NaAUA WQXYxuUqCrcfi5202HuBAn/A+TTSCTOf22/DUlVOIqwtNTWZ9y6SmTFM+o1nUnWwDh2Z Vcgg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=mW/LOTnTsMj5waRnbyiJBrlUqbYcaju/dZQD/CeCa/g=; fh=ZXDWg7hKG7Hj19AbRuutTLw+Zvn/B9RsGUUw/YagpFI=; b=SBBvj3962F98mel3fPGdD33opu7IPOBSkDJ08NsC3aITriJq8e4OGr8nlt0gu9ZeZt QgbKrDTmx0IFnI7NQV8XxHioUpE5KCfPB5wf/R8NI+QQGgE4BAr6PrQ9jWtOn8tA31NI XCYVzziJotcChnTx6N5vaeB1sXJygtKX+vjCxzp0XVkXf5jAC6UuvyKM0+ZzC1lZGKgd 6lNnXNo+ey0eZuq9p/Dt7KVjHruYnpWlz138IqdVJjZ6l7zCKqtEDmxY1nIe6em+rgiH qdbQAC4dGmuoPxmzjHS109MLHV4SZiM/8ESUYtXB1NIel5oGfCeh9xW1xKyhxGap0iYY pEqg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=clZSFJEr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c0b7a4239sm12269696f8f.94.2025.03.31.12.50.08 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 31 Mar 2025 12:50:09 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= Subject: [PULL 21/23] target/mips: Revert TARGET_PAGE_BITS_VARY Date: Mon, 31 Mar 2025 21:48:19 +0200 Message-ID: <20250331194822.77309-22-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250331194822.77309-1-philmd@linaro.org> References: <20250331194822.77309-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philmd@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Revert ee3863b9d41 and a08d60bc6c2b. The logic behind changing the system page size because of what the Loongson kernel "prefers" is flawed. In the Loongson-2E manual, section 5.5, it is clear that the cpu supports a 4k page size (along with many others). Similarly for the Loongson-3 series CPUs, the 4k page size is mentioned in the section 7.7 (PageMask Register). Therefore we must continue to support a 4k page size. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20250328175526.368121-2-richard.henderson@linaro.org> [PMD: Mention Loongson-3 series CPUs] Signed-off-by: Philippe Mathieu-Daudé --- target/mips/cpu-param.h | 5 ----- hw/mips/fuloong2e.c | 1 - hw/mips/loongson3_virt.c | 1 - target/mips/tcg/system/cp0_helper.c | 7 +------ target/mips/tcg/system/tlb_helper.c | 2 +- 5 files changed, 2 insertions(+), 14 deletions(-) diff --git a/target/mips/cpu-param.h b/target/mips/cpu-param.h index 11b3ac0ac63..8fcb1b4f5f2 100644 --- a/target/mips/cpu-param.h +++ b/target/mips/cpu-param.h @@ -18,12 +18,7 @@ # define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif #endif -#ifdef CONFIG_USER_ONLY #define TARGET_PAGE_BITS 12 -#else -#define TARGET_PAGE_BITS_VARY -#define TARGET_PAGE_BITS_MIN 12 -#endif #define TCG_GUEST_DEFAULT_MO (0) diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c index 646044e2749..2a8507b8b0a 100644 --- a/hw/mips/fuloong2e.c +++ b/hw/mips/fuloong2e.c @@ -334,7 +334,6 @@ static void mips_fuloong2e_machine_init(MachineClass *mc) mc->default_cpu_type = MIPS_CPU_TYPE_NAME("Loongson-2E"); mc->default_ram_size = 256 * MiB; mc->default_ram_id = "fuloong2e.ram"; - mc->minimum_page_bits = 14; machine_add_audiodev_property(mc); } diff --git a/hw/mips/loongson3_virt.c b/hw/mips/loongson3_virt.c index db1cc513147..1da20dccec4 100644 --- a/hw/mips/loongson3_virt.c +++ b/hw/mips/loongson3_virt.c @@ -677,7 +677,6 @@ static void loongson3v_machine_class_init(ObjectClass *oc, void *data) mc->max_cpus = LOONGSON_MAX_VCPUS; mc->default_ram_id = "loongson3.highram"; mc->default_ram_size = 1600 * MiB; - mc->minimum_page_bits = 14; mc->default_nic = "virtio-net-pci"; } diff --git a/target/mips/tcg/system/cp0_helper.c b/target/mips/tcg/system/cp0_helper.c index 01a07a169f6..8c2114c58a6 100644 --- a/target/mips/tcg/system/cp0_helper.c +++ b/target/mips/tcg/system/cp0_helper.c @@ -877,18 +877,13 @@ void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask) if ((mask >> maskbits) != 0) { goto invalid; } - /* We don't support VTLB entry smaller than target page */ - if ((maskbits + TARGET_PAGE_BITS_MIN) < TARGET_PAGE_BITS) { - goto invalid; - } env->CP0_PageMask = mask << CP0PM_MASK; return; invalid: /* When invalid, set to default target page size. */ - mask = (~TARGET_PAGE_MASK >> TARGET_PAGE_BITS_MIN); - env->CP0_PageMask = mask << CP0PM_MASK; + env->CP0_PageMask = 0; } void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1) diff --git a/target/mips/tcg/system/tlb_helper.c b/target/mips/tcg/system/tlb_helper.c index ca4d6b27bc9..123639fa18e 100644 --- a/target/mips/tcg/system/tlb_helper.c +++ b/target/mips/tcg/system/tlb_helper.c @@ -875,7 +875,7 @@ refill: break; } } - pw_pagemask = m >> TARGET_PAGE_BITS_MIN; + pw_pagemask = m >> TARGET_PAGE_BITS; update_pagemask(env, pw_pagemask << CP0PM_MASK, &pw_pagemask); pw_entryhi = (address & ~0x1fff) | (env->CP0_EntryHi & 0xFF); { From patchwork Mon Mar 31 19:48:20 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877312 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp1924698wrs; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c0b6656a0sm12170928f8f.37.2025.03.31.12.50.13 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 31 Mar 2025 12:50:14 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , qemu-stable@nongnu.org Subject: [PULL 22/23] target/mips: Require even maskbits in update_pagemask Date: Mon, 31 Mar 2025 21:48:20 +0200 Message-ID: <20250331194822.77309-23-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250331194822.77309-1-philmd@linaro.org> References: <20250331194822.77309-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson The number of bits set in PageMask must be even. Fixes: d40b55bc1b86 ("target/mips: Fix PageMask with variable page size") Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20250328175526.368121-3-richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé Cc: qemu-stable@nongnu.org --- target/mips/tcg/system/cp0_helper.c | 23 ++++++++--------------- 1 file changed, 8 insertions(+), 15 deletions(-) diff --git a/target/mips/tcg/system/cp0_helper.c b/target/mips/tcg/system/cp0_helper.c index 8c2114c58a6..5db8166d452 100644 --- a/target/mips/tcg/system/cp0_helper.c +++ b/target/mips/tcg/system/cp0_helper.c @@ -866,24 +866,17 @@ void helper_mtc0_memorymapid(CPUMIPSState *env, target_ulong arg1) void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask) { - uint32_t mask; - int maskbits; - /* Don't care MASKX as we don't support 1KB page */ - mask = extract32((uint32_t)arg1, CP0PM_MASK, 16); - maskbits = cto32(mask); + uint32_t mask = extract32((uint32_t)arg1, CP0PM_MASK, 16); + int maskbits = cto32(mask); - /* Ensure no more set bit after first zero */ - if ((mask >> maskbits) != 0) { - goto invalid; + /* Ensure no more set bit after first zero, and maskbits even. */ + if ((mask >> maskbits) == 0 && maskbits % 2 == 0) { + env->CP0_PageMask = mask << CP0PM_MASK; + } else { + /* When invalid, set to default target page size. */ + env->CP0_PageMask = 0; } - env->CP0_PageMask = mask << CP0PM_MASK; - - return; - -invalid: - /* When invalid, set to default target page size. */ - env->CP0_PageMask = 0; } void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1) From patchwork Mon Mar 31 19:48:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877317 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp1925236wrs; Mon, 31 Mar 2025 12:52:44 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCU7KE/Fp+DdOk5LpD0JRIa4toVfdHFhZpnUXA5N2FVui32NujFfTKG1ZoQlflL/SIuwwaxZyg==@linaro.org X-Google-Smtp-Source: AGHT+IEJhR8jfXYXOnwNnEzZDHHjINh+jpxOA1aJVMv2Yt3SdlnLt/h2FdhFDcWaLj4HECeYEMWK X-Received: by 2002:a05:6214:1d2f:b0:6e6:6505:ceb2 with SMTP id 6a1803df08f44-6eed621d7e8mr156632256d6.36.1743450764496; Mon, 31 Mar 2025 12:52:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743450764; cv=none; d=google.com; s=arc-20240605; b=HOka9FR+Hnt/QLdww/B0y40nFRmZe1rAczuq8VFWSyHhDyFHvXqAAP7jDuz7B5WlXV YQUj4ZuAu3o3eyxDSlNcAgbbHyJ1BC8BVvs4aPWuvzKFcav351ZlfCs71W9IPyCn6+5c /Eb55Z6slU53RfMty4zWZXZKN7YUZQETYwE7nOJutfy8JEaBtPs5ABVxf0dn716rjUon PRXBqDDFjc3zel9W11gGzmz9e60A2hKnZEGP8irgv7bfgvTIOlszW1vvX3QwbvvnFc7N Kj+ggGvGkEVjlkXwzsOc30YJYIALa8Dy6Gg54lgE5bgXSH/cmdHGleRkByiQLF5aor4M rB3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=/wI1i9qpwMZwJME1QE61gTcf1pbGJNg+cm1Z2vgD76Q=; fh=O7LQEuPUKRm68aNa1sjyGnw/Hj12o+u/i0zS3P0x7JY=; b=X1XdYMPg7SLel+8GQDBWrXh1G2RgXtoRzDe8NedcAF0Obp1BWhUkwllFjEUFGQtACE 9kTJvwt0OHOyBZnUtOefu6ec1s0LYxsHywQpvrJbArRxutH4A0rZibZMXgF+iI5JQskn q4ZCU5G1MZKDhKpVPwG52Lp/wAnAbcWPKYzRJU4kwNZeZeXN/Ik+C/wpKPIQMkDV7x5a kHf6Da0jwUbp8/da4shxoXJuozedpGO4iV7hEWIosSa79dYtUSdy9b97HYgF9xke2KdS Lg0kOI6sX0SYf+kMFnmmUx3IGRIVBh69OkkOdm8S7CVAsGYe3oQw94MobYtqLy0aIyhv YQWA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="at/lwAQu"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d82dedd03sm174803455e9.3.2025.03.31.12.50.19 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 31 Mar 2025 12:50:19 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , qemu-stable@nongnu.org Subject: [PULL 23/23] target/mips: Simplify and fix update_pagemask Date: Mon, 31 Mar 2025 21:48:21 +0200 Message-ID: <20250331194822.77309-24-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250331194822.77309-1-philmd@linaro.org> References: <20250331194822.77309-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson When update_pagemask was split from helper_mtc0_pagemask, we failed to actually write to the new parameter but continue to write to env->CP0_PageMask. Thus the use within page_table_walk_refill modifies cpu state and not the local variable as expected. Simplify by renaming to compute_pagemask and returning the value directly. No need for either env or pointer return. Fixes: 074cfcb4dae ("target/mips: Implement hardware page table walker for MIPS32") Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20250328175526.368121-4-richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé Cc: qemu-stable@nongnu.org --- target/mips/tcg/tcg-internal.h | 2 +- target/mips/tcg/system/cp0_helper.c | 10 +++++----- target/mips/tcg/system/tlb_helper.c | 2 +- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h index 74fc1309a71..950e6afc3f2 100644 --- a/target/mips/tcg/tcg-internal.h +++ b/target/mips/tcg/tcg-internal.h @@ -47,7 +47,7 @@ bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); void mmu_init(CPUMIPSState *env, const mips_def_t *def); -void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask); +uint32_t compute_pagemask(uint32_t val); void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra); uint32_t cpu_mips_get_random(CPUMIPSState *env); diff --git a/target/mips/tcg/system/cp0_helper.c b/target/mips/tcg/system/cp0_helper.c index 5db8166d452..78e422b0caf 100644 --- a/target/mips/tcg/system/cp0_helper.c +++ b/target/mips/tcg/system/cp0_helper.c @@ -864,24 +864,24 @@ void helper_mtc0_memorymapid(CPUMIPSState *env, target_ulong arg1) } } -void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask) +uint32_t compute_pagemask(uint32_t val) { /* Don't care MASKX as we don't support 1KB page */ - uint32_t mask = extract32((uint32_t)arg1, CP0PM_MASK, 16); + uint32_t mask = extract32(val, CP0PM_MASK, 16); int maskbits = cto32(mask); /* Ensure no more set bit after first zero, and maskbits even. */ if ((mask >> maskbits) == 0 && maskbits % 2 == 0) { - env->CP0_PageMask = mask << CP0PM_MASK; + return mask << CP0PM_MASK; } else { /* When invalid, set to default target page size. */ - env->CP0_PageMask = 0; + return 0; } } void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1) { - update_pagemask(env, arg1, &env->CP0_PageMask); + env->CP0_PageMask = compute_pagemask(arg1); } void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1) diff --git a/target/mips/tcg/system/tlb_helper.c b/target/mips/tcg/system/tlb_helper.c index 123639fa18e..df80301a412 100644 --- a/target/mips/tcg/system/tlb_helper.c +++ b/target/mips/tcg/system/tlb_helper.c @@ -876,7 +876,7 @@ refill: } } pw_pagemask = m >> TARGET_PAGE_BITS; - update_pagemask(env, pw_pagemask << CP0PM_MASK, &pw_pagemask); + pw_pagemask = compute_pagemask(pw_pagemask << CP0PM_MASK); pw_entryhi = (address & ~0x1fff) | (env->CP0_EntryHi & 0xFF); { target_ulong tmp_entryhi = env->CP0_EntryHi;