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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c0b658b52sm13272047f8f.4.2025.04.01.01.09.44 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 01 Apr 2025 01:09:44 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Gustavo Romero , Pierrick Bouvier , Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH-for-10.1 01/24] hw/core/cpu: Update CPUClass::mmu_index docstring Date: Tue, 1 Apr 2025 10:09:14 +0200 Message-ID: <20250401080938.32278-2-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250401080938.32278-1-philmd@linaro.org> References: <20250401080938.32278-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philmd@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Since commits 32a8ea12fab..90b7022e698 (target: "Split out TARGET_env_mmu_index"), target's memory_rw_debug() callbacks use the target's TARGET_env_mmu_index(), not the generic CPUClass::mmu_index() callback. Update the documentation. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/hw/core/cpu.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 84a71d8cf17..60b7abaf49b 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -104,8 +104,7 @@ struct SysemuCPUOps; * instantiatable CPU type. * @parse_features: Callback to parse command line arguments. * @reset_dump_flags: #CPUDumpFlags to use for reset logging. - * @mmu_index: Callback for choosing softmmu mmu index; - * may be used internally by memory_rw_debug without TCG. + * @mmu_index: Callback for choosing softmmu mmu index. * @memory_rw_debug: Callback for GDB memory access. * @dump_state: Callback for dumping state. * @query_cpu_fast: From patchwork Tue Apr 1 08:09:15 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877448 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp2131807wrs; Tue, 1 Apr 2025 01:10:36 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXqHfKsPucuM0vB7Fiyc0d77wAtYhnc3RU+ADzaGM8YfoHLwsA7zs+a+yz/X+tv6QNlt8CS1g==@linaro.org X-Google-Smtp-Source: AGHT+IH6Pwb4sbB8UDvGuOaCBIFJamJoDiD+DFzOOaZGhARp739Zet9GU/kPhdtxdCWC3PANY8qr X-Received: by 2002:a05:620a:40c6:b0:7c5:5909:18f3 with SMTP id af79cd13be357-7c75bc6904dmr320230385a.37.1743495035969; Tue, 01 Apr 2025 01:10:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743495035; cv=none; d=google.com; s=arc-20240605; b=Dj2147KyxlQAsBaQAU/UVafIHRovWJKd6UIRuCrHOxstoyBQx0f+z1QswnxfA1CMjW nmvJb264u/WQp8RHhE6YmoBcF0zryr4g4oAWTgCNptRFN2X2wn8SWzC9G+ArB3yME0ui s9TpvaqSbEJYvaa4C5wG6rF1e5As1C4RA/onyoqbFPuYyYbkEVTuiaeBTIA4p9ENve+v JaUlF/zuMg9NihcsHZqx2LC9o4lNJ3/rCLP4i08C6FxGNjczBxMN8l1UQEtT+qUVGrWt k2q0XcIz/53445JAwrFevFoJDRjLF3E0evhuP7/iK9qZ9dLMotCyzgxV44vi6/FMSbRz wR9Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Z/C9eBT5K6NV+Z7IEOoDW8bFUHrvBiPlv6gBs4OyowY=; fh=CAGeK5XzVxhZd11QbpVKk336R6CDVKo+zE/x8lNabbs=; b=B84oOJyOBfK97I2JylewSgR8W5HsvP5bzuxpz38LBmIvEmgeSQRvcj0Rya7L0cXF9S fIqi3r+5gkVbPbxkIi5QSHMD+i1Nt3PwzXfU1msJC4zGcMyedxcjlbkJl6qm22XMCLvo tQiVQl6w0D52FSIV7U4jDdzzKtWuyNyJRTFo4BIIE9+x2i2X0rvZy5p3b9tyDSuDuTlX Px4n1E+oUn4YMSanR5OIeRVoiPYQkhLAoFoDiPHVvcwYO2nhWiOzd3I1N3ZwdXccjtOO 6060ALiPxovvN8hmmaEzxhX4GQQD1Kj7mAotCFryCNZN4KNqOHTOPNqPvA5InQvhlt/y 3jtQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="PI/MTn3/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c0b79e1b0sm13319243f8f.75.2025.04.01.01.09.49 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 01 Apr 2025 01:09:50 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Gustavo Romero , Pierrick Bouvier , Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH-for-10.1 02/24] accel/tcg: Introduce TCGCPUOps::mmu_index() callback Date: Tue, 1 Apr 2025 10:09:15 +0200 Message-ID: <20250401080938.32278-3-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250401080938.32278-1-philmd@linaro.org> References: <20250401080938.32278-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philmd@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We'll move CPUClass::mmu_index() to TCGCPUOps::mmu_index(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/accel/tcg/cpu-ops.h | 3 +++ include/exec/cpu-mmu-index.h | 5 ++++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index f60e5303f21..106a0688da8 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -67,6 +67,9 @@ struct TCGCPUOps { /** @debug_excp_handler: Callback for handling debug exceptions */ void (*debug_excp_handler)(CPUState *cpu); + /** @mmu_index: Callback for choosing softmmu mmu index */ + int (*mmu_index)(CPUState *cpu, bool ifetch); + #ifdef CONFIG_USER_ONLY /** * @fake_user_interrupt: Callback for 'fake exception' handling. diff --git a/include/exec/cpu-mmu-index.h b/include/exec/cpu-mmu-index.h index cfc13d46bea..651526e9f97 100644 --- a/include/exec/cpu-mmu-index.h +++ b/include/exec/cpu-mmu-index.h @@ -10,6 +10,7 @@ #define EXEC_CPU_MMU_INDEX_H #include "hw/core/cpu.h" +#include "accel/tcg/cpu-ops.h" #include "tcg/debug-assert.h" #ifdef COMPILING_PER_TARGET #include "cpu.h" @@ -31,7 +32,9 @@ static inline int cpu_mmu_index(CPUState *cs, bool ifetch) # endif #endif - int ret = cs->cc->mmu_index(cs, ifetch); + const TCGCPUOps *tcg_ops = cs->cc->tcg_ops; + int ret = tcg_ops->mmu_index ? tcg_ops->mmu_index(cs, ifetch) + : cs->cc->mmu_index(cs, ifetch); tcg_debug_assert(ret >= 0 && ret < NB_MMU_MODES); return ret; } From patchwork Tue Apr 1 08:09:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877451 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp2131865wrs; Tue, 1 Apr 2025 01:10:45 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCX3lMXfJkAyceBSxrg74ij5zmQlodvRcgzdp9YWtMhZX6oDvMKkq/YQDWSTB7kPsf6fkMRn5w==@linaro.org X-Google-Smtp-Source: AGHT+IF9D+9sBTOq+T6bBv6NYyY0J1W2eQMnONOAfVjN0vt8HMcI4Uex1J+eFscWSeReC4bZDINQ X-Received: by 2002:a05:6214:5297:b0:6e8:9a2a:145b with SMTP id 6a1803df08f44-6eed60bd410mr171511116d6.23.1743495044893; Tue, 01 Apr 2025 01:10:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743495044; cv=none; d=google.com; s=arc-20240605; b=VROl0hZY1TCx/40zIRU5O/AVydi4PbFwWskst097dOLOlwx3lZDEOzC+Ck4JDyFnvu h1j0+sbEO1WnBARXwemQGtMVC/roUxFP34rZXbWJTEjSeFgXlN6+qvmIwEp0FKnoGuBE tyRn1Y6yFORd5uCw8Ebz0M23SxeIzus53H8Uoq75bJL4b7n8INpHsFTO3g7J55BKwNtR lQIZ2tHCutRQZQjuflkI/wEiGXNoIc0t/0SShRkI4WbnFefkw4VedNZIV9AmkWHCnjgR xs7Tm4cA5RfNPco3SNmPb8jEgp6Oj4FrXBbIo/EYG9AA6A0QhxyMKyv61lg5szEWKtvx eZwA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=bNXbkOwvuq2QN9fW+1tUFXQARVhg5/MHeMsjkrPZFlI=; fh=CAGeK5XzVxhZd11QbpVKk336R6CDVKo+zE/x8lNabbs=; b=lyvBVOUIbWAXNR0uHSR5cLjvtE2ecSFireN5RTaX5V9CylXq0pi2Y7rpwswfG1wVyK zddwP4FVgLIlipLd9lpx5wM3FYaKNV7diPHcmD+VquZ0OKX2WXP1Em1ZTPlJ3eyupPB8 dvnfcJHOfdw274TECKs43gEWiPwk6n6MOg2i/v+NMxgvjPW7k5zlMTIZAMqRq3xC7sUl JgRfI3aeseAsskcOrLzOqOjsqQHERTS2vfVpOa8Q3Un/UJVH23seChmP1+JiAeB0cwhT xQEtmLGteHL/f3y5VUE3jMTPCarxyRE0W2f1LVR7C/NLouu3GntNIap/bo4HspHJx8Xd Tfcg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lwuBmsfE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d8fbc10f7sm149580475e9.14.2025.04.01.01.09.54 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 01 Apr 2025 01:09:55 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Gustavo Romero , Pierrick Bouvier , Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH-for-10.1 03/24] target/alpha: Restrict SoftMMU mmu_index() to TCG Date: Tue, 1 Apr 2025 10:09:16 +0200 Message-ID: <20250401080938.32278-4-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250401080938.32278-1-philmd@linaro.org> References: <20250401080938.32278-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé --- target/alpha/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 935ad2ee1ae..99d839a2792 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -239,6 +239,7 @@ static const TCGCPUOps alpha_tcg_ops = { .translate_code = alpha_translate_code, .synchronize_from_tb = alpha_cpu_synchronize_from_tb, .restore_state_to_opc = alpha_restore_state_to_opc, + .mmu_index = alpha_cpu_mmu_index, #ifdef CONFIG_USER_ONLY .record_sigsegv = alpha_cpu_record_sigsegv, @@ -263,7 +264,6 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data) &acc->parent_realize); cc->class_by_name = alpha_cpu_class_by_name; - cc->mmu_index = alpha_cpu_mmu_index; cc->dump_state = alpha_cpu_dump_state; cc->set_pc = alpha_cpu_set_pc; cc->get_pc = alpha_cpu_get_pc; From patchwork Tue Apr 1 08:09:17 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877452 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp2132012wrs; Tue, 1 Apr 2025 01:11:09 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVk7roBiv/V8FSRuUcfEgtrN9152Ie6+IFwfeBk6vtTrkrGqrCAPRcaBNBKblotMWeB9AWUcw==@linaro.org X-Google-Smtp-Source: AGHT+IFXxRyZbFeTg6Raomqrk+Yv+I8V2FPublIhlXPT2GqGRc+JoUimH7Oi2qYL7JXqOKvFV0KM X-Received: by 2002:a05:622a:11c8:b0:476:909b:8287 with SMTP id d75a77b69052e-477ed7f361amr234251211cf.20.1743495069043; Tue, 01 Apr 2025 01:11:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743495069; cv=none; d=google.com; s=arc-20240605; b=Le3qqwWuYXBVA/WIu96ItKAYcFDbNDP3RPGL0dOHNXk22UeSJQGTJlUBkj4jmtBxtX /DyN1vEXx/gEXTzd7/bVHoDH6mj/pW9nIls0m+dmkijMgKCOPR9xKJB/5QI5OOLWpzDZ R14rkSoLHq19vI2XJycM9iooBO12H2GLwzo+5IaiTLj1ZuFWkVdKQD6J2xOjDq7ZZlSE L9S0vsyFz95jqoC22DAUMbRlV6uMS0cmL7TX5hq+yKzI8Z4QghiIimIosymxZX/ewiak TGjOsRMo7AANtJyyoJ4jYwQrO3ZE4BPFail2nRncYD+/GYqPQgErvZ186d1bSIzWUHCR BVdA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=iOUfwVEN3xQycXHlRqTY2E9mL68SSaiI0fdupHWA/TQ=; fh=CAGeK5XzVxhZd11QbpVKk336R6CDVKo+zE/x8lNabbs=; b=ezoUNaAK1r0Dq+XHH+VfR9vRHPeyWw+TG+sibyN4cqz7WjtLYi9kYipZBO8F7v8IcK q6lVJAvlCrF2oBqnTLMB8Q/99y0Ar5oiaOkwnXRC6geRuyVg39A13G325aQvRZBmjnvR ZRFBWziKJPkOeSphfedK1ZgAWeTv5O2PUSB0VzrZEHkspMiocGn0h4YCHxcDuae10A8r 17d0mykGiPJjA1TzgmcPUlXtNo8RUtIjt0SOeKNNJgcTrCUuMKh/0yX2eBKkHk5BmW78 M8hsdb6/aU//x/bB3eDo7JIM5ywwYxrhppXmfOYiVJawGlObc+pHwRM9vOt6e0VtMxv2 BalA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZXKy9IIR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c0b66ab6dsm13157538f8f.48.2025.04.01.01.09.59 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 01 Apr 2025 01:09:59 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Gustavo Romero , Pierrick Bouvier , Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH-for-10.1 04/24] target/arm: Restrict SoftMMU mmu_index() to TCG Date: Tue, 1 Apr 2025 10:09:17 +0200 Message-ID: <20250401080938.32278-5-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250401080938.32278-1-philmd@linaro.org> References: <20250401080938.32278-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Move arm_cpu_mmu_index() within CONFIG_TCG #ifdef'ry, convert CPUClass::mmu_index() to TCGCPUOps::mmu_index(). Signed-off-by: Philippe Mathieu-Daudé --- target/arm/cpu.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index f29661938c4..92909276f0f 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -122,6 +122,12 @@ void arm_restore_state_to_opc(CPUState *cs, env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT; } } + +static int arm_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + return arm_env_mmu_index(cpu_env(cs)); +} + #endif /* CONFIG_TCG */ #ifndef CONFIG_USER_ONLY @@ -145,11 +151,6 @@ static bool arm_cpu_has_work(CPUState *cs) } #endif /* !CONFIG_USER_ONLY */ -static int arm_cpu_mmu_index(CPUState *cs, bool ifetch) -{ - return arm_env_mmu_index(cpu_env(cs)); -} - void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void *opaque) { @@ -2676,6 +2677,7 @@ static const TCGCPUOps arm_tcg_ops = { .debug_excp_handler = arm_debug_excp_handler, .restore_state_to_opc = arm_restore_state_to_opc, + .mmu_index = arm_cpu_mmu_index, #ifdef CONFIG_USER_ONLY .record_sigsegv = arm_cpu_record_sigsegv, .record_sigbus = arm_cpu_record_sigbus, @@ -2709,7 +2711,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) &acc->parent_phases); cc->class_by_name = arm_cpu_class_by_name; - cc->mmu_index = arm_cpu_mmu_index; cc->dump_state = arm_cpu_dump_state; cc->set_pc = arm_cpu_set_pc; cc->get_pc = arm_cpu_get_pc; From patchwork Tue Apr 1 08:09:18 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877472 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp2133611wrs; Tue, 1 Apr 2025 01:16:02 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCX9t/+mIhkIEbOl7YCRbkjGChw4Dcx8jRr4x6Y9Dl8FTIMxvpRFaNVpb5z3SvNUPyAUCFkEUw==@linaro.org X-Google-Smtp-Source: AGHT+IEKvWqUFw73KqpV4JYJGEMBgjtHpTwgshKii9got2xoSkwkDIKg2wBn6EEyxPYqkjeUbRk7 X-Received: by 2002:ad4:5ba1:0:b0:6e5:bc9:95f8 with SMTP id 6a1803df08f44-6eed5f9bd8fmr155191266d6.17.1743495361977; Tue, 01 Apr 2025 01:16:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743495361; cv=none; d=google.com; s=arc-20240605; b=YKoLb/dbJrl4M6qsVu4UoJIfM+uI40Lkw5sSDSJP7J/0QacuJq8Kb7MqUEM+hYB/+W e2dugdppv+N4ibtRCbJPysLBpBfQOux/isKqZcyhGusI7wlApztLWVQ2+14IlRmQmw2F BV1qp/57mgdSol0AvNK4wBl0+yC4xFWzkiewrbSNSlN31RDtnzMaJPakhrGWRIrh+lgm u1DQTqXoRf42+Xr51KiLpbqG5zplOQQOianWxpZZUgj/OIx2fH3tz2MXinygIYdVm2NC R5d+9HJqFSG50Y+nmIYqcNwsO5V4dsFYBrIjlZvIid3FmgtcK+sEOvqm3Si+GDOorcpp hDOA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=mfcvOAj6GV5G3ldirX7XsQaX70LEZxyBu8Djn/9K/DU=; fh=CAGeK5XzVxhZd11QbpVKk336R6CDVKo+zE/x8lNabbs=; b=enhfmWN/4ihh0I8q+reG7DBIxB6+yQKkx2xht0VHEWAR6mBk4pICKwc2YPBUGHqqkR gRn/eBkTrZDgh4D3wh99VImhylJDwie3mastzK3Az8zdCqxgUMAL33KLFrVYt25eW46p CQJ5JPzrYglKmPh4Xn7GFgs0UBgUClSeeZ7dLTosLi5hjfBMo9Gp110YaarfLcloYhpS vJcf4B68ZRnHf81gTqXTb2ZZWkk9HNQIyjxA27A1RXo6Q+n0tgFJgkblP0RCznR5Ztr2 O98iul63fQvZwHckHmcdofjxpH+UIDOKgsvyewkgPmM8y5bnbVMMT6WTv/zVloOBxPYK olFA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ttQVAamI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c0b66277dsm13351147f8f.24.2025.04.01.01.10.04 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 01 Apr 2025 01:10:04 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Gustavo Romero , Pierrick Bouvier , Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH-for-10.1 05/24] target/avr: Restrict SoftMMU mmu_index() to TCG Date: Tue, 1 Apr 2025 10:09:18 +0200 Message-ID: <20250401080938.32278-6-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250401080938.32278-1-philmd@linaro.org> References: <20250401080938.32278-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philmd@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé --- target/avr/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 11218224704..feb73e722b3 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -228,6 +228,7 @@ static const TCGCPUOps avr_tcg_ops = { .translate_code = avr_cpu_translate_code, .synchronize_from_tb = avr_cpu_synchronize_from_tb, .restore_state_to_opc = avr_restore_state_to_opc, + .mmu_index = avr_cpu_mmu_index, .cpu_exec_interrupt = avr_cpu_exec_interrupt, .cpu_exec_halt = avr_cpu_has_work, .tlb_fill = avr_cpu_tlb_fill, @@ -250,7 +251,6 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = avr_cpu_class_by_name; - cc->mmu_index = avr_cpu_mmu_index; cc->dump_state = avr_cpu_dump_state; cc->set_pc = avr_cpu_set_pc; cc->get_pc = avr_cpu_get_pc; From patchwork Tue Apr 1 08:09:19 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877453 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp2132068wrs; Tue, 1 Apr 2025 01:11:18 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUkUyyxlA+Z2yQam7Y5taZ3Lualg51hCGG7XsqUQhXSHKtBAqbkOn818+0D5/qKv7HWD5VM9g==@linaro.org X-Google-Smtp-Source: AGHT+IHS9qBCYkiFtIuP7Ne0n/3uBfSUOrofzSrgLqYyCTEGzgzHGGv8972B9XX9ItFEM/pqKdoq X-Received: by 2002:ac8:5948:0:b0:476:ad9d:d4e9 with SMTP id d75a77b69052e-477e4ba8178mr149697241cf.24.1743495078377; Tue, 01 Apr 2025 01:11:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743495078; cv=none; d=google.com; s=arc-20240605; b=dYFWJvQPn9FpGpvRUxZqmKqEkhpLC6oDAQpCgiiGM1o2+PUR4S7nfv+916v2k5hxXA mrQ/O2OV9f7WZaMbbswZsRn1WS2JE6MbcPdOOlLbtn4QVWxqCKNDJlCMuzMZBltxPlC3 kQZCdp56gbRYDqj3uL51cE29lhajksYv8oh7hkQfaRJui6O//t2PCpTpkUH3pqjoQAK9 MeDcJxfWeobZHZFY6CNYDvU/XX3pVLnH50japTKVshOcPugHT/Pddo6fnGsqTB3qWXsc CnqNid9sDgJMS55i8mewguuGU6gV5S3y3QtAuEDPQmDTaM9FOBsHTe6bKO/hsYEt9tSJ /Zsw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=PkCoYIb7m4pc+ERBu4up+WFfgiLqv22+MYfn749jHu4=; fh=CAGeK5XzVxhZd11QbpVKk336R6CDVKo+zE/x8lNabbs=; b=h2vR/yT9DAbX9vM0KVv0j0ApbN65BcAeuM2NLzKgtKHn+X42+M1cmZPfVYP3a6kcEA oqqRbydogAdNLc21iwf8+NsHNWD9p52euYMRcUM1jHLCtfR5kqBFZ72terTyvVD41HX+ avJ7P8PVBj2SCuxKteN4m6+g+94IlW2WcipbGWaQwADOwkSLwp040oFakJGd+90x0Flq i1WUa7EgqZLJ69Ku+o842HUBndjgNtLgcbUj424jbAcZpsc8UXmUIsijnsDxuACmTdYX 3k7BgRFBWpgWS9r2wXAvqiE9zVYZvZNFw7uvvPUVvHFmu62xkl/Tx9ur36n8ytv8Gq/M ZFBw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=z4r3JOH6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d8fcceaaasm147949435e9.18.2025.04.01.01.10.08 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 01 Apr 2025 01:10:09 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Gustavo Romero , Pierrick Bouvier , Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH-for-10.1 06/24] target/hppa: Restrict SoftMMU mmu_index() to TCG Date: Tue, 1 Apr 2025 10:09:19 +0200 Message-ID: <20250401080938.32278-7-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250401080938.32278-1-philmd@linaro.org> References: <20250401080938.32278-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé --- target/hppa/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 0da8cdf41f5..51bff0c5d62 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -257,6 +257,7 @@ static const TCGCPUOps hppa_tcg_ops = { .translate_code = hppa_translate_code, .synchronize_from_tb = hppa_cpu_synchronize_from_tb, .restore_state_to_opc = hppa_restore_state_to_opc, + .mmu_index = hppa_cpu_mmu_index, #ifndef CONFIG_USER_ONLY .tlb_fill_align = hppa_cpu_tlb_fill_align, @@ -282,7 +283,6 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data) &acc->parent_phases); cc->class_by_name = hppa_cpu_class_by_name; - cc->mmu_index = hppa_cpu_mmu_index; cc->dump_state = hppa_cpu_dump_state; cc->set_pc = hppa_cpu_set_pc; cc->get_pc = hppa_cpu_get_pc; From patchwork Tue Apr 1 08:09:20 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877450 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp2131840wrs; Tue, 1 Apr 2025 01:10:41 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVJ3aWlfonlI6jjkq67BToJwDtwZ14+0xOOYKs7afG8IXgzKltt9+E3zuXYwMrmNuEnm/C4Ow==@linaro.org X-Google-Smtp-Source: AGHT+IFMFNHzR7mj6x+zx0pekBkWr80Lfb3Xcu+FJthhoadowSbcoJLVDxNbxUly7nbNZA+IzSdk X-Received: by 2002:ad4:5e8c:0:b0:6e8:eabf:fd44 with SMTP id 6a1803df08f44-6eed60a51c1mr176771436d6.27.1743495041695; Tue, 01 Apr 2025 01:10:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743495041; cv=none; d=google.com; s=arc-20240605; b=LFRtVl1Hom69rtQwLswxppaLafQo79HUnCpzEXRuTj2E+lTzGPqBVj+Of7kgncNYfv ORfeOdpl20y9z2ohAOTQtPw7EzKPLPKZM5FSh+vCe5q4aNJK29+WAa7H5QJyoxHmlWFY R7X1Yd/JVJPYFkB0Qm4BsLTtqgHanUKZTb94XHtunSKAuvRpM4gz1idrg5qzkdKcaOIX Yfq9ldD0kfiQxwT7o7UawMjQa/Q27vbjPL3m7gTwNtVoYsGzPZfkGsXO2NoX9E9yGGOq d6m3CJWV0KW1KhCT0hexUsG9w8H/w4VdoTclmLxn0MfnVE4Y/+LnXg5nxKxNOnO4IU02 T1vA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=fOHYuFnp4koozIqx1uCsPrUxKvA8s1qXFiegecsD2JY=; fh=CAGeK5XzVxhZd11QbpVKk336R6CDVKo+zE/x8lNabbs=; b=CSS0pEYt0tNKBf785RNzZEQBXWy1FsGIfUU5Z3qeSKUcRDhts1PmV4qZ0Q6XgOKhfq THNrUp1V9l+m0orhC/30KbB62FDGfAMLXdan7OPsxxb2qT6VUlTkWM3RdM7B7RvbWSGT uo3L+dUd5cPSbfO3xMrzOnGFKGdQ15YYDd+HphZeOunpTiUkxJYDn2uP7wlky2hp/py7 jfIxhHN/aMnirDtIR6IBmXz1f+LCSSP8xdD2ouyEMvBMh/trhRsCspcGSLGM7Vtvb5ba YZbh66qfjrJobZMAJnRHLWJ075z7js1kP3b1DZoG+nJ1TdpOV84m9W/d9zKWoWHZXZuA j8Gg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=GKE3MOv8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=fail header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d82dedc2dsm190349835e9.2.2025.04.01.01.10.13 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 01 Apr 2025 01:10:13 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Gustavo Romero , Pierrick Bouvier , Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH-for-10.1 07/24] target/i386: Remove unused cpu_(ldub, stb)_kernel macros Date: Tue, 1 Apr 2025 10:09:20 +0200 Message-ID: <20250401080938.32278-8-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250401080938.32278-1-philmd@linaro.org> References: <20250401080938.32278-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=philmd@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé --- target/i386/tcg/seg_helper.h | 6 ------ 1 file changed, 6 deletions(-) diff --git a/target/i386/tcg/seg_helper.h b/target/i386/tcg/seg_helper.h index ebf10352778..6b8606cd6d8 100644 --- a/target/i386/tcg/seg_helper.h +++ b/target/i386/tcg/seg_helper.h @@ -35,8 +35,6 @@ * TODO: Convert callers to compute cpu_mmu_index_kernel once * and use *_mmuidx_ra directly. */ -#define cpu_ldub_kernel_ra(e, p, r) \ - cpu_ldub_mmuidx_ra(e, p, cpu_mmu_index_kernel(e), r) #define cpu_lduw_kernel_ra(e, p, r) \ cpu_lduw_mmuidx_ra(e, p, cpu_mmu_index_kernel(e), r) #define cpu_ldl_kernel_ra(e, p, r) \ @@ -44,8 +42,6 @@ #define cpu_ldq_kernel_ra(e, p, r) \ cpu_ldq_mmuidx_ra(e, p, cpu_mmu_index_kernel(e), r) -#define cpu_stb_kernel_ra(e, p, v, r) \ - cpu_stb_mmuidx_ra(e, p, v, cpu_mmu_index_kernel(e), r) #define cpu_stw_kernel_ra(e, p, v, r) \ cpu_stw_mmuidx_ra(e, p, v, cpu_mmu_index_kernel(e), r) #define cpu_stl_kernel_ra(e, p, v, r) \ @@ -53,12 +49,10 @@ #define cpu_stq_kernel_ra(e, p, v, r) \ cpu_stq_mmuidx_ra(e, p, v, cpu_mmu_index_kernel(e), r) -#define cpu_ldub_kernel(e, p) cpu_ldub_kernel_ra(e, p, 0) #define cpu_lduw_kernel(e, p) cpu_lduw_kernel_ra(e, p, 0) #define cpu_ldl_kernel(e, p) cpu_ldl_kernel_ra(e, p, 0) #define cpu_ldq_kernel(e, p) cpu_ldq_kernel_ra(e, p, 0) -#define cpu_stb_kernel(e, p, v) cpu_stb_kernel_ra(e, p, v, 0) #define cpu_stw_kernel(e, p, v) cpu_stw_kernel_ra(e, p, v, 0) #define cpu_stl_kernel(e, p, v) cpu_stl_kernel_ra(e, p, v, 0) #define cpu_stq_kernel(e, p, v) cpu_stq_kernel_ra(e, p, v, 0) From patchwork Tue Apr 1 08:09:21 2025 Content-Type: text/plain; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c0b7a4351sm13659771f8f.98.2025.04.01.01.10.18 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 01 Apr 2025 01:10:18 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Gustavo Romero , Pierrick Bouvier , Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH-for-10.1 08/24] target/i386: Restrict cpu_mmu_index_kernel() to TCG Date: Tue, 1 Apr 2025 10:09:21 +0200 Message-ID: <20250401080938.32278-9-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250401080938.32278-1-philmd@linaro.org> References: <20250401080938.32278-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=philmd@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Move cpu_mmu_index_kernel() to seg_helper.c. Signed-off-by: Philippe Mathieu-Daudé --- target/i386/cpu.h | 1 - target/i386/tcg/seg_helper.h | 4 ++++ target/i386/cpu.c | 16 ---------------- target/i386/tcg/seg_helper.c | 16 ++++++++++++++++ 4 files changed, 20 insertions(+), 17 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 44ee263d8f1..e23a947a7c7 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2598,7 +2598,6 @@ static inline bool is_mmu_index_32(int mmu_index) } int x86_mmu_index_pl(CPUX86State *env, unsigned pl); -int cpu_mmu_index_kernel(CPUX86State *env); #define CC_DST (env->cc_dst) #define CC_SRC (env->cc_src) diff --git a/target/i386/tcg/seg_helper.h b/target/i386/tcg/seg_helper.h index 6b8606cd6d8..ea98e1a98ed 100644 --- a/target/i386/tcg/seg_helper.h +++ b/target/i386/tcg/seg_helper.h @@ -20,6 +20,8 @@ #ifndef SEG_HELPER_H #define SEG_HELPER_H +#include "cpu.h" + //#define DEBUG_PCALL #ifdef DEBUG_PCALL @@ -31,6 +33,8 @@ # define LOG_PCALL_STATE(cpu) do { } while (0) #endif +int cpu_mmu_index_kernel(CPUX86State *env); + /* * TODO: Convert callers to compute cpu_mmu_index_kernel once * and use *_mmuidx_ra directly. diff --git a/target/i386/cpu.c b/target/i386/cpu.c index af46c7a392a..0b74b9a3754 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -8669,22 +8669,6 @@ static int x86_cpu_mmu_index(CPUState *cs, bool ifetch) return x86_mmu_index_pl(env, env->hflags & HF_CPL_MASK); } -static int x86_mmu_index_kernel_pl(CPUX86State *env, unsigned pl) -{ - int mmu_index_32 = (env->hflags & HF_LMA_MASK) ? 0 : 1; - int mmu_index_base = - !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP64_IDX : - (pl < 3 && (env->eflags & AC_MASK) - ? MMU_KNOSMAP64_IDX : MMU_KSMAP64_IDX); - - return mmu_index_base + mmu_index_32; -} - -int cpu_mmu_index_kernel(CPUX86State *env) -{ - return x86_mmu_index_kernel_pl(env, env->hflags & HF_CPL_MASK); -} - static void x86_disas_set_info(CPUState *cs, disassemble_info *info) { X86CPU *cpu = X86_CPU(cs); diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c index 71962113fb8..f4370202fed 100644 --- a/target/i386/tcg/seg_helper.c +++ b/target/i386/tcg/seg_helper.c @@ -128,6 +128,22 @@ int get_pg_mode(CPUX86State *env) return pg_mode; } +static int x86_mmu_index_kernel_pl(CPUX86State *env, unsigned pl) +{ + int mmu_index_32 = (env->hflags & HF_LMA_MASK) ? 0 : 1; + int mmu_index_base = + !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP64_IDX : + (pl < 3 && (env->eflags & AC_MASK) + ? MMU_KNOSMAP64_IDX : MMU_KSMAP64_IDX); + + return mmu_index_base + mmu_index_32; +} + +int cpu_mmu_index_kernel(CPUX86State *env) +{ + return x86_mmu_index_kernel_pl(env, env->hflags & HF_CPL_MASK); +} + /* return non zero if error */ static inline int load_segment_ra(CPUX86State *env, uint32_t *e1_ptr, uint32_t *e2_ptr, int selector, From patchwork Tue Apr 1 08:09:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877469 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp2133220wrs; Tue, 1 Apr 2025 01:14:58 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCW+3gVQ6ZIrw0JjeqInSF5DlE/VNxvfyiNmnN75ckOd9tXs+OAiTJOh39Rh80fmeN+qbNgMWQ==@linaro.org X-Google-Smtp-Source: AGHT+IEgS60aXcDcYHWBcme9rAp9uyY8IRLB8mG9uh4pCrGL8XhraJPm9M6cMR1vaT3CHObcm76O X-Received: by 2002:a05:620a:4d03:b0:7c7:5ad8:aece with SMTP id af79cd13be357-7c75ad8b0bbmr333956385a.25.1743495297795; Tue, 01 Apr 2025 01:14:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743495297; cv=none; d=google.com; s=arc-20240605; b=SMYp5N7WoEV1WWmLFkHH7gTEVsZdMom39vDJnsZGBZMIGUwTqE2b8y/rSDaUtdk6+B HMy6PlfGj9F/HRFIj4W1jYquGE2nGN9sWlLq2uQ6VpmTXCopScSbxttK7rVEoSztBdBW azUTXiCgo/bFh1tx9PTqCsqJ0yJzDj5Mbp4PqojIGi+xwn+0pVvYUlyk5i4f0hTThO21 vSPfhfggoVzfHiLE9rq4D7Gz7hjSyfR4pabvQ4RXdnvxrh0jlx5YkYCQL400f/VOozy3 wE+csLlI5cJuwqivSWAKECJpUHpyB5wJYKgcVFWXDfGqY+9pSYNTfJbDBthgRet/feVk bnjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=WLT+75V3t7RNN4nMFI51bEe1MWRh5zKTcQJOkQ4RnJY=; fh=CAGeK5XzVxhZd11QbpVKk336R6CDVKo+zE/x8lNabbs=; b=ZxZzZUZof+pih9bHfMkQOXPz+9BofWEo2pg9bqMKA1QAFjNxkqMV2DGe6wyFq98s/F X6k7cJ1pAeMbZkJgGn0CHPI3BoxlgoE3BVo7r2AaqZFrTKlZ2e1o8J5F/aWubCS4YjIr YfGTHRRd5JYWziYq/Sf0l+eAAtCydbSguca7UqmCKQckSkxL6YJMjdLA3g/oA+mz3a+U gAKeDsvR8HaWbj9l1EHhpd5z6KJM3XzcuNPez3ztgiwD/cqvF6ip1Hao+xL7JI1nWHro XhOK7y3TDbvSZkEkPPoxe7XR6hmawrAmfAMoOA/bMUtrPPpG7pDR2gXJEJTj2eVnKQ6f zpRg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nw24V9Ij; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c0b7a8e0asm13312750f8f.101.2025.04.01.01.10.22 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 01 Apr 2025 01:10:23 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Gustavo Romero , Pierrick Bouvier , Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH-for-10.1 09/24] target/i386: Restrict SoftMMU mmu_index() to TCG Date: Tue, 1 Apr 2025 10:09:22 +0200 Message-ID: <20250401080938.32278-10-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250401080938.32278-1-philmd@linaro.org> References: <20250401080938.32278-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Move x86_cpu_mmu_index() to tcg-cpu.c, convert CPUClass::mmu_index() to TCGCPUOps::mmu_index(). Signed-off-by: Philippe Mathieu-Daudé --- target/i386/cpu.h | 2 -- target/i386/tcg/tcg-cpu.h | 2 ++ target/i386/cpu.c | 18 ------------------ target/i386/tcg/seg_helper.c | 1 + target/i386/tcg/tcg-cpu.c | 18 ++++++++++++++++++ 5 files changed, 21 insertions(+), 20 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index e23a947a7c7..35c16302bdc 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2597,8 +2597,6 @@ static inline bool is_mmu_index_32(int mmu_index) return mmu_index & 1; } -int x86_mmu_index_pl(CPUX86State *env, unsigned pl); - #define CC_DST (env->cc_dst) #define CC_SRC (env->cc_src) #define CC_SRC2 (env->cc_src2) diff --git a/target/i386/tcg/tcg-cpu.h b/target/i386/tcg/tcg-cpu.h index 53a84944551..7580f8afb4f 100644 --- a/target/i386/tcg/tcg-cpu.h +++ b/target/i386/tcg/tcg-cpu.h @@ -78,4 +78,6 @@ QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) != XSAVE_PKRU_OFFSET); bool tcg_cpu_realizefn(CPUState *cs, Error **errp); +int x86_mmu_index_pl(CPUX86State *env, unsigned pl); + #endif /* TCG_CPU_H */ diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 0b74b9a3754..d930ebd262e 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -8652,23 +8652,6 @@ static bool x86_cpu_has_work(CPUState *cs) } #endif /* !CONFIG_USER_ONLY */ -int x86_mmu_index_pl(CPUX86State *env, unsigned pl) -{ - int mmu_index_32 = (env->hflags & HF_CS64_MASK) ? 0 : 1; - int mmu_index_base = - pl == 3 ? MMU_USER64_IDX : - !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP64_IDX : - (env->eflags & AC_MASK) ? MMU_KNOSMAP64_IDX : MMU_KSMAP64_IDX; - - return mmu_index_base + mmu_index_32; -} - -static int x86_cpu_mmu_index(CPUState *cs, bool ifetch) -{ - CPUX86State *env = cpu_env(cs); - return x86_mmu_index_pl(env, env->hflags & HF_CPL_MASK); -} - static void x86_disas_set_info(CPUState *cs, disassemble_info *info) { X86CPU *cpu = X86_CPU(cs); @@ -8910,7 +8893,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data) cc->class_by_name = x86_cpu_class_by_name; cc->parse_features = x86_cpu_parse_featurestr; - cc->mmu_index = x86_cpu_mmu_index; cc->dump_state = x86_cpu_dump_state; cc->set_pc = x86_cpu_set_pc; cc->get_pc = x86_cpu_get_pc; diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c index f4370202fed..9dfbc4208cd 100644 --- a/target/i386/tcg/seg_helper.c +++ b/target/i386/tcg/seg_helper.c @@ -28,6 +28,7 @@ #include "helper-tcg.h" #include "seg_helper.h" #include "access.h" +#include "tcg-cpu.h" #ifdef TARGET_X86_64 #define SET_ESP(val, sp_mask) \ diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 36b8dc78a3e..35b17f2b183 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -94,6 +94,23 @@ static void x86_restore_state_to_opc(CPUState *cs, } } +int x86_mmu_index_pl(CPUX86State *env, unsigned pl) +{ + int mmu_index_32 = (env->hflags & HF_CS64_MASK) ? 0 : 1; + int mmu_index_base = + pl == 3 ? MMU_USER64_IDX : + !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP64_IDX : + (env->eflags & AC_MASK) ? MMU_KNOSMAP64_IDX : MMU_KSMAP64_IDX; + + return mmu_index_base + mmu_index_32; +} + +static int x86_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + CPUX86State *env = cpu_env(cs); + return x86_mmu_index_pl(env, env->hflags & HF_CPL_MASK); +} + #ifndef CONFIG_USER_ONLY static bool x86_debug_check_breakpoint(CPUState *cs) { @@ -112,6 +129,7 @@ static const TCGCPUOps x86_tcg_ops = { .translate_code = x86_translate_code, .synchronize_from_tb = x86_cpu_synchronize_from_tb, .restore_state_to_opc = x86_restore_state_to_opc, + .mmu_index = x86_cpu_mmu_index, .cpu_exec_enter = x86_cpu_exec_enter, .cpu_exec_exit = x86_cpu_exec_exit, #ifdef CONFIG_USER_ONLY From patchwork Tue Apr 1 08:09:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877463 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp2132338wrs; Tue, 1 Apr 2025 01:12:10 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXABAcKQqvVMATnuZgT43GKC2xKM0S9xbvxHNy+ICih5ebd9z8UMD3dalGBhaJS9DBsisGPFQ==@linaro.org X-Google-Smtp-Source: AGHT+IGV6HQw4tRxmJDBUIweqOsRzuuEPjphrnH4iFuiZRShxvpoVPQAFr9wQFGWHaXNsE0Tye4v X-Received: by 2002:ac8:7e86:0:b0:476:639e:edf1 with SMTP id d75a77b69052e-477e4b69c4emr180465511cf.23.1743495129920; Tue, 01 Apr 2025 01:12:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743495129; cv=none; d=google.com; s=arc-20240605; b=DeTjA269KHDDvCJqjuemhZhv2yYDJhIUuL2DZMoYDzo38mkE0VqToF3eJEiai5m18E ECEde1GM35bTz0EkinyrfGiKOV3wuRK2V0gi0K+V7CFQj3H9XGmascjyMXrhWFevg0dM jGkihN745qqtBPowfUjmkHsC4vPUY8mh8roiZq8v/uVWKx5PdpPfIA2sSUMabd/jvfZC YxY3omHqgqcNXC/V90OmkUOzTwSf+R19z2RPh1TfwkIgcvVdnZIKWZqfUX1KecWA1ZZg Y3ut2AZaDh0QDpjsk912BZ6PX8ffLdNdZjLLuOWWYzfqUcS6tOeK2Mu9m+p9/wlDAsIH LAKw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=43B0Gf644+rG+IGa27fovHaCeNyeLOk+U3XMHWBUZE8=; fh=CAGeK5XzVxhZd11QbpVKk336R6CDVKo+zE/x8lNabbs=; b=IH9s80cxTvyTdd2Ic52GLlI7941OyFYANgbwQXeWxCmAhfC7dqvneeeGEI8WZVUtcd fyPKTe6xrz/lgNkytdvNt4TdfWpaz+M9djY+e8x7jZBY3nmboOK49hXJPViIGsK4ugJJ xbqpmSf31pSHaEizbyZGKvl8Yjkz/AQG/GyFkMto08LOYu8hovEMK4JFjAs0UUU4rG/s agVBT2IRW6249EEWsF6QDPF9wIGzdpYIur+rHyWDF6YB/CFtfgRRXKcWqBdo0xTezfGJ tMbtszyE0SLFWWA5N4yuElWKA0yorDGxVbzoNOGbDCLbTbqy1wBXzbWpwIldHVAcxZdq UOVg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Z1+4tlwX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d8fcd774bsm147813735e9.23.2025.04.01.01.10.27 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 01 Apr 2025 01:10:27 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Gustavo Romero , Pierrick Bouvier , Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH-for-10.1 10/24] target/loongarch: Restrict SoftMMU mmu_index() to TCG Date: Tue, 1 Apr 2025 10:09:23 +0200 Message-ID: <20250401080938.32278-11-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250401080938.32278-1-philmd@linaro.org> References: <20250401080938.32278-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé --- target/loongarch/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index ea1665e2705..cb96b17911a 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -868,6 +868,7 @@ static const TCGCPUOps loongarch_tcg_ops = { .translate_code = loongarch_translate_code, .synchronize_from_tb = loongarch_cpu_synchronize_from_tb, .restore_state_to_opc = loongarch_restore_state_to_opc, + .mmu_index = loongarch_cpu_mmu_index, #ifndef CONFIG_USER_ONLY .tlb_fill = loongarch_cpu_tlb_fill, @@ -919,7 +920,6 @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data) &lacc->parent_phases); cc->class_by_name = loongarch_cpu_class_by_name; - cc->mmu_index = loongarch_cpu_mmu_index; cc->dump_state = loongarch_cpu_dump_state; cc->set_pc = loongarch_cpu_set_pc; cc->get_pc = loongarch_cpu_get_pc; From patchwork Tue Apr 1 08:09:24 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877466 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp2133045wrs; Tue, 1 Apr 2025 01:14:21 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUbNm2LMuYp6GIkqYkBZA5+PbbMtWdLHaxcqa7+iEuqiv0iid44+v2BdVAoKhfrv9BJaQ7pew==@linaro.org X-Google-Smtp-Source: AGHT+IEfdeCCgMlVeInBHWAcMTfKNU5QY6nmIKL1TuvVK5N1lyrVvORVSNdMCAwZM8/qdyA1stY/ X-Received: by 2002:a05:6214:20c4:b0:6e0:f451:2e22 with SMTP id 6a1803df08f44-6eed6239f91mr232798736d6.38.1743495261535; Tue, 01 Apr 2025 01:14:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743495261; cv=none; d=google.com; s=arc-20240605; b=jXpKnzsVqU0QszScp6WyLRTiF5ZknpzdpiRKx3I0QjZe13PbtFCjAr/pE/IGT5vx+D mVIjn3uwuJClmfzL8CkVIA0SCgV7Z8uzuF/herwNVuBV8DDCg+lVX1mX4TkAqpSrhUnU nAvTba/UOPI8HKTZ2vsGp0By+WMSroVcGxzZ+/TAHECRwOHC/75moPKrvWpO5MCxxKXu 5v6VIJXqNyTh77U4lUQvjMfcLXlyR+ZbMn5AWKlOqC8gYxWC72zwew7SPEpGyY6kLldS cycHmmwmrncgUlXZg55rCI+oWoyssKPvnFYlQ3z5Tb6MZ9AByUKnPkyuUJ9LRYFYHXON yXbw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=2GipMLU+zEgv9YkkQClbxhhgkFeUbIdD3++IpdMFRuI=; fh=CAGeK5XzVxhZd11QbpVKk336R6CDVKo+zE/x8lNabbs=; b=GDZ2n4ejhqWHtRSI1FeBipXkgl52cDWBJ2NXTYtKfy+WYMfW0NxK8fmcqxwS/n+B7k UFdq4xlvt151Li1xN4XvlDYgIQhiOHFwViCD5Z8xCzPb7hO8tbR158n+p65OAjQdLEx8 t0OVL8Ljuabv/Ikf2N8FXDH3+XVFoJio+zOIPOE8LXsYIwGIV/jYzqjB1hnPiTPzN5tG mu0OjPBbCTOqtsC213VaeSoJP4n3FxkNPTg4jvopqybmHCz8RyTc91eLUUNTTuCrbpn5 LiNIv7qSAtdsXBH8qWwg1ilzQfwR/pUCMRJISudOmxLcl+e9EbZGe1FWycyH97KPYbGC dcOw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tE5Rl28V; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d8fba4979sm151190345e9.7.2025.04.01.01.10.32 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 01 Apr 2025 01:10:32 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Gustavo Romero , Pierrick Bouvier , Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH-for-10.1 11/24] target/m68k: Restrict SoftMMU mmu_index() to TCG Date: Tue, 1 Apr 2025 10:09:24 +0200 Message-ID: <20250401080938.32278-12-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250401080938.32278-1-philmd@linaro.org> References: <20250401080938.32278-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé --- target/m68k/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 0065e1c1ca5..4409d8941ce 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -592,6 +592,7 @@ static const TCGCPUOps m68k_tcg_ops = { .initialize = m68k_tcg_init, .translate_code = m68k_translate_code, .restore_state_to_opc = m68k_restore_state_to_opc, + .mmu_index = m68k_cpu_mmu_index, #ifndef CONFIG_USER_ONLY .tlb_fill = m68k_cpu_tlb_fill, @@ -615,7 +616,6 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data) &mcc->parent_phases); cc->class_by_name = m68k_cpu_class_by_name; - cc->mmu_index = m68k_cpu_mmu_index; cc->dump_state = m68k_cpu_dump_state; cc->set_pc = m68k_cpu_set_pc; cc->get_pc = m68k_cpu_get_pc; From patchwork Tue Apr 1 08:09:25 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877462 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp2132324wrs; Tue, 1 Apr 2025 01:12:08 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXz3BYaAc5J9Xdm7Z8GEnaeIYiO33Ch/u2r2yv/oLU6+gSYMoQ1yZ5rz0Y37BCaY0PNxDrjfA==@linaro.org X-Google-Smtp-Source: AGHT+IEPhk/Uc0jHcgiTG7a2qInz9R83fQiOtnoEYjH0gVanXLLwadsWOsGTywH08wEIoj+BLB+m X-Received: by 2002:a05:622a:1983:b0:477:6e6b:aeb3 with SMTP id d75a77b69052e-477d784b72emr163177751cf.0.1743495127957; Tue, 01 Apr 2025 01:12:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743495127; cv=none; d=google.com; s=arc-20240605; b=LIp1W7BBmCgIv0vPsc+LpAzx5bWIzvwty0RZqy2If4ELsjQnue2xOLoTRp4OigZA/n WTQW+JNm9G/TjeC09FBrPkX3DYdyKoY55AmVU/F1F5bYWXKyrl8PHwzzhqk7izpuJK05 yIpq7JCIRR0SyRO6ixnAbPxW6nQaK4htZM92Iuf4TTUIPWeve6IceSEXfjqbP+NTSLJ5 IwIzj4iz5iOD3IvOQM+rzMKWv7+fi7MNvZP0+ofwCs+7QhcrnzwZVoIVFBghr3hIaTMk 7zqmYB8xSAlkfZ+EuTDoScKModnwB8/lohp4lmMGgM/AfyxmG0SGmqyvpESta66NcIH5 QyQQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=jTF2Nwd/7EYny8ycNBkkJ38P9w+PAXKeooK7567a9ug=; fh=CAGeK5XzVxhZd11QbpVKk336R6CDVKo+zE/x8lNabbs=; b=EfaMDhC7BIcMHpJPlgc1TaUsXCxFjoQ+45diI+YmcNyXZC3dWbJE0Qebouk3hjyiGe 4h4fq1uygIXFPk4KtzYCkony3i7AjhEPbhzlxQRG6DqcpKq4pNRBbkhTEFoKFytj4fzN kYQ7d5aWdyQVUy31DP9SQVeGjTuF19DDu08Q9/Y1kb0Rcr49tMwpX63SRi3NREQNDcAZ 40BlnViNyYwB7OUnZ7H4HiBrvWgaR4ARMl7djrbm9EwtQonU0gJAvre/AWUVIxdZIluu 6CmVGdmJLytZb/fASNri+LGB7f/mXaQEyR+c9ZrcYsF0j60HI70Y2ArMKvc6UU2EEM3i 4pzg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Aa+qmfI7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c0dcc66a4sm12394423f8f.42.2025.04.01.01.10.37 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 01 Apr 2025 01:10:38 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Gustavo Romero , Pierrick Bouvier , Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH-for-10.1 12/24] target/microblaze: Restrict SoftMMU mmu_index() to TCG Date: Tue, 1 Apr 2025 10:09:25 +0200 Message-ID: <20250401080938.32278-13-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250401080938.32278-1-philmd@linaro.org> References: <20250401080938.32278-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philmd@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé --- target/microblaze/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index f3bebea856e..88baeb6807a 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -431,6 +431,7 @@ static const TCGCPUOps mb_tcg_ops = { .translate_code = mb_translate_code, .synchronize_from_tb = mb_cpu_synchronize_from_tb, .restore_state_to_opc = mb_restore_state_to_opc, + .mmu_index = mb_cpu_mmu_index, #ifndef CONFIG_USER_ONLY .tlb_fill = mb_cpu_tlb_fill, @@ -455,7 +456,6 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data) &mcc->parent_phases); cc->class_by_name = mb_cpu_class_by_name; - cc->mmu_index = mb_cpu_mmu_index; cc->dump_state = mb_cpu_dump_state; cc->set_pc = mb_cpu_set_pc; cc->get_pc = mb_cpu_get_pc; From patchwork Tue Apr 1 08:09:26 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877454 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp2132071wrs; Tue, 1 Apr 2025 01:11:18 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUJPJCTqPmf7XPeL9Qdiy+U3AMWPOLMBOvHnwGuPLGnQL56VsYGwPjYqIRBAbdq242BTYX7KA==@linaro.org X-Google-Smtp-Source: AGHT+IFiI2OyV8Tb0FyrG1MiiIAKYOJcdl17057+BbT0FKtZcwEcBDlwp/MpfHkGiQSnLtSc9x/D X-Received: by 2002:ac8:5d08:0:b0:476:fd6e:df89 with SMTP id d75a77b69052e-477b3b2e646mr184194991cf.17.1743495078568; Tue, 01 Apr 2025 01:11:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743495078; cv=none; d=google.com; s=arc-20240605; b=c4+UovsOzcNJlNNdJo1U0iJJqfRWMVQSYVXgB8KtMLrMlueW1sYQlHZo+8Br3ieUF3 UNYKEABbOYWxi4oZqA7dhgQ+enO1ZVIsLMNV5kryeHuNq6pr0Zpnsx/7gxVxBFXxTd7B CCc0p6VuL5HAP4EHUK7pZb8xpzWzzGh0iq7lzgZouTGJBypdlWnukvrHPrD7wMksFw9E R9QjFHZifbLeIAqvYpdIqA4LDYtP6vVzm42zAKPuikqPv+rPCmDA4VRRqBYf870TgQFm EZoELPCL/1Mlozi/XjY6xJqm7vT8LiE8UtmixopeY8UNmv7N49hXxIfOMVYSIMP2Ch6G 0PVQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=kPB58+FTxXSO7a6ABgKbjWcxmkemD1i3O76geVQ4vzw=; fh=CAGeK5XzVxhZd11QbpVKk336R6CDVKo+zE/x8lNabbs=; b=VduwFkYYrCOh+Z12O1RGL9u8FXXkQniJUpNkCUX7QhrmqYmoMncOYT+3+JS0+JPC0n lWD3HDXq1WekMZOYOF/epf8bO/JZVKFyzhLEcn6pc+/YMXdZzhbA9ZOvEF2fZnAjYqb2 FPvi9HtNWA8EtRE0VWsg2DNk0Frm3VZbUdsR5wK08+sOGL2iy3XYBo6lMtD6H4J7Ph4J gwOh0OstRRrYgDFAP4ac8zAbqQCHJJMRFkqOsGvpvNMNeQ6kbCG5y63sHp77KUidtTmk rxeV4Gz1W8ExIrtiVN0Qq1SUJmapv1h47ygAwl3MYkEqHu9o8I9/xFDPyBI/hfFV1wFt g2fw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QzvYr6bI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d90000a09sm146854675e9.35.2025.04.01.01.10.42 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 01 Apr 2025 01:10:42 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Gustavo Romero , Pierrick Bouvier , Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH-for-10.1 13/24] target/mips: Restrict SoftMMU mmu_index() to TCG Date: Tue, 1 Apr 2025 10:09:26 +0200 Message-ID: <20250401080938.32278-14-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250401080938.32278-1-philmd@linaro.org> References: <20250401080938.32278-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé --- target/mips/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 47df563e123..269d3d69bd5 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -554,6 +554,7 @@ static const TCGCPUOps mips_tcg_ops = { .translate_code = mips_translate_code, .synchronize_from_tb = mips_cpu_synchronize_from_tb, .restore_state_to_opc = mips_restore_state_to_opc, + .mmu_index = mips_cpu_mmu_index, #if !defined(CONFIG_USER_ONLY) .tlb_fill = mips_cpu_tlb_fill, @@ -581,7 +582,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *data) &mcc->parent_phases); cc->class_by_name = mips_cpu_class_by_name; - cc->mmu_index = mips_cpu_mmu_index; cc->dump_state = mips_cpu_dump_state; cc->set_pc = mips_cpu_set_pc; cc->get_pc = mips_cpu_get_pc; From patchwork Tue Apr 1 08:09:27 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877456 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp2132121wrs; Tue, 1 Apr 2025 01:11:25 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCW6mySfW4GRd82hsCdz7T4KWGUMUXrQ2HGicv+Focqp9zqXDePMvRD6M6jDiC2bpbwcXroc0g==@linaro.org X-Google-Smtp-Source: AGHT+IESTPF30Il2SMjRSjFs/ekKtHCdY7VpIu6x05+SeXc85ojgWCFdm1De9wixwfw9rnS5BlEV X-Received: by 2002:ad4:5cc2:0:b0:6e4:3455:eba3 with SMTP id 6a1803df08f44-6eed51996e8mr162266946d6.6.1743495085724; Tue, 01 Apr 2025 01:11:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743495085; cv=none; d=google.com; s=arc-20240605; b=KjgiaSC7vaeh3WmM9NtxeYIls+blWZR+Z44LUkGbvLIj/9VXSd6K8SeoNVAT1oaNg/ DAdMOzORJZjVaja8QA2DMGdsVhfcYptF7gIAsMrMJXVW0RXjmGC87Ppu4KVqUmr4bQhQ zx6uydHlNvZTHVI4DpHJBRkfap3f4JJoGjSQ1dzhP0SsuQdfFS+zflh6x/tTE0L4P6Md 42gItlGqLqwQKFxvBbzFygAVSzH3Sb/62sOccd/18PtE1A85U6N+0YCy00lMCSzgFWEf x5LRJZ+JfvKJyJ009NmRN5Diwp2DlPV9An9nk/RotW4npH9VM0muB8cVncPWTapbzUOQ SM4g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=dvXtchFPfKjtzMUgyqA5zmnfVu8YMMkP3eOTXEU5C98=; fh=CAGeK5XzVxhZd11QbpVKk336R6CDVKo+zE/x8lNabbs=; b=BAgtNruMIv/EI9ErgnVwfjlp9l0e/8+g/4WrZEcurNTXJf+rEwFZWEl6LCAiCuxiYn PENOBX4Qc3xilJC2iIE8ofoEITUWY+CSg28Ce7cSZ/8AsENuIR6ZVyQYt3rQAXS4y3ry ERWHhXjNOUczDv0qnmsZ5Jf+tl1EbGH08awnH5+aY9AHztV4T+291so+H8/rf8vBDZn7 o4VP4ONko8Y8ZWpDTNroqzaCBE8PGc9BjsfBZzxIVZYPeGaMTwIVukuLCJ2WAjBp3uvu 0rnfCp222Epc/P78SMQGMZ53SbtHfyIW/e6xZ2kzR4dBF5SYqQ4K67lhW0xE5i03eb2T g9Hw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NPV5+lKb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d8314bbf1sm189138305e9.38.2025.04.01.01.10.48 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 01 Apr 2025 01:10:48 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Gustavo Romero , Pierrick Bouvier , Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH-for-10.1 14/24] target/openrisc: Restrict SoftMMU mmu_index() to TCG Date: Tue, 1 Apr 2025 10:09:27 +0200 Message-ID: <20250401080938.32278-15-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250401080938.32278-1-philmd@linaro.org> References: <20250401080938.32278-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé --- target/openrisc/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index e8abf1f8b5c..dc55594a7de 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -247,6 +247,7 @@ static const TCGCPUOps openrisc_tcg_ops = { .translate_code = openrisc_translate_code, .synchronize_from_tb = openrisc_cpu_synchronize_from_tb, .restore_state_to_opc = openrisc_restore_state_to_opc, + .mmu_index = openrisc_cpu_mmu_index, #ifndef CONFIG_USER_ONLY .tlb_fill = openrisc_cpu_tlb_fill, @@ -269,7 +270,6 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data) &occ->parent_phases); cc->class_by_name = openrisc_cpu_class_by_name; - cc->mmu_index = openrisc_cpu_mmu_index; cc->dump_state = openrisc_cpu_dump_state; cc->set_pc = openrisc_cpu_set_pc; cc->get_pc = openrisc_cpu_get_pc; From patchwork Tue Apr 1 08:09:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877470 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp2133613wrs; Tue, 1 Apr 2025 01:16:02 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVjSx7ssda/53mZksahRROMdqsFbPB/1XpOa/9rpLR23tKTLCEIfGRK94rF0CcyW69vOJ1NZg==@linaro.org X-Google-Smtp-Source: AGHT+IE8wKgENZi5dwFRiEGV+j4sCFtKI+7d+Rh9Jub7grHNO2G7IXbWhtS/QK+H7U/a3bqce8N0 X-Received: by 2002:a05:620a:404d:b0:7c5:6e5d:301d with SMTP id af79cd13be357-7c6862e57c3mr1558106785a.1.1743495362143; Tue, 01 Apr 2025 01:16:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743495362; cv=none; d=google.com; s=arc-20240605; b=jdtyws83nfH95TPOZcTA90/2CxK18nZHNOqfiPZe1DJqCqfMDsRIKxjxQcXbluFRDh n5zBHE0c5RDB8CpD6BNgRXNxrR7DHm0zBV+YcqwD33mYDL6oXxg+h14/8mqienwEQvAE rNCb/NPEifqXgOo1Q0R0/lv0b/MwnelO8iw51rU75n7dlTgtgOt+E64v8ODwmGyktQbQ H6O8R3PZSbe5Mi6pky1Iet1VBohiyXBZ74CHRaoZ6Bmm0ZwLgs+qOd4qzArpImcXrTiZ 3Dv6hfZv3gavVIv7xfN8NXn2XI48mEF+H9bMEZEruQnLLi3+9kHzdaAhV2Iz/r7HIe5p UJ/g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=XazkvPtQxLujQX55Abw1RSktScdF6AeI34V3jacj2nk=; fh=CAGeK5XzVxhZd11QbpVKk336R6CDVKo+zE/x8lNabbs=; b=PXaAU7nlZiH6NyTfSsYfFbYvN7o5c7NtSxwTDdbNxMjIVA+/FB8p3R0QWpyitletH0 321I8PPv7jEy4tdlDaYnYRNY0Q0Koc7BVDancctUyNYoYf3psQjXo8085JavvnK1JBVy IE5uGCGYWWtnJECxoP+/fOEOGz0s1IVlaCfXIWgEFBMR5AzZleKcX6NotZD/v80DV+R/ 7IurBlxOpCeowzOPRFFtYJIj+smOWjM6AS0JWl+bzK3kwF66Nl6Uq/rqSxcmNSif09Zf 6xCdOj8vDJPdvnU2OryW8nvR2pDtOwDZprpZqMmQ6JsZ5tu/oxPUH4XGPZlPnsfESv4Q S6Ig==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="SVqqSW+/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ea8d1673dsm13118235e9.0.2025.04.01.01.10.52 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 01 Apr 2025 01:10:53 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Gustavo Romero , Pierrick Bouvier , Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH-for-10.1 15/24] target/ppc: Restrict SoftMMU mmu_index() to TCG Date: Tue, 1 Apr 2025 10:09:28 +0200 Message-ID: <20250401080938.32278-16-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250401080938.32278-1-philmd@linaro.org> References: <20250401080938.32278-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé --- target/ppc/cpu_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 3686bbc9380..30238e9a223 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7481,6 +7481,7 @@ static const TCGCPUOps ppc_tcg_ops = { .initialize = ppc_translate_init, .translate_code = ppc_translate_code, .restore_state_to_opc = ppc_restore_state_to_opc, + .mmu_index = ppc_cpu_mmu_index, #ifdef CONFIG_USER_ONLY .record_sigsegv = ppc_cpu_record_sigsegv, @@ -7517,7 +7518,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data) &pcc->parent_phases); cc->class_by_name = ppc_cpu_class_by_name; - cc->mmu_index = ppc_cpu_mmu_index; cc->dump_state = ppc_cpu_dump_state; cc->set_pc = ppc_cpu_set_pc; cc->get_pc = ppc_cpu_get_pc; From patchwork Tue Apr 1 08:09:29 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877455 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp2132108wrs; Tue, 1 Apr 2025 01:11:24 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXLwGihloGVeeRoIF1LFGZN+JPaDBfzHQIm3TpsZ7Fj6bRGrTEJQMqbGlzItSP1qzmnOesJcg==@linaro.org X-Google-Smtp-Source: AGHT+IGfhzcqEJ+8Jo+b43wcMx73xQHD+rCLOpg/Ty29cDdGyRhyb0iIxZYTE1plhm3LiB/dhKhk X-Received: by 2002:a05:620a:2953:b0:7c5:af76:c827 with SMTP id af79cd13be357-7c69072edc7mr1699653885a.30.1743495084523; Tue, 01 Apr 2025 01:11:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743495084; cv=none; d=google.com; s=arc-20240605; b=LzmGXsaZI69rcSaHU3KmU2BrQyMh7ZyUIHmT2oEhjTWKoCXIF09308/SLa4eaHo6QW CQ4J7INfG2Oo93GKLtava6elkatylLCfK++Oy8GybITlfzvALSO7QPbJ91m/IcgCeji6 kHvd3kW9F9VdBbXKfO3YnqJJw7v5jQ90OflXIoezvkCckaDdu11O567uOViXd7xG4NbT nP5PP1MTsN0/PFwNNHRP/Sw5zoJNlhBaDUZXlWh+ljzT0VOu4HqBc0VztWt/ECRSGY48 u4YjYyW0PfowuE9pRb4VakPhLGs/keCUpgO+6+ok6x8si3O7Q86K1LDB8D5GzZ0c1mxq uE2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=tbBPJmAvAc99IgMdN0t2hESc9/XHhznc8n8w80Wh1ws=; fh=CAGeK5XzVxhZd11QbpVKk336R6CDVKo+zE/x8lNabbs=; b=CXQeYjekhaWNLkG/Dzvs2h6hcLO5uzzSB8QOsR/wmwryfizQxz/G2teH/vPlKdHnke 6nid61dkR5ZEwisegFluQcTckZm0wN3qcTm9Gm1+4k5id/JvWQqEuPqd4+XbKFudIhCy qtVQ3guCm+rrbK65qN86mLFPjQmly+EqmXc6AS08LFshrRAW82uN8bsoaUBVPS3vV+/H Po9Z974Gn8AY1Tnd1UlytFo8f9tstbRxQWXWAlMXaJdWsRNnv8t23xnPczN3jnZZrLeY a5F3UbHDmVoZsLxtk64bnVlmEgTYuvaQRs9sURkJ5Xe/IGbUXHAkLD0MdYYtGo7naGRT 90fQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="y/DytJU6"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c0b663470sm13368861f8f.27.2025.04.01.01.10.57 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 01 Apr 2025 01:10:57 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Gustavo Romero , Pierrick Bouvier , Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH-for-10.1 16/24] target/riscv: Restrict SoftMMU mmu_index() to TCG Date: Tue, 1 Apr 2025 10:09:29 +0200 Message-ID: <20250401080938.32278-17-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250401080938.32278-1-philmd@linaro.org> References: <20250401080938.32278-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Move riscv_cpu_mmu_index() to the TCG-specific file, convert CPUClass::mmu_index() to TCGCPUOps::mmu_index(). Signed-off-by: Philippe Mathieu-Daudé --- target/riscv/cpu.c | 6 ------ target/riscv/tcg/tcg-cpu.c | 6 ++++++ 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 09ded6829a2..430b02d2a58 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1021,11 +1021,6 @@ bool riscv_cpu_has_work(CPUState *cs) } #endif /* !CONFIG_USER_ONLY */ -static int riscv_cpu_mmu_index(CPUState *cs, bool ifetch) -{ - return riscv_env_mmu_index(cpu_env(cs), ifetch); -} - static void riscv_cpu_reset_hold(Object *obj, ResetType type) { #ifndef CONFIG_USER_ONLY @@ -3049,7 +3044,6 @@ static void riscv_cpu_common_class_init(ObjectClass *c, void *data) &mcc->parent_phases); cc->class_by_name = riscv_cpu_class_by_name; - cc->mmu_index = riscv_cpu_mmu_index; cc->dump_state = riscv_cpu_dump_state; cc->set_pc = riscv_cpu_set_pc; cc->get_pc = riscv_cpu_get_pc; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index e539b0266f3..710449d17e8 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -92,6 +92,11 @@ static const char *cpu_priv_ver_to_str(int priv_ver) return priv_spec_str; } +static int riscv_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + return riscv_env_mmu_index(cpu_env(cs), ifetch); +} + static void riscv_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -139,6 +144,7 @@ static const TCGCPUOps riscv_tcg_ops = { .translate_code = riscv_translate_code, .synchronize_from_tb = riscv_cpu_synchronize_from_tb, .restore_state_to_opc = riscv_restore_state_to_opc, + .mmu_index = riscv_cpu_mmu_index, #ifndef CONFIG_USER_ONLY .tlb_fill = riscv_cpu_tlb_fill, From patchwork Tue Apr 1 08:09:30 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877468 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp2133212wrs; Tue, 1 Apr 2025 01:14:56 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCX89vFbVp2YH4CTvSiPAaZlFZA98Ya9zH4KQkkgnrwiXLTPdd1ZavhDGzSyJrxS8YFijBBm9g==@linaro.org X-Google-Smtp-Source: AGHT+IHvhMqfyBnAzWwpFSiP5ISPqHS+M2FrsZLcb7oNMHWduo+bMpsBq2xq2O8wRDEzWirhnVVN X-Received: by 2002:a05:620a:468d:b0:7c5:5e05:df33 with SMTP id af79cd13be357-7c690897454mr1624342385a.51.1743495296022; Tue, 01 Apr 2025 01:14:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743495296; cv=none; d=google.com; s=arc-20240605; b=KQ5FzxQGKbXBssLEeLIa2fJmczCJwxFQfk5xYvu2ETCRrig7K0jGZeVEnkyW81jMZ9 Ld4haVIEdlvDgiDm36PAfJNMvUSaawTcHDH8RdARNmJF48LffY+b7SnRJ6NQ/eMOvBkE fwztxuUohTkP3nBSZzmIF2X6THMUacj0tMICSLeIQNxi10nxT0tZ/kbLkvXiw0Uehp/v 5lIiFLx0uLBlGDjO140s8F4c/KJRshDjby5B5Uksvh57/kbMwtYW9LoMVtMxDU9NoilG HBrXuos+gMDJeMVUB/aAfvzWjZ6D/VjbgOK0iVm95/IJPp4CdKRYPeF9JDvR19Ypr5Fy ffqQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Xf49rpCRtDiaQ+LoU13pvuqYxv6P0Zxq5lhMwhd2Njs=; fh=CAGeK5XzVxhZd11QbpVKk336R6CDVKo+zE/x8lNabbs=; b=FG6zlFZ6FQcoQ6v0QgBg4e3IABPBYOxa00X9npFaHflCaTO/0y/vzWABns71+bFC90 4U0+0UIWQGf38Hkc20t6MtiCvA11uMOomEmepl4N8dghzJaA93sbVzROVehSCEdb3wzI iC5NdHIPlVYoDjLv+n/FW3RwXihf5hp5xE3P7233fYBT9ZOVi0jU6mrufCVml4SABKEy Pit2xMPCPonLFjDx01zBWR9Pl5ntzBoXPZ+OXNOBqmSqVK8fYkFT37IvMg7KQo15WGuX sk+HLPIu8gbHRLRFah9a7RsxmCctyIDRcmITkp71IS1Vltjp0V33Tmhq4ElITs7zxARQ ERVA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WBjyI6si; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c0b7a4294sm13165846f8f.89.2025.04.01.01.11.02 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 01 Apr 2025 01:11:02 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Gustavo Romero , Pierrick Bouvier , Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH-for-10.1 17/24] target/rx: Restrict SoftMMU mmu_index() to TCG Date: Tue, 1 Apr 2025 10:09:30 +0200 Message-ID: <20250401080938.32278-18-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250401080938.32278-1-philmd@linaro.org> References: <20250401080938.32278-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=philmd@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé --- target/rx/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 723262f4b54..e14d9cbef93 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -208,6 +208,7 @@ static const TCGCPUOps rx_tcg_ops = { .translate_code = rx_translate_code, .synchronize_from_tb = rx_cpu_synchronize_from_tb, .restore_state_to_opc = rx_restore_state_to_opc, + .mmu_index = rx_cpu_mmu_index, .tlb_fill = rx_cpu_tlb_fill, .cpu_exec_interrupt = rx_cpu_exec_interrupt, @@ -228,7 +229,6 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data) &rcc->parent_phases); cc->class_by_name = rx_cpu_class_by_name; - cc->mmu_index = rx_cpu_mmu_index; cc->dump_state = rx_cpu_dump_state; cc->set_pc = rx_cpu_set_pc; cc->get_pc = rx_cpu_get_pc; From patchwork Tue Apr 1 08:09:31 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877458 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp2132197wrs; Tue, 1 Apr 2025 01:11:39 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWBUWHgkkhoOJMe3ci0WkvPO6oK2u0PLA//B0rGhiYt2xNUEhRS+jedRznyoFep7P0MrO9z6g==@linaro.org X-Google-Smtp-Source: AGHT+IGyR8qmr/tLoCrgEv8VSNns0Lc+ShnHg4gWOBAb4Ihb0UBnor8sAovzVGLiS1vP9WKeWCwj X-Received: by 2002:ac8:6656:0:b0:478:f00e:eed5 with SMTP id d75a77b69052e-478f00eeefemr46311421cf.48.1743495099310; Tue, 01 Apr 2025 01:11:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743495099; cv=none; d=google.com; s=arc-20240605; b=AoyuUBDpvOJCRsoF4q0xLCPTrb6WVEIcCm1V5Q+TYFLQDgyyats64WxBJ4U9VFDRoP mf0CtMrYaPjKiZADgs7V7RBC6DKy1wuWsJdLsjhvFkEB4aFoiIbu0phgvH8q3hXDy3kL No8h8jMegK/23u3V4ZWTkPDbqYOljadWfwoygrSS2dyy72xhYQKClD77Cg77OjQ5wa4D /i9T5ufJeRQG/6XxoNBfzeKlGiCcT9H2OMNmpbtbbtBFS66hb41rsi2OHfMDwMA+htrL az69N4CNsUv0aA6Gr0Rjr+c5M6G5tBqbcxpYJ6cD3QdDC6wCId5a0Azth3V3C3N0J1yr H+rQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=NWdRtuMa69kNKsLeJw7Q6GbvWUEnqwFnbkkmIh4OJyk=; fh=CAGeK5XzVxhZd11QbpVKk336R6CDVKo+zE/x8lNabbs=; b=dFi+hS5PP7gkayMgK2GGsSbYjgG5gGIccTlQivUpRJP8be0qzOi5a/Harjvs2kdd5z kdrRaKKocVJRj+cwf9nN5McXZKea3N6QenAIaFz15kQV02ZHrGlA69x4g9Zui126L8pn BTQBDBQ3Z97212FcuR8kUCQZI/2gRYFnfFIeeuKyKCGj7wG0IGuSfJR6LLfk/Ac11x9Q xBS2rAHXApZjg8RuXaKvqJPYhJiTAqi/WmV6hLia9om5X/ZfI2nVkHpxqxDFyCoWXJFj f8VR+YL8ECiNstIeXsS0q0cFfnXTz4pcQ+JZjwWRUFkDapx663PbQbYEzptC5af7Rm21 CHBw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="WILL9BF/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c0b7a41e8sm13639107f8f.92.2025.04.01.01.11.06 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 01 Apr 2025 01:11:07 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Gustavo Romero , Pierrick Bouvier , Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH-for-10.1 18/24] target/s390x: Restrict SoftMMU mmu_index() to TCG Date: Tue, 1 Apr 2025 10:09:31 +0200 Message-ID: <20250401080938.32278-19-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250401080938.32278-1-philmd@linaro.org> References: <20250401080938.32278-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé --- target/s390x/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 1f75629ddc2..320ace67198 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -348,6 +348,7 @@ static const TCGCPUOps s390_tcg_ops = { .initialize = s390x_translate_init, .translate_code = s390x_translate_code, .restore_state_to_opc = s390x_restore_state_to_opc, + .mmu_index = s390x_cpu_mmu_index, #ifdef CONFIG_USER_ONLY .record_sigsegv = s390_cpu_record_sigsegv, @@ -378,7 +379,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data) &scc->parent_phases); cc->class_by_name = s390_cpu_class_by_name; - cc->mmu_index = s390x_cpu_mmu_index; cc->dump_state = s390_cpu_dump_state; cc->query_cpu_fast = s390_query_cpu_fast; cc->set_pc = s390_cpu_set_pc; From patchwork Tue Apr 1 08:09:32 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877465 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp2132938wrs; Tue, 1 Apr 2025 01:13:56 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCW1qCFF/n0ftNpDBSBGcec4hn2PbLYY4MHs/J49T3qjOCHdyvDLFCguDZnb/gpOvLwMiHD+pQ==@linaro.org X-Google-Smtp-Source: AGHT+IE25jAb9asozAs1a7K3TWFGrt26eMd4r6e/bX0RDwpgtkCepOd+06+zx9QBuWTb6JpAB7de X-Received: by 2002:a05:620a:2491:b0:7c5:4278:d161 with SMTP id af79cd13be357-7c75bc6aa31mr319167485a.35.1743495236217; Tue, 01 Apr 2025 01:13:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743495236; cv=none; d=google.com; s=arc-20240605; b=N98mo9vrpFzYOXM4i3/XOO1XplexPfLDVGYtJiXr4d2SKOWRNnaPe9GovEOoSj2UcG 79HoM2SeR3b3ZS5/jLBghX1vUd1JHbFcKweigsSr4oMEbF1gy6CAO1XvWzx+Jp/cVnDr wpSXGo5YKq2EO7JxTO6D/ULdmn7NxlGKIQ4fAl3n9QYOh6C2vpU89+dMxSa6SnhZcajb irha1Rq9y4EI4OtEQXKhkh45KVoxAOlbF9bFmpZu0mSoRV8Eq1f2txGnytk3WAXiXTKZ TgJq+idQIIt2yTW0ykWXNCrj/Rov+NYBpMX0UEdk7nm+l5Z+o/fWvypYZGkST+nJTYwm zIYA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=kZ68jkJKHUSlJFLDdqHLGwkdWKmmPizBUNUJXgNfK9Y=; fh=CAGeK5XzVxhZd11QbpVKk336R6CDVKo+zE/x8lNabbs=; b=UYrlOTUr+Guiz7f3PZJXzYg0u49tXj0YBBb3uW3obO4WL/GEYvLD3DhmCVAkErGZ5U mKWD1qD4KRmfT7ElQ33xpSE4TpHM4Hh752gKYg7u0I0TlKE3HLLNgQHEINyovOZmzQaN 5EhkgKktOTkTCALJR9J+jRNm3o1jNBBo6xXLZhAfqhpP19NmsKoMv8AI9NKFhuaEwxrF 04vOfiH3DdtukFrlDh8OeFSkkWcD4KSNIoZseOD/Yh37ZktCQe7FbWzx+rNHs1TuqJY+ zryOCdGB1dz0pfrjATTHI3OoOE9pTrbaBv50PQ+P6ohrWQrB1cSpauIt71wMb8MEG3Xo 7kXA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zv1Vj+Xy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d8314bbf1sm189148775e9.38.2025.04.01.01.11.11 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 01 Apr 2025 01:11:11 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Gustavo Romero , Pierrick Bouvier , Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH-for-10.1 19/24] target/sh4: Restrict SoftMMU mmu_index() to TCG Date: Tue, 1 Apr 2025 10:09:32 +0200 Message-ID: <20250401080938.32278-20-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250401080938.32278-1-philmd@linaro.org> References: <20250401080938.32278-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philmd@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé --- target/sh4/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index ce84bdf539a..df093988cb1 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -266,6 +266,7 @@ static const TCGCPUOps superh_tcg_ops = { .translate_code = sh4_translate_code, .synchronize_from_tb = superh_cpu_synchronize_from_tb, .restore_state_to_opc = superh_restore_state_to_opc, + .mmu_index = sh4_cpu_mmu_index, #ifndef CONFIG_USER_ONLY .tlb_fill = superh_cpu_tlb_fill, @@ -291,7 +292,6 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data) &scc->parent_phases); cc->class_by_name = superh_cpu_class_by_name; - cc->mmu_index = sh4_cpu_mmu_index; cc->dump_state = superh_cpu_dump_state; cc->set_pc = superh_cpu_set_pc; cc->get_pc = superh_cpu_get_pc; From patchwork Tue Apr 1 08:09:33 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877460 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp2132283wrs; Tue, 1 Apr 2025 01:11:56 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUQYm/hlLS3tp2mLZR2vtnssl1qHc6bvyBe5EhpG1F72EWpitIwv3Ha88/M/oZOZM2uUumYnw==@linaro.org X-Google-Smtp-Source: AGHT+IHwy1nxhpMeFaBFbauZA+ISmglOshzuRG/USrv/BSpS7kc6jedegOz8Q++NZxpk0PRI27VJ X-Received: by 2002:a05:6214:c42:b0:6d1:7433:3670 with SMTP id 6a1803df08f44-6eed5f96d4fmr186300466d6.4.1743495116077; Tue, 01 Apr 2025 01:11:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743495116; cv=none; d=google.com; s=arc-20240605; b=jIXmY7MaZcpLBv1zQvGsbhQUQyzhY2cbkFc2DDDPfbej8OK7+i9IWdR3XrpKYfvJ/y 4eJyUtIYDRuopPW8cFljBQFQ4aPOEyAVJn/9dkVfl7lkvVxuROEHsqIF0SS0ORahJSKb C4Yb0qBjvYr2LUlZfimy6LAjDc/iL7J9JFz04g5qjV6DPVDe/G8jRm1BfyBz5yOmD9wa gogRIHpbeDDq6cUOf5KqtggMlQ3M50GozdqDxe924L4N6wieArPXVFGO8KxaHJmqPB4Y ER6gApmt1oUrN54M5OR3BWpSJ7bl7evUka+GVeRWvkjSN+7k4Xn7qkcU2Q4IT9sQa1P3 SdSw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=cdg2DA89NBw+OvEyUtqbsHb6LnvnVL3Tl7petd+Rj5I=; fh=CAGeK5XzVxhZd11QbpVKk336R6CDVKo+zE/x8lNabbs=; b=KclOdp4908JlAY5YVV+wy11wTtYAc3rvsq3jad9IBoL66PdbkHIYtj04nTz7x0Z11w OSWNXkxo1p5CoyYrShnGKTihPsjh4eRt6k+KMtOyVzB4Yqwa0e4hO/MpbcmmErXn9/d6 OuoFNZoTRhEDZsETAPj/tiqD2o85oglFngwG0GYotQO1hU0FUvB4B5ukiKWA1Ulc5b40 2wQKqdhpUlT6WLes3LaIdrs3V+pGqziuakQqX74oNy/xwteXhI9NGlR4eqLSDvB0FT0A RhRMqwwbJVS7x+UCI2A6bEt0/FNDiOi7kfBGj2K+X/B9KqRoCmKqSNCqeRW0CI8/62+d yHQw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XNEjoWk1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ea8d1673dsm13126475e9.0.2025.04.01.01.11.16 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 01 Apr 2025 01:11:16 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Gustavo Romero , Pierrick Bouvier , Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH-for-10.1 20/24] target/sparc: Restrict SoftMMU mmu_index() to TCG Date: Tue, 1 Apr 2025 10:09:33 +0200 Message-ID: <20250401080938.32278-21-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250401080938.32278-1-philmd@linaro.org> References: <20250401080938.32278-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé --- target/sparc/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 1bf00407af7..072d5da5736 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -1005,6 +1005,7 @@ static const TCGCPUOps sparc_tcg_ops = { .translate_code = sparc_translate_code, .synchronize_from_tb = sparc_cpu_synchronize_from_tb, .restore_state_to_opc = sparc_restore_state_to_opc, + .mmu_index = sparc_cpu_mmu_index, #ifndef CONFIG_USER_ONLY .tlb_fill = sparc_cpu_tlb_fill, @@ -1033,7 +1034,6 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = sparc_cpu_class_by_name; cc->parse_features = sparc_cpu_parse_features; - cc->mmu_index = sparc_cpu_mmu_index; cc->dump_state = sparc_cpu_dump_state; #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) cc->memory_rw_debug = sparc_cpu_memory_rw_debug; From patchwork Tue Apr 1 08:09:34 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877471 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp2133612wrs; Tue, 1 Apr 2025 01:16:02 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCV/jZgyyTt3g/uzLOpbqH85wJx2XEU/ixNf2h3Ue6O1K8JWS4cy/0+CuntZEiEQc9jt/7UB0w==@linaro.org X-Google-Smtp-Source: AGHT+IGLRIGW3AsffgnXc8RQ8/A/n/I/q7BqI974K00GIi2CM1+U/N52wi41LevCONyimRUAP7+E X-Received: by 2002:a05:622a:1820:b0:476:980c:109f with SMTP id d75a77b69052e-477e4b69912mr158199101cf.19.1743495361973; Tue, 01 Apr 2025 01:16:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743495361; cv=none; d=google.com; s=arc-20240605; b=Yoy/ebNKXFjhcfLY9DNsheUJ/1qhVrg0HKCw7Sc8dDYAeo8Sqeq8iXKjw7UjOUEGGn 8bW0LDRL9zU6sSG4KLhCM3bxBskI3toaJ2wFx2YjdhxAQbpmJzy6oAh/dmLP54Ke3fo8 CeLwmJab08RMO5PCSiYvzWXge5APODxBNUFLKfuboRhB20ucAGpqJW3Z/LVewujoa8YD 5vOrAr5pnIm726MvBUWNjDohsp+imZDQQzC2cL/xY51lNIJr+M91bxqNYbDhg3yyKxqL Ls43O/gJth6Wd58Ut68+WoiJzoLH6Po96EOUuWkU3ZAAEGGpjxEeQdTEucTGPjkmb/z/ e3WQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Jp1FKYkXGpdKTDVVOvTyK7ETPKiPrk5iqOmg0nQYNOs=; fh=CAGeK5XzVxhZd11QbpVKk336R6CDVKo+zE/x8lNabbs=; b=XEsacPiyFRihSZuPJwsYivw+GiYq/u7x4w86yPVplpEOH9c6q4tXbMX00sHK7ZdXVB Y7n60UPPzJrU6KHeqm38T2HcnjznJ44xJ2vqfQAeS2A/TlFvxHr7ertOe4o2PpZYLDKv Vf6Qw/jEl5Qye0OgTQbFqBXpj0UKs48mfBWcSXjKvPYCgp2d/0wu+kDhp9ckNEOsU6M/ hcH1bMjT3yfyMuT7IrfxRUSDvKNxm23f2ljqh5SH6pU8//8YwDDr2Gj25eF2fXabVxP+ mzrwFdKElBi/ZgaaXXHFDTUlV1yrX6czSbEpfr6jsFvLmQx6lAEjDER+BsEcxU5jUMwS Ab9A==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZW9uhZ7z; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d82a041d4sm196289745e9.0.2025.04.01.01.11.20 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 01 Apr 2025 01:11:21 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Gustavo Romero , Pierrick Bouvier , Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH-for-10.1 21/24] target/tricore: Restrict SoftMMU mmu_index() to TCG Date: Tue, 1 Apr 2025 10:09:34 +0200 Message-ID: <20250401080938.32278-22-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250401080938.32278-1-philmd@linaro.org> References: <20250401080938.32278-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé --- target/tricore/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 16acc4ecb92..833a93d37af 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -176,6 +176,7 @@ static const TCGCPUOps tricore_tcg_ops = { .translate_code = tricore_translate_code, .synchronize_from_tb = tricore_cpu_synchronize_from_tb, .restore_state_to_opc = tricore_restore_state_to_opc, + .mmu_index = tricore_cpu_mmu_index, .tlb_fill = tricore_cpu_tlb_fill, .cpu_exec_interrupt = tricore_cpu_exec_interrupt, .cpu_exec_halt = tricore_cpu_has_work, @@ -194,7 +195,6 @@ static void tricore_cpu_class_init(ObjectClass *c, void *data) resettable_class_set_parent_phases(rc, NULL, tricore_cpu_reset_hold, NULL, &mcc->parent_phases); cc->class_by_name = tricore_cpu_class_by_name; - cc->mmu_index = tricore_cpu_mmu_index; cc->gdb_read_register = tricore_cpu_gdb_read_register; cc->gdb_write_register = tricore_cpu_gdb_write_register; From patchwork Tue Apr 1 08:09:35 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877464 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp2132415wrs; Tue, 1 Apr 2025 01:12:27 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUUa2cqkXbxc/2symnTfe2Mht4ljriNshp0FXqBRhtAllle46ylPgJtVjsSNmlJ/6FE73270g==@linaro.org X-Google-Smtp-Source: AGHT+IH+4JbZoJtreHg2D+CO6M9pB1kSoAdPy9NGfy1wzEfEuixETjsbw8QFsgn9BDg+nawL3KGi X-Received: by 2002:a05:620a:1919:b0:7c5:6a66:5c1e with SMTP id af79cd13be357-7c6908a6c71mr1617790585a.58.1743495147416; Tue, 01 Apr 2025 01:12:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743495147; cv=none; d=google.com; s=arc-20240605; b=Qxs5jojqOofgi5x3wGM8NfF9kaxBQCKMiLFYebANjIqkGH1NsCZ7qhtAQSgZ317iTA zJWr1kYZLitobCcrvzn1ErPyn/JI6HPpJAWegS9GIAkprkeLnuuXvxB0JOeDnjclcm7t nsHbxETDcwqjxZCoThzIjlyiQ1/QnClN14LspIu9LxEWSruLnHtS/Z1TfQ+7gUS97ND4 3+y7Bj9m5yQet84US5YgvNym+MSTX/sbmJt1FC4YfCejEKw15AsyLngNKhX5kkgLGjJA DJzrpVsMPTviKRGZNK1XCh51jW34DJsRc/dY4Mg0c/YNzDjzXznb1H8DJ/JWiqq8FPNb gpbw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=f8ZPKPo3p91JZQi+uwfwY+X5hjgCllMtU8DHnaPsIEE=; fh=CAGeK5XzVxhZd11QbpVKk336R6CDVKo+zE/x8lNabbs=; b=LLsqx/h0A320zELsa0EUn0xIkMYutmqfvStzXSjH3Uo7RPCBdu61IPnDL0/aqerAOE Vo7BQooRn2pIm87UrUj2kuTURVH8lXCt+r7TxH0fDSR9hZJcwB0vbOMyQxJOGn9i714m klEwgLKDAPKg2Y6C50GiI09GZDFGiNw/lqvfHFRVMPn3kHgq/8iZe4ZQwV1IKBJeE5Yd hu8PhSPD8SDVl43HqqwgZanturuF7SIMdEt3Xn5iI/vg7lpbzmwEJd46pRUSmpX1E8/b 406mNeH5fe0iid1GHFQKD7ikdLkJsnGOwJ9DhGrTycGvejfHNu0YXhxuM5hvSHF9wvOn It5Q==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EYIJtxl6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c0b6588dbsm13230327f8f.2.2025.04.01.01.11.25 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 01 Apr 2025 01:11:26 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Gustavo Romero , Pierrick Bouvier , Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH-for-10.1 22/24] target/xtensa: Restrict SoftMMU mmu_index() to TCG Date: Tue, 1 Apr 2025 10:09:35 +0200 Message-ID: <20250401080938.32278-23-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250401080938.32278-1-philmd@linaro.org> References: <20250401080938.32278-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé --- target/xtensa/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index ec6a0a8b662..51f9ee9e89a 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -236,6 +236,7 @@ static const TCGCPUOps xtensa_tcg_ops = { .translate_code = xtensa_translate_code, .debug_excp_handler = xtensa_breakpoint_handler, .restore_state_to_opc = xtensa_restore_state_to_opc, + .mmu_index = xtensa_cpu_mmu_index, #ifndef CONFIG_USER_ONLY .tlb_fill = xtensa_cpu_tlb_fill, @@ -262,7 +263,6 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data) &xcc->parent_phases); cc->class_by_name = xtensa_cpu_class_by_name; - cc->mmu_index = xtensa_cpu_mmu_index; cc->dump_state = xtensa_cpu_dump_state; cc->set_pc = xtensa_cpu_set_pc; cc->get_pc = xtensa_cpu_get_pc; From patchwork Tue Apr 1 08:09:36 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877459 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp2132252wrs; Tue, 1 Apr 2025 01:11:50 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVRF/oKWvM9Mqax3NselOJ2DpcWOI5n+JW4H9Sn1zWiTyjXaU7hHWQxWOVfYv2LCnzAf/LyTw==@linaro.org X-Google-Smtp-Source: AGHT+IHZkRLBNFRXVu8gm5twSvlPlE0nxNTf2Ww303/lU4FAoO/+MWxFzUMqnenN59wp91xW5/0T X-Received: by 2002:ac8:5a44:0:b0:476:9847:7c73 with SMTP id d75a77b69052e-477ed80ba98mr157244241cf.26.1743495110130; Tue, 01 Apr 2025 01:11:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743495110; cv=none; d=google.com; s=arc-20240605; b=WjqfDlQB9VjFYSxRo1qPTWbWEde8Yl3SRO2xwgP8KYLgaaCua79Xe9A/MnaLXPyChz Vw84PCvpHdj8pnL5y1apo+VWvWDZQ0mInVqdYhRJWtfnU5Y/EW6UymyeW40UTgQxxI8w fwFVTgUymDwmveAhqwJ4OPiWbTwyQv3RczuuPI+pQ5zbQc48oet1XzvmuMCi8bApEcA6 uwIBtAxDvapP5+JyDqq+9UNZ0OT6czJJf8i/4pOVF54pZeEQEYjK/l6Lv901uwjlhoRY vLRF4A42TREoKxH9+/vTLOpayNGfbd6WRAWMyXo9JytIFOCRPZ1a5lR3HCK8wjaCKBnp iY7A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=xFyvhroy74MCVS8YFBdiJPFNhSZTwEwf1bl1oXT/Waw=; fh=CAGeK5XzVxhZd11QbpVKk336R6CDVKo+zE/x8lNabbs=; b=AxuAQOec77F0VQ+d3Dv3FwNsc58wdhvqZIxj6RGD1ecnBL1kv2DyKrvo2avYSxyT7e ucLEGZCi3TFuP5qhakpsixV5myXSMYdhvclidxFX1pC3h1+Rb32OYoIjBI2OVaTa6bU8 QNj771sogE4BBgg47QINmUfBsKKFY/qqiOAYVb2Smd0C2cpL+rcfV/WU6L2Lm8iLY4pZ IWMMX8bd0VOK1V6ix7J9yvTL5vFSW+P7Vc8Kjnlw3D594x1qvNedg9BfwT7KvU7biiSJ 4lRJHxP+EnqrUuCQ184AisBzM59MZV2cpyMFkUDbBe1ik4etF7NxZvd9uyAyoKicAZyV 0qUQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gke2AiFX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c0b7a8e0asm13315116f8f.101.2025.04.01.01.11.30 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 01 Apr 2025 01:11:30 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Gustavo Romero , Pierrick Bouvier , Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH-for-10.1 23/24] hw/core/cpu: Remove CPUClass::mmu_index() Date: Tue, 1 Apr 2025 10:09:36 +0200 Message-ID: <20250401080938.32278-24-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250401080938.32278-1-philmd@linaro.org> References: <20250401080938.32278-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org All targets have been converted to TCGCPUOps::mmu_index(), remove the now unused CPUClass::mmu_index(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/exec/cpu-mmu-index.h | 4 +--- include/hw/core/cpu.h | 2 -- 2 files changed, 1 insertion(+), 5 deletions(-) diff --git a/include/exec/cpu-mmu-index.h b/include/exec/cpu-mmu-index.h index 651526e9f97..a87b6f7c4b7 100644 --- a/include/exec/cpu-mmu-index.h +++ b/include/exec/cpu-mmu-index.h @@ -32,9 +32,7 @@ static inline int cpu_mmu_index(CPUState *cs, bool ifetch) # endif #endif - const TCGCPUOps *tcg_ops = cs->cc->tcg_ops; - int ret = tcg_ops->mmu_index ? tcg_ops->mmu_index(cs, ifetch) - : cs->cc->mmu_index(cs, ifetch); + int ret = cs->cc->tcg_ops->mmu_index(cs, ifetch); tcg_debug_assert(ret >= 0 && ret < NB_MMU_MODES); return ret; } diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 60b7abaf49b..10b6b25b344 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -104,7 +104,6 @@ struct SysemuCPUOps; * instantiatable CPU type. * @parse_features: Callback to parse command line arguments. * @reset_dump_flags: #CPUDumpFlags to use for reset logging. - * @mmu_index: Callback for choosing softmmu mmu index. * @memory_rw_debug: Callback for GDB memory access. * @dump_state: Callback for dumping state. * @query_cpu_fast: @@ -151,7 +150,6 @@ struct CPUClass { ObjectClass *(*class_by_name)(const char *cpu_model); void (*parse_features)(const char *typename, char *str, Error **errp); - int (*mmu_index)(CPUState *cpu, bool ifetch); int (*memory_rw_debug)(CPUState *cpu, vaddr addr, uint8_t *buf, size_t len, bool is_write); void (*dump_state)(CPUState *cpu, FILE *, int flags); From patchwork Tue Apr 1 08:09:37 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877467 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp2133192wrs; Tue, 1 Apr 2025 01:14:52 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXGKydTAh6qlpi3uOLTbkaIgIPNeVoyfbArP434GXEGonkMLUBp26d3BAcRM1np1BIU0AJyDQ==@linaro.org X-Google-Smtp-Source: AGHT+IG0EpL0dnUFZiwn6dfqERistn26Jdm9tE+7jWFCwhRXuwTotOTxmMJaKCz/XO0vW7ejPLui X-Received: by 2002:a05:6214:21cb:b0:6e8:86d3:be73 with SMTP id 6a1803df08f44-6eed62b3586mr234086366d6.37.1743495292451; Tue, 01 Apr 2025 01:14:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743495292; cv=none; d=google.com; s=arc-20240605; b=FlWLVHDhrr99njIK/RkbcZV8C+En18j8IlSO0NnIiLZsa2VwcJJrYRw6TBu7f1lDG0 FBsPwwJ2cPfTmQo7nVIONGpbeq48jgoDOOpaHYmgTyNusYQDzm7Pi11+hYLeSb0h5ScG gewjhBRmkgiITv6lmR0YigG1fF8gmD4vJ1NMR9QHS7GR0ylYZ2NAUj7Pvplbb9n89gqc xM93BGQNxonhFbWXTlqDxQQFCu5RFCDEkzdw/NRR1vlRJtvB94tbuMK9UBVEcMM0ubZg hV0ZNRgixgqp988f2DpKDOWmfuR3Pyzk0wJoUIIYHhz0K/eaGYTvzsW8vzYM7620qn7n CM3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Jpgz3OtVHhFfAhVmnuMWKFfUOyUSx9BejJG8YbABqHQ=; fh=CAGeK5XzVxhZd11QbpVKk336R6CDVKo+zE/x8lNabbs=; b=d240Kilt4/8vMYHJJ0LigbIxTwK2Skse3uK9QTfq6AuMr5A6aOUYjLCPe604SnKoa2 kZuj41SrsOaachmNUYxQS3JiMjFQgqbXwu2xzAaJmjDVvp53FCErxiCejSTf1y1muDMZ /nSMbP7OOJXOjTLjetuBC+cTrKMmNNyx300dzs6KBYUIUeF3CVppg+H/pAJfUBvFrMlM xkIKWtX4dl44KrxDRFCRNd4/RbsBlGVSCxog7NaHOEmRnMlVwKYzOjEyLWuOAtVzCmG/ lpQIK/8PaWOGfiEBmUANjPBDOkEE/oVo/IwR+ODLuc7SPWvY1Cr7Mmkyu4X5lgMzC8VK tnwA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZYfjq95W; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d8fba3ef1sm153088175e9.2.2025.04.01.01.11.35 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 01 Apr 2025 01:11:35 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Gustavo Romero , Pierrick Bouvier , Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH-for-10.1 24/24] exec: Restrict cpu-mmu-index.h to accel/tcg/ Date: Tue, 1 Apr 2025 10:09:37 +0200 Message-ID: <20250401080938.32278-25-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250401080938.32278-1-philmd@linaro.org> References: <20250401080938.32278-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé --- include/{exec => accel/tcg}/cpu-mmu-index.h | 6 +++--- include/exec/cpu_ldst.h | 2 +- accel/tcg/translator.c | 2 +- semihosting/uaccess.c | 2 +- target/arm/gdbstub64.c | 2 +- target/hppa/mem_helper.c | 2 +- target/i386/tcg/translate.c | 2 +- target/loongarch/cpu_helper.c | 2 +- target/microblaze/helper.c | 2 +- target/microblaze/mmu.c | 2 +- target/openrisc/translate.c | 2 +- target/sparc/cpu.c | 2 +- target/sparc/mmu_helper.c | 2 +- target/tricore/helper.c | 2 +- target/xtensa/mmu_helper.c | 2 +- 15 files changed, 17 insertions(+), 17 deletions(-) rename include/{exec => accel/tcg}/cpu-mmu-index.h (87%) diff --git a/include/exec/cpu-mmu-index.h b/include/accel/tcg/cpu-mmu-index.h similarity index 87% rename from include/exec/cpu-mmu-index.h rename to include/accel/tcg/cpu-mmu-index.h index a87b6f7c4b7..3699c18b4cb 100644 --- a/include/exec/cpu-mmu-index.h +++ b/include/accel/tcg/cpu-mmu-index.h @@ -6,8 +6,8 @@ * SPDX-License-Identifier: LGPL-2.1-or-later */ -#ifndef EXEC_CPU_MMU_INDEX_H -#define EXEC_CPU_MMU_INDEX_H +#ifndef ACCEL_TCG_CPU_MMU_INDEX_H +#define ACCEL_TCG_CPU_MMU_INDEX_H #include "hw/core/cpu.h" #include "accel/tcg/cpu-ops.h" @@ -37,4 +37,4 @@ static inline int cpu_mmu_index(CPUState *cs, bool ifetch) return ret; } -#endif /* EXEC_CPU_MMU_INDEX_H */ +#endif /* ACCEL_TCG_CPU_MMU_INDEX_H */ diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 313100fcda1..63847f6e618 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -68,7 +68,7 @@ #include "exec/cpu-common.h" #include "exec/cpu-ldst-common.h" -#include "exec/cpu-mmu-index.h" +#include "accel/tcg/cpu-mmu-index.h" #include "exec/abi_ptr.h" #if defined(CONFIG_USER_ONLY) diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index 36a6a9e0408..c53bbdef99f 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -12,7 +12,7 @@ #include "qemu/log.h" #include "qemu/error-report.h" #include "exec/cpu-ldst-common.h" -#include "exec/cpu-mmu-index.h" +#include "accel/tcg/cpu-mmu-index.h" #include "exec/target_page.h" #include "exec/translator.h" #include "exec/plugin-gen.h" diff --git a/semihosting/uaccess.c b/semihosting/uaccess.c index 92b2421dce5..81ffecaaba4 100644 --- a/semihosting/uaccess.c +++ b/semihosting/uaccess.c @@ -8,7 +8,7 @@ */ #include "qemu/osdep.h" -#include "exec/cpu-mmu-index.h" +#include "accel/tcg/cpu-mmu-index.h" #include "exec/exec-all.h" #include "exec/target_page.h" #include "exec/tlb-flags.h" diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 3bbca4cbb98..64ee9b3b567 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -28,7 +28,7 @@ #include "mte_user_helper.h" #endif #ifdef CONFIG_TCG -#include "exec/cpu-mmu-index.h" +#include "accel/tcg/cpu-mmu-index.h" #include "exec/target_page.h" #endif diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index df4e35f4de6..554d7bf4d14 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -22,7 +22,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "exec/cputlb.h" -#include "exec/cpu-mmu-index.h" +#include "accel/tcg/cpu-mmu-index.h" #include "exec/page-protection.h" #include "exec/target_page.h" #include "exec/helper-proto.h" diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 7e6d1ef9379..ca49f8d6dcb 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -20,7 +20,7 @@ #include "qemu/host-utils.h" #include "cpu.h" -#include "exec/cpu-mmu-index.h" +#include "accel/tcg/cpu-mmu-index.h" #include "exec/exec-all.h" #include "exec/translation-block.h" #include "tcg/tcg-op.h" diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c index 4597e29b153..bb343078bf7 100644 --- a/target/loongarch/cpu_helper.c +++ b/target/loongarch/cpu_helper.c @@ -8,7 +8,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/cpu-mmu-index.h" +#include "accel/tcg/cpu-mmu-index.h" #include "exec/target_page.h" #include "internals.h" #include "cpu-csr.h" diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 9e6969ccc9a..92031924830 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -21,7 +21,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/cputlb.h" -#include "exec/cpu-mmu-index.h" +#include "accel/tcg/cpu-mmu-index.h" #include "exec/page-protection.h" #include "exec/target_page.h" #include "qemu/host-utils.h" diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c index 7f20c4e4c69..95a12e16f8e 100644 --- a/target/microblaze/mmu.c +++ b/target/microblaze/mmu.c @@ -22,7 +22,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/cputlb.h" -#include "exec/cpu-mmu-index.h" +#include "accel/tcg/cpu-mmu-index.h" #include "exec/page-protection.h" #include "exec/target_page.h" diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 4a8e203cf88..d4ce60188bd 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/cpu-mmu-index.h" +#include "accel/tcg/cpu-mmu-index.h" #include "exec/exec-all.h" #include "tcg/tcg-op.h" #include "qemu/log.h" diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 072d5da5736..af3cec43e78 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -22,7 +22,7 @@ #include "cpu.h" #include "qemu/module.h" #include "qemu/qemu-print.h" -#include "exec/cpu-mmu-index.h" +#include "accel/tcg/cpu-mmu-index.h" #include "exec/exec-all.h" #include "exec/translation-block.h" #include "hw/qdev-properties.h" diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index b3351eebd0a..217580a4d8c 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -21,7 +21,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/cputlb.h" -#include "exec/cpu-mmu-index.h" +#include "accel/tcg/cpu-mmu-index.h" #include "exec/page-protection.h" #include "exec/target_page.h" #include "exec/tlb-flags.h" diff --git a/target/tricore/helper.c b/target/tricore/helper.c index a5ae5bcb619..e4c53d453dd 100644 --- a/target/tricore/helper.c +++ b/target/tricore/helper.c @@ -20,7 +20,7 @@ #include "hw/registerfields.h" #include "cpu.h" #include "exec/cputlb.h" -#include "exec/cpu-mmu-index.h" +#include "accel/tcg/cpu-mmu-index.h" #include "exec/page-protection.h" #include "exec/target_page.h" #include "fpu/softfloat-helpers.h" diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c index 45601a4b850..a7dd8100555 100644 --- a/target/xtensa/mmu_helper.c +++ b/target/xtensa/mmu_helper.c @@ -33,7 +33,7 @@ #include "exec/helper-proto.h" #include "qemu/host-utils.h" #include "exec/cputlb.h" -#include "exec/cpu-mmu-index.h" +#include "accel/tcg/cpu-mmu-index.h" #include "exec/exec-all.h" #include "exec/page-protection.h" #include "exec/target_page.h"