From patchwork Fri Apr 4 02:59:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring \(Arm\)" X-Patchwork-Id: 878538 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 75A8C4315A; Fri, 4 Apr 2025 02:59:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743735582; cv=none; b=rry8xRT6GOb4tg5bx0Ieg5l+sKnUaiB/8wuIV/QDzAR+QSEcu+Kwxkty2dYOGRbzgCy3YRzXEUq4DQfUPAnUXJds4aoH2qbm4Jf+3GgETrsiGV0DJsppfhWAhDgFKANKSLHoqsdinaYzwBOnAGPgem8vC+M9GqkasUIbWZ0yykE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743735582; c=relaxed/simple; bh=5rtDQ0pe7WShvacxxNJLUqvyINRo/AXE5vD1stW6jE8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=E2GmcHzQOr8EXL/QFtI90QujtX5m8SrQNKiTEkJiKA14r+PKdlN1fIBZhx+20FyAivBLvwqyr/5+qbBgjQk3XwRg/uyKScPXFnGRvoVzFIfnpAbiA6EEjDcgIG0oNySuj+2WGBNULE+LVA1bo2oRzosJnI9GAaP8L0Cdxq3HJt0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=RiI7QF4Q; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="RiI7QF4Q" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A9EE0C4CEE7; Fri, 4 Apr 2025 02:59:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1743735581; bh=5rtDQ0pe7WShvacxxNJLUqvyINRo/AXE5vD1stW6jE8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=RiI7QF4QKTnEWoFPph74b7vTTM/C0H5U/et9pNcxSlU59KyGPZFNV+brPyXwaepz9 KLVDwu3w2hDzi/J6nmwnrAUCMbyIJUNguH4ZwmXy7GY3k34plvSw0apXzHjtbL/JiB fHNKWkKHWfVX6kKZAkXCeaCuVd3YVWKwvmfjXf+eCSUKsqRLiSyyjTzKvwC48Fgl/N 66plYdx2J+E8uU09r4TVAJ84N2SBEaXKVQQscPog8/6dDfqp2eL2fR2J2DXkp7XQC5 VoVJj3czjxbBwKonugcBm3JgGhq2hncnAlD4K3x2D04gPtAliniMLLFtRSWpExAY+v iavi1HrZP7Thg== From: "Rob Herring (Arm)" Date: Thu, 03 Apr 2025 21:59:22 -0500 Subject: [PATCH 01/19] arm64: dts: allwinner: h5/h6: Drop spurious 'clock-latency-ns' properties Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250403-dt-cpu-schema-v1-1-076be7171a85@kernel.org> References: <20250403-dt-cpu-schema-v1-0-076be7171a85@kernel.org> In-Reply-To: <20250403-dt-cpu-schema-v1-0-076be7171a85@kernel.org> To: Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , "Rafael J. Wysocki" , Viresh Kumar , Matthias Brugger , AngeloGioacchino Del Regno , Vincenzo Frascino , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Bjorn Andersson , Konrad Dybcio , Thomas Bogendoerfer , Viresh Kumar , Nishanth Menon , Stephen Boyd , zhouyanjie@wanyeetech.com, Conor Dooley , Nicolas Ferre , Claudiu Beznea , Steen Hegelund , Daniel Machon , UNGLinuxDriver@microchip.com, Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Heiko Stuebner , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Geert Uytterhoeven , Magnus Damm Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-mips@vger.kernel.org, imx@lists.linux.dev, linux-rockchip@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-renesas-soc@vger.kernel.org X-Mailer: b4 0.15-dev 'clock-latency-ns' is not a valid property for CPU nodes. It belongs in OPP table (which has it). Drop them from the CPU nodes. Signed-off-by: Rob Herring (Arm) --- arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 4 ---- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 4 ---- 2 files changed, 8 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi index d3caf27b6a55..48802bf02f3b 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi @@ -16,7 +16,6 @@ cpu0: cpu@0 { reg = <0>; enable-method = "psci"; clocks = <&ccu CLK_CPUX>; - clock-latency-ns = <244144>; /* 8 32k periods */ #cooling-cells = <2>; }; @@ -26,7 +25,6 @@ cpu1: cpu@1 { reg = <1>; enable-method = "psci"; clocks = <&ccu CLK_CPUX>; - clock-latency-ns = <244144>; /* 8 32k periods */ #cooling-cells = <2>; }; @@ -36,7 +34,6 @@ cpu2: cpu@2 { reg = <2>; enable-method = "psci"; clocks = <&ccu CLK_CPUX>; - clock-latency-ns = <244144>; /* 8 32k periods */ #cooling-cells = <2>; }; @@ -46,7 +43,6 @@ cpu3: cpu@3 { reg = <3>; enable-method = "psci"; clocks = <&ccu CLK_CPUX>; - clock-latency-ns = <244144>; /* 8 32k periods */ #cooling-cells = <2>; }; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index 2301c59b41b1..73e8604315c5 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -27,7 +27,6 @@ cpu0: cpu@0 { reg = <0>; enable-method = "psci"; clocks = <&ccu CLK_CPUX>; - clock-latency-ns = <244144>; /* 8 32k periods */ #cooling-cells = <2>; i-cache-size = <0x8000>; i-cache-line-size = <64>; @@ -44,7 +43,6 @@ cpu1: cpu@1 { reg = <1>; enable-method = "psci"; clocks = <&ccu CLK_CPUX>; - clock-latency-ns = <244144>; /* 8 32k periods */ #cooling-cells = <2>; i-cache-size = <0x8000>; i-cache-line-size = <64>; @@ -61,7 +59,6 @@ cpu2: cpu@2 { reg = <2>; enable-method = "psci"; clocks = <&ccu CLK_CPUX>; - clock-latency-ns = <244144>; /* 8 32k periods */ #cooling-cells = <2>; i-cache-size = <0x8000>; i-cache-line-size = <64>; @@ -78,7 +75,6 @@ cpu3: cpu@3 { reg = <3>; enable-method = "psci"; clocks = <&ccu CLK_CPUX>; - clock-latency-ns = <244144>; /* 8 32k periods */ #cooling-cells = <2>; i-cache-size = <0x8000>; i-cache-line-size = <64>; From patchwork Fri Apr 4 02:59:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring \(Arm\)" X-Patchwork-Id: 878375 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E81B8149E17; Fri, 4 Apr 2025 02:59:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743735584; cv=none; b=bsPWlCa/qHC/QpeGh/7dNnrara+DWPat5CgysTEbrvu4HdOFZPOx7ciXrVIGKuwJHPA+ukdv43obWLorZM3t9wp1W5sMNHp8qsJ0rxZSiuvAtW4nHTpITBsXh2VtVA11G3V4IaiyqwtPvxQ0z7ikhcg1lDD44H1W/Q1McadeqDc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743735584; c=relaxed/simple; bh=BFNG9yNPBQp7lePtcF6xD0SGvnVh48+ACatG3ueW7Nc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ndkbzm/yf17XGrYIrf/jhMl/aKBzHGI9U9B6bA+Ac8JT21uQi1TPcXK+lMBXDeaGZ6GE9nIraxkglIzDc4HYT9XfeUo6TWkBbehiDiZfkc3/6rOfMlzG025xll8xN3QEJBvo+xdZY6A7EIXHVegleRuLr86OCsNNbeOrKz3OlHM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=VJ0e7SAx; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="VJ0e7SAx" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0DBB4C4CEF9; Fri, 4 Apr 2025 02:59:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1743735583; bh=BFNG9yNPBQp7lePtcF6xD0SGvnVh48+ACatG3ueW7Nc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=VJ0e7SAxLo+dcCqV1y3fiUbeOj8nzMsubkIcSK61bhYmhFqk2usnd0d5OPi7EKFdM DRyI+aUiub90+OB8O8n9WkGNHSq5XjDhMNm+jODyHcVHCh8hI7SogIEa2XHIKBVbw8 6tHA5u923suAWQtSIIk/r+qK55kVswhMUDnDMPy8x6G2h1iJ6myNUFghF4bIy9SHk7 1uL3lBV9f3bS0qy+RIFP3V8Bnxf3aItkKniTAn6Dhy/J/vRlG5X3AfYwDnSpkSqKXZ 5Fe4SyAA72tc2gCFbxbhmwKehbH+Di1xzgWfn9O8OHHZMPggV0LnlKOpky195Gw6O8 kIqHaQHcEPOZg== From: "Rob Herring (Arm)" Date: Thu, 03 Apr 2025 21:59:23 -0500 Subject: [PATCH 02/19] arm64: dts: broadcom: bcm2712: Use "l2-cache" for L2 cache node names Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250403-dt-cpu-schema-v1-2-076be7171a85@kernel.org> References: <20250403-dt-cpu-schema-v1-0-076be7171a85@kernel.org> In-Reply-To: <20250403-dt-cpu-schema-v1-0-076be7171a85@kernel.org> To: Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , "Rafael J. Wysocki" , Viresh Kumar , Matthias Brugger , AngeloGioacchino Del Regno , Vincenzo Frascino , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Bjorn Andersson , Konrad Dybcio , Thomas Bogendoerfer , Viresh Kumar , Nishanth Menon , Stephen Boyd , zhouyanjie@wanyeetech.com, Conor Dooley , Nicolas Ferre , Claudiu Beznea , Steen Hegelund , Daniel Machon , UNGLinuxDriver@microchip.com, Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Heiko Stuebner , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Geert Uytterhoeven , Magnus Damm Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-mips@vger.kernel.org, imx@lists.linux.dev, linux-rockchip@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-renesas-soc@vger.kernel.org X-Mailer: b4 0.15-dev There's no need include the CPU number in the L2 cache node names as the names are local to the CPU nodes. The documented node name is also just "l2-cache". Signed-off-by: Rob Herring (Arm) --- arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi index 9e610a89a337..ad0cac8e4444 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi @@ -64,7 +64,7 @@ cpu0: cpu@0 { i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set next-level-cache = <&l2_cache_l0>; - l2_cache_l0: l2-cache-l0 { + l2_cache_l0: l2-cache { compatible = "cache"; cache-size = <0x80000>; cache-line-size = <64>; @@ -88,7 +88,7 @@ cpu1: cpu@1 { i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set next-level-cache = <&l2_cache_l1>; - l2_cache_l1: l2-cache-l1 { + l2_cache_l1: l2-cache { compatible = "cache"; cache-size = <0x80000>; cache-line-size = <64>; @@ -112,7 +112,7 @@ cpu2: cpu@2 { i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set next-level-cache = <&l2_cache_l2>; - l2_cache_l2: l2-cache-l2 { + l2_cache_l2: l2-cache { compatible = "cache"; cache-size = <0x80000>; cache-line-size = <64>; @@ -136,7 +136,7 @@ cpu3: cpu@3 { i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set next-level-cache = <&l2_cache_l3>; - l2_cache_l3: l2-cache-l3 { + l2_cache_l3: l2-cache { compatible = "cache"; cache-size = <0x80000>; cache-line-size = <64>; From patchwork Fri Apr 4 02:59:24 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring \(Arm\)" X-Patchwork-Id: 878537 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 23F1B1624C9; Fri, 4 Apr 2025 02:59:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743735585; cv=none; b=MKsMEiL/huPkKrXjAkh9cWw38Z4FDRHIb9eUz5F2kHxoezZQUVMUA5hYZkQDpw5QRjYSV0LByX1ZEhKRuXZxRyKM+EMpnxRGP5lTE3BV94t/LPhQh1QNsl3sZ4c/8d1m8GGvHGPhY95P3YmbXDQVE23KtXJSFLXbMD4oXKJGP3w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743735585; c=relaxed/simple; bh=TR8856X/yXYP9UKEhMkJp7m8f9J+E8ChQGwtop6ZgA8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=e54X88oZxnDXtjG+6i6bdkl+i3u/j6Si43gWPUE8o58Oh677VWOKpWa4aKdUb9zMLZzEDy2Bu7bAhYvcyAZgs/NM/2X00pD4aiGI4Bvou/p2PAynL6QUrg9+ZqSYuY7ee/abX6fowiDF2NdMf92nl4yE0g380IPpCHsETks84M8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=DUkDnjSM; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="DUkDnjSM" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 65CD0C4AF09; Fri, 4 Apr 2025 02:59:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1743735584; bh=TR8856X/yXYP9UKEhMkJp7m8f9J+E8ChQGwtop6ZgA8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=DUkDnjSM63kRZnwvM0O4CQNp4fGHP7NjHc0kMEGoFudbMbZwd7akrMVPzA7z4fsP/ LbzLYWMYPxL/Vp+jaNCT4G1kQQzfAPiLVe4GRnL7kHU6DyYihy7ZNO+Y43TX8Bnp/E SQu6P3nGqwmxa0ZwYvgvpIfC7S8pOEGp4HN86eV4rekb6QVHa59ZiQ86gFvXN16cYI ucq6IBizPqNpMPbRYiTdJeylxn6GfB6XEj6dMKmNQaF7mrRz9hp4c59gvk5IxjrbBn Mw/HuaEhMQ/esGlKPERqAE7RhxCvANISjn9KUarZ5Qu46dIXeGUrJsVuY8dHYWwh96 LEIua7+H5rxVg== From: "Rob Herring (Arm)" Date: Thu, 03 Apr 2025 21:59:24 -0500 Subject: [PATCH 03/19] arm64: dts: morello: Fix-up cache nodes Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250403-dt-cpu-schema-v1-3-076be7171a85@kernel.org> References: <20250403-dt-cpu-schema-v1-0-076be7171a85@kernel.org> In-Reply-To: <20250403-dt-cpu-schema-v1-0-076be7171a85@kernel.org> To: Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , "Rafael J. Wysocki" , Viresh Kumar , Matthias Brugger , AngeloGioacchino Del Regno , Vincenzo Frascino , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Bjorn Andersson , Konrad Dybcio , Thomas Bogendoerfer , Viresh Kumar , Nishanth Menon , Stephen Boyd , zhouyanjie@wanyeetech.com, Conor Dooley , Nicolas Ferre , Claudiu Beznea , Steen Hegelund , Daniel Machon , UNGLinuxDriver@microchip.com, Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Heiko Stuebner , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Geert Uytterhoeven , Magnus Damm Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-mips@vger.kernel.org, imx@lists.linux.dev, linux-rockchip@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-renesas-soc@vger.kernel.org X-Mailer: b4 0.15-dev There's no need include the CPU number in the L2 cache node names as the names are local to the CPU nodes. The documented node name is also just "l2-cache". The L3 cache is not part of cpu@0/l2-cache as it is shared among all cores. Move it to /cpus node which is the typical place for shared caches. Signed-off-by: Rob Herring (Arm) --- arch/arm64/boot/dts/arm/morello.dtsi | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/arm/morello.dtsi b/arch/arm64/boot/dts/arm/morello.dtsi index 0bab0b3ea969..5bc1c725dc86 100644 --- a/arch/arm64/boot/dts/arm/morello.dtsi +++ b/arch/arm64/boot/dts/arm/morello.dtsi @@ -44,7 +44,7 @@ cpu0: cpu@0 { next-level-cache = <&l2_0>; clocks = <&scmi_dvfs 0>; - l2_0: l2-cache-0 { + l2_0: l2-cache { compatible = "cache"; cache-level = <2>; /* 8 ways set associative */ @@ -53,13 +53,6 @@ l2_0: l2-cache-0 { cache-sets = <2048>; cache-unified; next-level-cache = <&l3_0>; - - l3_0: l3-cache { - compatible = "cache"; - cache-level = <3>; - cache-size = <0x100000>; - cache-unified; - }; }; }; @@ -78,7 +71,7 @@ cpu1: cpu@100 { next-level-cache = <&l2_1>; clocks = <&scmi_dvfs 0>; - l2_1: l2-cache-1 { + l2_1: l2-cache { compatible = "cache"; cache-level = <2>; /* 8 ways set associative */ @@ -105,7 +98,7 @@ cpu2: cpu@10000 { next-level-cache = <&l2_2>; clocks = <&scmi_dvfs 1>; - l2_2: l2-cache-2 { + l2_2: l2-cache { compatible = "cache"; cache-level = <2>; /* 8 ways set associative */ @@ -132,7 +125,7 @@ cpu3: cpu@10100 { next-level-cache = <&l2_3>; clocks = <&scmi_dvfs 1>; - l2_3: l2-cache-3 { + l2_3: l2-cache { compatible = "cache"; cache-level = <2>; /* 8 ways set associative */ @@ -143,6 +136,13 @@ l2_3: l2-cache-3 { next-level-cache = <&l3_0>; }; }; + + l3_0: l3-cache { + compatible = "cache"; + cache-level = <3>; + cache-size = <0x100000>; + cache-unified; + }; }; firmware { From patchwork Fri Apr 4 02:59:25 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring \(Arm\)" X-Patchwork-Id: 878374 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8616617A318; Fri, 4 Apr 2025 02:59:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743735586; cv=none; b=B495s353vuBplVcMJGn542Az/k8G+5NI2Kb2y/I6OkEhIDxZyqRe81oyaSaFrDk2pwhamjkzTdQVUPA4GRjPRFSIYJ4NSp5K51fvOUm4DArRsl0fXLEMEpD9eZIvEG8Y68oS6cYUvEwsTK0g6iydKG0t30+wpDDvgM5CPjvn/Ds= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743735586; c=relaxed/simple; bh=Z1vjAGywXYfiVgOwNiyG0noL4S7j+UnQpBh2x5H0shU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=dGVH4+Nt9DI/O0iAaFVFRmYaHRwNYDhONut+9gZAW6Io+ZfkbhyEc6BGF3LE0quIbG3+2cmhXVtz3364eQ3WgLFQEIfO6u5YlD6/7oua3180loB7AuDNRCAyGJtiUUbYwFvsB7d+kLlPJpvdvRQniNDqyYOOS65tK+SsW63ULGc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=qGkOYwQv; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="qGkOYwQv" Received: by smtp.kernel.org (Postfix) with ESMTPSA id AB4E3C4CEE3; Fri, 4 Apr 2025 02:59:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1743735586; bh=Z1vjAGywXYfiVgOwNiyG0noL4S7j+UnQpBh2x5H0shU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=qGkOYwQvYSxLYVzVO275Gh1fX6j5hRYE+1mqVqk/+RSIeVV6WelGep2C9jlA5gi/U J8f32eUfkmjd4CKkjwzjMcFCCYuNbc3W7cDHzU8kV+CoIIW2I7zifAImjHi6xO5APq GP7ZY4d3hqhJw3Ll3TqtcJCCdiSrMhjekkx/TYEQsNcn83Lvtqo5F0u6LGEAelzhCs K8y8ktRzgD4FEsRcLIpliun0dZS+cO9Hsq4AfvtqOnRUDs9uilMS65MUAIHz+2naEI 1XY946kOQqa6r5pNxrcjViJzQwrOwIzKcD5DlB6RkVhJUJwH3QGAuvJNQwbBiyQEoT JNFST/H+h3Szw== From: "Rob Herring (Arm)" Date: Thu, 03 Apr 2025 21:59:25 -0500 Subject: [PATCH 04/19] arm64: dts: microchip: sparx5: Fix CPU node "enable-method" property dependencies Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250403-dt-cpu-schema-v1-4-076be7171a85@kernel.org> References: <20250403-dt-cpu-schema-v1-0-076be7171a85@kernel.org> In-Reply-To: <20250403-dt-cpu-schema-v1-0-076be7171a85@kernel.org> To: Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , "Rafael J. Wysocki" , Viresh Kumar , Matthias Brugger , AngeloGioacchino Del Regno , Vincenzo Frascino , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Bjorn Andersson , Konrad Dybcio , Thomas Bogendoerfer , Viresh Kumar , Nishanth Menon , Stephen Boyd , zhouyanjie@wanyeetech.com, Conor Dooley , Nicolas Ferre , Claudiu Beznea , Steen Hegelund , Daniel Machon , UNGLinuxDriver@microchip.com, Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Heiko Stuebner , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Geert Uytterhoeven , Magnus Damm Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-mips@vger.kernel.org, imx@lists.linux.dev, linux-rockchip@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-renesas-soc@vger.kernel.org X-Mailer: b4 0.15-dev The "spin-table" enable-method requires "cpu-release-addr" property, so add a dummy entry. It is assumed the bootloader will fill in the correct values. Signed-off-by: Rob Herring (Arm) --- arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi index 32bb76b3202a..83bf5c81b5f7 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi @@ -12,10 +12,12 @@ &psci { &cpu0 { enable-method = "spin-table"; + cpu-release-addr = /bits/ 64 <0>; }; &cpu1 { enable-method = "spin-table"; + cpu-release-addr = /bits/ 64 <0>; }; &uart0 { From patchwork Fri Apr 4 02:59:26 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring \(Arm\)" X-Patchwork-Id: 878536 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B1A2218BBAE; Fri, 4 Apr 2025 02:59:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743735587; cv=none; b=PVitVn5mwQ+trZ1BC/KoT9GA9ZLh+CDtArxGUzwm+FyK9PdeBtE3FZnN/R0XOVSMMrjGJW5o/ctppzhUDPHejhQj5fIMPexqL/kFhSLbkFsgVSM9t5Igal7PRnu2nhDuABYDHYm6NR7LRgVW4alI310hLMbVnHfxSutxgXOHYJ0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743735587; c=relaxed/simple; bh=6GCFc3TOy1LAHhIH0FHC3IwyJd+TMm/GWKIlM1Cgt/k=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Xwcj3M4bYb/Pkix0vHiMBN+wn4dW+LCKtK5O0+CyV98t8Whzu01g+edIpU0hgdzYKodx/3L0nJZdLycMWsNLjkIWpNaNrCQmeY+5oF9wmt30HZXTY40k8PzGglpZnCd0ZHoMeTPJzkgoj8JvykZCHWBh+3/9hSotpo7uGn0CO4w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ngLHJxNx; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ngLHJxNx" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E7AC8C4CEE3; Fri, 4 Apr 2025 02:59:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1743735587; bh=6GCFc3TOy1LAHhIH0FHC3IwyJd+TMm/GWKIlM1Cgt/k=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=ngLHJxNxnM7sSXQ/6PRU0/L8GowkeGVz0Ortjzfu1yG8wov4Gpm+9CtRA4A+TLiG4 bCFnTdm7eePjs27Jwo2iOOLCf9C0vJc14qGDQxWUpH51Jzq2AntWhJ5ymBtGZvNQM5 UOVBRJCOirbMZ6VBEwvR5DJnz4mNMbLs2JgfUfC+cZRb4F0YYVCbJoAPB2Z7qSiVhj h7Ov7J5cOOmAEVS9IgbJr/thA2JvOUu8QffoaJQlg7noZ4NdGuPX9mhxF/OmZReIaP N/HEf3FZg5HDKq2z+hCE1TRDsJW1iYSq+Hc0EkC+HchK0tEXoPYfIBHDYWOcRUnDsn hraIn9sJZ6Tvw== From: "Rob Herring (Arm)" Date: Thu, 03 Apr 2025 21:59:26 -0500 Subject: [PATCH 05/19] arm64: dts: qcom: qdu1000: Fix qcom,freq-domain Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250403-dt-cpu-schema-v1-5-076be7171a85@kernel.org> References: <20250403-dt-cpu-schema-v1-0-076be7171a85@kernel.org> In-Reply-To: <20250403-dt-cpu-schema-v1-0-076be7171a85@kernel.org> To: Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , "Rafael J. Wysocki" , Viresh Kumar , Matthias Brugger , AngeloGioacchino Del Regno , Vincenzo Frascino , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Bjorn Andersson , Konrad Dybcio , Thomas Bogendoerfer , Viresh Kumar , Nishanth Menon , Stephen Boyd , zhouyanjie@wanyeetech.com, Conor Dooley , Nicolas Ferre , Claudiu Beznea , Steen Hegelund , Daniel Machon , UNGLinuxDriver@microchip.com, Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Heiko Stuebner , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Geert Uytterhoeven , Magnus Damm Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-mips@vger.kernel.org, imx@lists.linux.dev, linux-rockchip@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-renesas-soc@vger.kernel.org X-Mailer: b4 0.15-dev The correct property name is 'qcom,freq-domain', not 'qcom,freq-domains'. Signed-off-by: Rob Herring (Arm) --- arch/arm64/boot/dts/qcom/qdu1000.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi index f973aa8f7477..7c8d78fd7ebf 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -47,7 +47,7 @@ cpu0: cpu@0 { enable-method = "psci"; power-domains = <&cpu_pd0>; power-domain-names = "psci"; - qcom,freq-domains = <&cpufreq_hw 0>; + qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&l2_0>; l2_0: l2-cache { compatible = "cache"; @@ -70,7 +70,7 @@ cpu1: cpu@100 { enable-method = "psci"; power-domains = <&cpu_pd1>; power-domain-names = "psci"; - qcom,freq-domains = <&cpufreq_hw 0>; + qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&l2_100>; l2_100: l2-cache { compatible = "cache"; @@ -88,7 +88,7 @@ cpu2: cpu@200 { enable-method = "psci"; power-domains = <&cpu_pd2>; power-domain-names = "psci"; - qcom,freq-domains = <&cpufreq_hw 0>; + qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&l2_200>; l2_200: l2-cache { compatible = "cache"; @@ -106,7 +106,7 @@ cpu3: cpu@300 { enable-method = "psci"; power-domains = <&cpu_pd3>; power-domain-names = "psci"; - qcom,freq-domains = <&cpufreq_hw 0>; + qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&l2_300>; l2_300: l2-cache { compatible = "cache"; From patchwork Fri Apr 4 02:59:27 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring \(Arm\)" X-Patchwork-Id: 878373 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 908641624C9; Fri, 4 Apr 2025 02:59:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743735588; cv=none; b=GqTczs088wgNW3HKo4O86ZqwGzOTPfuNiZZCnJCrbX9b/wlPc7470cIf9gpNrjK84qANi8ZmMPtxOAXI5m98b14bGgA1fYlEmRnOdnIKqnvzxfhPCFN2HncPZjBrEYtaUi6bWrHCXkG214h5HAPWZblvSLpB+VMAAunhxUHx2Pw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743735588; c=relaxed/simple; bh=gxonXFhgUAPjWh8ts8EKS+oHyduTymt0daNZo0ExVAA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=B7lQawviuQFbhcyhg9/WHOLUij979Gzjv3VT0KxiBBh1S3aJakxnjL9i5Db1JMx8XjhCPHzKw+GmWk1noqMDc2tyL6pHNJERT35yBAy35QcTWXYUuwvoi5Zp1G/uZUMHu9OdjsYHObfxbYVFjcEx6PUXHVr6TEfvcCMoGlz9uvU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=q5AlyHo+; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="q5AlyHo+" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 17ABBC4CEE7; Fri, 4 Apr 2025 02:59:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1743735588; bh=gxonXFhgUAPjWh8ts8EKS+oHyduTymt0daNZo0ExVAA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=q5AlyHo+mQj3kurh2xUoSRYFq+1yRj9H+a7Gmn4LnwFHLR3AnDO/JaVceXofqiY/3 /xQ+f5of5Hm4HbuSD27xDVrwkVEIeMMW4VTsN9M/FKQTp1fK9AAZ1eNnJHWa5EVcch 1YuoXfohfyZI1t8ysMs/oJtbRtc/lXOx22hjlh62miVS8jEZ76LPU2rDV7Ip7Sp4hP 1k08hbFngCdFOvEVrao83FuUXXn8xaBe6pMb28raR8ttL4HJfNlJ9x1l7dFVwdX5Po 4DdcqBBRZFzRhTz4d6M83O7pVB3CLQkueenV35FwvKPcQwLGetut/o2MUhYhZQg6e7 ZVrW1lHWld3gQ== From: "Rob Herring (Arm)" Date: Thu, 03 Apr 2025 21:59:27 -0500 Subject: [PATCH 06/19] arm64: dts: qcom: msm8939: Fix CPU node "enable-method" property dependencies Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250403-dt-cpu-schema-v1-6-076be7171a85@kernel.org> References: <20250403-dt-cpu-schema-v1-0-076be7171a85@kernel.org> In-Reply-To: <20250403-dt-cpu-schema-v1-0-076be7171a85@kernel.org> To: Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , "Rafael J. Wysocki" , Viresh Kumar , Matthias Brugger , AngeloGioacchino Del Regno , Vincenzo Frascino , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Bjorn Andersson , Konrad Dybcio , Thomas Bogendoerfer , Viresh Kumar , Nishanth Menon , Stephen Boyd , zhouyanjie@wanyeetech.com, Conor Dooley , Nicolas Ferre , Claudiu Beznea , Steen Hegelund , Daniel Machon , UNGLinuxDriver@microchip.com, Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Heiko Stuebner , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Geert Uytterhoeven , Magnus Damm Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-mips@vger.kernel.org, imx@lists.linux.dev, linux-rockchip@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-renesas-soc@vger.kernel.org X-Mailer: b4 0.15-dev The "qcom,acc" and "qcom,saw" properties aren't valid with "spin-table" enable-method nor are they used on 64-bit kernels, so they can be dropped. The "spin-table" enable-method requires "cpu-release-addr" property, so add a dummy entry. It is assumed the bootloader will fill in the correct values. Signed-off-by: Rob Herring (Arm) --- arch/arm64/boot/dts/qcom/msm8939.dtsi | 24 ++++++++---------------- 1 file changed, 8 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8939.dtsi b/arch/arm64/boot/dts/qcom/msm8939.dtsi index 7cd5660de1b3..36f2ba3fb81c 100644 --- a/arch/arm64/boot/dts/qcom/msm8939.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8939.dtsi @@ -46,10 +46,9 @@ cpu0: cpu@100 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "spin-table"; + cpu-release-addr = /bits/ 64 <0>; reg = <0x100>; next-level-cache = <&l2_1>; - qcom,acc = <&acc0>; - qcom,saw = <&saw0>; cpu-idle-states = <&cpu_sleep_0>; clocks = <&apcs1_mbox>; #cooling-cells = <2>; @@ -64,10 +63,9 @@ cpu1: cpu@101 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "spin-table"; + cpu-release-addr = /bits/ 64 <0>; reg = <0x101>; next-level-cache = <&l2_1>; - qcom,acc = <&acc1>; - qcom,saw = <&saw1>; cpu-idle-states = <&cpu_sleep_0>; clocks = <&apcs1_mbox>; #cooling-cells = <2>; @@ -77,10 +75,9 @@ cpu2: cpu@102 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "spin-table"; + cpu-release-addr = /bits/ 64 <0>; reg = <0x102>; next-level-cache = <&l2_1>; - qcom,acc = <&acc2>; - qcom,saw = <&saw2>; cpu-idle-states = <&cpu_sleep_0>; clocks = <&apcs1_mbox>; #cooling-cells = <2>; @@ -90,10 +87,9 @@ cpu3: cpu@103 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "spin-table"; + cpu-release-addr = /bits/ 64 <0>; reg = <0x103>; next-level-cache = <&l2_1>; - qcom,acc = <&acc3>; - qcom,saw = <&saw3>; cpu-idle-states = <&cpu_sleep_0>; clocks = <&apcs1_mbox>; #cooling-cells = <2>; @@ -103,9 +99,8 @@ cpu4: cpu@0 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "spin-table"; + cpu-release-addr = /bits/ 64 <0>; reg = <0x0>; - qcom,acc = <&acc4>; - qcom,saw = <&saw4>; cpu-idle-states = <&cpu_sleep_0>; clocks = <&apcs0_mbox>; #cooling-cells = <2>; @@ -121,10 +116,9 @@ cpu5: cpu@1 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "spin-table"; + cpu-release-addr = /bits/ 64 <0>; reg = <0x1>; next-level-cache = <&l2_0>; - qcom,acc = <&acc5>; - qcom,saw = <&saw5>; cpu-idle-states = <&cpu_sleep_0>; clocks = <&apcs0_mbox>; #cooling-cells = <2>; @@ -134,10 +128,9 @@ cpu6: cpu@2 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "spin-table"; + cpu-release-addr = /bits/ 64 <0>; reg = <0x2>; next-level-cache = <&l2_0>; - qcom,acc = <&acc6>; - qcom,saw = <&saw6>; cpu-idle-states = <&cpu_sleep_0>; clocks = <&apcs0_mbox>; #cooling-cells = <2>; @@ -147,10 +140,9 @@ cpu7: cpu@3 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "spin-table"; + cpu-release-addr = /bits/ 64 <0>; reg = <0x3>; next-level-cache = <&l2_0>; - qcom,acc = <&acc7>; - qcom,saw = <&saw7>; cpu-idle-states = <&cpu_sleep_0>; clocks = <&apcs0_mbox>; #cooling-cells = <2>; From patchwork Fri Apr 4 02:59:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring \(Arm\)" X-Patchwork-Id: 878535 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AADE413AA2E; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="MpXVnVMr" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CFD73C4CEE7; Fri, 4 Apr 2025 02:59:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1743735591; bh=nVo5X/MosXjoMIZOdVn7ETl8AN7NiwovxfdEw8OmSOs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=MpXVnVMrGj9jX534Z3QILWihteFROOZpFGF7cY4LpdJ/vHXhydB+UXGlWiL4yWQB4 MkCR3gilGWmLGChDVWTTcfkMDs63dzW3J8NpL+I63xv6gf44HszHnPF5aNKa0h4T7c caRfFdYnPhzgZc1JocQT3/Q6LiL9G+DMwtJtDjgwmmquwSNBTS2H8djS9qC2sphBN2 P1Cgp4AVOzpzTpPm8SpIsWdV0ESebX0hsTqoMjdNevs2pD82PnipJyPInDkUM2QXYA Z7Lg/Tk+1JcZyy9fVa7gbntS/8pmlDuzwioeuqSQW0x75dypqHfY+J4/VPsE36jmr2 bm5Z7w4iLaFaQ== From: "Rob Herring (Arm)" Date: Thu, 03 Apr 2025 21:59:28 -0500 Subject: [PATCH 07/19] arm64: dts: qcom: msm8992-lg-h815: Fix CPU node "enable-method" property dependencies Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250403-dt-cpu-schema-v1-7-076be7171a85@kernel.org> References: <20250403-dt-cpu-schema-v1-0-076be7171a85@kernel.org> In-Reply-To: <20250403-dt-cpu-schema-v1-0-076be7171a85@kernel.org> To: Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , "Rafael J. Wysocki" , Viresh Kumar , Matthias Brugger , AngeloGioacchino Del Regno , Vincenzo Frascino , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Bjorn Andersson , Konrad Dybcio , Thomas Bogendoerfer , Viresh Kumar , Nishanth Menon , Stephen Boyd , zhouyanjie@wanyeetech.com, Conor Dooley , Nicolas Ferre , Claudiu Beznea , Steen Hegelund , Daniel Machon , UNGLinuxDriver@microchip.com, Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Heiko Stuebner , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Geert Uytterhoeven , Magnus Damm Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-mips@vger.kernel.org, imx@lists.linux.dev, linux-rockchip@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-renesas-soc@vger.kernel.org X-Mailer: b4 0.15-dev The "spin-table" enable-method requires "cpu-release-addr" property, so add a dummy entry. It is assumed the bootloader will fill in the correct values. Signed-off-by: Rob Herring (Arm) --- arch/arm64/boot/dts/qcom/msm8992-lg-h815.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8992-lg-h815.dts b/arch/arm64/boot/dts/qcom/msm8992-lg-h815.dts index 4520d5d51a29..6a231afad85d 100644 --- a/arch/arm64/boot/dts/qcom/msm8992-lg-h815.dts +++ b/arch/arm64/boot/dts/qcom/msm8992-lg-h815.dts @@ -93,26 +93,32 @@ key-vol-up { &cpu0 { enable-method = "spin-table"; + cpu-release-addr = /bits/ 64 <0>; }; &cpu1 { enable-method = "spin-table"; + cpu-release-addr = /bits/ 64 <0>; }; &cpu2 { enable-method = "spin-table"; + cpu-release-addr = /bits/ 64 <0>; }; &cpu3 { enable-method = "spin-table"; + cpu-release-addr = /bits/ 64 <0>; }; &cpu4 { enable-method = "spin-table"; + cpu-release-addr = /bits/ 64 <0>; }; &cpu5 { enable-method = "spin-table"; + cpu-release-addr = /bits/ 64 <0>; }; &pm8994_resin { From patchwork Fri Apr 4 02:59:29 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring \(Arm\)" X-Patchwork-Id: 878372 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AF3B313B2BB; Fri, 4 Apr 2025 02:59:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743735592; cv=none; b=SmBpb2xZXgTxTKDrxXr12pY31I620VjYsxWmXVCNecWRE2utAjIYIpEKMN6Mudf+EHwt7MiUNJ4CTQshs4k59yKs16xJr/3Q15XxAP0xuVdT8bxAUhnwSnSCXtGmw6dhcoeN6wxTUSxpncLnRw1xCuXOa9XPuDUPr3xCNsUDFbE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743735592; c=relaxed/simple; bh=NXfOJoK0Dz0mef/BAq7y8KxDDG3duFbiuiL1Z6QJ9BI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=notKgkXuQIbGCaCqoPTV4WYTP0ZBMSu+PIwUyCbScNE4HGR5ll3CUb7cyuI0TJKcSi/s58xY++LxgoqaQm3U8pEkRu1hVQpHRC93u798+lN8IE/llJqOgcR+O4YNRo79My/6X5AFwOTTJuVfUMPoHwPRGOyzwai0T1CiffMzAPQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=sGzlfMKi; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="sGzlfMKi" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2DE6DC4CEE7; Fri, 4 Apr 2025 02:59:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1743735592; bh=NXfOJoK0Dz0mef/BAq7y8KxDDG3duFbiuiL1Z6QJ9BI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=sGzlfMKi1upb46KlxcbmpIatBcJlDA+lJRioYblOpv5TuMcIgUURlrFv/QVkqvcTU cqjZ3jite7u9/lrkFPtYLaZQU+UPcpDjuKKwQKVdaz05Zt2Wg2bX8aD21CBMmgztP/ 597TFjZnnA5cS1HbMOvLF6ZZO6RT4hAa1J+fA2rlUycXmgZf53mYjv6qE+Elqb9F7E V6LVIXszs4tasfp/HFFOFuNBTRwJoQvjb168YTZBNWldrVQST227wqM+8fQaQlV3RP O1V2tZKhlzmE6O5RVW6E9/CixcMg8/3k12lNJLB9F/Ieoqt9oPG0IvqU/qqu+JWsS6 zwQKoFaWCIVXQ== From: "Rob Herring (Arm)" Date: Thu, 03 Apr 2025 21:59:29 -0500 Subject: [PATCH 08/19] arm: dts: qcom: msm8916: Move "qcom,acc" and "qcom,saw" to 32-bit .dtsi Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250403-dt-cpu-schema-v1-8-076be7171a85@kernel.org> References: <20250403-dt-cpu-schema-v1-0-076be7171a85@kernel.org> In-Reply-To: <20250403-dt-cpu-schema-v1-0-076be7171a85@kernel.org> To: Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , "Rafael J. Wysocki" , Viresh Kumar , Matthias Brugger , AngeloGioacchino Del Regno , Vincenzo Frascino , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Bjorn Andersson , Konrad Dybcio , Thomas Bogendoerfer , Viresh Kumar , Nishanth Menon , Stephen Boyd , zhouyanjie@wanyeetech.com, Conor Dooley , Nicolas Ferre , Claudiu Beznea , Steen Hegelund , Daniel Machon , UNGLinuxDriver@microchip.com, Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Heiko Stuebner , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Geert Uytterhoeven , Magnus Damm Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-mips@vger.kernel.org, imx@lists.linux.dev, linux-rockchip@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-renesas-soc@vger.kernel.org X-Mailer: b4 0.15-dev The "qcom,acc" and "qcom,saw" properties are only used with 32-bit kernels. Of course, booting a 64-bit or 32-bit kernel shouldn't matter to the DTS, but the "enable-method" is already different for 32-bit. Signed-off-by: Rob Herring (Arm) --- arch/arm/boot/dts/qcom/qcom-msm8916-smp.dtsi | 8 ++++++++ arch/arm64/boot/dts/qcom/msm8916.dtsi | 8 -------- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8916-smp.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8916-smp.dtsi index 94b7694eeeff..594cc4a3a78b 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8916-smp.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8916-smp.dtsi @@ -4,15 +4,23 @@ / { cpus { cpu@0 { enable-method = "qcom,msm8916-smp"; + qcom,acc = <&cpu0_acc>; + qcom,saw = <&cpu0_saw>; }; cpu@1 { enable-method = "qcom,msm8916-smp"; + qcom,acc = <&cpu1_acc>; + qcom,saw = <&cpu1_saw>; }; cpu@2 { enable-method = "qcom,msm8916-smp"; + qcom,acc = <&cpu2_acc>; + qcom,saw = <&cpu2_saw>; }; cpu@3 { enable-method = "qcom,msm8916-smp"; + qcom,acc = <&cpu3_acc>; + qcom,saw = <&cpu3_saw>; }; idle-states { diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 8f35c9af1878..88e452752de6 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -144,8 +144,6 @@ cpu0: cpu@0 { #cooling-cells = <2>; power-domains = <&cpu_pd0>; power-domain-names = "psci"; - qcom,acc = <&cpu0_acc>; - qcom,saw = <&cpu0_saw>; }; cpu1: cpu@1 { @@ -159,8 +157,6 @@ cpu1: cpu@1 { #cooling-cells = <2>; power-domains = <&cpu_pd1>; power-domain-names = "psci"; - qcom,acc = <&cpu1_acc>; - qcom,saw = <&cpu1_saw>; }; cpu2: cpu@2 { @@ -174,8 +170,6 @@ cpu2: cpu@2 { #cooling-cells = <2>; power-domains = <&cpu_pd2>; power-domain-names = "psci"; - qcom,acc = <&cpu2_acc>; - qcom,saw = <&cpu2_saw>; }; cpu3: cpu@3 { @@ -189,8 +183,6 @@ cpu3: cpu@3 { #cooling-cells = <2>; power-domains = <&cpu_pd3>; power-domain-names = "psci"; - qcom,acc = <&cpu3_acc>; - qcom,saw = <&cpu3_saw>; }; l2_0: l2-cache { From patchwork Fri Apr 4 02:59:30 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring \(Arm\)" X-Patchwork-Id: 878534 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DCF8919F10A; Fri, 4 Apr 2025 02:59:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743735594; cv=none; b=LJSv96gKStWGIH0i46vZAvk2qWN7SzWsBWnq/y4eTOXqI6/PnKObsTWXxSIvj5UDQtQqntNPIwCmHhXbUrAkN8T/RgD5icVW5TUmZ2cWGxiqoqNBvqirJeMBiDqFLGpvrl4BsxGorQrCeQydlqoum0090iquV5MEEM1dHfhyMcs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743735594; c=relaxed/simple; bh=1W6pnPI2cQreK/3+uRQUHI1ov/YAXvY/bkfHhelXghU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=nfeWP8b7m/hzLTyRmJ37Oz/Ro9KQrwT73PtpsEXa+rU02LDjw5fiXYl4VV7U3NRa4NerczdSLUlCOAO5t7cql+/GO0cmZsGaKr0YkxnqZ/mqjOm6UW9CtpgMfWoT49HeNqqrrXSHyW8SOpHhg7OZVp8wxk178aeqh44XhbPCnIw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=GdLsVFPS; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="GdLsVFPS" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8C76AC4CEE3; Fri, 4 Apr 2025 02:59:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1743735593; bh=1W6pnPI2cQreK/3+uRQUHI1ov/YAXvY/bkfHhelXghU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=GdLsVFPSPAzYBAvq539ZzBXsdV331WjtxuwM2qUxhzUdt56UPc33KEAtCXWymZboA Xqnktp3sh/XpKkjPwQ3eobyzfRsUtvBVCoQS5qeq/6fsr3BXauJ/ePBcaokzPWlWiy G9iMmBqkj5xkX4YVCwshcoXdrU4KiF7VJnZtxyww2fsu52Fu/eTEx7rax/36xxr7lB th/RHNX1p6qaubojJKCMRYZz+neBX6eJgKCm6pR6/ACSKgrfLr31J+RCRvDXXEI7fo 5PBzr7JXyURO63S0RDpJfsN2CzW3IYZC4xYP3ghIso/ijjEJBp1c/zraQoVAZ8ptE9 S1lLwK2TnC1fQ== From: "Rob Herring (Arm)" Date: Thu, 03 Apr 2025 21:59:30 -0500 Subject: [PATCH 09/19] arm: dts: qcom: sdx55/sdx65: Fix CPU power-domain-names Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250403-dt-cpu-schema-v1-9-076be7171a85@kernel.org> References: <20250403-dt-cpu-schema-v1-0-076be7171a85@kernel.org> In-Reply-To: <20250403-dt-cpu-schema-v1-0-076be7171a85@kernel.org> To: Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , "Rafael J. Wysocki" , Viresh Kumar , Matthias Brugger , AngeloGioacchino Del Regno , Vincenzo Frascino , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Bjorn Andersson , Konrad Dybcio , Thomas Bogendoerfer , Viresh Kumar , Nishanth Menon , Stephen Boyd , zhouyanjie@wanyeetech.com, Conor Dooley , Nicolas Ferre , Claudiu Beznea , Steen Hegelund , Daniel Machon , UNGLinuxDriver@microchip.com, Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Heiko Stuebner , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Geert Uytterhoeven , Magnus Damm Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-mips@vger.kernel.org, imx@lists.linux.dev, linux-rockchip@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-renesas-soc@vger.kernel.org X-Mailer: b4 0.15-dev "rpmhpd" is not documented nor used anywhere. As the enable-method is "psci" use "psci" for the power-domain name. Signed-off-by: Rob Herring (Arm) --- arch/arm/boot/dts/qcom/qcom-sdx55.dtsi | 2 +- arch/arm/boot/dts/qcom/qcom-sdx65.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi index 39530eb580ea..64d9858b4248 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi @@ -57,7 +57,7 @@ cpu0: cpu@0 { enable-method = "psci"; clocks = <&apcs>; power-domains = <&rpmhpd SDX55_CX>; - power-domain-names = "rpmhpd"; + power-domain-names = "psci"; operating-points-v2 = <&cpu_opp_table>; }; }; diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi index 6b23ee676c9e..bfd04e53c5a8 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi @@ -58,7 +58,7 @@ cpu0: cpu@0 { enable-method = "psci"; clocks = <&apcs>; power-domains = <&rpmhpd SDX65_CX_AO>; - power-domain-names = "rpmhpd"; + power-domain-names = "psci"; operating-points-v2 = <&cpu_opp_table>; }; }; From patchwork Fri Apr 4 02:59:31 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring \(Arm\)" X-Patchwork-Id: 878371 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 92C2A1A3145; Fri, 4 Apr 2025 02:59:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743735595; cv=none; b=isDvbDiVo0yjDZb/fs8WFHHh9pHLhHk07M0iOkU2raVMMJuG4+PjcbspaQ82mxEXefEp39YCpmeXF7TzYuefJv3+Gz8GNpz+qFL3hH85loakul++n4bfGtigZ027S6Sf1Tsj5h+0/gYlxBwIajfgfk7NuPRRAFCNca1t99Btyhw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743735595; c=relaxed/simple; bh=xMgbsjBv9Kef+UFcQ6l0JsE73pnNHHIi5V3EKTVvKZU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=o3OmKVHGLmO6DTcJTKw6TEpS7St29Bzh/4fsrexhJyP1jGdL9/GQIxi/CXY3QIv8WUWMKWl1OvDYc8evUqtQaKChoEEVjBBJa890c+1v+++jEkDQ8+o350kGK6hCWXOX5sD6NBnqWpeVkQ56FIMC/Q7aRQe3Moo+jiNXHac1cA0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=IWCsZoJx; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="IWCsZoJx" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D85A7C4CEEA; Fri, 4 Apr 2025 02:59:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1743735595; bh=xMgbsjBv9Kef+UFcQ6l0JsE73pnNHHIi5V3EKTVvKZU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=IWCsZoJxuJf4uC4DHbLlZqGIlVn0yqULR8Xtwd1cvdcGj7FhgjRQsG2SZFQd0XerM CRUVey1D2fQtZTk306phmWw6frB7jh1SH8kVjnZg+Qubx0VBm/vyiWFIzZpWBR08PA /LZ/0lId4BBMvcDw1WOPh7PViu2YUoTQ+UAqMt+Y7hyQdMNBm+uZwkM3WH9Tcr5/23 Vd8Ft9GnkB81oQy2ce+2bXpECXxW3bO6y598SZCfo3GvNV1vdgjQQvH5ZZ6EYT4wcG 6pqTzBxnPTqB8+Dy9NGVG76jnC1SNKcdt17QiODpJwYElrrof8OiFD5VlOEZ+y99Gs jg+wxJbjyDYcA== From: "Rob Herring (Arm)" Date: Thu, 03 Apr 2025 21:59:31 -0500 Subject: [PATCH 10/19] arm/arm64: dts: imx: Drop redundant CPU "clock-latency" Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250403-dt-cpu-schema-v1-10-076be7171a85@kernel.org> References: <20250403-dt-cpu-schema-v1-0-076be7171a85@kernel.org> In-Reply-To: <20250403-dt-cpu-schema-v1-0-076be7171a85@kernel.org> To: Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , "Rafael J. Wysocki" , Viresh Kumar , Matthias Brugger , AngeloGioacchino Del Regno , Vincenzo Frascino , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Bjorn Andersson , Konrad Dybcio , Thomas Bogendoerfer , Viresh Kumar , Nishanth Menon , Stephen Boyd , zhouyanjie@wanyeetech.com, Conor Dooley , Nicolas Ferre , Claudiu Beznea , Steen Hegelund , Daniel Machon , UNGLinuxDriver@microchip.com, Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Heiko Stuebner , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Geert Uytterhoeven , Magnus Damm Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-mips@vger.kernel.org, imx@lists.linux.dev, linux-rockchip@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-renesas-soc@vger.kernel.org X-Mailer: b4 0.15-dev The "clock-latency" property is part of the deprecated opp-v1 binding and is redundant if the opp-v2 table has equal or larger values in any "clock-latency-ns". The OPP tables have values of 150000, so it can be removed. Signed-off-by: Rob Herring (Arm) --- arch/arm/boot/dts/nxp/imx/imx7s.dtsi | 1 - arch/arm64/boot/dts/freescale/imx8mm.dtsi | 4 ---- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 4 ---- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 4 ---- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 4 ---- 5 files changed, 17 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx7s.dtsi b/arch/arm/boot/dts/nxp/imx/imx7s.dtsi index 2629968001a7..9235dd7e93bb 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7s.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx7s.dtsi @@ -73,7 +73,6 @@ cpu0: cpu@0 { device_type = "cpu"; reg = <0>; clock-frequency = <792000000>; - clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clks IMX7D_CLK_ARM>; cpu-idle-states = <&cpu_sleep_wait>; operating-points-v2 = <&cpu0_opp_table>; diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 4de3bf22902b..cfebaa01217e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -62,7 +62,6 @@ A53_0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0>; - clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MM_CLK_ARM>; enable-method = "psci"; i-cache-size = <0x8000>; @@ -83,7 +82,6 @@ A53_1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x1>; - clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MM_CLK_ARM>; enable-method = "psci"; i-cache-size = <0x8000>; @@ -102,7 +100,6 @@ A53_2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x2>; - clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MM_CLK_ARM>; enable-method = "psci"; i-cache-size = <0x8000>; @@ -121,7 +118,6 @@ A53_3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x3>; - clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MM_CLK_ARM>; enable-method = "psci"; i-cache-size = <0x8000>; diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index a5f9cfb46e5d..848ba5e46ee6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -62,7 +62,6 @@ A53_0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0>; - clock-latency = <61036>; clocks = <&clk IMX8MN_CLK_ARM>; enable-method = "psci"; i-cache-size = <0x8000>; @@ -83,7 +82,6 @@ A53_1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x1>; - clock-latency = <61036>; clocks = <&clk IMX8MN_CLK_ARM>; enable-method = "psci"; i-cache-size = <0x8000>; @@ -102,7 +100,6 @@ A53_2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x2>; - clock-latency = <61036>; clocks = <&clk IMX8MN_CLK_ARM>; enable-method = "psci"; i-cache-size = <0x8000>; @@ -121,7 +118,6 @@ A53_3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x3>; - clock-latency = <61036>; clocks = <&clk IMX8MN_CLK_ARM>; enable-method = "psci"; i-cache-size = <0x8000>; diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index ce6793b2d57e..f8afdba71c36 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -65,7 +65,6 @@ A53_0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0>; - clock-latency = <61036>; clocks = <&clk IMX8MP_CLK_ARM>; enable-method = "psci"; i-cache-size = <0x8000>; @@ -86,7 +85,6 @@ A53_1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x1>; - clock-latency = <61036>; clocks = <&clk IMX8MP_CLK_ARM>; enable-method = "psci"; i-cache-size = <0x8000>; @@ -105,7 +103,6 @@ A53_2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x2>; - clock-latency = <61036>; clocks = <&clk IMX8MP_CLK_ARM>; enable-method = "psci"; i-cache-size = <0x8000>; @@ -124,7 +121,6 @@ A53_3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x3>; - clock-latency = <61036>; clocks = <&clk IMX8MP_CLK_ARM>; enable-method = "psci"; i-cache-size = <0x8000>; diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index d51de8d899b2..d27b824995eb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -106,7 +106,6 @@ A53_0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0>; - clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; i-cache-size = <0x8000>; @@ -126,7 +125,6 @@ A53_1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x1>; - clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; i-cache-size = <0x8000>; @@ -144,7 +142,6 @@ A53_2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x2>; - clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; i-cache-size = <0x8000>; @@ -162,7 +159,6 @@ A53_3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x3>; - clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; i-cache-size = <0x8000>; From patchwork Fri Apr 4 02:59:32 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring \(Arm\)" X-Patchwork-Id: 878533 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC5541A725A; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="XIrMHwGT" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0AB7BC4CEE9; Fri, 4 Apr 2025 02:59:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1743735596; bh=xxnpE5qJ/N71v6fr0ntanbnn0YWeubI80yQwzP2nKgo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=XIrMHwGTXb4RmttX/4kwcXrnnodX0JBT8uweoux/nL/HuKOCPfCBajnBFPeD8Vts6 Gxe61aW4gvaTXmKw6+t5HolmnAW2Voe3vCOH6CoEzBtJxFC7kFmaeCW+xjLtma4zQz ++plRy91W12HopTil7NZc1ybIwDLVV4XS0vSsAgmEKXZzpEGXa0NWNGe8YGQUDFq7g UO7KBuOKY4U2H35uR9JTDOezj0jCkY4PTq+UF987lhUjRS4VKyqb6aJ/ET9NTmi+nP 8TGp3QOoj802IkgOm+5C2Z/QNMN0ZE8AL8H0rwftmHSLbeAbe8AJfG9aNj9PPoqaWO BgFjh05sC9akQ== From: "Rob Herring (Arm)" Date: Thu, 03 Apr 2025 21:59:32 -0500 Subject: [PATCH 11/19] arm: dts: qcom: ipq4019: Drop redundant CPU "clock-latency" Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250403-dt-cpu-schema-v1-11-076be7171a85@kernel.org> References: <20250403-dt-cpu-schema-v1-0-076be7171a85@kernel.org> In-Reply-To: <20250403-dt-cpu-schema-v1-0-076be7171a85@kernel.org> To: Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , "Rafael J. Wysocki" , Viresh Kumar , Matthias Brugger , AngeloGioacchino Del Regno , Vincenzo Frascino , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Bjorn Andersson , Konrad Dybcio , Thomas Bogendoerfer , Viresh Kumar , Nishanth Menon , Stephen Boyd , zhouyanjie@wanyeetech.com, Conor Dooley , Nicolas Ferre , Claudiu Beznea , Steen Hegelund , Daniel Machon , UNGLinuxDriver@microchip.com, Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Heiko Stuebner , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Geert Uytterhoeven , Magnus Damm Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-mips@vger.kernel.org, imx@lists.linux.dev, linux-rockchip@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-renesas-soc@vger.kernel.org X-Mailer: b4 0.15-dev The "clock-latency" property is part of the deprecated opp-v1 binding and is redundant if the opp-v2 table has equal or larger values in any "clock-latency-ns". The OPP table has values of 256000, so it can be removed. Signed-off-by: Rob Herring (Arm) --- arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi index 06b20c196faf..fceb2f5f5482 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi @@ -53,7 +53,6 @@ cpu@0 { reg = <0x0>; clocks = <&gcc GCC_APPS_CLK_SRC>; clock-frequency = <0>; - clock-latency = <256000>; operating-points-v2 = <&cpu0_opp_table>; }; @@ -67,7 +66,6 @@ cpu@1 { reg = <0x1>; clocks = <&gcc GCC_APPS_CLK_SRC>; clock-frequency = <0>; - clock-latency = <256000>; operating-points-v2 = <&cpu0_opp_table>; }; @@ -81,7 +79,6 @@ cpu@2 { reg = <0x2>; clocks = <&gcc GCC_APPS_CLK_SRC>; clock-frequency = <0>; - clock-latency = <256000>; operating-points-v2 = <&cpu0_opp_table>; }; @@ -95,7 +92,6 @@ cpu@3 { reg = <0x3>; clocks = <&gcc GCC_APPS_CLK_SRC>; clock-frequency = <0>; - clock-latency = <256000>; operating-points-v2 = <&cpu0_opp_table>; }; From patchwork Fri Apr 4 02:59:33 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring \(Arm\)" X-Patchwork-Id: 878370 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EE3A61448D5; Fri, 4 Apr 2025 02:59:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743735598; cv=none; b=SBjTYQyylbM+cthQj3YehQbpyV1eQNvnhDIepJTun92qErsKGtwMdQDtmzJk8XfzbuCkxNSjM6JKPd05BeA9B8G2effxb1V2kQN+hbni1YzMh9h+uh2KHe7J26ekdUXFGu4u3W+4xCRHG5KN6yDCsUhQ2t5uTf+jY6/U/0U4OwE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743735598; c=relaxed/simple; bh=xnnf/JMo7g8hotGpKUR0IYT07WFDf4YWzcm+WUwyUKc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=sRlh/mKpvjFZMXN1w2MColaCwlwT9hvPs+E2ThEUXTK2rTgIvuGf0Ume/xZ6m2obHKQpWY0BEHMyA1DvtdJZwsf4O+T2xS7BPKAMkc0RXL0WMeAnNdhHR3dXx0xL/nc0S1pi49bP76VEExP0zqek22iZ9KJuoFIJcfTpdPGFY3I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=L9m4MVF+; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="L9m4MVF+" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 508DAC4CEE3; Fri, 4 Apr 2025 02:59:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1743735597; bh=xnnf/JMo7g8hotGpKUR0IYT07WFDf4YWzcm+WUwyUKc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=L9m4MVF+CjyKiJF4HQGUCr+TFqomiA/bqC44XWNkWA1DHlVlz11Nva+tpMBnQsZxX eTghr2qdE7kh4uMtWQ2MvUFrOCocer4i0q+HiEXH8Yt9NsFAAkTbMYbobNxAg5B3lG HHB/EKqho1Fxd955zmMMskUQxaJYEZ0sW4L4SQ0hth4v8pPtWW9kSY7nJbdWOg61zc /3x+zwMvRp7HYKDbQcQia+tpYSJckx6QMv5w4fAf+Q6BLKjiplevqbbSxd52uFDNcV +xjhIsAKGFyvY9b16zN1Ba9+p4FruKxUwWqia9z0I/HKN3uYF2G35eyAKEDXjpJG/1 lKJRzlS2Kq4Sw== From: "Rob Herring (Arm)" Date: Thu, 03 Apr 2025 21:59:33 -0500 Subject: [PATCH 12/19] arm: dts: rockchip: Drop redundant CPU "clock-latency" Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250403-dt-cpu-schema-v1-12-076be7171a85@kernel.org> References: <20250403-dt-cpu-schema-v1-0-076be7171a85@kernel.org> In-Reply-To: <20250403-dt-cpu-schema-v1-0-076be7171a85@kernel.org> To: Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , "Rafael J. Wysocki" , Viresh Kumar , Matthias Brugger , AngeloGioacchino Del Regno , Vincenzo Frascino , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Bjorn Andersson , Konrad Dybcio , Thomas Bogendoerfer , Viresh Kumar , Nishanth Menon , Stephen Boyd , zhouyanjie@wanyeetech.com, Conor Dooley , Nicolas Ferre , Claudiu Beznea , Steen Hegelund , Daniel Machon , UNGLinuxDriver@microchip.com, Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Heiko Stuebner , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Geert Uytterhoeven , Magnus Damm Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-mips@vger.kernel.org, imx@lists.linux.dev, linux-rockchip@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-renesas-soc@vger.kernel.org X-Mailer: b4 0.15-dev The "clock-latency" property is part of the deprecated opp-v1 binding and is redundant if the opp-v2 table has equal or larger values in any "clock-latency-ns". Add any missing "clock-latency-ns" properties and remove "clock-latency". Signed-off-by: Rob Herring (Arm) --- arch/arm/boot/dts/rockchip/rk3128.dtsi | 8 +++++++- arch/arm/boot/dts/rockchip/rk3188.dtsi | 1 - arch/arm/boot/dts/rockchip/rk322x.dtsi | 1 - arch/arm/boot/dts/rockchip/rk3288.dtsi | 5 +---- arch/arm/boot/dts/rockchip/rv1108.dtsi | 1 - 5 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi index d4572146d135..c49099954c28 100644 --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi @@ -48,7 +48,6 @@ cpu0: cpu@f00 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0xf00>; - clock-latency = <40000>; clocks = <&cru ARMCLK>; resets = <&cru SRST_CORE0>; operating-points-v2 = <&cpu_opp_table>; @@ -87,31 +86,38 @@ cpu_opp_table: opp-table-0 { opp-216000000 { opp-hz = /bits/ 64 <216000000>; opp-microvolt = <950000 950000 1325000>; + clock-latency-ns = <40000>; }; opp-408000000 { opp-hz = /bits/ 64 <408000000>; opp-microvolt = <950000 950000 1325000>; + clock-latency-ns = <40000>; }; opp-600000000 { opp-hz = /bits/ 64 <600000000>; opp-microvolt = <950000 950000 1325000>; + clock-latency-ns = <40000>; }; opp-696000000 { opp-hz = /bits/ 64 <696000000>; opp-microvolt = <975000 975000 1325000>; + clock-latency-ns = <40000>; }; opp-816000000 { opp-hz = /bits/ 64 <816000000>; opp-microvolt = <1075000 1075000 1325000>; opp-suspend; + clock-latency-ns = <40000>; }; opp-1008000000 { opp-hz = /bits/ 64 <1008000000>; opp-microvolt = <1200000 1200000 1325000>; + clock-latency-ns = <40000>; }; opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; opp-microvolt = <1325000 1325000 1325000>; + clock-latency-ns = <40000>; }; }; diff --git a/arch/arm/boot/dts/rockchip/rk3188.dtsi b/arch/arm/boot/dts/rockchip/rk3188.dtsi index 44b54af0bbf9..850bd6e67895 100644 --- a/arch/arm/boot/dts/rockchip/rk3188.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3188.dtsi @@ -23,7 +23,6 @@ cpu0: cpu@0 { compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <0x0>; - clock-latency = <40000>; clocks = <&cru ARMCLK>; operating-points-v2 = <&cpu0_opp_table>; resets = <&cru SRST_CORE0>; diff --git a/arch/arm/boot/dts/rockchip/rk322x.dtsi b/arch/arm/boot/dts/rockchip/rk322x.dtsi index 96421355c274..cd11a018105b 100644 --- a/arch/arm/boot/dts/rockchip/rk322x.dtsi +++ b/arch/arm/boot/dts/rockchip/rk322x.dtsi @@ -36,7 +36,6 @@ cpu0: cpu@f00 { resets = <&cru SRST_CORE0>; operating-points-v2 = <&cpu0_opp_table>; #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; clocks = <&cru ARMCLK>; enable-method = "psci"; }; diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi index 3f1d640afafa..42d705b544ec 100644 --- a/arch/arm/boot/dts/rockchip/rk3288.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi @@ -70,7 +70,6 @@ cpu0: cpu@500 { resets = <&cru SRST_CORE0>; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; clocks = <&cru ARMCLK>; dynamic-power-coefficient = <370>; }; @@ -81,7 +80,6 @@ cpu1: cpu@501 { resets = <&cru SRST_CORE1>; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; clocks = <&cru ARMCLK>; dynamic-power-coefficient = <370>; }; @@ -92,7 +90,6 @@ cpu2: cpu@502 { resets = <&cru SRST_CORE2>; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; clocks = <&cru ARMCLK>; dynamic-power-coefficient = <370>; }; @@ -103,7 +100,6 @@ cpu3: cpu@503 { resets = <&cru SRST_CORE3>; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; clocks = <&cru ARMCLK>; dynamic-power-coefficient = <370>; }; @@ -116,6 +112,7 @@ cpu_opp_table: opp-table-0 { opp-126000000 { opp-hz = /bits/ 64 <126000000>; opp-microvolt = <900000>; + clock-latency-ns = <40000>; }; opp-216000000 { opp-hz = /bits/ 64 <216000000>; diff --git a/arch/arm/boot/dts/rockchip/rv1108.dtsi b/arch/arm/boot/dts/rockchip/rv1108.dtsi index f3291f3bbc6f..42a4d72597a5 100644 --- a/arch/arm/boot/dts/rockchip/rv1108.dtsi +++ b/arch/arm/boot/dts/rockchip/rv1108.dtsi @@ -32,7 +32,6 @@ cpu0: cpu@f00 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0xf00>; - clock-latency = <40000>; clocks = <&cru ARMCLK>; #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <75>; From patchwork Fri Apr 4 02:59:34 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring \(Arm\)" X-Patchwork-Id: 878532 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5A6781AF0B5; Fri, 4 Apr 2025 02:59:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743735599; cv=none; b=C96rBtrLcAQPlEMsL6tQOmjkudxJ6lArFx0i7iOJldWRQX4hLPRtZXRbYVonkUtqHypPNDSE34KNwEwZjC6Pb+KRvob5Lkxa0hj2oVcEsqvQkhI8/HdegTa1U8Unx3i519e8XeUBU8kB1C/0bxH95cWw8oULgFwI53/OGSHQQmU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743735599; c=relaxed/simple; bh=4ruN2yfM04MfyMd6Xn/cn9jUkSuoetlWEHVWLk/RgcU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=bKQqs0qQqSX+0nhogJLgeKWVKr5Ii0zE44z+8NHYiL9D8soGH4bWSZn12z4UY5O1T+nSraPyplceo6xFcTBNALud1ipgdfdl2i5QQrD+nd3Dxr6A7n1AqprXqSQ6Jo9e69c91r1tgrmlYNJIp2oZpCDC/v7lkJvWo2bFhRlgFI0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=NSI78iUL; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="NSI78iUL" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 84474C4CEEC; Fri, 4 Apr 2025 02:59:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1743735598; bh=4ruN2yfM04MfyMd6Xn/cn9jUkSuoetlWEHVWLk/RgcU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=NSI78iULj7EW28JG6UGcyucWTfviR4kacHtacvVklWgcec5mnFZIlv9fRfA/TVrJy ykQoMv6ZI5LSkZnkgkd1LHdl0FUdDkos7cOsilXzM4YH8EtkHmpEbg7CUUCsa4cMEQ 34nltx4QMZnliKNpDFK2EVs5rEq6DlFMy7GTEskilCGVfIBgVWXB3M/MSZV+I/Cwh/ TcCvoRsiAFSsQY6saLpV+bNzRfI0Ly2Vy51nN0TLGGDzxTGpDHquXnFBg4U+YUqWHb JXFP+8N0MFAi9iBySk4TVdw8xIS2tRGUhAUWn4805s5EUR4SpRiaqcdYYmNjroveZ9 WPd+aaU3lumQw== From: "Rob Herring (Arm)" Date: Thu, 03 Apr 2025 21:59:34 -0500 Subject: [PATCH 13/19] arm64: dts: amlogic: Drop redundant CPU "clock-latency" Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250403-dt-cpu-schema-v1-13-076be7171a85@kernel.org> References: <20250403-dt-cpu-schema-v1-0-076be7171a85@kernel.org> In-Reply-To: <20250403-dt-cpu-schema-v1-0-076be7171a85@kernel.org> To: Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , "Rafael J. Wysocki" , Viresh Kumar , Matthias Brugger , AngeloGioacchino Del Regno , Vincenzo Frascino , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Bjorn Andersson , Konrad Dybcio , Thomas Bogendoerfer , Viresh Kumar , Nishanth Menon , Stephen Boyd , zhouyanjie@wanyeetech.com, Conor Dooley , Nicolas Ferre , Claudiu Beznea , Steen Hegelund , Daniel Machon , UNGLinuxDriver@microchip.com, Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Heiko Stuebner , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Geert Uytterhoeven , Magnus Damm Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-mips@vger.kernel.org, imx@lists.linux.dev, linux-rockchip@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-renesas-soc@vger.kernel.org X-Mailer: b4 0.15-dev The "clock-latency" property is part of the deprecated opp-v1 binding and is redundant if the opp-v2 table has equal or larger values in any "clock-latency-ns". Add any missing "clock-latency-ns" properties and remove "clock-latency". Signed-off-by: Rob Herring (Arm) --- arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am.dts | 4 ---- arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts | 4 ---- arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts | 4 ---- arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts | 4 ---- arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts | 4 ---- arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 1 + arch/arm64/boot/dts/amlogic/meson-g12b-a311d-libretech-cc.dts | 6 ------ arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi | 2 ++ arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi | 6 ------ arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi | 6 ------ arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi | 6 ------ arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts | 6 ------ arch/arm64/boot/dts/amlogic/meson-g12b-odroid.dtsi | 6 ------ arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts | 6 ------ arch/arm64/boot/dts/amlogic/meson-g12b-s922x.dtsi | 2 ++ arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi | 6 ------ arch/arm64/boot/dts/amlogic/meson-sm1-ac2xx.dtsi | 4 ---- arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi | 4 ---- arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts | 4 ---- arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi | 4 ---- arch/arm64/boot/dts/amlogic/meson-sm1-s905d3-libretech-cc.dts | 4 ---- arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts | 4 ---- arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 1 + 23 files changed, 6 insertions(+), 92 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am.dts index 9aa36f17ffa2..d0a3b4b9229c 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am.dts @@ -267,28 +267,24 @@ &cpu0 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu1 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu2 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu3 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; ðmac { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts index 952b8d02e5c2..4353485c6f26 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts @@ -220,28 +220,24 @@ &cpu0 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu1 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu2 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu3 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cvbs_vdac_port { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts index 52fbc5103e45..f39fcabc763f 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts @@ -314,28 +314,24 @@ &cpu0 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu1 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu2 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu3 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cvbs_vdac_port { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts index 5407049d2647..b5bf8ecc91e6 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts @@ -407,28 +407,24 @@ &cpu0 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu1 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu2 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu3 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &clkc_audio { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts index 01da83658ae3..5ab460a3e637 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts @@ -263,28 +263,24 @@ &cpu0 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu1 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu2 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu3 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cvbs_vdac_port { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi index 543e70669df5..deee61dbe074 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi @@ -62,6 +62,7 @@ cpu_opp_table: opp-table { opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <731000>; + clock-latency-ns = <50000>; }; opp-1200000000 { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-libretech-cc.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-libretech-cc.dts index adedc1340c78..415248931ab1 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-libretech-cc.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-libretech-cc.dts @@ -76,42 +76,36 @@ &cpu0 { cpu-supply = <&vddcpu_b>; operating-points-v2 = <&cpu_opp_table_0>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu1 { cpu-supply = <&vddcpu_b>; operating-points-v2 = <&cpu_opp_table_0>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu100 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cpu101 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cpu102 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cpu103 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &pwm_ab { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi index 8e9ad1e51d66..8ecb5bd125c1 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi @@ -14,6 +14,7 @@ cpu_opp_table_0: opp-table-0 { opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <761000>; + clock-latency-ns = <50000>; }; opp-1200000000 { @@ -54,6 +55,7 @@ cpub_opp_table_1: opp-table-1 { opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <731000>; + clock-latency-ns = <50000>; }; opp-1200000000 { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi index 92e8b26ecccc..39011b645128 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi @@ -155,42 +155,36 @@ &cpu0 { cpu-supply = <&vddcpu_b>; operating-points-v2 = <&cpu_opp_table_0>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu1 { cpu-supply = <&vddcpu_b>; operating-points-v2 = <&cpu_opp_table_0>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu100 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cpu101 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cpu102 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cpu103 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &ext_mdio { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi index 54663c55a20e..1b08303c4282 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi @@ -263,42 +263,36 @@ &cpu0 { cpu-supply = <&vddcpu_b>; operating-points-v2 = <&cpu_opp_table_0>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu1 { cpu-supply = <&vddcpu_b>; operating-points-v2 = <&cpu_opp_table_0>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu100 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cpu101 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cpu102 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cpu103 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; ðmac { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi index 48650bad230d..fc737499f207 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi @@ -51,42 +51,36 @@ &cpu0 { cpu-supply = <&vddcpu_b>; operating-points-v2 = <&cpu_opp_table_0>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu1 { cpu-supply = <&vddcpu_b>; operating-points-v2 = <&cpu_opp_table_0>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu100 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cpu101 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cpu102 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cpu103 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &pwm_ab { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts index e21831dfceee..d5938a4a6da3 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts @@ -281,42 +281,36 @@ &cpu0 { cpu-supply = <&vddcpu_b>; operating-points-v2 = <&cpu_opp_table_0>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu1 { cpu-supply = <&vddcpu_b>; operating-points-v2 = <&cpu_opp_table_0>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu100 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cpu101 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cpu102 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cpu103 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; /* RK817 only supports 12.5mV steps, round up the values */ diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid.dtsi index 7e8964bacfce..3298d59833b6 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid.dtsi @@ -227,42 +227,36 @@ &cpu0 { cpu-supply = <&vddcpu_b>; operating-points-v2 = <&cpu_opp_table_0>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu1 { cpu-supply = <&vddcpu_b>; operating-points-v2 = <&cpu_opp_table_0>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu100 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cpu101 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cpu102 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cpu103 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cpu_thermal { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts index fc05ecf90714..1e5c6f984945 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts @@ -259,42 +259,36 @@ &cpu0 { cpu-supply = <&vddcpu_b>; operating-points-v2 = <&cpu_opp_table_0>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu1 { cpu-supply = <&vddcpu_b>; operating-points-v2 = <&cpu_opp_table_0>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu100 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cpu101 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cpu102 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cpu103 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cpu_thermal { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-s922x.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-s922x.dtsi index 44c23c984034..19cad93a6889 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-s922x.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-s922x.dtsi @@ -14,6 +14,7 @@ cpu_opp_table_0: opp-table-0 { opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <731000>; + clock-latency-ns = <50000>; }; opp-1200000000 { @@ -59,6 +60,7 @@ cpub_opp_table_1: opp-table-1 { opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <771000>; + clock-latency-ns = <50000>; }; opp-1200000000 { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi index a7a0fc264cdc..9b6d780eada7 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi @@ -213,42 +213,36 @@ &cpu0 { cpu-supply = <&vddcpu_b>; operating-points-v2 = <&cpu_opp_table_0>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu1 { cpu-supply = <&vddcpu_b>; operating-points-v2 = <&cpu_opp_table_0>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu100 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cpu101 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cpu102 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cpu103 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cvbs_vdac_port { diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-ac2xx.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1-ac2xx.dtsi index a3463149db3d..9be3084b090d 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-ac2xx.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-ac2xx.dtsi @@ -147,28 +147,24 @@ &cpu0 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu1 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU1_CLK>; - clock-latency = <50000>; }; &cpu2 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU2_CLK>; - clock-latency = <50000>; }; &cpu3 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU3_CLK>; - clock-latency = <50000>; }; &cvbs_vdac_port { diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi index 40db95f64636..538b35036954 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi @@ -185,28 +185,24 @@ &cpu0 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu1 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU1_CLK>; - clock-latency = <50000>; }; &cpu2 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU2_CLK>; - clock-latency = <50000>; }; &cpu3 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU3_CLK>; - clock-latency = <50000>; }; &ext_mdio { diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts index 5d75ad3f3e46..a3d9b66b6878 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts @@ -51,28 +51,24 @@ &cpu0 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu1 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU1_CLK>; - clock-latency = <50000>; }; &cpu2 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU2_CLK>; - clock-latency = <50000>; }; &cpu3 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU3_CLK>; - clock-latency = <50000>; }; &pwm_AO_cd { diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi index ad8d07883760..c4524eb4f099 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi @@ -250,28 +250,24 @@ &cpu0 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu1 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU1_CLK>; - clock-latency = <50000>; }; &cpu2 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU2_CLK>; - clock-latency = <50000>; }; &cpu3 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU3_CLK>; - clock-latency = <50000>; }; &ext_mdio { diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-s905d3-libretech-cc.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-s905d3-libretech-cc.dts index 537370db360f..5daadfb170b4 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-s905d3-libretech-cc.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-s905d3-libretech-cc.dts @@ -64,26 +64,22 @@ &cpu0 { cpu-supply = <&vddcpu_b>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu1 { cpu-supply = <&vddcpu_b>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU1_CLK>; - clock-latency = <50000>; }; &cpu2 { cpu-supply = <&vddcpu_b>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU2_CLK>; - clock-latency = <50000>; }; &cpu3 { cpu-supply = <&vddcpu_b>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU3_CLK>; - clock-latency = <50000>; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts index 37d7f64b6d5d..024d2eb8e6ee 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts @@ -359,28 +359,24 @@ &cpu0 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu1 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU1_CLK>; - clock-latency = <50000>; }; &cpu2 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU2_CLK>; - clock-latency = <50000>; }; &cpu3 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU3_CLK>; - clock-latency = <50000>; }; ðmac { diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi index 97e4b52066dc..966ebb19cc55 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi @@ -100,6 +100,7 @@ cpu_opp_table: opp-table { opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <770000>; + clock-latency-ns = <50000>; }; opp-1200000000 { From patchwork Fri Apr 4 02:59:35 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring \(Arm\)" X-Patchwork-Id: 878369 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DB7441B4227; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="g/nOEnzC" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E4003C4CEE3; Fri, 4 Apr 2025 02:59:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1743735600; bh=jooiBRiLZ5KXTeX7sTZYMvh719V+Qu5vq1GtZM6CWWA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=g/nOEnzC90yU3P0Hon/50j7bjUU/KNblbpYe76syN5W2QOwwzzoNvatmCdI8LKjVB GXztCu4IL/A0IORZ4wEe5qoYTPu5Pg2qdTI/GADX2IpCtl7Qlq3BQHZO/zX+1p8D+1 WWVmMPsdLpyQouxJvuQnVlL4t01jBhIea2T09Usomwxj5PZfFpxRCGDgrurnsztTdB LvDckdMjWvj4seYBkbJOQVVX3OvNQDV+Z/f9IycDIz/I8RnpgnpRFLLS+VkO+vHJ7g W15YUZMzei1FJHwfHbyfxPUCyc1xy9tvhheao1yd31ibmMsHDhN8tRCzytLaIxuI+5 QtnT/Tce6b/3w== From: "Rob Herring (Arm)" Date: Thu, 03 Apr 2025 21:59:35 -0500 Subject: [PATCH 14/19] dt-bindings: arm/cpus: Add schemas for "enable-method" dependencies Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250403-dt-cpu-schema-v1-14-076be7171a85@kernel.org> References: <20250403-dt-cpu-schema-v1-0-076be7171a85@kernel.org> In-Reply-To: <20250403-dt-cpu-schema-v1-0-076be7171a85@kernel.org> To: Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , "Rafael J. Wysocki" , Viresh Kumar , Matthias Brugger , AngeloGioacchino Del Regno , Vincenzo Frascino , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Bjorn Andersson , Konrad Dybcio , Thomas Bogendoerfer , Viresh Kumar , Nishanth Menon , Stephen Boyd , zhouyanjie@wanyeetech.com, Conor Dooley , Nicolas Ferre , Claudiu Beznea , Steen Hegelund , Daniel Machon , UNGLinuxDriver@microchip.com, Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Heiko Stuebner , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Geert Uytterhoeven , Magnus Damm Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-mips@vger.kernel.org, imx@lists.linux.dev, linux-rockchip@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-renesas-soc@vger.kernel.org X-Mailer: b4 0.15-dev Replace the prose for properties dependent on specific "enable-method" values with schemas defining the same requirements. Both "qcom,acc" and "qcom,saw" properties appear to be required for any of the Qualcomm enable-method values, so the schema is a bit simpler than what the text said. The references to arm/msm/qcom,saw2.txt and arm/msm/qcom,kpss-acc.txt are out of date, so just drop them. Signed-off-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/arm/cpus.yaml | 82 +++++++++++++++---------- 1 file changed, 49 insertions(+), 33 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 2e666b2a4dcd..963a9320cba8 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -273,8 +273,6 @@ properties: description: The DT specification defines this as 64-bit always, but some 32-bit Arm systems have used a 32-bit value which must be supported. - Required for systems that have an "enable-method" - property value of "spin-table". cpu-idle-states: $ref: /schemas/types.yaml#/definitions/phandle-array @@ -333,24 +331,13 @@ properties: qcom,saw: $ref: /schemas/types.yaml#/definitions/phandle - description: | - Specifies the SAW* node associated with this CPU. - - Required for systems that have an "enable-method" property - value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2" - - * arm/msm/qcom,saw2.txt + description: + Specifies the SAW node associated with this CPU. qcom,acc: $ref: /schemas/types.yaml#/definitions/phandle - description: | - Specifies the ACC* node associated with this CPU. - - Required for systems that have an "enable-method" property - value of "qcom,kpss-acc-v1", "qcom,kpss-acc-v2", "qcom,msm8226-smp" or - "qcom,msm8916-smp". - - * arm/msm/qcom,kpss-acc.txt + description: + Specifies the ACC node associated with this CPU. rockchip,pmu: $ref: /schemas/types.yaml#/definitions/phandle @@ -378,22 +365,51 @@ properties: formed by encoding the target CPU id into the low bits of the physical start address it should jump to. -if: - # If the enable-method property contains one of those values - properties: - enable-method: - contains: - enum: - - brcm,bcm11351-cpu-method - - brcm,bcm23550 - - brcm,bcm-nsp-smp - # and if enable-method is present - required: - - enable-method - -then: - required: - - secondary-boot-reg +allOf: + - if: + # If the enable-method property contains one of those values + properties: + enable-method: + contains: + enum: + - brcm,bcm11351-cpu-method + - brcm,bcm23550 + - brcm,bcm-nsp-smp + # and if enable-method is present + required: + - enable-method + then: + required: + - secondary-boot-reg + - if: + properties: + enable-method: + enum: + - spin-table + - renesas,r9a06g032-smp + required: + - enable-method + then: + required: + - cpu-release-addr + - if: + properties: + enable-method: + enum: + - qcom,kpss-acc-v1 + - qcom,kpss-acc-v2 + - qcom,msm8226-smp + - qcom,msm8916-smp + required: + - enable-method + then: + required: + - qcom,acc + - qcom,saw + else: + properties: + qcom,acc: false + qcom,saw: false required: - device_type From patchwork Fri Apr 4 02:59:36 2025 Content-Type: text/plain; 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b=JmBEkMMoTM8UCzNLKfBPMpj0d+1HrhnF5MuDUE27fULruswO4bqwS4W6EnD6ulP/OhaaH8Ce7d6C4crdaHcDoEcV2loU2ZtoPQTzfF3CPB83j54+gG4Cs6ph9bK+nqdCcJ3PAynx+k3FWZFN2FMuwr3iF2uuBRftLWvKUj+LiEU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=dMWjOXGo; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="dMWjOXGo" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5C0E7C4CEEA; Fri, 4 Apr 2025 03:00:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1743735601; bh=6cslgmm9oQIu/lOy/Nngvpo3/Efl2kNGCI97+vDsecU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=dMWjOXGofzF2+tDya9v6l8znJNIr0XFdwvGI+daCjlkFRLuMzx9sNn4HHfNMsEjWt pgrdJOHr0uVGh9HgUr/nTO+5y6FiiQlMDGsELglKzmI+PqZrG58NBPEDcwy8l8HpKc JOOXdTwbEZ1iNhXJkRnKTCideHzOnBoxGrg/0mNfDVKWWmx9xxz/wMtFnStrhM473Q 5bK2NAeUuwKQJKl6yijneJ+QIiZ4zLzrzf4ypXsZNFc16VAyE2aZgwAl/6H63lCYua EX5vmVkwswaYPlmACGBIfBBDS5IdDS1y/zNsjyKj7uoJoq4RplRjGnqafkptFbZBzh yDi2XjUD/mJ1Q== From: "Rob Herring (Arm)" Date: Thu, 03 Apr 2025 21:59:36 -0500 Subject: [PATCH 15/19] dt-bindings: arm/cpus: Re-wrap 'description' entries Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250403-dt-cpu-schema-v1-15-076be7171a85@kernel.org> References: <20250403-dt-cpu-schema-v1-0-076be7171a85@kernel.org> In-Reply-To: <20250403-dt-cpu-schema-v1-0-076be7171a85@kernel.org> To: Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , "Rafael J. Wysocki" , Viresh Kumar , Matthias Brugger , AngeloGioacchino Del Regno , Vincenzo Frascino , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Bjorn Andersson , Konrad Dybcio , Thomas Bogendoerfer , Viresh Kumar , Nishanth Menon , Stephen Boyd , zhouyanjie@wanyeetech.com, Conor Dooley , Nicolas Ferre , Claudiu Beznea , Steen Hegelund , Daniel Machon , UNGLinuxDriver@microchip.com, Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Heiko Stuebner , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Geert Uytterhoeven , Magnus Damm Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-mips@vger.kernel.org, imx@lists.linux.dev, linux-rockchip@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-renesas-soc@vger.kernel.org X-Mailer: b4 0.15-dev Some of the 'description' entries have odd line wrapping and incorrect YAML block modifiers. The 'description' entries should typically wrap at 80 chars. Reformat the entries to follow that along with using '>' modifiers as appropriate. Signed-off-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/arm/cpus.yaml | 85 +++++++++++-------------- 1 file changed, 36 insertions(+), 49 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 963a9320cba8..3e76de3e950d 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -10,9 +10,9 @@ maintainers: - Lorenzo Pieralisi description: |+ - The device tree allows to describe the layout of CPUs in a system through - the "cpus" node, which in turn contains a number of subnodes (ie "cpu") - defining properties for every cpu. + The device tree allows to describe the layout of CPUs in a system through the + "cpus" node, which in turn contains a number of subnodes (ie "cpu") defining + properties for every cpu. Bindings for CPU nodes follow the Devicetree Specification, available from: @@ -41,45 +41,40 @@ description: |+ properties: reg: maxItems: 1 - description: | - Usage and definition depend on ARM architecture version and - configuration: + description: > + Usage and definition depend on ARM architecture version and configuration: - On uniprocessor ARM architectures previous to v7 - this property is required and must be set to 0. + On uniprocessor ARM architectures previous to v7 this property is required + and must be set to 0. - On ARM 11 MPcore based systems this property is - required and matches the CPUID[11:0] register bits. + On ARM 11 MPcore based systems this property is required and matches the + CPUID[11:0] register bits. - Bits [11:0] in the reg cell must be set to - bits [11:0] in CPU ID register. + Bits [11:0] in the reg cell must be set to bits [11:0] in CPU ID register. All other bits in the reg cell must be set to 0. - On 32-bit ARM v7 or later systems this property is - required and matches the CPU MPIDR[23:0] register - bits. + On 32-bit ARM v7 or later systems this property is required and matches + the CPU MPIDR[23:0] register bits. - Bits [23:0] in the reg cell must be set to - bits [23:0] in MPIDR. + Bits [23:0] in the reg cell must be set to bits [23:0] in MPIDR. All other bits in the reg cell must be set to 0. - On ARM v8 64-bit systems this property is required - and matches the MPIDR_EL1 register affinity bits. + On ARM v8 64-bit systems this property is required and matches the + MPIDR_EL1 register affinity bits. * If cpus node's #address-cells property is set to 2 - The first reg cell bits [7:0] must be set to - bits [39:32] of MPIDR_EL1. + The first reg cell bits [7:0] must be set to bits [39:32] of + MPIDR_EL1. - The second reg cell bits [23:0] must be set to - bits [23:0] of MPIDR_EL1. + The second reg cell bits [23:0] must be set to bits [23:0] of + MPIDR_EL1. * If cpus node's #address-cells property is set to 1 - The reg cell bits [23:0] must be set to bits [23:0] - of MPIDR_EL1. + The reg cell bits [23:0] must be set to bits [23:0] of MPIDR_EL1. All other bits in the reg cells must be set to 0. @@ -278,29 +273,26 @@ properties: $ref: /schemas/types.yaml#/definitions/phandle-array items: maxItems: 1 - description: | - List of phandles to idle state nodes supported - by this cpu (see ./idle-states.yaml). + description: + List of phandles to idle state nodes supported by this cpu (see + ./idle-states.yaml). capacity-dmips-mhz: description: u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in - DMIPS/MHz, relative to highest capacity-dmips-mhz - in the system. + DMIPS/MHz, relative to highest capacity-dmips-mhz in the system. cci-control-port: true dynamic-power-coefficient: $ref: /schemas/types.yaml#/definitions/uint32 - description: - A u32 value that represents the running time dynamic - power coefficient in units of uW/MHz/V^2. The - coefficient can either be calculated from power + description: > + A u32 value that represents the running time dynamic power coefficient in + units of uW/MHz/V^2. The coefficient can either be calculated from power measurements or derived by analysis. - The dynamic power consumption of the CPU is - proportional to the square of the Voltage (V) and - the clock frequency (f). The coefficient is used to + The dynamic power consumption of the CPU is proportional to the square of + the Voltage (V) and the clock frequency (f). The coefficient is used to calculate the dynamic power as below - Pdyn = dynamic-power-coefficient * V^2 * f @@ -309,10 +301,6 @@ properties: performance-domains: maxItems: 1 - description: - List of phandles and performance domain specifiers, as defined by - bindings of the performance domain provider. See also - dvfs/performance-domain.yaml. power-domains: description: @@ -341,22 +329,21 @@ properties: rockchip,pmu: $ref: /schemas/types.yaml#/definitions/phandle - description: | + description: > Specifies the syscon node controlling the cpu core power domains. - Optional for systems that have an "enable-method" - property value of "rockchip,rk3066-smp" - While optional, it is the preferred way to get access to - the cpu-core power-domains. + Optional for systems that have an "enable-method" property value of + "rockchip,rk3066-smp". While optional, it is the preferred way to get + access to the cpu-core power-domains. secondary-boot-reg: $ref: /schemas/types.yaml#/definitions/uint32 - description: | + description: > Required for systems that have an "enable-method" property value of "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp". - This includes the following SoCs: | - BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550 + This includes the following SoCs: + BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550, BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312 The secondary-boot-reg property is a u32 value that specifies the From patchwork Fri Apr 4 02:59:37 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring \(Arm\)" X-Patchwork-Id: 878368 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F306A1CF284; Fri, 4 Apr 2025 03:00:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743735603; cv=none; b=Uoe3bVOQmPbm/SJWud15QFajmFy1DRlXNobKBcbtL3SVEqNQ68QtHPWBu7camP8M077jsVUsBpz0sYUyOVhXfbA7RHJmV2B/LVCZhYvDGjhCFBYVuVMjRXLqNWQx+BVuiSOtw1hRmNEIRx7L0tzJz8HbMNng5phXfEB7NUTmQuk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743735603; c=relaxed/simple; bh=oVGi9LwOUr1+hNrJwoDMMLjyDofanD4Qd7/JOe/aRMw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Lpkmv558NhZhl+HiMcBaADdICvimo36idwzaqvil3wrhG0+iBtOSKq1LcJoW9kRD9rMLGCpffewUk4qbrZeTm/SGxJ2Vaf3VST29qd2eEKr1xuWqLo/IGR8TDZ1AQnmHeipigQHQs/ltKh9U6/NmePulb3orbuWg/to8OlZWUp4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=uK9nKufj; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="uK9nKufj" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A1A8EC4CEE7; Fri, 4 Apr 2025 03:00:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1743735602; bh=oVGi9LwOUr1+hNrJwoDMMLjyDofanD4Qd7/JOe/aRMw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=uK9nKufjP+IzSykFxQTjmnYd2dqL7STkiN6hiK8+ji7QTyS6gWUiu1u9C2OsGHn4A UUVKxicewOK3olz4cK7R8+rvVygmEeyOjYJ/XybvE2hSdAaUShwA26AC3kdkFRm0Ke PnwjgfqxaA+k1p/yF9dzhXAO38jVYb7c1vGDsm5R6/bWI22AYdeZdV8SwVwUo/uph6 8njaUuSZePjfDVosNksNGLsMU5CGBgO2SMVw3zxckT0uAcfgSYU7Gf4VdpmsDExi8O i8AjKEoK9kCcyO2xwncvhJekKB/D/3D6qqXPOB/9b35CSHw88934H5EB3tERPiGyrB plN55+SUAVCew== From: "Rob Herring (Arm)" Date: Thu, 03 Apr 2025 21:59:37 -0500 Subject: [PATCH 16/19] dt-bindings: Reference opp-v1 schema in CPU schemas Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250403-dt-cpu-schema-v1-16-076be7171a85@kernel.org> References: <20250403-dt-cpu-schema-v1-0-076be7171a85@kernel.org> In-Reply-To: <20250403-dt-cpu-schema-v1-0-076be7171a85@kernel.org> To: Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , "Rafael J. Wysocki" , Viresh Kumar , Matthias Brugger , AngeloGioacchino Del Regno , Vincenzo Frascino , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Bjorn Andersson , Konrad Dybcio , Thomas Bogendoerfer , Viresh Kumar , Nishanth Menon , Stephen Boyd , zhouyanjie@wanyeetech.com, Conor Dooley , Nicolas Ferre , Claudiu Beznea , Steen Hegelund , Daniel Machon , UNGLinuxDriver@microchip.com, Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Heiko Stuebner , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Geert Uytterhoeven , Magnus Damm Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-mips@vger.kernel.org, imx@lists.linux.dev, linux-rockchip@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-renesas-soc@vger.kernel.org X-Mailer: b4 0.15-dev The opp-v1 binding is only used in MIPS and arm32 CPU nodes, so add a $ref to it in the CPU schemas and drop the "select". As opp-v1 has long been deprecated, mark it as such. Signed-off-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/arm/cpus.yaml | 1 + Documentation/devicetree/bindings/mips/cpus.yaml | 3 ++- Documentation/devicetree/bindings/opp/opp-v1.yaml | 2 +- 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 3e76de3e950d..3d2b6286efb8 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -353,6 +353,7 @@ properties: physical start address it should jump to. allOf: + - $ref: /schemas/opp/opp-v1.yaml# - if: # If the enable-method property contains one of those values properties: diff --git a/Documentation/devicetree/bindings/mips/cpus.yaml b/Documentation/devicetree/bindings/mips/cpus.yaml index a85137add668..471373ad0cfb 100644 --- a/Documentation/devicetree/bindings/mips/cpus.yaml +++ b/Documentation/devicetree/bindings/mips/cpus.yaml @@ -50,6 +50,7 @@ properties: device_type: true allOf: + - $ref: /schemas/opp/opp-v1.yaml# - if: properties: compatible: @@ -68,7 +69,7 @@ required: - compatible - reg -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/opp/opp-v1.yaml b/Documentation/devicetree/bindings/opp/opp-v1.yaml index 07e26c267815..1b59b103dab6 100644 --- a/Documentation/devicetree/bindings/opp/opp-v1.yaml +++ b/Documentation/devicetree/bindings/opp/opp-v1.yaml @@ -18,7 +18,7 @@ description: |+ This binding only supports voltage-frequency pairs. -select: true +deprecated: true properties: operating-points: From patchwork Fri Apr 4 02:59:38 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring \(Arm\)" X-Patchwork-Id: 878530 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 924E51DE2A9; Fri, 4 Apr 2025 03:00:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743735604; cv=none; b=gE8ycj5biaEva0y95HqyU+CoKMiBPPWKc9qW5GnlDycYrENky/XtjJG/CT/DIuH3oj0+4TIBBKRyhCLeslqyGqvvbTmGhUft35HRhKe3vWO5MgvoFT61rl7X1o5btvSvzLuiQF/jaSnKc+9jsc4OYlhtov/Nhg3V9EUHJ7NwBrI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743735604; c=relaxed/simple; bh=qt04cpMtce1Dpx+XQO1X0rXON/Jr6p5yPdGytRb8Eas=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=aAzoLtlrtUNpeGssoRdFpjT4hfeWlKwRhc6thYTnzv2jA+q0kJOz8m/uv72ySkhaSrfnUWTn04VFlEdZjHmZD1Ft+5+i0SOSRfWKhY91xJA65ks86wXkfHI6+CWKXJ722Zp1WOV8wmXtuoxxdXaz5G3yANq+LlXAbYt3WyA+NBI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Q/n2/+qA; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Q/n2/+qA" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D06E7C4CEE3; Fri, 4 Apr 2025 03:00:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1743735604; bh=qt04cpMtce1Dpx+XQO1X0rXON/Jr6p5yPdGytRb8Eas=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Q/n2/+qAbQ4lqGimi3B39jw61JwhYStJxbhIKpQByr6sATNhR0pByuj78+ofl0w3b mDYpwWD136Zeead5FiF3meTxotK0fSVSKY+pLIMCy6nHHT2XntZ2hIuZGE0CofixOf 66GxYVVp8SPCEKljznidvtg8tyHPaWU3lqYPRODKskhUIdq8wmiyjOHnbX1UV5O/Hd 1zXJDjHiwOeHhIiGKBrIEfSSy+5HgAQSIgjQkV+JNHxsvQiURpsgi3Auk/qhrqM7bU xft6O+le2YtCNm5Wk4E3pmvSVZajHPPBt2o9L5ObkWzDIY4YhQ+RA9wpGjeEYy7Lxk JSnSa3SGRCJlA== From: "Rob Herring (Arm)" Date: Thu, 03 Apr 2025 21:59:38 -0500 Subject: [PATCH 17/19] dt-bindings: arm/cpus: Add missing properties Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250403-dt-cpu-schema-v1-17-076be7171a85@kernel.org> References: <20250403-dt-cpu-schema-v1-0-076be7171a85@kernel.org> In-Reply-To: <20250403-dt-cpu-schema-v1-0-076be7171a85@kernel.org> To: Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , "Rafael J. Wysocki" , Viresh Kumar , Matthias Brugger , AngeloGioacchino Del Regno , Vincenzo Frascino , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Bjorn Andersson , Konrad Dybcio , Thomas Bogendoerfer , Viresh Kumar , Nishanth Menon , Stephen Boyd , zhouyanjie@wanyeetech.com, Conor Dooley , Nicolas Ferre , Claudiu Beznea , Steen Hegelund , Daniel Machon , UNGLinuxDriver@microchip.com, Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Heiko Stuebner , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Geert Uytterhoeven , Magnus Damm Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-mips@vger.kernel.org, imx@lists.linux.dev, linux-rockchip@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-renesas-soc@vger.kernel.org X-Mailer: b4 0.15-dev The Arm CPU schema is missing a number of properties already in use. This has gone unnoticed as extra properties have not been restricted. Add a missing reference to cpu.yaml, and add all the missing properties. As "clock-latency" and "voltage-tolerance" are related to opp-v1, add those properties to the opp-v1.yaml schema. With this, other properties can be prevented from creeping in with 'unevaluatedProperties: false'. Signed-off-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/arm/cpus.yaml | 46 ++++++++++++++++++++++- Documentation/devicetree/bindings/opp/opp-v1.yaml | 16 ++++++++ 2 files changed, 61 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 3d2b6286efb8..6f74ebfd38df 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -299,6 +299,16 @@ properties: where voltage is in V, frequency is in MHz. + interconnects: + minItems: 1 + maxItems: 2 + + nvmem-cells: + maxItems: 1 + + nvmem-cell-names: + const: speed_grade + performance-domains: maxItems: 1 @@ -317,6 +327,31 @@ properties: corresponding to the index of an SCMI performance domain provider, must be "perf". + resets: + maxItems: 1 + + arm-supply: + deprecated: true + description: Use 'cpu-supply' instead + + cpu0-supply: + deprecated: true + description: Use 'cpu-supply' instead + + mem-supply: true + + proc-supply: + deprecated: true + description: Use 'cpu-supply' instead + + sram-supply: + deprecated: true + description: Use 'mem-supply' instead + + mediatek,cci: + $ref: /schemas/types.yaml#/definitions/phandle + description: Link to Mediatek Cache Coherent Interconnect + qcom,saw: $ref: /schemas/types.yaml#/definitions/phandle description: @@ -327,6 +362,11 @@ properties: description: Specifies the ACC node associated with this CPU. + qcom,freq-domain: + description: Specifies the QCom CPUFREQ HW associated with the CPU. + $ref: /schemas/types.yaml#/definitions/phandle-array + maxItems: 1 + rockchip,pmu: $ref: /schemas/types.yaml#/definitions/phandle description: > @@ -352,7 +392,11 @@ properties: formed by encoding the target CPU id into the low bits of the physical start address it should jump to. + thermal-idle: + type: object + allOf: + - $ref: /schemas/cpu.yaml# - $ref: /schemas/opp/opp-v1.yaml# - if: # If the enable-method property contains one of those values @@ -407,7 +451,7 @@ required: dependencies: rockchip,pmu: [enable-method] -additionalProperties: true +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/opp/opp-v1.yaml b/Documentation/devicetree/bindings/opp/opp-v1.yaml index 1b59b103dab6..61c080e50859 100644 --- a/Documentation/devicetree/bindings/opp/opp-v1.yaml +++ b/Documentation/devicetree/bindings/opp/opp-v1.yaml @@ -21,6 +21,18 @@ description: |+ deprecated: true properties: + clock-latency: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The latency in nanoseconds for clock changes. Use OPP tables for new + designs instead. + + voltage-tolerance: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 10 + description: + The voltage tolerance in percent. Use OPP tables for new designs instead. + operating-points: $ref: /schemas/types.yaml#/definitions/uint32-matrix items: @@ -28,8 +40,12 @@ properties: - description: Frequency in kHz - description: Voltage for OPP in uV +dependencies: + clock-latency: [ operating-points ] + voltage-tolerance: [ operating-points ] additionalProperties: true + examples: - | cpus { From patchwork Fri Apr 4 02:59:39 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring \(Arm\)" X-Patchwork-Id: 878367 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BFEA21E1DF7; Fri, 4 Apr 2025 03:00:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743735605; cv=none; b=ABvrrU/lKaL3W4v/6Sw/i+ChVeMTH7isquA1HwqNUn+liK8wQaECleIqqdArbopjIkIvLK3RPSm5+aBUepIdXlppioUc7y6NVZOfDE2nRTzz58gr8cdGzLZdzrKT62C/s2sZeemUBTLhZjmtImdoe8oBDce90T+x/glFPUN7Luc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743735605; c=relaxed/simple; bh=VTRjZwZIi8q294b4YyTHrd0BG++P7ph5Qta/NAw+IT8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ZJ/603cTIzp5ecrMS613WuWn/ZyXkXVjlXR/LtkD1jwznHSSUQCpi3/a9oO2VwIavbfXnfhpdaFt0vox4f+GdEkU2NG1Kfny1gOO7CciC06U/8AZZwHThm9kvIitipEqn3Ac+wYjCRwUeJrLROgWGBZkMyTT9rCKkoM//nFpv7A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=BIydFOU9; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="BIydFOU9" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1030DC4CEE9; Fri, 4 Apr 2025 03:00:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1743735605; bh=VTRjZwZIi8q294b4YyTHrd0BG++P7ph5Qta/NAw+IT8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=BIydFOU9aJ9WhFAro8qghVTYQjHFs1Y2yZH4wibAW+ULHXKPCLPkRsy8d5oEx+P1/ 7Hf6x9eRUkjhWNVFDw8HAyxVL60tteeZLa+l0vLO0aXmI7gnLie+EpmL2PS11qVJYp xtIncqHBwXONuQspx+OM+dasoKJT4dzSHFN57/cN4VWkCms54jj2egjQDdMFmuhRKE mLjNtcfcBBslTMrt3O/4G+vg3XGVeaNpnOm2YoZvIupH38/6PxnwbZhh+59CyPHO7k rN6g4n76GbbVf3pd7BHkiVfkXnCHHO23yIhvWKPkp9pE4zZ+IRqV+P5Mdn30fiwwoM XayRRMFqSmyww== From: "Rob Herring (Arm)" Date: Thu, 03 Apr 2025 21:59:39 -0500 Subject: [PATCH 18/19] dt-bindings: arm/cpus: Add power-domains constraints Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250403-dt-cpu-schema-v1-18-076be7171a85@kernel.org> References: <20250403-dt-cpu-schema-v1-0-076be7171a85@kernel.org> In-Reply-To: <20250403-dt-cpu-schema-v1-0-076be7171a85@kernel.org> To: Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , "Rafael J. Wysocki" , Viresh Kumar , Matthias Brugger , AngeloGioacchino Del Regno , Vincenzo Frascino , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Bjorn Andersson , Konrad Dybcio , Thomas Bogendoerfer , Viresh Kumar , Nishanth Menon , Stephen Boyd , zhouyanjie@wanyeetech.com, Conor Dooley , Nicolas Ferre , Claudiu Beznea , Steen Hegelund , Daniel Machon , UNGLinuxDriver@microchip.com, Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Heiko Stuebner , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Geert Uytterhoeven , Magnus Damm Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-mips@vger.kernel.org, imx@lists.linux.dev, linux-rockchip@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-renesas-soc@vger.kernel.org X-Mailer: b4 0.15-dev The "power-domains" and "power-domains-names" properties are missing any constraints. Add the constraints and drop the generic descriptions. Signed-off-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/arm/cpus.yaml | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 6f74ebfd38df..5bd5822db8af 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -313,19 +313,15 @@ properties: maxItems: 1 power-domains: - description: - List of phandles and PM domain specifiers, as defined by bindings of the - PM domain provider (see also ../power_domain.txt). + maxItems: 1 power-domain-names: description: - A list of power domain name strings sorted in the same order as the - power-domains property. - For PSCI based platforms, the name corresponding to the index of the PSCI PM domain provider, must be "psci". For SCMI based platforms, the name corresponding to the index of an SCMI performance domain provider, must be "perf". + enum: [ psci, perf, cpr ] resets: maxItems: 1 From patchwork Fri Apr 4 02:59:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring \(Arm\)" X-Patchwork-Id: 878529 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 21FFE1EA7D3; Fri, 4 Apr 2025 03:00:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743735608; cv=none; b=frHoOBV7NCnisA2+wTi4HiKeuSxTYqH/revKdfIvqSAs8HZtgCXQ9vOJclGu1uo7YHKA0VwJSvdian7OwFzV7gXY0v75xWdTVJLZPBRkZEonaKlEr/zhwEMVms0aqPPQSQ8/0g9e2hJhromRgqgj6QWYIWEpXxt4vHF9EcHWP1g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743735608; c=relaxed/simple; bh=+bglFes+JWUyYqhoWvdBTyyAUTU6Hu68wW9iKCwLBnY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=T3vzCW2csWyQQwS3YUVXhlHwsgdSP1pP5zga5dn5g/rM8iZ/laffF1ocfXgt7Yqnosc6LquwTtSq+u/SITm2gSE65OujzqnB2tnaPh5Yo51D4YaF6BtntGkuc9DsCR4dHLV0vi74CJjENCGN17TKddxpUME/aaLQHGA3DTt8ak4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ZzYCy357; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ZzYCy357" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 53F80C4CEE3; Fri, 4 Apr 2025 03:00:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1743735606; bh=+bglFes+JWUyYqhoWvdBTyyAUTU6Hu68wW9iKCwLBnY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=ZzYCy3572wAcb8VXN5IFR/xxSAoz+Ll8686K4A7qg8wIFI38fvJ8QSFQwX/eI7L6g 9GswgwONrsiJoNkwsyrplALvNfCFcd8MaJKyb2kpDe/SMbAsiOEjmnUMrHu/+qEU44 fc6+c+FKbR7mO9dkD4/sTpNP2Yvqw5zu1a79e2a7C/Y3mq9VrjXacawISc3gE7kwgm R1rrrZ20y/p8is2HZkHzkIPf4pvhIgTK1ctQnusjL0OrXjK1ZXlPMNFNLcVp0TxB9Z E9pl1+SlJ/3xi8ckKlkbV5SPf06nhMkBkco7rmYFgKHjgOa8xRquq6E/AnK3C/a00M T7EX1lGR7l7NQ== From: "Rob Herring (Arm)" Date: Thu, 03 Apr 2025 21:59:40 -0500 Subject: [PATCH 19/19] dt-bindings: cpufreq: Drop redundant Mediatek binding Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250403-dt-cpu-schema-v1-19-076be7171a85@kernel.org> References: <20250403-dt-cpu-schema-v1-0-076be7171a85@kernel.org> In-Reply-To: <20250403-dt-cpu-schema-v1-0-076be7171a85@kernel.org> To: Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , "Rafael J. Wysocki" , Viresh Kumar , Matthias Brugger , AngeloGioacchino Del Regno , Vincenzo Frascino , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Bjorn Andersson , Konrad Dybcio , Thomas Bogendoerfer , Viresh Kumar , Nishanth Menon , Stephen Boyd , zhouyanjie@wanyeetech.com, Conor Dooley , Nicolas Ferre , Claudiu Beznea , Steen Hegelund , Daniel Machon , UNGLinuxDriver@microchip.com, Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Heiko Stuebner , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Geert Uytterhoeven , Magnus Damm Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-mips@vger.kernel.org, imx@lists.linux.dev, linux-rockchip@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-renesas-soc@vger.kernel.org X-Mailer: b4 0.15-dev The Mediatek CPUFreq binding document just describes properties from the CPU node which the driver uses. This is redundant as all the properties are described in the arm/cpus.yaml schema. Signed-off-by: Rob Herring (Arm) --- .../bindings/cpufreq/cpufreq-mediatek.txt | 250 --------------------- 1 file changed, 250 deletions(-) diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt deleted file mode 100644 index e0a4ba599abc..000000000000 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt +++ /dev/null @@ -1,250 +0,0 @@ -Binding for MediaTek's CPUFreq driver -===================================== - -Required properties: -- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names. -- clock-names: Should contain the following: - "cpu" - The multiplexer for clock input of CPU cluster. - "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock - source (usually MAINPLL) when the original CPU PLL is under - transition and not stable yet. - Please refer to Documentation/devicetree/bindings/clock/clock-bindings.txt for - generic clock consumer properties. -- operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp-v2.yaml - for detail. -- proc-supply: Regulator for Vproc of CPU cluster. - -Optional properties: -- sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver - needs to do "voltage tracking" to step by step scale up/down Vproc and - Vsram to fit SoC specific needs. When absent, the voltage scaling - flow is handled by hardware, hence no software "voltage tracking" is - needed. -- mediatek,cci: - Used to confirm the link status between cpufreq and mediatek cci. Because - cpufreq and mediatek cci could share the same regulator in some MediaTek SoCs. - To prevent the issue of high frequency and low voltage, we need to use this - property to make sure mediatek cci is ready. - For details of mediatek cci, please refer to - Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml -- #cooling-cells: - For details, please refer to - Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml - -Example 1 (MT7623 SoC): - - cpu_opp_table: opp_table { - compatible = "operating-points-v2"; - opp-shared; - - opp-598000000 { - opp-hz = /bits/ 64 <598000000>; - opp-microvolt = <1050000>; - }; - - opp-747500000 { - opp-hz = /bits/ 64 <747500000>; - opp-microvolt = <1050000>; - }; - - opp-1040000000 { - opp-hz = /bits/ 64 <1040000000>; - opp-microvolt = <1150000>; - }; - - opp-1196000000 { - opp-hz = /bits/ 64 <1196000000>; - opp-microvolt = <1200000>; - }; - - opp-1300000000 { - opp-hz = /bits/ 64 <1300000000>; - opp-microvolt = <1300000>; - }; - }; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - clocks = <&infracfg CLK_INFRA_CPUSEL>, - <&apmixedsys CLK_APMIXED_MAINPLL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cpu_opp_table>; - #cooling-cells = <2>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x1>; - operating-points-v2 = <&cpu_opp_table>; - }; - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x2>; - operating-points-v2 = <&cpu_opp_table>; - }; - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x3>; - operating-points-v2 = <&cpu_opp_table>; - }; - -Example 2 (MT8173 SoC): - cpu_opp_table_a: opp_table_a { - compatible = "operating-points-v2"; - opp-shared; - - opp-507000000 { - opp-hz = /bits/ 64 <507000000>; - opp-microvolt = <859000>; - }; - - opp-702000000 { - opp-hz = /bits/ 64 <702000000>; - opp-microvolt = <908000>; - }; - - opp-1001000000 { - opp-hz = /bits/ 64 <1001000000>; - opp-microvolt = <983000>; - }; - - opp-1105000000 { - opp-hz = /bits/ 64 <1105000000>; - opp-microvolt = <1009000>; - }; - - opp-1183000000 { - opp-hz = /bits/ 64 <1183000000>; - opp-microvolt = <1028000>; - }; - - opp-1404000000 { - opp-hz = /bits/ 64 <1404000000>; - opp-microvolt = <1083000>; - }; - - opp-1508000000 { - opp-hz = /bits/ 64 <1508000000>; - opp-microvolt = <1109000>; - }; - - opp-1573000000 { - opp-hz = /bits/ 64 <1573000000>; - opp-microvolt = <1125000>; - }; - }; - - cpu_opp_table_b: opp_table_b { - compatible = "operating-points-v2"; - opp-shared; - - opp-507000000 { - opp-hz = /bits/ 64 <507000000>; - opp-microvolt = <828000>; - }; - - opp-702000000 { - opp-hz = /bits/ 64 <702000000>; - opp-microvolt = <867000>; - }; - - opp-1001000000 { - opp-hz = /bits/ 64 <1001000000>; - opp-microvolt = <927000>; - }; - - opp-1209000000 { - opp-hz = /bits/ 64 <1209000000>; - opp-microvolt = <968000>; - }; - - opp-1404000000 { - opp-hz = /bits/ 64 <1007000000>; - opp-microvolt = <1028000>; - }; - - opp-1612000000 { - opp-hz = /bits/ 64 <1612000000>; - opp-microvolt = <1049000>; - }; - - opp-1807000000 { - opp-hz = /bits/ 64 <1807000000>; - opp-microvolt = <1089000>; - }; - - opp-1989000000 { - opp-hz = /bits/ 64 <1989000000>; - opp-microvolt = <1125000>; - }; - }; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x000>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&infracfg CLK_INFRA_CA53SEL>, - <&apmixedsys CLK_APMIXED_MAINPLL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cpu_opp_table_a>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x001>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&infracfg CLK_INFRA_CA53SEL>, - <&apmixedsys CLK_APMIXED_MAINPLL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cpu_opp_table_a>; - }; - - cpu2: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x100>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&infracfg CLK_INFRA_CA72SEL>, - <&apmixedsys CLK_APMIXED_MAINPLL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cpu_opp_table_b>; - }; - - cpu3: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x101>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&infracfg CLK_INFRA_CA72SEL>, - <&apmixedsys CLK_APMIXED_MAINPLL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cpu_opp_table_b>; - }; - - &cpu0 { - proc-supply = <&mt6397_vpca15_reg>; - }; - - &cpu1 { - proc-supply = <&mt6397_vpca15_reg>; - }; - - &cpu2 { - proc-supply = <&da9211_vcpu_reg>; - sram-supply = <&mt6397_vsramca7_reg>; - }; - - &cpu3 { - proc-supply = <&da9211_vcpu_reg>; - sram-supply = <&mt6397_vsramca7_reg>; - };