From patchwork Mon Apr 7 12:06:25 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Darren.Ye" X-Patchwork-Id: 878793 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 97B90226520; Mon, 7 Apr 2025 12:08:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744027715; cv=none; b=egB72+52tquu21YpGErbYHA+1SBJSuFNTTsuRGpu7p+kRcmF2DeRxIkD1eKsahk3J4lUQtnPZKBd1xXfrJGHiiKy1C1VFfxi4gh1dzLzFPeHlH7ktrTRuWGvgL5jV2ZVJmZruyWYId6vS9okgaGYtudRZlkn5qgg0SXlMG9oghk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744027715; c=relaxed/simple; bh=muPUZ77kfA9Av545vi+9iJF31G7JcE9qkimniOnh6bM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=NMAp3m63moLx6mXFvut6HliwlCO8v2JIZv4fnR8cljqqreYqvOpE6zjq0Idi5uvVNp7+meDZe4jS2R8MoMsFifuQkz5MkwUbYR84PlG3+q5VtObWNBPZmcrDwQve2oIZCLxs0ptPBuIXvKeInqRRDz24bTMfa7EjEiclWriFd2A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=AKM4T2ei; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="AKM4T2ei" X-UUID: 02f4a42413a911f0aae1fd9735fae912-20250407 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=t45h2K/DAsVv7bzVikraPn5qJ6SE+6gaua4uz6B/apM=; b=AKM4T2eizWenDdICVtHFiP+EQx3h89yYnfdd9VovVusjkVTNpIQ0dYWfgGks6sobm87HbWGtuuylffj/LxOMapjLtV2E64OyZCFo0V6K0CdRpZLkcxeatTq0zw2XPJBCbsOZSaZpo8T4iQbSho8hshVbvS0MiKbsk6aP+QkCBac=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.2.1, REQID:444e1aac-dab8-46c5-9137-913a1f268851, IP:0, UR L:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION:r elease,TS:0 X-CID-META: VersionHash:0ef645f, CLOUDID:6c14c7a5-c619-47e3-a41b-90eedbf5b947, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:nil,Content:0|50,EDM:-3 ,IP:nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV :0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 02f4a42413a911f0aae1fd9735fae912-20250407 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 662049071; Mon, 07 Apr 2025 20:08:26 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Mon, 7 Apr 2025 20:08:25 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Mon, 7 Apr 2025 20:08:24 +0800 From: Darren.Ye To: Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Jaroslav Kysela , Takashi Iwai , Linus Walleij , Bartosz Golaszewski CC: , , , , , , Darren Ye Subject: [PATCH v2 01/11] ASoC: mediatek: common: modify mtk afe common driver for mt8196 Date: Mon, 7 Apr 2025 20:06:25 +0800 Message-ID: <20250407120708.26495-2-darren.ye@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250407120708.26495-1-darren.ye@mediatek.com> References: <20250407120708.26495-1-darren.ye@mediatek.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N From: Darren Ye update the mtk_memif_set_channel interface for the mt8196 platform. Signed-off-by: Darren Ye --- sound/soc/mediatek/common/mtk-afe-fe-dai.c | 23 +++++++++++++--------- sound/soc/mediatek/common/mtk-afe-fe-dai.h | 1 + sound/soc/mediatek/common/mtk-base-afe.h | 13 ++++++++++++ 3 files changed, 28 insertions(+), 9 deletions(-) diff --git a/sound/soc/mediatek/common/mtk-afe-fe-dai.c b/sound/soc/mediatek/common/mtk-afe-fe-dai.c index 3809068f5620..caf703faf424 100644 --- a/sound/soc/mediatek/common/mtk-afe-fe-dai.c +++ b/sound/soc/mediatek/common/mtk-afe-fe-dai.c @@ -459,8 +459,13 @@ int mtk_memif_set_channel(struct mtk_base_afe *afe, struct mtk_base_afe_memif *memif = &afe->memif[id]; unsigned int mono; - if (memif->data->mono_shift < 0) - return 0; + dev_dbg(afe->dev, "id: %d, channel: %d\n", id, channel); + + mono = memif->data->mono_invert ^ (channel == 1); + + if (memif->data->mono_shift > 0) + mtk_regmap_update_bits(afe->regmap, memif->data->mono_reg, + 0x1, mono, memif->data->mono_shift); if (memif->data->quad_ch_mask) { unsigned int quad_ch = (channel == 4) ? 1 : 0; @@ -470,11 +475,6 @@ int mtk_memif_set_channel(struct mtk_base_afe *afe, quad_ch, memif->data->quad_ch_shift); } - if (memif->data->mono_invert) - mono = (channel == 1) ? 0 : 1; - else - mono = (channel == 1) ? 1 : 0; - /* for specific configuration of memif mono mode */ if (memif->data->int_odd_flag_reg) mtk_regmap_update_bits(afe->regmap, @@ -482,8 +482,13 @@ int mtk_memif_set_channel(struct mtk_base_afe *afe, 1, mono, memif->data->int_odd_flag_shift); - return mtk_regmap_update_bits(afe->regmap, memif->data->mono_reg, - 1, mono, memif->data->mono_shift); + if (memif->data->ch_num_maskbit) { + mtk_regmap_update_bits(afe->regmap, memif->data->ch_num_reg, + memif->data->ch_num_maskbit, + channel, memif->data->ch_num_shift); + } + + return 0; } EXPORT_SYMBOL_GPL(mtk_memif_set_channel); diff --git a/sound/soc/mediatek/common/mtk-afe-fe-dai.h b/sound/soc/mediatek/common/mtk-afe-fe-dai.h index b6d0f2b27e86..b720c1dd8012 100644 --- a/sound/soc/mediatek/common/mtk-afe-fe-dai.h +++ b/sound/soc/mediatek/common/mtk-afe-fe-dai.h @@ -12,6 +12,7 @@ struct snd_soc_dai_ops; struct mtk_base_afe; struct mtk_base_afe_memif; +struct mtk_base_irq_data; int mtk_afe_fe_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai); diff --git a/sound/soc/mediatek/common/mtk-base-afe.h b/sound/soc/mediatek/common/mtk-base-afe.h index f51578b6c50a..01c27fe92e2f 100644 --- a/sound/soc/mediatek/common/mtk-base-afe.h +++ b/sound/soc/mediatek/common/mtk-base-afe.h @@ -53,9 +53,11 @@ struct mtk_base_memif_data { int enable_reg; int enable_shift; int hd_reg; + int hd_mask; int hd_shift; int hd_align_reg; int hd_align_mshift; + int hd_msb_shift; int msb_reg; int msb_shift; int msb_end_reg; @@ -65,6 +67,10 @@ struct mtk_base_memif_data { int ch_num_reg; int ch_num_shift; int ch_num_maskbit; + /* VUL 24~26 only for CM2 */ + int out_on_use_reg; + int out_on_use_mask; + int out_on_use_shift; /* playback memif only */ int pbuf_reg; int pbuf_mask; @@ -72,6 +78,9 @@ struct mtk_base_memif_data { int minlen_reg; int minlen_mask; int minlen_shift; + int maxlen_reg; + int maxlen_mask; + int maxlen_shift; }; struct mtk_base_irq_data { @@ -87,6 +96,10 @@ struct mtk_base_irq_data { int irq_clr_reg; int irq_clr_shift; int irq_status_shift; + int irq_ap_en_reg; + int irq_ap_en_shift; + int irq_scp_en_reg; + int irq_scp_en_shift; }; struct device; From patchwork Mon Apr 7 12:06:26 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Darren.Ye" X-Patchwork-Id: 879156 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B353922DFAB; Mon, 7 Apr 2025 12:10:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744027858; cv=none; b=ki65XrmDMk5YJNSMM/JWidcgCG8u/bZGSABnwi42YD2Oj6QhhxSXJ6s3hF4ASs3j44mOJJ8/zdm+CFQ0sUNRMliTQTIPxhIswtQ9pxsUW7q6lfGHuNlPTTdT6u0q9BJ0YLU+GlnxHkbof3HO5YaWrgiwJhJx/BK82yw8uVQ+NA8= ARC-Message-Signature: i=1; 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Mon, 07 Apr 2025 20:10:49 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by MTKMBS09N1.mediatek.inc (172.21.101.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Mon, 7 Apr 2025 20:10:47 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Mon, 7 Apr 2025 20:10:46 +0800 From: Darren.Ye To: Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Jaroslav Kysela , Takashi Iwai , Linus Walleij , Bartosz Golaszewski CC: , , , , , , Darren Ye Subject: [PATCH v2 02/11] ASoC: mediatek: common: modify mtk afe platform driver for mt8196 Date: Mon, 7 Apr 2025 20:06:26 +0800 Message-ID: <20250407120708.26495-3-darren.ye@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250407120708.26495-1-darren.ye@mediatek.com> References: <20250407120708.26495-1-darren.ye@mediatek.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N From: Darren Ye Mofify the pcm pointer interface to support 64-bit address access. Signed-off-by: Darren Ye --- .../mediatek/common/mtk-afe-platform-driver.c | 47 ++++++++++++------- .../mediatek/common/mtk-afe-platform-driver.h | 2 + 2 files changed, 33 insertions(+), 16 deletions(-) diff --git a/sound/soc/mediatek/common/mtk-afe-platform-driver.c b/sound/soc/mediatek/common/mtk-afe-platform-driver.c index 6b6330583941..a86594dca2b7 100644 --- a/sound/soc/mediatek/common/mtk-afe-platform-driver.c +++ b/sound/soc/mediatek/common/mtk-afe-platform-driver.c @@ -86,29 +86,44 @@ snd_pcm_uframes_t mtk_afe_pcm_pointer(struct snd_soc_component *component, const struct mtk_base_memif_data *memif_data = memif->data; struct regmap *regmap = afe->regmap; struct device *dev = afe->dev; - int reg_ofs_base = memif_data->reg_ofs_base; - int reg_ofs_cur = memif_data->reg_ofs_cur; - unsigned int hw_ptr = 0, hw_base = 0; - int ret, pcm_ptr_bytes; - - ret = regmap_read(regmap, reg_ofs_cur, &hw_ptr); - if (ret || hw_ptr == 0) { - dev_err(dev, "%s hw_ptr err\n", __func__); - pcm_ptr_bytes = 0; + unsigned int hw_ptr_lower32 = 0, hw_ptr_upper32 = 0; + unsigned int hw_base_lower32 = 0, hw_base_upper32 = 0; + unsigned long long hw_ptr = 0, hw_base = 0; + int ret; + unsigned long long pcm_ptr_bytes = 0; + + ret = regmap_read(regmap, memif_data->reg_ofs_cur, &hw_ptr_lower32); + if (ret || hw_ptr_lower32 == 0) { + dev_err(dev, "%s hw_ptr_lower32 err\n", __func__); goto POINTER_RETURN_FRAMES; } - ret = regmap_read(regmap, reg_ofs_base, &hw_base); - if (ret || hw_base == 0) { - dev_err(dev, "%s hw_ptr err\n", __func__); - pcm_ptr_bytes = 0; - goto POINTER_RETURN_FRAMES; + if (memif_data->reg_ofs_cur_msb) { + ret = regmap_read(regmap, memif_data->reg_ofs_cur_msb, &hw_ptr_upper32); + if (ret) { + dev_err(dev, "%s hw_ptr_upper32 err\n", __func__); + goto POINTER_RETURN_FRAMES; + } } - pcm_ptr_bytes = hw_ptr - hw_base; + ret = regmap_read(regmap, memif_data->reg_ofs_base, &hw_base_lower32); + if (ret || hw_base_lower32 == 0) { + dev_err(dev, "%s hw_base_lower32 err\n", __func__); + goto POINTER_RETURN_FRAMES; + } + if (memif_data->reg_ofs_base_msb) { + ret = regmap_read(regmap, memif_data->reg_ofs_base_msb, &hw_base_upper32); + if (ret) { + dev_err(dev, "%s hw_base_upper32 err\n", __func__); + goto POINTER_RETURN_FRAMES; + } + } + hw_ptr = ((unsigned long long)hw_ptr_upper32 << 32) + hw_ptr_lower32; + hw_base = ((unsigned long long)hw_base_upper32 << 32) + hw_base_lower32; POINTER_RETURN_FRAMES: - return bytes_to_frames(substream->runtime, pcm_ptr_bytes); + pcm_ptr_bytes = MTK_WORD_SIZE_ALIGN(hw_ptr - hw_base); + return bytes_to_frames(substream->runtime, (ssize_t)pcm_ptr_bytes); } EXPORT_SYMBOL_GPL(mtk_afe_pcm_pointer); diff --git a/sound/soc/mediatek/common/mtk-afe-platform-driver.h b/sound/soc/mediatek/common/mtk-afe-platform-driver.h index fcc923b88f12..9809e60db511 100644 --- a/sound/soc/mediatek/common/mtk-afe-platform-driver.h +++ b/sound/soc/mediatek/common/mtk-afe-platform-driver.h @@ -12,6 +12,8 @@ #define AFE_PCM_NAME "mtk-afe-pcm" extern const struct snd_soc_component_driver mtk_afe_pcm_platform; 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Mon, 07 Apr 2025 20:10:54 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Mon, 7 Apr 2025 20:10:51 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Mon, 7 Apr 2025 20:10:50 +0800 From: Darren.Ye To: Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Jaroslav Kysela , Takashi Iwai , Linus Walleij , Bartosz Golaszewski CC: , , , , , , Darren Ye Subject: [PATCH v2 03/11] ASoC: mediatek: mt8196: add common header Date: Mon, 7 Apr 2025 20:06:27 +0800 Message-ID: <20250407120708.26495-4-darren.ye@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250407120708.26495-1-darren.ye@mediatek.com> References: <20250407120708.26495-1-darren.ye@mediatek.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N From: Darren Ye Add header files for register definitions and structures. Signed-off-by: Darren Ye --- sound/soc/mediatek/mt8196/mt8196-afe-common.h | 194 + .../mediatek/mt8196/mt8196-interconnection.h | 121 + sound/soc/mediatek/mt8196/mt8196-reg.h | 12068 ++++++++++++++++ 3 files changed, 12383 insertions(+) create mode 100644 sound/soc/mediatek/mt8196/mt8196-afe-common.h create mode 100644 sound/soc/mediatek/mt8196/mt8196-interconnection.h create mode 100644 sound/soc/mediatek/mt8196/mt8196-reg.h diff --git a/sound/soc/mediatek/mt8196/mt8196-afe-common.h b/sound/soc/mediatek/mt8196/mt8196-afe-common.h new file mode 100644 index 000000000000..6db424ba7d27 --- /dev/null +++ b/sound/soc/mediatek/mt8196/mt8196-afe-common.h @@ -0,0 +1,194 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * mt8196-afe-common.h -- Mediatek 8196 audio driver definitions + * + * Copyright (c) 2024 MediaTek Inc. + * Author: Darren Ye + */ + +#ifndef _MT_8196_AFE_COMMON_H_ +#define _MT_8196_AFE_COMMON_H_ +#include +#include +#include +#include +#include +#include "mt8196-reg.h" +#include "mtk-base-afe.h" + +/* HW IPM 2.0 */ +enum { + MTK_AFE_IPM2P0_RATE_8K = 0x0, + MTK_AFE_IPM2P0_RATE_11K = 0x1, + MTK_AFE_IPM2P0_RATE_12K = 0x2, + MTK_AFE_IPM2P0_RATE_16K = 0x4, + MTK_AFE_IPM2P0_RATE_22K = 0x5, + MTK_AFE_IPM2P0_RATE_24K = 0x6, + MTK_AFE_IPM2P0_RATE_32K = 0x8, + MTK_AFE_IPM2P0_RATE_44K = 0x9, + MTK_AFE_IPM2P0_RATE_48K = 0xa, + MTK_AFE_IPM2P0_RATE_88K = 0xd, + MTK_AFE_IPM2P0_RATE_96K = 0xe, + MTK_AFE_IPM2P0_RATE_176K = 0x11, + MTK_AFE_IPM2P0_RATE_192K = 0x12, + MTK_AFE_IPM2P0_RATE_352K = 0x15, + MTK_AFE_IPM2P0_RATE_384K = 0x16, +}; + +enum { + MTKAIF_PROTOCOL_1 = 0, + MTKAIF_PROTOCOL_2, + MTKAIF_PROTOCOL_2_CLK_P2, +}; + +enum { + MT8196_MEMIF_DL0, + MT8196_MEMIF_DL1, + MT8196_MEMIF_DL2, + MT8196_MEMIF_DL3, + MT8196_MEMIF_DL4, + MT8196_MEMIF_DL5, + MT8196_MEMIF_DL6, + MT8196_MEMIF_DL7, + MT8196_MEMIF_DL8, + MT8196_MEMIF_DL23, + MT8196_MEMIF_DL24, + MT8196_MEMIF_DL25, + MT8196_MEMIF_DL26, + MT8196_MEMIF_DL_4CH, + MT8196_MEMIF_DL_24CH, + MT8196_MEMIF_VUL0, + MT8196_MEMIF_VUL1, + MT8196_MEMIF_VUL2, + MT8196_MEMIF_VUL3, + MT8196_MEMIF_VUL4, + MT8196_MEMIF_VUL5, + MT8196_MEMIF_VUL6, + MT8196_MEMIF_VUL7, + MT8196_MEMIF_VUL8, + MT8196_MEMIF_VUL9, + MT8196_MEMIF_VUL10, + MT8196_MEMIF_VUL24, + MT8196_MEMIF_VUL25, + MT8196_MEMIF_VUL26, + MT8196_MEMIF_VUL_CM0, + MT8196_MEMIF_VUL_CM1, + MT8196_MEMIF_VUL_CM2, + MT8196_MEMIF_ETDM_IN0, + MT8196_MEMIF_ETDM_IN1, + MT8196_MEMIF_ETDM_IN2, + MT8196_MEMIF_ETDM_IN3, + MT8196_MEMIF_ETDM_IN4, + MT8196_MEMIF_ETDM_IN6, + MT8196_MEMIF_HDMI, + MT8196_MEMIF_NUM, + MT8196_DAI_ADDA = MT8196_MEMIF_NUM, + MT8196_DAI_ADDA_CH34, + MT8196_DAI_ADDA_CH56, + MT8196_DAI_AP_DMIC, + MT8196_DAI_AP_DMIC_CH34, + MT8196_DAI_AP_DMIC_MULTICH, + MT8196_DAI_I2S_IN0, + MT8196_DAI_I2S_IN1, + MT8196_DAI_I2S_IN2, + MT8196_DAI_I2S_IN3, + MT8196_DAI_I2S_IN4, + MT8196_DAI_I2S_IN6, + MT8196_DAI_I2S_OUT0, + MT8196_DAI_I2S_OUT1, + MT8196_DAI_I2S_OUT2, + MT8196_DAI_I2S_OUT3, + MT8196_DAI_I2S_OUT4, + MT8196_DAI_I2S_OUT6, + MT8196_DAI_FM_I2S_MASTER, + MT8196_DAI_TDM, + MT8196_DAI_TDM_DPTX, + MT8196_DAI_NUM, +}; + +#define MT8196_DAI_I2S_MAX_NUM 13 //depends each platform's max i2s num + +/* update irq ID (= enum) from AFE_IRQ_MCU_STATUS */ +enum { + MT8196_IRQ_0, + MT8196_IRQ_1, + MT8196_IRQ_2, + MT8196_IRQ_3, + MT8196_IRQ_4, + MT8196_IRQ_5, + MT8196_IRQ_6, + MT8196_IRQ_7, + MT8196_IRQ_8, + MT8196_IRQ_9, + MT8196_IRQ_10, + MT8196_IRQ_11, + MT8196_IRQ_12, + MT8196_IRQ_13, + MT8196_IRQ_14, + MT8196_IRQ_15, + MT8196_IRQ_16, + MT8196_IRQ_17, + MT8196_IRQ_18, + MT8196_IRQ_19, + MT8196_IRQ_20, + MT8196_IRQ_21, + MT8196_IRQ_22, + MT8196_IRQ_23, + MT8196_IRQ_24, + MT8196_IRQ_25, + MT8196_IRQ_26, + MT8196_IRQ_31, /* used only for TDM */ + MT8196_IRQ_NUM, +}; + +/* update irq ID (= enum) from AFE_IRQ_MCU_STATUS */ +enum { + MT8196_CUS_IRQ_TDM = 0, /* used only for TDM */ + MT8196_CUS_IRQ_NUM, +}; + +/* MCLK */ +enum { + MT8196_I2SIN0_MCK = 0, + MT8196_I2SIN1_MCK, + MT8196_FMI2S_MCK, + MT8196_TDMOUT_MCK, + MT8196_TDMOUT_BCK, + MT8196_MCK_NUM, +}; + +/* CM*/ +enum { + CM0, + CM1, + CM2, + CM_NUM, +}; + +struct mt8196_afe_private { + struct clk **clk; + struct regmap *cksys_ck; + struct regmap *vlp_ck; + int irq_cnt[MT8196_MEMIF_NUM]; + int dram_resource_counter; + + /* xrun assert */ + int xrun_assert[MT8196_MEMIF_NUM]; + + /* dai */ + void *dai_priv[MT8196_DAI_NUM]; + + /* mck */ + int mck_rate[MT8196_MCK_NUM]; + + /* channel merge */ + unsigned int cm_rate[CM_NUM]; + unsigned int cm_channels; +}; + +int mt8196_dai_adda_register(struct mtk_base_afe *afe); +int mt8196_dai_i2s_register(struct mtk_base_afe *afe); +int mt8196_dai_tdm_register(struct mtk_base_afe *afe); +int mt8196_dai_set_priv(struct mtk_base_afe *afe, int id, + int priv_size, const void *priv_data); +#endif diff --git a/sound/soc/mediatek/mt8196/mt8196-interconnection.h b/sound/soc/mediatek/mt8196/mt8196-interconnection.h new file mode 100644 index 000000000000..e884ec3ecb31 --- /dev/null +++ b/sound/soc/mediatek/mt8196/mt8196-interconnection.h @@ -0,0 +1,121 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Mediatek MT8196 audio driver interconnection definition + * + * Copyright (c) 2024 MediaTek Inc. + * Author: Darren Ye + */ + +#ifndef _MT8196_INTERCONNECTION_H_ +#define _MT8196_INTERCONNECTION_H_ + +/* in port define */ + +#define I_CONNSYS_I2S_CH1 0 +#define I_CONNSYS_I2S_CH2 1 +#define I_GAIN0_OUT_CH1 6 +#define I_GAIN0_OUT_CH2 7 +#define I_GAIN1_OUT_CH1 8 +#define I_GAIN1_OUT_CH2 9 +#define I_GAIN2_OUT_CH1 10 +#define I_GAIN2_OUT_CH2 11 +#define I_GAIN3_OUT_CH1 12 +#define I_GAIN3_OUT_CH2 13 +#define I_STF_CH1 14 +#define I_ADDA_UL_CH1 16 +#define I_ADDA_UL_CH2 17 +#define I_ADDA_UL_CH3 18 +#define I_ADDA_UL_CH4 19 +#define I_UL_PROX_CH1 20 +#define I_UL_PROX_CH2 21 +#define I_ADDA_UL_CH5 24 +#define I_ADDA_UL_CH6 25 +#define I_DMIC0_CH1 28 +#define I_DMIC0_CH2 29 +#define I_DMIC1_CH1 30 +#define I_DMIC1_CH2 31 + +/* in port define >= 32 */ +#define I_32_OFFSET 32 +#define I_DL0_CH1 (32 - I_32_OFFSET) +#define I_DL0_CH2 (33 - I_32_OFFSET) +#define I_DL1_CH1 (34 - I_32_OFFSET) +#define I_DL1_CH2 (35 - I_32_OFFSET) +#define I_DL2_CH1 (36 - I_32_OFFSET) +#define I_DL2_CH2 (37 - I_32_OFFSET) +#define I_DL3_CH1 (38 - I_32_OFFSET) +#define I_DL3_CH2 (39 - I_32_OFFSET) +#define I_DL4_CH1 (40 - I_32_OFFSET) +#define I_DL4_CH2 (41 - I_32_OFFSET) +#define I_DL5_CH1 (42 - I_32_OFFSET) +#define I_DL5_CH2 (43 - I_32_OFFSET) +#define I_DL6_CH1 (44 - I_32_OFFSET) +#define I_DL6_CH2 (45 - I_32_OFFSET) +#define I_DL7_CH1 (46 - I_32_OFFSET) +#define I_DL7_CH2 (47 - I_32_OFFSET) +#define I_DL8_CH1 (48 - I_32_OFFSET) +#define I_DL8_CH2 (49 - I_32_OFFSET) +#define I_DL_4CH_CH1 (50 - I_32_OFFSET) +#define I_DL_4CH_CH2 (51 - I_32_OFFSET) +#define I_DL_4CH_CH3 (52 - I_32_OFFSET) +#define I_DL_4CH_CH4 (53 - I_32_OFFSET) +#define I_DL_24CH_CH1 (54 - I_32_OFFSET) +#define I_DL_24CH_CH2 (55 - I_32_OFFSET) +#define I_DL_24CH_CH3 (56 - I_32_OFFSET) +#define I_DL_24CH_CH4 (57 - I_32_OFFSET) +#define I_DL_24CH_CH5 (58 - I_32_OFFSET) +#define I_DL_24CH_CH6 (59 - I_32_OFFSET) +#define I_DL_24CH_CH7 (60 - I_32_OFFSET) +#define I_DL_24CH_CH8 (61 - I_32_OFFSET) + +/* in port define >= 64 */ +#define I_64_OFFSET 64 +#define I_DL23_CH1 (78 - I_64_OFFSET) +#define I_DL23_CH2 (79 - I_64_OFFSET) +#define I_DL24_CH1 (80 - I_64_OFFSET) +#define I_DL24_CH2 (81 - I_64_OFFSET) +#define I_DL25_CH1 (82 - I_64_OFFSET) +#define I_DL25_CH2 (83 - I_64_OFFSET) +#define I_DL26_CH1 (84 - I_64_OFFSET) +#define I_DL26_CH2 (85 - I_64_OFFSET) + +/* in port define >= 128 */ +#define I_128_OFFSET 128 +#define I_PCM_0_CAP_CH1 (130 - I_128_OFFSET) +#define I_PCM_0_CAP_CH2 (131 - I_128_OFFSET) +#define I_PCM_1_CAP_CH1 (132 - I_128_OFFSET) +#define I_PCM_1_CAP_CH2 (133 - I_128_OFFSET) +#define I_I2SIN0_CH1 (134 - I_128_OFFSET) +#define I_I2SIN0_CH2 (135 - I_128_OFFSET) +#define I_I2SIN1_CH1 (136 - I_128_OFFSET) +#define I_I2SIN1_CH2 (137 - I_128_OFFSET) +#define I_I2SIN2_CH1 (138 - I_128_OFFSET) +#define I_I2SIN2_CH2 (139 - I_128_OFFSET) +#define I_I2SIN3_CH1 (140 - I_128_OFFSET) +#define I_I2SIN3_CH2 (141 - I_128_OFFSET) +#define I_I2SIN4_CH1 (142 - I_128_OFFSET) +#define I_I2SIN4_CH2 (143 - I_128_OFFSET) +#define I_I2SIN4_CH3 (144 - I_128_OFFSET) +#define I_I2SIN4_CH4 (145 - I_128_OFFSET) +#define I_I2SIN4_CH5 (146 - I_128_OFFSET) +#define I_I2SIN4_CH6 (147 - I_128_OFFSET) +#define I_I2SIN4_CH7 (148 - I_128_OFFSET) +#define I_I2SIN4_CH8 (149 - I_128_OFFSET) + +/* in port define >= 160 */ +#define I_160_OFFSET 160 +#define I_I2SIN6_CH1 (166 - I_160_OFFSET) +#define I_I2SIN6_CH2 (167 - I_160_OFFSET) + +/* in port define >= 192 */ +#define I_192_OFFSET 192 +#define I_SRC_0_OUT_CH1 (198 - I_192_OFFSET) +#define I_SRC_0_OUT_CH2 (199 - I_192_OFFSET) +#define I_SRC_1_OUT_CH1 (200 - I_192_OFFSET) +#define I_SRC_1_OUT_CH2 (201 - I_192_OFFSET) +#define I_SRC_2_OUT_CH1 (202 - I_192_OFFSET) +#define I_SRC_2_OUT_CH2 (203 - I_192_OFFSET) +#define I_SRC_3_OUT_CH1 (204 - I_192_OFFSET) +#define I_SRC_3_OUT_CH2 (205 - I_192_OFFSET) + +#endif diff --git a/sound/soc/mediatek/mt8196/mt8196-reg.h b/sound/soc/mediatek/mt8196/mt8196-reg.h new file mode 100644 index 000000000000..df9c803637a6 --- /dev/null +++ b/sound/soc/mediatek/mt8196/mt8196-reg.h @@ -0,0 +1,12068 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * mt8196-reg.h -- Mediatek 8196 audio driver reg definition + * + * Copyright (c) 2024 MediaTek Inc. + * Author: Darren Ye + */ + +#ifndef _MT8196_REG_H_ +#define _MT8196_REG_H_ + + /* reg bit enum */ +enum { + MT8196_MEMIF_PBUF_SIZE_32_BYTES, + MT8196_MEMIF_PBUF_SIZE_64_BYTES, + MT8196_MEMIF_PBUF_SIZE_128_BYTES, + MT8196_MEMIF_PBUF_SIZE_256_BYTES, + MT8196_MEMIF_PBUF_SIZE_NUM, +}; + +enum { + MT8196_MEMIF_MAX_LEN_0_BYTES, + MT8196_MEMIF_MAX_LEN_16_BYTES, + MT8196_MEMIF_MAX_LEN_32_BYTES, + MT8196_MEMIF_MAX_LEN_64_BYTES, +}; + +enum { + MT8196_MEMIF_MIN_LEN_NOT_SUPPORT, + MT8196_MEMIF_MIN_LEN_16_BYTES, + MT8196_MEMIF_MIN_LEN_32_BYTES, + MT8196_MEMIF_MIN_LEN_64_BYTES, +}; + +/***************************************************************************** + * R E G I S T E R D E F I N I T I O N + *****************************************************************************/ +/* AUDIO_TOP_CON0 */ +#define PDN_MTKAIFV4_SFT 25 +#define PDN_MTKAIFV4_MASK 0x1 +#define PDN_MTKAIFV4_MASK_SFT (0x1 << 25) +#define PDN_FM_I2S_SFT 24 +#define PDN_FM_I2S_MASK 0x1 +#define PDN_FM_I2S_MASK_SFT (0x1 << 24) +#define PDN_HW_GAIN01_SFT 21 +#define PDN_HW_GAIN01_MASK 0x1 +#define PDN_HW_GAIN01_MASK_SFT (0x1 << 21) +#define PDN_HW_GAIN23_SFT 20 +#define PDN_HW_GAIN23_MASK 0x1 +#define PDN_HW_GAIN23_MASK_SFT (0x1 << 20) +#define PDN_STF_SFT 19 +#define PDN_STF_MASK 0x1 +#define PDN_STF_MASK_SFT (0x1 << 19) +#define PDN_CM0_SFT 18 +#define PDN_CM0_MASK 0x1 +#define PDN_CM0_MASK_SFT (0x1 << 18) +#define PDN_CM1_SFT 17 +#define PDN_CM1_MASK 0x1 +#define PDN_CM1_MASK_SFT (0x1 << 17) +#define PDN_CM2_SFT 16 +#define PDN_CM2_MASK 0x1 +#define PDN_CM2_MASK_SFT (0x1 << 16) +#define PDN_PCM0_SFT 14 +#define PDN_PCM0_MASK 0x1 +#define PDN_PCM0_MASK_SFT (0x1 << 14) +#define PDN_PCM1_SFT 13 +#define PDN_PCM1_MASK 0x1 +#define PDN_PCM1_MASK_SFT (0x1 << 13) + +/* AUDIO_TOP_CON1 */ +#define PDN_UL0_ADC_SFT 23 +#define PDN_UL0_ADC_MASK 0x1 +#define PDN_UL0_ADC_MASK_SFT (0x1 << 23) +#define PDN_UL0_TML_SFT 22 +#define PDN_UL0_TML_MASK 0x1 +#define PDN_UL0_TML_MASK_SFT (0x1 << 22) +#define PDN_UL0_ADC_HIRES_SFT 21 +#define PDN_UL0_ADC_HIRES_MASK 0x1 +#define PDN_UL0_ADC_HIRES_MASK_SFT (0x1 << 21) +#define PDN_UL0_ADC_HIRES_TML_SFT 20 +#define PDN_UL0_ADC_HIRES_TML_MASK 0x1 +#define PDN_UL0_ADC_HIRES_TML_MASK_SFT (0x1 << 20) +#define PDN_UL1_ADC_SFT 19 +#define PDN_UL1_ADC_MASK 0x1 +#define PDN_UL1_ADC_MASK_SFT (0x1 << 19) +#define PDN_UL1_TML_SFT 18 +#define PDN_UL1_TML_MASK 0x1 +#define PDN_UL1_TML_MASK_SFT (0x1 << 18) +#define PDN_UL1_ADC_HIRES_SFT 17 +#define PDN_UL1_ADC_HIRES_MASK 0x1 +#define PDN_UL1_ADC_HIRES_MASK_SFT (0x1 << 17) +#define PDN_UL1_ADC_HIRES_TML_SFT 16 +#define PDN_UL1_ADC_HIRES_TML_MASK 0x1 +#define PDN_UL1_ADC_HIRES_TML_MASK_SFT (0x1 << 16) +#define PDN_UL2_ADC_SFT 15 +#define PDN_UL2_ADC_MASK 0x1 +#define PDN_UL2_ADC_MASK_SFT (0x1 << 15) +#define PDN_UL2_TML_SFT 14 +#define PDN_UL2_TML_MASK 0x1 +#define PDN_UL2_TML_MASK_SFT (0x1 << 14) +#define PDN_UL2_ADC_HIRES_SFT 13 +#define PDN_UL2_ADC_HIRES_MASK 0x1 +#define PDN_UL2_ADC_HIRES_MASK_SFT (0x1 << 13) +#define PDN_UL2_ADC_HIRES_TML_SFT 12 +#define PDN_UL2_ADC_HIRES_TML_MASK 0x1 +#define PDN_UL2_ADC_HIRES_TML_MASK_SFT (0x1 << 12) + +/* AUDIO_TOP_CON2 */ +#define PDN_TDM_OUT_SFT 24 +#define PDN_TDM_OUT_MASK 0x1 +#define PDN_TDM_OUT_MASK_SFT (0x1 << 24) +#define PDN_ETDM_OUT0_SFT 21 +#define PDN_ETDM_OUT0_MASK 0x1 +#define PDN_ETDM_OUT0_MASK_SFT (0x1 << 21) +#define PDN_ETDM_OUT1_SFT 20 +#define PDN_ETDM_OUT1_MASK 0x1 +#define PDN_ETDM_OUT1_MASK_SFT (0x1 << 20) +#define PDN_ETDM_OUT2_SFT 19 +#define PDN_ETDM_OUT2_MASK 0x1 +#define PDN_ETDM_OUT2_MASK_SFT (0x1 << 19) +#define PDN_ETDM_OUT3_SFT 18 +#define PDN_ETDM_OUT3_MASK 0x1 +#define PDN_ETDM_OUT3_MASK_SFT (0x1 << 18) +#define PDN_ETDM_OUT4_SFT 17 +#define PDN_ETDM_OUT4_MASK 0x1 +#define PDN_ETDM_OUT4_MASK_SFT (0x1 << 17) +#define PDN_ETDM_OUT5_SFT 16 +#define PDN_ETDM_OUT5_MASK 0x1 +#define PDN_ETDM_OUT5_MASK_SFT (0x1 << 16) +#define PDN_ETDM_OUT6_SFT 15 +#define PDN_ETDM_OUT6_MASK 0x1 +#define PDN_ETDM_OUT6_MASK_SFT (0x1 << 15) +#define PDN_ETDM_IN0_SFT 13 +#define PDN_ETDM_IN0_MASK 0x1 +#define PDN_ETDM_IN0_MASK_SFT (0x1 << 13) +#define PDN_ETDM_IN1_SFT 12 +#define PDN_ETDM_IN1_MASK 0x1 +#define PDN_ETDM_IN1_MASK_SFT (0x1 << 12) +#define PDN_ETDM_IN2_SFT 11 +#define PDN_ETDM_IN2_MASK 0x1 +#define PDN_ETDM_IN2_MASK_SFT (0x1 << 11) +#define PDN_ETDM_IN3_SFT 10 +#define PDN_ETDM_IN3_MASK 0x1 +#define PDN_ETDM_IN3_MASK_SFT (0x1 << 10) +#define PDN_ETDM_IN4_SFT 9 +#define PDN_ETDM_IN4_MASK 0x1 +#define PDN_ETDM_IN4_MASK_SFT (0x1 << 9) +#define PDN_ETDM_IN5_SFT 8 +#define PDN_ETDM_IN5_MASK 0x1 +#define PDN_ETDM_IN5_MASK_SFT (0x1 << 8) +#define PDN_ETDM_IN6_SFT 7 +#define PDN_ETDM_IN6_MASK 0x1 +#define PDN_ETDM_IN6_MASK_SFT (0x1 << 7) + +/* AUDIO_TOP_CON3 */ +#define PDN_CONNSYS_I2S_ASRC_SFT 25 +#define PDN_CONNSYS_I2S_ASRC_MASK 0x1 +#define PDN_CONNSYS_I2S_ASRC_MASK_SFT (0x1 << 25) +#define PDN_GENERAL0_ASRC_SFT 24 +#define PDN_GENERAL0_ASRC_MASK 0x1 +#define PDN_GENERAL0_ASRC_MASK_SFT (0x1 << 24) +#define PDN_GENERAL1_ASRC_SFT 23 +#define PDN_GENERAL1_ASRC_MASK 0x1 +#define PDN_GENERAL1_ASRC_MASK_SFT (0x1 << 23) +#define PDN_GENERAL2_ASRC_SFT 22 +#define PDN_GENERAL2_ASRC_MASK 0x1 +#define PDN_GENERAL2_ASRC_MASK_SFT (0x1 << 22) +#define PDN_GENERAL3_ASRC_SFT 21 +#define PDN_GENERAL3_ASRC_MASK 0x1 +#define PDN_GENERAL3_ASRC_MASK_SFT (0x1 << 21) +#define PDN_GENERAL4_ASRC_SFT 20 +#define PDN_GENERAL4_ASRC_MASK 0x1 +#define PDN_GENERAL4_ASRC_MASK_SFT (0x1 << 20) +#define PDN_GENERAL5_ASRC_SFT 19 +#define PDN_GENERAL5_ASRC_MASK 0x1 +#define PDN_GENERAL5_ASRC_MASK_SFT (0x1 << 19) +#define PDN_GENERAL6_ASRC_SFT 18 +#define PDN_GENERAL6_ASRC_MASK 0x1 +#define PDN_GENERAL6_ASRC_MASK_SFT (0x1 << 18) +#define PDN_GENERAL7_ASRC_SFT 17 +#define PDN_GENERAL7_ASRC_MASK 0x1 +#define PDN_GENERAL7_ASRC_MASK_SFT (0x1 << 17) +#define PDN_GENERAL8_ASRC_SFT 16 +#define PDN_GENERAL8_ASRC_MASK 0x1 +#define PDN_GENERAL8_ASRC_MASK_SFT (0x1 << 16) +#define PDN_GENERAL9_ASRC_SFT 15 +#define PDN_GENERAL9_ASRC_MASK 0x1 +#define PDN_GENERAL9_ASRC_MASK_SFT (0x1 << 15) +#define PDN_GENERAL10_ASRC_SFT 14 +#define PDN_GENERAL10_ASRC_MASK 0x1 +#define PDN_GENERAL10_ASRC_MASK_SFT (0x1 << 14) +#define PDN_GENERAL11_ASRC_SFT 13 +#define PDN_GENERAL11_ASRC_MASK 0x1 +#define PDN_GENERAL11_ASRC_MASK_SFT (0x1 << 13) +#define PDN_GENERAL12_ASRC_SFT 12 +#define PDN_GENERAL12_ASRC_MASK 0x1 +#define PDN_GENERAL12_ASRC_MASK_SFT (0x1 << 12) +#define PDN_GENERAL13_ASRC_SFT 11 +#define PDN_GENERAL13_ASRC_MASK 0x1 +#define PDN_GENERAL13_ASRC_MASK_SFT (0x1 << 11) +#define PDN_GENERAL14_ASRC_SFT 10 +#define PDN_GENERAL14_ASRC_MASK 0x1 +#define PDN_GENERAL14_ASRC_MASK_SFT (0x1 << 10) +#define PDN_GENERAL15_ASRC_SFT 9 +#define PDN_GENERAL15_ASRC_MASK 0x1 +#define PDN_GENERAL15_ASRC_MASK_SFT (0x1 << 9) + +/* AUDIO_TOP_CON4 */ +#define PDN_APLL_TUNER1_SFT 13 +#define PDN_APLL_TUNER1_MASK 0x1 +#define PDN_APLL_TUNER1_MASK_SFT (0x1 << 13) +#define PDN_APLL_TUNER2_SFT 12 +#define PDN_APLL_TUNER2_MASK 0x1 +#define PDN_APLL_TUNER2_MASK_SFT (0x1 << 12) +#define CG_H208M_CK_SFT 4 +#define CG_H208M_CK_MASK 0x1 +#define CG_H208M_CK_MASK_SFT (0x1 << 4) +#define CG_APLL2_CK_SFT 3 +#define CG_APLL2_CK_MASK 0x1 +#define CG_APLL2_CK_MASK_SFT (0x1 << 3) +#define CG_APLL1_CK_SFT 2 +#define CG_APLL1_CK_MASK 0x1 +#define CG_APLL1_CK_MASK_SFT (0x1 << 2) +#define CG_AUDIO_F26M_CK_SFT 1 +#define CG_AUDIO_F26M_CK_MASK 0x1 +#define CG_AUDIO_F26M_CK_MASK_SFT (0x1 << 1) +#define CG_AUDIO_HOPPING_CK_SFT 0 +#define CG_AUDIO_HOPPING_CK_MASK 0x1 +#define CG_AUDIO_HOPPING_CK_MASK_SFT (0x1 << 0) + +/* AUDIO_ENGEN_CON0 */ +/* AUDIO_ENGEN_CON0_USER1 */ +/* AUDIO_ENGEN_CON0_USER1 */ +#define MULTI_USER_BYPASS_SFT 17 +#define MULTI_USER_BYPASS_MASK 0x1 +#define MULTI_USER_BYPASS_MASK_SFT (0x1 << 17) +#define MULTI_USER_RST_SFT 16 +#define MULTI_USER_RST_MASK 0x1 +#define MULTI_USER_RST_MASK_SFT (0x1 << 16) +#define AUDIO_F26M_EN_RST_SFT 8 +#define AUDIO_F26M_EN_RST_MASK 0x1 +#define AUDIO_F26M_EN_RST_MASK_SFT (0x1 << 8) +#define AUDIO_APLL2_EN_ON_SFT 3 +#define AUDIO_APLL2_EN_ON_MASK 0x1 +#define AUDIO_APLL2_EN_ON_MASK_SFT (0x1 << 3) +#define AUDIO_APLL1_EN_ON_SFT 2 +#define AUDIO_APLL1_EN_ON_MASK 0x1 +#define AUDIO_APLL1_EN_ON_MASK_SFT (0x1 << 2) +#define AUDIO_F3P25M_EN_ON_SFT 1 +#define AUDIO_F3P25M_EN_ON_MASK 0x1 +#define AUDIO_F3P25M_EN_ON_MASK_SFT (0x1 << 1) +#define AUDIO_26M_EN_ON_SFT 0 +#define AUDIO_26M_EN_ON_MASK 0x1 +#define AUDIO_26M_EN_ON_MASK_SFT (0x1 << 0) + +/* AFE_SINEGEN_CON0 */ +#define DAC_EN_SFT 26 +#define DAC_EN_MASK 0x1 +#define DAC_EN_MASK_SFT (0x1 << 26) +#define TIE_SW_CH2_SFT 25 +#define TIE_SW_CH2_MASK 0x1 +#define TIE_SW_CH2_MASK_SFT (0x1 << 25) +#define TIE_SW_CH1_SFT 24 +#define TIE_SW_CH1_MASK 0x1 +#define TIE_SW_CH1_MASK_SFT (0x1 << 24) +#define AMP_DIV_CH2_SFT 20 +#define AMP_DIV_CH2_MASK 0xf +#define AMP_DIV_CH2_MASK_SFT (0xf << 20) +#define FREQ_DIV_CH2_SFT 12 +#define FREQ_DIV_CH2_MASK 0x1f +#define FREQ_DIV_CH2_MASK_SFT (0x1f << 12) +#define AMP_DIV_CH1_SFT 8 +#define AMP_DIV_CH1_MASK 0xf +#define AMP_DIV_CH1_MASK_SFT (0xf << 8) +#define FREQ_DIV_CH1_SFT 0 +#define FREQ_DIV_CH1_MASK 0x1f +#define FREQ_DIV_CH1_MASK_SFT (0x1f << 0) + +/* AFE_SINEGEN_CON1 */ +#define SINE_DOMAIN_SFT 20 +#define SINE_DOMAIN_MASK 0x7 +#define SINE_DOMAIN_MASK_SFT (0x7 << 20) +#define SINE_MODE_SFT 12 +#define SINE_MODE_MASK 0x1f +#define SINE_MODE_MASK_SFT (0x1f << 12) +#define INNER_LOOP_BACKI_SEL_SFT 8 +#define INNER_LOOP_BACKI_SEL_MASK 0x1 +#define INNER_LOOP_BACKI_SEL_MASK_SFT (0x1 << 8) +#define INNER_LOOP_BACK_MODE_SFT 0 +#define INNER_LOOP_BACK_MODE_MASK 0xff +#define INNER_LOOP_BACK_MODE_MASK_SFT (0xff << 0) + +/* AFE_SINEGEN_CON2 */ +#define TIE_CH1_CONSTANT_SFT 0 +#define TIE_CH1_CONSTANT_MASK 0xffffffff +#define TIE_CH1_CONSTANT_MASK_SFT (0xffffffff << 0) + +/* AFE_SINEGEN_CON3 */ +#define TIE_CH2_CONSTANT_SFT 0 +#define TIE_CH2_CONSTANT_MASK 0xffffffff +#define TIE_CH2_CONSTANT_MASK_SFT (0xffffffff << 0) + +/* AFE_APLL1_TUNER_CFG */ +/* AFE_APLL2_TUNER_CFG */ +#define UPPER_BOUND_SFT 8 +#define UPPER_BOUND_MASK 0xff +#define UPPER_BOUND_MASK_SFT (0xff << 8) +#define APLL_DIV_SFT 4 +#define APLL_DIV_MASK 0xf +#define APLL_DIV_MASK_SFT (0xf << 4) +#define XTAL_EN_128FS_SEL_SFT 1 +#define XTAL_EN_128FS_SEL_MASK 0x3 +#define XTAL_EN_128FS_SEL_MASK_SFT (0x3 << 1) +#define FREQ_TUNER_EN_SFT 0 +#define FREQ_TUNER_EN_MASK 0x1 +#define FREQ_TUNER_EN_MASK_SFT (0x1 << 0) + +/* AFE_APLL1_TUNER_MON0 */ +/* AFE_APLL2_TUNER_MON0 */ +#define TUNER_MON_SFT 0 +#define TUNER_MON_MASK 0xffffffff +#define TUNER_MON_MASK_SFT (0xffffffff << 0) + +/* AUDIO_TOP_RG0 */ +/* AUDIO_TOP_RG1 */ +/* AUDIO_TOP_RG2 */ +/* AUDIO_TOP_RG3 */ +/* AUDIO_TOP_RG4 */ +#define RESERVE_RG_SFT 0 +#define RESERVE_RG_MASK 0xffffffff +#define RESERVE_RG_MASK_SFT (0xffffffff << 0) + +/* AFE_SPM_CONTROL_REQ */ +#define AFE_DDREN_REQ_SFT 4 +#define AFE_DDREN_REQ_MASK 0x1 +#define AFE_DDREN_REQ_MASK_SFT (0x1 << 4) +#define AFE_INFRA_REQ_SFT 3 +#define AFE_INFRA_REQ_MASK 0x1 +#define AFE_INFRA_REQ_MASK_SFT (0x1 << 3) +#define AFE_VRF18_REQ_SFT 2 +#define AFE_VRF18_REQ_MASK 0x1 +#define AFE_VRF18_REQ_MASK_SFT (0x1 << 2) +#define AFE_APSRC_REQ_SFT 1 +#define AFE_APSRC_REQ_MASK 0x1 +#define AFE_APSRC_REQ_MASK_SFT (0x1 << 1) +#define AFE_SRCCLKENA_REQ_SFT 0 +#define AFE_SRCCLKENA_REQ_MASK 0x1 +#define AFE_SRCCLKENA_REQ_MASK_SFT (0x1 << 0) + +/* AFE_SPM_CONTROL_ACK */ +#define SPM_RESOURCE_CONTROL_ACK_SFT 0 +#define SPM_RESOURCE_CONTROL_ACK_MASK 0xffffffff +#define SPM_RESOURCE_CONTROL_ACK_MASK_SFT (0xffffffff << 0) + +/* AUD_TOP_CFG_VCORE_RG */ +#define AUD_TOP_CFG_SFT 0 +#define AUD_TOP_CFG_MASK 0xffffffff +#define AUD_TOP_CFG_MASK_SFT (0xffffffff << 0) + +/* AUDIO_TOP_IP_VERSION */ +#define AUDIO_TOP_IP_VERSION_SFT 0 +#define AUDIO_TOP_IP_VERSION_MASK 0xffffffff +#define AUDIO_TOP_IP_VERSION_MASK_SFT (0xffffffff << 0) + +/* AUDIO_ENGEN_CON0_MON */ +#define AUDIO_ENGEN_MON_SFT 0 +#define AUDIO_ENGEN_MON_MASK 0xffffffff +#define AUDIO_ENGEN_MON_MASK_SFT (0xffffffff << 0) + +/* AUD_TOP_CFG_VLP_RG */ +#define I2SIN1_DAT_SEL_SFT 31 +#define I2SIN1_DAT_SEL_MASK 0x1 +#define I2SIN1_DAT_SEL_MASK_SFT (0x1 << 31) +#define FMI2S_IN_SEL_SFT 30 +#define FMI2S_IN_SEL_MASK 0x1 +#define FMI2S_IN_SEL_MASK_SFT (0x1 << 30) +#define RG_I2S4_IN_BCK_NEG_EG_LATCH_SFT 21 +#define RG_I2S4_IN_BCK_NEG_EG_LATCH_MASK 0x1 +#define RG_I2S4_IN_BCK_NEG_EG_LATCH_MASK_SFT (0x1 << 21) +#define RG_I2S4_OUT_BCK_NEG_EG_LATCH_SFT 20 +#define RG_I2S4_OUT_BCK_NEG_EG_LATCH_MASK 0x1 +#define RG_I2S4_OUT_BCK_NEG_EG_LATCH_MASK_SFT (0x1 << 20) +#define RG_I2S4_IN_SLV_LRCK_LATCH_EDGE_SFT 19 +#define RG_I2S4_IN_SLV_LRCK_LATCH_EDGE_MASK 0x1 +#define RG_I2S4_IN_SLV_LRCK_LATCH_EDGE_MASK_SFT (0x1 << 19) +#define RG_I2S4_IN_SLV_BCK_INV_SEL_SFT 18 +#define RG_I2S4_IN_SLV_BCK_INV_SEL_MASK 0x1 +#define RG_I2S4_IN_SLV_BCK_INV_SEL_MASK_SFT (0x1 << 18) +#define RG_I2S4_OUT_SLV_LRCK_LATCH_EDGE_SFT 17 +#define RG_I2S4_OUT_SLV_LRCK_LATCH_EDGE_MASK 0x1 +#define RG_I2S4_OUT_SLV_LRCK_LATCH_EDGE_MASK_SFT (0x1 << 17) +#define RG_I2S4_OUT_SLV_BCK_INV_SEL_SFT 16 +#define RG_I2S4_OUT_SLV_BCK_INV_SEL_MASK 0x1 +#define RG_I2S4_OUT_SLV_BCK_INV_SEL_MASK_SFT (0x1 << 16) +#define RG_I2S5_IN_BCK_NEG_EG_LATCH_SFT 13 +#define RG_I2S5_IN_BCK_NEG_EG_LATCH_MASK 0x1 +#define RG_I2S5_IN_BCK_NEG_EG_LATCH_MASK_SFT (0x1 << 13) +#define RG_I2S5_OUT_BCK_NEG_EG_LATCH_SFT 12 +#define RG_I2S5_OUT_BCK_NEG_EG_LATCH_MASK 0x1 +#define RG_I2S5_OUT_BCK_NEG_EG_LATCH_MASK_SFT (0x1 << 12) +#define RG_I2S5_IN_SLV_LRCK_LATCH_EDGE_SFT 11 +#define RG_I2S5_IN_SLV_LRCK_LATCH_EDGE_MASK 0x1 +#define RG_I2S5_IN_SLV_LRCK_LATCH_EDGE_MASK_SFT (0x1 << 11) +#define RG_I2S5_IN_SLV_BCK_INV_SEL_SFT 10 +#define RG_I2S5_IN_SLV_BCK_INV_SEL_MASK 0x1 +#define RG_I2S5_IN_SLV_BCK_INV_SEL_MASK_SFT (0x1 << 10) +#define RG_I2S5_OUT_SLV_LRCK_LATCH_EDGE_SFT 9 +#define RG_I2S5_OUT_SLV_LRCK_LATCH_EDGE_MASK 0x1 +#define RG_I2S5_OUT_SLV_LRCK_LATCH_EDGE_MASK_SFT (0x1 << 9) +#define RG_I2S5_OUT_SLV_BCK_INV_SEL_SFT 8 +#define RG_I2S5_OUT_SLV_BCK_INV_SEL_MASK 0x1 +#define RG_I2S5_OUT_SLV_BCK_INV_SEL_MASK_SFT (0x1 << 8) +#define RG_I2S4_PAD_TOP_CK_EN_SFT 5 +#define RG_I2S4_PAD_TOP_CK_EN_MASK 0x1 +#define RG_I2S4_PAD_TOP_CK_EN_MASK_SFT (0x1 << 5) +#define RG_I2S5_PAD_TOP_CK_EN_SFT 4 +#define RG_I2S5_PAD_TOP_CK_EN_MASK 0x1 +#define RG_I2S5_PAD_TOP_CK_EN_MASK_SFT (0x1 << 4) +#define RG_TEST_TYPE_SFT 2 +#define RG_TEST_TYPE_MASK 0x1 +#define RG_TEST_TYPE_MASK_SFT (0x1 << 2) +#define RG_SW_RESET_SFT 1 +#define RG_SW_RESET_MASK 0x1 +#define RG_SW_RESET_MASK_SFT (0x1 << 1) +#define RG_TEST_ON_SFT 0 +#define RG_TEST_ON_MASK 0x1 +#define RG_TEST_ON_MASK_SFT (0x1 << 0) + +/* AUD_TOP_MON_RG */ +#define AUD_TOP_MON_SFT 0 +#define AUD_TOP_MON_MASK 0xffffffff +#define AUD_TOP_MON_MASK_SFT (0xffffffff << 0) + +/* AUDIO_USE_DEFAULT_DELSEL0 */ +#define USE_DEFAULT_DELSEL_RG_SFT 0 +#define USE_DEFAULT_DELSEL_RG_MASK 0xffffffff +#define USE_DEFAULT_DELSEL_RG_MASK_SFT (0xffffffff << 0) + +/* AUDIO_USE_DEFAULT_DELSEL1 */ +#define USE_DEFAULT_DELSEL_RG_SFT 0 +#define USE_DEFAULT_DELSEL_RG_MASK 0xffffffff +#define USE_DEFAULT_DELSEL_RG_MASK_SFT (0xffffffff << 0) + +/* AUDIO_USE_DEFAULT_DELSEL2 */ +#define USE_DEFAULT_DELSEL_RG_SFT 0 +#define USE_DEFAULT_DELSEL_RG_MASK 0xffffffff +#define USE_DEFAULT_DELSEL_RG_MASK_SFT (0xffffffff << 0) + +/* AFE_CONNSYS_I2S_IPM_VER_MON */ +#define RG_CONNSYS_I2S_IPM_VER_MON_SFT 0 +#define RG_CONNSYS_I2S_IPM_VER_MON_MASK 0xffffffff +#define RG_CONNSYS_I2S_IPM_VER_MON_MASK_SFT (0xffffffff << 0) + +/* AFE_CONNSYS_I2S_MON_SEL */ +#define RG_CONNSYS_I2S_MON_SEL_SFT 0 +#define RG_CONNSYS_I2S_MON_SEL_MASK 0xff +#define RG_CONNSYS_I2S_MON_SEL_MASK_SFT (0xff << 0) + +/* AFE_CONNSYS_I2S_MON */ +#define RG_CONNSYS_I2S_MON_SFT 0 +#define RG_CONNSYS_I2S_MON_MASK 0xffffffff +#define RG_CONNSYS_I2S_MON_MASK_SFT (0xffffffff << 0) + +/* AFE_CONNSYS_I2S_CON */ +#define I2S_SOFT_RST_SFT 31 +#define I2S_SOFT_RST_MASK 0x1 +#define I2S_SOFT_RST_MASK_SFT (0x1 << 31) +#define BCK_NEG_EG_LATCH_SFT 30 +#define BCK_NEG_EG_LATCH_MASK 0x1 +#define BCK_NEG_EG_LATCH_MASK_SFT (0x1 << 30) +#define BCK_INV_SFT 29 +#define BCK_INV_MASK 0x1 +#define BCK_INV_MASK_SFT (0x1 << 29) +#define I2SIN_PAD_SEL_SFT 28 +#define I2SIN_PAD_SEL_MASK 0x1 +#define I2SIN_PAD_SEL_MASK_SFT (0x1 << 28) +#define I2S_LOOPBACK_SFT 20 +#define I2S_LOOPBACK_MASK 0x1 +#define I2S_LOOPBACK_MASK_SFT (0x1 << 20) +#define I2S_HDEN_SFT 12 +#define I2S_HDEN_MASK 0x1 +#define I2S_HDEN_MASK_SFT (0x1 << 12) +#define I2S_MODE_SFT 8 +#define I2S_MODE_MASK 0xf +#define I2S_MODE_MASK_SFT (0xf << 8) +#define I2S_BYPSRC_SFT 6 +#define I2S_BYPSRC_MASK 0x1 +#define I2S_BYPSRC_MASK_SFT (0x1 << 6) +#define INV_LRCK_SFT 5 +#define INV_LRCK_MASK 0x1 +#define INV_LRCK_MASK_SFT (0x1 << 5) +#define I2S_FMT_SFT 3 +#define I2S_FMT_MASK 0x1 +#define I2S_FMT_MASK_SFT (0x1 << 3) +#define I2S_SRC_SFT 2 +#define I2S_SRC_MASK 0x1 +#define I2S_SRC_MASK_SFT (0x1 << 2) +#define I2S_WLEN_SFT 1 +#define I2S_WLEN_MASK 0x1 +#define I2S_WLEN_MASK_SFT (0x1 << 1) +#define I2S_EN_SFT 0 +#define I2S_EN_MASK 0x1 +#define I2S_EN_MASK_SFT (0x1 << 0) + +/* AFE_PCM0_INTF_CON0 */ +#define PCM0_HDEN_SFT 26 +#define PCM0_HDEN_MASK 0x1 +#define PCM0_HDEN_MASK_SFT (0x1 << 26) +#define PCM0_SYNC_DELSEL_SFT 25 +#define PCM0_SYNC_DELSEL_MASK 0x1 +#define PCM0_SYNC_DELSEL_MASK_SFT (0x1 << 25) +#define PCM0_TX_LR_SWAP_SFT 24 +#define PCM0_TX_LR_SWAP_MASK 0x1 +#define PCM0_TX_LR_SWAP_MASK_SFT (0x1 << 24) +#define PCM0_SYNC_OUT_INV_SFT 23 +#define PCM0_SYNC_OUT_INV_MASK 0x1 +#define PCM0_SYNC_OUT_INV_MASK_SFT (0x1 << 23) +#define PCM0_BCLK_OUT_INV_SFT 22 +#define PCM0_BCLK_OUT_INV_MASK 0x1 +#define PCM0_BCLK_OUT_INV_MASK_SFT (0x1 << 22) +#define PCM0_SYNC_IN_INV_SFT 21 +#define PCM0_SYNC_IN_INV_MASK 0x1 +#define PCM0_SYNC_IN_INV_MASK_SFT (0x1 << 21) +#define PCM0_BCLK_IN_INV_SFT 20 +#define PCM0_BCLK_IN_INV_MASK 0x1 +#define PCM0_BCLK_IN_INV_MASK_SFT (0x1 << 20) +#define PCM0_TX_LCH_RPT_SFT 19 +#define PCM0_TX_LCH_RPT_MASK 0x1 +#define PCM0_TX_LCH_RPT_MASK_SFT (0x1 << 19) +#define PCM0_VBT_16K_MODE_SFT 18 +#define PCM0_VBT_16K_MODE_MASK 0x1 +#define PCM0_VBT_16K_MODE_MASK_SFT (0x1 << 18) +#define PCM0_BIT_LENGTH_SFT 16 +#define PCM0_BIT_LENGTH_MASK 0x3 +#define PCM0_BIT_LENGTH_MASK_SFT (0x3 << 16) +#define PCM0_WLEN_SFT 14 +#define PCM0_WLEN_MASK 0x3 +#define PCM0_WLEN_MASK_SFT (0x3 << 14) +#define PCM0_SYNC_LENGTH_SFT 9 +#define PCM0_SYNC_LENGTH_MASK 0x1f +#define PCM0_SYNC_LENGTH_MASK_SFT (0x1f << 9) +#define PCM0_SYNC_TYPE_SFT 8 +#define PCM0_SYNC_TYPE_MASK 0x1 +#define PCM0_SYNC_TYPE_MASK_SFT (0x1 << 8) +#define PCM0_BYP_ASRC_SFT 7 +#define PCM0_BYP_ASRC_MASK 0x1 +#define PCM0_BYP_ASRC_MASK_SFT (0x1 << 7) +#define PCM0_SLAVE_SFT 6 +#define PCM0_SLAVE_MASK 0x1 +#define PCM0_SLAVE_MASK_SFT (0x1 << 6) +#define PCM0_MODE_SFT 3 +#define PCM0_MODE_MASK 0x7 +#define PCM0_MODE_MASK_SFT (0x7 << 3) +#define PCM0_FMT_SFT 1 +#define PCM0_FMT_MASK 0x3 +#define PCM0_FMT_MASK_SFT (0x3 << 1) +#define PCM0_EN_SFT 0 +#define PCM0_EN_MASK 0x1 +#define PCM0_EN_MASK_SFT (0x1 << 0) + +/* AFE_PCM0_INTF_CON1 */ +#define PCM0_TX_RX_LOOPBACK_SFT 31 +#define PCM0_TX_RX_LOOPBACK_MASK 0x1 +#define PCM0_TX_RX_LOOPBACK_MASK_SFT (0x1 << 31) +#define PCM0_BUFFER_LOOPBACK_SFT 30 +#define PCM0_BUFFER_LOOPBACK_MASK 0x1 +#define PCM0_BUFFER_LOOPBACK_MASK_SFT (0x1 << 30) +#define PCM0_PARALLEL_LOOPBACK_SFT 29 +#define PCM0_PARALLEL_LOOPBACK_MASK 0x1 +#define PCM0_PARALLEL_LOOPBACK_MASK_SFT (0x1 << 29) +#define PCM0_SERIAL_LOOPBACK_SFT 28 +#define PCM0_SERIAL_LOOPBACK_MASK 0x1 +#define PCM0_SERIAL_LOOPBACK_MASK_SFT (0x1 << 28) +#define PCM0_DAI_LOOPBACK_SFT 27 +#define PCM0_DAI_LOOPBACK_MASK 0x1 +#define PCM0_DAI_LOOPBACK_MASK_SFT (0x1 << 27) +#define PCM0_I2S_LOOPBACK_SFT 26 +#define PCM0_I2S_LOOPBACK_MASK 0x1 +#define PCM0_I2S_LOOPBACK_MASK_SFT (0x1 << 26) +#define PCM0_1X_EN_DOMAIN_SFT 23 +#define PCM0_1X_EN_DOMAIN_MASK 0x7 +#define PCM0_1X_EN_DOMAIN_MASK_SFT (0x7 << 23) +#define PCM0_1X_EN_MODE_SFT 18 +#define PCM0_1X_EN_MODE_MASK 0x1f +#define PCM0_1X_EN_MODE_MASK_SFT (0x1f << 18) +#define PCM0_TX3_RCH_DBG_MODE_SFT 17 +#define PCM0_TX3_RCH_DBG_MODE_MASK 0x1 +#define PCM0_TX3_RCH_DBG_MODE_MASK_SFT (0x1 << 17) +#define PCM0_PCM1_LOOPBACK_SFT 16 +#define PCM0_PCM1_LOOPBACK_MASK 0x1 +#define PCM0_PCM1_LOOPBACK_MASK_SFT (0x1 << 16) +#define PCM0_LOOPBACK_CH_SEL_SFT 12 +#define PCM0_LOOPBACK_CH_SEL_MASK 0x3 +#define PCM0_LOOPBACK_CH_SEL_MASK_SFT (0x3 << 12) +#define PCM0_BT_MODE_SFT 11 +#define PCM0_BT_MODE_MASK 0x1 +#define PCM0_BT_MODE_MASK_SFT (0x1 << 11) +#define PCM0_EXT_MODEM_SFT 10 +#define PCM0_EXT_MODEM_MASK 0x1 +#define PCM0_EXT_MODEM_MASK_SFT (0x1 << 10) +#define PCM0_USE_MD3_SFT 9 +#define PCM0_USE_MD3_MASK 0x1 +#define PCM0_USE_MD3_MASK_SFT (0x1 << 9) +#define PCM0_FIX_VALUE_SEL_SFT 8 +#define PCM0_FIX_VALUE_SEL_MASK 0x1 +#define PCM0_FIX_VALUE_SEL_MASK_SFT (0x1 << 8) +#define PCM0_TX_FIX_VALUE_SFT 0 +#define PCM0_TX_FIX_VALUE_MASK 0xff +#define PCM0_TX_FIX_VALUE_MASK_SFT (0xff << 0) + +/* AFE_PCM_INTF_MON */ +#define PCM0_TX_FIFO_OV_SFT 5 +#define PCM0_TX_FIFO_OV_MASK 0x1 +#define PCM0_TX_FIFO_OV_MASK_SFT (0x1 << 5) +#define PCM0_RX_FIFO_OV_SFT 4 +#define PCM0_RX_FIFO_OV_MASK 0x1 +#define PCM0_RX_FIFO_OV_MASK_SFT (0x1 << 4) +#define PCM1_TX_FIFO_OV_SFT 3 +#define PCM1_TX_FIFO_OV_MASK 0x1 +#define PCM1_TX_FIFO_OV_MASK_SFT (0x1 << 3) +#define PCM1_RX_FIFO_OV_SFT 2 +#define PCM1_RX_FIFO_OV_MASK 0x1 +#define PCM1_RX_FIFO_OV_MASK_SFT (0x1 << 2) +#define PCM0_SYNC_GLITCH_SFT 1 +#define PCM0_SYNC_GLITCH_MASK 0x1 +#define PCM0_SYNC_GLITCH_MASK_SFT (0x1 << 1) +#define PCM1_SYNC_GLITCH_SFT 0 +#define PCM1_SYNC_GLITCH_MASK 0x1 +#define PCM1_SYNC_GLITCH_MASK_SFT (0x1 << 0) + +/* AFE_PCM1_INTF_CON0 */ +#define PCM1_TX_FIX_VALUE_SFT 24 +#define PCM1_TX_FIX_VALUE_MASK 0xff +#define PCM1_TX_FIX_VALUE_MASK_SFT (0xff << 24) +#define PCM1_FIX_VALUE_SEL_SFT 23 +#define PCM1_FIX_VALUE_SEL_MASK 0x1 +#define PCM1_FIX_VALUE_SEL_MASK_SFT (0x1 << 23) +#define PCM1_BUFFER_LOOPBACK_SFT 22 +#define PCM1_BUFFER_LOOPBACK_MASK 0x1 +#define PCM1_BUFFER_LOOPBACK_MASK_SFT (0x1 << 22) +#define PCM1_PARALLEL_LOOPBACK_SFT 21 +#define PCM1_PARALLEL_LOOPBACK_MASK 0x1 +#define PCM1_PARALLEL_LOOPBACK_MASK_SFT (0x1 << 21) +#define PCM1_SERIAL_LOOPBACK_SFT 20 +#define PCM1_SERIAL_LOOPBACK_MASK 0x1 +#define PCM1_SERIAL_LOOPBACK_MASK_SFT (0x1 << 20) +#define PCM1_DAI_PCM1_LOOPBACK_SFT 19 +#define PCM1_DAI_PCM1_LOOPBACK_MASK 0x1 +#define PCM1_DAI_PCM1_LOOPBACK_MASK_SFT (0x1 << 19) +#define PCM1_I2S_PCM1_LOOPBACK_SFT 18 +#define PCM1_I2S_PCM1_LOOPBACK_MASK 0x1 +#define PCM1_I2S_PCM1_LOOPBACK_MASK_SFT (0x1 << 18) +#define PCM1_SYNC_DELSEL_SFT 17 +#define PCM1_SYNC_DELSEL_MASK 0x1 +#define PCM1_SYNC_DELSEL_MASK_SFT (0x1 << 17) +#define PCM1_TX_LR_SWAP_SFT 16 +#define PCM1_TX_LR_SWAP_MASK 0x1 +#define PCM1_TX_LR_SWAP_MASK_SFT (0x1 << 16) +#define PCM1_SYNC_IN_INV_SFT 15 +#define PCM1_SYNC_IN_INV_MASK 0x1 +#define PCM1_SYNC_IN_INV_MASK_SFT (0x1 << 15) +#define PCM1_BCLK_IN_INV_SFT 14 +#define PCM1_BCLK_IN_INV_MASK 0x1 +#define PCM1_BCLK_IN_INV_MASK_SFT (0x1 << 14) +#define PCM1_TX_LCH_RPT_SFT 13 +#define PCM1_TX_LCH_RPT_MASK 0x1 +#define PCM1_TX_LCH_RPT_MASK_SFT (0x1 << 13) +#define PCM1_VBT_16K_MODE_SFT 12 +#define PCM1_VBT_16K_MODE_MASK 0x1 +#define PCM1_VBT_16K_MODE_MASK_SFT (0x1 << 12) +#define PCM1_LOOPBACK_CH_SEL_SFT 10 +#define PCM1_LOOPBACK_CH_SEL_MASK 0x3 +#define PCM1_LOOPBACK_CH_SEL_MASK_SFT (0x3 << 10) +#define PCM1_TX2_BT_MODE_SFT 8 +#define PCM1_TX2_BT_MODE_MASK 0x1 +#define PCM1_TX2_BT_MODE_MASK_SFT (0x1 << 8) +#define PCM1_BT_MODE_SFT 7 +#define PCM1_BT_MODE_MASK 0x1 +#define PCM1_BT_MODE_MASK_SFT (0x1 << 7) +#define PCM1_AFIFO_SFT 6 +#define PCM1_AFIFO_MASK 0x1 +#define PCM1_AFIFO_MASK_SFT (0x1 << 6) +#define PCM1_WLEN_SFT 5 +#define PCM1_WLEN_MASK 0x1 +#define PCM1_WLEN_MASK_SFT (0x1 << 5) +#define PCM1_MODE_SFT 3 +#define PCM1_MODE_MASK 0x3 +#define PCM1_MODE_MASK_SFT (0x3 << 3) +#define PCM1_FMT_SFT 1 +#define PCM1_FMT_MASK 0x3 +#define PCM1_FMT_MASK_SFT (0x3 << 1) +#define PCM1_EN_SFT 0 +#define PCM1_EN_MASK 0x1 +#define PCM1_EN_MASK_SFT (0x1 << 0) + +/* AFE_PCM1_INTF_CON1 */ +#define PCM1_1X_EN_DOMAIN_SFT 23 +#define PCM1_1X_EN_DOMAIN_MASK 0x7 +#define PCM1_1X_EN_DOMAIN_MASK_SFT (0x7 << 23) +#define PCM1_1X_EN_MODE_SFT 18 +#define PCM1_1X_EN_MODE_MASK 0x1f +#define PCM1_1X_EN_MODE_MASK_SFT (0x1f << 18) + +/* AFE_PCM_TOP_IP_VERSION */ +#define AFE_PCM_TOP_IP_VERSION_SFT 0 +#define AFE_PCM_TOP_IP_VERSION_MASK 0xffffffff +#define AFE_PCM_TOP_IP_VERSION_MASK_SFT (0xffffffff << 0) + +/* AFE_IRQ_MCU_EN */ +#define AFE_IRQ_MCU_EN_SFT 0 +#define AFE_IRQ_MCU_EN_MASK 0xffffffff +#define AFE_IRQ_MCU_EN_MASK_SFT (0xffffffff << 0) + +/* AFE_IRQ_MCU_DSP_EN */ +#define AFE_IRQ_DSP_EN_SFT 0 +#define AFE_IRQ_DSP_EN_MASK 0xffffffff +#define AFE_IRQ_DSP_EN_MASK_SFT (0xffffffff << 0) + +/* AFE_IRQ_MCU_DSP2_EN */ +#define AFE_IRQ_DSP2_EN_SFT 0 +#define AFE_IRQ_DSP2_EN_MASK 0xffffffff +#define AFE_IRQ_DSP2_EN_MASK_SFT (0xffffffff << 0) + +/* AFE_IRQ_MCU_SCP_EN */ +#define IRQ31_MCU_SCP_EN_SFT 31 +#define IRQ30_MCU_SCP_EN_SFT 30 +#define IRQ29_MCU_SCP_EN_SFT 29 +#define IRQ28_MCU_SCP_EN_SFT 28 +#define IRQ27_MCU_SCP_EN_SFT 27 +#define IRQ26_MCU_SCP_EN_SFT 26 +#define IRQ25_MCU_SCP_EN_SFT 25 +#define IRQ24_MCU_SCP_EN_SFT 24 +#define IRQ23_MCU_SCP_EN_SFT 23 +#define IRQ22_MCU_SCP_EN_SFT 22 +#define IRQ21_MCU_SCP_EN_SFT 21 +#define IRQ20_MCU_SCP_EN_SFT 20 +#define IRQ19_MCU_SCP_EN_SFT 19 +#define IRQ18_MCU_SCP_EN_SFT 18 +#define IRQ17_MCU_SCP_EN_SFT 17 +#define IRQ16_MCU_SCP_EN_SFT 16 +#define IRQ15_MCU_SCP_EN_SFT 15 +#define IRQ14_MCU_SCP_EN_SFT 14 +#define IRQ13_MCU_SCP_EN_SFT 13 +#define IRQ12_MCU_SCP_EN_SFT 12 +#define IRQ11_MCU_SCP_EN_SFT 11 +#define IRQ10_MCU_SCP_EN_SFT 10 +#define IRQ9_MCU_SCP_EN_SFT 9 +#define IRQ8_MCU_SCP_EN_SFT 8 +#define IRQ7_MCU_SCP_EN_SFT 7 +#define IRQ6_MCU_SCP_EN_SFT 6 +#define IRQ5_MCU_SCP_EN_SFT 5 +#define IRQ4_MCU_SCP_EN_SFT 4 +#define IRQ3_MCU_SCP_EN_SFT 3 +#define IRQ2_MCU_SCP_EN_SFT 2 +#define IRQ1_MCU_SCP_EN_SFT 1 +#define IRQ0_MCU_SCP_EN_SFT 0 + +/* AFE_CUSTOM_IRQ_MCU_EN */ +#define AFE_CUSTOM_IRQ_MCU_EN_SFT 0 +#define AFE_CUSTOM_IRQ_MCU_EN_MASK 0xffffffff +#define AFE_CUSTOM_IRQ_MCU_EN_MASK_SFT (0xffffffff << 0) + +/* AFE_CUSTOM_IRQ_MCU_DSP_EN */ +#define AFE_CUSTOM_IRQ_DSP_EN_SFT 0 +#define AFE_CUSTOM_IRQ_DSP_EN_MASK 0xffffffff +#define AFE_CUSTOM_IRQ_DSP_EN_MASK_SFT (0xffffffff << 0) + +/* AFE_CUSTOM_IRQ_MCU_DSP2_EN */ +#define AFE_CUSTOM_IRQ_DSP2_EN_SFT 0 +#define AFE_CUSTOM_IRQ_DSP2_EN_MASK 0xffffffff +#define AFE_CUSTOM_IRQ_DSP2_EN_MASK_SFT (0xffffffff << 0) + +/* AFE_CUSTOM_IRQ_MCU_SCP_EN */ +#define AFE_CUSTOM_IRQ_SCP_EN_SFT 0 +#define AFE_CUSTOM_IRQ_SCP_EN_MASK 0xffffffff +#define AFE_CUSTOM_IRQ_SCP_EN_MASK_SFT (0xffffffff << 0) + +/* AFE_IRQ_MCU_STATUS */ +#define IRQ26_MCU_SFT 26 +#define IRQ26_MCU_MASK 0x1 +#define IRQ26_MCU_MASK_SFT (0x1 << 26) +#define IRQ25_MCU_SFT 25 +#define IRQ25_MCU_MASK 0x1 +#define IRQ25_MCU_MASK_SFT (0x1 << 25) +#define IRQ24_MCU_SFT 24 +#define IRQ24_MCU_MASK 0x1 +#define IRQ24_MCU_MASK_SFT (0x1 << 24) +#define IRQ23_MCU_SFT 23 +#define IRQ23_MCU_MASK 0x1 +#define IRQ23_MCU_MASK_SFT (0x1 << 23) +#define IRQ22_MCU_SFT 22 +#define IRQ22_MCU_MASK 0x1 +#define IRQ22_MCU_MASK_SFT (0x1 << 22) +#define IRQ21_MCU_SFT 21 +#define IRQ21_MCU_MASK 0x1 +#define IRQ21_MCU_MASK_SFT (0x1 << 21) +#define IRQ20_MCU_SFT 20 +#define IRQ20_MCU_MASK 0x1 +#define IRQ20_MCU_MASK_SFT (0x1 << 20) +#define IRQ19_MCU_SFT 19 +#define IRQ19_MCU_MASK 0x1 +#define IRQ19_MCU_MASK_SFT (0x1 << 19) +#define IRQ18_MCU_SFT 18 +#define IRQ18_MCU_MASK 0x1 +#define IRQ18_MCU_MASK_SFT (0x1 << 18) +#define IRQ17_MCU_SFT 17 +#define IRQ17_MCU_MASK 0x1 +#define IRQ17_MCU_MASK_SFT (0x1 << 17) +#define IRQ16_MCU_SFT 16 +#define IRQ16_MCU_MASK 0x1 +#define IRQ16_MCU_MASK_SFT (0x1 << 16) +#define IRQ15_MCU_SFT 15 +#define IRQ15_MCU_MASK 0x1 +#define IRQ15_MCU_MASK_SFT (0x1 << 15) +#define IRQ14_MCU_SFT 14 +#define IRQ14_MCU_MASK 0x1 +#define IRQ14_MCU_MASK_SFT (0x1 << 14) +#define IRQ13_MCU_SFT 13 +#define IRQ13_MCU_MASK 0x1 +#define IRQ13_MCU_MASK_SFT (0x1 << 13) +#define IRQ12_MCU_SFT 12 +#define IRQ12_MCU_MASK 0x1 +#define IRQ12_MCU_MASK_SFT (0x1 << 12) +#define IRQ11_MCU_SFT 11 +#define IRQ11_MCU_MASK 0x1 +#define IRQ11_MCU_MASK_SFT (0x1 << 11) +#define IRQ10_MCU_SFT 10 +#define IRQ10_MCU_MASK 0x1 +#define IRQ10_MCU_MASK_SFT (0x1 << 10) +#define IRQ9_MCU_SFT 9 +#define IRQ9_MCU_MASK 0x1 +#define IRQ9_MCU_MASK_SFT (0x1 << 9) +#define IRQ8_MCU_SFT 8 +#define IRQ8_MCU_MASK 0x1 +#define IRQ8_MCU_MASK_SFT (0x1 << 8) +#define IRQ7_MCU_SFT 7 +#define IRQ7_MCU_MASK 0x1 +#define IRQ7_MCU_MASK_SFT (0x1 << 7) +#define IRQ6_MCU_SFT 6 +#define IRQ6_MCU_MASK 0x1 +#define IRQ6_MCU_MASK_SFT (0x1 << 6) +#define IRQ5_MCU_SFT 5 +#define IRQ5_MCU_MASK 0x1 +#define IRQ5_MCU_MASK_SFT (0x1 << 5) +#define IRQ4_MCU_SFT 4 +#define IRQ4_MCU_MASK 0x1 +#define IRQ4_MCU_MASK_SFT (0x1 << 4) +#define IRQ3_MCU_SFT 3 +#define IRQ3_MCU_MASK 0x1 +#define IRQ3_MCU_MASK_SFT (0x1 << 3) +#define IRQ2_MCU_SFT 2 +#define IRQ2_MCU_MASK 0x1 +#define IRQ2_MCU_MASK_SFT (0x1 << 2) +#define IRQ1_MCU_SFT 1 +#define IRQ1_MCU_MASK 0x1 +#define IRQ1_MCU_MASK_SFT (0x1 << 1) +#define IRQ0_MCU_SFT 0 +#define IRQ0_MCU_MASK 0x1 +#define IRQ0_MCU_MASK_SFT (0x1 << 0) + +/* AFE_CUSTOM_IRQ_MCU_STATUS */ +#define CUSTOM_IRQ21_MCU_SFT 21 +#define CUSTOM_IRQ21_MCU_MASK 0x1 +#define CUSTOM_IRQ21_MCU_MASK_SFT (0x1 << 21) +#define CUSTOM_IRQ20_MCU_SFT 20 +#define CUSTOM_IRQ20_MCU_MASK 0x1 +#define CUSTOM_IRQ20_MCU_MASK_SFT (0x1 << 20) +#define CUSTOM_IRQ19_MCU_SFT 19 +#define CUSTOM_IRQ19_MCU_MASK 0x1 +#define CUSTOM_IRQ19_MCU_MASK_SFT (0x1 << 19) +#define CUSTOM_IRQ18_MCU_SFT 18 +#define CUSTOM_IRQ18_MCU_MASK 0x1 +#define CUSTOM_IRQ18_MCU_MASK_SFT (0x1 << 18) +#define CUSTOM_IRQ17_MCU_SFT 17 +#define CUSTOM_IRQ17_MCU_MASK 0x1 +#define CUSTOM_IRQ17_MCU_MASK_SFT (0x1 << 17) +#define CUSTOM_IRQ16_MCU_SFT 16 +#define CUSTOM_IRQ16_MCU_MASK 0x1 +#define CUSTOM_IRQ16_MCU_MASK_SFT (0x1 << 16) +#define CUSTOM_IRQ9_MCU_SFT 9 +#define CUSTOM_IRQ9_MCU_MASK 0x1 +#define CUSTOM_IRQ9_MCU_MASK_SFT (0x1 << 9) +#define CUSTOM_IRQ8_MCU_SFT 8 +#define CUSTOM_IRQ8_MCU_MASK 0x1 +#define CUSTOM_IRQ8_MCU_MASK_SFT (0x1 << 8) +#define CUSTOM_IRQ7_MCU_SFT 7 +#define CUSTOM_IRQ7_MCU_MASK 0x1 +#define CUSTOM_IRQ7_MCU_MASK_SFT (0x1 << 7) +#define CUSTOM_IRQ6_MCU_SFT 6 +#define CUSTOM_IRQ6_MCU_MASK 0x1 +#define CUSTOM_IRQ6_MCU_MASK_SFT (0x1 << 6) +#define CUSTOM_IRQ5_MCU_SFT 5 +#define CUSTOM_IRQ5_MCU_MASK 0x1 +#define CUSTOM_IRQ5_MCU_MASK_SFT (0x1 << 5) +#define CUSTOM_IRQ4_MCU_SFT 4 +#define CUSTOM_IRQ4_MCU_MASK 0x1 +#define CUSTOM_IRQ4_MCU_MASK_SFT (0x1 << 4) +#define CUSTOM_IRQ3_MCU_SFT 3 +#define CUSTOM_IRQ3_MCU_MASK 0x1 +#define CUSTOM_IRQ3_MCU_MASK_SFT (0x1 << 3) +#define CUSTOM_IRQ2_MCU_SFT 2 +#define CUSTOM_IRQ2_MCU_MASK 0x1 +#define CUSTOM_IRQ2_MCU_MASK_SFT (0x1 << 2) +#define CUSTOM_IRQ1_MCU_SFT 1 +#define CUSTOM_IRQ1_MCU_MASK 0x1 +#define CUSTOM_IRQ1_MCU_MASK_SFT (0x1 << 1) +#define CUSTOM_IRQ0_MCU_SFT 0 +#define CUSTOM_IRQ0_MCU_MASK 0x1 +#define CUSTOM_IRQ0_MCU_MASK_SFT (0x1 << 0) + +/* AFE_IRQ_MCU_CFG */ +#define AFE_IRQ_CLR_CFG_SFT 31 +#define AFE_IRQ_CLR_CFG_MASK 0x1 +#define AFE_IRQ_CLR_CFG_MASK_SFT (0x1 << 31) +#define AFE_IRQ_MISS_FLAG_CLR_CFG_SFT 30 +#define AFE_IRQ_MISS_FLAG_CLR_CFG_MASK 0x1 +#define AFE_IRQ_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30) +#define AFE_IRQ_MCU_CNT_SFT 0 +#define AFE_IRQ_MCU_CNT_MASK 0xffffff +#define AFE_IRQ_MCU_CNT_MASK_SFT (0xffffff << 0) + +/* AFE_IRQ0_MCU_CFG0 */ +#define AFE_IRQ0_MCU_DOMAIN_SFT 9 +#define AFE_IRQ0_MCU_DOMAIN_MASK 0x7 +#define AFE_IRQ0_MCU_DOMAIN_MASK_SFT (0x7 << 9) +#define AFE_IRQ0_MCU_FS_SFT 4 +#define AFE_IRQ0_MCU_FS_MASK 0x1f +#define AFE_IRQ0_MCU_FS_MASK_SFT (0x1f << 4) +#define AFE_IRQ0_MCU_ON_SFT 0 +#define AFE_IRQ0_MCU_ON_MASK 0x1 +#define AFE_IRQ0_MCU_ON_MASK_SFT (0x1 << 0) + +/* AFE_IRQ0_MCU_CFG1 */ +#define AFE_IRQ0_CLR_CFG_SFT 31 +#define AFE_IRQ0_CLR_CFG_MASK 0x1 +#define AFE_IRQ0_CLR_CFG_MASK_SFT (0x1 << 31) +#define AFE_IRQ0_MISS_FLAG_CLR_CFG_SFT 30 +#define AFE_IRQ0_MISS_FLAG_CLR_CFG_MASK 0x1 +#define AFE_IRQ0_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30) +#define AFE_IRQ0_MCU_CNT_SFT 0 +#define AFE_IRQ0_MCU_CNT_MASK 0xffffff +#define AFE_IRQ0_MCU_CNT_MASK_SFT (0xffffff << 0) + +/* AFE_IRQ1_MCU_CFG0 */ +#define AFE_IRQ1_MCU_DOMAIN_SFT 9 +#define AFE_IRQ1_MCU_DOMAIN_MASK 0x7 +#define AFE_IRQ1_MCU_DOMAIN_MASK_SFT (0x7 << 9) +#define AFE_IRQ1_MCU_FS_SFT 4 +#define AFE_IRQ1_MCU_FS_MASK 0x1f +#define AFE_IRQ1_MCU_FS_MASK_SFT (0x1f << 4) +#define AFE_IRQ1_MCU_ON_SFT 0 +#define AFE_IRQ1_MCU_ON_MASK 0x1 +#define AFE_IRQ1_MCU_ON_MASK_SFT (0x1 << 0) + +/* AFE_IRQ1_MCU_CFG1 */ +#define AFE_IRQ1_CLR_CFG_SFT 31 +#define AFE_IRQ1_CLR_CFG_MASK 0x1 +#define AFE_IRQ1_CLR_CFG_MASK_SFT (0x1 << 31) +#define AFE_IRQ1_MISS_FLAG_CLR_CFG_SFT 30 +#define AFE_IRQ1_MISS_FLAG_CLR_CFG_MASK 0x1 +#define AFE_IRQ1_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30) +#define AFE_IRQ1_MCU_CNT_SFT 0 +#define AFE_IRQ1_MCU_CNT_MASK 0xffffff +#define AFE_IRQ1_MCU_CNT_MASK_SFT (0xffffff << 0) + +/* AFE_IRQ2_MCU_CFG0 */ +#define AFE_IRQ2_MCU_DOMAIN_SFT 9 +#define AFE_IRQ2_MCU_DOMAIN_MASK 0x7 +#define AFE_IRQ2_MCU_DOMAIN_MASK_SFT (0x7 << 9) +#define AFE_IRQ2_MCU_FS_SFT 4 +#define AFE_IRQ2_MCU_FS_MASK 0x1f +#define AFE_IRQ2_MCU_FS_MASK_SFT (0x1f << 4) +#define AFE_IRQ2_MCU_ON_SFT 0 +#define AFE_IRQ2_MCU_ON_MASK 0x1 +#define AFE_IRQ2_MCU_ON_MASK_SFT (0x1 << 0) + +/* AFE_IRQ2_MCU_CFG1 */ +#define AFE_IRQ2_CLR_CFG_SFT 31 +#define AFE_IRQ2_CLR_CFG_MASK 0x1 +#define AFE_IRQ2_CLR_CFG_MASK_SFT (0x1 << 31) +#define AFE_IRQ2_MISS_FLAG_CLR_CFG_SFT 30 +#define AFE_IRQ2_MISS_FLAG_CLR_CFG_MASK 0x1 +#define AFE_IRQ2_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30) +#define AFE_IRQ2_MCU_CNT_SFT 0 +#define AFE_IRQ2_MCU_CNT_MASK 0xffffff +#define AFE_IRQ2_MCU_CNT_MASK_SFT (0xffffff << 0) + +/* AFE_IRQ3_MCU_CFG0 */ +#define AFE_IRQ3_MCU_DOMAIN_SFT 9 +#define AFE_IRQ3_MCU_DOMAIN_MASK 0x7 +#define AFE_IRQ3_MCU_DOMAIN_MASK_SFT (0x7 << 9) +#define AFE_IRQ3_MCU_FS_SFT 4 +#define AFE_IRQ3_MCU_FS_MASK 0x1f +#define AFE_IRQ3_MCU_FS_MASK_SFT (0x1f << 4) +#define AFE_IRQ3_MCU_ON_SFT 0 +#define AFE_IRQ3_MCU_ON_MASK 0x1 +#define AFE_IRQ3_MCU_ON_MASK_SFT (0x1 << 0) + +/* AFE_IRQ3_MCU_CFG1 */ +#define AFE_IRQ3_CLR_CFG_SFT 31 +#define AFE_IRQ3_CLR_CFG_MASK 0x1 +#define AFE_IRQ3_CLR_CFG_MASK_SFT (0x1 << 31) +#define AFE_IRQ3_MISS_FLAG_CLR_CFG_SFT 30 +#define AFE_IRQ3_MISS_FLAG_CLR_CFG_MASK 0x1 +#define AFE_IRQ3_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30) +#define AFE_IRQ3_MCU_CNT_SFT 0 +#define AFE_IRQ3_MCU_CNT_MASK 0xffffff +#define AFE_IRQ3_MCU_CNT_MASK_SFT (0xffffff << 0) + +/* AFE_IRQ4_MCU_CFG0 */ +#define AFE_IRQ4_MCU_DOMAIN_SFT 9 +#define AFE_IRQ4_MCU_DOMAIN_MASK 0x7 +#define AFE_IRQ4_MCU_DOMAIN_MASK_SFT (0x7 << 9) +#define AFE_IRQ4_MCU_FS_SFT 4 +#define AFE_IRQ4_MCU_FS_MASK 0x1f +#define AFE_IRQ4_MCU_FS_MASK_SFT (0x1f << 4) +#define AFE_IRQ4_MCU_ON_SFT 0 +#define AFE_IRQ4_MCU_ON_MASK 0x1 +#define AFE_IRQ4_MCU_ON_MASK_SFT (0x1 << 0) + +/* AFE_IRQ4_MCU_CFG1 */ +#define AFE_IRQ4_CLR_CFG_SFT 31 +#define AFE_IRQ4_CLR_CFG_MASK 0x1 +#define AFE_IRQ4_CLR_CFG_MASK_SFT (0x1 << 31) +#define AFE_IRQ4_MISS_FLAG_CLR_CFG_SFT 30 +#define AFE_IRQ4_MISS_FLAG_CLR_CFG_MASK 0x1 +#define AFE_IRQ4_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30) +#define AFE_IRQ4_MCU_CNT_SFT 0 +#define AFE_IRQ4_MCU_CNT_MASK 0xffffff +#define AFE_IRQ4_MCU_CNT_MASK_SFT (0xffffff << 0) + +/* AFE_IRQ5_MCU_CFG0 */ +#define AFE_IRQ5_MCU_DOMAIN_SFT 9 +#define AFE_IRQ5_MCU_DOMAIN_MASK 0x7 +#define AFE_IRQ5_MCU_DOMAIN_MASK_SFT (0x7 << 9) +#define AFE_IRQ5_MCU_FS_SFT 4 +#define AFE_IRQ5_MCU_FS_MASK 0x1f +#define AFE_IRQ5_MCU_FS_MASK_SFT (0x1f << 4) +#define AFE_IRQ5_MCU_ON_SFT 0 +#define AFE_IRQ5_MCU_ON_MASK 0x1 +#define AFE_IRQ5_MCU_ON_MASK_SFT (0x1 << 0) + +/* AFE_IRQ5_MCU_CFG1 */ +#define AFE_IRQ5_CLR_CFG_SFT 31 +#define AFE_IRQ5_CLR_CFG_MASK 0x1 +#define AFE_IRQ5_CLR_CFG_MASK_SFT (0x1 << 31) +#define AFE_IRQ5_MISS_FLAG_CLR_CFG_SFT 30 +#define AFE_IRQ5_MISS_FLAG_CLR_CFG_MASK 0x1 +#define AFE_IRQ5_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30) +#define AFE_IRQ5_MCU_CNT_SFT 0 +#define AFE_IRQ5_MCU_CNT_MASK 0xffffff +#define AFE_IRQ5_MCU_CNT_MASK_SFT (0xffffff << 0) + +/* AFE_IRQ6_MCU_CFG0 */ +#define AFE_IRQ6_MCU_DOMAIN_SFT 9 +#define AFE_IRQ6_MCU_DOMAIN_MASK 0x7 +#define AFE_IRQ6_MCU_DOMAIN_MASK_SFT (0x7 << 9) +#define AFE_IRQ6_MCU_FS_SFT 4 +#define AFE_IRQ6_MCU_FS_MASK 0x1f +#define AFE_IRQ6_MCU_FS_MASK_SFT (0x1f << 4) +#define AFE_IRQ6_MCU_ON_SFT 0 +#define AFE_IRQ6_MCU_ON_MASK 0x1 +#define AFE_IRQ6_MCU_ON_MASK_SFT (0x1 << 0) + +/* AFE_IRQ6_MCU_CFG1 */ +#define AFE_IRQ6_CLR_CFG_SFT 31 +#define AFE_IRQ6_CLR_CFG_MASK 0x1 +#define AFE_IRQ6_CLR_CFG_MASK_SFT (0x1 << 31) +#define AFE_IRQ6_MISS_FLAG_CLR_CFG_SFT 30 +#define AFE_IRQ6_MISS_FLAG_CLR_CFG_MASK 0x1 +#define AFE_IRQ6_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30) +#define AFE_IRQ6_MCU_CNT_SFT 0 +#define AFE_IRQ6_MCU_CNT_MASK 0xffffff +#define AFE_IRQ6_MCU_CNT_MASK_SFT (0xffffff << 0) + +/* AFE_IRQ7_MCU_CFG0 */ +#define AFE_IRQ7_MCU_DOMAIN_SFT 9 +#define AFE_IRQ7_MCU_DOMAIN_MASK 0x7 +#define AFE_IRQ7_MCU_DOMAIN_MASK_SFT (0x7 << 9) +#define AFE_IRQ7_MCU_FS_SFT 4 +#define AFE_IRQ7_MCU_FS_MASK 0x1f +#define AFE_IRQ7_MCU_FS_MASK_SFT (0x1f << 4) +#define AFE_IRQ7_MCU_ON_SFT 0 +#define AFE_IRQ7_MCU_ON_MASK 0x1 +#define AFE_IRQ7_MCU_ON_MASK_SFT (0x1 << 0) + +/* AFE_IRQ7_MCU_CFG1 */ +#define AFE_IRQ7_CLR_CFG_SFT 31 +#define AFE_IRQ7_CLR_CFG_MASK 0x1 +#define AFE_IRQ7_CLR_CFG_MASK_SFT (0x1 << 31) +#define AFE_IRQ7_MISS_FLAG_CLR_CFG_SFT 30 +#define AFE_IRQ7_MISS_FLAG_CLR_CFG_MASK 0x1 +#define AFE_IRQ7_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30) +#define AFE_IRQ7_MCU_CNT_SFT 0 +#define AFE_IRQ7_MCU_CNT_MASK 0xffffff +#define AFE_IRQ7_MCU_CNT_MASK_SFT (0xffffff << 0) + +/* AFE_IRQ8_MCU_CFG0 */ +#define AFE_IRQ8_MCU_DOMAIN_SFT 9 +#define AFE_IRQ8_MCU_DOMAIN_MASK 0x7 +#define AFE_IRQ8_MCU_DOMAIN_MASK_SFT (0x7 << 9) +#define AFE_IRQ8_MCU_FS_SFT 4 +#define AFE_IRQ8_MCU_FS_MASK 0x1f +#define AFE_IRQ8_MCU_FS_MASK_SFT (0x1f << 4) +#define AFE_IRQ8_MCU_ON_SFT 0 +#define AFE_IRQ8_MCU_ON_MASK 0x1 +#define AFE_IRQ8_MCU_ON_MASK_SFT (0x1 << 0) + +/* AFE_IRQ8_MCU_CFG1 */ +#define AFE_IRQ8_CLR_CFG_SFT 31 +#define AFE_IRQ8_CLR_CFG_MASK 0x1 +#define AFE_IRQ8_CLR_CFG_MASK_SFT (0x1 << 31) +#define AFE_IRQ8_MISS_FLAG_CLR_CFG_SFT 30 +#define AFE_IRQ8_MISS_FLAG_CLR_CFG_MASK 0x1 +#define AFE_IRQ8_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30) +#define AFE_IRQ8_MCU_CNT_SFT 0 +#define AFE_IRQ8_MCU_CNT_MASK 0xffffff +#define AFE_IRQ8_MCU_CNT_MASK_SFT (0xffffff << 0) + +/* AFE_IRQ9_MCU_CFG0 */ +#define AFE_IRQ9_MCU_DOMAIN_SFT 9 +#define AFE_IRQ9_MCU_DOMAIN_MASK 0x7 +#define AFE_IRQ9_MCU_DOMAIN_MASK_SFT (0x7 << 9) +#define AFE_IRQ9_MCU_FS_SFT 4 +#define AFE_IRQ9_MCU_FS_MASK 0x1f +#define AFE_IRQ9_MCU_FS_MASK_SFT (0x1f << 4) +#define AFE_IRQ9_MCU_ON_SFT 0 +#define AFE_IRQ9_MCU_ON_MASK 0x1 +#define AFE_IRQ9_MCU_ON_MASK_SFT (0x1 << 0) + +/* AFE_IRQ9_MCU_CFG1 */ +#define AFE_IRQ9_CLR_CFG_SFT 31 +#define AFE_IRQ9_CLR_CFG_MASK 0x1 +#define AFE_IRQ9_CLR_CFG_MASK_SFT (0x1 << 31) +#define AFE_IRQ9_MISS_FLAG_CLR_CFG_SFT 30 +#define AFE_IRQ9_MISS_FLAG_CLR_CFG_MASK 0x1 +#define AFE_IRQ9_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30) +#define AFE_IRQ9_MCU_CNT_SFT 0 +#define AFE_IRQ9_MCU_CNT_MASK 0xffffff +#define AFE_IRQ9_MCU_CNT_MASK_SFT (0xffffff << 0) + +/* AFE_IRQ10_MCU_CFG0 */ +#define AFE_IRQ10_MCU_DOMAIN_SFT 9 +#define AFE_IRQ10_MCU_DOMAIN_MASK 0x7 +#define AFE_IRQ10_MCU_DOMAIN_MASK_SFT (0x7 << 9) +#define AFE_IRQ10_MCU_FS_SFT 4 +#define AFE_IRQ10_MCU_FS_MASK 0x1f +#define AFE_IRQ10_MCU_FS_MASK_SFT (0x1f << 4) +#define AFE_IRQ10_MCU_ON_SFT 0 +#define AFE_IRQ10_MCU_ON_MASK 0x1 +#define AFE_IRQ10_MCU_ON_MASK_SFT (0x1 << 0) + +/* AFE_IRQ10_MCU_CFG1 */ +#define AFE_IRQ10_CLR_CFG_SFT 31 +#define AFE_IRQ10_CLR_CFG_MASK 0x1 +#define AFE_IRQ10_CLR_CFG_MASK_SFT (0x1 << 31) +#define AFE_IRQ10_MISS_FLAG_CLR_CFG_SFT 30 +#define AFE_IRQ10_MISS_FLAG_CLR_CFG_MASK 0x1 +#define AFE_IRQ10_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30) +#define AFE_IRQ10_MCU_CNT_SFT 0 +#define AFE_IRQ10_MCU_CNT_MASK 0xffffff +#define AFE_IRQ10_MCU_CNT_MASK_SFT (0xffffff << 0) + +/* AFE_IRQ11_MCU_CFG0 */ +#define AFE_IRQ11_MCU_DOMAIN_SFT 9 +#define AFE_IRQ11_MCU_DOMAIN_MASK 0x7 +#define AFE_IRQ11_MCU_DOMAIN_MASK_SFT (0x7 << 9) +#define AFE_IRQ11_MCU_FS_SFT 4 +#define AFE_IRQ11_MCU_FS_MASK 0x1f +#define AFE_IRQ11_MCU_FS_MASK_SFT (0x1f << 4) +#define AFE_IRQ11_MCU_ON_SFT 0 +#define AFE_IRQ11_MCU_ON_MASK 0x1 +#define AFE_IRQ11_MCU_ON_MASK_SFT (0x1 << 0) + +/* AFE_IRQ11_MCU_CFG1 */ +#define AFE_IRQ11_CLR_CFG_SFT 31 +#define AFE_IRQ11_CLR_CFG_MASK 0x1 +#define AFE_IRQ11_CLR_CFG_MASK_SFT (0x1 << 31) +#define AFE_IRQ11_MISS_FLAG_CLR_CFG_SFT 30 +#define AFE_IRQ11_MISS_FLAG_CLR_CFG_MASK 0x1 +#define AFE_IRQ11_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30) +#define AFE_IRQ11_MCU_CNT_SFT 0 +#define AFE_IRQ11_MCU_CNT_MASK 0xffffff +#define AFE_IRQ11_MCU_CNT_MASK_SFT (0xffffff << 0) + +/* AFE_IRQ12_MCU_CFG0 */ +#define AFE_IRQ12_MCU_DOMAIN_SFT 9 +#define AFE_IRQ12_MCU_DOMAIN_MASK 0x7 +#define AFE_IRQ12_MCU_DOMAIN_MASK_SFT (0x7 << 9) +#define AFE_IRQ12_MCU_FS_SFT 4 +#define AFE_IRQ12_MCU_FS_MASK 0x1f +#define AFE_IRQ12_MCU_FS_MASK_SFT (0x1f << 4) +#define AFE_IRQ12_MCU_ON_SFT 0 +#define AFE_IRQ12_MCU_ON_MASK 0x1 +#define AFE_IRQ12_MCU_ON_MASK_SFT (0x1 << 0) + +/* AFE_IRQ12_MCU_CFG1 */ +#define AFE_IRQ12_CLR_CFG_SFT 31 +#define AFE_IRQ12_CLR_CFG_MASK 0x1 +#define AFE_IRQ12_CLR_CFG_MASK_SFT (0x1 << 31) +#define AFE_IRQ12_MISS_FLAG_CLR_CFG_SFT 30 +#define AFE_IRQ12_MISS_FLAG_CLR_CFG_MASK 0x1 +#define AFE_IRQ12_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30) +#define AFE_IRQ12_MCU_CNT_SFT 0 +#define AFE_IRQ12_MCU_CNT_MASK 0xffffff +#define AFE_IRQ12_MCU_CNT_MASK_SFT (0xffffff << 0) + +/* AFE_IRQ13_MCU_CFG0 */ +#define AFE_IRQ13_MCU_DOMAIN_SFT 9 +#define AFE_IRQ13_MCU_DOMAIN_MASK 0x7 +#define AFE_IRQ13_MCU_DOMAIN_MASK_SFT (0x7 << 9) +#define AFE_IRQ13_MCU_FS_SFT 4 +#define AFE_IRQ13_MCU_FS_MASK 0x1f +#define AFE_IRQ13_MCU_FS_MASK_SFT (0x1f << 4) +#define AFE_IRQ13_MCU_ON_SFT 0 +#define AFE_IRQ13_MCU_ON_MASK 0x1 +#define AFE_IRQ13_MCU_ON_MASK_SFT (0x1 << 0) + +/* AFE_IRQ13_MCU_CFG1 */ +#define AFE_IRQ13_CLR_CFG_SFT 31 +#define AFE_IRQ13_CLR_CFG_MASK 0x1 +#define AFE_IRQ13_CLR_CFG_MASK_SFT (0x1 << 31) +#define AFE_IRQ13_MISS_FLAG_CLR_CFG_SFT 30 +#define AFE_IRQ13_MISS_FLAG_CLR_CFG_MASK 0x1 +#define AFE_IRQ13_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30) +#define AFE_IRQ13_MCU_CNT_SFT 0 +#define AFE_IRQ13_MCU_CNT_MASK 0xffffff +#define AFE_IRQ13_MCU_CNT_MASK_SFT (0xffffff << 0) + +/* AFE_IRQ14_MCU_CFG0 */ +#define AFE_IRQ14_MCU_DOMAIN_SFT 9 +#define AFE_IRQ14_MCU_DOMAIN_MASK 0x7 +#define AFE_IRQ14_MCU_DOMAIN_MASK_SFT (0x7 << 9) +#define AFE_IRQ14_MCU_FS_SFT 4 +#define AFE_IRQ14_MCU_FS_MASK 0x1f +#define AFE_IRQ14_MCU_FS_MASK_SFT (0x1f << 4) +#define AFE_IRQ14_MCU_ON_SFT 0 +#define AFE_IRQ14_MCU_ON_MASK 0x1 +#define AFE_IRQ14_MCU_ON_MASK_SFT (0x1 << 0) + +/* AFE_IRQ14_MCU_CFG1 */ +#define AFE_IRQ14_CLR_CFG_SFT 31 +#define AFE_IRQ14_CLR_CFG_MASK 0x1 +#define AFE_IRQ14_CLR_CFG_MASK_SFT (0x1 << 31) +#define AFE_IRQ14_MISS_FLAG_CLR_CFG_SFT 30 +#define AFE_IRQ14_MISS_FLAG_CLR_CFG_MASK 0x1 +#define AFE_IRQ14_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30) +#define AFE_IRQ14_MCU_CNT_SFT 0 +#define AFE_IRQ14_MCU_CNT_MASK 0xffffff +#define AFE_IRQ14_MCU_CNT_MASK_SFT (0xffffff << 0) + +/* AFE_IRQ15_MCU_CFG0 */ +#define AFE_IRQ15_MCU_DOMAIN_SFT 9 +#define AFE_IRQ15_MCU_DOMAIN_MASK 0x7 +#define AFE_IRQ15_MCU_DOMAIN_MASK_SFT (0x7 << 9) +#define AFE_IRQ15_MCU_FS_SFT 4 +#define AFE_IRQ15_MCU_FS_MASK 0x1f +#define AFE_IRQ15_MCU_FS_MASK_SFT (0x1f << 4) +#define AFE_IRQ15_MCU_ON_SFT 0 +#define AFE_IRQ15_MCU_ON_MASK 0x1 +#define AFE_IRQ15_MCU_ON_MASK_SFT (0x1 << 0) + +/* AFE_IRQ15_MCU_CFG1 */ +#define AFE_IRQ15_CLR_CFG_SFT 31 +#define AFE_IRQ15_CLR_CFG_MASK 0x1 +#define AFE_IRQ15_CLR_CFG_MASK_SFT (0x1 << 31) +#define AFE_IRQ15_MISS_FLAG_CLR_CFG_SFT 30 +#define AFE_IRQ15_MISS_FLAG_CLR_CFG_MASK 0x1 +#define AFE_IRQ15_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30) +#define AFE_IRQ15_MCU_CNT_SFT 0 +#define AFE_IRQ15_MCU_CNT_MASK 0xffffff +#define AFE_IRQ15_MCU_CNT_MASK_SFT (0xffffff << 0) + +/* AFE_IRQ16_MCU_CFG0 */ +#define AFE_IRQ16_MCU_DOMAIN_SFT 9 +#define AFE_IRQ16_MCU_DOMAIN_MASK 0x7 +#define AFE_IRQ16_MCU_DOMAIN_MASK_SFT (0x7 << 9) +#define AFE_IRQ16_MCU_FS_SFT 4 +#define AFE_IRQ16_MCU_FS_MASK 0x1f +#define AFE_IRQ16_MCU_FS_MASK_SFT (0x1f << 4) +#define AFE_IRQ16_MCU_ON_SFT 0 +#define AFE_IRQ16_MCU_ON_MASK 0x1 +#define AFE_IRQ16_MCU_ON_MASK_SFT (0x1 << 0) + +/* AFE_IRQ16_MCU_CFG1 */ +#define AFE_IRQ16_CLR_CFG_SFT 31 +#define AFE_IRQ16_CLR_CFG_MASK 0x1 +#define AFE_IRQ16_CLR_CFG_MASK_SFT (0x1 << 31) +#define AFE_IRQ16_MISS_FLAG_CLR_CFG_SFT 30 +#define AFE_IRQ16_MISS_FLAG_CLR_CFG_MASK 0x1 +#define AFE_IRQ16_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30) +#define AFE_IRQ16_MCU_CNT_SFT 0 +#define AFE_IRQ16_MCU_CNT_MASK 0xffffff +#define AFE_IRQ16_MCU_CNT_MASK_SFT (0xffffff << 0) + +/* AFE_IRQ17_MCU_CFG0 */ +#define AFE_IRQ17_MCU_DOMAIN_SFT 9 +#define AFE_IRQ17_MCU_DOMAIN_MASK 0x7 +#define AFE_IRQ17_MCU_DOMAIN_MASK_SFT (0x7 << 9) +#define AFE_IRQ17_MCU_FS_SFT 4 +#define AFE_IRQ17_MCU_FS_MASK 0x1f +#define AFE_IRQ17_MCU_FS_MASK_SFT (0x1f << 4) +#define AFE_IRQ17_MCU_ON_SFT 0 +#define AFE_IRQ17_MCU_ON_MASK 0x1 +#define AFE_IRQ17_MCU_ON_MASK_SFT (0x1 << 0) + +/* AFE_IRQ17_MCU_CFG1 */ +#define AFE_IRQ17_CLR_CFG_SFT 31 +#define AFE_IRQ17_CLR_CFG_MASK 0x1 +#define AFE_IRQ17_CLR_CFG_MASK_SFT (0x1 << 31) +#define AFE_IRQ17_MISS_FLAG_CLR_CFG_SFT 30 +#define AFE_IRQ17_MISS_FLAG_CLR_CFG_MASK 0x1 +#define AFE_IRQ17_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30) +#define AFE_IRQ17_MCU_CNT_SFT 0 +#define AFE_IRQ17_MCU_CNT_MASK 0xffffff +#define AFE_IRQ17_MCU_CNT_MASK_SFT (0xffffff << 0) + +/* AFE_IRQ18_MCU_CFG0 */ +#define AFE_IRQ18_MCU_DOMAIN_SFT 9 +#define AFE_IRQ18_MCU_DOMAIN_MASK 0x7 +#define AFE_IRQ18_MCU_DOMAIN_MASK_SFT (0x7 << 9) +#define AFE_IRQ18_MCU_FS_SFT 4 +#define AFE_IRQ18_MCU_FS_MASK 0x1f +#define AFE_IRQ18_MCU_FS_MASK_SFT (0x1f << 4) +#define AFE_IRQ18_MCU_ON_SFT 0 +#define AFE_IRQ18_MCU_ON_MASK 0x1 +#define AFE_IRQ18_MCU_ON_MASK_SFT (0x1 << 0) + +/* AFE_IRQ18_MCU_CFG1 */ +#define AFE_IRQ18_CLR_CFG_SFT 31 +#define AFE_IRQ18_CLR_CFG_MASK 0x1 +#define AFE_IRQ18_CLR_CFG_MASK_SFT (0x1 << 31) +#define AFE_IRQ18_MISS_FLAG_CLR_CFG_SFT 30 +#define AFE_IRQ18_MISS_FLAG_CLR_CFG_MASK 0x1 +#define AFE_IRQ18_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30) +#define AFE_IRQ18_MCU_CNT_SFT 0 +#define AFE_IRQ18_MCU_CNT_MASK 0xffffff +#define AFE_IRQ18_MCU_CNT_MASK_SFT (0xffffff << 0) + +/* AFE_IRQ19_MCU_CFG0 */ +#define AFE_IRQ19_MCU_DOMAIN_SFT 9 +#define AFE_IRQ19_MCU_DOMAIN_MASK 0x7 +#define AFE_IRQ19_MCU_DOMAIN_MASK_SFT (0x7 << 9) +#define AFE_IRQ19_MCU_FS_SFT 4 +#define AFE_IRQ19_MCU_FS_MASK 0x1f +#define AFE_IRQ19_MCU_FS_MASK_SFT (0x1f << 4) +#define AFE_IRQ19_MCU_ON_SFT 0 +#define AFE_IRQ19_MCU_ON_MASK 0x1 +#define AFE_IRQ19_MCU_ON_MASK_SFT (0x1 << 0) + +/* AFE_IRQ19_MCU_CFG1 */ +#define AFE_IRQ19_CLR_CFG_SFT 31 +#define AFE_IRQ19_CLR_CFG_MASK 0x1 +#define AFE_IRQ19_CLR_CFG_MASK_SFT (0x1 << 31) +#define AFE_IRQ19_MISS_FLAG_CLR_CFG_SFT 30 +#define AFE_IRQ19_MISS_FLAG_CLR_CFG_MASK 0x1 +#define AFE_IRQ19_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30) +#define AFE_IRQ19_MCU_CNT_SFT 0 +#define AFE_IRQ19_MCU_CNT_MASK 0xffffff +#define AFE_IRQ19_MCU_CNT_MASK_SFT (0xffffff << 0) + +/* AFE_IRQ20_MCU_CFG0 */ +#define AFE_IRQ20_MCU_DOMAIN_SFT 9 +#define AFE_IRQ20_MCU_DOMAIN_MASK 0x7 +#define AFE_IRQ20_MCU_DOMAIN_MASK_SFT (0x7 << 9) +#define AFE_IRQ20_MCU_FS_SFT 4 +#define AFE_IRQ20_MCU_FS_MASK 0x1f +#define AFE_IRQ20_MCU_FS_MASK_SFT (0x1f << 4) +#define AFE_IRQ20_MCU_ON_SFT 0 +#define AFE_IRQ20_MCU_ON_MASK 0x1 +#define AFE_IRQ20_MCU_ON_MASK_SFT (0x1 << 0) + +/* AFE_IRQ20_MCU_CFG1 */ +#define AFE_IRQ20_CLR_CFG_SFT 31 +#define AFE_IRQ20_CLR_CFG_MASK 0x1 +#define AFE_IRQ20_CLR_CFG_MASK_SFT (0x1 << 31) +#define AFE_IRQ20_MISS_FLAG_CLR_CFG_SFT 30 +#define AFE_IRQ20_MISS_FLAG_CLR_CFG_MASK 0x1 +#define AFE_IRQ20_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30) +#define AFE_IRQ20_MCU_CNT_SFT 0 +#define AFE_IRQ20_MCU_CNT_MASK 0xffffff +#define AFE_IRQ20_MCU_CNT_MASK_SFT (0xffffff << 0) + +/* AFE_IRQ21_MCU_CFG0 */ +#define AFE_IRQ21_MCU_DOMAIN_SFT 9 +#define AFE_IRQ21_MCU_DOMAIN_MASK 0x7 +#define AFE_IRQ21_MCU_DOMAIN_MASK_SFT (0x7 << 9) +#define AFE_IRQ21_MCU_FS_SFT 4 +#define AFE_IRQ21_MCU_FS_MASK 0x1f +#define AFE_IRQ21_MCU_FS_MASK_SFT (0x1f << 4) +#define AFE_IRQ21_MCU_ON_SFT 0 +#define AFE_IRQ21_MCU_ON_MASK 0x1 +#define AFE_IRQ21_MCU_ON_MASK_SFT (0x1 << 0) + +/* AFE_IRQ21_MCU_CFG1 */ +#define AFE_IRQ21_CLR_CFG_SFT 31 +#define AFE_IRQ21_CLR_CFG_MASK 0x1 +#define AFE_IRQ21_CLR_CFG_MASK_SFT (0x1 << 31) +#define AFE_IRQ21_MISS_FLAG_CLR_CFG_SFT 30 +#define AFE_IRQ21_MISS_FLAG_CLR_CFG_MASK 0x1 +#define AFE_IRQ21_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30) +#define AFE_IRQ21_MCU_CNT_SFT 0 +#define AFE_IRQ21_MCU_CNT_MASK 0xffffff +#define AFE_IRQ21_MCU_CNT_MASK_SFT (0xffffff << 0) + +/* AFE_IRQ22_MCU_CFG0 */ +#define AFE_IRQ22_MCU_DOMAIN_SFT 9 +#define AFE_IRQ22_MCU_DOMAIN_MASK 0x7 +#define AFE_IRQ22_MCU_DOMAIN_MASK_SFT (0x7 << 9) +#define AFE_IRQ22_MCU_FS_SFT 4 +#define AFE_IRQ22_MCU_FS_MASK 0x1f +#define AFE_IRQ22_MCU_FS_MASK_SFT (0x1f << 4) +#define AFE_IRQ22_MCU_ON_SFT 0 +#define AFE_IRQ22_MCU_ON_MASK 0x1 +#define AFE_IRQ22_MCU_ON_MASK_SFT (0x1 << 0) + +/* AFE_IRQ22_MCU_CFG1 */ +#define AFE_IRQ22_CLR_CFG_SFT 31 +#define AFE_IRQ22_CLR_CFG_MASK 0x1 +#define AFE_IRQ22_CLR_CFG_MASK_SFT (0x1 << 31) +#define AFE_IRQ22_MISS_FLAG_CLR_CFG_SFT 30 +#define AFE_IRQ22_MISS_FLAG_CLR_CFG_MASK 0x1 +#define AFE_IRQ22_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30) +#define AFE_IRQ22_MCU_CNT_SFT 0 +#define AFE_IRQ22_MCU_CNT_MASK 0xffffff +#define AFE_IRQ22_MCU_CNT_MASK_SFT (0xffffff << 0) + +/* AFE_IRQ23_MCU_CFG0 */ +#define AFE_IRQ23_MCU_DOMAIN_SFT 9 +#define AFE_IRQ23_MCU_DOMAIN_MASK 0x7 +#define AFE_IRQ23_MCU_DOMAIN_MASK_SFT (0x7 << 9) +#define AFE_IRQ23_MCU_FS_SFT 4 +#define AFE_IRQ23_MCU_FS_MASK 0x1f +#define AFE_IRQ23_MCU_FS_MASK_SFT (0x1f << 4) +#define AFE_IRQ23_MCU_ON_SFT 0 +#define AFE_IRQ23_MCU_ON_MASK 0x1 +#define AFE_IRQ23_MCU_ON_MASK_SFT (0x1 << 0) + +/* AFE_IRQ23_MCU_CFG1 */ +#define AFE_IRQ23_CLR_CFG_SFT 31 +#define AFE_IRQ23_CLR_CFG_MASK 0x1 +#define AFE_IRQ23_CLR_CFG_MASK_SFT (0x1 << 31) +#define AFE_IRQ23_MISS_FLAG_CLR_CFG_SFT 30 +#define AFE_IRQ23_MISS_FLAG_CLR_CFG_MASK 0x1 +#define AFE_IRQ23_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30) +#define AFE_IRQ23_MCU_CNT_SFT 0 +#define AFE_IRQ23_MCU_CNT_MASK 0xffffff +#define AFE_IRQ23_MCU_CNT_MASK_SFT (0xffffff << 0) + +/* AFE_IRQ24_MCU_CFG0 */ +#define AFE_IRQ24_MCU_DOMAIN_SFT 9 +#define AFE_IRQ24_MCU_DOMAIN_MASK 0x7 +#define AFE_IRQ24_MCU_DOMAIN_MASK_SFT (0x7 << 9) +#define AFE_IRQ24_MCU_FS_SFT 4 +#define AFE_IRQ24_MCU_FS_MASK 0x1f +#define AFE_IRQ24_MCU_FS_MASK_SFT (0x1f << 4) +#define AFE_IRQ24_MCU_ON_SFT 0 +#define AFE_IRQ24_MCU_ON_MASK 0x1 +#define AFE_IRQ24_MCU_ON_MASK_SFT (0x1 << 0) + +/* AFE_IRQ24_MCU_CFG1 */ +#define AFE_IRQ24_CLR_CFG_SFT 31 +#define AFE_IRQ24_CLR_CFG_MASK 0x1 +#define AFE_IRQ24_CLR_CFG_MASK_SFT (0x1 << 31) +#define AFE_IRQ24_MISS_FLAG_CLR_CFG_SFT 30 +#define AFE_IRQ24_MISS_FLAG_CLR_CFG_MASK 0x1 +#define AFE_IRQ24_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30) +#define AFE_IRQ24_MCU_CNT_SFT 0 +#define AFE_IRQ24_MCU_CNT_MASK 0xffffff +#define AFE_IRQ24_MCU_CNT_MASK_SFT (0xffffff << 0) + +/* AFE_IRQ25_MCU_CFG0 */ +#define AFE_IRQ25_MCU_DOMAIN_SFT 9 +#define AFE_IRQ25_MCU_DOMAIN_MASK 0x7 +#define AFE_IRQ25_MCU_DOMAIN_MASK_SFT (0x7 << 9) +#define AFE_IRQ25_MCU_FS_SFT 4 +#define AFE_IRQ25_MCU_FS_MASK 0x1f +#define AFE_IRQ25_MCU_FS_MASK_SFT (0x1f << 4) +#define AFE_IRQ25_MCU_ON_SFT 0 +#define AFE_IRQ25_MCU_ON_MASK 0x1 +#define AFE_IRQ25_MCU_ON_MASK_SFT (0x1 << 0) + +/* AFE_IRQ25_MCU_CFG1 */ +#define AFE_IRQ25_CLR_CFG_SFT 31 +#define AFE_IRQ25_CLR_CFG_MASK 0x1 +#define AFE_IRQ25_CLR_CFG_MASK_SFT (0x1 << 31) +#define AFE_IRQ25_MISS_FLAG_CLR_CFG_SFT 30 +#define AFE_IRQ25_MISS_FLAG_CLR_CFG_MASK 0x1 +#define AFE_IRQ25_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30) +#define AFE_IRQ25_MCU_CNT_SFT 0 +#define AFE_IRQ25_MCU_CNT_MASK 0xffffff +#define AFE_IRQ25_MCU_CNT_MASK_SFT (0xffffff << 0) + +/* AFE_IRQ26_MCU_CFG0 */ +#define AFE_IRQ26_MCU_DOMAIN_SFT 9 +#define AFE_IRQ26_MCU_DOMAIN_MASK 0x7 +#define AFE_IRQ26_MCU_DOMAIN_MASK_SFT (0x7 << 9) +#define AFE_IRQ26_MCU_FS_SFT 4 +#define AFE_IRQ26_MCU_FS_MASK 0x1f +#define AFE_IRQ26_MCU_FS_MASK_SFT (0x1f << 4) +#define AFE_IRQ26_MCU_ON_SFT 0 +#define AFE_IRQ26_MCU_ON_MASK 0x1 +#define AFE_IRQ26_MCU_ON_MASK_SFT (0x1 << 0) + +/* AFE_IRQ26_MCU_CFG1 */ +#define AFE_IRQ26_CLR_CFG_SFT 31 +#define AFE_IRQ26_CLR_CFG_MASK 0x1 +#define AFE_IRQ26_CLR_CFG_MASK_SFT (0x1 << 31) +#define AFE_IRQ26_MISS_FLAG_CLR_CFG_SFT 30 +#define AFE_IRQ26_MISS_FLAG_CLR_CFG_MASK 0x1 +#define AFE_IRQ26_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30) +#define AFE_IRQ26_MCU_CNT_SFT 0 +#define AFE_IRQ26_MCU_CNT_MASK 0xffffff +#define AFE_IRQ26_MCU_CNT_MASK_SFT (0xffffff << 0) + +/* AFE_CUSTOM_IRQ0_MCU_CFG0 */ +#define AFE_CUSTOM_IRQ0_MCU_ON_SFT 0 +#define AFE_CUSTOM_IRQ0_MCU_ON_MASK 0x1 +#define AFE_CUSTOM_IRQ0_MCU_ON_MASK_SFT (0x1 << 0) + +/* AFE_IRQ_MCU_MON0 */ +#define AFE_IRQ26_MISS_FLAG_SFT 26 +#define AFE_IRQ26_MISS_FLAG_MASK 0x1 +#define AFE_IRQ26_MISS_FLAG_MASK_SFT (0x1 << 26) +#define AFE_IRQ25_MISS_FLAG_SFT 25 +#define AFE_IRQ25_MISS_FLAG_MASK 0x1 +#define AFE_IRQ25_MISS_FLAG_MASK_SFT (0x1 << 25) +#define AFE_IRQ24_MISS_FLAG_SFT 24 +#define AFE_IRQ24_MISS_FLAG_MASK 0x1 +#define AFE_IRQ24_MISS_FLAG_MASK_SFT (0x1 << 24) +#define AFE_IRQ23_MISS_FLAG_SFT 23 +#define AFE_IRQ23_MISS_FLAG_MASK 0x1 +#define AFE_IRQ23_MISS_FLAG_MASK_SFT (0x1 << 23) +#define AFE_IRQ22_MISS_FLAG_SFT 22 +#define AFE_IRQ22_MISS_FLAG_MASK 0x1 +#define AFE_IRQ22_MISS_FLAG_MASK_SFT (0x1 << 22) +#define AFE_IRQ21_MISS_FLAG_SFT 21 +#define AFE_IRQ21_MISS_FLAG_MASK 0x1 +#define AFE_IRQ21_MISS_FLAG_MASK_SFT (0x1 << 21) +#define AFE_IRQ20_MISS_FLAG_SFT 20 +#define AFE_IRQ20_MISS_FLAG_MASK 0x1 +#define AFE_IRQ20_MISS_FLAG_MASK_SFT (0x1 << 20) +#define AFE_IRQ19_MISS_FLAG_SFT 19 +#define AFE_IRQ19_MISS_FLAG_MASK 0x1 +#define AFE_IRQ19_MISS_FLAG_MASK_SFT (0x1 << 19) +#define AFE_IRQ18_MISS_FLAG_SFT 18 +#define AFE_IRQ18_MISS_FLAG_MASK 0x1 +#define AFE_IRQ18_MISS_FLAG_MASK_SFT (0x1 << 18) +#define AFE_IRQ17_MISS_FLAG_SFT 17 +#define AFE_IRQ17_MISS_FLAG_MASK 0x1 +#define AFE_IRQ17_MISS_FLAG_MASK_SFT (0x1 << 17) +#define AFE_IRQ16_MISS_FLAG_SFT 16 +#define AFE_IRQ16_MISS_FLAG_MASK 0x1 +#define AFE_IRQ16_MISS_FLAG_MASK_SFT (0x1 << 16) +#define AFE_IRQ15_MISS_FLAG_SFT 15 +#define AFE_IRQ15_MISS_FLAG_MASK 0x1 +#define AFE_IRQ15_MISS_FLAG_MASK_SFT (0x1 << 15) +#define AFE_IRQ14_MISS_FLAG_SFT 14 +#define AFE_IRQ14_MISS_FLAG_MASK 0x1 +#define AFE_IRQ14_MISS_FLAG_MASK_SFT (0x1 << 14) +#define AFE_IRQ13_MISS_FLAG_SFT 13 +#define AFE_IRQ13_MISS_FLAG_MASK 0x1 +#define AFE_IRQ13_MISS_FLAG_MASK_SFT (0x1 << 13) +#define AFE_IRQ12_MISS_FLAG_SFT 12 +#define AFE_IRQ12_MISS_FLAG_MASK 0x1 +#define AFE_IRQ12_MISS_FLAG_MASK_SFT (0x1 << 12) +#define AFE_IRQ11_MISS_FLAG_SFT 11 +#define AFE_IRQ11_MISS_FLAG_MASK 0x1 +#define AFE_IRQ11_MISS_FLAG_MASK_SFT (0x1 << 11) +#define AFE_IRQ10_MISS_FLAG_SFT 10 +#define AFE_IRQ10_MISS_FLAG_MASK 0x1 +#define AFE_IRQ10_MISS_FLAG_MASK_SFT (0x1 << 10) +#define AFE_IRQ9_MISS_FLAG_SFT 9 +#define AFE_IRQ9_MISS_FLAG_MASK 0x1 +#define AFE_IRQ9_MISS_FLAG_MASK_SFT (0x1 << 9) +#define AFE_IRQ8_MISS_FLAG_SFT 8 +#define AFE_IRQ8_MISS_FLAG_MASK 0x1 +#define AFE_IRQ8_MISS_FLAG_MASK_SFT (0x1 << 8) +#define AFE_IRQ7_MISS_FLAG_SFT 7 +#define AFE_IRQ7_MISS_FLAG_MASK 0x1 +#define AFE_IRQ7_MISS_FLAG_MASK_SFT (0x1 << 7) +#define AFE_IRQ6_MISS_FLAG_SFT 6 +#define AFE_IRQ6_MISS_FLAG_MASK 0x1 +#define AFE_IRQ6_MISS_FLAG_MASK_SFT (0x1 << 6) +#define AFE_IRQ5_MISS_FLAG_SFT 5 +#define AFE_IRQ5_MISS_FLAG_MASK 0x1 +#define AFE_IRQ5_MISS_FLAG_MASK_SFT (0x1 << 5) +#define AFE_IRQ4_MISS_FLAG_SFT 4 +#define AFE_IRQ4_MISS_FLAG_MASK 0x1 +#define AFE_IRQ4_MISS_FLAG_MASK_SFT (0x1 << 4) +#define AFE_IRQ3_MISS_FLAG_SFT 3 +#define AFE_IRQ3_MISS_FLAG_MASK 0x1 +#define AFE_IRQ3_MISS_FLAG_MASK_SFT (0x1 << 3) +#define AFE_IRQ2_MISS_FLAG_SFT 2 +#define AFE_IRQ2_MISS_FLAG_MASK 0x1 +#define AFE_IRQ2_MISS_FLAG_MASK_SFT (0x1 << 2) +#define AFE_IRQ1_MISS_FLAG_SFT 1 +#define AFE_IRQ1_MISS_FLAG_MASK 0x1 +#define AFE_IRQ1_MISS_FLAG_MASK_SFT (0x1 << 1) +#define AFE_IRQ0_MISS_FLAG_SFT 0 +#define AFE_IRQ0_MISS_FLAG_MASK 0x1 +#define AFE_IRQ0_MISS_FLAG_MASK_SFT (0x1 << 0) + +/* AFE_IRQ_MCU_MON1 */ +#define AFE_CUSTOM_IRQ21_MISS_FLAG_SFT 21 +#define AFE_CUSTOM_IRQ21_MISS_FLAG_MASK 0x1 +#define AFE_CUSTOM_IRQ21_MISS_FLAG_MASK_SFT (0x1 << 21) +#define AFE_CUSTOM_IRQ20_MISS_FLAG_SFT 20 +#define AFE_CUSTOM_IRQ20_MISS_FLAG_MASK 0x1 +#define AFE_CUSTOM_IRQ20_MISS_FLAG_MASK_SFT (0x1 << 20) +#define AFE_CUSTOM_IRQ19_MISS_FLAG_SFT 19 +#define AFE_CUSTOM_IRQ19_MISS_FLAG_MASK 0x1 +#define AFE_CUSTOM_IRQ19_MISS_FLAG_MASK_SFT (0x1 << 19) +#define AFE_CUSTOM_IRQ18_MISS_FLAG_SFT 18 +#define AFE_CUSTOM_IRQ18_MISS_FLAG_MASK 0x1 +#define AFE_CUSTOM_IRQ18_MISS_FLAG_MASK_SFT (0x1 << 18) +#define AFE_CUSTOM_IRQ17_MISS_FLAG_SFT 17 +#define AFE_CUSTOM_IRQ17_MISS_FLAG_MASK 0x1 +#define AFE_CUSTOM_IRQ17_MISS_FLAG_MASK_SFT (0x1 << 17) +#define AFE_CUSTOM_IRQ16_MISS_FLAG_SFT 16 +#define AFE_CUSTOM_IRQ16_MISS_FLAG_MASK 0x1 +#define AFE_CUSTOM_IRQ16_MISS_FLAG_MASK_SFT (0x1 << 16) +#define AFE_CUSTOM_IRQ9_MISS_FLAG_SFT 9 +#define AFE_CUSTOM_IRQ9_MISS_FLAG_MASK 0x1 +#define AFE_CUSTOM_IRQ9_MISS_FLAG_MASK_SFT (0x1 << 9) +#define AFE_CUSTOM_IRQ8_MISS_FLAG_SFT 8 +#define AFE_CUSTOM_IRQ8_MISS_FLAG_MASK 0x1 +#define AFE_CUSTOM_IRQ8_MISS_FLAG_MASK_SFT (0x1 << 8) +#define AFE_CUSTOM_IRQ7_MISS_FLAG_SFT 7 +#define AFE_CUSTOM_IRQ7_MISS_FLAG_MASK 0x1 +#define AFE_CUSTOM_IRQ7_MISS_FLAG_MASK_SFT (0x1 << 7) +#define AFE_CUSTOM_IRQ6_MISS_FLAG_SFT 6 +#define AFE_CUSTOM_IRQ6_MISS_FLAG_MASK 0x1 +#define AFE_CUSTOM_IRQ6_MISS_FLAG_MASK_SFT (0x1 << 6) +#define AFE_CUSTOM_IRQ5_MISS_FLAG_SFT 5 +#define AFE_CUSTOM_IRQ5_MISS_FLAG_MASK 0x1 +#define AFE_CUSTOM_IRQ5_MISS_FLAG_MASK_SFT (0x1 << 5) +#define AFE_CUSTOM_IRQ4_MISS_FLAG_SFT 4 +#define AFE_CUSTOM_IRQ4_MISS_FLAG_MASK 0x1 +#define AFE_CUSTOM_IRQ4_MISS_FLAG_MASK_SFT (0x1 << 4) +#define AFE_CUSTOM_IRQ3_MISS_FLAG_SFT 3 +#define AFE_CUSTOM_IRQ3_MISS_FLAG_MASK 0x1 +#define AFE_CUSTOM_IRQ3_MISS_FLAG_MASK_SFT (0x1 << 3) +#define AFE_CUSTOM_IRQ2_MISS_FLAG_SFT 2 +#define AFE_CUSTOM_IRQ2_MISS_FLAG_MASK 0x1 +#define AFE_CUSTOM_IRQ2_MISS_FLAG_MASK_SFT (0x1 << 2) +#define AFE_CUSTOM_IRQ1_MISS_FLAG_SFT 1 +#define AFE_CUSTOM_IRQ1_MISS_FLAG_MASK 0x1 +#define AFE_CUSTOM_IRQ1_MISS_FLAG_MASK_SFT (0x1 << 1) +#define AFE_CUSTOM_IRQ0_MISS_FLAG_SFT 0 +#define AFE_CUSTOM_IRQ0_MISS_FLAG_MASK 0x1 +#define AFE_CUSTOM_IRQ0_MISS_FLAG_MASK_SFT (0x1 << 0) + +/* AFE_IRQ_MCU_MON2 */ +#define AFE_IRQ_B_R_CNT_SFT 8 +#define AFE_IRQ_B_R_CNT_MASK 0xff +#define AFE_IRQ_B_R_CNT_MASK_SFT (0xff << 8) +#define AFE_IRQ_B_F_CNT_SFT 0 +#define AFE_IRQ_B_F_CNT_MASK 0xff +#define AFE_IRQ_B_F_CNT_MASK_SFT (0xff << 0) + +/* AFE_IRQ0_CNT_MON */ +#define AFE_IRQ0_CNT_MON_SFT 0 +#define AFE_IRQ0_CNT_MON_MASK 0xffffff +#define AFE_IRQ0_CNT_MON_MASK_SFT (0xffffff << 0) + +/* AFE_IRQ1_CNT_MON */ +#define AFE_IRQ1_CNT_MON_SFT 0 +#define AFE_IRQ1_CNT_MON_MASK 0xffffff +#define AFE_IRQ1_CNT_MON_MASK_SFT (0xffffff << 0) + +/* AFE_IRQ2_CNT_MON */ +#define AFE_IRQ2_CNT_MON_SFT 0 +#define AFE_IRQ2_CNT_MON_MASK 0xffffff +#define AFE_IRQ2_CNT_MON_MASK_SFT (0xffffff << 0) + +/* AFE_IRQ3_CNT_MON */ +#define AFE_IRQ3_CNT_MON_SFT 0 +#define AFE_IRQ3_CNT_MON_MASK 0xffffff +#define AFE_IRQ3_CNT_MON_MASK_SFT (0xffffff << 0) + +/* AFE_IRQ4_CNT_MON */ +#define AFE_IRQ4_CNT_MON_SFT 0 +#define AFE_IRQ4_CNT_MON_MASK 0xffffff +#define AFE_IRQ4_CNT_MON_MASK_SFT (0xffffff << 0) + +/* AFE_IRQ5_CNT_MON */ +#define AFE_IRQ5_CNT_MON_SFT 0 +#define AFE_IRQ5_CNT_MON_MASK 0xffffff +#define AFE_IRQ5_CNT_MON_MASK_SFT (0xffffff << 0) + +/* AFE_IRQ6_CNT_MON */ +#define AFE_IRQ6_CNT_MON_SFT 0 +#define AFE_IRQ6_CNT_MON_MASK 0xffffff +#define AFE_IRQ6_CNT_MON_MASK_SFT (0xffffff << 0) + +/* AFE_IRQ7_CNT_MON */ +#define AFE_IRQ7_CNT_MON_SFT 0 +#define AFE_IRQ7_CNT_MON_MASK 0xffffff +#define AFE_IRQ7_CNT_MON_MASK_SFT (0xffffff << 0) + +/* AFE_IRQ8_CNT_MON */ +#define AFE_IRQ8_CNT_MON_SFT 0 +#define AFE_IRQ8_CNT_MON_MASK 0xffffff +#define AFE_IRQ8_CNT_MON_MASK_SFT (0xffffff << 0) + +/* AFE_IRQ9_CNT_MON */ +#define AFE_IRQ9_CNT_MON_SFT 0 +#define AFE_IRQ9_CNT_MON_MASK 0xffffff +#define AFE_IRQ9_CNT_MON_MASK_SFT (0xffffff << 0) + +/* AFE_IRQ10_CNT_MON */ +#define AFE_IRQ10_CNT_MON_SFT 0 +#define AFE_IRQ10_CNT_MON_MASK 0xffffff +#define AFE_IRQ10_CNT_MON_MASK_SFT (0xffffff << 0) + +/* AFE_IRQ11_CNT_MON */ +#define AFE_IRQ11_CNT_MON_SFT 0 +#define AFE_IRQ11_CNT_MON_MASK 0xffffff +#define AFE_IRQ11_CNT_MON_MASK_SFT (0xffffff << 0) + +/* AFE_IRQ12_CNT_MON */ +#define AFE_IRQ12_CNT_MON_SFT 0 +#define AFE_IRQ12_CNT_MON_MASK 0xffffff +#define AFE_IRQ12_CNT_MON_MASK_SFT (0xffffff << 0) + +/* AFE_IRQ13_CNT_MON */ +#define AFE_IRQ13_CNT_MON_SFT 0 +#define AFE_IRQ13_CNT_MON_MASK 0xffffff +#define AFE_IRQ13_CNT_MON_MASK_SFT (0xffffff << 0) + +/* AFE_IRQ14_CNT_MON */ +#define AFE_IRQ14_CNT_MON_SFT 0 +#define AFE_IRQ14_CNT_MON_MASK 0xffffff +#define AFE_IRQ14_CNT_MON_MASK_SFT (0xffffff << 0) + +/* AFE_IRQ15_CNT_MON */ +#define AFE_IRQ15_CNT_MON_SFT 0 +#define AFE_IRQ15_CNT_MON_MASK 0xffffff +#define AFE_IRQ15_CNT_MON_MASK_SFT (0xffffff << 0) + +/* AFE_IRQ16_CNT_MON */ +#define AFE_IRQ16_CNT_MON_SFT 0 +#define AFE_IRQ16_CNT_MON_MASK 0xffffff +#define AFE_IRQ16_CNT_MON_MASK_SFT (0xffffff << 0) + +/* AFE_IRQ17_CNT_MON */ +#define AFE_IRQ17_CNT_MON_SFT 0 +#define AFE_IRQ17_CNT_MON_MASK 0xffffff +#define AFE_IRQ17_CNT_MON_MASK_SFT (0xffffff << 0) + +/* AFE_IRQ18_CNT_MON */ +#define AFE_IRQ18_CNT_MON_SFT 0 +#define AFE_IRQ18_CNT_MON_MASK 0xffffff +#define AFE_IRQ18_CNT_MON_MASK_SFT (0xffffff << 0) + +/* AFE_IRQ19_CNT_MON */ +#define AFE_IRQ19_CNT_MON_SFT 0 +#define AFE_IRQ19_CNT_MON_MASK 0xffffff +#define AFE_IRQ19_CNT_MON_MASK_SFT (0xffffff << 0) + +/* AFE_IRQ20_CNT_MON */ +#define AFE_IRQ20_CNT_MON_SFT 0 +#define AFE_IRQ20_CNT_MON_MASK 0xffffff +#define AFE_IRQ20_CNT_MON_MASK_SFT (0xffffff << 0) + +/* AFE_IRQ21_CNT_MON */ +#define AFE_IRQ21_CNT_MON_SFT 0 +#define AFE_IRQ21_CNT_MON_MASK 0xffffff +#define AFE_IRQ21_CNT_MON_MASK_SFT (0xffffff << 0) + +/* AFE_IRQ22_CNT_MON */ +#define AFE_IRQ22_CNT_MON_SFT 0 +#define AFE_IRQ22_CNT_MON_MASK 0xffffff +#define AFE_IRQ22_CNT_MON_MASK_SFT (0xffffff << 0) + +/* AFE_IRQ23_CNT_MON */ +#define AFE_IRQ23_CNT_MON_SFT 0 +#define AFE_IRQ23_CNT_MON_MASK 0xffffff +#define AFE_IRQ23_CNT_MON_MASK_SFT (0xffffff << 0) + +/* AFE_IRQ24_CNT_MON */ +#define AFE_IRQ24_CNT_MON_SFT 0 +#define AFE_IRQ24_CNT_MON_MASK 0xffffff +#define AFE_IRQ24_CNT_MON_MASK_SFT (0xffffff << 0) + +/* AFE_IRQ25_CNT_MON */ +#define AFE_IRQ25_CNT_MON_SFT 0 +#define AFE_IRQ25_CNT_MON_MASK 0xffffff +#define AFE_IRQ25_CNT_MON_MASK_SFT (0xffffff << 0) + +/* AFE_IRQ26_CNT_MON */ +#define AFE_IRQ26_CNT_MON_SFT 0 +#define AFE_IRQ26_CNT_MON_MASK 0xffffff +#define AFE_IRQ26_CNT_MON_MASK_SFT (0xffffff << 0) + +/* AFE_CUSTOM_IRQ0_CNT_MON */ +#define AFE_CUSTOM_IRQ0_CNT_MON_SFT 0 +#define AFE_CUSTOM_IRQ0_CNT_MON_MASK 0xffffff +#define AFE_CUSTOM_IRQ0_CNT_MON_MASK_SFT (0xffffff << 0) + +/* AFE_CUSTOM_IRQ0_MCU_CFG1 */ +#define AFE_CUSTOM_IRQ0_CLR_CFG_SFT 31 +#define AFE_CUSTOM_IRQ0_CLR_CFG_MASK 0x1 +#define AFE_CUSTOM_IRQ0_CLR_CFG_MASK_SFT (0x1 << 31) +#define AFE_CUSTOM_IRQ0_MISS_FLAG_CLR_CFG_SFT 30 +#define AFE_CUSTOM_IRQ0_MISS_FLAG_CLR_CFG_MASK 0x1 +#define AFE_CUSTOM_IRQ0_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30) +#define AFE_CUSTOM_IRQ0_MCU_CNT_SFT 0 +#define AFE_CUSTOM_IRQ0_MCU_CNT_MASK 0xffffff +#define AFE_CUSTOM_IRQ0_MCU_CNT_MASK_SFT (0xffffff << 0) + +/* AFE_GAIN0_CON1_R */ +/* AFE_GAIN1_CON1_R */ +/* AFE_GAIN2_CON1_R */ +/* AFE_GAIN3_CON1_R */ +#define GAIN_TARGET_R_SFT 0 +#define GAIN_TARGET_R_MASK 0xffffffff +#define GAIN_TARGET_R_MASK_SFT (0xffffffff << 0) + +/* AFE_GAIN0_CON1_L */ +/* AFE_GAIN1_CON1_L */ +/* AFE_GAIN2_CON1_L */ +/* AFE_GAIN3_CON1_L */ +#define GAIN_TARGET_L_SFT 0 +#define GAIN_TARGET_L_MASK 0xffffffff +#define GAIN_TARGET_L_MASK_SFT (0xffffffff << 0) + +/* AFE_GAIN0_CON2 */ +#define GAIN0_DOWN_STEP_SFT 0 +#define GAIN0_DOWN_STEP_MASK 0x3fffff +#define GAIN0_DOWN_STEP_MASK_SFT (0x3fffff << 0) + +/* AFE_GAIN0_CON3 */ +#define GAIN0_UP_STEP_SFT 0 +#define GAIN0_UP_STEP_MASK 0x3fffff +#define GAIN0_UP_STEP_MASK_SFT (0x3fffff << 0) + +/* AFE_GAIN0_CUR_R */ +/* AFE_GAIN1_CUR_R */ +/* AFE_GAIN2_CUR_R */ +/* AFE_GAIN3_CUR_R */ +#define AFE_GAIN_CUR_R_SFT 0 +#define AFE_GAIN_CUR_R_MASK 0xffffffff +#define AFE_GAIN_CUR_R_MASK_SFT (0xffffffff << 0) + +/* AFE_GAIN0_CUR_L */ +/* AFE_GAIN1_CUR_L */ +/* AFE_GAIN2_CUR_L */ +/* AFE_GAIN3_CUR_L */ +#define AFE_GAIN_CUR_L_SFT 0 +#define AFE_GAIN_CUR_L_MASK 0xffffffff +#define AFE_GAIN_CUR_L_MASK_SFT (0xffffffff << 0) + +/* AFE_GAIN0_CON0 */ +/* AFE_GAIN1_CON0 */ +/* AFE_GAIN2_CON0 */ +/* AFE_GAIN3_CON0 */ +#define GAIN_TARGET_SYNC_ON_SFT 24 +#define GAIN_TARGET_SYNC_ON_MASK 0x1 +#define GAIN_TARGET_SYNC_ON_MASK_SFT (0x1 << 24) +#define GAIN_TIMEOUT_SFT 18 +#define GAIN_TIMEOUT_MASK 0x3f +#define GAIN_TIMEOUT_MASK_SFT (0x3f << 18) +#define GAIN_TRIG_SFT 17 +#define GAIN_TRIG_MASK 0x1 +#define GAIN_TRIG_MASK_SFT (0x1 << 17) +#define GAIN_ON_SFT 16 +#define GAIN_ON_MASK 0x1 +#define GAIN_ON_MASK_SFT (0x1 << 16) +#define GAIN_SAMPLE_PER_STEP_SFT 8 +#define GAIN_SAMPLE_PER_STEP_MASK 0xff +#define GAIN_SAMPLE_PER_STEP_MASK_SFT (0xff << 8) +#define GAIN_SEL_DOMAIN_SFT 5 +#define GAIN_SEL_DOMAIN_MASK 0x7 +#define GAIN_SEL_DOMAIN_MASK_SFT (0x7 << 5) +#define GAIN_SEL_FS_SFT 0 +#define GAIN_SEL_FS_MASK 0x1f +#define GAIN_SEL_FS_MASK_SFT (0x1f << 0) + +/* AFE_GAIN1_CON2 */ +#define GAIN1_DOWN_STEP_SFT 0 +#define GAIN1_DOWN_STEP_MASK 0x3fffff +#define GAIN1_DOWN_STEP_MASK_SFT (0x3fffff << 0) + +/* AFE_GAIN1_CON3 */ +#define GAIN1_UP_STEP_SFT 0 +#define GAIN1_UP_STEP_MASK 0x3fffff +#define GAIN1_UP_STEP_MASK_SFT (0x3fffff << 0) + +/* AFE_GAIN2_CON2 */ +#define GAIN2_DOWN_STEP_SFT 0 +#define GAIN2_DOWN_STEP_MASK 0x3fffff +#define GAIN2_DOWN_STEP_MASK_SFT (0x3fffff << 0) + +/* AFE_GAIN2_CON3 */ +#define GAIN2_UP_STEP_SFT 0 +#define GAIN2_UP_STEP_MASK 0x3fffff +#define GAIN2_UP_STEP_MASK_SFT (0x3fffff << 0) + +/* AFE_GAIN3_CON2 */ +#define GAIN3_DOWN_STEP_SFT 0 +#define GAIN3_DOWN_STEP_MASK 0x3fffff +#define GAIN3_DOWN_STEP_MASK_SFT (0x3fffff << 0) + +/* AFE_GAIN3_CON3 */ +#define GAIN3_UP_STEP_SFT 0 +#define GAIN3_UP_STEP_MASK 0x3fffff +#define GAIN3_UP_STEP_MASK_SFT (0x3fffff << 0) + +/* AFE_STF_CON0 */ +#define SLT_CNT_FLAG_RESET_SFT 28 +#define SLT_CNT_FLAG_RESET_MASK 0x1 +#define SLT_CNT_FLAG_RESET_MASK_SFT (0x1 << 28) +#define SLT_CNT_THD_SFT 16 +#define SLT_CNT_THD_MASK 0xfff +#define SLT_CNT_THD_MASK_SFT (0xfff << 16) +#define SIDE_TONE_HALF_TAP_NUM_SFT 4 +#define SIDE_TONE_HALF_TAP_NUM_MASK 0x7f +#define SIDE_TONE_HALF_TAP_NUM_MASK_SFT (0x7f << 4) +#define SIDE_TONE_ODD_MODE_SFT 1 +#define SIDE_TONE_ODD_MODE_MASK 0x1 +#define SIDE_TONE_ODD_MODE_MASK_SFT (0x1 << 1) +#define SIDE_TONE_ON_SFT 0 +#define SIDE_TONE_ON_MASK 0x1 +#define SIDE_TONE_ON_MASK_SFT (0x1 << 0) + +/* AFE_STF_CON1 */ +#define SIDE_TONE_IN_EN_SEL_DOMAIN_SFT 5 +#define SIDE_TONE_IN_EN_SEL_DOMAIN_MASK 0x7 +#define SIDE_TONE_IN_EN_SEL_DOMAIN_MASK_SFT (0x7 << 5) +#define SIDE_TONE_IN_EN_SEL_FS_SFT 0 +#define SIDE_TONE_IN_EN_SEL_FS_MASK 0x1f +#define SIDE_TONE_IN_EN_SEL_FS_MASK_SFT (0x1f << 0) + +/* AFE_STF_COEFF */ +#define SIDE_TONE_COEFFICIENT_R_W_SEL_SFT 24 +#define SIDE_TONE_COEFFICIENT_R_W_SEL_MASK 0x1 +#define SIDE_TONE_COEFFICIENT_R_W_SEL_MASK_SFT (0x1 << 24) +#define SIDE_TONE_COEFFICIENT_ADDR_SFT 16 +#define SIDE_TONE_COEFFICIENT_ADDR_MASK 0x1f +#define SIDE_TONE_COEFFICIENT_ADDR_MASK_SFT (0x1f << 16) +#define SIDE_TONE_COEFFICIENT_SFT 0 +#define SIDE_TONE_COEFFICIENT_MASK 0xffff +#define SIDE_TONE_COEFFICIENT_MASK_SFT (0xffff << 0) + +/* AFE_STF_GAIN */ +#define SIDE_TONE_POSITIVE_GAIN_SFT 16 +#define SIDE_TONE_POSITIVE_GAIN_MASK 0x7 +#define SIDE_TONE_POSITIVE_GAIN_MASK_SFT (0x7 << 16) +#define SIDE_TONE_GAIN_SFT 0 +#define SIDE_TONE_GAIN_MASK 0xffff +#define SIDE_TONE_GAIN_MASK_SFT (0xffff << 0) + +/* AFE_STF_MON */ +#define SIDE_TONE_R_RDY_SFT 30 +#define SIDE_TONE_R_RDY_MASK 0x1 +#define SIDE_TONE_R_RDY_MASK_SFT (0x1 << 30) +#define SIDE_TONE_W_RDY_SFT 29 +#define SIDE_TONE_W_RDY_MASK 0x1 +#define SIDE_TONE_W_RDY_MASK_SFT (0x1 << 29) +#define SLT_CNT_FLAG_SFT 28 +#define SLT_CNT_FLAG_MASK 0x1 +#define SLT_CNT_FLAG_MASK_SFT (0x1 << 28) +#define SLT_CNT_SFT 16 +#define SLT_CNT_MASK 0xfff +#define SLT_CNT_MASK_SFT (0xfff << 16) +#define SIDE_TONE_COEFF_SFT 0 +#define SIDE_TONE_COEFF_MASK 0xffff +#define SIDE_TONE_COEFF_MASK_SFT (0xffff << 0) + +/* AFE_STF_IP_VERSION */ +#define SIDE_TONE_IP_VERSION_SFT 0 +#define SIDE_TONE_IP_VERSION_MASK 0xffffffff +#define SIDE_TONE_IP_VERSION_MASK_SFT (0xffffffff << 0) + +/* AFE_CM_REG */ +#define AFE_CM_UPDATE_CNT_SFT 16 +#define AFE_CM_UPDATE_CNT_MASK 0x7fff +#define AFE_CM_UPDATE_CNT_MASK_SFT (0x7fff << 16) +#define AFE_CM_1X_EN_SEL_FS_SFT 8 +#define AFE_CM_1X_EN_SEL_FS_MASK 0x1f +#define AFE_CM_1X_EN_SEL_FS_MASK_SFT (0x1f << 8) +#define AFE_CM_CH_NUM_SFT 2 +#define AFE_CM_CH_NUM_MASK 0x1f +#define AFE_CM_CH_NUM_MASK_SFT (0x1f << 2) +#define AFE_CM_BYTE_SWAP_SFT 1 +#define AFE_CM_BYTE_SWAP_MASK 0x1 +#define AFE_CM_BYTE_SWAP_MASK_SFT (0x1 << 1) +#define AFE_CM_BYPASS_MODE_SFT 31 +#define AFE_CM_BYPASS_MODE_MASK 0x1 +#define AFE_CM_BYPASS_MODE_MASK_SFT (0x1 << 31) + +/* AFE_CM0_CON0 */ +#define AFE_CM0_BYPASS_MODE_SFT 31 +#define AFE_CM0_BYPASS_MODE_MASK 0x1 +#define AFE_CM0_BYPASS_MODE_MASK_SFT (0x1 << 31) +#define AFE_CM0_UPDATE_CNT_SFT 16 +#define AFE_CM0_UPDATE_CNT_MASK 0x7fff +#define AFE_CM0_UPDATE_CNT_MASK_SFT (0x7fff << 16) +#define AFE_CM0_1X_EN_SEL_DOMAIN_SFT 13 +#define AFE_CM0_1X_EN_SEL_DOMAIN_MASK 0x7 +#define AFE_CM0_1X_EN_SEL_DOMAIN_MASK_SFT (0x7 << 13) +#define AFE_CM0_1X_EN_SEL_FS_SFT 8 +#define AFE_CM0_1X_EN_SEL_FS_MASK 0x1f +#define AFE_CM0_1X_EN_SEL_FS_MASK_SFT (0x1f << 8) +#define AFE_CM0_OUTPUT_MUX_SFT 7 +#define AFE_CM0_OUTPUT_MUX_MASK 0x1 +#define AFE_CM0_OUTPUT_MUX_MASK_SFT (0x1 << 7) +#define AFE_CM0_CH_NUM_SFT 2 +#define AFE_CM0_CH_NUM_MASK 0x1f +#define AFE_CM0_CH_NUM_MASK_SFT (0x1f << 2) +#define AFE_CM0_BYTE_SWAP_SFT 1 +#define AFE_CM0_BYTE_SWAP_MASK 0x1 +#define AFE_CM0_BYTE_SWAP_MASK_SFT (0x1 << 1) +#define AFE_CM0_ON_SFT 0 +#define AFE_CM0_ON_MASK 0x1 +#define AFE_CM0_ON_MASK_SFT (0x1 << 0) + +/* AFE_CM0_MON */ +#define AFE_CM0_BYPASS_MODE_MON_SFT 31 +#define AFE_CM0_BYPASS_MODE_MON_MASK 0x1 +#define AFE_CM0_BYPASS_MODE_MON_MASK_SFT (0x1 << 31) +#define AFE_CM0_OUTPUT_CNT_MON_SFT 16 +#define AFE_CM0_OUTPUT_CNT_MON_MASK 0x7fff +#define AFE_CM0_OUTPUT_CNT_MON_MASK_SFT (0x7fff << 16) +#define AFE_CM0_CUR_CHSET_MON_SFT 5 +#define AFE_CM0_CUR_CHSET_MON_MASK 0xf +#define AFE_CM0_CUR_CHSET_MON_MASK_SFT (0xf << 5) +#define AFE_CM0_ODD_FLAG_MON_SFT 4 +#define AFE_CM0_ODD_FLAG_MON_MASK 0x1 +#define AFE_CM0_ODD_FLAG_MON_MASK_SFT (0x1 << 4) +#define AFE_CM0_BYTE_SWAP_MON_SFT 1 +#define AFE_CM0_BYTE_SWAP_MON_MASK 0x1 +#define AFE_CM0_BYTE_SWAP_MON_MASK_SFT (0x1 << 1) +#define AFE_CM0_ON_MON_SFT 0 +#define AFE_CM0_ON_MON_MASK 0x1 +#define AFE_CM0_ON_MON_MASK_SFT (0x1 << 0) + +/* AFE_CM0_IP_VERSION */ +#define AFE_CM0_IP_VERSION_SFT 0 +#define AFE_CM0_IP_VERSION_MASK 0xffffffff +#define AFE_CM0_IP_VERSION_MASK_SFT (0xffffffff << 0) + +/* AFE_CM1_CON0 */ +#define AFE_CM1_BYPASS_MODE_SFT 31 +#define AFE_CM1_BYPASS_MODE_MASK 0x1 +#define AFE_CM1_BYPASS_MODE_MASK_SFT (0x1 << 31) +#define AFE_CM1_UPDATE_CNT_SFT 16 +#define AFE_CM1_UPDATE_CNT_MASK 0x7fff +#define AFE_CM1_UPDATE_CNT_MASK_SFT (0x7fff << 16) +#define AFE_CM1_1X_EN_SEL_DOMAIN_SFT 13 +#define AFE_CM1_1X_EN_SEL_DOMAIN_MASK 0x7 +#define AFE_CM1_1X_EN_SEL_DOMAIN_MASK_SFT (0x7 << 13) +#define AFE_CM1_1X_EN_SEL_FS_SFT 8 +#define AFE_CM1_1X_EN_SEL_FS_MASK 0x1f +#define AFE_CM1_1X_EN_SEL_FS_MASK_SFT (0x1f << 8) +#define AFE_CM1_OUTPUT_MUX_SFT 7 +#define AFE_CM1_OUTPUT_MUX_MASK 0x1 +#define AFE_CM1_OUTPUT_MUX_MASK_SFT (0x1 << 7) +#define AFE_CM1_CH_NUM_SFT 2 +#define AFE_CM1_CH_NUM_MASK 0x1f +#define AFE_CM1_CH_NUM_MASK_SFT (0x1f << 2) +#define AFE_CM1_BYTE_SWAP_SFT 1 +#define AFE_CM1_BYTE_SWAP_MASK 0x1 +#define AFE_CM1_BYTE_SWAP_MASK_SFT (0x1 << 1) +#define AFE_CM1_ON_SFT 0 +#define AFE_CM1_ON_MASK 0x1 +#define AFE_CM1_ON_MASK_SFT (0x1 << 0) + +/* AFE_CM1_MON */ +#define AFE_CM1_BYPASS_MODE_MON_SFT 31 +#define AFE_CM1_BYPASS_MODE_MON_MASK 0x1 +#define AFE_CM1_BYPASS_MODE_MON_MASK_SFT (0x1 << 31) +#define AFE_CM1_OUTPUT_CNT_MON_SFT 16 +#define AFE_CM1_OUTPUT_CNT_MON_MASK 0x7fff +#define AFE_CM1_OUTPUT_CNT_MON_MASK_SFT (0x7fff << 16) +#define AFE_CM1_CUR_CHSET_MON_SFT 5 +#define AFE_CM1_CUR_CHSET_MON_MASK 0xf +#define AFE_CM1_CUR_CHSET_MON_MASK_SFT (0xf << 5) +#define AFE_CM1_ODD_FLAG_MON_SFT 4 +#define AFE_CM1_ODD_FLAG_MON_MASK 0x1 +#define AFE_CM1_ODD_FLAG_MON_MASK_SFT (0x1 << 4) +#define AFE_CM1_BYTE_SWAP_MON_SFT 1 +#define AFE_CM1_BYTE_SWAP_MON_MASK 0x1 +#define AFE_CM1_BYTE_SWAP_MON_MASK_SFT (0x1 << 1) +#define AFE_CM1_ON_MON_SFT 0 +#define AFE_CM1_ON_MON_MASK 0x1 +#define AFE_CM1_ON_MON_MASK_SFT (0x1 << 0) + +/* AFE_CM1_IP_VERSION */ +#define AFE_CM1_IP_VERSION_SFT 0 +#define AFE_CM1_IP_VERSION_MASK 0xffffffff +#define AFE_CM1_IP_VERSION_MASK_SFT (0xffffffff << 0) + +/* AFE_CM2_CON0 */ +#define AFE_CM2_BYPASS_MODE_SFT 31 +#define AFE_CM2_BYPASS_MODE_MASK 0x1 +#define AFE_CM2_BYPASS_MODE_MASK_SFT (0x1 << 31) +#define AFE_CM2_UPDATE_CNT_SFT 16 +#define AFE_CM2_UPDATE_CNT_MASK 0x7fff +#define AFE_CM2_UPDATE_CNT_MASK_SFT (0x7fff << 16) +#define AFE_CM2_1X_EN_SEL_DOMAIN_SFT 13 +#define AFE_CM2_1X_EN_SEL_DOMAIN_MASK 0x7 +#define AFE_CM2_1X_EN_SEL_DOMAIN_MASK_SFT (0x7 << 13) +#define AFE_CM2_1X_EN_SEL_FS_SFT 8 +#define AFE_CM2_1X_EN_SEL_FS_MASK 0x1f +#define AFE_CM2_1X_EN_SEL_FS_MASK_SFT (0x1f << 8) +#define AFE_CM2_OUTPUT_MUX_SFT 7 +#define AFE_CM2_OUTPUT_MUX_MASK 0x1 +#define AFE_CM2_OUTPUT_MUX_MASK_SFT (0x1 << 7) +#define AFE_CM2_CH_NUM_SFT 2 +#define AFE_CM2_CH_NUM_MASK 0x1f +#define AFE_CM2_CH_NUM_MASK_SFT (0x1f << 2) +#define AFE_CM2_BYTE_SWAP_SFT 1 +#define AFE_CM2_BYTE_SWAP_MASK 0x1 +#define AFE_CM2_BYTE_SWAP_MASK_SFT (0x1 << 1) +#define AFE_CM2_ON_SFT 0 +#define AFE_CM2_ON_MASK 0x1 +#define AFE_CM2_ON_MASK_SFT (0x1 << 0) + +/* AFE_CM2_MON */ +#define AFE_CM2_BYPASS_MODE_MON_SFT 31 +#define AFE_CM2_BYPASS_MODE_MON_MASK 0x1 +#define AFE_CM2_BYPASS_MODE_MON_MASK_SFT (0x1 << 31) +#define AFE_CM2_OUTPUT_CNT_MON_SFT 16 +#define AFE_CM2_OUTPUT_CNT_MON_MASK 0x7fff +#define AFE_CM2_OUTPUT_CNT_MON_MASK_SFT (0x7fff << 16) +#define AFE_CM2_CUR_CHSET_MON_SFT 5 +#define AFE_CM2_CUR_CHSET_MON_MASK 0xf +#define AFE_CM2_CUR_CHSET_MON_MASK_SFT (0xf << 5) +#define AFE_CM2_ODD_FLAG_MON_SFT 4 +#define AFE_CM2_ODD_FLAG_MON_MASK 0x1 +#define AFE_CM2_ODD_FLAG_MON_MASK_SFT (0x1 << 4) +#define AFE_CM2_BYTE_SWAP_MON_SFT 1 +#define AFE_CM2_BYTE_SWAP_MON_MASK 0x1 +#define AFE_CM2_BYTE_SWAP_MON_MASK_SFT (0x1 << 1) +#define AFE_CM2_ON_MON_SFT 0 +#define AFE_CM2_ON_MON_MASK 0x1 +#define AFE_CM2_ON_MON_MASK_SFT (0x1 << 0) + +/* AFE_CM2_IP_VERSION */ +#define AFE_CM2_IP_VERSION_SFT 0 +#define AFE_CM2_IP_VERSION_MASK 0xffffffff +#define AFE_CM2_IP_VERSION_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL0_SRC_CON0 */ +#define ULCF_CFG_EN_CTL_SFT 31 +#define ULCF_CFG_EN_CTL_MASK 0x1 +#define ULCF_CFG_EN_CTL_MASK_SFT (0x1 << 31) +#define UL_DMIC_PHASE_SEL_CH1_SFT 27 +#define UL_DMIC_PHASE_SEL_CH1_MASK 0x7 +#define UL_DMIC_PHASE_SEL_CH1_MASK_SFT (0x7 << 27) +#define UL_DMIC_PHASE_SEL_CH2_SFT 24 +#define UL_DMIC_PHASE_SEL_CH2_MASK 0x7 +#define UL_DMIC_PHASE_SEL_CH2_MASK_SFT (0x7 << 24) +#define UL_DMIC_TWO_WIRE_CTL_SFT 23 +#define UL_DMIC_TWO_WIRE_CTL_MASK 0x1 +#define UL_DMIC_TWO_WIRE_CTL_MASK_SFT (0x1 << 23) +#define UL_MODE_3P25M_CH2_CTL_SFT 22 +#define UL_MODE_3P25M_CH2_CTL_MASK 0x1 +#define UL_MODE_3P25M_CH2_CTL_MASK_SFT (0x1 << 22) +#define UL_MODE_3P25M_CH1_CTL_SFT 21 +#define UL_MODE_3P25M_CH1_CTL_MASK 0x1 +#define UL_MODE_3P25M_CH1_CTL_MASK_SFT (0x1 << 21) +#define UL_VOICE_MODE_CH1_CH2_CTL_SFT 17 +#define UL_VOICE_MODE_CH1_CH2_CTL_MASK 0x7 +#define UL_VOICE_MODE_CH1_CH2_CTL_MASK_SFT (0x7 << 17) +#define UL_AP_DMIC_ON_SFT 16 +#define UL_AP_DMIC_ON_MASK 0x1 +#define UL_AP_DMIC_ON_MASK_SFT (0x1 << 16) +#define DMIC_LOW_POWER_MODE_CTL_SFT 14 +#define DMIC_LOW_POWER_MODE_CTL_MASK 0x3 +#define DMIC_LOW_POWER_MODE_CTL_MASK_SFT (0x3 << 14) +#define UL_DISABLE_HW_CG_CTL_SFT 12 +#define UL_DISABLE_HW_CG_CTL_MASK 0x1 +#define UL_DISABLE_HW_CG_CTL_MASK_SFT (0x1 << 12) +#define AMIC_26M_SEL_CTL_SFT 11 +#define AMIC_26M_SEL_CTL_MASK 0x1 +#define AMIC_26M_SEL_CTL_MASK_SFT (0x1 << 11) +#define UL_IIR_ON_TMP_CTL_SFT 10 +#define UL_IIR_ON_TMP_CTL_MASK 0x1 +#define UL_IIR_ON_TMP_CTL_MASK_SFT (0x1 << 10) +#define UL_IIRMODE_CTL_SFT 7 +#define UL_IIRMODE_CTL_MASK 0x7 +#define UL_IIRMODE_CTL_MASK_SFT (0x7 << 7) +#define DIGMIC_4P33M_SEL_SFT 6 +#define DIGMIC_4P33M_SEL_MASK 0x1 +#define DIGMIC_4P33M_SEL_MASK_SFT (0x1 << 6) +#define DIGMIC_3P25M_1P625M_SEL_CTL_SFT 5 +#define DIGMIC_3P25M_1P625M_SEL_CTL_MASK 0x1 +#define DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT (0x1 << 5) +#define AMIC_6P5M_SEL_CTL_SFT 4 +#define AMIC_6P5M_SEL_CTL_MASK 0x1 +#define AMIC_6P5M_SEL_CTL_MASK_SFT (0x1 << 4) +#define AMIC_1P625M_SEL_CTL_SFT 3 +#define AMIC_1P625M_SEL_CTL_MASK 0x1 +#define AMIC_1P625M_SEL_CTL_MASK_SFT (0x1 << 3) +#define UL_LOOP_BACK_MODE_CTL_SFT 2 +#define UL_LOOP_BACK_MODE_CTL_MASK 0x1 +#define UL_LOOP_BACK_MODE_CTL_MASK_SFT (0x1 << 2) +#define UL_SDM_3_LEVEL_CTL_SFT 1 +#define UL_SDM_3_LEVEL_CTL_MASK 0x1 +#define UL_SDM_3_LEVEL_CTL_MASK_SFT (0x1 << 1) +#define UL_SRC_ON_TMP_CTL_SFT 0 +#define UL_SRC_ON_TMP_CTL_MASK 0x1 +#define UL_SRC_ON_TMP_CTL_MASK_SFT (0x1 << 0) + +/* AFE_ADDA_UL0_SRC_CON1 */ +#define ADDA_UL_GAIN_VALUE_SFT 16 +#define ADDA_UL_GAIN_VALUE_MASK 0xffff +#define ADDA_UL_GAIN_VALUE_MASK_SFT (0xffff << 16) +#define ADDA_UL_POSTIVEGAIN_SFT 12 +#define ADDA_UL_POSTIVEGAIN_MASK 0x7 +#define ADDA_UL_POSTIVEGAIN_MASK_SFT (0x7 << 12) +#define ADDA_UL_ODDTAP_MODE_SFT 11 +#define ADDA_UL_ODDTAP_MODE_MASK 0x1 +#define ADDA_UL_ODDTAP_MODE_MASK_SFT (0x1 << 11) +#define ADDA_UL_HALF_TAP_NUM_SFT 5 +#define ADDA_UL_HALF_TAP_NUM_MASK 0x3f +#define ADDA_UL_HALF_TAP_NUM_MASK_SFT (0x3f << 5) +#define FIFO_SOFT_RST_SFT 4 +#define FIFO_SOFT_RST_MASK 0x1 +#define FIFO_SOFT_RST_MASK_SFT (0x1 << 4) +#define FIFO_SOFT_RST_EN_SFT 3 +#define FIFO_SOFT_RST_EN_MASK 0x1 +#define FIFO_SOFT_RST_EN_MASK_SFT (0x1 << 3) +#define LR_SWAP_SFT 2 +#define LR_SWAP_MASK 0x1 +#define LR_SWAP_MASK_SFT (0x1 << 2) +#define GAIN_MODE_SFT 0 +#define GAIN_MODE_MASK 0x3 +#define GAIN_MODE_MASK_SFT (0x3 << 0) + +/* AFE_ADDA_UL0_SRC_CON2 */ +#define C_DAC_EN_CTL_SFT 27 +#define C_DAC_EN_CTL_MASK 0x1 +#define C_DAC_EN_CTL_MASK_SFT (0x1 << 27) +#define C_MUTE_SW_CTL_SFT 26 +#define C_MUTE_SW_CTL_MASK 0x1 +#define C_MUTE_SW_CTL_MASK_SFT (0x1 << 26) +#define C_AMP_DIV_CH2_CTL_SFT 21 +#define C_AMP_DIV_CH2_CTL_MASK 0x7 +#define C_AMP_DIV_CH2_CTL_MASK_SFT (0x7 << 21) +#define C_FREQ_DIV_CH2_CTL_SFT 16 +#define C_FREQ_DIV_CH2_CTL_MASK 0x1f +#define C_FREQ_DIV_CH2_CTL_MASK_SFT (0x1f << 16) +#define C_SINE_MODE_CH2_CTL_SFT 12 +#define C_SINE_MODE_CH2_CTL_MASK 0xf +#define C_SINE_MODE_CH2_CTL_MASK_SFT (0xf << 12) +#define C_AMP_DIV_CH1_CTL_SFT 9 +#define C_AMP_DIV_CH1_CTL_MASK 0x7 +#define C_AMP_DIV_CH1_CTL_MASK_SFT (0x7 << 9) +#define C_FREQ_DIV_CH1_CTL_SFT 4 +#define C_FREQ_DIV_CH1_CTL_MASK 0x1f +#define C_FREQ_DIV_CH1_CTL_MASK_SFT (0x1f << 4) +#define C_SINE_MODE_CH1_CTL_SFT 0 +#define C_SINE_MODE_CH1_CTL_MASK 0xf +#define C_SINE_MODE_CH1_CTL_MASK_SFT (0xf << 0) + +/* AFE_ADDA_UL0_SRC_DEBUG */ +#define UL_SLT_CNT_FLAG_RESET_CTL_SFT 16 +#define UL_SLT_CNT_FLAG_RESET_CTL_MASK 0x1 +#define UL_SLT_CNT_FLAG_RESET_CTL_MASK_SFT (0x1 << 16) +#define FIFO_DIGMIC_TESTIN_SFT 12 +#define FIFO_DIGMIC_TESTIN_MASK 0x3 +#define FIFO_DIGMIC_TESTIN_MASK_SFT (0x3 << 12) +#define FIFO_DIGMIC_WDATA_TESTEN_SFT 11 +#define FIFO_DIGMIC_WDATA_TESTEN_MASK 0x1 +#define FIFO_DIGMIC_WDATA_TESTEN_MASK_SFT (0x1 << 11) +#define SLT_CNT_THD_CTL_SFT 0 +#define SLT_CNT_THD_CTL_MASK 0x7ff +#define SLT_CNT_THD_CTL_MASK_SFT (0x7ff << 0) + +/* AFE_ADDA_UL0_SRC_DEBUG_MON0 */ +#define SLT_CNT_FLAG_CTL_SFT 16 +#define SLT_CNT_FLAG_CTL_MASK 0x1 +#define SLT_CNT_FLAG_CTL_MASK_SFT (0x1 << 16) +#define SLT_COUNTER_CTL_SFT 0 +#define SLT_COUNTER_CTL_MASK 0x7ff +#define SLT_COUNTER_CTL_MASK_SFT (0x7ff << 0) + +/* AFE_ADDA_UL0_IIR_COEF_02_01 */ +#define ADDA_IIR_COEF_02_01_SFT 0 +#define ADDA_IIR_COEF_02_01_MASK 0xffffffff +#define ADDA_IIR_COEF_02_01_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL0_IIR_COEF_04_03 */ +#define ADDA_IIR_COEF_04_03_SFT 0 +#define ADDA_IIR_COEF_04_03_MASK 0xffffffff +#define ADDA_IIR_COEF_04_03_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL0_IIR_COEF_06_05 */ +#define ADDA_IIR_COEF_06_05_SFT 0 +#define ADDA_IIR_COEF_06_05_MASK 0xffffffff +#define ADDA_IIR_COEF_06_05_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL0_IIR_COEF_08_07 */ +#define ADDA_IIR_COEF_08_07_SFT 0 +#define ADDA_IIR_COEF_08_07_MASK 0xffffffff +#define ADDA_IIR_COEF_08_07_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL0_IIR_COEF_10_09 */ +#define ADDA_IIR_COEF_10_09_SFT 0 +#define ADDA_IIR_COEF_10_09_MASK 0xffffffff +#define ADDA_IIR_COEF_10_09_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL0_ULCF_CFG_02_01 */ +#define ADDA_ULCF_CFG_02_01_SFT 0 +#define ADDA_ULCF_CFG_02_01_MASK 0xffffffff +#define ADDA_ULCF_CFG_02_01_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL0_ULCF_CFG_04_03 */ +#define ADDA_ULCF_CFG_04_03_SFT 0 +#define ADDA_ULCF_CFG_04_03_MASK 0xffffffff +#define ADDA_ULCF_CFG_04_03_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL0_ULCF_CFG_06_05 */ +#define ADDA_ULCF_CFG_06_05_SFT 0 +#define ADDA_ULCF_CFG_06_05_MASK 0xffffffff +#define ADDA_ULCF_CFG_06_05_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL0_ULCF_CFG_08_07 */ +#define ADDA_ULCF_CFG_08_07_SFT 0 +#define ADDA_ULCF_CFG_08_07_MASK 0xffffffff +#define ADDA_ULCF_CFG_08_07_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL0_ULCF_CFG_10_09 */ +#define ADDA_ULCF_CFG_10_09_SFT 0 +#define ADDA_ULCF_CFG_10_09_MASK 0xffffffff +#define ADDA_ULCF_CFG_10_09_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL0_ULCF_CFG_12_11 */ +#define ADDA_ULCF_CFG_12_11_SFT 0 +#define ADDA_ULCF_CFG_12_11_MASK 0xffffffff +#define ADDA_ULCF_CFG_12_11_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL0_ULCF_CFG_14_13 */ +#define ADDA_ULCF_CFG_14_13_SFT 0 +#define ADDA_ULCF_CFG_14_13_MASK 0xffffffff +#define ADDA_ULCF_CFG_14_13_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL0_ULCF_CFG_16_15 */ +#define ADDA_ULCF_CFG_16_15_SFT 0 +#define ADDA_ULCF_CFG_16_15_MASK 0xffffffff +#define ADDA_ULCF_CFG_16_15_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL0_ULCF_CFG_18_17 */ +#define ADDA_ULCF_CFG_18_17_SFT 0 +#define ADDA_ULCF_CFG_18_17_MASK 0xffffffff +#define ADDA_ULCF_CFG_18_17_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL0_ULCF_CFG_20_19 */ +#define ADDA_ULCF_CFG_20_19_SFT 0 +#define ADDA_ULCF_CFG_20_19_MASK 0xffffffff +#define ADDA_ULCF_CFG_20_19_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL0_ULCF_CFG_22_21 */ +#define ADDA_ULCF_CFG_22_21_SFT 0 +#define ADDA_ULCF_CFG_22_21_MASK 0xffffffff +#define ADDA_ULCF_CFG_22_21_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL0_ULCF_CFG_24_23 */ +#define ADDA_ULCF_CFG_24_23_SFT 0 +#define ADDA_ULCF_CFG_24_23_MASK 0xffffffff +#define ADDA_ULCF_CFG_24_23_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL0_ULCF_CFG_26_25 */ +#define ADDA_ULCF_CFG_26_25_SFT 0 +#define ADDA_ULCF_CFG_26_25_MASK 0xffffffff +#define ADDA_ULCF_CFG_26_25_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL0_ULCF_CFG_28_27 */ +#define ADDA_ULCF_CFG_28_27_SFT 0 +#define ADDA_ULCF_CFG_28_27_MASK 0xffffffff +#define ADDA_ULCF_CFG_28_27_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL0_ULCF_CFG_30_29 */ +#define ADDA_ULCF_CFG_30_29_SFT 0 +#define ADDA_ULCF_CFG_30_29_MASK 0xffffffff +#define ADDA_ULCF_CFG_30_29_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL0_ULCF_CFG_32_31 */ +#define ADDA_ULCF_CFG_32_31_SFT 0 +#define ADDA_ULCF_CFG_32_31_MASK 0xffffffff +#define ADDA_ULCF_CFG_32_31_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL0_IP_VERSION */ +#define ADDA_ULCF_IP_VERSION_SFT 0 +#define ADDA_ULCF_IP_VERSION_MASK 0xffffffff +#define ADDA_ULCF_IP_VERSION_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL1_SRC_CON0 */ +#define ULCF_CFG_EN_CTL_SFT 31 +#define ULCF_CFG_EN_CTL_MASK 0x1 +#define ULCF_CFG_EN_CTL_MASK_SFT (0x1 << 31) +#define UL_DMIC_PHASE_SEL_CH1_SFT 27 +#define UL_DMIC_PHASE_SEL_CH1_MASK 0x7 +#define UL_DMIC_PHASE_SEL_CH1_MASK_SFT (0x7 << 27) +#define UL_DMIC_PHASE_SEL_CH2_SFT 24 +#define UL_DMIC_PHASE_SEL_CH2_MASK 0x7 +#define UL_DMIC_PHASE_SEL_CH2_MASK_SFT (0x7 << 24) +#define UL_DMIC_TWO_WIRE_CTL_SFT 23 +#define UL_DMIC_TWO_WIRE_CTL_MASK 0x1 +#define UL_DMIC_TWO_WIRE_CTL_MASK_SFT (0x1 << 23) +#define UL_MODE_3P25M_CH2_CTL_SFT 22 +#define UL_MODE_3P25M_CH2_CTL_MASK 0x1 +#define UL_MODE_3P25M_CH2_CTL_MASK_SFT (0x1 << 22) +#define UL_MODE_3P25M_CH1_CTL_SFT 21 +#define UL_MODE_3P25M_CH1_CTL_MASK 0x1 +#define UL_MODE_3P25M_CH1_CTL_MASK_SFT (0x1 << 21) +#define UL_VOICE_MODE_CH1_CH2_CTL_SFT 17 +#define UL_VOICE_MODE_CH1_CH2_CTL_MASK 0x7 +#define UL_VOICE_MODE_CH1_CH2_CTL_MASK_SFT (0x7 << 17) +#define UL_AP_DMIC_ON_SFT 16 +#define UL_AP_DMIC_ON_MASK 0x1 +#define UL_AP_DMIC_ON_MASK_SFT (0x1 << 16) +#define DMIC_LOW_POWER_MODE_CTL_SFT 14 +#define DMIC_LOW_POWER_MODE_CTL_MASK 0x3 +#define DMIC_LOW_POWER_MODE_CTL_MASK_SFT (0x3 << 14) +#define UL_DISABLE_HW_CG_CTL_SFT 12 +#define UL_DISABLE_HW_CG_CTL_MASK 0x1 +#define UL_DISABLE_HW_CG_CTL_MASK_SFT (0x1 << 12) +#define AMIC_26M_SEL_CTL_SFT 11 +#define AMIC_26M_SEL_CTL_MASK 0x1 +#define AMIC_26M_SEL_CTL_MASK_SFT (0x1 << 11) +#define UL_IIR_ON_TMP_CTL_SFT 10 +#define UL_IIR_ON_TMP_CTL_MASK 0x1 +#define UL_IIR_ON_TMP_CTL_MASK_SFT (0x1 << 10) +#define UL_IIRMODE_CTL_SFT 7 +#define UL_IIRMODE_CTL_MASK 0x7 +#define UL_IIRMODE_CTL_MASK_SFT (0x7 << 7) +#define DIGMIC_4P33M_SEL_SFT 6 +#define DIGMIC_4P33M_SEL_MASK 0x1 +#define DIGMIC_4P33M_SEL_MASK_SFT (0x1 << 6) +#define DIGMIC_3P25M_1P625M_SEL_CTL_SFT 5 +#define DIGMIC_3P25M_1P625M_SEL_CTL_MASK 0x1 +#define DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT (0x1 << 5) +#define AMIC_6P5M_SEL_CTL_SFT 4 +#define AMIC_6P5M_SEL_CTL_MASK 0x1 +#define AMIC_6P5M_SEL_CTL_MASK_SFT (0x1 << 4) +#define AMIC_1P625M_SEL_CTL_SFT 3 +#define AMIC_1P625M_SEL_CTL_MASK 0x1 +#define AMIC_1P625M_SEL_CTL_MASK_SFT (0x1 << 3) +#define UL_LOOP_BACK_MODE_CTL_SFT 2 +#define UL_LOOP_BACK_MODE_CTL_MASK 0x1 +#define UL_LOOP_BACK_MODE_CTL_MASK_SFT (0x1 << 2) +#define UL_SDM_3_LEVEL_CTL_SFT 1 +#define UL_SDM_3_LEVEL_CTL_MASK 0x1 +#define UL_SDM_3_LEVEL_CTL_MASK_SFT (0x1 << 1) +#define UL_SRC_ON_TMP_CTL_SFT 0 +#define UL_SRC_ON_TMP_CTL_MASK 0x1 +#define UL_SRC_ON_TMP_CTL_MASK_SFT (0x1 << 0) + +/* AFE_ADDA_UL1_SRC_CON1 */ +#define ADDA_UL_GAIN_VALUE_SFT 16 +#define ADDA_UL_GAIN_VALUE_MASK 0xffff +#define ADDA_UL_GAIN_VALUE_MASK_SFT (0xffff << 16) +#define ADDA_UL_POSTIVEGAIN_SFT 12 +#define ADDA_UL_POSTIVEGAIN_MASK 0x7 +#define ADDA_UL_POSTIVEGAIN_MASK_SFT (0x7 << 12) +#define ADDA_UL_ODDTAP_MODE_SFT 11 +#define ADDA_UL_ODDTAP_MODE_MASK 0x1 +#define ADDA_UL_ODDTAP_MODE_MASK_SFT (0x1 << 11) +#define ADDA_UL_HALF_TAP_NUM_SFT 5 +#define ADDA_UL_HALF_TAP_NUM_MASK 0x3f +#define ADDA_UL_HALF_TAP_NUM_MASK_SFT (0x3f << 5) +#define FIFO_SOFT_RST_SFT 4 +#define FIFO_SOFT_RST_MASK 0x1 +#define FIFO_SOFT_RST_MASK_SFT (0x1 << 4) +#define FIFO_SOFT_RST_EN_SFT 3 +#define FIFO_SOFT_RST_EN_MASK 0x1 +#define FIFO_SOFT_RST_EN_MASK_SFT (0x1 << 3) +#define LR_SWAP_SFT 2 +#define LR_SWAP_MASK 0x1 +#define LR_SWAP_MASK_SFT (0x1 << 2) +#define GAIN_MODE_SFT 0 +#define GAIN_MODE_MASK 0x3 +#define GAIN_MODE_MASK_SFT (0x3 << 0) + +/* AFE_ADDA_UL1_SRC_CON2 */ +#define C_DAC_EN_CTL_SFT 27 +#define C_DAC_EN_CTL_MASK 0x1 +#define C_DAC_EN_CTL_MASK_SFT (0x1 << 27) +#define C_MUTE_SW_CTL_SFT 26 +#define C_MUTE_SW_CTL_MASK 0x1 +#define C_MUTE_SW_CTL_MASK_SFT (0x1 << 26) +#define C_AMP_DIV_CH2_CTL_SFT 21 +#define C_AMP_DIV_CH2_CTL_MASK 0x7 +#define C_AMP_DIV_CH2_CTL_MASK_SFT (0x7 << 21) +#define C_FREQ_DIV_CH2_CTL_SFT 16 +#define C_FREQ_DIV_CH2_CTL_MASK 0x1f +#define C_FREQ_DIV_CH2_CTL_MASK_SFT (0x1f << 16) +#define C_SINE_MODE_CH2_CTL_SFT 12 +#define C_SINE_MODE_CH2_CTL_MASK 0xf +#define C_SINE_MODE_CH2_CTL_MASK_SFT (0xf << 12) +#define C_AMP_DIV_CH1_CTL_SFT 9 +#define C_AMP_DIV_CH1_CTL_MASK 0x7 +#define C_AMP_DIV_CH1_CTL_MASK_SFT (0x7 << 9) +#define C_FREQ_DIV_CH1_CTL_SFT 4 +#define C_FREQ_DIV_CH1_CTL_MASK 0x1f +#define C_FREQ_DIV_CH1_CTL_MASK_SFT (0x1f << 4) +#define C_SINE_MODE_CH1_CTL_SFT 0 +#define C_SINE_MODE_CH1_CTL_MASK 0xf +#define C_SINE_MODE_CH1_CTL_MASK_SFT (0xf << 0) + +/* AFE_ADDA_UL1_SRC_DEBUG */ +#define UL_SLT_CNT_FLAG_RESET_CTL_SFT 16 +#define UL_SLT_CNT_FLAG_RESET_CTL_MASK 0x1 +#define UL_SLT_CNT_FLAG_RESET_CTL_MASK_SFT (0x1 << 16) +#define FIFO_DIGMIC_TESTIN_SFT 12 +#define FIFO_DIGMIC_TESTIN_MASK 0x3 +#define FIFO_DIGMIC_TESTIN_MASK_SFT (0x3 << 12) +#define FIFO_DIGMIC_WDATA_TESTEN_SFT 11 +#define FIFO_DIGMIC_WDATA_TESTEN_MASK 0x1 +#define FIFO_DIGMIC_WDATA_TESTEN_MASK_SFT (0x1 << 11) +#define SLT_CNT_THD_CTL_SFT 0 +#define SLT_CNT_THD_CTL_MASK 0x7ff +#define SLT_CNT_THD_CTL_MASK_SFT (0x7ff << 0) + +/* AFE_ADDA_UL1_SRC_DEBUG_MON0 */ +#define SLT_CNT_FLAG_CTL_SFT 16 +#define SLT_CNT_FLAG_CTL_MASK 0x1 +#define SLT_CNT_FLAG_CTL_MASK_SFT (0x1 << 16) +#define SLT_COUNTER_CTL_SFT 0 +#define SLT_COUNTER_CTL_MASK 0x7ff +#define SLT_COUNTER_CTL_MASK_SFT (0x7ff << 0) + +/* AFE_ADDA_UL1_IIR_COEF_02_01 */ +#define ADDA_IIR_COEF_02_01_SFT 0 +#define ADDA_IIR_COEF_02_01_MASK 0xffffffff +#define ADDA_IIR_COEF_02_01_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL1_IIR_COEF_04_03 */ +#define ADDA_IIR_COEF_04_03_SFT 0 +#define ADDA_IIR_COEF_04_03_MASK 0xffffffff +#define ADDA_IIR_COEF_04_03_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL1_IIR_COEF_06_05 */ +#define ADDA_IIR_COEF_06_05_SFT 0 +#define ADDA_IIR_COEF_06_05_MASK 0xffffffff +#define ADDA_IIR_COEF_06_05_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL1_IIR_COEF_08_07 */ +#define ADDA_IIR_COEF_08_07_SFT 0 +#define ADDA_IIR_COEF_08_07_MASK 0xffffffff +#define ADDA_IIR_COEF_08_07_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL1_IIR_COEF_10_09 */ +#define ADDA_IIR_COEF_10_09_SFT 0 +#define ADDA_IIR_COEF_10_09_MASK 0xffffffff +#define ADDA_IIR_COEF_10_09_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL1_ULCF_CFG_02_01 */ +#define ADDA_ULCF_CFG_02_01_SFT 0 +#define ADDA_ULCF_CFG_02_01_MASK 0xffffffff +#define ADDA_ULCF_CFG_02_01_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL1_ULCF_CFG_04_03 */ +#define ADDA_ULCF_CFG_04_03_SFT 0 +#define ADDA_ULCF_CFG_04_03_MASK 0xffffffff +#define ADDA_ULCF_CFG_04_03_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL1_ULCF_CFG_06_05 */ +#define ADDA_ULCF_CFG_06_05_SFT 0 +#define ADDA_ULCF_CFG_06_05_MASK 0xffffffff +#define ADDA_ULCF_CFG_06_05_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL1_ULCF_CFG_08_07 */ +#define ADDA_ULCF_CFG_08_07_SFT 0 +#define ADDA_ULCF_CFG_08_07_MASK 0xffffffff +#define ADDA_ULCF_CFG_08_07_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL1_ULCF_CFG_10_09 */ +#define ADDA_ULCF_CFG_10_09_SFT 0 +#define ADDA_ULCF_CFG_10_09_MASK 0xffffffff +#define ADDA_ULCF_CFG_10_09_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL1_ULCF_CFG_12_11 */ +#define ADDA_ULCF_CFG_12_11_SFT 0 +#define ADDA_ULCF_CFG_12_11_MASK 0xffffffff +#define ADDA_ULCF_CFG_12_11_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL1_ULCF_CFG_14_13 */ +#define ADDA_ULCF_CFG_14_13_SFT 0 +#define ADDA_ULCF_CFG_14_13_MASK 0xffffffff +#define ADDA_ULCF_CFG_14_13_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL1_ULCF_CFG_16_15 */ +#define ADDA_ULCF_CFG_16_15_SFT 0 +#define ADDA_ULCF_CFG_16_15_MASK 0xffffffff +#define ADDA_ULCF_CFG_16_15_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL1_ULCF_CFG_18_17 */ +#define ADDA_ULCF_CFG_18_17_SFT 0 +#define ADDA_ULCF_CFG_18_17_MASK 0xffffffff +#define ADDA_ULCF_CFG_18_17_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL1_ULCF_CFG_20_19 */ +#define ADDA_ULCF_CFG_20_19_SFT 0 +#define ADDA_ULCF_CFG_20_19_MASK 0xffffffff +#define ADDA_ULCF_CFG_20_19_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL1_ULCF_CFG_22_21 */ +#define ADDA_ULCF_CFG_22_21_SFT 0 +#define ADDA_ULCF_CFG_22_21_MASK 0xffffffff +#define ADDA_ULCF_CFG_22_21_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL1_ULCF_CFG_24_23 */ +#define ADDA_ULCF_CFG_24_23_SFT 0 +#define ADDA_ULCF_CFG_24_23_MASK 0xffffffff +#define ADDA_ULCF_CFG_24_23_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL1_ULCF_CFG_26_25 */ +#define ADDA_ULCF_CFG_26_25_SFT 0 +#define ADDA_ULCF_CFG_26_25_MASK 0xffffffff +#define ADDA_ULCF_CFG_26_25_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL1_ULCF_CFG_28_27 */ +#define ADDA_ULCF_CFG_28_27_SFT 0 +#define ADDA_ULCF_CFG_28_27_MASK 0xffffffff +#define ADDA_ULCF_CFG_28_27_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL1_ULCF_CFG_30_29 */ +#define ADDA_ULCF_CFG_30_29_SFT 0 +#define ADDA_ULCF_CFG_30_29_MASK 0xffffffff +#define ADDA_ULCF_CFG_30_29_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL1_ULCF_CFG_32_31 */ +#define ADDA_ULCF_CFG_32_31_SFT 0 +#define ADDA_ULCF_CFG_32_31_MASK 0xffffffff +#define ADDA_ULCF_CFG_32_31_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL1_IP_VERSION */ +#define ADDA_ULCF_IP_VERSION_SFT 0 +#define ADDA_ULCF_IP_VERSION_MASK 0xffffffff +#define ADDA_ULCF_IP_VERSION_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL2_SRC_CON0 */ +#define ULCF_CFG_EN_CTL_SFT 31 +#define ULCF_CFG_EN_CTL_MASK 0x1 +#define ULCF_CFG_EN_CTL_MASK_SFT (0x1 << 31) +#define UL_DMIC_PHASE_SEL_CH1_SFT 27 +#define UL_DMIC_PHASE_SEL_CH1_MASK 0x7 +#define UL_DMIC_PHASE_SEL_CH1_MASK_SFT (0x7 << 27) +#define UL_DMIC_PHASE_SEL_CH2_SFT 24 +#define UL_DMIC_PHASE_SEL_CH2_MASK 0x7 +#define UL_DMIC_PHASE_SEL_CH2_MASK_SFT (0x7 << 24) +#define UL_DMIC_TWO_WIRE_CTL_SFT 23 +#define UL_DMIC_TWO_WIRE_CTL_MASK 0x1 +#define UL_DMIC_TWO_WIRE_CTL_MASK_SFT (0x1 << 23) +#define UL_MODE_3P25M_CH2_CTL_SFT 22 +#define UL_MODE_3P25M_CH2_CTL_MASK 0x1 +#define UL_MODE_3P25M_CH2_CTL_MASK_SFT (0x1 << 22) +#define UL_MODE_3P25M_CH1_CTL_SFT 21 +#define UL_MODE_3P25M_CH1_CTL_MASK 0x1 +#define UL_MODE_3P25M_CH1_CTL_MASK_SFT (0x1 << 21) +#define UL_VOICE_MODE_CH1_CH2_CTL_SFT 17 +#define UL_VOICE_MODE_CH1_CH2_CTL_MASK 0x7 +#define UL_VOICE_MODE_CH1_CH2_CTL_MASK_SFT (0x7 << 17) +#define UL_AP_DMIC_ON_SFT 16 +#define UL_AP_DMIC_ON_MASK 0x1 +#define UL_AP_DMIC_ON_MASK_SFT (0x1 << 16) +#define DMIC_LOW_POWER_MODE_CTL_SFT 14 +#define DMIC_LOW_POWER_MODE_CTL_MASK 0x3 +#define DMIC_LOW_POWER_MODE_CTL_MASK_SFT (0x3 << 14) +#define UL_DISABLE_HW_CG_CTL_SFT 12 +#define UL_DISABLE_HW_CG_CTL_MASK 0x1 +#define UL_DISABLE_HW_CG_CTL_MASK_SFT (0x1 << 12) +#define AMIC_26M_SEL_CTL_SFT 11 +#define AMIC_26M_SEL_CTL_MASK 0x1 +#define AMIC_26M_SEL_CTL_MASK_SFT (0x1 << 11) +#define UL_IIR_ON_TMP_CTL_SFT 10 +#define UL_IIR_ON_TMP_CTL_MASK 0x1 +#define UL_IIR_ON_TMP_CTL_MASK_SFT (0x1 << 10) +#define UL_IIRMODE_CTL_SFT 7 +#define UL_IIRMODE_CTL_MASK 0x7 +#define UL_IIRMODE_CTL_MASK_SFT (0x7 << 7) +#define DIGMIC_4P33M_SEL_SFT 6 +#define DIGMIC_4P33M_SEL_MASK 0x1 +#define DIGMIC_4P33M_SEL_MASK_SFT (0x1 << 6) +#define DIGMIC_3P25M_1P625M_SEL_CTL_SFT 5 +#define DIGMIC_3P25M_1P625M_SEL_CTL_MASK 0x1 +#define DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT (0x1 << 5) +#define AMIC_6P5M_SEL_CTL_SFT 4 +#define AMIC_6P5M_SEL_CTL_MASK 0x1 +#define AMIC_6P5M_SEL_CTL_MASK_SFT (0x1 << 4) +#define AMIC_1P625M_SEL_CTL_SFT 3 +#define AMIC_1P625M_SEL_CTL_MASK 0x1 +#define AMIC_1P625M_SEL_CTL_MASK_SFT (0x1 << 3) +#define UL_LOOP_BACK_MODE_CTL_SFT 2 +#define UL_LOOP_BACK_MODE_CTL_MASK 0x1 +#define UL_LOOP_BACK_MODE_CTL_MASK_SFT (0x1 << 2) +#define UL_SDM_3_LEVEL_CTL_SFT 1 +#define UL_SDM_3_LEVEL_CTL_MASK 0x1 +#define UL_SDM_3_LEVEL_CTL_MASK_SFT (0x1 << 1) +#define UL_SRC_ON_TMP_CTL_SFT 0 +#define UL_SRC_ON_TMP_CTL_MASK 0x1 +#define UL_SRC_ON_TMP_CTL_MASK_SFT (0x1 << 0) + +/* AFE_ADDA_UL2_SRC_CON1 */ +#define ADDA_UL_GAIN_VALUE_SFT 16 +#define ADDA_UL_GAIN_VALUE_MASK 0xffff +#define ADDA_UL_GAIN_VALUE_MASK_SFT (0xffff << 16) +#define ADDA_UL_POSTIVEGAIN_SFT 12 +#define ADDA_UL_POSTIVEGAIN_MASK 0x7 +#define ADDA_UL_POSTIVEGAIN_MASK_SFT (0x7 << 12) +#define ADDA_UL_ODDTAP_MODE_SFT 11 +#define ADDA_UL_ODDTAP_MODE_MASK 0x1 +#define ADDA_UL_ODDTAP_MODE_MASK_SFT (0x1 << 11) +#define ADDA_UL_HALF_TAP_NUM_SFT 5 +#define ADDA_UL_HALF_TAP_NUM_MASK 0x3f +#define ADDA_UL_HALF_TAP_NUM_MASK_SFT (0x3f << 5) +#define FIFO_SOFT_RST_SFT 4 +#define FIFO_SOFT_RST_MASK 0x1 +#define FIFO_SOFT_RST_MASK_SFT (0x1 << 4) +#define FIFO_SOFT_RST_EN_SFT 3 +#define FIFO_SOFT_RST_EN_MASK 0x1 +#define FIFO_SOFT_RST_EN_MASK_SFT (0x1 << 3) +#define LR_SWAP_SFT 2 +#define LR_SWAP_MASK 0x1 +#define LR_SWAP_MASK_SFT (0x1 << 2) +#define GAIN_MODE_SFT 0 +#define GAIN_MODE_MASK 0x3 +#define GAIN_MODE_MASK_SFT (0x3 << 0) + +/* AFE_ADDA_UL2_SRC_CON2 */ +#define C_DAC_EN_CTL_SFT 27 +#define C_DAC_EN_CTL_MASK 0x1 +#define C_DAC_EN_CTL_MASK_SFT (0x1 << 27) +#define C_MUTE_SW_CTL_SFT 26 +#define C_MUTE_SW_CTL_MASK 0x1 +#define C_MUTE_SW_CTL_MASK_SFT (0x1 << 26) +#define C_AMP_DIV_CH2_CTL_SFT 21 +#define C_AMP_DIV_CH2_CTL_MASK 0x7 +#define C_AMP_DIV_CH2_CTL_MASK_SFT (0x7 << 21) +#define C_FREQ_DIV_CH2_CTL_SFT 16 +#define C_FREQ_DIV_CH2_CTL_MASK 0x1f +#define C_FREQ_DIV_CH2_CTL_MASK_SFT (0x1f << 16) +#define C_SINE_MODE_CH2_CTL_SFT 12 +#define C_SINE_MODE_CH2_CTL_MASK 0xf +#define C_SINE_MODE_CH2_CTL_MASK_SFT (0xf << 12) +#define C_AMP_DIV_CH1_CTL_SFT 9 +#define C_AMP_DIV_CH1_CTL_MASK 0x7 +#define C_AMP_DIV_CH1_CTL_MASK_SFT (0x7 << 9) +#define C_FREQ_DIV_CH1_CTL_SFT 4 +#define C_FREQ_DIV_CH1_CTL_MASK 0x1f +#define C_FREQ_DIV_CH1_CTL_MASK_SFT (0x1f << 4) +#define C_SINE_MODE_CH1_CTL_SFT 0 +#define C_SINE_MODE_CH1_CTL_MASK 0xf +#define C_SINE_MODE_CH1_CTL_MASK_SFT (0xf << 0) + +/* AFE_ADDA_UL2_SRC_DEBUG */ +#define UL_SLT_CNT_FLAG_RESET_CTL_SFT 16 +#define UL_SLT_CNT_FLAG_RESET_CTL_MASK 0x1 +#define UL_SLT_CNT_FLAG_RESET_CTL_MASK_SFT (0x1 << 16) +#define FIFO_DIGMIC_TESTIN_SFT 12 +#define FIFO_DIGMIC_TESTIN_MASK 0x3 +#define FIFO_DIGMIC_TESTIN_MASK_SFT (0x3 << 12) +#define FIFO_DIGMIC_WDATA_TESTEN_SFT 11 +#define FIFO_DIGMIC_WDATA_TESTEN_MASK 0x1 +#define FIFO_DIGMIC_WDATA_TESTEN_MASK_SFT (0x1 << 11) +#define SLT_CNT_THD_CTL_SFT 0 +#define SLT_CNT_THD_CTL_MASK 0x7ff +#define SLT_CNT_THD_CTL_MASK_SFT (0x7ff << 0) + +/* AFE_ADDA_UL2_SRC_DEBUG_MON0 */ +#define SLT_CNT_FLAG_CTL_SFT 16 +#define SLT_CNT_FLAG_CTL_MASK 0x1 +#define SLT_CNT_FLAG_CTL_MASK_SFT (0x1 << 16) +#define SLT_COUNTER_CTL_SFT 0 +#define SLT_COUNTER_CTL_MASK 0x7ff +#define SLT_COUNTER_CTL_MASK_SFT (0x7ff << 0) + +/* AFE_ADDA_UL2_IIR_COEF_02_01 */ +#define ADDA_IIR_COEF_02_01_SFT 0 +#define ADDA_IIR_COEF_02_01_MASK 0xffffffff +#define ADDA_IIR_COEF_02_01_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL2_IIR_COEF_04_03 */ +#define ADDA_IIR_COEF_04_03_SFT 0 +#define ADDA_IIR_COEF_04_03_MASK 0xffffffff +#define ADDA_IIR_COEF_04_03_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL2_IIR_COEF_06_05 */ +#define ADDA_IIR_COEF_06_05_SFT 0 +#define ADDA_IIR_COEF_06_05_MASK 0xffffffff +#define ADDA_IIR_COEF_06_05_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL2_IIR_COEF_08_07 */ +#define ADDA_IIR_COEF_08_07_SFT 0 +#define ADDA_IIR_COEF_08_07_MASK 0xffffffff +#define ADDA_IIR_COEF_08_07_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL2_IIR_COEF_10_09 */ +#define ADDA_IIR_COEF_10_09_SFT 0 +#define ADDA_IIR_COEF_10_09_MASK 0xffffffff +#define ADDA_IIR_COEF_10_09_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL2_ULCF_CFG_02_01 */ +#define ADDA_ULCF_CFG_02_01_SFT 0 +#define ADDA_ULCF_CFG_02_01_MASK 0xffffffff +#define ADDA_ULCF_CFG_02_01_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL2_ULCF_CFG_04_03 */ +#define ADDA_ULCF_CFG_04_03_SFT 0 +#define ADDA_ULCF_CFG_04_03_MASK 0xffffffff +#define ADDA_ULCF_CFG_04_03_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL2_ULCF_CFG_06_05 */ +#define ADDA_ULCF_CFG_06_05_SFT 0 +#define ADDA_ULCF_CFG_06_05_MASK 0xffffffff +#define ADDA_ULCF_CFG_06_05_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL2_ULCF_CFG_08_07 */ +#define ADDA_ULCF_CFG_08_07_SFT 0 +#define ADDA_ULCF_CFG_08_07_MASK 0xffffffff +#define ADDA_ULCF_CFG_08_07_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL2_ULCF_CFG_10_09 */ +#define ADDA_ULCF_CFG_10_09_SFT 0 +#define ADDA_ULCF_CFG_10_09_MASK 0xffffffff +#define ADDA_ULCF_CFG_10_09_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL2_ULCF_CFG_12_11 */ +#define ADDA_ULCF_CFG_12_11_SFT 0 +#define ADDA_ULCF_CFG_12_11_MASK 0xffffffff +#define ADDA_ULCF_CFG_12_11_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL2_ULCF_CFG_14_13 */ +#define ADDA_ULCF_CFG_14_13_SFT 0 +#define ADDA_ULCF_CFG_14_13_MASK 0xffffffff +#define ADDA_ULCF_CFG_14_13_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL2_ULCF_CFG_16_15 */ +#define ADDA_ULCF_CFG_16_15_SFT 0 +#define ADDA_ULCF_CFG_16_15_MASK 0xffffffff +#define ADDA_ULCF_CFG_16_15_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL2_ULCF_CFG_18_17 */ +#define ADDA_ULCF_CFG_18_17_SFT 0 +#define ADDA_ULCF_CFG_18_17_MASK 0xffffffff +#define ADDA_ULCF_CFG_18_17_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL2_ULCF_CFG_20_19 */ +#define ADDA_ULCF_CFG_20_19_SFT 0 +#define ADDA_ULCF_CFG_20_19_MASK 0xffffffff +#define ADDA_ULCF_CFG_20_19_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL2_ULCF_CFG_22_21 */ +#define ADDA_ULCF_CFG_22_21_SFT 0 +#define ADDA_ULCF_CFG_22_21_MASK 0xffffffff +#define ADDA_ULCF_CFG_22_21_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL2_ULCF_CFG_24_23 */ +#define ADDA_ULCF_CFG_24_23_SFT 0 +#define ADDA_ULCF_CFG_24_23_MASK 0xffffffff +#define ADDA_ULCF_CFG_24_23_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL2_ULCF_CFG_26_25 */ +#define ADDA_ULCF_CFG_26_25_SFT 0 +#define ADDA_ULCF_CFG_26_25_MASK 0xffffffff +#define ADDA_ULCF_CFG_26_25_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL2_ULCF_CFG_28_27 */ +#define ADDA_ULCF_CFG_28_27_SFT 0 +#define ADDA_ULCF_CFG_28_27_MASK 0xffffffff +#define ADDA_ULCF_CFG_28_27_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL2_ULCF_CFG_30_29 */ +#define ADDA_ULCF_CFG_30_29_SFT 0 +#define ADDA_ULCF_CFG_30_29_MASK 0xffffffff +#define ADDA_ULCF_CFG_30_29_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL2_ULCF_CFG_32_31 */ +#define ADDA_ULCF_CFG_32_31_SFT 0 +#define ADDA_ULCF_CFG_32_31_MASK 0xffffffff +#define ADDA_ULCF_CFG_32_31_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL2_IP_VERSION */ +#define ADDA_ULCF_IP_VERSION_SFT 0 +#define ADDA_ULCF_IP_VERSION_MASK 0xffffffff +#define ADDA_ULCF_IP_VERSION_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_PROXIMITY_CON0 */ +#define PROXIMITY_CH1_ON_SFT 12 +#define PROXIMITY_CH1_ON_MASK 0x1 +#define PROXIMITY_CH1_ON_MASK_SFT (0x1 << 12) +#define PROXIMITY_CH1_SEL_SFT 8 +#define PROXIMITY_CH1_SEL_MASK 0xf +#define PROXIMITY_CH1_SEL_MASK_SFT (0xf << 8) +#define PROXIMITY_CH2_ON_SFT 4 +#define PROXIMITY_CH2_ON_MASK 0x1 +#define PROXIMITY_CH2_ON_MASK_SFT (0x1 << 4) +#define PROXIMITY_CH2_SEL_SFT 0 +#define PROXIMITY_CH2_SEL_MASK 0xf +#define PROXIMITY_CH2_SEL_MASK_SFT (0xf << 0) + +/* AFE_ADDA_ULSRC_PHASE_CON0 */ +#define DMIC1_PHASE_FCLK_SEL_SFT 30 +#define DMIC1_PHASE_FCLK_SEL_MASK 0x3 +#define DMIC1_PHASE_FCLK_SEL_MASK_SFT (0x3 << 30) +#define DMIC0_PHASE_FCLK_SEL_SFT 28 +#define DMIC0_PHASE_FCLK_SEL_MASK 0x3 +#define DMIC0_PHASE_FCLK_SEL_MASK_SFT (0x3 << 28) +#define UL3_PHASE_FCLK_SEL_SFT 26 +#define UL3_PHASE_FCLK_SEL_MASK 0x3 +#define UL3_PHASE_FCLK_SEL_MASK_SFT (0x3 << 26) +#define UL2_PHASE_FCLK_SEL_SFT 24 +#define UL2_PHASE_FCLK_SEL_MASK 0x3 +#define UL2_PHASE_FCLK_SEL_MASK_SFT (0x3 << 24) +#define UL1_PHASE_FCLK_SEL_SFT 22 +#define UL1_PHASE_FCLK_SEL_MASK 0x3 +#define UL1_PHASE_FCLK_SEL_MASK_SFT (0x3 << 22) +#define UL0_PHASE_FCLK_SEL_SFT 20 +#define UL0_PHASE_FCLK_SEL_MASK 0x3 +#define UL0_PHASE_FCLK_SEL_MASK_SFT (0x3 << 20) +#define UL_PHASE_SYNC_FCLK_2_ON_SFT 18 +#define UL_PHASE_SYNC_FCLK_2_ON_MASK 0x1 +#define UL_PHASE_SYNC_FCLK_2_ON_MASK_SFT (0x1 << 18) +#define UL_PHASE_SYNC_FCLK_1_ON_SFT 17 +#define UL_PHASE_SYNC_FCLK_1_ON_MASK 0x1 +#define UL_PHASE_SYNC_FCLK_1_ON_MASK_SFT (0x1 << 17) +#define UL_PHASE_SYNC_FCLK_0_ON_SFT 16 +#define UL_PHASE_SYNC_FCLK_0_ON_MASK 0x1 +#define UL_PHASE_SYNC_FCLK_0_ON_MASK_SFT (0x1 << 16) +#define DMIC1_PHASE_HCLK_SEL_SFT 14 +#define DMIC1_PHASE_HCLK_SEL_MASK 0x3 +#define DMIC1_PHASE_HCLK_SEL_MASK_SFT (0x3 << 14) +#define DMIC0_PHASE_HCLK_SEL_SFT 12 +#define DMIC0_PHASE_HCLK_SEL_MASK 0x3 +#define DMIC0_PHASE_HCLK_SEL_MASK_SFT (0x3 << 12) +#define UL3_PHASE_HCLK_SEL_SFT 10 +#define UL3_PHASE_HCLK_SEL_MASK 0x3 +#define UL3_PHASE_HCLK_SEL_MASK_SFT (0x3 << 10) +#define UL2_PHASE_HCLK_SEL_SFT 8 +#define UL2_PHASE_HCLK_SEL_MASK 0x3 +#define UL2_PHASE_HCLK_SEL_MASK_SFT (0x3 << 8) +#define UL1_PHASE_HCLK_SEL_SFT 6 +#define UL1_PHASE_HCLK_SEL_MASK 0x3 +#define UL1_PHASE_HCLK_SEL_MASK_SFT (0x3 << 6) +#define UL0_PHASE_HCLK_SEL_SFT 4 +#define UL0_PHASE_HCLK_SEL_MASK 0x3 +#define UL0_PHASE_HCLK_SEL_MASK_SFT (0x3 << 4) +#define UL_PHASE_SYNC_HCLK_2_ON_SFT 2 +#define UL_PHASE_SYNC_HCLK_2_ON_MASK 0x1 +#define UL_PHASE_SYNC_HCLK_2_ON_MASK_SFT (0x1 << 2) +#define UL_PHASE_SYNC_HCLK_1_ON_SFT 1 +#define UL_PHASE_SYNC_HCLK_1_ON_MASK 0x1 +#define UL_PHASE_SYNC_HCLK_1_ON_MASK_SFT (0x1 << 1) +#define UL_PHASE_SYNC_HCLK_0_ON_SFT 0 +#define UL_PHASE_SYNC_HCLK_0_ON_MASK 0x1 +#define UL_PHASE_SYNC_HCLK_0_ON_MASK_SFT (0x1 << 0) + +/* AFE_ADDA_ULSRC_PHASE_CON1 */ +#define DMIC_CLK_PHASE_SYNC_SET_SFT 31 +#define DMIC_CLK_PHASE_SYNC_SET_MASK 0x1 +#define DMIC_CLK_PHASE_SYNC_SET_MASK_SFT (0x1 << 31) +#define DMIC1_PHASE_SYNC_FCLK_SET_SFT 11 +#define DMIC1_PHASE_SYNC_FCLK_SET_MASK 0x1 +#define DMIC1_PHASE_SYNC_FCLK_SET_MASK_SFT (0x1 << 11) +#define DMIC1_PHASE_SYNC_HCLK_SET_SFT 10 +#define DMIC1_PHASE_SYNC_HCLK_SET_MASK 0x1 +#define DMIC1_PHASE_SYNC_HCLK_SET_MASK_SFT (0x1 << 10) +#define DMIC0_PHASE_SYNC_FCLK_SET_SFT 9 +#define DMIC0_PHASE_SYNC_FCLK_SET_MASK 0x1 +#define DMIC0_PHASE_SYNC_FCLK_SET_MASK_SFT (0x1 << 9) +#define DMIC0_PHASE_SYNC_HCLK_SET_SFT 8 +#define DMIC0_PHASE_SYNC_HCLK_SET_MASK 0x1 +#define DMIC0_PHASE_SYNC_HCLK_SET_MASK_SFT (0x1 << 8) +#define UL3_PHASE_SYNC_FCLK_SET_SFT 7 +#define UL3_PHASE_SYNC_FCLK_SET_MASK 0x1 +#define UL3_PHASE_SYNC_FCLK_SET_MASK_SFT (0x1 << 7) +#define UL3_PHASE_SYNC_HCLK_SET_SFT 6 +#define UL3_PHASE_SYNC_HCLK_SET_MASK 0x1 +#define UL3_PHASE_SYNC_HCLK_SET_MASK_SFT (0x1 << 6) +#define UL2_PHASE_SYNC_FCLK_SET_SFT 5 +#define UL2_PHASE_SYNC_FCLK_SET_MASK 0x1 +#define UL2_PHASE_SYNC_FCLK_SET_MASK_SFT (0x1 << 5) +#define UL2_PHASE_SYNC_HCLK_SET_SFT 4 +#define UL2_PHASE_SYNC_HCLK_SET_MASK 0x1 +#define UL2_PHASE_SYNC_HCLK_SET_MASK_SFT (0x1 << 4) +#define UL1_PHASE_SYNC_FCLK_SET_SFT 3 +#define UL1_PHASE_SYNC_FCLK_SET_MASK 0x1 +#define UL1_PHASE_SYNC_FCLK_SET_MASK_SFT (0x1 << 3) +#define UL1_PHASE_SYNC_HCLK_SET_SFT 2 +#define UL1_PHASE_SYNC_HCLK_SET_MASK 0x1 +#define UL1_PHASE_SYNC_HCLK_SET_MASK_SFT (0x1 << 2) +#define UL0_PHASE_SYNC_FCLK_SET_SFT 1 +#define UL0_PHASE_SYNC_FCLK_SET_MASK 0x1 +#define UL0_PHASE_SYNC_FCLK_SET_MASK_SFT (0x1 << 1) +#define UL0_PHASE_SYNC_HCLK_SET_SFT 0 +#define UL0_PHASE_SYNC_HCLK_SET_MASK 0x1 +#define UL0_PHASE_SYNC_HCLK_SET_MASK_SFT (0x1 << 0) + +/* AFE_ADDA_ULSRC_PHASE_CON2 */ +#define DMIC1_PHASE_SYNC_1X_EN_SEL_SFT 26 +#define DMIC1_PHASE_SYNC_1X_EN_SEL_MASK 0x3 +#define DMIC1_PHASE_SYNC_1X_EN_SEL_MASK_SFT (0x3 << 26) +#define DMIC0_PHASE_SYNC_1X_EN_SEL_SFT 24 +#define DMIC0_PHASE_SYNC_1X_EN_SEL_MASK 0x3 +#define DMIC0_PHASE_SYNC_1X_EN_SEL_MASK_SFT (0x3 << 24) +#define UL3_PHASE_SYNC_1X_EN_SEL_SFT 22 +#define UL3_PHASE_SYNC_1X_EN_SEL_MASK 0x3 +#define UL3_PHASE_SYNC_1X_EN_SEL_MASK_SFT (0x3 << 22) +#define UL2_PHASE_SYNC_1X_EN_SEL_SFT 20 +#define UL2_PHASE_SYNC_1X_EN_SEL_MASK 0x3 +#define UL2_PHASE_SYNC_1X_EN_SEL_MASK_SFT (0x3 << 20) +#define UL1_PHASE_SYNC_1X_EN_SEL_SFT 18 +#define UL1_PHASE_SYNC_1X_EN_SEL_MASK 0x3 +#define UL1_PHASE_SYNC_1X_EN_SEL_MASK_SFT (0x3 << 18) +#define UL0_PHASE_SYNC_1X_EN_SEL_SFT 16 +#define UL0_PHASE_SYNC_1X_EN_SEL_MASK 0x3 +#define UL0_PHASE_SYNC_1X_EN_SEL_MASK_SFT (0x3 << 16) +#define UL_PHASE_SYNC_FCLK_1X_EN_2_ON_SFT 5 +#define UL_PHASE_SYNC_FCLK_1X_EN_2_ON_MASK 0x1 +#define UL_PHASE_SYNC_FCLK_1X_EN_2_ON_MASK_SFT (0x1 << 5) +#define UL_PHASE_SYNC_FCLK_1X_EN_1_ON_SFT 4 +#define UL_PHASE_SYNC_FCLK_1X_EN_1_ON_MASK 0x1 +#define UL_PHASE_SYNC_FCLK_1X_EN_1_ON_MASK_SFT (0x1 << 4) +#define UL_PHASE_SYNC_FCLK_1X_EN_0_ON_SFT 3 +#define UL_PHASE_SYNC_FCLK_1X_EN_0_ON_MASK 0x1 +#define UL_PHASE_SYNC_FCLK_1X_EN_0_ON_MASK_SFT (0x1 << 3) +#define UL_PHASE_SYNC_HCLK_1X_EN_2_ON_SFT 2 +#define UL_PHASE_SYNC_HCLK_1X_EN_2_ON_MASK 0x1 +#define UL_PHASE_SYNC_HCLK_1X_EN_2_ON_MASK_SFT (0x1 << 2) +#define UL_PHASE_SYNC_HCLK_1X_EN_1_ON_SFT 1 +#define UL_PHASE_SYNC_HCLK_1X_EN_1_ON_MASK 0x1 +#define UL_PHASE_SYNC_HCLK_1X_EN_1_ON_MASK_SFT (0x1 << 1) +#define UL_PHASE_SYNC_HCLK_1X_EN_0_ON_SFT 0 +#define UL_PHASE_SYNC_HCLK_1X_EN_0_ON_MASK 0x1 +#define UL_PHASE_SYNC_HCLK_1X_EN_0_ON_MASK_SFT (0x1 << 0) + +/* AFE_ADDA_ULSRC_PHASE_CON3 */ +#define DMIC1_PHASE_SYNC_SOFT_RST_SEL_SFT 26 +#define DMIC1_PHASE_SYNC_SOFT_RST_SEL_MASK 0x3 +#define DMIC1_PHASE_SYNC_SOFT_RST_SEL_MASK_SFT (0x3 << 26) +#define DMIC0_PHASE_SYNC_SOFT_RST_SEL_SFT 24 +#define DMIC0_PHASE_SYNC_SOFT_RST_SEL_MASK 0x3 +#define DMIC0_PHASE_SYNC_SOFT_RST_SEL_MASK_SFT (0x3 << 24) +#define UL3_PHASE_SYNC_SOFT_RST_SEL_SFT 22 +#define UL3_PHASE_SYNC_SOFT_RST_SEL_MASK 0x3 +#define UL3_PHASE_SYNC_SOFT_RST_SEL_MASK_SFT (0x3 << 22) +#define UL2_PHASE_SYNC_SOFT_RST_SEL_SFT 20 +#define UL2_PHASE_SYNC_SOFT_RST_SEL_MASK 0x3 +#define UL2_PHASE_SYNC_SOFT_RST_SEL_MASK_SFT (0x3 << 20) +#define UL1_PHASE_SYNC_SOFT_RST_SEL_SFT 18 +#define UL1_PHASE_SYNC_SOFT_RST_SEL_MASK 0x3 +#define UL1_PHASE_SYNC_SOFT_RST_SEL_MASK_SFT (0x3 << 18) +#define UL0_PHASE_SYNC_SOFT_RST_SEL_SFT 16 +#define UL0_PHASE_SYNC_SOFT_RST_SEL_MASK 0x3 +#define UL0_PHASE_SYNC_SOFT_RST_SEL_MASK_SFT (0x3 << 16) +#define DMIC1_PHASE_SYNC_CH1_FIFO_SEL_SFT 13 +#define DMIC1_PHASE_SYNC_CH1_FIFO_SEL_MASK 0x1 +#define DMIC1_PHASE_SYNC_CH1_FIFO_SEL_MASK_SFT (0x1 << 13) +#define DMIC0_PHASE_SYNC_CH1_FIFO_SEL_SFT 12 +#define DMIC0_PHASE_SYNC_CH1_FIFO_SEL_MASK 0x1 +#define DMIC0_PHASE_SYNC_CH1_FIFO_SEL_MASK_SFT (0x1 << 12) +#define UL3_PHASE_SYNC_CH1_FIFO_SEL_SFT 11 +#define UL3_PHASE_SYNC_CH1_FIFO_SEL_MASK 0x1 +#define UL3_PHASE_SYNC_CH1_FIFO_SEL_MASK_SFT (0x1 << 11) +#define UL2_PHASE_SYNC_CH1_FIFO_SEL_SFT 10 +#define UL2_PHASE_SYNC_CH1_FIFO_SEL_MASK 0x1 +#define UL2_PHASE_SYNC_CH1_FIFO_SEL_MASK_SFT (0x1 << 10) +#define UL1_PHASE_SYNC_CH1_FIFO_SEL_SFT 9 +#define UL1_PHASE_SYNC_CH1_FIFO_SEL_MASK 0x1 +#define UL1_PHASE_SYNC_CH1_FIFO_SEL_MASK_SFT (0x1 << 9) +#define UL0_PHASE_SYNC_CH1_FIFO_SEL_SFT 8 +#define UL0_PHASE_SYNC_CH1_FIFO_SEL_MASK 0x1 +#define UL0_PHASE_SYNC_CH1_FIFO_SEL_MASK_SFT (0x1 << 8) +#define UL_PHASE_SYNC_SOFT_RST_EN_2_ON_SFT 5 +#define UL_PHASE_SYNC_SOFT_RST_EN_2_ON_MASK 0x1 +#define UL_PHASE_SYNC_SOFT_RST_EN_2_ON_MASK_SFT (0x1 << 5) +#define UL_PHASE_SYNC_SOFT_RST_EN_1_ON_SFT 4 +#define UL_PHASE_SYNC_SOFT_RST_EN_1_ON_MASK 0x1 +#define UL_PHASE_SYNC_SOFT_RST_EN_1_ON_MASK_SFT (0x1 << 4) +#define UL_PHASE_SYNC_SOFT_RST_EN_0_ON_SFT 3 +#define UL_PHASE_SYNC_SOFT_RST_EN_0_ON_MASK 0x1 +#define UL_PHASE_SYNC_SOFT_RST_EN_0_ON_MASK_SFT (0x1 << 3) +#define UL_PHASE_SYNC_SOFT_RST_2_ON_SFT 2 +#define UL_PHASE_SYNC_SOFT_RST_2_ON_MASK 0x1 +#define UL_PHASE_SYNC_SOFT_RST_2_ON_MASK_SFT (0x1 << 2) +#define UL_PHASE_SYNC_SOFT_RST_1_ON_SFT 1 +#define UL_PHASE_SYNC_SOFT_RST_1_ON_MASK 0x1 +#define UL_PHASE_SYNC_SOFT_RST_1_ON_MASK_SFT (0x1 << 1) +#define UL_PHASE_SYNC_SOFT_RST_0_ON_SFT 0 +#define UL_PHASE_SYNC_SOFT_RST_0_ON_MASK 0x1 +#define UL_PHASE_SYNC_SOFT_RST_0_ON_MASK_SFT (0x1 << 0) + +/* AFE_MTKAIF_IPM_VER_MON */ +#define RG_MTKAIF_IPM_VER_MON_SFT 0 +#define RG_MTKAIF_IPM_VER_MON_MASK 0xffffffff +#define RG_MTKAIF_IPM_VER_MON_MASK_SFT (0xffffffff << 0) + +/* AFE_MTKAIF_MON_SEL */ +#define RG_MTKAIF_MON_SEL_SFT 0 +#define RG_MTKAIF_MON_SEL_MASK 0xff +#define RG_MTKAIF_MON_SEL_MASK_SFT (0xff << 0) + +/* AFE_MTKAIF_MON */ +#define RG_MTKAIF_MON_SFT 0 +#define RG_MTKAIF_MON_MASK 0xffffffff +#define RG_MTKAIF_MON_MASK_SFT (0xffffffff << 0) + +/* AFE_MTKAIF0_CFG0 */ +#define RG_MTKAIF0_RXIF_CLKINV_SFT 31 +#define RG_MTKAIF0_RXIF_CLKINV_MASK 0x1 +#define RG_MTKAIF0_RXIF_CLKINV_MASK_SFT (0x1 << 31) +#define RG_MTKAIF0_RXIF_BYPASS_SRC_SFT 17 +#define RG_MTKAIF0_RXIF_BYPASS_SRC_MASK 0x1 +#define RG_MTKAIF0_RXIF_BYPASS_SRC_MASK_SFT (0x1 << 17) +#define RG_MTKAIF0_RXIF_PROTOCOL2_SFT 16 +#define RG_MTKAIF0_RXIF_PROTOCOL2_MASK 0x1 +#define RG_MTKAIF0_RXIF_PROTOCOL2_MASK_SFT (0x1 << 16) +#define RG_MTKAIF0_TXIF_NLE_DEBUG_SFT 8 +#define RG_MTKAIF0_TXIF_NLE_DEBUG_MASK 0x1 +#define RG_MTKAIF0_TXIF_NLE_DEBUG_MASK_SFT (0x1 << 8) +#define RG_MTKAIF0_TXIF_BYPASS_SRC_SFT 5 +#define RG_MTKAIF0_TXIF_BYPASS_SRC_MASK 0x1 +#define RG_MTKAIF0_TXIF_BYPASS_SRC_MASK_SFT (0x1 << 5) +#define RG_MTKAIF0_TXIF_PROTOCOL2_SFT 4 +#define RG_MTKAIF0_TXIF_PROTOCOL2_MASK 0x1 +#define RG_MTKAIF0_TXIF_PROTOCOL2_MASK_SFT (0x1 << 4) +#define RG_MTKAIF0_TXIF_8TO5_SFT 2 +#define RG_MTKAIF0_TXIF_8TO5_MASK 0x1 +#define RG_MTKAIF0_TXIF_8TO5_MASK_SFT (0x1 << 2) +#define RG_MTKAIF0_RXIF_8TO5_SFT 1 +#define RG_MTKAIF0_RXIF_8TO5_MASK 0x1 +#define RG_MTKAIF0_RXIF_8TO5_MASK_SFT (0x1 << 1) +#define RG_MTKAIF0_TX2RX_LOOPBACK1_SFT 0 +#define RG_MTKAIF0_TX2RX_LOOPBACK1_MASK 0x1 +#define RG_MTKAIF0_TX2RX_LOOPBACK1_MASK_SFT (0x1 << 0) + +/* AFE_MTKAIF0_TX_CFG0 */ +#define RG_MTKAIF0_TXIF_NLE_FIFO_SWAP_SFT 23 +#define RG_MTKAIF0_TXIF_NLE_FIFO_SWAP_MASK 0x1 +#define RG_MTKAIF0_TXIF_NLE_FIFO_SWAP_MASK_SFT (0x1 << 23) +#define RG_MTKAIF0_TXIF_NLE_FIFO_RSP_SFT 20 +#define RG_MTKAIF0_TXIF_NLE_FIFO_RSP_MASK 0x7 +#define RG_MTKAIF0_TXIF_NLE_FIFO_RSP_MASK_SFT (0x7 << 20) +#define RG_MTKAIF0_TXIF_FIFO_SWAP_SFT 15 +#define RG_MTKAIF0_TXIF_FIFO_SWAP_MASK 0x1 +#define RG_MTKAIF0_TXIF_FIFO_SWAP_MASK_SFT (0x1 << 15) +#define RG_MTKAIF0_TXIF_FIFO_RSP_SFT 12 +#define RG_MTKAIF0_TXIF_FIFO_RSP_MASK 0x7 +#define RG_MTKAIF0_TXIF_FIFO_RSP_MASK_SFT (0x7 << 12) +#define RG_MTKAIF0_TXIF_SYNC_WORD1_SFT 4 +#define RG_MTKAIF0_TXIF_SYNC_WORD1_MASK 0x7 +#define RG_MTKAIF0_TXIF_SYNC_WORD1_MASK_SFT (0x7 << 4) +#define RG_MTKAIF0_TXIF_SYNC_WORD0_SFT 0 +#define RG_MTKAIF0_TXIF_SYNC_WORD0_MASK 0x7 +#define RG_MTKAIF0_TXIF_SYNC_WORD0_MASK_SFT (0x7 << 0) + +/* AFE_MTKAIF0_RX_CFG0 */ +#define RG_MTKAIF0_RXIF_VOICE_MODE_SFT 20 +#define RG_MTKAIF0_RXIF_VOICE_MODE_MASK 0xf +#define RG_MTKAIF0_RXIF_VOICE_MODE_MASK_SFT (0xf << 20) +#define RG_MTKAIF0_RXIF_DETECT_ON_SFT 16 +#define RG_MTKAIF0_RXIF_DETECT_ON_MASK 0x1 +#define RG_MTKAIF0_RXIF_DETECT_ON_MASK_SFT (0x1 << 16) +#define RG_MTKAIF0_RXIF_DATA_BIT_SFT 8 +#define RG_MTKAIF0_RXIF_DATA_BIT_MASK 0x7 +#define RG_MTKAIF0_RXIF_DATA_BIT_MASK_SFT (0x7 << 8) +#define RG_MTKAIF0_RXIF_FIFO_RSP_SFT 4 +#define RG_MTKAIF0_RXIF_FIFO_RSP_MASK 0x7 +#define RG_MTKAIF0_RXIF_FIFO_RSP_MASK_SFT (0x7 << 4) +#define RG_MTKAIF0_RXIF_DATA_MODE_SFT 0 +#define RG_MTKAIF0_RXIF_DATA_MODE_MASK 0x1 +#define RG_MTKAIF0_RXIF_DATA_MODE_MASK_SFT (0x1 << 0) + +/* AFE_MTKAIF0_RX_CFG1 */ +#define RG_MTKAIF0_RXIF_CLEAR_SYNC_FAIL_SFT 28 +#define RG_MTKAIF0_RXIF_CLEAR_SYNC_FAIL_MASK 0x1 +#define RG_MTKAIF0_RXIF_CLEAR_SYNC_FAIL_MASK_SFT (0x1 << 28) +#define RG_MTKAIF0_RXIF_SYNC_CNT_TABLE_SFT 16 +#define RG_MTKAIF0_RXIF_SYNC_CNT_TABLE_MASK 0xfff +#define RG_MTKAIF0_RXIF_SYNC_CNT_TABLE_MASK_SFT (0xfff << 16) +#define RG_MTKAIF0_RXIF_SYNC_SEARCH_TABLE_SFT 12 +#define RG_MTKAIF0_RXIF_SYNC_SEARCH_TABLE_MASK 0xf +#define RG_MTKAIF0_RXIF_SYNC_SEARCH_TABLE_MASK_SFT (0xf << 12) +#define RG_MTKAIF0_RXIF_INVALID_SYNC_CHECK_ROUND_SFT 8 +#define RG_MTKAIF0_RXIF_INVALID_SYNC_CHECK_ROUND_MASK 0xf +#define RG_MTKAIF0_RXIF_INVALID_SYNC_CHECK_ROUND_MASK_SFT (0xf << 8) +#define RG_MTKAIF0_RXIF_SYNC_CHECK_ROUND_SFT 4 +#define RG_MTKAIF0_RXIF_SYNC_CHECK_ROUND_MASK 0xf +#define RG_MTKAIF0_RXIF_SYNC_CHECK_ROUND_MASK_SFT (0xf << 4) + +/* AFE_MTKAIF0_RX_CFG2 */ +#define RG_MTKAIF0_RXIF_SYNC_WORD1_DISABLE_SFT 27 +#define RG_MTKAIF0_RXIF_SYNC_WORD1_DISABLE_MASK 0x1 +#define RG_MTKAIF0_RXIF_SYNC_WORD1_DISABLE_MASK_SFT (0x1 << 27) +#define RG_MTKAIF0_RXIF_SYNC_WORD1_SFT 24 +#define RG_MTKAIF0_RXIF_SYNC_WORD1_MASK 0x7 +#define RG_MTKAIF0_RXIF_SYNC_WORD1_MASK_SFT (0x7 << 24) +#define RG_MTKAIF0_RXIF_SYNC_WORD0_DISABLE_SFT 23 +#define RG_MTKAIF0_RXIF_SYNC_WORD0_DISABLE_MASK 0x1 +#define RG_MTKAIF0_RXIF_SYNC_WORD0_DISABLE_MASK_SFT (0x1 << 23) +#define RG_MTKAIF0_RXIF_SYNC_WORD0_SFT 20 +#define RG_MTKAIF0_RXIF_SYNC_WORD0_MASK 0x7 +#define RG_MTKAIF0_RXIF_SYNC_WORD0_MASK_SFT (0x7 << 20) +#define RG_MTKAIF0_RXIF_DELAY_CYCLE_SFT 12 +#define RG_MTKAIF0_RXIF_DELAY_CYCLE_MASK 0xf +#define RG_MTKAIF0_RXIF_DELAY_CYCLE_MASK_SFT (0xf << 12) +#define RG_MTKAIF0_RXIF_DELAY_DATA_SFT 8 +#define RG_MTKAIF0_RXIF_DELAY_DATA_MASK 0x1 +#define RG_MTKAIF0_RXIF_DELAY_DATA_MASK_SFT (0x1 << 8) + +/* AFE_MTKAIF1_CFG0 */ +#define RG_MTKAIF1_RXIF_CLKINV_ADC_SFT 31 +#define RG_MTKAIF1_RXIF_CLKINV_ADC_MASK 0x1 +#define RG_MTKAIF1_RXIF_CLKINV_ADC_MASK_SFT (0x1 << 31) +#define RG_MTKAIF1_RXIF_BYPASS_SRC_SFT 17 +#define RG_MTKAIF1_RXIF_BYPASS_SRC_MASK 0x1 +#define RG_MTKAIF1_RXIF_BYPASS_SRC_MASK_SFT (0x1 << 17) +#define RG_MTKAIF1_RXIF_PROTOCOL2_SFT 16 +#define RG_MTKAIF1_RXIF_PROTOCOL2_MASK 0x1 +#define RG_MTKAIF1_RXIF_PROTOCOL2_MASK_SFT (0x1 << 16) +#define RG_MTKAIF1_TXIF_NLE_DEBUG_SFT 8 +#define RG_MTKAIF1_TXIF_NLE_DEBUG_MASK 0x1 +#define RG_MTKAIF1_TXIF_NLE_DEBUG_MASK_SFT (0x1 << 8) +#define RG_MTKAIF1_TXIF_BYPASS_SRC_SFT 5 +#define RG_MTKAIF1_TXIF_BYPASS_SRC_MASK 0x1 +#define RG_MTKAIF1_TXIF_BYPASS_SRC_MASK_SFT (0x1 << 5) +#define RG_MTKAIF1_TXIF_PROTOCOL2_SFT 4 +#define RG_MTKAIF1_TXIF_PROTOCOL2_MASK 0x1 +#define RG_MTKAIF1_TXIF_PROTOCOL2_MASK_SFT (0x1 << 4) +#define RG_MTKAIF1_TXIF_8TO5_SFT 2 +#define RG_MTKAIF1_TXIF_8TO5_MASK 0x1 +#define RG_MTKAIF1_TXIF_8TO5_MASK_SFT (0x1 << 2) +#define RG_MTKAIF1_RXIF_8TO5_SFT 1 +#define RG_MTKAIF1_RXIF_8TO5_MASK 0x1 +#define RG_MTKAIF1_RXIF_8TO5_MASK_SFT (0x1 << 1) +#define RG_MTKAIF1_IF_LOOPBACK1_SFT 0 +#define RG_MTKAIF1_IF_LOOPBACK1_MASK 0x1 +#define RG_MTKAIF1_IF_LOOPBACK1_MASK_SFT (0x1 << 0) + +/* AFE_MTKAIF1_TX_CFG0 */ +#define RG_MTKAIF1_TXIF_NLE_FIFO_SWAP_SFT 23 +#define RG_MTKAIF1_TXIF_NLE_FIFO_SWAP_MASK 0x1 +#define RG_MTKAIF1_TXIF_NLE_FIFO_SWAP_MASK_SFT (0x1 << 23) +#define RG_MTKAIF1_TXIF_NLE_FIFO_RSP_SFT 20 +#define RG_MTKAIF1_TXIF_NLE_FIFO_RSP_MASK 0x7 +#define RG_MTKAIF1_TXIF_NLE_FIFO_RSP_MASK_SFT (0x7 << 20) +#define RG_MTKAIF1_TXIF_FIFO_SWAP_SFT 15 +#define RG_MTKAIF1_TXIF_FIFO_SWAP_MASK 0x1 +#define RG_MTKAIF1_TXIF_FIFO_SWAP_MASK_SFT (0x1 << 15) +#define RG_MTKAIF1_TXIF_FIFO_RSP_SFT 12 +#define RG_MTKAIF1_TXIF_FIFO_RSP_MASK 0x7 +#define RG_MTKAIF1_TXIF_FIFO_RSP_MASK_SFT (0x7 << 12) +#define RG_MTKAIF1_TXIF_SYNC_WORD1_SFT 4 +#define RG_MTKAIF1_TXIF_SYNC_WORD1_MASK 0x7 +#define RG_MTKAIF1_TXIF_SYNC_WORD1_MASK_SFT (0x7 << 4) +#define RG_MTKAIF1_TXIF_SYNC_WORD0_SFT 0 +#define RG_MTKAIF1_TXIF_SYNC_WORD0_MASK 0x7 +#define RG_MTKAIF1_TXIF_SYNC_WORD0_MASK_SFT (0x7 << 0) + +/* AFE_MTKAIF1_RX_CFG0 */ +#define RG_MTKAIF1_RXIF_VOICE_MODE_SFT 20 +#define RG_MTKAIF1_RXIF_VOICE_MODE_MASK 0xf +#define RG_MTKAIF1_RXIF_VOICE_MODE_MASK_SFT (0xf << 20) +#define RG_MTKAIF1_RXIF_DETECT_ON_SFT 16 +#define RG_MTKAIF1_RXIF_DETECT_ON_MASK 0x1 +#define RG_MTKAIF1_RXIF_DETECT_ON_MASK_SFT (0x1 << 16) +#define RG_MTKAIF1_RXIF_DATA_BIT_SFT 8 +#define RG_MTKAIF1_RXIF_DATA_BIT_MASK 0x7 +#define RG_MTKAIF1_RXIF_DATA_BIT_MASK_SFT (0x7 << 8) +#define RG_MTKAIF1_RXIF_FIFO_RSP_SFT 4 +#define RG_MTKAIF1_RXIF_FIFO_RSP_MASK 0x7 +#define RG_MTKAIF1_RXIF_FIFO_RSP_MASK_SFT (0x7 << 4) +#define RG_MTKAIF1_RXIF_DATA_MODE_SFT 0 +#define RG_MTKAIF1_RXIF_DATA_MODE_MASK 0x1 +#define RG_MTKAIF1_RXIF_DATA_MODE_MASK_SFT (0x1 << 0) + +/* AFE_MTKAIF1_RX_CFG1 */ +#define RG_MTKAIF1_RXIF_CLEAR_SYNC_FAIL_SFT 28 +#define RG_MTKAIF1_RXIF_CLEAR_SYNC_FAIL_MASK 0x1 +#define RG_MTKAIF1_RXIF_CLEAR_SYNC_FAIL_MASK_SFT (0x1 << 28) +#define RG_MTKAIF1_RXIF_SYNC_CNT_TABLE_SFT 16 +#define RG_MTKAIF1_RXIF_SYNC_CNT_TABLE_MASK 0xfff +#define RG_MTKAIF1_RXIF_SYNC_CNT_TABLE_MASK_SFT (0xfff << 16) +#define RG_MTKAIF1_RXIF_SYNC_SEARCH_TABLE_SFT 12 +#define RG_MTKAIF1_RXIF_SYNC_SEARCH_TABLE_MASK 0xf +#define RG_MTKAIF1_RXIF_SYNC_SEARCH_TABLE_MASK_SFT (0xf << 12) +#define RG_MTKAIF1_RXIF_INVALID_SYNC_CHECK_ROUND_SFT 8 +#define RG_MTKAIF1_RXIF_INVALID_SYNC_CHECK_ROUND_MASK 0xf +#define RG_MTKAIF1_RXIF_INVALID_SYNC_CHECK_ROUND_MASK_SFT (0xf << 8) +#define RG_MTKAIF1_RXIF_SYNC_CHECK_ROUND_SFT 4 +#define RG_MTKAIF1_RXIF_SYNC_CHECK_ROUND_MASK 0xf +#define RG_MTKAIF1_RXIF_SYNC_CHECK_ROUND_MASK_SFT (0xf << 4) + +/* AFE_MTKAIF1_RX_CFG2 */ +#define RG_MTKAIF1_RXIF_SYNC_WORD1_DISABLE_SFT 27 +#define RG_MTKAIF1_RXIF_SYNC_WORD1_DISABLE_MASK 0x1 +#define RG_MTKAIF1_RXIF_SYNC_WORD1_DISABLE_MASK_SFT (0x1 << 27) +#define RG_MTKAIF1_RXIF_SYNC_WORD1_SFT 24 +#define RG_MTKAIF1_RXIF_SYNC_WORD1_MASK 0x7 +#define RG_MTKAIF1_RXIF_SYNC_WORD1_MASK_SFT (0x7 << 24) +#define RG_MTKAIF1_RXIF_SYNC_WORD0_DISABLE_SFT 23 +#define RG_MTKAIF1_RXIF_SYNC_WORD0_DISABLE_MASK 0x1 +#define RG_MTKAIF1_RXIF_SYNC_WORD0_DISABLE_MASK_SFT (0x1 << 23) +#define RG_MTKAIF1_RXIF_SYNC_WORD0_SFT 20 +#define RG_MTKAIF1_RXIF_SYNC_WORD0_MASK 0x7 +#define RG_MTKAIF1_RXIF_SYNC_WORD0_MASK_SFT (0x7 << 20) +#define RG_MTKAIF1_RXIF_DELAY_CYCLE_SFT 12 +#define RG_MTKAIF1_RXIF_DELAY_CYCLE_MASK 0xf +#define RG_MTKAIF1_RXIF_DELAY_CYCLE_MASK_SFT (0xf << 12) +#define RG_MTKAIF1_RXIF_DELAY_DATA_SFT 8 +#define RG_MTKAIF1_RXIF_DELAY_DATA_MASK 0x1 +#define RG_MTKAIF1_RXIF_DELAY_DATA_MASK_SFT (0x1 << 8) + +/* AFE_AUD_PAD_TOP_CFG0 */ +#define AUD_PAD_TOP_FIFO_RSP_SFT 4 +#define AUD_PAD_TOP_FIFO_RSP_MASK 0xf +#define AUD_PAD_TOP_FIFO_RSP_MASK_SFT (0xf << 4) +#define RG_RX_PROTOCOL2_SFT 3 +#define RG_RX_PROTOCOL2_MASK 0x1 +#define RG_RX_PROTOCOL2_MASK_SFT (0x1 << 3) +#define RG_RX_FIFO_ON_SFT 0 +#define RG_RX_FIFO_ON_MASK 0x1 +#define RG_RX_FIFO_ON_MASK_SFT (0x1 << 0) + +/* AFE_AUD_PAD_TOP_MON */ +#define AUD_PAD_TOP_MON_SFT 0 +#define AUD_PAD_TOP_MON_MASK 0xffff +#define AUD_PAD_TOP_MON_MASK_SFT (0xffff << 0) + +/* AFE_ADDA_MTKAIFV4_TX_CFG0 */ +#define MTKAIFV4_TXIF_EN_SEL_SFT 12 +#define MTKAIFV4_TXIF_EN_SEL_MASK 0x1 +#define MTKAIFV4_TXIF_EN_SEL_MASK_SFT (0x1 << 12) +#define MTKAIFV4_TXIF_V4_SFT 11 +#define MTKAIFV4_TXIF_V4_MASK 0x1 +#define MTKAIFV4_TXIF_V4_MASK_SFT (0x1 << 11) +#define MTKAIFV4_ADDA6_OUT_EN_SEL_SFT 10 +#define MTKAIFV4_ADDA6_OUT_EN_SEL_MASK 0x1 +#define MTKAIFV4_ADDA6_OUT_EN_SEL_MASK_SFT (0x1 << 10) +#define MTKAIFV4_ADDA_OUT_EN_SEL_SFT 9 +#define MTKAIFV4_ADDA_OUT_EN_SEL_MASK 0x1 +#define MTKAIFV4_ADDA_OUT_EN_SEL_MASK_SFT (0x1 << 9) +#define MTKAIFV4_TXIF_INPUT_MODE_SFT 4 +#define MTKAIFV4_TXIF_INPUT_MODE_MASK 0x1f +#define MTKAIFV4_TXIF_INPUT_MODE_MASK_SFT (0x1f << 4) +#define MTKAIFV4_TXIF_FOUR_CHANNEL_SFT 1 +#define MTKAIFV4_TXIF_FOUR_CHANNEL_MASK 0x1 +#define MTKAIFV4_TXIF_FOUR_CHANNEL_MASK_SFT (0x1 << 1) +#define MTKAIFV4_TXIF_AFE_ON_SFT 0 +#define MTKAIFV4_TXIF_AFE_ON_MASK 0x1 +#define MTKAIFV4_TXIF_AFE_ON_MASK_SFT (0x1 << 0) + +/* AFE_ADDA6_MTKAIFV4_TX_CFG0 */ +#define ADDA6_MTKAIFV4_TXIF_EN_SEL_SFT 12 +#define ADDA6_MTKAIFV4_TXIF_EN_SEL_MASK 0x1 +#define ADDA6_MTKAIFV4_TXIF_EN_SEL_MASK_SFT (0x1 << 12) +#define ADDA6_MTKAIFV4_TXIF_INPUT_MODE_SFT 4 +#define ADDA6_MTKAIFV4_TXIF_INPUT_MODE_MASK 0x1f +#define ADDA6_MTKAIFV4_TXIF_INPUT_MODE_MASK_SFT (0x1f << 4) +#define ADDA6_MTKAIFV4_TXIF_FOUR_CHANNEL_SFT 1 +#define ADDA6_MTKAIFV4_TXIF_FOUR_CHANNEL_MASK 0x1 +#define ADDA6_MTKAIFV4_TXIF_FOUR_CHANNEL_MASK_SFT (0x1 << 1) +#define ADDA6_MTKAIFV4_TXIF_AFE_ON_SFT 0 +#define ADDA6_MTKAIFV4_TXIF_AFE_ON_MASK 0x1 +#define ADDA6_MTKAIFV4_TXIF_AFE_ON_MASK_SFT (0x1 << 0) + +/* AFE_ADDA_MTKAIFV4_RX_CFG0 */ +#define MTKAIFV4_RXIF_CLKINV_SFT 31 +#define MTKAIFV4_RXIF_CLKINV_MASK 0x1 +#define MTKAIFV4_RXIF_CLKINV_MASK_SFT (0x1 << 31) +#define MTKAIFV4_RXIF_LOOPBACK_MODE_SFT 28 +#define MTKAIFV4_RXIF_LOOPBACK_MODE_MASK 0x1 +#define MTKAIFV4_RXIF_LOOPBACK_MODE_MASK_SFT (0x1 << 28) +#define MTKAIFV4_UL_CH7CH8_IN_EN_SEL_SFT 19 +#define MTKAIFV4_UL_CH7CH8_IN_EN_SEL_MASK 0x1 +#define MTKAIFV4_UL_CH7CH8_IN_EN_SEL_MASK_SFT (0x1 << 19) +#define MTKAIFV4_UL_CH5CH6_IN_EN_SEL_SFT 18 +#define MTKAIFV4_UL_CH5CH6_IN_EN_SEL_MASK 0x1 +#define MTKAIFV4_UL_CH5CH6_IN_EN_SEL_MASK_SFT (0x1 << 18) +#define MTKAIFV4_UL_CH3CH4_IN_EN_SEL_SFT 17 +#define MTKAIFV4_UL_CH3CH4_IN_EN_SEL_MASK 0x1 +#define MTKAIFV4_UL_CH3CH4_IN_EN_SEL_MASK_SFT (0x1 << 17) +#define MTKAIFV4_UL_CH1CH2_IN_EN_SEL_SFT 16 +#define MTKAIFV4_UL_CH1CH2_IN_EN_SEL_MASK 0x1 +#define MTKAIFV4_UL_CH1CH2_IN_EN_SEL_MASK_SFT (0x1 << 16) +#define MTKAIFV4_RXIF_EN_SEL_SFT 12 +#define MTKAIFV4_RXIF_EN_SEL_MASK 0x1 +#define MTKAIFV4_RXIF_EN_SEL_MASK_SFT (0x1 << 12) +#define MTKAIFV4_RXIF_INPUT_MODE_SFT 4 +#define MTKAIFV4_RXIF_INPUT_MODE_MASK 0x1f +#define MTKAIFV4_RXIF_INPUT_MODE_MASK_SFT (0x1f << 4) +#define MTKAIFV4_RXIF_FOUR_CHANNEL_SFT 1 +#define MTKAIFV4_RXIF_FOUR_CHANNEL_MASK 0x1 +#define MTKAIFV4_RXIF_FOUR_CHANNEL_MASK_SFT (0x1 << 1) +#define MTKAIFV4_RXIF_AFE_ON_SFT 0 +#define MTKAIFV4_RXIF_AFE_ON_MASK 0x1 +#define MTKAIFV4_RXIF_AFE_ON_MASK_SFT (0x1 << 0) + +/* AFE_ADDA_MTKAIFV4_RX_CFG1 */ +#define MTKAIFV4_RXIF_SYNC_CNT_TABLE_SFT 17 +#define MTKAIFV4_RXIF_SYNC_CNT_TABLE_MASK 0xfff +#define MTKAIFV4_RXIF_SYNC_CNT_TABLE_MASK_SFT (0xfff << 17) +#define MTKAIFV4_RXIF_SYNC_SEARCH_TABLE_SFT 12 +#define MTKAIFV4_RXIF_SYNC_SEARCH_TABLE_MASK 0x1f +#define MTKAIFV4_RXIF_SYNC_SEARCH_TABLE_MASK_SFT (0x1f << 12) +#define MTKAIFV4_RXIF_INVAILD_SYNC_CHECK_ROUND_SFT 8 +#define MTKAIFV4_RXIF_INVAILD_SYNC_CHECK_ROUND_MASK 0xf +#define MTKAIFV4_RXIF_INVAILD_SYNC_CHECK_ROUND_MASK_SFT (0xf << 8) +#define MTKAIFV4_RXIF_SYNC_CHECK_ROUND_SFT 4 +#define MTKAIFV4_RXIF_SYNC_CHECK_ROUND_MASK 0xf +#define MTKAIFV4_RXIF_SYNC_CHECK_ROUND_MASK_SFT (0xf << 4) +#define MTKAIFV4_RXIF_FIFO_RSP_SFT 1 +#define MTKAIFV4_RXIF_FIFO_RSP_MASK 0x7 +#define MTKAIFV4_RXIF_FIFO_RSP_MASK_SFT (0x7 << 1) +#define MTKAIFV4_RXIF_SELF_DEFINE_TABLE_SFT 0 +#define MTKAIFV4_RXIF_SELF_DEFINE_TABLE_MASK 0x1 +#define MTKAIFV4_RXIF_SELF_DEFINE_TABLE_MASK_SFT (0x1 << 0) + +/* AFE_ADDA6_MTKAIFV4_RX_CFG0 */ +#define ADDA6_MTKAIFV4_RXIF_CLKINV_SFT 31 +#define ADDA6_MTKAIFV4_RXIF_CLKINV_MASK 0x1 +#define ADDA6_MTKAIFV4_RXIF_CLKINV_MASK_SFT (0x1 << 31) +#define ADDA6_MTKAIFV4_RXIF_LOOPBACK_MODE_SFT 28 +#define ADDA6_MTKAIFV4_RXIF_LOOPBACK_MODE_MASK 0x1 +#define ADDA6_MTKAIFV4_RXIF_LOOPBACK_MODE_MASK_SFT (0x1 << 28) +#define ADDA6_MTKAIFV4_RXIF_EN_SEL_SFT 12 +#define ADDA6_MTKAIFV4_RXIF_EN_SEL_MASK 0x1 +#define ADDA6_MTKAIFV4_RXIF_EN_SEL_MASK_SFT (0x1 << 12) +#define ADDA6_MTKAIFV4_RXIF_INPUT_MODE_SFT 4 +#define ADDA6_MTKAIFV4_RXIF_INPUT_MODE_MASK 0x1f +#define ADDA6_MTKAIFV4_RXIF_INPUT_MODE_MASK_SFT (0x1f << 4) +#define ADDA6_MTKAIFV4_RXIF_FOUR_CHANNEL_SFT 1 +#define ADDA6_MTKAIFV4_RXIF_FOUR_CHANNEL_MASK 0x1 +#define ADDA6_MTKAIFV4_RXIF_FOUR_CHANNEL_MASK_SFT (0x1 << 1) +#define ADDA6_MTKAIFV4_RXIF_AFE_ON_SFT 0 +#define ADDA6_MTKAIFV4_RXIF_AFE_ON_MASK 0x1 +#define ADDA6_MTKAIFV4_RXIF_AFE_ON_MASK_SFT (0x1 << 0) + +/* AFE_ADDA6_MTKAIFV4_RX_CFG1 */ +#define ADDA6_MTKAIFV4_RXIF_SYNC_CNT_TABLE_SFT 17 +#define ADDA6_MTKAIFV4_RXIF_SYNC_CNT_TABLE_MASK 0xfff +#define ADDA6_MTKAIFV4_RXIF_SYNC_CNT_TABLE_MASK_SFT (0xfff << 17) +#define ADDA6_MTKAIFV4_RXIF_SYNC_SEARCH_TABLE_SFT 12 +#define ADDA6_MTKAIFV4_RXIF_SYNC_SEARCH_TABLE_MASK 0x1f +#define ADDA6_MTKAIFV4_RXIF_SYNC_SEARCH_TABLE_MASK_SFT (0x1f << 12) +#define ADDA6_MTKAIFV4_RXIF_INVAILD_SYNC_CHECK_ROUND_SFT 8 +#define ADDA6_MTKAIFV4_RXIF_INVAILD_SYNC_CHECK_ROUND_MASK 0xf +#define ADDA6_MTKAIFV4_RXIF_INVAILD_SYNC_CHECK_ROUND_MASK_SFT (0xf << 8) +#define ADDA6_MTKAIFV4_RXIF_SYNC_CHECK_ROUND_SFT 4 +#define ADDA6_MTKAIFV4_RXIF_SYNC_CHECK_ROUND_MASK 0xf +#define ADDA6_MTKAIFV4_RXIF_SYNC_CHECK_ROUND_MASK_SFT (0xf << 4) +#define ADDA6_MTKAIFV4_RXIF_FIFO_RSP_SFT 1 +#define ADDA6_MTKAIFV4_RXIF_FIFO_RSP_MASK 0x7 +#define ADDA6_MTKAIFV4_RXIF_FIFO_RSP_MASK_SFT (0x7 << 1) +#define ADDA6_MTKAIFV4_RXIF_SELF_DEFINE_TABLE_SFT 0 +#define ADDA6_MTKAIFV4_RXIF_SELF_DEFINE_TABLE_MASK 0x1 +#define ADDA6_MTKAIFV4_RXIF_SELF_DEFINE_TABLE_MASK_SFT (0x1 << 0) + +/* AFE_ADDA_MTKAIFV4_TX_SYNCWORD_CFG */ +#define ADDA6_MTKAIFV4_TXIF_SYNCWORD_SFT 16 +#define ADDA6_MTKAIFV4_TXIF_SYNCWORD_MASK 0xffff +#define ADDA6_MTKAIFV4_TXIF_SYNCWORD_MASK_SFT (0xffff << 16) +#define ADDA_MTKAIFV4_TXIF_SYNCWORD_SFT 0 +#define ADDA_MTKAIFV4_TXIF_SYNCWORD_MASK 0xffff +#define ADDA_MTKAIFV4_TXIF_SYNCWORD_MASK_SFT (0xffff << 0) + +/* AFE_ADDA_MTKAIFV4_RX_SYNCWORD_CFG */ +#define ADDA6_MTKAIFV4_RXIF_SYNCWORD_SFT 16 +#define ADDA6_MTKAIFV4_RXIF_SYNCWORD_MASK 0xffff +#define ADDA6_MTKAIFV4_RXIF_SYNCWORD_MASK_SFT (0xffff << 16) +#define ADDA_MTKAIFV4_RXIF_SYNCWORD_SFT 0 +#define ADDA_MTKAIFV4_RXIF_SYNCWORD_MASK 0xffff +#define ADDA_MTKAIFV4_RXIF_SYNCWORD_MASK_SFT (0xffff << 0) + +/* AFE_ADDA_MTKAIFV4_MON0 */ +#define MTKAIFV4_TXIF_SDATA_OUT_SFT 23 +#define MTKAIFV4_TXIF_SDATA_OUT_MASK 0x1 +#define MTKAIFV4_TXIF_SDATA_OUT_MASK_SFT (0x1 << 23) +#define MTKAIFV4_RXIF_SDATA_IN_SFT 22 +#define MTKAIFV4_RXIF_SDATA_IN_MASK 0x1 +#define MTKAIFV4_RXIF_SDATA_IN_MASK_SFT (0x1 << 22) +#define MTKAIFV4_RXIF_SEARCH_FAIL_FLAG_SFT 21 +#define MTKAIFV4_RXIF_SEARCH_FAIL_FLAG_MASK 0x1 +#define MTKAIFV4_RXIF_SEARCH_FAIL_FLAG_MASK_SFT (0x1 << 21) +#define MTKAIFV4_RXIF_ADC_FIFO_STATUS_SFT 0 +#define MTKAIFV4_RXIF_ADC_FIFO_STATUS_MASK 0xfff +#define MTKAIFV4_RXIF_ADC_FIFO_STATUS_MASK_SFT (0xfff << 0) + +/* AFE_ADDA_MTKAIFV4_MON1 */ +#define MTKAIFV4_RXIF_OUT_CH4_SFT 24 +#define MTKAIFV4_RXIF_OUT_CH4_MASK 0xff +#define MTKAIFV4_RXIF_OUT_CH4_MASK_SFT (0xff << 24) +#define MTKAIFV4_RXIF_OUT_CH3_SFT 16 +#define MTKAIFV4_RXIF_OUT_CH3_MASK 0xff +#define MTKAIFV4_RXIF_OUT_CH3_MASK_SFT (0xff << 16) +#define MTKAIFV4_RXIF_OUT_CH2_SFT 8 +#define MTKAIFV4_RXIF_OUT_CH2_MASK 0xff +#define MTKAIFV4_RXIF_OUT_CH2_MASK_SFT (0xff << 8) +#define MTKAIFV4_RXIF_OUT_CH1_SFT 0 +#define MTKAIFV4_RXIF_OUT_CH1_MASK 0xff +#define MTKAIFV4_RXIF_OUT_CH1_MASK_SFT (0xff << 0) + +/* AFE_ADDA6_MTKAIFV4_MON0 */ +#define ADDA6_MTKAIFV4_TXIF_SDATA_OUT_SFT 23 +#define ADDA6_MTKAIFV4_TXIF_SDATA_OUT_MASK 0x1 +#define ADDA6_MTKAIFV4_TXIF_SDATA_OUT_MASK_SFT (0x1 << 23) +#define ADDA6_MTKAIFV4_RXIF_SDATA_IN_SFT 22 +#define ADDA6_MTKAIFV4_RXIF_SDATA_IN_MASK 0x1 +#define ADDA6_MTKAIFV4_RXIF_SDATA_IN_MASK_SFT (0x1 << 22) +#define ADDA6_MTKAIFV4_RXIF_SEARCH_FAIL_FLAG_SFT 21 +#define ADDA6_MTKAIFV4_RXIF_SEARCH_FAIL_FLAG_MASK 0x1 +#define ADDA6_MTKAIFV4_RXIF_SEARCH_FAIL_FLAG_MASK_SFT (0x1 << 21) +#define ADDA6_MTKAIFV3P3_RXIF_ADC_FIFO_STATUS_SFT 0 +#define ADDA6_MTKAIFV3P3_RXIF_ADC_FIFO_STATUS_MASK 0xfff +#define ADDA6_MTKAIFV3P3_RXIF_ADC_FIFO_STATUS_MASK_SFT (0xfff << 0) + +/* ETDM_IN0_CON0 */ +#define REG_ETDM_IN_EN_SFT 0 +#define REG_ETDM_IN_EN_MASK 0x1 +#define REG_ETDM_IN_EN_MASK_SFT (0x1 << 0) +#define REG_SYNC_MODE_SFT 1 +#define REG_SYNC_MODE_MASK 0x1 +#define REG_SYNC_MODE_MASK_SFT (0x1 << 1) +#define REG_LSB_FIRST_SFT 3 +#define REG_LSB_FIRST_MASK 0x1 +#define REG_LSB_FIRST_MASK_SFT (0x1 << 3) +#define REG_SOFT_RST_SFT 4 +#define REG_SOFT_RST_MASK 0x1 +#define REG_SOFT_RST_MASK_SFT (0x1 << 4) +#define REG_SLAVE_MODE_SFT 5 +#define REG_SLAVE_MODE_MASK 0x1 +#define REG_SLAVE_MODE_MASK_SFT (0x1 << 5) +#define REG_FMT_SFT 6 +#define REG_FMT_MASK 0x7 +#define REG_FMT_MASK_SFT (0x7 << 6) +#define REG_LRCK_EDGE_SEL_SFT 10 +#define REG_LRCK_EDGE_SEL_MASK 0x1 +#define REG_LRCK_EDGE_SEL_MASK_SFT (0x1 << 10) +#define REG_BIT_LENGTH_SFT 11 +#define REG_BIT_LENGTH_MASK 0x1f +#define REG_BIT_LENGTH_MASK_SFT (0x1f << 11) +#define REG_WORD_LENGTH_SFT 16 +#define REG_WORD_LENGTH_MASK 0x1f +#define REG_WORD_LENGTH_MASK_SFT (0x1f << 16) +#define REG_CH_NUM_SFT 23 +#define REG_CH_NUM_MASK 0x1f +#define REG_CH_NUM_MASK_SFT (0x1f << 23) +#define REG_RELATCH_1X_EN_DOMAIN_SEL_SFT 28 +#define REG_RELATCH_1X_EN_DOMAIN_SEL_MASK 0x7 +#define REG_RELATCH_1X_EN_DOMAIN_SEL_MASK_SFT (0x7 << 28) +#define REG_VALID_TOGETHER_SFT 31 +#define REG_VALID_TOGETHER_MASK 0x1 +#define REG_VALID_TOGETHER_MASK_SFT (0x1 << 31) + +/* ETDM_IN0_CON1 */ +/* ETDM_IN1_CON1 */ +/* ETDM_IN2_CON1 */ +/* ETDM_IN3_CON1 */ +/* ETDM_IN4_CON1 */ +/* ETDM_IN5_CON1 */ +/* ETDM_IN6_CON1 */ +#define REG_INITIAL_COUNT_SFT 0 +#define REG_INITIAL_COUNT_MASK 0x1f +#define REG_INITIAL_COUNT_MASK_SFT (0x1f << 0) +#define REG_INITIAL_POINT_SFT 5 +#define REG_INITIAL_POINT_MASK 0x1f +#define REG_INITIAL_POINT_MASK_SFT (0x1f << 5) +#define REG_LRCK_AUTO_OFF_SFT 10 +#define REG_LRCK_AUTO_OFF_MASK 0x1 +#define REG_LRCK_AUTO_OFF_MASK_SFT (0x1 << 10) +#define REG_BCK_AUTO_OFF_SFT 11 +#define REG_BCK_AUTO_OFF_MASK 0x1 +#define REG_BCK_AUTO_OFF_MASK_SFT (0x1 << 11) +#define REG_INITIAL_LRCK_SFT 13 +#define REG_INITIAL_LRCK_MASK 0x1 +#define REG_INITIAL_LRCK_MASK_SFT (0x1 << 13) +#define REG_NO_ALIGN_1X_EN_SFT 14 +#define REG_NO_ALIGN_1X_EN_MASK 0x1 +#define REG_NO_ALIGN_1X_EN_MASK_SFT (0x1 << 14) +#define REG_LRCK_RESET_SFT 15 +#define REG_LRCK_RESET_MASK 0x1 +#define REG_LRCK_RESET_MASK_SFT (0x1 << 15) +#define PINMUX_MCLK_CTRL_OE_SFT 16 +#define PINMUX_MCLK_CTRL_OE_MASK 0x1 +#define PINMUX_MCLK_CTRL_OE_MASK_SFT (0x1 << 16) +#define REG_OUTPUT_CR_EN_SFT 18 +#define REG_OUTPUT_CR_EN_MASK 0x1 +#define REG_OUTPUT_CR_EN_MASK_SFT (0x1 << 18) +#define REG_LR_ALIGN_SFT 19 +#define REG_LR_ALIGN_MASK 0x1 +#define REG_LR_ALIGN_MASK_SFT (0x1 << 19) +#define REG_LRCK_WIDTH_SFT 20 +#define REG_LRCK_WIDTH_MASK 0x3ff +#define REG_LRCK_WIDTH_MASK_SFT (0x3ff << 20) +#define REG_DIRECT_INPUT_MASTER_BCK_SFT 30 +#define REG_DIRECT_INPUT_MASTER_BCK_MASK 0x1 +#define REG_DIRECT_INPUT_MASTER_BCK_MASK_SFT (0x1 << 30) +#define REG_LRCK_AUTO_MODE_SFT 31 +#define REG_LRCK_AUTO_MODE_MASK 0x1 +#define REG_LRCK_AUTO_MODE_MASK_SFT (0x1 << 31) + +/* ETDM_IN0_CON2 */ +/* ETDM_IN1_CON2 */ +/* ETDM_IN2_CON2 */ +/* ETDM_IN3_CON2 */ +/* ETDM_IN4_CON2 */ +/* ETDM_IN5_CON2 */ +/* ETDM_IN6_CON2 */ +#define REG_UPDATE_POINT_SFT 0 +#define REG_UPDATE_POINT_MASK 0x1f +#define REG_UPDATE_POINT_MASK_SFT (0x1f << 0) +#define REG_UPDATE_GAP_SFT 5 +#define REG_UPDATE_GAP_MASK 0x1f +#define REG_UPDATE_GAP_MASK_SFT (0x1f << 5) +#define REG_CLOCK_SOURCE_SEL_SFT 10 +#define REG_CLOCK_SOURCE_SEL_MASK 0x7 +#define REG_CLOCK_SOURCE_SEL_MASK_SFT (0x7 << 10) +#define REG_CK_EN_SEL_AUTO_SFT 14 +#define REG_CK_EN_SEL_AUTO_MASK 0x1 +#define REG_CK_EN_SEL_AUTO_MASK_SFT (0x1 << 14) +#define REG_MULTI_IP_TOTAL_CHNUM_SFT 15 +#define REG_MULTI_IP_TOTAL_CHNUM_MASK 0x1f +#define REG_MULTI_IP_TOTAL_CHNUM_MASK_SFT (0x1f << 15) +#define REG_MASK_AUTO_SFT 20 +#define REG_MASK_AUTO_MASK 0x1 +#define REG_MASK_AUTO_MASK_SFT (0x1 << 20) +#define REG_MASK_NUM_SFT 21 +#define REG_MASK_NUM_MASK 0x1f +#define REG_MASK_NUM_MASK_SFT (0x1f << 21) +#define REG_UPDATE_POINT_AUTO_SFT 26 +#define REG_UPDATE_POINT_AUTO_MASK 0x1 +#define REG_UPDATE_POINT_AUTO_MASK_SFT (0x1 << 26) +#define REG_SDATA_DELAY_0P5T_EN_SFT 27 +#define REG_SDATA_DELAY_0P5T_EN_MASK 0x1 +#define REG_SDATA_DELAY_0P5T_EN_MASK_SFT (0x1 << 27) +#define REG_SDATA_DELAY_BCK_INV_SFT 28 +#define REG_SDATA_DELAY_BCK_INV_MASK 0x1 +#define REG_SDATA_DELAY_BCK_INV_MASK_SFT (0x1 << 28) +#define REG_LRCK_DELAY_0P5T_EN_SFT 29 +#define REG_LRCK_DELAY_0P5T_EN_MASK 0x1 +#define REG_LRCK_DELAY_0P5T_EN_MASK_SFT (0x1 << 29) +#define REG_LRCK_DELAY_BCK_INV_SFT 30 +#define REG_LRCK_DELAY_BCK_INV_MASK 0x1 +#define REG_LRCK_DELAY_BCK_INV_MASK_SFT (0x1 << 30) +#define REG_MULTI_IP_MODE_SFT 31 +#define REG_MULTI_IP_MODE_MASK 0x1 +#define REG_MULTI_IP_MODE_MASK_SFT (0x1 << 31) + +/* ETDM_IN0_CON3 */ +/* ETDM_IN1_CON3 */ +/* ETDM_IN2_CON3 */ +/* ETDM_IN3_CON3 */ +/* ETDM_IN4_CON3 */ +/* ETDM_IN5_CON3 */ +/* ETDM_IN6_CON3 */ +#define REG_DISABLE_OUT_SFT 0 +#define REG_DISABLE_OUT_MASK 0xffff +#define REG_DISABLE_OUT_MASK_SFT (0xffff << 0) +#define REG_RJ_DATA_RIGHT_ALIGN_SFT 16 +#define REG_RJ_DATA_RIGHT_ALIGN_MASK 0x1 +#define REG_RJ_DATA_RIGHT_ALIGN_MASK_SFT (0x1 << 16) +#define REG_MONITOR_SEL_SFT 17 +#define REG_MONITOR_SEL_MASK 0x3 +#define REG_MONITOR_SEL_MASK_SFT (0x3 << 17) +#define REG_CNT_UPPER_LIMIT_SFT 19 +#define REG_CNT_UPPER_LIMIT_MASK 0x3f +#define REG_CNT_UPPER_LIMIT_MASK_SFT (0x3f << 19) +#define REG_COMPACT_SAMPLE_END_DIS_SFT 25 +#define REG_COMPACT_SAMPLE_END_DIS_MASK 0x1 +#define REG_COMPACT_SAMPLE_END_DIS_MASK_SFT (0x1 << 25) +#define REG_FS_TIMING_SEL_SFT 26 +#define REG_FS_TIMING_SEL_MASK 0x1f +#define REG_FS_TIMING_SEL_MASK_SFT (0x1f << 26) +#define REG_SAMPLE_END_MODE_SFT 31 +#define REG_SAMPLE_END_MODE_MASK 0x1 +#define REG_SAMPLE_END_MODE_MASK_SFT (0x1 << 31) + +/* ETDM_IN0_CON4 */ +/* ETDM_IN1_CON4 */ +/* ETDM_IN2_CON4 */ +/* ETDM_IN3_CON4 */ +/* ETDM_IN4_CON4 */ +/* ETDM_IN5_CON4 */ +/* ETDM_IN6_CON4 */ +#define REG_ALWAYS_OPEN_1X_EN_SFT 31 +#define REG_ALWAYS_OPEN_1X_EN_MASK 0x1 +#define REG_ALWAYS_OPEN_1X_EN_MASK_SFT (0x1 << 31) +#define REG_WAIT_LAST_SAMPLE_SFT 30 +#define REG_WAIT_LAST_SAMPLE_MASK 0x1 +#define REG_WAIT_LAST_SAMPLE_MASK_SFT (0x1 << 30) +#define REG_SAMPLE_END_POINT_SFT 25 +#define REG_SAMPLE_END_POINT_MASK 0x1f +#define REG_SAMPLE_END_POINT_MASK_SFT (0x1f << 25) +#define REG_RELATCH_1X_EN_SEL_SFT 20 +#define REG_RELATCH_1X_EN_SEL_MASK 0x1f +#define REG_RELATCH_1X_EN_SEL_MASK_SFT (0x1f << 20) +#define REG_MASTER_WS_INV_SFT 19 +#define REG_MASTER_WS_INV_MASK 0x1 +#define REG_MASTER_WS_INV_MASK_SFT (0x1 << 19) +#define REG_MASTER_BCK_INV_SFT 18 +#define REG_MASTER_BCK_INV_MASK 0x1 +#define REG_MASTER_BCK_INV_MASK_SFT (0x1 << 18) +#define REG_SLAVE_LRCK_INV_SFT 17 +#define REG_SLAVE_LRCK_INV_MASK 0x1 +#define REG_SLAVE_LRCK_INV_MASK_SFT (0x1 << 17) +#define REG_SLAVE_BCK_INV_SFT 16 +#define REG_SLAVE_BCK_INV_MASK 0x1 +#define REG_SLAVE_BCK_INV_MASK_SFT (0x1 << 16) +#define REG_REPACK_CHNUM_SFT 12 +#define REG_REPACK_CHNUM_MASK 0xf +#define REG_REPACK_CHNUM_MASK_SFT (0xf << 12) +#define REG_ASYNC_RESET_SFT 11 +#define REG_ASYNC_RESET_MASK 0x1 +#define REG_ASYNC_RESET_MASK_SFT (0x1 << 11) +#define REG_REPACK_WORD_LENGTH_SFT 9 +#define REG_REPACK_WORD_LENGTH_MASK 0x3 +#define REG_REPACK_WORD_LENGTH_MASK_SFT (0x3 << 9) +#define REG_REPACK_AUTO_MODE_SFT 8 +#define REG_REPACK_AUTO_MODE_MASK 0x1 +#define REG_REPACK_AUTO_MODE_MASK_SFT (0x1 << 8) +#define REG_REPACK_MODE_SFT 0 +#define REG_REPACK_MODE_MASK 0x3f +#define REG_REPACK_MODE_MASK_SFT (0x3f << 0) + +/* ETDM_IN0_CON5 */ +/* ETDM_IN1_CON5 */ +/* ETDM_IN2_CON5 */ +/* ETDM_IN3_CON5 */ +/* ETDM_IN4_CON5 */ +/* ETDM_IN5_CON5 */ +/* ETDM_IN6_CON5 */ +#define REG_LR_SWAP_SFT 16 +#define REG_LR_SWAP_MASK 0xffff +#define REG_LR_SWAP_MASK_SFT (0xffff << 16) +#define REG_ODD_FLAG_EN_SFT 0 +#define REG_ODD_FLAG_EN_MASK 0xffff +#define REG_ODD_FLAG_EN_MASK_SFT (0xffff << 0) + +/* ETDM_IN0_CON6 */ +/* ETDM_IN1_CON6 */ +/* ETDM_IN2_CON6 */ +/* ETDM_IN3_CON6 */ +/* ETDM_IN4_CON6 */ +/* ETDM_IN5_CON6 */ +/* ETDM_IN6_CON6 */ +#define LCH_DATA_REG_SFT 0 +#define LCH_DATA_REG_MASK 0xffffffff +#define LCH_DATA_REG_MASK_SFT (0xffffffff << 0) + +/* ETDM_IN0_CON7 */ +/* ETDM_IN1_CON7 */ +/* ETDM_IN2_CON7 */ +/* ETDM_IN3_CON7 */ +/* ETDM_IN4_CON7 */ +/* ETDM_IN5_CON7 */ +/* ETDM_IN6_CON7 */ +#define RCH_DATA_REG_SFT 0 +#define RCH_DATA_REG_MASK 0xffffffff +#define RCH_DATA_REG_MASK_SFT (0xffffffff << 0) + +/* ETDM_IN0_CON8 */ +/* ETDM_IN1_CON8 */ +/* ETDM_IN2_CON8 */ +/* ETDM_IN3_CON8 */ +/* ETDM_IN4_CON8 */ +/* ETDM_IN5_CON8 */ +/* ETDM_IN6_CON8 */ +#define REG_AFIFO_THRESHOLD_SFT 29 +#define REG_AFIFO_THRESHOLD_MASK 0x3 +#define REG_AFIFO_THRESHOLD_MASK_SFT (0x3 << 29) +#define REG_CK_EN_SEL_MANUAL_SFT 16 +#define REG_CK_EN_SEL_MANUAL_MASK 0x3ff +#define REG_CK_EN_SEL_MANUAL_MASK_SFT (0x3ff << 16) +#define REG_AFIFO_SW_RESET_SFT 15 +#define REG_AFIFO_SW_RESET_MASK 0x1 +#define REG_AFIFO_SW_RESET_MASK_SFT (0x1 << 15) +#define REG_AFIFO_RESET_SEL_SFT 14 +#define REG_AFIFO_RESET_SEL_MASK 0x1 +#define REG_AFIFO_RESET_SEL_MASK_SFT (0x1 << 14) +#define REG_AFIFO_AUTO_RESET_DIS_SFT 9 +#define REG_AFIFO_AUTO_RESET_DIS_MASK 0x1 +#define REG_AFIFO_AUTO_RESET_DIS_MASK_SFT (0x1 << 9) +#define REG_ETDM_USE_AFIFO_SFT 8 +#define REG_ETDM_USE_AFIFO_MASK 0x1 +#define REG_ETDM_USE_AFIFO_MASK_SFT (0x1 << 8) +#define REG_AFIFO_CLOCK_DOMAIN_SEL_SFT 5 +#define REG_AFIFO_CLOCK_DOMAIN_SEL_MASK 0x7 +#define REG_AFIFO_CLOCK_DOMAIN_SEL_MASK_SFT (0x7 << 5) +#define REG_AFIFO_MODE_SFT 0 +#define REG_AFIFO_MODE_MASK 0x1f +#define REG_AFIFO_MODE_MASK_SFT (0x1f << 0) + +/* ETDM_IN0_CON9 */ +/* ETDM_IN1_CON9 */ +/* ETDM_IN2_CON9 */ +/* ETDM_IN3_CON9 */ +/* ETDM_IN4_CON9 */ +/* ETDM_IN5_CON9 */ +/* ETDM_IN6_CON9 */ +#define REG_OUT2LATCH_TIME_SFT 10 +#define REG_OUT2LATCH_TIME_MASK 0x1f +#define REG_OUT2LATCH_TIME_MASK_SFT (0x1f << 10) +#define REG_ALMOST_END_BIT_COUNT_SFT 5 +#define REG_ALMOST_END_BIT_COUNT_MASK 0x1f +#define REG_ALMOST_END_BIT_COUNT_MASK_SFT (0x1f << 5) +#define REG_ALMOST_END_CH_COUNT_SFT 0 +#define REG_ALMOST_END_CH_COUNT_MASK 0x1f +#define REG_ALMOST_END_CH_COUNT_MASK_SFT (0x1f << 0) + +/* ETDM_IN0_MON */ +/* ETDM_IN1_MON */ +/* ETDM_IN2_MON */ +/* ETDM_IN3_MON */ +/* ETDM_IN4_MON */ +/* ETDM_IN5_MON */ +/* ETDM_IN6_MON */ +#define LRCK_INV_SFT 30 +#define LRCK_INV_MASK 0x1 +#define LRCK_INV_MASK_SFT (0x1 << 30) +#define EN_SYNC_OUT_SFT 29 +#define EN_SYNC_OUT_MASK 0x1 +#define EN_SYNC_OUT_MASK_SFT (0x1 << 29) +#define HOPPING_EN_SYNC_OUT_PRE_SFT 28 +#define HOPPING_EN_SYNC_OUT_PRE_MASK 0x1 +#define HOPPING_EN_SYNC_OUT_PRE_MASK_SFT (0x1 << 28) +#define WFULL_SFT 27 +#define WFULL_MASK 0x1 +#define WFULL_MASK_SFT (0x1 << 27) +#define REMPTY_SFT 26 +#define REMPTY_MASK 0x1 +#define REMPTY_MASK_SFT (0x1 << 26) +#define ETDM_2X_CK_EN_SFT 25 +#define ETDM_2X_CK_EN_MASK 0x1 +#define ETDM_2X_CK_EN_MASK_SFT (0x1 << 25) +#define ETDM_1X_CK_EN_SFT 24 +#define ETDM_1X_CK_EN_MASK 0x1 +#define ETDM_1X_CK_EN_MASK_SFT (0x1 << 24) +#define SDATA0_SFT 23 +#define SDATA0_MASK 0x1 +#define SDATA0_MASK_SFT (0x1 << 23) +#define CURRENT_STATUS_SFT 21 +#define CURRENT_STATUS_MASK 0x3 +#define CURRENT_STATUS_MASK_SFT (0x3 << 21) +#define BIT_POINT_SFT 16 +#define BIT_POINT_MASK 0x1f +#define BIT_POINT_MASK_SFT (0x1f << 16) +#define BIT_CH_COUNT_SFT 10 +#define BIT_CH_COUNT_MASK 0x3f +#define BIT_CH_COUNT_MASK_SFT (0x3f << 10) +#define BIT_COUNT_SFT 5 +#define BIT_COUNT_MASK 0x1f +#define BIT_COUNT_MASK_SFT (0x1f << 5) +#define CH_COUNT_SFT 0 +#define CH_COUNT_MASK 0x1f +#define CH_COUNT_MASK_SFT (0x1f << 0) + +/* ETDM_OUT0_CON0 */ +/* ETDM_OUT1_CON0 */ +/* ETDM_OUT2_CON0 */ +/* ETDM_OUT3_CON0 */ +/* ETDM_OUT4_CON0 */ +/* ETDM_OUT5_CON0 */ +/* ETDM_OUT6_CON0 */ +#define OUT_REG_ETDM_OUT_EN_SFT 0 +#define OUT_REG_ETDM_OUT_EN_MASK 0x1 +#define OUT_REG_ETDM_OUT_EN_MASK_SFT (0x1 << 0) +#define OUT_REG_SYNC_MODE_SFT 1 +#define OUT_REG_SYNC_MODE_MASK 0x1 +#define OUT_REG_SYNC_MODE_MASK_SFT (0x1 << 1) +#define OUT_REG_LSB_FIRST_SFT 3 +#define OUT_REG_LSB_FIRST_MASK 0x1 +#define OUT_REG_LSB_FIRST_MASK_SFT (0x1 << 3) +#define OUT_REG_SOFT_RST_SFT 4 +#define OUT_REG_SOFT_RST_MASK 0x1 +#define OUT_REG_SOFT_RST_MASK_SFT (0x1 << 4) +#define OUT_REG_SLAVE_MODE_SFT 5 +#define OUT_REG_SLAVE_MODE_MASK 0x1 +#define OUT_REG_SLAVE_MODE_MASK_SFT (0x1 << 5) +#define OUT_REG_FMT_SFT 6 +#define OUT_REG_FMT_MASK 0x7 +#define OUT_REG_FMT_MASK_SFT (0x7 << 6) +#define OUT_REG_LRCK_EDGE_SEL_SFT 10 +#define OUT_REG_LRCK_EDGE_SEL_MASK 0x1 +#define OUT_REG_LRCK_EDGE_SEL_MASK_SFT (0x1 << 10) +#define OUT_REG_BIT_LENGTH_SFT 11 +#define OUT_REG_BIT_LENGTH_MASK 0x1f +#define OUT_REG_BIT_LENGTH_MASK_SFT (0x1f << 11) +#define OUT_REG_WORD_LENGTH_SFT 16 +#define OUT_REG_WORD_LENGTH_MASK 0x1f +#define OUT_REG_WORD_LENGTH_MASK_SFT (0x1f << 16) +#define OUT_REG_CH_NUM_SFT 23 +#define OUT_REG_CH_NUM_MASK 0x1f +#define OUT_REG_CH_NUM_MASK_SFT (0x1f << 23) +#define OUT_REG_RELATCH_DOMAIN_SEL_SFT 28 +#define OUT_REG_RELATCH_DOMAIN_SEL_MASK 0x7 +#define OUT_REG_RELATCH_DOMAIN_SEL_MASK_SFT (0x7 << 28) +#define OUT_REG_VALID_TOGETHER_SFT 31 +#define OUT_REG_VALID_TOGETHER_MASK 0x1 +#define OUT_REG_VALID_TOGETHER_MASK_SFT (0x1 << 31) + +/* ETDM_OUT0_CON1 */ +/* ETDM_OUT1_CON1 */ +/* ETDM_OUT2_CON1 */ +/* ETDM_OUT3_CON1 */ +/* ETDM_OUT4_CON1 */ +/* ETDM_OUT5_CON1 */ +/* ETDM_OUT6_CON1 */ +#define OUT_REG_INITIAL_COUNT_SFT 0 +#define OUT_REG_INITIAL_COUNT_MASK 0x1f +#define OUT_REG_INITIAL_COUNT_MASK_SFT (0x1f << 0) +#define OUT_REG_INITIAL_POINT_SFT 5 +#define OUT_REG_INITIAL_POINT_MASK 0x1f +#define OUT_REG_INITIAL_POINT_MASK_SFT (0x1f << 5) +#define OUT_REG_LRCK_AUTO_OFF_SFT 10 +#define OUT_REG_LRCK_AUTO_OFF_MASK 0x1 +#define OUT_REG_LRCK_AUTO_OFF_MASK_SFT (0x1 << 10) +#define OUT_REG_BCK_AUTO_OFF_SFT 11 +#define OUT_REG_BCK_AUTO_OFF_MASK 0x1 +#define OUT_REG_BCK_AUTO_OFF_MASK_SFT (0x1 << 11) +#define OUT_REG_INITIAL_LRCK_SFT 13 +#define OUT_REG_INITIAL_LRCK_MASK 0x1 +#define OUT_REG_INITIAL_LRCK_MASK_SFT (0x1 << 13) +#define OUT_REG_NO_ALIGN_1X_EN_SFT 14 +#define OUT_REG_NO_ALIGN_1X_EN_MASK 0x1 +#define OUT_REG_NO_ALIGN_1X_EN_MASK_SFT (0x1 << 14) +#define OUT_REG_LRCK_RESET_SFT 15 +#define OUT_REG_LRCK_RESET_MASK 0x1 +#define OUT_REG_LRCK_RESET_MASK_SFT (0x1 << 15) +#define OUT_PINMUX_MCLK_CTRL_OE_SFT 16 +#define OUT_PINMUX_MCLK_CTRL_OE_MASK 0x1 +#define OUT_PINMUX_MCLK_CTRL_OE_MASK_SFT (0x1 << 16) +#define OUT_REG_OUTPUT_CR_EN_SFT 18 +#define OUT_REG_OUTPUT_CR_EN_MASK 0x1 +#define OUT_REG_OUTPUT_CR_EN_MASK_SFT (0x1 << 18) +#define OUT_REG_LRCK_WIDTH_SFT 19 +#define OUT_REG_LRCK_WIDTH_MASK 0x3ff +#define OUT_REG_LRCK_WIDTH_MASK_SFT (0x3ff << 19) +#define OUT_REG_LRCK_AUTO_MODE_SFT 29 +#define OUT_REG_LRCK_AUTO_MODE_MASK 0x1 +#define OUT_REG_LRCK_AUTO_MODE_MASK_SFT (0x1 << 29) +#define OUT_REG_DIRECT_INPUT_MASTER_BCK_SFT 30 +#define OUT_REG_DIRECT_INPUT_MASTER_BCK_MASK 0x1 +#define OUT_REG_DIRECT_INPUT_MASTER_BCK_MASK_SFT (0x1 << 30) +#define OUT_REG_16B_COMPACT_MODE_SFT 31 +#define OUT_REG_16B_COMPACT_MODE_MASK 0x1 +#define OUT_REG_16B_COMPACT_MODE_MASK_SFT (0x1 << 31) + +/* ETDM_OUT0_CON2 */ +/* ETDM_OUT1_CON2 */ +/* ETDM_OUT2_CON2 */ +/* ETDM_OUT3_CON2 */ +/* ETDM_OUT4_CON2 */ +/* ETDM_OUT5_CON2 */ +/* ETDM_OUT6_CON2 */ +#define OUT_REG_IN2LATCH_TIME_SFT 0 +#define OUT_REG_IN2LATCH_TIME_MASK 0x1f +#define OUT_REG_IN2LATCH_TIME_MASK_SFT (0x1f << 0) +#define OUT_REG_MASK_NUM_SFT 5 +#define OUT_REG_MASK_NUM_MASK 0x1f +#define OUT_REG_MASK_NUM_MASK_SFT (0x1f << 5) +#define OUT_REG_MASK_AUTO_SFT 10 +#define OUT_REG_MASK_AUTO_MASK 0x1 +#define OUT_REG_MASK_AUTO_MASK_SFT (0x1 << 10) +#define OUT_REG_SDATA_SHIFT_SFT 11 +#define OUT_REG_SDATA_SHIFT_MASK 0x3 +#define OUT_REG_SDATA_SHIFT_MASK_SFT (0x3 << 11) +#define OUT_REG_ALMOST_END_BIT_COUNT_SFT 13 +#define OUT_REG_ALMOST_END_BIT_COUNT_MASK 0x1f +#define OUT_REG_ALMOST_END_BIT_COUNT_MASK_SFT (0x1f << 13) +#define OUT_REG_SDATA_CON_SFT 18 +#define OUT_REG_SDATA_CON_MASK 0x3 +#define OUT_REG_SDATA_CON_MASK_SFT (0x3 << 18) +#define OUT_REG_REDUNDANT_0_SFT 20 +#define OUT_REG_REDUNDANT_0_MASK 0x1 +#define OUT_REG_REDUNDANT_0_MASK_SFT (0x1 << 20) +#define OUT_REG_SDATA_AUTO_OFF_SFT 21 +#define OUT_REG_SDATA_AUTO_OFF_MASK 0x1 +#define OUT_REG_SDATA_AUTO_OFF_MASK_SFT (0x1 << 21) +#define OUT_REG_BCK_OFF_TIME_SFT 22 +#define OUT_REG_BCK_OFF_TIME_MASK 0x3 +#define OUT_REG_BCK_OFF_TIME_MASK_SFT (0x3 << 22) +#define OUT_REG_MONITOR_SEL_SFT 24 +#define OUT_REG_MONITOR_SEL_MASK 0x3 +#define OUT_REG_MONITOR_SEL_MASK_SFT (0x3 << 24) +#define OUT_REG_SHIFT_AUTO_SFT 26 +#define OUT_REG_SHIFT_AUTO_MASK 0x1 +#define OUT_REG_SHIFT_AUTO_MASK_SFT (0x1 << 26) +#define OUT_REG_SDATA_DELAY_0P5T_EN_SFT 27 +#define OUT_REG_SDATA_DELAY_0P5T_EN_MASK 0x1 +#define OUT_REG_SDATA_DELAY_0P5T_EN_MASK_SFT (0x1 << 27) +#define OUT_REG_SDATA_DELAY_BCK_INV_SFT 28 +#define OUT_REG_SDATA_DELAY_BCK_INV_MASK 0x1 +#define OUT_REG_SDATA_DELAY_BCK_INV_MASK_SFT (0x1 << 28) +#define OUT_REG_LRCK_DELAY_0P5T_EN_SFT 29 +#define OUT_REG_LRCK_DELAY_0P5T_EN_MASK 0x1 +#define OUT_REG_LRCK_DELAY_0P5T_EN_MASK_SFT (0x1 << 29) +#define OUT_REG_LRCK_DELAY_BCK_INV_SFT 30 +#define OUT_REG_LRCK_DELAY_BCK_INV_MASK 0x1 +#define OUT_REG_LRCK_DELAY_BCK_INV_MASK_SFT (0x1 << 30) +#define OUT_REG_OFF_CR_EN_SFT 31 +#define OUT_REG_OFF_CR_EN_MASK 0x1 +#define OUT_REG_OFF_CR_EN_MASK_SFT (0x1 << 31) + +/* ETDM_OUT0_CON3 */ +/* ETDM_OUT1_CON3 */ +/* ETDM_OUT2_CON3 */ +/* ETDM_OUT3_CON3 */ +/* ETDM_OUT4_CON3 */ +/* ETDM_OUT5_CON3 */ +/* ETDM_OUT6_CON3 */ +#define OUT_REG_START_CH_PAIR0_SFT 0 +#define OUT_REG_START_CH_PAIR0_MASK 0xf +#define OUT_REG_START_CH_PAIR0_MASK_SFT (0xf << 0) +#define OUT_REG_START_CH_PAIR1_SFT 4 +#define OUT_REG_START_CH_PAIR1_MASK 0xf +#define OUT_REG_START_CH_PAIR1_MASK_SFT (0xf << 4) +#define OUT_REG_START_CH_PAIR2_SFT 8 +#define OUT_REG_START_CH_PAIR2_MASK 0xf +#define OUT_REG_START_CH_PAIR2_MASK_SFT (0xf << 8) +#define OUT_REG_START_CH_PAIR3_SFT 12 +#define OUT_REG_START_CH_PAIR3_MASK 0xf +#define OUT_REG_START_CH_PAIR3_MASK_SFT (0xf << 12) +#define OUT_REG_START_CH_PAIR4_SFT 16 +#define OUT_REG_START_CH_PAIR4_MASK 0xf +#define OUT_REG_START_CH_PAIR4_MASK_SFT (0xf << 16) +#define OUT_REG_START_CH_PAIR5_SFT 20 +#define OUT_REG_START_CH_PAIR5_MASK 0xf +#define OUT_REG_START_CH_PAIR5_MASK_SFT (0xf << 20) +#define OUT_REG_START_CH_PAIR6_SFT 24 +#define OUT_REG_START_CH_PAIR6_MASK 0xf +#define OUT_REG_START_CH_PAIR6_MASK_SFT (0xf << 24) +#define OUT_REG_START_CH_PAIR7_SFT 28 +#define OUT_REG_START_CH_PAIR7_MASK 0xf +#define OUT_REG_START_CH_PAIR7_MASK_SFT (0xf << 28) + +/* ETDM_OUT0_CON4 */ +/* ETDM_OUT1_CON4 */ +/* ETDM_OUT2_CON4 */ +/* ETDM_OUT3_CON4 */ +/* ETDM_OUT4_CON4 */ +/* ETDM_OUT5_CON4 */ +/* ETDM_OUT6_CON4 */ +#define OUT_REG_FS_TIMING_SEL_SFT 0 +#define OUT_REG_FS_TIMING_SEL_MASK 0x1f +#define OUT_REG_FS_TIMING_SEL_MASK_SFT (0x1f << 0) +#define OUT_REG_CLOCK_SOURCE_SEL_SFT 6 +#define OUT_REG_CLOCK_SOURCE_SEL_MASK 0x7 +#define OUT_REG_CLOCK_SOURCE_SEL_MASK_SFT (0x7 << 6) +#define OUT_REG_CK_EN_SEL_AUTO_SFT 10 +#define OUT_REG_CK_EN_SEL_AUTO_MASK 0x1 +#define OUT_REG_CK_EN_SEL_AUTO_MASK_SFT (0x1 << 10) +#define OUT_REG_ASYNC_RESET_SFT 11 +#define OUT_REG_ASYNC_RESET_MASK 0x1 +#define OUT_REG_ASYNC_RESET_MASK_SFT (0x1 << 11) +#define OUT_REG_CK_EN_SEL_MANUAL_SFT 14 +#define OUT_REG_CK_EN_SEL_MANUAL_MASK 0x3ff +#define OUT_REG_CK_EN_SEL_MANUAL_MASK_SFT (0x3ff << 14) +#define OUT_REG_RELATCH_EN_SEL_SFT 24 +#define OUT_REG_RELATCH_EN_SEL_MASK 0x1f +#define OUT_REG_RELATCH_EN_SEL_MASK_SFT (0x1f << 24) +#define OUT_REG_WAIT_LAST_SAMPLE_SFT 30 +#define OUT_REG_WAIT_LAST_SAMPLE_MASK 0x1 +#define OUT_REG_WAIT_LAST_SAMPLE_MASK_SFT (0x1 << 30) +#define OUT_REG_ALWAYS_OPEN_1X_EN_SFT 31 +#define OUT_REG_ALWAYS_OPEN_1X_EN_MASK 0x1 +#define OUT_REG_ALWAYS_OPEN_1X_EN_MASK_SFT (0x1 << 31) + +/* ETDM_OUT0_CON5 */ +/* ETDM_OUT1_CON5 */ +/* ETDM_OUT2_CON5 */ +/* ETDM_OUT3_CON5 */ +/* ETDM_OUT4_CON5 */ +/* ETDM_OUT5_CON5 */ +/* ETDM_OUT6_CON5 */ +#define OUT_REG_REPACK_BITNUM_SFT 0 +#define OUT_REG_REPACK_BITNUM_MASK 0x3 +#define OUT_REG_REPACK_BITNUM_MASK_SFT (0x3 << 0) +#define OUT_REG_REPACK_CHNUM_SFT 2 +#define OUT_REG_REPACK_CHNUM_MASK 0xf +#define OUT_REG_REPACK_CHNUM_MASK_SFT (0xf << 2) +#define OUT_REG_SLAVE_BCK_INV_SFT 7 +#define OUT_REG_SLAVE_BCK_INV_MASK 0x1 +#define OUT_REG_SLAVE_BCK_INV_MASK_SFT (0x1 << 7) +#define OUT_REG_SLAVE_LRCK_INV_SFT 8 +#define OUT_REG_SLAVE_LRCK_INV_MASK 0x1 +#define OUT_REG_SLAVE_LRCK_INV_MASK_SFT (0x1 << 8) +#define OUT_REG_MASTER_BCK_INV_SFT 9 +#define OUT_REG_MASTER_BCK_INV_MASK 0x1 +#define OUT_REG_MASTER_BCK_INV_MASK_SFT (0x1 << 9) +#define OUT_REG_MASTER_WS_INV_SFT 10 +#define OUT_REG_MASTER_WS_INV_MASK 0x1 +#define OUT_REG_MASTER_WS_INV_MASK_SFT (0x1 << 10) +#define OUT_REG_REPACK_24B_MSB_ALIGN_SFT 11 +#define OUT_REG_REPACK_24B_MSB_ALIGN_MASK 0x1 +#define OUT_REG_REPACK_24B_MSB_ALIGN_MASK_SFT (0x1 << 11) +#define OUT_REG_LR_SWAP_SFT 16 +#define OUT_REG_LR_SWAP_MASK 0xffff +#define OUT_REG_LR_SWAP_MASK_SFT (0xffff << 16) + +/* ETDM_OUT0_CON6 */ +/* ETDM_OUT1_CON6 */ +/* ETDM_OUT2_CON6 */ +/* ETDM_OUT3_CON6 */ +/* ETDM_OUT4_CON6 */ +/* ETDM_OUT5_CON6 */ +/* ETDM_OUT6_CON6 */ +#define OUT_LCH_DATA_REG_SFT 0 +#define OUT_LCH_DATA_REG_MASK 0xffffffff +#define OUT_LCH_DATA_REG_MASK_SFT (0xffffffff << 0) + +/* ETDM_OUT0_CON7 */ +/* ETDM_OUT1_CON7 */ +/* ETDM_OUT2_CON7 */ +/* ETDM_OUT3_CON7 */ +/* ETDM_OUT4_CON7 */ +/* ETDM_OUT5_CON7 */ +/* ETDM_OUT6_CON7 */ +#define OUT_RCH_DATA_REG_SFT 0 +#define OUT_RCH_DATA_REG_MASK 0xffffffff +#define OUT_RCH_DATA_REG_MASK_SFT (0xffffffff << 0) + +/* ETDM_OUT0_CON8 */ +/* ETDM_OUT1_CON8 */ +/* ETDM_OUT2_CON8 */ +/* ETDM_OUT3_CON8 */ +/* ETDM_OUT4_CON8 */ +/* ETDM_OUT5_CON8 */ +/* ETDM_OUT6_CON8 */ +#define OUT_REG_START_CH_PAIR8_SFT 0 +#define OUT_REG_START_CH_PAIR8_MASK 0xf +#define OUT_REG_START_CH_PAIR8_MASK_SFT (0xf << 0) +#define OUT_REG_START_CH_PAIR9_SFT 4 +#define OUT_REG_START_CH_PAIR9_MASK 0xf +#define OUT_REG_START_CH_PAIR9_MASK_SFT (0xf << 4) +#define OUT_REG_START_CH_PAIR10_SFT 8 +#define OUT_REG_START_CH_PAIR10_MASK 0xf +#define OUT_REG_START_CH_PAIR10_MASK_SFT (0xf << 8) +#define OUT_REG_START_CH_PAIR11_SFT 12 +#define OUT_REG_START_CH_PAIR11_MASK 0xf +#define OUT_REG_START_CH_PAIR11_MASK_SFT (0xf << 12) +#define OUT_REG_START_CH_PAIR12_SFT 16 +#define OUT_REG_START_CH_PAIR12_MASK 0xf +#define OUT_REG_START_CH_PAIR12_MASK_SFT (0xf << 16) +#define OUT_REG_START_CH_PAIR13_SFT 20 +#define OUT_REG_START_CH_PAIR13_MASK 0xf +#define OUT_REG_START_CH_PAIR13_MASK_SFT (0xf << 20) +#define OUT_REG_START_CH_PAIR14_SFT 24 +#define OUT_REG_START_CH_PAIR14_MASK 0xf +#define OUT_REG_START_CH_PAIR14_MASK_SFT (0xf << 24) +#define OUT_REG_START_CH_PAIR15_SFT 28 +#define OUT_REG_START_CH_PAIR15_MASK 0xf +#define OUT_REG_START_CH_PAIR15_MASK_SFT (0xf << 28) + +/* ETDM_OUT0_CON9 */ +/* ETDM_OUT1_CON9 */ +/* ETDM_OUT2_CON9 */ +/* ETDM_OUT3_CON9 */ +/* ETDM_OUT4_CON9 */ +/* ETDM_OUT5_CON9 */ +/* ETDM_OUT6_CON9 */ +#define OUT_REG_AFIFO_THRESHOLD_SFT 29 +#define OUT_REG_AFIFO_THRESHOLD_MASK 0x3 +#define OUT_REG_AFIFO_THRESHOLD_MASK_SFT (0x3 << 29) +#define OUT_REG_AFIFO_SW_RESET_SFT 15 +#define OUT_REG_AFIFO_SW_RESET_MASK 0x1 +#define OUT_REG_AFIFO_SW_RESET_MASK_SFT (0x1 << 15) +#define OUT_REG_AFIFO_RESET_SEL_SFT 14 +#define OUT_REG_AFIFO_RESET_SEL_MASK 0x1 +#define OUT_REG_AFIFO_RESET_SEL_MASK_SFT (0x1 << 14) +#define OUT_REG_AFIFO_AUTO_RESET_DIS_SFT 9 +#define OUT_REG_AFIFO_AUTO_RESET_DIS_MASK 0x1 +#define OUT_REG_AFIFO_AUTO_RESET_DIS_MASK_SFT (0x1 << 9) +#define OUT_REG_ETDM_USE_AFIFO_SFT 8 +#define OUT_REG_ETDM_USE_AFIFO_MASK 0x1 +#define OUT_REG_ETDM_USE_AFIFO_MASK_SFT (0x1 << 8) +#define OUT_REG_AFIFO_CLOCK_DOMAIN_SEL_SFT 5 +#define OUT_REG_AFIFO_CLOCK_DOMAIN_SEL_MASK 0x7 +#define OUT_REG_AFIFO_CLOCK_DOMAIN_SEL_MASK_SFT (0x7 << 5) +#define OUT_REG_AFIFO_MODE_SFT 0 +#define OUT_REG_AFIFO_MODE_MASK 0x1f +#define OUT_REG_AFIFO_MODE_MASK_SFT (0x1f << 0) + +/* ETDM_OUT0_MON */ +/* ETDM_OUT1_MON */ +/* ETDM_OUT2_MON */ +/* ETDM_OUT3_MON */ +/* ETDM_OUT4_MON */ +/* ETDM_OUT5_MON */ +/* ETDM_OUT6_MON */ +#define LRCK_INV_SFT 30 +#define LRCK_INV_MASK 0x1 +#define LRCK_INV_MASK_SFT (0x1 << 30) +#define EN_SYNC_OUT_SFT 29 +#define EN_SYNC_OUT_MASK 0x1 +#define EN_SYNC_OUT_MASK_SFT (0x1 << 29) +#define HOPPING_EN_SYNC_OUT_PRE_SFT 28 +#define HOPPING_EN_SYNC_OUT_PRE_MASK 0x1 +#define HOPPING_EN_SYNC_OUT_PRE_MASK_SFT (0x1 << 28) +#define ETDM_2X_CK_EN_SFT 25 +#define ETDM_2X_CK_EN_MASK 0x1 +#define ETDM_2X_CK_EN_MASK_SFT (0x1 << 25) +#define ETDM_1X_CK_EN_SFT 24 +#define ETDM_1X_CK_EN_MASK 0x1 +#define ETDM_1X_CK_EN_MASK_SFT (0x1 << 24) +#define SDATA0_SFT 23 +#define SDATA0_MASK 0x1 +#define SDATA0_MASK_SFT (0x1 << 23) +#define CURRENT_STATUS_SFT 21 +#define CURRENT_STATUS_MASK 0x3 +#define CURRENT_STATUS_MASK_SFT (0x3 << 21) +#define BIT_POINT_SFT 16 +#define BIT_POINT_MASK 0x1f +#define BIT_POINT_MASK_SFT (0x1f << 16) +#define BIT_CH_COUNT_SFT 10 +#define BIT_CH_COUNT_MASK 0x3f +#define BIT_CH_COUNT_MASK_SFT (0x3f << 10) +#define BIT_COUNT_SFT 5 +#define BIT_COUNT_MASK 0x1f +#define BIT_COUNT_MASK_SFT (0x1f << 5) +#define CH_COUNT_SFT 0 +#define CH_COUNT_MASK 0x1f +#define CH_COUNT_MASK_SFT (0x1f << 0) + +/* ETDM_0_3_COWORK_CON0 */ +#define ETDM_OUT0_DATA_SEL_SFT 0 +#define ETDM_OUT0_DATA_SEL_MASK 0xf +#define ETDM_OUT0_DATA_SEL_MASK_SFT (0xf << 0) +#define ETDM_OUT0_SYNC_SEL_SFT 4 +#define ETDM_OUT0_SYNC_SEL_MASK 0xf +#define ETDM_OUT0_SYNC_SEL_MASK_SFT (0xf << 4) +#define ETDM_OUT0_SLAVE_SEL_SFT 8 +#define ETDM_OUT0_SLAVE_SEL_MASK 0xf +#define ETDM_OUT0_SLAVE_SEL_MASK_SFT (0xf << 8) +#define ETDM_OUT1_DATA_SEL_SFT 12 +#define ETDM_OUT1_DATA_SEL_MASK 0xf +#define ETDM_OUT1_DATA_SEL_MASK_SFT (0xf << 12) +#define ETDM_OUT1_SYNC_SEL_SFT 16 +#define ETDM_OUT1_SYNC_SEL_MASK 0xf +#define ETDM_OUT1_SYNC_SEL_MASK_SFT (0xf << 16) +#define ETDM_OUT1_SLAVE_SEL_SFT 20 +#define ETDM_OUT1_SLAVE_SEL_MASK 0xf +#define ETDM_OUT1_SLAVE_SEL_MASK_SFT (0xf << 20) +#define ETDM_IN0_SLAVE_SEL_SFT 24 +#define ETDM_IN0_SLAVE_SEL_MASK 0xf +#define ETDM_IN0_SLAVE_SEL_MASK_SFT (0xf << 24) +#define ETDM_IN0_SYNC_SEL_SFT 28 +#define ETDM_IN0_SYNC_SEL_MASK 0xf +#define ETDM_IN0_SYNC_SEL_MASK_SFT (0xf << 28) + +/* ETDM_0_3_COWORK_CON1 */ +#define ETDM_IN0_SDATA0_SEL_SFT 0 +#define ETDM_IN0_SDATA0_SEL_MASK 0xf +#define ETDM_IN0_SDATA0_SEL_MASK_SFT (0xf << 0) +#define ETDM_IN0_SDATA1_15_SEL_SFT 4 +#define ETDM_IN0_SDATA1_15_SEL_MASK 0xf +#define ETDM_IN0_SDATA1_15_SEL_MASK_SFT (0xf << 4) +#define ETDM_IN1_SLAVE_SEL_SFT 8 +#define ETDM_IN1_SLAVE_SEL_MASK 0xf +#define ETDM_IN1_SLAVE_SEL_MASK_SFT (0xf << 8) +#define ETDM_IN1_SYNC_SEL_SFT 12 +#define ETDM_IN1_SYNC_SEL_MASK 0xf +#define ETDM_IN1_SYNC_SEL_MASK_SFT (0xf << 12) +#define ETDM_IN1_SDATA0_SEL_SFT 16 +#define ETDM_IN1_SDATA0_SEL_MASK 0xf +#define ETDM_IN1_SDATA0_SEL_MASK_SFT (0xf << 16) +#define ETDM_IN1_SDATA1_15_SEL_SFT 20 +#define ETDM_IN1_SDATA1_15_SEL_MASK 0xf +#define ETDM_IN1_SDATA1_15_SEL_MASK_SFT (0xf << 20) + +/* ETDM_0_3_COWORK_CON2 */ +#define ETDM_OUT2_DATA_SEL_SFT 0 +#define ETDM_OUT2_DATA_SEL_MASK 0xf +#define ETDM_OUT2_DATA_SEL_MASK_SFT (0xf << 0) +#define ETDM_OUT2_SYNC_SEL_SFT 4 +#define ETDM_OUT2_SYNC_SEL_MASK 0xf +#define ETDM_OUT2_SYNC_SEL_MASK_SFT (0xf << 4) +#define ETDM_OUT2_SLAVE_SEL_SFT 8 +#define ETDM_OUT2_SLAVE_SEL_MASK 0xf +#define ETDM_OUT2_SLAVE_SEL_MASK_SFT (0xf << 8) +#define ETDM_OUT3_DATA_SEL_SFT 12 +#define ETDM_OUT3_DATA_SEL_MASK 0xf +#define ETDM_OUT3_DATA_SEL_MASK_SFT (0xf << 12) +#define ETDM_OUT3_SYNC_SEL_SFT 16 +#define ETDM_OUT3_SYNC_SEL_MASK 0xf +#define ETDM_OUT3_SYNC_SEL_MASK_SFT (0xf << 16) +#define ETDM_OUT3_SLAVE_SEL_SFT 20 +#define ETDM_OUT3_SLAVE_SEL_MASK 0xf +#define ETDM_OUT3_SLAVE_SEL_MASK_SFT (0xf << 20) +#define ETDM_IN2_SLAVE_SEL_SFT 24 +#define ETDM_IN2_SLAVE_SEL_MASK 0xf +#define ETDM_IN2_SLAVE_SEL_MASK_SFT (0xf << 24) +#define ETDM_IN2_SYNC_SEL_SFT 28 +#define ETDM_IN2_SYNC_SEL_MASK 0xf +#define ETDM_IN2_SYNC_SEL_MASK_SFT (0xf << 28) + +/* ETDM_0_3_COWORK_CON3 */ +#define ETDM_IN2_SDATA0_SEL_SFT 0 +#define ETDM_IN2_SDATA0_SEL_MASK 0xf +#define ETDM_IN2_SDATA0_SEL_MASK_SFT (0xf << 0) +#define ETDM_IN2_SDATA1_15_SEL_SFT 4 +#define ETDM_IN2_SDATA1_15_SEL_MASK 0xf +#define ETDM_IN2_SDATA1_15_SEL_MASK_SFT (0xf << 4) +#define ETDM_IN3_SLAVE_SEL_SFT 8 +#define ETDM_IN3_SLAVE_SEL_MASK 0xf +#define ETDM_IN3_SLAVE_SEL_MASK_SFT (0xf << 8) +#define ETDM_IN3_SYNC_SEL_SFT 12 +#define ETDM_IN3_SYNC_SEL_MASK 0xf +#define ETDM_IN3_SYNC_SEL_MASK_SFT (0xf << 12) +#define ETDM_IN3_SDATA0_SEL_SFT 16 +#define ETDM_IN3_SDATA0_SEL_MASK 0xf +#define ETDM_IN3_SDATA0_SEL_MASK_SFT (0xf << 16) +#define ETDM_IN3_SDATA1_15_SEL_SFT 20 +#define ETDM_IN3_SDATA1_15_SEL_MASK 0xf +#define ETDM_IN3_SDATA1_15_SEL_MASK_SFT (0xf << 20) + +/* ETDM_4_7_COWORK_CON0 */ +#define ETDM_OUT4_DATA_SEL_SFT 0 +#define ETDM_OUT4_DATA_SEL_MASK 0xf +#define ETDM_OUT4_DATA_SEL_MASK_SFT (0xf << 0) +#define ETDM_OUT4_SYNC_SEL_SFT 4 +#define ETDM_OUT4_SYNC_SEL_MASK 0xf +#define ETDM_OUT4_SYNC_SEL_MASK_SFT (0xf << 4) +#define ETDM_OUT4_SLAVE_SEL_SFT 8 +#define ETDM_OUT4_SLAVE_SEL_MASK 0xf +#define ETDM_OUT4_SLAVE_SEL_MASK_SFT (0xf << 8) +#define ETDM_OUT5_DATA_SEL_SFT 12 +#define ETDM_OUT5_DATA_SEL_MASK 0xf +#define ETDM_OUT5_DATA_SEL_MASK_SFT (0xf << 12) +#define ETDM_OUT5_SYNC_SEL_SFT 16 +#define ETDM_OUT5_SYNC_SEL_MASK 0xf +#define ETDM_OUT5_SYNC_SEL_MASK_SFT (0xf << 16) +#define ETDM_OUT5_SLAVE_SEL_SFT 20 +#define ETDM_OUT5_SLAVE_SEL_MASK 0xf +#define ETDM_OUT5_SLAVE_SEL_MASK_SFT (0xf << 20) +#define ETDM_IN4_SLAVE_SEL_SFT 24 +#define ETDM_IN4_SLAVE_SEL_MASK 0xf +#define ETDM_IN4_SLAVE_SEL_MASK_SFT (0xf << 24) +#define ETDM_IN4_SYNC_SEL_SFT 28 +#define ETDM_IN4_SYNC_SEL_MASK 0xf +#define ETDM_IN4_SYNC_SEL_MASK_SFT (0xf << 28) + +/* ETDM_4_7_COWORK_CON1 */ +#define ETDM_IN4_SDATA0_SEL_SFT 0 +#define ETDM_IN4_SDATA0_SEL_MASK 0xf +#define ETDM_IN4_SDATA0_SEL_MASK_SFT (0xf << 0) +#define ETDM_IN4_SDATA1_15_SEL_SFT 4 +#define ETDM_IN4_SDATA1_15_SEL_MASK 0xf +#define ETDM_IN4_SDATA1_15_SEL_MASK_SFT (0xf << 4) +#define ETDM_IN5_SLAVE_SEL_SFT 8 +#define ETDM_IN5_SLAVE_SEL_MASK 0xf +#define ETDM_IN5_SLAVE_SEL_MASK_SFT (0xf << 8) +#define ETDM_IN5_SYNC_SEL_SFT 12 +#define ETDM_IN5_SYNC_SEL_MASK 0xf +#define ETDM_IN5_SYNC_SEL_MASK_SFT (0xf << 12) +#define ETDM_IN5_SDATA0_SEL_SFT 16 +#define ETDM_IN5_SDATA0_SEL_MASK 0xf +#define ETDM_IN5_SDATA0_SEL_MASK_SFT (0xf << 16) +#define ETDM_IN5_SDATA1_15_SEL_SFT 20 +#define ETDM_IN5_SDATA1_15_SEL_MASK 0xf +#define ETDM_IN5_SDATA1_15_SEL_MASK_SFT (0xf << 20) + +/* ETDM_4_7_COWORK_CON2 */ +#define ETDM_OUT6_DATA_SEL_SFT 0 +#define ETDM_OUT6_DATA_SEL_MASK 0xf +#define ETDM_OUT6_DATA_SEL_MASK_SFT (0xf << 0) +#define ETDM_OUT6_SYNC_SEL_SFT 4 +#define ETDM_OUT6_SYNC_SEL_MASK 0xf +#define ETDM_OUT6_SYNC_SEL_MASK_SFT (0xf << 4) +#define ETDM_OUT6_SLAVE_SEL_SFT 8 +#define ETDM_OUT6_SLAVE_SEL_MASK 0xf +#define ETDM_OUT6_SLAVE_SEL_MASK_SFT (0xf << 8) +#define ETDM_OUT7_DATA_SEL_SFT 12 +#define ETDM_OUT7_DATA_SEL_MASK 0xf +#define ETDM_OUT7_DATA_SEL_MASK_SFT (0xf << 12) +#define ETDM_OUT7_SYNC_SEL_SFT 16 +#define ETDM_OUT7_SYNC_SEL_MASK 0xf +#define ETDM_OUT7_SYNC_SEL_MASK_SFT (0xf << 16) +#define ETDM_OUT7_SLAVE_SEL_SFT 20 +#define ETDM_OUT7_SLAVE_SEL_MASK 0xf +#define ETDM_OUT7_SLAVE_SEL_MASK_SFT (0xf << 20) +#define ETDM_IN6_SLAVE_SEL_SFT 24 +#define ETDM_IN6_SLAVE_SEL_MASK 0xf +#define ETDM_IN6_SLAVE_SEL_MASK_SFT (0xf << 24) +#define ETDM_IN6_SYNC_SEL_SFT 28 +#define ETDM_IN6_SYNC_SEL_MASK 0xf +#define ETDM_IN6_SYNC_SEL_MASK_SFT (0xf << 28) + +/* ETDM_4_7_COWORK_CON3 */ +#define ETDM_IN6_SDATA0_SEL_SFT 0 +#define ETDM_IN6_SDATA0_SEL_MASK 0xf +#define ETDM_IN6_SDATA0_SEL_MASK_SFT (0xf << 0) +#define ETDM_IN6_SDATA1_15_SEL_SFT 4 +#define ETDM_IN6_SDATA1_15_SEL_MASK 0xf +#define ETDM_IN6_SDATA1_15_SEL_MASK_SFT (0xf << 4) +#define ETDM_IN7_SLAVE_SEL_SFT 8 +#define ETDM_IN7_SLAVE_SEL_MASK 0xf +#define ETDM_IN7_SLAVE_SEL_MASK_SFT (0xf << 8) +#define ETDM_IN7_SYNC_SEL_SFT 12 +#define ETDM_IN7_SYNC_SEL_MASK 0xf +#define ETDM_IN7_SYNC_SEL_MASK_SFT (0xf << 12) +#define ETDM_IN7_SDATA0_SEL_SFT 16 +#define ETDM_IN7_SDATA0_SEL_MASK 0xf +#define ETDM_IN7_SDATA0_SEL_MASK_SFT (0xf << 16) +#define ETDM_IN7_SDATA1_15_SEL_SFT 20 +#define ETDM_IN7_SDATA1_15_SEL_MASK 0xf +#define ETDM_IN7_SDATA1_15_SEL_MASK_SFT (0xf << 20) + +/* AFE_DPTX_CON */ +#define DPTX_CHANNEL_ENABLE_SFT 8 +#define DPTX_CHANNEL_ENABLE_MASK 0xff +#define DPTX_CHANNEL_ENABLE_MASK_SFT (0xff << 8) +#define DPTX_REGISTER_MONITOR_SELECT_SFT 3 +#define DPTX_REGISTER_MONITOR_SELECT_MASK 0xf +#define DPTX_REGISTER_MONITOR_SELECT_MASK_SFT (0xf << 3) +#define DPTX_16BIT_SFT 2 +#define DPTX_16BIT_MASK 0x1 +#define DPTX_16BIT_MASK_SFT (0x1 << 2) +#define DPTX_CHANNEL_NUMBER_SFT 1 +#define DPTX_CHANNEL_NUMBER_MASK 0x1 +#define DPTX_CHANNEL_NUMBER_MASK_SFT (0x1 << 1) +#define DPTX_ON_SFT 0 +#define DPTX_ON_MASK 0x1 +#define DPTX_ON_MASK_SFT (0x1 << 0) + +/* AFE_DPTX_MON */ +#define AFE_DPTX_MON0_SFT 0 +#define AFE_DPTX_MON0_MASK 0xffffffff +#define AFE_DPTX_MON0_MASK_SFT (0xffffffff << 0) + +/* AFE_TDM_CON1 */ +#define TDM_EN_SFT 0 +#define TDM_EN_MASK 0x1 +#define TDM_EN_MASK_SFT (0x1 << 0) +#define BCK_INVERSE_SFT 1 +#define BCK_INVERSE_MASK 0x1 +#define BCK_INVERSE_MASK_SFT (0x1 << 1) +#define LRCK_INVERSE_SFT 2 +#define LRCK_INVERSE_MASK 0x1 +#define LRCK_INVERSE_MASK_SFT (0x1 << 2) +#define DELAY_DATA_SFT 3 +#define DELAY_DATA_MASK 0x1 +#define DELAY_DATA_MASK_SFT (0x1 << 3) +#define LEFT_ALIGN_SFT 4 +#define LEFT_ALIGN_MASK 0x1 +#define LEFT_ALIGN_MASK_SFT (0x1 << 4) +#define TDM_LRCK_D0P5T_SFT 5 +#define TDM_LRCK_D0P5T_MASK 0x1 +#define TDM_LRCK_D0P5T_MASK_SFT (0x1 << 5) +#define TDM_SDATA_D0P5T_SFT 6 +#define TDM_SDATA_D0P5T_MASK 0x1 +#define TDM_SDATA_D0P5T_MASK_SFT (0x1 << 6) +#define WLEN_SFT 8 +#define WLEN_MASK 0x3 +#define WLEN_MASK_SFT (0x3 << 8) +#define CHANNEL_NUM_SFT 10 +#define CHANNEL_NUM_MASK 0x3 +#define CHANNEL_NUM_MASK_SFT (0x3 << 10) +#define CHANNEL_BCK_CYCLES_SFT 12 +#define CHANNEL_BCK_CYCLES_MASK 0x3 +#define CHANNEL_BCK_CYCLES_MASK_SFT (0x3 << 12) +#define HDMI_CLK_INV_SEL_SFT 15 +#define HDMI_CLK_INV_SEL_MASK 0x1 +#define HDMI_CLK_INV_SEL_MASK_SFT (0x1 << 15) +#define DAC_BIT_NUM_SFT 16 +#define DAC_BIT_NUM_MASK 0x1f +#define DAC_BIT_NUM_MASK_SFT (0x1f << 16) +#define LRCK_TDM_WIDTH_SFT 24 +#define LRCK_TDM_WIDTH_MASK 0xff +#define LRCK_TDM_WIDTH_MASK_SFT (0xff << 24) + +/* AFE_TDM_CON2 */ +#define ST_CH_PAIR_SOUT0_SFT 0 +#define ST_CH_PAIR_SOUT0_MASK 0x7 +#define ST_CH_PAIR_SOUT0_MASK_SFT (0x7 << 0) +#define ST_CH_PAIR_SOUT1_SFT 4 +#define ST_CH_PAIR_SOUT1_MASK 0x7 +#define ST_CH_PAIR_SOUT1_MASK_SFT (0x7 << 4) +#define ST_CH_PAIR_SOUT2_SFT 8 +#define ST_CH_PAIR_SOUT2_MASK 0x7 +#define ST_CH_PAIR_SOUT2_MASK_SFT (0x7 << 8) +#define ST_CH_PAIR_SOUT3_SFT 12 +#define ST_CH_PAIR_SOUT3_MASK 0x7 +#define ST_CH_PAIR_SOUT3_MASK_SFT (0x7 << 12) +#define TDM_FIX_VALUE_SEL_SFT 16 +#define TDM_FIX_VALUE_SEL_MASK 0x1 +#define TDM_FIX_VALUE_SEL_MASK_SFT (0x1 << 16) +#define TDM_I2S_LOOPBACK_SFT 20 +#define TDM_I2S_LOOPBACK_MASK 0x1 +#define TDM_I2S_LOOPBACK_MASK_SFT (0x1 << 20) +#define TDM_I2S_LOOPBACK_CH_SFT 21 +#define TDM_I2S_LOOPBACK_CH_MASK 0x3 +#define TDM_I2S_LOOPBACK_CH_MASK_SFT (0x3 << 21) +#define TDM_USE_SINEGEN_INPUT_SFT 23 +#define TDM_USE_SINEGEN_INPUT_MASK 0x1 +#define TDM_USE_SINEGEN_INPUT_MASK_SFT (0x1 << 23) +#define TDM_FIX_VALUE_SFT 24 +#define TDM_FIX_VALUE_MASK 0xff +#define TDM_FIX_VALUE_MASK_SFT (0xff << 24) + +/* AFE_TDM_CON3 */ +#define TDM_OUT_SEL_DOMAIN_SFT 29 +#define TDM_OUT_SEL_DOMAIN_MASK 0x7 +#define TDM_OUT_SEL_DOMAIN_MASK_SFT (0x7 << 29) +#define TDM_OUT_SEL_FS_SFT 24 +#define TDM_OUT_SEL_FS_MASK 0x1f +#define TDM_OUT_SEL_FS_MASK_SFT (0x1f << 24) +#define TDM_OUT_MON_SEL_SFT 3 +#define TDM_OUT_MON_SEL_MASK 0x1 +#define TDM_OUT_MON_SEL_MASK_SFT (0x1 << 3) +#define RG_TDM_OUT_ASYNC_FIFO_SOFT_RST_EN_SFT 2 +#define RG_TDM_OUT_ASYNC_FIFO_SOFT_RST_EN_MASK 0x1 +#define RG_TDM_OUT_ASYNC_FIFO_SOFT_RST_EN_MASK_SFT (0x1 << 2) +#define RG_TDM_OUT_ASYNC_FIFO_SOFT_RST_SFT 1 +#define RG_TDM_OUT_ASYNC_FIFO_SOFT_RST_MASK 0x1 +#define RG_TDM_OUT_ASYNC_FIFO_SOFT_RST_MASK_SFT (0x1 << 1) +#define TDM_UPDATE_EN_SEL_SFT 0 +#define TDM_UPDATE_EN_SEL_MASK 0x1 +#define TDM_UPDATE_EN_SEL_MASK_SFT (0x1 << 0) + +/* AFE_TDM_OUT_MON */ +#define AFE_TDM_OUT_MON_SFT 0 +#define AFE_TDM_OUT_MON_MASK 0xffffffff +#define AFE_TDM_OUT_MON_MASK_SFT (0xffffffff << 0) + +/* AFE_HDMI_CONN0 */ +#define HDMI_O_7_SFT 21 +#define HDMI_O_7_MASK 0x7 +#define HDMI_O_7_MASK_SFT (0x7 << 21) +#define HDMI_O_6_SFT 18 +#define HDMI_O_6_MASK 0x7 +#define HDMI_O_6_MASK_SFT (0x7 << 18) +#define HDMI_O_5_SFT 15 +#define HDMI_O_5_MASK 0x7 +#define HDMI_O_5_MASK_SFT (0x7 << 15) +#define HDMI_O_4_SFT 12 +#define HDMI_O_4_MASK 0x7 +#define HDMI_O_4_MASK_SFT (0x7 << 12) +#define HDMI_O_3_SFT 9 +#define HDMI_O_3_MASK 0x7 +#define HDMI_O_3_MASK_SFT (0x7 << 9) +#define HDMI_O_2_SFT 6 +#define HDMI_O_2_MASK 0x7 +#define HDMI_O_2_MASK_SFT (0x7 << 6) +#define HDMI_O_1_SFT 3 +#define HDMI_O_1_MASK 0x7 +#define HDMI_O_1_MASK_SFT (0x7 << 3) +#define HDMI_O_0_SFT 0 +#define HDMI_O_0_MASK 0x7 +#define HDMI_O_0_MASK_SFT (0x7 << 0) + +/* AFE_TDM_TOP_IP_VERSION */ +#define AFE_TDM_TOP_IP_VERSION_SFT 0 +#define AFE_TDM_TOP_IP_VERSION_MASK 0xffffffff +#define AFE_TDM_TOP_IP_VERSION_MASK_SFT (0xffffffff << 0) + +/* AFE_CBIP_CFG0 */ +#define CBIP_TOP_SLV_MUX_WAY_EN_SFT 16 +#define CBIP_TOP_SLV_MUX_WAY_EN_MASK 0xffff +#define CBIP_TOP_SLV_MUX_WAY_EN_MASK_SFT (0xffff << 16) +#define RESERVED_04_SFT 15 +#define RESERVED_04_MASK 0x1 +#define RESERVED_04_MASK_SFT (0x1 << 15) +#define CBIP_ASYNC_MST_RG_FIFO_THRE_SFT 13 +#define CBIP_ASYNC_MST_RG_FIFO_THRE_MASK 0x3 +#define CBIP_ASYNC_MST_RG_FIFO_THRE_MASK_SFT (0x3 << 13) +#define CBIP_ASYNC_MST_POSTWRITE_DIS_SFT 12 +#define CBIP_ASYNC_MST_POSTWRITE_DIS_MASK 0x1 +#define CBIP_ASYNC_MST_POSTWRITE_DIS_MASK_SFT (0x1 << 12) +#define RESERVED_03_SFT 11 +#define RESERVED_03_MASK 0x1 +#define RESERVED_03_MASK_SFT (0x1 << 11) +#define CBIP_ASYNC_SLV_RG_FIFO_THRE_SFT 9 +#define CBIP_ASYNC_SLV_RG_FIFO_THRE_MASK 0x3 +#define CBIP_ASYNC_SLV_RG_FIFO_THRE_MASK_SFT (0x3 << 9) +#define CBIP_ASYNC_SLV_POSTWRITE_DIS_SFT 8 +#define CBIP_ASYNC_SLV_POSTWRITE_DIS_MASK 0x1 +#define CBIP_ASYNC_SLV_POSTWRITE_DIS_MASK_SFT (0x1 << 8) +#define AUDIOSYS_BUSY_SFT 7 +#define AUDIOSYS_BUSY_MASK 0x1 +#define AUDIOSYS_BUSY_MASK_SFT (0x1 << 7) +#define CBIP_SLV_DECODER_ERR_FLAG_EN_SFT 6 +#define CBIP_SLV_DECODER_ERR_FLAG_EN_MASK 0x1 +#define CBIP_SLV_DECODER_ERR_FLAG_EN_MASK_SFT (0x1 << 6) +#define CBIP_SLV_DECODER_SLAVE_WAY_EN_SFT 5 +#define CBIP_SLV_DECODER_SLAVE_WAY_EN_MASK 0x1 +#define CBIP_SLV_DECODER_SLAVE_WAY_EN_MASK_SFT (0x1 << 5) +#define APB_R2T_SFT 3 +#define APB_R2T_MASK 0x1 +#define APB_R2T_MASK_SFT (0x1 << 3) +#define APB_W2T_SFT 2 +#define APB_W2T_MASK 0x1 +#define APB_W2T_MASK_SFT (0x1 << 2) +#define AHB_IDLE_EN_INT_SFT 1 +#define AHB_IDLE_EN_INT_MASK 0x1 +#define AHB_IDLE_EN_INT_MASK_SFT (0x1 << 1) +#define AHB_IDLE_EN_EXT_SFT 0 +#define AHB_IDLE_EN_EXT_MASK 0x1 +#define AHB_IDLE_EN_EXT_MASK_SFT (0x1 << 0) + +/* AFE_CBIP_SLV_DECODER_MON0 */ +#define CBIP_SLV_DECODER_ERR_DOMAIN_SFT 4 +#define CBIP_SLV_DECODER_ERR_DOMAIN_MASK 0x1 +#define CBIP_SLV_DECODER_ERR_DOMAIN_MASK_SFT (0x1 << 4) +#define CBIP_SLV_DECODER_ERR_ID_SFT 3 +#define CBIP_SLV_DECODER_ERR_ID_MASK 0x1 +#define CBIP_SLV_DECODER_ERR_ID_MASK_SFT (0x1 << 3) +#define CBIP_SLV_DECODER_ERR_RW_SFT 2 +#define CBIP_SLV_DECODER_ERR_RW_MASK 0x1 +#define CBIP_SLV_DECODER_ERR_RW_MASK_SFT (0x1 << 2) +#define CBIP_SLV_DECODER_ERR_DECERR_SFT 1 +#define CBIP_SLV_DECODER_ERR_DECERR_MASK 0x1 +#define CBIP_SLV_DECODER_ERR_DECERR_MASK_SFT (0x1 << 1) +#define CBIP_SLV_DECODER_CTRL_UPDATE_STATUS_SFT 0 +#define CBIP_SLV_DECODER_CTRL_UPDATE_STATUS_MASK 0x1 +#define CBIP_SLV_DECODER_CTRL_UPDATE_STATUS_MASK_SFT (0x1 << 0) + +/* AFE_CBIP_SLV_DECODER_MON1 */ +#define CBIP_SLV_DECODER_ERR_ADDR_SFT 0 +#define CBIP_SLV_DECODER_ERR_ADDR_MASK 0xffffffff +#define CBIP_SLV_DECODER_ERR_ADDR_MASK_SFT (0xffffffff << 0) + +/* AFE_CBIP_SLV_MUX_MON_CFG */ +#define CBIP_SLV_MUX_ERR_FLAG_EN_SFT 3 +#define CBIP_SLV_MUX_ERR_FLAG_EN_MASK 0x1 +#define CBIP_SLV_MUX_ERR_FLAG_EN_MASK_SFT (0x1 << 3) +#define CBIP_SLV_MUX_REG_SLAVE_WAY_EN_SFT 2 +#define CBIP_SLV_MUX_REG_SLAVE_WAY_EN_MASK 0x1 +#define CBIP_SLV_MUX_REG_SLAVE_WAY_EN_MASK_SFT (0x1 << 2) +#define CBIP_SLV_MUX_REG_LAYER_WAY_EN_SFT 0 +#define CBIP_SLV_MUX_REG_LAYER_WAY_EN_MASK 0x3 +#define CBIP_SLV_MUX_REG_LAYER_WAY_EN_MASK_SFT (0x3 << 0) + +/* AFE_CBIP_SLV_MUX_MON0 */ +#define CBIP_SLV_MUX_ERR_DOMAIN_SFT 8 +#define CBIP_SLV_MUX_ERR_DOMAIN_MASK 0x1 +#define CBIP_SLV_MUX_ERR_DOMAIN_MASK_SFT (0x1 << 8) +#define CBIP_SLV_MUX_ERR_ID_SFT 7 +#define CBIP_SLV_MUX_ERR_ID_MASK 0x1 +#define CBIP_SLV_MUX_ERR_ID_MASK_SFT (0x1 << 7) +#define CBIP_SLV_MUX_ERR_RD_SFT 6 +#define CBIP_SLV_MUX_ERR_RD_MASK 0x1 +#define CBIP_SLV_MUX_ERR_RD_MASK_SFT (0x1 << 6) +#define CBIP_SLV_MUX_ERR_WR_SFT 5 +#define CBIP_SLV_MUX_ERR_WR_MASK 0x1 +#define CBIP_SLV_MUX_ERR_WR_MASK_SFT (0x1 << 5) +#define CBIP_SLV_MUX_ERR_EN_SLV_SFT 4 +#define CBIP_SLV_MUX_ERR_EN_SLV_MASK 0x1 +#define CBIP_SLV_MUX_ERR_EN_SLV_MASK_SFT (0x1 << 4) +#define CBIP_SLV_MUX_ERR_EN_MST_SFT 2 +#define CBIP_SLV_MUX_ERR_EN_MST_MASK 0x3 +#define CBIP_SLV_MUX_ERR_EN_MST_MASK_SFT (0x3 << 2) +#define CBIP_SLV_MUX_CTRL_UPDATE_STATUS_SFT 0 +#define CBIP_SLV_MUX_CTRL_UPDATE_STATUS_MASK 0x3 +#define CBIP_SLV_MUX_CTRL_UPDATE_STATUS_MASK_SFT (0x3 << 0) + +/* AFE_CBIP_SLV_MUX_MON1 */ +#define CBIP_SLV_MUX_ERR_ADDR_SFT 0 +#define CBIP_SLV_MUX_ERR_ADDR_MASK 0xffffffff +#define CBIP_SLV_MUX_ERR_ADDR_MASK_SFT (0xffffffff << 0) + +/* AFE_MEMIF_CON0 */ +#define CPU_COMPACT_MODE_SFT 2 +#define CPU_COMPACT_MODE_MASK 0x1 +#define CPU_COMPACT_MODE_MASK_SFT (0x1 << 2) +#define CPU_HD_ALIGN_SFT 1 +#define CPU_HD_ALIGN_MASK 0x1 +#define CPU_HD_ALIGN_MASK_SFT (0x1 << 1) +#define SYSRAM_SIGN_SFT 0 +#define SYSRAM_SIGN_MASK 0x1 +#define SYSRAM_SIGN_MASK_SFT (0x1 << 0) + +/* AFE_MEMIF_ONE_HEART */ +#define DL_ONE_HEART_ON_2_SFT 2 +#define DL_ONE_HEART_ON_2_MASK 0x1 +#define DL_ONE_HEART_ON_2_MASK_SFT (0x1 << 2) +#define DL_ONE_HEART_ON_1_SFT 1 +#define DL_ONE_HEART_ON_1_MASK 0x1 +#define DL_ONE_HEART_ON_1_MASK_SFT (0x1 << 1) +#define DL_ONE_HEART_ON_0_SFT 0 +#define DL_ONE_HEART_ON_0_MASK 0x1 +#define DL_ONE_HEART_ON_0_MASK_SFT (0x1 << 0) + +/* AFE_DL0_BASE_MSB */ +#define DL0_BASE_ADDR_MSB_SFT 0 +#define DL0_BASE_ADDR_MSB_MASK 0x1ff +#define DL0_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_DL0_BASE */ +#define DL0_BASE_ADDR_SFT 4 +#define DL0_BASE_ADDR_MASK 0xfffffff +#define DL0_BASE_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_DL0_CUR_MSB */ +#define DL0_CUR_PTR_MSB_SFT 0 +#define DL0_CUR_PTR_MSB_MASK 0x1ff +#define DL0_CUR_PTR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_DL0_CUR */ +#define DL0_CUR_PTR_SFT 0 +#define DL0_CUR_PTR_MASK 0xffffffff +#define DL0_CUR_PTR_MASK_SFT (0xffffffff << 0) + +/* AFE_DL0_END_MSB */ +#define DL0_END_ADDR_MSB_SFT 0 +#define DL0_END_ADDR_MSB_MASK 0x1ff +#define DL0_END_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_DL0_END */ +#define DL0_END_ADDR_SFT 4 +#define DL0_END_ADDR_MASK 0xfffffff +#define DL0_END_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_DL0_RCH_MON */ +#define DL0_RCH_DATA_SFT 0 +#define DL0_RCH_DATA_MASK 0xffffffff +#define DL0_RCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_DL0_LCH_MON */ +#define DL0_LCH_DATA_SFT 0 +#define DL0_LCH_DATA_MASK 0xffffffff +#define DL0_LCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_DL0_CON0 */ +#define DL0_ON_SFT 28 +#define DL0_ON_MASK 0x1 +#define DL0_ON_MASK_SFT (0x1 << 28) +#define DL0_ONE_HEART_SEL_SFT 22 +#define DL0_ONE_HEART_SEL_MASK 0x3 +#define DL0_ONE_HEART_SEL_MASK_SFT (0x3 << 22) +#define DL0_MINLEN_SFT 20 +#define DL0_MINLEN_MASK 0x3 +#define DL0_MINLEN_MASK_SFT (0x3 << 20) +#define DL0_MAXLEN_SFT 16 +#define DL0_MAXLEN_MASK 0x3 +#define DL0_MAXLEN_MASK_SFT (0x3 << 16) +#define DL0_SEL_DOMAIN_SFT 13 +#define DL0_SEL_DOMAIN_MASK 0x7 +#define DL0_SEL_DOMAIN_MASK_SFT (0x7 << 13) +#define DL0_SEL_FS_SFT 8 +#define DL0_SEL_FS_MASK 0x1f +#define DL0_SEL_FS_MASK_SFT (0x1f << 8) +#define DL0_SW_CLEAR_BUF_EMPTY_SFT 7 +#define DL0_SW_CLEAR_BUF_EMPTY_MASK 0x1 +#define DL0_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 7) +#define DL0_PBUF_SIZE_SFT 5 +#define DL0_PBUF_SIZE_MASK 0x3 +#define DL0_PBUF_SIZE_MASK_SFT (0x3 << 5) +#define DL0_MONO_SFT 4 +#define DL0_MONO_MASK 0x1 +#define DL0_MONO_MASK_SFT (0x1 << 4) +#define DL0_NORMAL_MODE_SFT 3 +#define DL0_NORMAL_MODE_MASK 0x1 +#define DL0_NORMAL_MODE_MASK_SFT (0x1 << 3) +#define DL0_HALIGN_SFT 2 +#define DL0_HALIGN_MASK 0x1 +#define DL0_HALIGN_MASK_SFT (0x1 << 2) +#define DL0_HD_MODE_SFT 0 +#define DL0_HD_MODE_MASK 0x3 +#define DL0_HD_MODE_MASK_SFT (0x3 << 0) + +/* AFE_DL1_BASE_MSB */ +#define DL1_BASE_ADDR_MSB_SFT 0 +#define DL1_BASE_ADDR_MSB_MASK 0x1ff +#define DL1_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_DL1_BASE */ +#define DL1_BASE_ADDR_SFT 4 +#define DL1_BASE_ADDR_MASK 0xfffffff +#define DL1_BASE_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_DL1_CUR_MSB */ +#define DL1_CUR_PTR_MSB_SFT 0 +#define DL1_CUR_PTR_MSB_MASK 0x1ff +#define DL1_CUR_PTR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_DL1_CUR */ +#define DL1_CUR_PTR_SFT 0 +#define DL1_CUR_PTR_MASK 0xffffffff +#define DL1_CUR_PTR_MASK_SFT (0xffffffff << 0) + +/* AFE_DL1_END_MSB */ +#define DL1_END_ADDR_MSB_SFT 0 +#define DL1_END_ADDR_MSB_MASK 0x1ff +#define DL1_END_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_DL1_END */ +#define DL1_END_ADDR_SFT 4 +#define DL1_END_ADDR_MASK 0xfffffff +#define DL1_END_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_DL1_RCH_MON */ +#define DL1_RCH_DATA_SFT 0 +#define DL1_RCH_DATA_MASK 0xffffffff +#define DL1_RCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_DL1_LCH_MON */ +#define DL1_LCH_DATA_SFT 0 +#define DL1_LCH_DATA_MASK 0xffffffff +#define DL1_LCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_DL1_CON0 */ +#define DL1_ON_SFT 28 +#define DL1_ON_MASK 0x1 +#define DL1_ON_MASK_SFT (0x1 << 28) +#define DL1_ONE_HEART_SEL_SFT 22 +#define DL1_ONE_HEART_SEL_MASK 0x3 +#define DL1_ONE_HEART_SEL_MASK_SFT (0x3 << 22) +#define DL1_MINLEN_SFT 20 +#define DL1_MINLEN_MASK 0x3 +#define DL1_MINLEN_MASK_SFT (0x3 << 20) +#define DL1_MAXLEN_SFT 16 +#define DL1_MAXLEN_MASK 0x3 +#define DL1_MAXLEN_MASK_SFT (0x3 << 16) +#define DL1_SEL_DOMAIN_SFT 13 +#define DL1_SEL_DOMAIN_MASK 0x7 +#define DL1_SEL_DOMAIN_MASK_SFT (0x7 << 13) +#define DL1_SEL_FS_SFT 8 +#define DL1_SEL_FS_MASK 0x1f +#define DL1_SEL_FS_MASK_SFT (0x1f << 8) +#define DL1_SW_CLEAR_BUF_EMPTY_SFT 7 +#define DL1_SW_CLEAR_BUF_EMPTY_MASK 0x1 +#define DL1_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 7) +#define DL1_PBUF_SIZE_SFT 5 +#define DL1_PBUF_SIZE_MASK 0x3 +#define DL1_PBUF_SIZE_MASK_SFT (0x3 << 5) +#define DL1_MONO_SFT 4 +#define DL1_MONO_MASK 0x1 +#define DL1_MONO_MASK_SFT (0x1 << 4) +#define DL1_NORMAL_MODE_SFT 3 +#define DL1_NORMAL_MODE_MASK 0x1 +#define DL1_NORMAL_MODE_MASK_SFT (0x1 << 3) +#define DL1_HALIGN_SFT 2 +#define DL1_HALIGN_MASK 0x1 +#define DL1_HALIGN_MASK_SFT (0x1 << 2) +#define DL1_HD_MODE_SFT 0 +#define DL1_HD_MODE_MASK 0x3 +#define DL1_HD_MODE_MASK_SFT (0x3 << 0) + +/* AFE_DL2_BASE_MSB */ +#define DL2_BASE__ADDR_MSB_SFT 0 +#define DL2_BASE__ADDR_MSB_MASK 0x1ff +#define DL2_BASE__ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_DL2_BASE */ +#define DL2_BASE_ADDR_SFT 4 +#define DL2_BASE_ADDR_MASK 0xfffffff +#define DL2_BASE_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_DL2_CUR_MSB */ +#define DL2_CUR_PTR_MSB_SFT 0 +#define DL2_CUR_PTR_MSB_MASK 0x1ff +#define DL2_CUR_PTR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_DL2_CUR */ +#define DL2_CUR_PTR_SFT 0 +#define DL2_CUR_PTR_MASK 0xffffffff +#define DL2_CUR_PTR_MASK_SFT (0xffffffff << 0) + +/* AFE_DL2_END_MSB */ +#define DL2_END_ADDR_MSB_SFT 0 +#define DL2_END_ADDR_MSB_MASK 0x1ff +#define DL2_END_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_DL2_END */ +#define DL2_END_ADDR_SFT 4 +#define DL2_END_ADDR_MASK 0xfffffff +#define DL2_END_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_DL2_RCH_MON */ +#define DL2_RCH_DATA_SFT 0 +#define DL2_RCH_DATA_MASK 0xffffffff +#define DL2_RCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_DL2_LCH_MON */ +#define DL2_LCH_DATA_SFT 0 +#define DL2_LCH_DATA_MASK 0xffffffff +#define DL2_LCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_DL2_CON0 */ +#define DL2_ON_SFT 28 +#define DL2_ON_MASK 0x1 +#define DL2_ON_MASK_SFT (0x1 << 28) +#define DL2_ONE_HEART_SEL_SFT 22 +#define DL2_ONE_HEART_SEL_MASK 0x3 +#define DL2_ONE_HEART_SEL_MASK_SFT (0x3 << 22) +#define DL2_MINLEN_SFT 20 +#define DL2_MINLEN_MASK 0x3 +#define DL2_MINLEN_MASK_SFT (0x3 << 20) +#define DL2_MAXLEN_SFT 16 +#define DL2_MAXLEN_MASK 0x3 +#define DL2_MAXLEN_MASK_SFT (0x3 << 16) +#define DL2_SEL_DOMAIN_SFT 13 +#define DL2_SEL_DOMAIN_MASK 0x7 +#define DL2_SEL_DOMAIN_MASK_SFT (0x7 << 13) +#define DL2_SEL_FS_SFT 8 +#define DL2_SEL_FS_MASK 0x1f +#define DL2_SEL_FS_MASK_SFT (0x1f << 8) +#define DL2_SW_CLEAR_BUF_EMPTY_SFT 7 +#define DL2_SW_CLEAR_BUF_EMPTY_MASK 0x1 +#define DL2_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 7) +#define DL2_PBUF_SIZE_SFT 5 +#define DL2_PBUF_SIZE_MASK 0x3 +#define DL2_PBUF_SIZE_MASK_SFT (0x3 << 5) +#define DL2_MONO_SFT 4 +#define DL2_MONO_MASK 0x1 +#define DL2_MONO_MASK_SFT (0x1 << 4) +#define DL2_NORMAL_MODE_SFT 3 +#define DL2_NORMAL_MODE_MASK 0x1 +#define DL2_NORMAL_MODE_MASK_SFT (0x1 << 3) +#define DL2_HALIGN_SFT 2 +#define DL2_HALIGN_MASK 0x1 +#define DL2_HALIGN_MASK_SFT (0x1 << 2) +#define DL2_HD_MODE_SFT 0 +#define DL2_HD_MODE_MASK 0x3 +#define DL2_HD_MODE_MASK_SFT (0x3 << 0) + +/* AFE_DL3_BASE_MSB */ +#define DL3_BASE__ADDR_MSB_SFT 0 +#define DL3_BASE__ADDR_MSB_MASK 0x1ff +#define DL3_BASE__ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_DL3_BASE */ +#define DL3_BASE_ADDR_SFT 4 +#define DL3_BASE_ADDR_MASK 0xfffffff +#define DL3_BASE_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_DL3_CUR_MSB */ +#define DL3_CUR_PTR_MSB_SFT 0 +#define DL3_CUR_PTR_MSB_MASK 0x1ff +#define DL3_CUR_PTR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_DL3_CUR */ +#define DL3_CUR_PTR_SFT 0 +#define DL3_CUR_PTR_MASK 0xffffffff +#define DL3_CUR_PTR_MASK_SFT (0xffffffff << 0) + +/* AFE_DL3_END_MSB */ +#define DL3_END_ADDR_MSB_SFT 0 +#define DL3_END_ADDR_MSB_MASK 0x1ff +#define DL3_END_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_DL3_END */ +#define DL3_END_ADDR_SFT 4 +#define DL3_END_ADDR_MASK 0xfffffff +#define DL3_END_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_DL3_RCH_MON */ +#define DL3_RCH_DATA_SFT 0 +#define DL3_RCH_DATA_MASK 0xffffffff +#define DL3_RCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_DL3_LCH_MON */ +#define DL3_LCH_DATA_SFT 0 +#define DL3_LCH_DATA_MASK 0xffffffff +#define DL3_LCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_DL3_CON0 */ +#define DL3_ON_SFT 28 +#define DL3_ON_MASK 0x1 +#define DL3_ON_MASK_SFT (0x1 << 28) +#define DL3_ONE_HEART_SEL_SFT 22 +#define DL3_ONE_HEART_SEL_MASK 0x3 +#define DL3_ONE_HEART_SEL_MASK_SFT (0x3 << 22) +#define DL3_MINLEN_SFT 20 +#define DL3_MINLEN_MASK 0x3 +#define DL3_MINLEN_MASK_SFT (0x3 << 20) +#define DL3_MAXLEN_SFT 16 +#define DL3_MAXLEN_MASK 0x3 +#define DL3_MAXLEN_MASK_SFT (0x3 << 16) +#define DL3_SEL_DOMAIN_SFT 13 +#define DL3_SEL_DOMAIN_MASK 0x7 +#define DL3_SEL_DOMAIN_MASK_SFT (0x7 << 13) +#define DL3_SEL_FS_SFT 8 +#define DL3_SEL_FS_MASK 0x1f +#define DL3_SEL_FS_MASK_SFT (0x1f << 8) +#define DL3_SW_CLEAR_BUF_EMPTY_SFT 7 +#define DL3_SW_CLEAR_BUF_EMPTY_MASK 0x1 +#define DL3_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 7) +#define DL3_PBUF_SIZE_SFT 5 +#define DL3_PBUF_SIZE_MASK 0x3 +#define DL3_PBUF_SIZE_MASK_SFT (0x3 << 5) +#define DL3_MONO_SFT 4 +#define DL3_MONO_MASK 0x1 +#define DL3_MONO_MASK_SFT (0x1 << 4) +#define DL3_NORMAL_MODE_SFT 3 +#define DL3_NORMAL_MODE_MASK 0x1 +#define DL3_NORMAL_MODE_MASK_SFT (0x1 << 3) +#define DL3_HALIGN_SFT 2 +#define DL3_HALIGN_MASK 0x1 +#define DL3_HALIGN_MASK_SFT (0x1 << 2) +#define DL3_HD_MODE_SFT 0 +#define DL3_HD_MODE_MASK 0x3 +#define DL3_HD_MODE_MASK_SFT (0x3 << 0) + +/* AFE_DL4_BASE_MSB */ +#define DL4_BASE__ADDR_MSB_SFT 0 +#define DL4_BASE__ADDR_MSB_MASK 0x1ff +#define DL4_BASE__ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_DL4_BASE */ +#define DL4_BASE_ADDR_SFT 4 +#define DL4_BASE_ADDR_MASK 0xfffffff +#define DL4_BASE_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_DL4_CUR_MSB */ +#define DL4_CUR_PTR_MSB_SFT 0 +#define DL4_CUR_PTR_MSB_MASK 0x1ff +#define DL4_CUR_PTR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_DL4_CUR */ +#define DL4_CUR_PTR_SFT 0 +#define DL4_CUR_PTR_MASK 0xffffffff +#define DL4_CUR_PTR_MASK_SFT (0xffffffff << 0) + +/* AFE_DL4_END_MSB */ +#define DL4_END_ADDR_MSB_SFT 0 +#define DL4_END_ADDR_MSB_MASK 0x1ff +#define DL4_END_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_DL4_END */ +#define DL4_END_ADDR_SFT 4 +#define DL4_END_ADDR_MASK 0xfffffff +#define DL4_END_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_DL4_RCH_MON */ +#define DL4_RCH_DATA_SFT 0 +#define DL4_RCH_DATA_MASK 0xffffffff +#define DL4_RCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_DL4_LCH_MON */ +#define DL4_LCH_DATA_SFT 0 +#define DL4_LCH_DATA_MASK 0xffffffff +#define DL4_LCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_DL4_CON0 */ +#define DL4_ON_SFT 28 +#define DL4_ON_MASK 0x1 +#define DL4_ON_MASK_SFT (0x1 << 28) +#define DL4_ONE_HEART_SEL_SFT 22 +#define DL4_ONE_HEART_SEL_MASK 0x3 +#define DL4_ONE_HEART_SEL_MASK_SFT (0x3 << 22) +#define DL4_MINLEN_SFT 20 +#define DL4_MINLEN_MASK 0x3 +#define DL4_MINLEN_MASK_SFT (0x3 << 20) +#define DL4_MAXLEN_SFT 16 +#define DL4_MAXLEN_MASK 0x3 +#define DL4_MAXLEN_MASK_SFT (0x3 << 16) +#define DL4_SEL_DOMAIN_SFT 13 +#define DL4_SEL_DOMAIN_MASK 0x7 +#define DL4_SEL_DOMAIN_MASK_SFT (0x7 << 13) +#define DL4_SEL_FS_SFT 8 +#define DL4_SEL_FS_MASK 0x1f +#define DL4_SEL_FS_MASK_SFT (0x1f << 8) +#define DL4_SW_CLEAR_BUF_EMPTY_SFT 7 +#define DL4_SW_CLEAR_BUF_EMPTY_MASK 0x1 +#define DL4_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 7) +#define DL4_PBUF_SIZE_SFT 5 +#define DL4_PBUF_SIZE_MASK 0x3 +#define DL4_PBUF_SIZE_MASK_SFT (0x3 << 5) +#define DL4_MONO_SFT 4 +#define DL4_MONO_MASK 0x1 +#define DL4_MONO_MASK_SFT (0x1 << 4) +#define DL4_NORMAL_MODE_SFT 3 +#define DL4_NORMAL_MODE_MASK 0x1 +#define DL4_NORMAL_MODE_MASK_SFT (0x1 << 3) +#define DL4_HALIGN_SFT 2 +#define DL4_HALIGN_MASK 0x1 +#define DL4_HALIGN_MASK_SFT (0x1 << 2) +#define DL4_HD_MODE_SFT 0 +#define DL4_HD_MODE_MASK 0x3 +#define DL4_HD_MODE_MASK_SFT (0x3 << 0) + +/* AFE_DL5_BASE_MSB */ +#define DL5_BASE__ADDR_MSB_SFT 0 +#define DL5_BASE__ADDR_MSB_MASK 0x1ff +#define DL5_BASE__ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_DL5_BASE */ +#define DL5_BASE_ADDR_SFT 4 +#define DL5_BASE_ADDR_MASK 0xfffffff +#define DL5_BASE_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_DL5_CUR_MSB */ +#define DL5_CUR_PTR_MSB_SFT 0 +#define DL5_CUR_PTR_MSB_MASK 0x1ff +#define DL5_CUR_PTR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_DL5_CUR */ +#define DL5_CUR_PTR_SFT 0 +#define DL5_CUR_PTR_MASK 0xffffffff +#define DL5_CUR_PTR_MASK_SFT (0xffffffff << 0) + +/* AFE_DL5_END_MSB */ +#define DL5_END_ADDR_MSB_SFT 0 +#define DL5_END_ADDR_MSB_MASK 0x1ff +#define DL5_END_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_DL5_END */ +#define DL5_END_ADDR_SFT 4 +#define DL5_END_ADDR_MASK 0xfffffff +#define DL5_END_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_DL5_RCH_MON */ +#define DL5_RCH_DATA_SFT 0 +#define DL5_RCH_DATA_MASK 0xffffffff +#define DL5_RCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_DL5_LCH_MON */ +#define DL5_LCH_DATA_SFT 0 +#define DL5_LCH_DATA_MASK 0xffffffff +#define DL5_LCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_DL5_CON0 */ +#define DL5_ON_SFT 28 +#define DL5_ON_MASK 0x1 +#define DL5_ON_MASK_SFT (0x1 << 28) +#define DL5_ONE_HEART_SEL_SFT 22 +#define DL5_ONE_HEART_SEL_MASK 0x3 +#define DL5_ONE_HEART_SEL_MASK_SFT (0x3 << 22) +#define DL5_MINLEN_SFT 20 +#define DL5_MINLEN_MASK 0x3 +#define DL5_MINLEN_MASK_SFT (0x3 << 20) +#define DL5_MAXLEN_SFT 16 +#define DL5_MAXLEN_MASK 0x3 +#define DL5_MAXLEN_MASK_SFT (0x3 << 16) +#define DL5_SEL_DOMAIN_SFT 13 +#define DL5_SEL_DOMAIN_MASK 0x7 +#define DL5_SEL_DOMAIN_MASK_SFT (0x7 << 13) +#define DL5_SEL_FS_SFT 8 +#define DL5_SEL_FS_MASK 0x1f +#define DL5_SEL_FS_MASK_SFT (0x1f << 8) +#define DL5_SW_CLEAR_BUF_EMPTY_SFT 7 +#define DL5_SW_CLEAR_BUF_EMPTY_MASK 0x1 +#define DL5_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 7) +#define DL5_PBUF_SIZE_SFT 5 +#define DL5_PBUF_SIZE_MASK 0x3 +#define DL5_PBUF_SIZE_MASK_SFT (0x3 << 5) +#define DL5_MONO_SFT 4 +#define DL5_MONO_MASK 0x1 +#define DL5_MONO_MASK_SFT (0x1 << 4) +#define DL5_NORMAL_MODE_SFT 3 +#define DL5_NORMAL_MODE_MASK 0x1 +#define DL5_NORMAL_MODE_MASK_SFT (0x1 << 3) +#define DL5_HALIGN_SFT 2 +#define DL5_HALIGN_MASK 0x1 +#define DL5_HALIGN_MASK_SFT (0x1 << 2) +#define DL5_HD_MODE_SFT 0 +#define DL5_HD_MODE_MASK 0x3 +#define DL5_HD_MODE_MASK_SFT (0x3 << 0) + +/* AFE_DL6_BASE_MSB */ +#define DL6_BASE__ADDR_MSB_SFT 0 +#define DL6_BASE__ADDR_MSB_MASK 0x1ff +#define DL6_BASE__ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_DL6_BASE */ +#define DL6_BASE_ADDR_SFT 4 +#define DL6_BASE_ADDR_MASK 0xfffffff +#define DL6_BASE_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_DL6_CUR_MSB */ +#define DL6_CUR_PTR_MSB_SFT 0 +#define DL6_CUR_PTR_MSB_MASK 0x1ff +#define DL6_CUR_PTR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_DL6_CUR */ +#define DL6_CUR_PTR_SFT 0 +#define DL6_CUR_PTR_MASK 0xffffffff +#define DL6_CUR_PTR_MASK_SFT (0xffffffff << 0) + +/* AFE_DL6_END_MSB */ +#define DL6_END_ADDR_MSB_SFT 0 +#define DL6_END_ADDR_MSB_MASK 0x1ff +#define DL6_END_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_DL6_END */ +#define DL6_END_ADDR_SFT 4 +#define DL6_END_ADDR_MASK 0xfffffff +#define DL6_END_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_DL6_RCH_MON */ +#define DL6_RCH_DATA_SFT 0 +#define DL6_RCH_DATA_MASK 0xffffffff +#define DL6_RCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_DL6_LCH_MON */ +#define DL6_LCH_DATA_SFT 0 +#define DL6_LCH_DATA_MASK 0xffffffff +#define DL6_LCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_DL6_CON0 */ +#define DL6_ON_SFT 28 +#define DL6_ON_MASK 0x1 +#define DL6_ON_MASK_SFT (0x1 << 28) +#define DL6_ONE_HEART_SEL_SFT 22 +#define DL6_ONE_HEART_SEL_MASK 0x3 +#define DL6_ONE_HEART_SEL_MASK_SFT (0x3 << 22) +#define DL6_MINLEN_SFT 20 +#define DL6_MINLEN_MASK 0x3 +#define DL6_MINLEN_MASK_SFT (0x3 << 20) +#define DL6_MAXLEN_SFT 16 +#define DL6_MAXLEN_MASK 0x3 +#define DL6_MAXLEN_MASK_SFT (0x3 << 16) +#define DL6_SEL_DOMAIN_SFT 13 +#define DL6_SEL_DOMAIN_MASK 0x7 +#define DL6_SEL_DOMAIN_MASK_SFT (0x7 << 13) +#define DL6_SEL_FS_SFT 8 +#define DL6_SEL_FS_MASK 0x1f +#define DL6_SEL_FS_MASK_SFT (0x1f << 8) +#define DL6_SW_CLEAR_BUF_EMPTY_SFT 7 +#define DL6_SW_CLEAR_BUF_EMPTY_MASK 0x1 +#define DL6_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 7) +#define DL6_PBUF_SIZE_SFT 5 +#define DL6_PBUF_SIZE_MASK 0x3 +#define DL6_PBUF_SIZE_MASK_SFT (0x3 << 5) +#define DL6_MONO_SFT 4 +#define DL6_MONO_MASK 0x1 +#define DL6_MONO_MASK_SFT (0x1 << 4) +#define DL6_NORMAL_MODE_SFT 3 +#define DL6_NORMAL_MODE_MASK 0x1 +#define DL6_NORMAL_MODE_MASK_SFT (0x1 << 3) +#define DL6_HALIGN_SFT 2 +#define DL6_HALIGN_MASK 0x1 +#define DL6_HALIGN_MASK_SFT (0x1 << 2) +#define DL6_HD_MODE_SFT 0 +#define DL6_HD_MODE_MASK 0x3 +#define DL6_HD_MODE_MASK_SFT (0x3 << 0) + +/* AFE_DL7_BASE_MSB */ +#define DL7_BASE__ADDR_MSB_SFT 0 +#define DL7_BASE__ADDR_MSB_MASK 0x1ff +#define DL7_BASE__ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_DL7_BASE */ +#define DL7_BASE_ADDR_SFT 4 +#define DL7_BASE_ADDR_MASK 0xfffffff +#define DL7_BASE_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_DL7_CUR_MSB */ +#define DL7_CUR_PTR_MSB_SFT 0 +#define DL7_CUR_PTR_MSB_MASK 0x1ff +#define DL7_CUR_PTR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_DL7_CUR */ +#define DL7_CUR_PTR_SFT 0 +#define DL7_CUR_PTR_MASK 0xffffffff +#define DL7_CUR_PTR_MASK_SFT (0xffffffff << 0) + +/* AFE_DL7_END_MSB */ +#define DL7_END_ADDR_MSB_SFT 0 +#define DL7_END_ADDR_MSB_MASK 0x1ff +#define DL7_END_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_DL7_END */ +#define DL7_END_ADDR_SFT 4 +#define DL7_END_ADDR_MASK 0xfffffff +#define DL7_END_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_DL7_RCH_MON */ +#define DL7_RCH_DATA_SFT 0 +#define DL7_RCH_DATA_MASK 0xffffffff +#define DL7_RCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_DL7_LCH_MON */ +#define DL7_LCH_DATA_SFT 0 +#define DL7_LCH_DATA_MASK 0xffffffff +#define DL7_LCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_DL7_CON0 */ +#define DL7_ON_SFT 28 +#define DL7_ON_MASK 0x1 +#define DL7_ON_MASK_SFT (0x1 << 28) +#define DL7_ONE_HEART_SEL_SFT 22 +#define DL7_ONE_HEART_SEL_MASK 0x3 +#define DL7_ONE_HEART_SEL_MASK_SFT (0x3 << 22) +#define DL7_MINLEN_SFT 20 +#define DL7_MINLEN_MASK 0x3 +#define DL7_MINLEN_MASK_SFT (0x3 << 20) +#define DL7_MAXLEN_SFT 16 +#define DL7_MAXLEN_MASK 0x3 +#define DL7_MAXLEN_MASK_SFT (0x3 << 16) +#define DL7_SEL_DOMAIN_SFT 13 +#define DL7_SEL_DOMAIN_MASK 0x7 +#define DL7_SEL_DOMAIN_MASK_SFT (0x7 << 13) +#define DL7_SEL_FS_SFT 8 +#define DL7_SEL_FS_MASK 0x1f +#define DL7_SEL_FS_MASK_SFT (0x1f << 8) +#define DL7_SW_CLEAR_BUF_EMPTY_SFT 7 +#define DL7_SW_CLEAR_BUF_EMPTY_MASK 0x1 +#define DL7_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 7) +#define DL7_PBUF_SIZE_SFT 5 +#define DL7_PBUF_SIZE_MASK 0x3 +#define DL7_PBUF_SIZE_MASK_SFT (0x3 << 5) +#define DL7_MONO_SFT 4 +#define DL7_MONO_MASK 0x1 +#define DL7_MONO_MASK_SFT (0x1 << 4) +#define DL7_NORMAL_MODE_SFT 3 +#define DL7_NORMAL_MODE_MASK 0x1 +#define DL7_NORMAL_MODE_MASK_SFT (0x1 << 3) +#define DL7_HALIGN_SFT 2 +#define DL7_HALIGN_MASK 0x1 +#define DL7_HALIGN_MASK_SFT (0x1 << 2) +#define DL7_HD_MODE_SFT 0 +#define DL7_HD_MODE_MASK 0x3 +#define DL7_HD_MODE_MASK_SFT (0x3 << 0) + +/* AFE_DL8_BASE_MSB */ +#define DL8_BASE__ADDR_MSB_SFT 0 +#define DL8_BASE__ADDR_MSB_MASK 0x1ff +#define DL8_BASE__ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_DL8_BASE */ +#define DL8_BASE_ADDR_SFT 4 +#define DL8_BASE_ADDR_MASK 0xfffffff +#define DL8_BASE_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_DL8_CUR_MSB */ +#define DL8_CUR_PTR_MSB_SFT 0 +#define DL8_CUR_PTR_MSB_MASK 0x1ff +#define DL8_CUR_PTR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_DL8_CUR */ +#define DL8_CUR_PTR_SFT 0 +#define DL8_CUR_PTR_MASK 0xffffffff +#define DL8_CUR_PTR_MASK_SFT (0xffffffff << 0) + +/* AFE_DL8_END_MSB */ +#define DL8_END_ADDR_MSB_SFT 0 +#define DL8_END_ADDR_MSB_MASK 0x1ff +#define DL8_END_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_DL8_END */ +#define DL8_END_ADDR_SFT 4 +#define DL8_END_ADDR_MASK 0xfffffff +#define DL8_END_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_DL8_RCH_MON */ +#define DL8_RCH_DATA_SFT 0 +#define DL8_RCH_DATA_MASK 0xffffffff +#define DL8_RCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_DL8_LCH_MON */ +#define DL8_LCH_DATA_SFT 0 +#define DL8_LCH_DATA_MASK 0xffffffff +#define DL8_LCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_DL8_CON0 */ +#define DL8_ON_SFT 28 +#define DL8_ON_MASK 0x1 +#define DL8_ON_MASK_SFT (0x1 << 28) +#define DL8_ONE_HEART_SEL_SFT 22 +#define DL8_ONE_HEART_SEL_MASK 0x3 +#define DL8_ONE_HEART_SEL_MASK_SFT (0x3 << 22) +#define DL8_MINLEN_SFT 20 +#define DL8_MINLEN_MASK 0x3 +#define DL8_MINLEN_MASK_SFT (0x3 << 20) +#define DL8_MAXLEN_SFT 16 +#define DL8_MAXLEN_MASK 0x3 +#define DL8_MAXLEN_MASK_SFT (0x3 << 16) +#define DL8_SEL_DOMAIN_SFT 13 +#define DL8_SEL_DOMAIN_MASK 0x7 +#define DL8_SEL_DOMAIN_MASK_SFT (0x7 << 13) +#define DL8_SEL_FS_SFT 8 +#define DL8_SEL_FS_MASK 0x1f +#define DL8_SEL_FS_MASK_SFT (0x1f << 8) +#define DL8_SW_CLEAR_BUF_EMPTY_SFT 7 +#define DL8_SW_CLEAR_BUF_EMPTY_MASK 0x1 +#define DL8_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 7) +#define DL8_PBUF_SIZE_SFT 5 +#define DL8_PBUF_SIZE_MASK 0x3 +#define DL8_PBUF_SIZE_MASK_SFT (0x3 << 5) +#define DL8_MONO_SFT 4 +#define DL8_MONO_MASK 0x1 +#define DL8_MONO_MASK_SFT (0x1 << 4) +#define DL8_NORMAL_MODE_SFT 3 +#define DL8_NORMAL_MODE_MASK 0x1 +#define DL8_NORMAL_MODE_MASK_SFT (0x1 << 3) +#define DL8_HALIGN_SFT 2 +#define DL8_HALIGN_MASK 0x1 +#define DL8_HALIGN_MASK_SFT (0x1 << 2) +#define DL8_HD_MODE_SFT 0 +#define DL8_HD_MODE_MASK 0x3 +#define DL8_HD_MODE_MASK_SFT (0x3 << 0) + +/* AFE_DL_4CH_BASE_MSB */ +#define DL_4CH_BASE__ADDR_MSB_SFT 0 +#define DL_4CH_BASE__ADDR_MSB_MASK 0x1ff +#define DL_4CH_BASE__ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_DL_4CH_BASE */ +#define DL_4CH_BASE_ADDR_SFT 4 +#define DL_4CH_BASE_ADDR_MASK 0xfffffff +#define DL_4CH_BASE_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_DL_4CH_CUR_MSB */ +#define DL_4CH_CUR_PTR_MSB_SFT 0 +#define DL_4CH_CUR_PTR_MSB_MASK 0x1ff +#define DL_4CH_CUR_PTR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_DL_4CH_CUR */ +#define DL_4CH_CUR_PTR_SFT 0 +#define DL_4CH_CUR_PTR_MASK 0xffffffff +#define DL_4CH_CUR_PTR_MASK_SFT (0xffffffff << 0) + +/* AFE_DL_4CH_END_MSB */ +#define DL_4CH_END_ADDR_MSB_SFT 0 +#define DL_4CH_END_ADDR_MSB_MASK 0x1ff +#define DL_4CH_END_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_DL_4CH_END */ +#define DL_4CH_END_ADDR_SFT 4 +#define DL_4CH_END_ADDR_MASK 0xfffffff +#define DL_4CH_END_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_DL_4CH_CON0 */ +#define DL_4CH_ON_SFT 31 +#define DL_4CH_ON_MASK 0x1 +#define DL_4CH_ON_MASK_SFT (0x1 << 31) +#define DL_4CH_NUM_SFT 24 +#define DL_4CH_NUM_MASK 0x1f +#define DL_4CH_NUM_MASK_SFT (0x1f << 24) +#define DL_4CH_ONE_HEART_SEL_SFT 22 +#define DL_4CH_ONE_HEART_SEL_MASK 0x3 +#define DL_4CH_ONE_HEART_SEL_MASK_SFT (0x3 << 22) +#define DL_4CH_MINLEN_SFT 20 +#define DL_4CH_MINLEN_MASK 0x3 +#define DL_4CH_MINLEN_MASK_SFT (0x3 << 20) +#define DL_4CH_MAXLEN_SFT 16 +#define DL_4CH_MAXLEN_MASK 0x3 +#define DL_4CH_MAXLEN_MASK_SFT (0x3 << 16) +#define DL_4CH_SEL_DOMAIN_SFT 13 +#define DL_4CH_SEL_DOMAIN_MASK 0x7 +#define DL_4CH_SEL_DOMAIN_MASK_SFT (0x7 << 13) +#define DL_4CH_SEL_FS_SFT 8 +#define DL_4CH_SEL_FS_MASK 0x1f +#define DL_4CH_SEL_FS_MASK_SFT (0x1f << 8) +#define DL_4CH_BUF_EMPTY_CLR_SFT 7 +#define DL_4CH_BUF_EMPTY_CLR_MASK 0x1 +#define DL_4CH_BUF_EMPTY_CLR_MASK_SFT (0x1 << 7) +#define DL_4CH_PBUF_SIZE_SFT 5 +#define DL_4CH_PBUF_SIZE_MASK 0x3 +#define DL_4CH_PBUF_SIZE_MASK_SFT (0x3 << 5) +#define DL_4CH_HANG_CLR_SFT 4 +#define DL_4CH_HANG_CLR_MASK 0x1 +#define DL_4CH_HANG_CLR_MASK_SFT (0x1 << 4) +#define DL_4CH_NORMAL_MODE_SFT 3 +#define DL_4CH_NORMAL_MODE_MASK 0x1 +#define DL_4CH_NORMAL_MODE_MASK_SFT (0x1 << 3) +#define DL_4CH_HALIGN_SFT 2 +#define DL_4CH_HALIGN_MASK 0x1 +#define DL_4CH_HALIGN_MASK_SFT (0x1 << 2) +#define DL_4CH_HD_MODE_SFT 0 +#define DL_4CH_HD_MODE_MASK 0x3 +#define DL_4CH_HD_MODE_MASK_SFT (0x3 << 0) + +/* AFE_DL_24CH_BASE_MSB */ +#define DL_24CH_BASE__ADDR_MSB_SFT 0 +#define DL_24CH_BASE__ADDR_MSB_MASK 0x1ff +#define DL_24CH_BASE__ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_DL_24CH_BASE */ +#define DL_24CH_BASE_ADDR_SFT 4 +#define DL_24CH_BASE_ADDR_MASK 0xfffffff +#define DL_24CH_BASE_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_DL_24CH_CUR_MSB */ +#define DL_24CH_CUR_PTR_MSB_SFT 0 +#define DL_24CH_CUR_PTR_MSB_MASK 0x1ff +#define DL_24CH_CUR_PTR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_DL_24CH_CUR */ +#define DL_24CH_CUR_PTR_SFT 0 +#define DL_24CH_CUR_PTR_MASK 0xffffffff +#define DL_24CH_CUR_PTR_MASK_SFT (0xffffffff << 0) + +/* AFE_DL_24CH_END_MSB */ +#define DL_24CH_END_ADDR_MSB_SFT 0 +#define DL_24CH_END_ADDR_MSB_MASK 0x1ff +#define DL_24CH_END_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_DL_24CH_END */ +#define DL_24CH_END_ADDR_SFT 4 +#define DL_24CH_END_ADDR_MASK 0xfffffff +#define DL_24CH_END_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_DL_24CH_CON0 */ +#define DL_24CH_ON_SFT 31 +#define DL_24CH_ON_MASK 0x1 +#define DL_24CH_ON_MASK_SFT (0x1 << 31) +#define DL_24CH_NUM_SFT 24 +#define DL_24CH_NUM_MASK 0x3f +#define DL_24CH_NUM_MASK_SFT (0x3f << 24) +#define DL_24CH_ONE_HEART_SEL_SFT 22 +#define DL_24CH_ONE_HEART_SEL_MASK 0x3 +#define DL_24CH_ONE_HEART_SEL_MASK_SFT (0x3 << 22) +#define DL_24CH_MINLEN_SFT 20 +#define DL_24CH_MINLEN_MASK 0x3 +#define DL_24CH_MINLEN_MASK_SFT (0x3 << 20) +#define DL_24CH_MAXLEN_SFT 16 +#define DL_24CH_MAXLEN_MASK 0x3 +#define DL_24CH_MAXLEN_MASK_SFT (0x3 << 16) +#define DL_24CH_SEL_DOMAIN_SFT 13 +#define DL_24CH_SEL_DOMAIN_MASK 0x7 +#define DL_24CH_SEL_DOMAIN_MASK_SFT (0x7 << 13) +#define DL_24CH_SEL_FS_SFT 8 +#define DL_24CH_SEL_FS_MASK 0x1f +#define DL_24CH_SEL_FS_MASK_SFT (0x1f << 8) +#define DL_24CH_BUF_EMPTY_CLR_SFT 7 +#define DL_24CH_BUF_EMPTY_CLR_MASK 0x1 +#define DL_24CH_BUF_EMPTY_CLR_MASK_SFT (0x1 << 7) +#define DL_24CH_PBUF_SIZE_SFT 5 +#define DL_24CH_PBUF_SIZE_MASK 0x3 +#define DL_24CH_PBUF_SIZE_MASK_SFT (0x3 << 5) +#define DL_24CH_HANG_CLR_SFT 4 +#define DL_24CH_HANG_CLR_MASK 0x1 +#define DL_24CH_HANG_CLR_MASK_SFT (0x1 << 4) +#define DL_24CH_NORMAL_MODE_SFT 3 +#define DL_24CH_NORMAL_MODE_MASK 0x1 +#define DL_24CH_NORMAL_MODE_MASK_SFT (0x1 << 3) +#define DL_24CH_HALIGN_SFT 2 +#define DL_24CH_HALIGN_MASK 0x1 +#define DL_24CH_HALIGN_MASK_SFT (0x1 << 2) +#define DL_24CH_HD_MODE_SFT 0 +#define DL_24CH_HD_MODE_MASK 0x3 +#define DL_24CH_HD_MODE_MASK_SFT (0x3 << 0) + +/* AFE_DL23_BASE_MSB */ +#define DL23_BASE__ADDR_MSB_SFT 0 +#define DL23_BASE__ADDR_MSB_MASK 0x1ff +#define DL23_BASE__ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_DL23_BASE */ +#define DL23_BASE_ADDR_SFT 4 +#define DL23_BASE_ADDR_MASK 0xfffffff +#define DL23_BASE_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_DL23_CUR_MSB */ +#define DL23_CUR_PTR_MSB_SFT 0 +#define DL23_CUR_PTR_MSB_MASK 0x1ff +#define DL23_CUR_PTR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_DL23_CUR */ +#define DL23_CUR_PTR_SFT 0 +#define DL23_CUR_PTR_MASK 0xffffffff +#define DL23_CUR_PTR_MASK_SFT (0xffffffff << 0) + +/* AFE_DL23_END_MSB */ +#define DL23_END_ADDR_MSB_SFT 0 +#define DL23_END_ADDR_MSB_MASK 0x1ff +#define DL23_END_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_DL23_END */ +#define DL23_END_ADDR_SFT 4 +#define DL23_END_ADDR_MASK 0xfffffff +#define DL23_END_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_DL23_RCH_MON */ +#define DL23_RCH_DATA_SFT 0 +#define DL23_RCH_DATA_MASK 0xffffffff +#define DL23_RCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_DL23_LCH_MON */ +#define DL23_LCH_DATA_SFT 0 +#define DL23_LCH_DATA_MASK 0xffffffff +#define DL23_LCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_DL23_CON0 */ +#define DL23_ON_SFT 28 +#define DL23_ON_MASK 0x1 +#define DL23_ON_MASK_SFT (0x1 << 28) +#define DL23_ONE_HEART_SEL_SFT 22 +#define DL23_ONE_HEART_SEL_MASK 0x3 +#define DL23_ONE_HEART_SEL_MASK_SFT (0x3 << 22) +#define DL23_MINLEN_SFT 20 +#define DL23_MINLEN_MASK 0x3 +#define DL23_MINLEN_MASK_SFT (0x3 << 20) +#define DL23_MAXLEN_SFT 16 +#define DL23_MAXLEN_MASK 0x3 +#define DL23_MAXLEN_MASK_SFT (0x3 << 16) +#define DL23_SEL_DOMAIN_SFT 13 +#define DL23_SEL_DOMAIN_MASK 0x7 +#define DL23_SEL_DOMAIN_MASK_SFT (0x7 << 13) +#define DL23_SEL_FS_SFT 8 +#define DL23_SEL_FS_MASK 0x1f +#define DL23_SEL_FS_MASK_SFT (0x1f << 8) +#define DL23_SW_CLEAR_BUF_EMPTY_SFT 7 +#define DL23_SW_CLEAR_BUF_EMPTY_MASK 0x1 +#define DL23_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 7) +#define DL23_PBUF_SIZE_SFT 5 +#define DL23_PBUF_SIZE_MASK 0x3 +#define DL23_PBUF_SIZE_MASK_SFT (0x3 << 5) +#define DL23_MONO_SFT 4 +#define DL23_MONO_MASK 0x1 +#define DL23_MONO_MASK_SFT (0x1 << 4) +#define DL23_NORMAL_MODE_SFT 3 +#define DL23_NORMAL_MODE_MASK 0x1 +#define DL23_NORMAL_MODE_MASK_SFT (0x1 << 3) +#define DL23_HALIGN_SFT 2 +#define DL23_HALIGN_MASK 0x1 +#define DL23_HALIGN_MASK_SFT (0x1 << 2) +#define DL23_HD_MODE_SFT 0 +#define DL23_HD_MODE_MASK 0x3 +#define DL23_HD_MODE_MASK_SFT (0x3 << 0) + +/* AFE_DL24_BASE_MSB */ +#define DL24_BASE__ADDR_MSB_SFT 0 +#define DL24_BASE__ADDR_MSB_MASK 0x1ff +#define DL24_BASE__ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_DL24_BASE */ +#define DL24_BASE_ADDR_SFT 4 +#define DL24_BASE_ADDR_MASK 0xfffffff +#define DL24_BASE_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_DL24_CUR_MSB */ +#define DL24_CUR_PTR_MSB_SFT 0 +#define DL24_CUR_PTR_MSB_MASK 0x1ff +#define DL24_CUR_PTR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_DL24_CUR */ +#define DL24_CUR_PTR_SFT 0 +#define DL24_CUR_PTR_MASK 0xffffffff +#define DL24_CUR_PTR_MASK_SFT (0xffffffff << 0) + +/* AFE_DL24_END_MSB */ +#define DL24_END_ADDR_MSB_SFT 0 +#define DL24_END_ADDR_MSB_MASK 0x1ff +#define DL24_END_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_DL24_END */ +#define DL24_END_ADDR_SFT 4 +#define DL24_END_ADDR_MASK 0xfffffff +#define DL24_END_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_DL24_RCH_MON */ +#define DL24_RCH_DATA_SFT 0 +#define DL24_RCH_DATA_MASK 0xffffffff +#define DL24_RCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_DL24_LCH_MON */ +#define DL24_LCH_DATA_SFT 0 +#define DL24_LCH_DATA_MASK 0xffffffff +#define DL24_LCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_DL24_CON0 */ +#define DL24_ON_SFT 28 +#define DL24_ON_MASK 0x1 +#define DL24_ON_MASK_SFT (0x1 << 28) +#define DL24_ONE_HEART_SEL_SFT 22 +#define DL24_ONE_HEART_SEL_MASK 0x3 +#define DL24_ONE_HEART_SEL_MASK_SFT (0x3 << 22) +#define DL24_MINLEN_SFT 20 +#define DL24_MINLEN_MASK 0x3 +#define DL24_MINLEN_MASK_SFT (0x3 << 20) +#define DL24_MAXLEN_SFT 16 +#define DL24_MAXLEN_MASK 0x3 +#define DL24_MAXLEN_MASK_SFT (0x3 << 16) +#define DL24_SEL_DOMAIN_SFT 13 +#define DL24_SEL_DOMAIN_MASK 0x7 +#define DL24_SEL_DOMAIN_MASK_SFT (0x7 << 13) +#define DL24_SEL_FS_SFT 8 +#define DL24_SEL_FS_MASK 0x1f +#define DL24_SEL_FS_MASK_SFT (0x1f << 8) +#define DL24_SW_CLEAR_BUF_EMPTY_SFT 7 +#define DL24_SW_CLEAR_BUF_EMPTY_MASK 0x1 +#define DL24_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 7) +#define DL24_PBUF_SIZE_SFT 5 +#define DL24_PBUF_SIZE_MASK 0x3 +#define DL24_PBUF_SIZE_MASK_SFT (0x3 << 5) +#define DL24_MONO_SFT 4 +#define DL24_MONO_MASK 0x1 +#define DL24_MONO_MASK_SFT (0x1 << 4) +#define DL24_NORMAL_MODE_SFT 3 +#define DL24_NORMAL_MODE_MASK 0x1 +#define DL24_NORMAL_MODE_MASK_SFT (0x1 << 3) +#define DL24_HALIGN_SFT 2 +#define DL24_HALIGN_MASK 0x1 +#define DL24_HALIGN_MASK_SFT (0x1 << 2) +#define DL24_HD_MODE_SFT 0 +#define DL24_HD_MODE_MASK 0x3 +#define DL24_HD_MODE_MASK_SFT (0x3 << 0) + +/* AFE_DL25_BASE_MSB */ +#define DL25_BASE__ADDR_MSB_SFT 0 +#define DL25_BASE__ADDR_MSB_MASK 0x1ff +#define DL25_BASE__ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_DL25_BASE */ +#define DL25_BASE_ADDR_SFT 4 +#define DL25_BASE_ADDR_MASK 0xfffffff +#define DL25_BASE_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_DL25_CUR_MSB */ +#define DL25_CUR_PTR_MSB_SFT 0 +#define DL25_CUR_PTR_MSB_MASK 0x1ff +#define DL25_CUR_PTR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_DL25_CUR */ +#define DL25_CUR_PTR_SFT 0 +#define DL25_CUR_PTR_MASK 0xffffffff +#define DL25_CUR_PTR_MASK_SFT (0xffffffff << 0) + +/* AFE_DL25_END_MSB */ +#define DL25_END_ADDR_MSB_SFT 0 +#define DL25_END_ADDR_MSB_MASK 0x1ff +#define DL25_END_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_DL25_END */ +#define DL25_END_ADDR_SFT 4 +#define DL25_END_ADDR_MASK 0xfffffff +#define DL25_END_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_DL25_RCH_MON */ +#define DL25_RCH_DATA_SFT 0 +#define DL25_RCH_DATA_MASK 0xffffffff +#define DL25_RCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_DL25_LCH_MON */ +#define DL25_LCH_DATA_SFT 0 +#define DL25_LCH_DATA_MASK 0xffffffff +#define DL25_LCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_DL25_CON0 */ +#define DL25_ON_SFT 28 +#define DL25_ON_MASK 0x1 +#define DL25_ON_MASK_SFT (0x1 << 28) +#define DL25_ONE_HEART_SEL_SFT 22 +#define DL25_ONE_HEART_SEL_MASK 0x3 +#define DL25_ONE_HEART_SEL_MASK_SFT (0x3 << 22) +#define DL25_MINLEN_SFT 20 +#define DL25_MINLEN_MASK 0x3 +#define DL25_MINLEN_MASK_SFT (0x3 << 20) +#define DL25_MAXLEN_SFT 16 +#define DL25_MAXLEN_MASK 0x3 +#define DL25_MAXLEN_MASK_SFT (0x3 << 16) +#define DL25_SEL_DOMAIN_SFT 13 +#define DL25_SEL_DOMAIN_MASK 0x7 +#define DL25_SEL_DOMAIN_MASK_SFT (0x7 << 13) +#define DL25_SEL_FS_SFT 8 +#define DL25_SEL_FS_MASK 0x1f +#define DL25_SEL_FS_MASK_SFT (0x1f << 8) +#define DL25_SW_CLEAR_BUF_EMPTY_SFT 7 +#define DL25_SW_CLEAR_BUF_EMPTY_MASK 0x1 +#define DL25_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 7) +#define DL25_PBUF_SIZE_SFT 5 +#define DL25_PBUF_SIZE_MASK 0x3 +#define DL25_PBUF_SIZE_MASK_SFT (0x3 << 5) +#define DL25_MONO_SFT 4 +#define DL25_MONO_MASK 0x1 +#define DL25_MONO_MASK_SFT (0x1 << 4) +#define DL25_NORMAL_MODE_SFT 3 +#define DL25_NORMAL_MODE_MASK 0x1 +#define DL25_NORMAL_MODE_MASK_SFT (0x1 << 3) +#define DL25_HALIGN_SFT 2 +#define DL25_HALIGN_MASK 0x1 +#define DL25_HALIGN_MASK_SFT (0x1 << 2) +#define DL25_HD_MODE_SFT 0 +#define DL25_HD_MODE_MASK 0x3 +#define DL25_HD_MODE_MASK_SFT (0x3 << 0) + +/* AFE_DL26_BASE_MSB */ +#define DL26_BASE__ADDR_MSB_SFT 0 +#define DL26_BASE__ADDR_MSB_MASK 0x1ff +#define DL26_BASE__ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_DL26_BASE */ +#define DL26_BASE_ADDR_SFT 4 +#define DL26_BASE_ADDR_MASK 0xfffffff +#define DL26_BASE_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_DL26_CUR_MSB */ +#define DL26_CUR_PTR_MSB_SFT 0 +#define DL26_CUR_PTR_MSB_MASK 0x1ff +#define DL26_CUR_PTR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_DL26_CUR */ +#define DL26_CUR_PTR_SFT 0 +#define DL26_CUR_PTR_MASK 0xffffffff +#define DL26_CUR_PTR_MASK_SFT (0xffffffff << 0) + +/* AFE_DL26_END_MSB */ +#define DL26_END_ADDR_MSB_SFT 0 +#define DL26_END_ADDR_MSB_MASK 0x1ff +#define DL26_END_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_DL26_END */ +#define DL26_END_ADDR_SFT 4 +#define DL26_END_ADDR_MASK 0xfffffff +#define DL26_END_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_DL26_RCH_MON */ +#define DL26_RCH_DATA_SFT 0 +#define DL26_RCH_DATA_MASK 0xffffffff +#define DL26_RCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_DL26_LCH_MON */ +#define DL26_LCH_DATA_SFT 0 +#define DL26_LCH_DATA_MASK 0xffffffff +#define DL26_LCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_DL26_CON0 */ +#define DL26_ON_SFT 28 +#define DL26_ON_MASK 0x1 +#define DL26_ON_MASK_SFT (0x1 << 28) +#define DL26_ONE_HEART_SEL_SFT 22 +#define DL26_ONE_HEART_SEL_MASK 0x3 +#define DL26_ONE_HEART_SEL_MASK_SFT (0x3 << 22) +#define DL26_MINLEN_SFT 20 +#define DL26_MINLEN_MASK 0x3 +#define DL26_MINLEN_MASK_SFT (0x3 << 20) +#define DL26_MAXLEN_SFT 16 +#define DL26_MAXLEN_MASK 0x3 +#define DL26_MAXLEN_MASK_SFT (0x3 << 16) +#define DL26_SEL_DOMAIN_SFT 13 +#define DL26_SEL_DOMAIN_MASK 0x7 +#define DL26_SEL_DOMAIN_MASK_SFT (0x7 << 13) +#define DL26_SEL_FS_SFT 8 +#define DL26_SEL_FS_MASK 0x1f +#define DL26_SEL_FS_MASK_SFT (0x1f << 8) +#define DL26_SW_CLEAR_BUF_EMPTY_SFT 7 +#define DL26_SW_CLEAR_BUF_EMPTY_MASK 0x1 +#define DL26_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 7) +#define DL26_PBUF_SIZE_SFT 5 +#define DL26_PBUF_SIZE_MASK 0x3 +#define DL26_PBUF_SIZE_MASK_SFT (0x3 << 5) +#define DL26_MONO_SFT 4 +#define DL26_MONO_MASK 0x1 +#define DL26_MONO_MASK_SFT (0x1 << 4) +#define DL26_NORMAL_MODE_SFT 3 +#define DL26_NORMAL_MODE_MASK 0x1 +#define DL26_NORMAL_MODE_MASK_SFT (0x1 << 3) +#define DL26_HALIGN_SFT 2 +#define DL26_HALIGN_MASK 0x1 +#define DL26_HALIGN_MASK_SFT (0x1 << 2) +#define DL26_HD_MODE_SFT 0 +#define DL26_HD_MODE_MASK 0x3 +#define DL26_HD_MODE_MASK_SFT (0x3 << 0) + +/* AFE_VUL0_BASE_MSB */ +#define VUL0_BASE_ADDR_MSB_SFT 0 +#define VUL0_BASE_ADDR_MSB_MASK 0x1ff +#define VUL0_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_VUL0_BASE */ +#define VUL0_BASE_ADDR_SFT 4 +#define VUL0_BASE_ADDR_MASK 0xfffffff +#define VUL0_BASE_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_VUL0_CUR_MSB */ +#define VUL0_CUR_PTR_MSB_SFT 0 +#define VUL0_CUR_PTR_MSB_MASK 0x1ff +#define VUL0_CUR_PTR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_VUL0_CUR */ +#define VUL0_CUR_PTR_SFT 0 +#define VUL0_CUR_PTR_MASK 0xffffffff +#define VUL0_CUR_PTR_MASK_SFT (0xffffffff << 0) + +/* AFE_VUL0_END_MSB */ +#define VUL0_END_ADDR_MSB_SFT 0 +#define VUL0_END_ADDR_MSB_MASK 0x1ff +#define VUL0_END_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_VUL0_END */ +#define VUL0_END_ADDR_SFT 4 +#define VUL0_END_ADDR_MASK 0xfffffff +#define VUL0_END_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_VUL0_RCH_MON */ +#define VUL0_RCH_DATA_SFT 0 +#define VUL0_RCH_DATA_MASK 0xffffffff +#define VUL0_RCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_VUL0_LCH_MON */ +#define VUL0_LCH_DATA_SFT 0 +#define VUL0_LCH_DATA_MASK 0xffffffff +#define VUL0_LCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_VUL0_CON0 */ +#define VUL0_ON_SFT 28 +#define VUL0_ON_MASK 0x1 +#define VUL0_ON_MASK_SFT (0x1 << 28) +#define VUL0_MINLEN_SFT 20 +#define VUL0_MINLEN_MASK 0x3 +#define VUL0_MINLEN_MASK_SFT (0x3 << 20) +#define VUL0_MAXLEN_SFT 16 +#define VUL0_MAXLEN_MASK 0x3 +#define VUL0_MAXLEN_MASK_SFT (0x3 << 16) +#define VUL0_SEL_DOMAIN_SFT 13 +#define VUL0_SEL_DOMAIN_MASK 0x7 +#define VUL0_SEL_DOMAIN_MASK_SFT (0x7 << 13) +#define VUL0_SEL_FS_SFT 8 +#define VUL0_SEL_FS_MASK 0x1f +#define VUL0_SEL_FS_MASK_SFT (0x1f << 8) +#define VUL0_SW_CLEAR_BUF_FULL_SFT 7 +#define VUL0_SW_CLEAR_BUF_FULL_MASK 0x1 +#define VUL0_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 7) +#define VUL0_WR_SIGN_SFT 6 +#define VUL0_WR_SIGN_MASK 0x1 +#define VUL0_WR_SIGN_MASK_SFT (0x1 << 6) +#define VUL0_R_MONO_SFT 5 +#define VUL0_R_MONO_MASK 0x1 +#define VUL0_R_MONO_MASK_SFT (0x1 << 5) +#define VUL0_MONO_SFT 4 +#define VUL0_MONO_MASK 0x1 +#define VUL0_MONO_MASK_SFT (0x1 << 4) +#define VUL0_NORMAL_MODE_SFT 3 +#define VUL0_NORMAL_MODE_MASK 0x1 +#define VUL0_NORMAL_MODE_MASK_SFT (0x1 << 3) +#define VUL0_HALIGN_SFT 2 +#define VUL0_HALIGN_MASK 0x1 +#define VUL0_HALIGN_MASK_SFT (0x1 << 2) +#define VUL0_HD_MODE_SFT 0 +#define VUL0_HD_MODE_MASK 0x3 +#define VUL0_HD_MODE_MASK_SFT (0x3 << 0) + +/* AFE_VUL1_BASE_MSB */ +#define VUL1_BASE_ADDR_MSB_SFT 0 +#define VUL1_BASE_ADDR_MSB_MASK 0x1ff +#define VUL1_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_VUL1_BASE */ +#define VUL1_BASE_ADDR_SFT 4 +#define VUL1_BASE_ADDR_MASK 0xfffffff +#define VUL1_BASE_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_VUL1_CUR_MSB */ +#define VUL1_CUR_PTR_MSB_SFT 0 +#define VUL1_CUR_PTR_MSB_MASK 0x1ff +#define VUL1_CUR_PTR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_VUL1_CUR */ +#define VUL1_CUR_PTR_SFT 0 +#define VUL1_CUR_PTR_MASK 0xffffffff +#define VUL1_CUR_PTR_MASK_SFT (0xffffffff << 0) + +/* AFE_VUL1_END_MSB */ +#define VUL1_END_ADDR_MSB_SFT 0 +#define VUL1_END_ADDR_MSB_MASK 0x1ff +#define VUL1_END_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_VUL1_END */ +#define VUL1_END_ADDR_SFT 4 +#define VUL1_END_ADDR_MASK 0xfffffff +#define VUL1_END_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_VUL1_RCH_MON */ +#define VUL1_RCH_DATA_SFT 0 +#define VUL1_RCH_DATA_MASK 0xffffffff +#define VUL1_RCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_VUL1_LCH_MON */ +#define VUL1_LCH_DATA_SFT 0 +#define VUL1_LCH_DATA_MASK 0xffffffff +#define VUL1_LCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_VUL1_CON0 */ +#define VUL1_ON_SFT 28 +#define VUL1_ON_MASK 0x1 +#define VUL1_ON_MASK_SFT (0x1 << 28) +#define VUL1_MINLEN_SFT 20 +#define VUL1_MINLEN_MASK 0x3 +#define VUL1_MINLEN_MASK_SFT (0x3 << 20) +#define VUL1_MAXLEN_SFT 16 +#define VUL1_MAXLEN_MASK 0x3 +#define VUL1_MAXLEN_MASK_SFT (0x3 << 16) +#define VUL1_SEL_DOMAIN_SFT 13 +#define VUL1_SEL_DOMAIN_MASK 0x7 +#define VUL1_SEL_DOMAIN_MASK_SFT (0x7 << 13) +#define VUL1_SEL_FS_SFT 8 +#define VUL1_SEL_FS_MASK 0x1f +#define VUL1_SEL_FS_MASK_SFT (0x1f << 8) +#define VUL1_SW_CLEAR_BUF_FULL_SFT 7 +#define VUL1_SW_CLEAR_BUF_FULL_MASK 0x1 +#define VUL1_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 7) +#define VUL1_WR_SIGN_SFT 6 +#define VUL1_WR_SIGN_MASK 0x1 +#define VUL1_WR_SIGN_MASK_SFT (0x1 << 6) +#define VUL1_R_MONO_SFT 5 +#define VUL1_R_MONO_MASK 0x1 +#define VUL1_R_MONO_MASK_SFT (0x1 << 5) +#define VUL1_MONO_SFT 4 +#define VUL1_MONO_MASK 0x1 +#define VUL1_MONO_MASK_SFT (0x1 << 4) +#define VUL1_NORMAL_MODE_SFT 3 +#define VUL1_NORMAL_MODE_MASK 0x1 +#define VUL1_NORMAL_MODE_MASK_SFT (0x1 << 3) +#define VUL1_HALIGN_SFT 2 +#define VUL1_HALIGN_MASK 0x1 +#define VUL1_HALIGN_MASK_SFT (0x1 << 2) +#define VUL1_HD_MODE_SFT 0 +#define VUL1_HD_MODE_MASK 0x3 +#define VUL1_HD_MODE_MASK_SFT (0x3 << 0) + +/* AFE_VUL2_BASE_MSB */ +#define VUL2_BASE_ADDR_MSB_SFT 0 +#define VUL2_BASE_ADDR_MSB_MASK 0x1ff +#define VUL2_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_VUL2_BASE */ +#define VUL2_BASE_ADDR_SFT 4 +#define VUL2_BASE_ADDR_MASK 0xfffffff +#define VUL2_BASE_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_VUL2_CUR_MSB */ +#define VUL2_CUR_PTR_MSB_SFT 0 +#define VUL2_CUR_PTR_MSB_MASK 0x1ff +#define VUL2_CUR_PTR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_VUL2_CUR */ +#define VUL2_CUR_PTR_SFT 0 +#define VUL2_CUR_PTR_MASK 0xffffffff +#define VUL2_CUR_PTR_MASK_SFT (0xffffffff << 0) + +/* AFE_VUL2_END_MSB */ +#define VUL2_END_ADDR_MSB_SFT 0 +#define VUL2_END_ADDR_MSB_MASK 0x1ff +#define VUL2_END_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_VUL2_END */ +#define VUL2_END_ADDR_SFT 4 +#define VUL2_END_ADDR_MASK 0xfffffff +#define VUL2_END_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_VUL2_RCH_MON */ +#define VUL2_RCH_DATA_SFT 0 +#define VUL2_RCH_DATA_MASK 0xffffffff +#define VUL2_RCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_VUL2_LCH_MON */ +#define VUL2_LCH_DATA_SFT 0 +#define VUL2_LCH_DATA_MASK 0xffffffff +#define VUL2_LCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_VUL2_CON0 */ +#define VUL2_ON_SFT 28 +#define VUL2_ON_MASK 0x1 +#define VUL2_ON_MASK_SFT (0x1 << 28) +#define VUL2_MINLEN_SFT 20 +#define VUL2_MINLEN_MASK 0x3 +#define VUL2_MINLEN_MASK_SFT (0x3 << 20) +#define VUL2_MAXLEN_SFT 16 +#define VUL2_MAXLEN_MASK 0x3 +#define VUL2_MAXLEN_MASK_SFT (0x3 << 16) +#define VUL2_SEL_DOMAIN_SFT 13 +#define VUL2_SEL_DOMAIN_MASK 0x7 +#define VUL2_SEL_DOMAIN_MASK_SFT (0x7 << 13) +#define VUL2_SEL_FS_SFT 8 +#define VUL2_SEL_FS_MASK 0x1f +#define VUL2_SEL_FS_MASK_SFT (0x1f << 8) +#define VUL2_SW_CLEAR_BUF_FULL_SFT 7 +#define VUL2_SW_CLEAR_BUF_FULL_MASK 0x1 +#define VUL2_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 7) +#define VUL2_WR_SIGN_SFT 6 +#define VUL2_WR_SIGN_MASK 0x1 +#define VUL2_WR_SIGN_MASK_SFT (0x1 << 6) +#define VUL2_R_MONO_SFT 5 +#define VUL2_R_MONO_MASK 0x1 +#define VUL2_R_MONO_MASK_SFT (0x1 << 5) +#define VUL2_MONO_SFT 4 +#define VUL2_MONO_MASK 0x1 +#define VUL2_MONO_MASK_SFT (0x1 << 4) +#define VUL2_NORMAL_MODE_SFT 3 +#define VUL2_NORMAL_MODE_MASK 0x1 +#define VUL2_NORMAL_MODE_MASK_SFT (0x1 << 3) +#define VUL2_HALIGN_SFT 2 +#define VUL2_HALIGN_MASK 0x1 +#define VUL2_HALIGN_MASK_SFT (0x1 << 2) +#define VUL2_HD_MODE_SFT 0 +#define VUL2_HD_MODE_MASK 0x3 +#define VUL2_HD_MODE_MASK_SFT (0x3 << 0) + +/* AFE_VUL3_BASE_MSB */ +#define VUL3_BASE_ADDR_MSB_SFT 0 +#define VUL3_BASE_ADDR_MSB_MASK 0x1ff +#define VUL3_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_VUL3_BASE */ +#define VUL3_BASE_ADDR_SFT 4 +#define VUL3_BASE_ADDR_MASK 0xfffffff +#define VUL3_BASE_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_VUL3_CUR_MSB */ +#define VUL3_CUR_PTR_MSB_SFT 0 +#define VUL3_CUR_PTR_MSB_MASK 0x1ff +#define VUL3_CUR_PTR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_VUL3_CUR */ +#define VUL3_CUR_PTR_SFT 0 +#define VUL3_CUR_PTR_MASK 0xffffffff +#define VUL3_CUR_PTR_MASK_SFT (0xffffffff << 0) + +/* AFE_VUL3_END_MSB */ +#define VUL3_END_ADDR_MSB_SFT 0 +#define VUL3_END_ADDR_MSB_MASK 0x1ff +#define VUL3_END_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_VUL3_END */ +#define VUL3_END_ADDR_SFT 4 +#define VUL3_END_ADDR_MASK 0xfffffff +#define VUL3_END_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_VUL3_RCH_MON */ +#define VUL3_RCH_DATA_SFT 0 +#define VUL3_RCH_DATA_MASK 0xffffffff +#define VUL3_RCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_VUL3_LCH_MON */ +#define VUL3_LCH_DATA_SFT 0 +#define VUL3_LCH_DATA_MASK 0xffffffff +#define VUL3_LCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_VUL3_CON0 */ +#define VUL3_ON_SFT 28 +#define VUL3_ON_MASK 0x1 +#define VUL3_ON_MASK_SFT (0x1 << 28) +#define VUL3_MINLEN_SFT 20 +#define VUL3_MINLEN_MASK 0x3 +#define VUL3_MINLEN_MASK_SFT (0x3 << 20) +#define VUL3_MAXLEN_SFT 16 +#define VUL3_MAXLEN_MASK 0x3 +#define VUL3_MAXLEN_MASK_SFT (0x3 << 16) +#define VUL3_SEL_DOMAIN_SFT 13 +#define VUL3_SEL_DOMAIN_MASK 0x7 +#define VUL3_SEL_DOMAIN_MASK_SFT (0x7 << 13) +#define VUL3_SEL_FS_SFT 8 +#define VUL3_SEL_FS_MASK 0x1f +#define VUL3_SEL_FS_MASK_SFT (0x1f << 8) +#define VUL3_SW_CLEAR_BUF_FULL_SFT 7 +#define VUL3_SW_CLEAR_BUF_FULL_MASK 0x1 +#define VUL3_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 7) +#define VUL3_WR_SIGN_SFT 6 +#define VUL3_WR_SIGN_MASK 0x1 +#define VUL3_WR_SIGN_MASK_SFT (0x1 << 6) +#define VUL3_R_MONO_SFT 5 +#define VUL3_R_MONO_MASK 0x1 +#define VUL3_R_MONO_MASK_SFT (0x1 << 5) +#define VUL3_MONO_SFT 4 +#define VUL3_MONO_MASK 0x1 +#define VUL3_MONO_MASK_SFT (0x1 << 4) +#define VUL3_NORMAL_MODE_SFT 3 +#define VUL3_NORMAL_MODE_MASK 0x1 +#define VUL3_NORMAL_MODE_MASK_SFT (0x1 << 3) +#define VUL3_HALIGN_SFT 2 +#define VUL3_HALIGN_MASK 0x1 +#define VUL3_HALIGN_MASK_SFT (0x1 << 2) +#define VUL3_HD_MODE_SFT 0 +#define VUL3_HD_MODE_MASK 0x3 +#define VUL3_HD_MODE_MASK_SFT (0x3 << 0) + +/* AFE_VUL4_BASE_MSB */ +#define VUL4_BASE_ADDR_MSB_SFT 0 +#define VUL4_BASE_ADDR_MSB_MASK 0x1ff +#define VUL4_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_VUL4_BASE */ +#define VUL4_BASE_ADDR_SFT 4 +#define VUL4_BASE_ADDR_MASK 0xfffffff +#define VUL4_BASE_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_VUL4_CUR_MSB */ +#define VUL4_CUR_PTR_MSB_SFT 0 +#define VUL4_CUR_PTR_MSB_MASK 0x1ff +#define VUL4_CUR_PTR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_VUL4_CUR */ +#define VUL4_CUR_PTR_SFT 0 +#define VUL4_CUR_PTR_MASK 0xffffffff +#define VUL4_CUR_PTR_MASK_SFT (0xffffffff << 0) + +/* AFE_VUL4_END_MSB */ +#define VUL4_END_ADDR_MSB_SFT 0 +#define VUL4_END_ADDR_MSB_MASK 0x1ff +#define VUL4_END_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_VUL4_END */ +#define VUL4_END_ADDR_SFT 4 +#define VUL4_END_ADDR_MASK 0xfffffff +#define VUL4_END_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_VUL4_RCH_MON */ +#define VUL4_RCH_DATA_SFT 0 +#define VUL4_RCH_DATA_MASK 0xffffffff +#define VUL4_RCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_VUL4_LCH_MON */ +#define VUL4_LCH_DATA_SFT 0 +#define VUL4_LCH_DATA_MASK 0xffffffff +#define VUL4_LCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_VUL4_CON0 */ +#define VUL4_ON_SFT 28 +#define VUL4_ON_MASK 0x1 +#define VUL4_ON_MASK_SFT (0x1 << 28) +#define VUL4_MINLEN_SFT 20 +#define VUL4_MINLEN_MASK 0x3 +#define VUL4_MINLEN_MASK_SFT (0x3 << 20) +#define VUL4_MAXLEN_SFT 16 +#define VUL4_MAXLEN_MASK 0x3 +#define VUL4_MAXLEN_MASK_SFT (0x3 << 16) +#define VUL4_SEL_DOMAIN_SFT 13 +#define VUL4_SEL_DOMAIN_MASK 0x7 +#define VUL4_SEL_DOMAIN_MASK_SFT (0x7 << 13) +#define VUL4_SEL_FS_SFT 8 +#define VUL4_SEL_FS_MASK 0x1f +#define VUL4_SEL_FS_MASK_SFT (0x1f << 8) +#define VUL4_SW_CLEAR_BUF_FULL_SFT 7 +#define VUL4_SW_CLEAR_BUF_FULL_MASK 0x1 +#define VUL4_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 7) +#define VUL4_WR_SIGN_SFT 6 +#define VUL4_WR_SIGN_MASK 0x1 +#define VUL4_WR_SIGN_MASK_SFT (0x1 << 6) +#define VUL4_R_MONO_SFT 5 +#define VUL4_R_MONO_MASK 0x1 +#define VUL4_R_MONO_MASK_SFT (0x1 << 5) +#define VUL4_MONO_SFT 4 +#define VUL4_MONO_MASK 0x1 +#define VUL4_MONO_MASK_SFT (0x1 << 4) +#define VUL4_NORMAL_MODE_SFT 3 +#define VUL4_NORMAL_MODE_MASK 0x1 +#define VUL4_NORMAL_MODE_MASK_SFT (0x1 << 3) +#define VUL4_HALIGN_SFT 2 +#define VUL4_HALIGN_MASK 0x1 +#define VUL4_HALIGN_MASK_SFT (0x1 << 2) +#define VUL4_HD_MODE_SFT 0 +#define VUL4_HD_MODE_MASK 0x3 +#define VUL4_HD_MODE_MASK_SFT (0x3 << 0) + +/* AFE_VUL5_BASE_MSB */ +#define VUL5_BASE_ADDR_MSB_SFT 0 +#define VUL5_BASE_ADDR_MSB_MASK 0x1ff +#define VUL5_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_VUL5_BASE */ +#define VUL5_BASE_ADDR_SFT 4 +#define VUL5_BASE_ADDR_MASK 0xfffffff +#define VUL5_BASE_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_VUL5_CUR_MSB */ +#define VUL5_CUR_PTR_MSB_SFT 0 +#define VUL5_CUR_PTR_MSB_MASK 0x1ff +#define VUL5_CUR_PTR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_VUL5_CUR */ +#define VUL5_CUR_PTR_SFT 0 +#define VUL5_CUR_PTR_MASK 0xffffffff +#define VUL5_CUR_PTR_MASK_SFT (0xffffffff << 0) + +/* AFE_VUL5_END_MSB */ +#define VUL5_END_ADDR_MSB_SFT 0 +#define VUL5_END_ADDR_MSB_MASK 0x1ff +#define VUL5_END_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_VUL5_END */ +#define VUL5_END_ADDR_SFT 4 +#define VUL5_END_ADDR_MASK 0xfffffff +#define VUL5_END_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_VUL5_RCH_MON */ +#define VUL5_RCH_DATA_SFT 0 +#define VUL5_RCH_DATA_MASK 0xffffffff +#define VUL5_RCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_VUL5_LCH_MON */ +#define VUL5_LCH_DATA_SFT 0 +#define VUL5_LCH_DATA_MASK 0xffffffff +#define VUL5_LCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_VUL5_CON0 */ +#define VUL5_ON_SFT 28 +#define VUL5_ON_MASK 0x1 +#define VUL5_ON_MASK_SFT (0x1 << 28) +#define VUL5_MINLEN_SFT 20 +#define VUL5_MINLEN_MASK 0x3 +#define VUL5_MINLEN_MASK_SFT (0x3 << 20) +#define VUL5_MAXLEN_SFT 16 +#define VUL5_MAXLEN_MASK 0x3 +#define VUL5_MAXLEN_MASK_SFT (0x3 << 16) +#define VUL5_SEL_DOMAIN_SFT 13 +#define VUL5_SEL_DOMAIN_MASK 0x7 +#define VUL5_SEL_DOMAIN_MASK_SFT (0x7 << 13) +#define VUL5_SEL_FS_SFT 8 +#define VUL5_SEL_FS_MASK 0x1f +#define VUL5_SEL_FS_MASK_SFT (0x1f << 8) +#define VUL5_SW_CLEAR_BUF_FULL_SFT 7 +#define VUL5_SW_CLEAR_BUF_FULL_MASK 0x1 +#define VUL5_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 7) +#define VUL5_WR_SIGN_SFT 6 +#define VUL5_WR_SIGN_MASK 0x1 +#define VUL5_WR_SIGN_MASK_SFT (0x1 << 6) +#define VUL5_R_MONO_SFT 5 +#define VUL5_R_MONO_MASK 0x1 +#define VUL5_R_MONO_MASK_SFT (0x1 << 5) +#define VUL5_MONO_SFT 4 +#define VUL5_MONO_MASK 0x1 +#define VUL5_MONO_MASK_SFT (0x1 << 4) +#define VUL5_NORMAL_MODE_SFT 3 +#define VUL5_NORMAL_MODE_MASK 0x1 +#define VUL5_NORMAL_MODE_MASK_SFT (0x1 << 3) +#define VUL5_HALIGN_SFT 2 +#define VUL5_HALIGN_MASK 0x1 +#define VUL5_HALIGN_MASK_SFT (0x1 << 2) +#define VUL5_HD_MODE_SFT 0 +#define VUL5_HD_MODE_MASK 0x3 +#define VUL5_HD_MODE_MASK_SFT (0x3 << 0) + +/* AFE_VUL6_BASE_MSB */ +#define VUL6_BASE_ADDR_MSB_SFT 0 +#define VUL6_BASE_ADDR_MSB_MASK 0x1ff +#define VUL6_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_VUL6_BASE */ +#define VUL6_BASE_ADDR_SFT 4 +#define VUL6_BASE_ADDR_MASK 0xfffffff +#define VUL6_BASE_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_VUL6_CUR_MSB */ +#define VUL6_CUR_PTR_MSB_SFT 0 +#define VUL6_CUR_PTR_MSB_MASK 0x1ff +#define VUL6_CUR_PTR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_VUL6_CUR */ +#define VUL6_CUR_PTR_SFT 0 +#define VUL6_CUR_PTR_MASK 0xffffffff +#define VUL6_CUR_PTR_MASK_SFT (0xffffffff << 0) + +/* AFE_VUL6_END_MSB */ +#define VUL6_END_ADDR_MSB_SFT 0 +#define VUL6_END_ADDR_MSB_MASK 0x1ff +#define VUL6_END_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_VUL6_END */ +#define VUL6_END_ADDR_SFT 4 +#define VUL6_END_ADDR_MASK 0xfffffff +#define VUL6_END_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_VUL6_RCH_MON */ +#define VUL6_RCH_DATA_SFT 0 +#define VUL6_RCH_DATA_MASK 0xffffffff +#define VUL6_RCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_VUL6_LCH_MON */ +#define VUL6_LCH_DATA_SFT 0 +#define VUL6_LCH_DATA_MASK 0xffffffff +#define VUL6_LCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_VUL6_CON0 */ +#define VUL6_ON_SFT 28 +#define VUL6_ON_MASK 0x1 +#define VUL6_ON_MASK_SFT (0x1 << 28) +#define VUL6_MINLEN_SFT 20 +#define VUL6_MINLEN_MASK 0x3 +#define VUL6_MINLEN_MASK_SFT (0x3 << 20) +#define VUL6_MAXLEN_SFT 16 +#define VUL6_MAXLEN_MASK 0x3 +#define VUL6_MAXLEN_MASK_SFT (0x3 << 16) +#define VUL6_SEL_DOMAIN_SFT 13 +#define VUL6_SEL_DOMAIN_MASK 0x7 +#define VUL6_SEL_DOMAIN_MASK_SFT (0x7 << 13) +#define VUL6_SEL_FS_SFT 8 +#define VUL6_SEL_FS_MASK 0x1f +#define VUL6_SEL_FS_MASK_SFT (0x1f << 8) +#define VUL6_SW_CLEAR_BUF_FULL_SFT 7 +#define VUL6_SW_CLEAR_BUF_FULL_MASK 0x1 +#define VUL6_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 7) +#define VUL6_WR_SIGN_SFT 6 +#define VUL6_WR_SIGN_MASK 0x1 +#define VUL6_WR_SIGN_MASK_SFT (0x1 << 6) +#define VUL6_R_MONO_SFT 5 +#define VUL6_R_MONO_MASK 0x1 +#define VUL6_R_MONO_MASK_SFT (0x1 << 5) +#define VUL6_MONO_SFT 4 +#define VUL6_MONO_MASK 0x1 +#define VUL6_MONO_MASK_SFT (0x1 << 4) +#define VUL6_NORMAL_MODE_SFT 3 +#define VUL6_NORMAL_MODE_MASK 0x1 +#define VUL6_NORMAL_MODE_MASK_SFT (0x1 << 3) +#define VUL6_HALIGN_SFT 2 +#define VUL6_HALIGN_MASK 0x1 +#define VUL6_HALIGN_MASK_SFT (0x1 << 2) +#define VUL6_HD_MODE_SFT 0 +#define VUL6_HD_MODE_MASK 0x3 +#define VUL6_HD_MODE_MASK_SFT (0x3 << 0) + +/* AFE_VUL7_BASE_MSB */ +#define VUL7_BASE_ADDR_MSB_SFT 0 +#define VUL7_BASE_ADDR_MSB_MASK 0x1ff +#define VUL7_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_VUL7_BASE */ +#define VUL7_BASE_ADDR_SFT 4 +#define VUL7_BASE_ADDR_MASK 0xfffffff +#define VUL7_BASE_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_VUL7_CUR_MSB */ +#define VUL7_CUR_PTR_MSB_SFT 0 +#define VUL7_CUR_PTR_MSB_MASK 0x1ff +#define VUL7_CUR_PTR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_VUL7_CUR */ +#define VUL7_CUR_PTR_SFT 0 +#define VUL7_CUR_PTR_MASK 0xffffffff +#define VUL7_CUR_PTR_MASK_SFT (0xffffffff << 0) + +/* AFE_VUL7_END_MSB */ +#define VUL7_END_ADDR_MSB_SFT 0 +#define VUL7_END_ADDR_MSB_MASK 0x1ff +#define VUL7_END_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_VUL7_END */ +#define VUL7_END_ADDR_SFT 4 +#define VUL7_END_ADDR_MASK 0xfffffff +#define VUL7_END_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_VUL7_RCH_MON */ +#define VUL7_RCH_DATA_SFT 0 +#define VUL7_RCH_DATA_MASK 0xffffffff +#define VUL7_RCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_VUL7_LCH_MON */ +#define VUL7_LCH_DATA_SFT 0 +#define VUL7_LCH_DATA_MASK 0xffffffff +#define VUL7_LCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_VUL7_CON0 */ +#define VUL7_ON_SFT 28 +#define VUL7_ON_MASK 0x1 +#define VUL7_ON_MASK_SFT (0x1 << 28) +#define VUL7_MINLEN_SFT 20 +#define VUL7_MINLEN_MASK 0x3 +#define VUL7_MINLEN_MASK_SFT (0x3 << 20) +#define VUL7_MAXLEN_SFT 16 +#define VUL7_MAXLEN_MASK 0x3 +#define VUL7_MAXLEN_MASK_SFT (0x3 << 16) +#define VUL7_SEL_DOMAIN_SFT 13 +#define VUL7_SEL_DOMAIN_MASK 0x7 +#define VUL7_SEL_DOMAIN_MASK_SFT (0x7 << 13) +#define VUL7_SEL_FS_SFT 8 +#define VUL7_SEL_FS_MASK 0x1f +#define VUL7_SEL_FS_MASK_SFT (0x1f << 8) +#define VUL7_SW_CLEAR_BUF_FULL_SFT 7 +#define VUL7_SW_CLEAR_BUF_FULL_MASK 0x1 +#define VUL7_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 7) +#define VUL7_WR_SIGN_SFT 6 +#define VUL7_WR_SIGN_MASK 0x1 +#define VUL7_WR_SIGN_MASK_SFT (0x1 << 6) +#define VUL7_R_MONO_SFT 5 +#define VUL7_R_MONO_MASK 0x1 +#define VUL7_R_MONO_MASK_SFT (0x1 << 5) +#define VUL7_MONO_SFT 4 +#define VUL7_MONO_MASK 0x1 +#define VUL7_MONO_MASK_SFT (0x1 << 4) +#define VUL7_NORMAL_MODE_SFT 3 +#define VUL7_NORMAL_MODE_MASK 0x1 +#define VUL7_NORMAL_MODE_MASK_SFT (0x1 << 3) +#define VUL7_HALIGN_SFT 2 +#define VUL7_HALIGN_MASK 0x1 +#define VUL7_HALIGN_MASK_SFT (0x1 << 2) +#define VUL7_HD_MODE_SFT 0 +#define VUL7_HD_MODE_MASK 0x3 +#define VUL7_HD_MODE_MASK_SFT (0x3 << 0) + +/* AFE_VUL8_BASE_MSB */ +#define VUL8_BASE_ADDR_MSB_SFT 0 +#define VUL8_BASE_ADDR_MSB_MASK 0x1ff +#define VUL8_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_VUL8_BASE */ +#define VUL8_BASE_ADDR_SFT 4 +#define VUL8_BASE_ADDR_MASK 0xfffffff +#define VUL8_BASE_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_VUL8_CUR_MSB */ +#define VUL8_CUR_PTR_MSB_SFT 0 +#define VUL8_CUR_PTR_MSB_MASK 0x1ff +#define VUL8_CUR_PTR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_VUL8_CUR */ +#define VUL8_CUR_PTR_SFT 0 +#define VUL8_CUR_PTR_MASK 0xffffffff +#define VUL8_CUR_PTR_MASK_SFT (0xffffffff << 0) + +/* AFE_VUL8_END_MSB */ +#define VUL8_END_ADDR_MSB_SFT 0 +#define VUL8_END_ADDR_MSB_MASK 0x1ff +#define VUL8_END_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_VUL8_END */ +#define VUL8_END_ADDR_SFT 4 +#define VUL8_END_ADDR_MASK 0xfffffff +#define VUL8_END_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_VUL8_RCH_MON */ +#define VUL8_RCH_DATA_SFT 0 +#define VUL8_RCH_DATA_MASK 0xffffffff +#define VUL8_RCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_VUL8_LCH_MON */ +#define VUL8_LCH_DATA_SFT 0 +#define VUL8_LCH_DATA_MASK 0xffffffff +#define VUL8_LCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_VUL8_CON0 */ +#define VUL8_ON_SFT 28 +#define VUL8_ON_MASK 0x1 +#define VUL8_ON_MASK_SFT (0x1 << 28) +#define VUL8_MINLEN_SFT 20 +#define VUL8_MINLEN_MASK 0x3 +#define VUL8_MINLEN_MASK_SFT (0x3 << 20) +#define VUL8_MAXLEN_SFT 16 +#define VUL8_MAXLEN_MASK 0x3 +#define VUL8_MAXLEN_MASK_SFT (0x3 << 16) +#define VUL8_SEL_DOMAIN_SFT 13 +#define VUL8_SEL_DOMAIN_MASK 0x7 +#define VUL8_SEL_DOMAIN_MASK_SFT (0x7 << 13) +#define VUL8_SEL_FS_SFT 8 +#define VUL8_SEL_FS_MASK 0x1f +#define VUL8_SEL_FS_MASK_SFT (0x1f << 8) +#define VUL8_SW_CLEAR_BUF_FULL_SFT 7 +#define VUL8_SW_CLEAR_BUF_FULL_MASK 0x1 +#define VUL8_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 7) +#define VUL8_WR_SIGN_SFT 6 +#define VUL8_WR_SIGN_MASK 0x1 +#define VUL8_WR_SIGN_MASK_SFT (0x1 << 6) +#define VUL8_R_MONO_SFT 5 +#define VUL8_R_MONO_MASK 0x1 +#define VUL8_R_MONO_MASK_SFT (0x1 << 5) +#define VUL8_MONO_SFT 4 +#define VUL8_MONO_MASK 0x1 +#define VUL8_MONO_MASK_SFT (0x1 << 4) +#define VUL8_NORMAL_MODE_SFT 3 +#define VUL8_NORMAL_MODE_MASK 0x1 +#define VUL8_NORMAL_MODE_MASK_SFT (0x1 << 3) +#define VUL8_HALIGN_SFT 2 +#define VUL8_HALIGN_MASK 0x1 +#define VUL8_HALIGN_MASK_SFT (0x1 << 2) +#define VUL8_HD_MODE_SFT 0 +#define VUL8_HD_MODE_MASK 0x3 +#define VUL8_HD_MODE_MASK_SFT (0x3 << 0) + +/* AFE_VUL9_BASE_MSB */ +#define VUL9_BASE_ADDR_MSB_SFT 0 +#define VUL9_BASE_ADDR_MSB_MASK 0x1ff +#define VUL9_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_VUL9_BASE */ +#define VUL9_BASE_ADDR_SFT 4 +#define VUL9_BASE_ADDR_MASK 0xfffffff +#define VUL9_BASE_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_VUL9_CUR_MSB */ +#define VUL9_CUR_PTR_MSB_SFT 0 +#define VUL9_CUR_PTR_MSB_MASK 0x1ff +#define VUL9_CUR_PTR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_VUL9_CUR */ +#define VUL9_CUR_PTR_SFT 0 +#define VUL9_CUR_PTR_MASK 0xffffffff +#define VUL9_CUR_PTR_MASK_SFT (0xffffffff << 0) + +/* AFE_VUL9_END_MSB */ +#define VUL9_END_ADDR_MSB_SFT 0 +#define VUL9_END_ADDR_MSB_MASK 0x1ff +#define VUL9_END_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_VUL9_END */ +#define VUL9_END_ADDR_SFT 4 +#define VUL9_END_ADDR_MASK 0xfffffff +#define VUL9_END_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_VUL9_RCH_MON */ +#define VUL9_RCH_DATA_SFT 0 +#define VUL9_RCH_DATA_MASK 0xffffffff +#define VUL9_RCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_VUL9_LCH_MON */ +#define VUL9_LCH_DATA_SFT 0 +#define VUL9_LCH_DATA_MASK 0xffffffff +#define VUL9_LCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_VUL9_CON0 */ +#define VUL9_ON_SFT 28 +#define VUL9_ON_MASK 0x1 +#define VUL9_ON_MASK_SFT (0x1 << 28) +#define VUL9_MINLEN_SFT 20 +#define VUL9_MINLEN_MASK 0x3 +#define VUL9_MINLEN_MASK_SFT (0x3 << 20) +#define VUL9_MAXLEN_SFT 16 +#define VUL9_MAXLEN_MASK 0x3 +#define VUL9_MAXLEN_MASK_SFT (0x3 << 16) +#define VUL9_SEL_DOMAIN_SFT 13 +#define VUL9_SEL_DOMAIN_MASK 0x7 +#define VUL9_SEL_DOMAIN_MASK_SFT (0x7 << 13) +#define VUL9_SEL_FS_SFT 8 +#define VUL9_SEL_FS_MASK 0x1f +#define VUL9_SEL_FS_MASK_SFT (0x1f << 8) +#define VUL9_SW_CLEAR_BUF_FULL_SFT 7 +#define VUL9_SW_CLEAR_BUF_FULL_MASK 0x1 +#define VUL9_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 7) +#define VUL9_WR_SIGN_SFT 6 +#define VUL9_WR_SIGN_MASK 0x1 +#define VUL9_WR_SIGN_MASK_SFT (0x1 << 6) +#define VUL9_R_MONO_SFT 5 +#define VUL9_R_MONO_MASK 0x1 +#define VUL9_R_MONO_MASK_SFT (0x1 << 5) +#define VUL9_MONO_SFT 4 +#define VUL9_MONO_MASK 0x1 +#define VUL9_MONO_MASK_SFT (0x1 << 4) +#define VUL9_NORMAL_MODE_SFT 3 +#define VUL9_NORMAL_MODE_MASK 0x1 +#define VUL9_NORMAL_MODE_MASK_SFT (0x1 << 3) +#define VUL9_HALIGN_SFT 2 +#define VUL9_HALIGN_MASK 0x1 +#define VUL9_HALIGN_MASK_SFT (0x1 << 2) +#define VUL9_HD_MODE_SFT 0 +#define VUL9_HD_MODE_MASK 0x3 +#define VUL9_HD_MODE_MASK_SFT (0x3 << 0) + +/* AFE_VUL10_BASE_MSB */ +#define VUL10_BASE_ADDR_MSB_SFT 0 +#define VUL10_BASE_ADDR_MSB_MASK 0x1ff +#define VUL10_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_VUL10_BASE */ +#define VUL10_BASE_ADDR_SFT 4 +#define VUL10_BASE_ADDR_MASK 0xfffffff +#define VUL10_BASE_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_VUL10_CUR_MSB */ +#define VUL10_CUR_PTR_MSB_SFT 0 +#define VUL10_CUR_PTR_MSB_MASK 0x1ff +#define VUL10_CUR_PTR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_VUL10_CUR */ +#define VUL10_CUR_PTR_SFT 0 +#define VUL10_CUR_PTR_MASK 0xffffffff +#define VUL10_CUR_PTR_MASK_SFT (0xffffffff << 0) + +/* AFE_VUL10_END_MSB */ +#define VUL10_END_ADDR_MSB_SFT 0 +#define VUL10_END_ADDR_MSB_MASK 0x1ff +#define VUL10_END_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_VUL10_END */ +#define VUL10_END_ADDR_SFT 4 +#define VUL10_END_ADDR_MASK 0xfffffff +#define VUL10_END_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_VUL10_RCH_MON */ +#define VUL10_RCH_DATA_SFT 0 +#define VUL10_RCH_DATA_MASK 0xffffffff +#define VUL10_RCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_VUL10_LCH_MON */ +#define VUL10_LCH_DATA_SFT 0 +#define VUL10_LCH_DATA_MASK 0xffffffff +#define VUL10_LCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_VUL10_CON0 */ +#define VUL10_ON_SFT 28 +#define VUL10_ON_MASK 0x1 +#define VUL10_ON_MASK_SFT (0x1 << 28) +#define VUL10_MINLEN_SFT 20 +#define VUL10_MINLEN_MASK 0x3 +#define VUL10_MINLEN_MASK_SFT (0x3 << 20) +#define VUL10_MAXLEN_SFT 16 +#define VUL10_MAXLEN_MASK 0x3 +#define VUL10_MAXLEN_MASK_SFT (0x3 << 16) +#define VUL10_SEL_DOMAIN_SFT 13 +#define VUL10_SEL_DOMAIN_MASK 0x7 +#define VUL10_SEL_DOMAIN_MASK_SFT (0x7 << 13) +#define VUL10_SEL_FS_SFT 8 +#define VUL10_SEL_FS_MASK 0x1f +#define VUL10_SEL_FS_MASK_SFT (0x1f << 8) +#define VUL10_SW_CLEAR_BUF_FULL_SFT 7 +#define VUL10_SW_CLEAR_BUF_FULL_MASK 0x1 +#define VUL10_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 7) +#define VUL10_WR_SIGN_SFT 6 +#define VUL10_WR_SIGN_MASK 0x1 +#define VUL10_WR_SIGN_MASK_SFT (0x1 << 6) +#define VUL10_R_MONO_SFT 5 +#define VUL10_R_MONO_MASK 0x1 +#define VUL10_R_MONO_MASK_SFT (0x1 << 5) +#define VUL10_MONO_SFT 4 +#define VUL10_MONO_MASK 0x1 +#define VUL10_MONO_MASK_SFT (0x1 << 4) +#define VUL10_NORMAL_MODE_SFT 3 +#define VUL10_NORMAL_MODE_MASK 0x1 +#define VUL10_NORMAL_MODE_MASK_SFT (0x1 << 3) +#define VUL10_HALIGN_SFT 2 +#define VUL10_HALIGN_MASK 0x1 +#define VUL10_HALIGN_MASK_SFT (0x1 << 2) +#define VUL10_HD_MODE_SFT 0 +#define VUL10_HD_MODE_MASK 0x3 +#define VUL10_HD_MODE_MASK_SFT (0x3 << 0) + +/* AFE_VUL24_BASE_MSB */ +#define VUL24_BASE_ADDR_MSB_SFT 0 +#define VUL24_BASE_ADDR_MSB_MASK 0x1ff +#define VUL24_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_VUL24_BASE */ +#define VUL24_BASE_ADDR_SFT 4 +#define VUL24_BASE_ADDR_MASK 0xfffffff +#define VUL24_BASE_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_VUL24_CUR_MSB */ +#define VUL24_CUR_PTR_MSB_SFT 0 +#define VUL24_CUR_PTR_MSB_MASK 0x1ff +#define VUL24_CUR_PTR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_VUL24_CUR */ +#define VUL24_CUR_PTR_SFT 0 +#define VUL24_CUR_PTR_MASK 0xffffffff +#define VUL24_CUR_PTR_MASK_SFT (0xffffffff << 0) + +/* AFE_VUL24_END_MSB */ +#define VUL24_END_ADDR_MSB_SFT 0 +#define VUL24_END_ADDR_MSB_MASK 0x1ff +#define VUL24_END_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_VUL24_END */ +#define VUL24_END_ADDR_SFT 4 +#define VUL24_END_ADDR_MASK 0xfffffff +#define VUL24_END_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_VUL24_CON0 */ +#define OUT_ON_USE_VUL24_SFT 29 +#define OUT_ON_USE_VUL24_MASK 0x1 +#define OUT_ON_USE_VUL24_MASK_SFT (0x1 << 29) +#define VUL24_ON_SFT 28 +#define VUL24_ON_MASK 0x1 +#define VUL24_ON_MASK_SFT (0x1 << 28) +#define VUL24_MINLEN_SFT 20 +#define VUL24_MINLEN_MASK 0x3 +#define VUL24_MINLEN_MASK_SFT (0x3 << 20) +#define VUL24_MAXLEN_SFT 16 +#define VUL24_MAXLEN_MASK 0x3 +#define VUL24_MAXLEN_MASK_SFT (0x3 << 16) +#define VUL24_SEL_DOMAIN_SFT 13 +#define VUL24_SEL_DOMAIN_MASK 0x7 +#define VUL24_SEL_DOMAIN_MASK_SFT (0x7 << 13) +#define VUL24_SEL_FS_SFT 8 +#define VUL24_SEL_FS_MASK 0x1f +#define VUL24_SEL_FS_MASK_SFT (0x1f << 8) +#define VUL24_SW_CLEAR_BUF_FULL_SFT 7 +#define VUL24_SW_CLEAR_BUF_FULL_MASK 0x1 +#define VUL24_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 7) +#define VUL24_WR_SIGN_SFT 6 +#define VUL24_WR_SIGN_MASK 0x1 +#define VUL24_WR_SIGN_MASK_SFT (0x1 << 6) +#define VUL24_R_MONO_SFT 5 +#define VUL24_R_MONO_MASK 0x1 +#define VUL24_R_MONO_MASK_SFT (0x1 << 5) +#define VUL24_MONO_SFT 4 +#define VUL24_MONO_MASK 0x1 +#define VUL24_MONO_MASK_SFT (0x1 << 4) +#define VUL24_NORMAL_MODE_SFT 3 +#define VUL24_NORMAL_MODE_MASK 0x1 +#define VUL24_NORMAL_MODE_MASK_SFT (0x1 << 3) +#define VUL24_HALIGN_SFT 2 +#define VUL24_HALIGN_MASK 0x1 +#define VUL24_HALIGN_MASK_SFT (0x1 << 2) +#define VUL24_HD_MODE_SFT 0 +#define VUL24_HD_MODE_MASK 0x3 +#define VUL24_HD_MODE_MASK_SFT (0x3 << 0) + +/* AFE_VUL25_BASE_MSB */ +#define VUL25_BASE_ADDR_MSB_SFT 0 +#define VUL25_BASE_ADDR_MSB_MASK 0x1ff +#define VUL25_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_VUL25_BASE */ +#define VUL25_BASE_ADDR_SFT 4 +#define VUL25_BASE_ADDR_MASK 0xfffffff +#define VUL25_BASE_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_VUL25_CUR_MSB */ +#define VUL25_CUR_PTR_MSB_SFT 0 +#define VUL25_CUR_PTR_MSB_MASK 0x1ff +#define VUL25_CUR_PTR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_VUL25_CUR */ +#define VUL25_CUR_PTR_SFT 0 +#define VUL25_CUR_PTR_MASK 0xffffffff +#define VUL25_CUR_PTR_MASK_SFT (0xffffffff << 0) + +/* AFE_VUL25_END_MSB */ +#define VUL25_END_ADDR_MSB_SFT 0 +#define VUL25_END_ADDR_MSB_MASK 0x1ff +#define VUL25_END_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_VUL25_END */ +#define VUL25_END_ADDR_SFT 4 +#define VUL25_END_ADDR_MASK 0xfffffff +#define VUL25_END_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_VUL25_CON0 */ +#define OUT_ON_USE_VUL25_SFT 29 +#define OUT_ON_USE_VUL25_MASK 0x1 +#define OUT_ON_USE_VUL25_MASK_SFT (0x1 << 29) +#define VUL25_ON_SFT 28 +#define VUL25_ON_MASK 0x1 +#define VUL25_ON_MASK_SFT (0x1 << 28) +#define VUL25_MINLEN_SFT 20 +#define VUL25_MINLEN_MASK 0x3 +#define VUL25_MINLEN_MASK_SFT (0x3 << 20) +#define VUL25_MAXLEN_SFT 16 +#define VUL25_MAXLEN_MASK 0x3 +#define VUL25_MAXLEN_MASK_SFT (0x3 << 16) +#define VUL25_SEL_DOMAIN_SFT 13 +#define VUL25_SEL_DOMAIN_MASK 0x7 +#define VUL25_SEL_DOMAIN_MASK_SFT (0x7 << 13) +#define VUL25_SEL_FS_SFT 8 +#define VUL25_SEL_FS_MASK 0x1f +#define VUL25_SEL_FS_MASK_SFT (0x1f << 8) +#define VUL25_SW_CLEAR_BUF_FULL_SFT 7 +#define VUL25_SW_CLEAR_BUF_FULL_MASK 0x1 +#define VUL25_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 7) +#define VUL25_WR_SIGN_SFT 6 +#define VUL25_WR_SIGN_MASK 0x1 +#define VUL25_WR_SIGN_MASK_SFT (0x1 << 6) +#define VUL25_R_MONO_SFT 5 +#define VUL25_R_MONO_MASK 0x1 +#define VUL25_R_MONO_MASK_SFT (0x1 << 5) +#define VUL25_MONO_SFT 4 +#define VUL25_MONO_MASK 0x1 +#define VUL25_MONO_MASK_SFT (0x1 << 4) +#define VUL25_NORMAL_MODE_SFT 3 +#define VUL25_NORMAL_MODE_MASK 0x1 +#define VUL25_NORMAL_MODE_MASK_SFT (0x1 << 3) +#define VUL25_HALIGN_SFT 2 +#define VUL25_HALIGN_MASK 0x1 +#define VUL25_HALIGN_MASK_SFT (0x1 << 2) +#define VUL25_HD_MODE_SFT 0 +#define VUL25_HD_MODE_MASK 0x3 +#define VUL25_HD_MODE_MASK_SFT (0x3 << 0) + +/* AFE_VUL26_BASE_MSB */ +#define VUL26_BASE_ADDR_MSB_SFT 0 +#define VUL26_BASE_ADDR_MSB_MASK 0x1ff +#define VUL26_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_VUL26_BASE */ +#define VUL26_BASE_ADDR_SFT 4 +#define VUL26_BASE_ADDR_MASK 0xfffffff +#define VUL26_BASE_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_VUL26_CUR_MSB */ +#define VUL26_CUR_PTR_MSB_SFT 0 +#define VUL26_CUR_PTR_MSB_MASK 0x1ff +#define VUL26_CUR_PTR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_VUL26_CUR */ +#define VUL26_CUR_PTR_SFT 0 +#define VUL26_CUR_PTR_MASK 0xffffffff +#define VUL26_CUR_PTR_MASK_SFT (0xffffffff << 0) + +/* AFE_VUL26_END_MSB */ +#define VUL26_END_ADDR_MSB_SFT 0 +#define VUL26_END_ADDR_MSB_MASK 0x1ff +#define VUL26_END_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_VUL26_END */ +#define VUL26_END_ADDR_SFT 4 +#define VUL26_END_ADDR_MASK 0xfffffff +#define VUL26_END_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_VUL26_CON0 */ +#define OUT_ON_USE_VUL26_SFT 29 +#define OUT_ON_USE_VUL26_MASK 0x1 +#define OUT_ON_USE_VUL26_MASK_SFT (0x1 << 29) +#define VUL26_ON_SFT 28 +#define VUL26_ON_MASK 0x1 +#define VUL26_ON_MASK_SFT (0x1 << 28) +#define VUL26_MINLEN_SFT 20 +#define VUL26_MINLEN_MASK 0x3 +#define VUL26_MINLEN_MASK_SFT (0x3 << 20) +#define VUL26_MAXLEN_SFT 16 +#define VUL26_MAXLEN_MASK 0x3 +#define VUL26_MAXLEN_MASK_SFT (0x3 << 16) +#define VUL26_SEL_DOMAIN_SFT 13 +#define VUL26_SEL_DOMAIN_MASK 0x7 +#define VUL26_SEL_DOMAIN_MASK_SFT (0x7 << 13) +#define VUL26_SEL_FS_SFT 8 +#define VUL26_SEL_FS_MASK 0x1f +#define VUL26_SEL_FS_MASK_SFT (0x1f << 8) +#define VUL26_SW_CLEAR_BUF_FULL_SFT 7 +#define VUL26_SW_CLEAR_BUF_FULL_MASK 0x1 +#define VUL26_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 7) +#define VUL26_WR_SIGN_SFT 6 +#define VUL26_WR_SIGN_MASK 0x1 +#define VUL26_WR_SIGN_MASK_SFT (0x1 << 6) +#define VUL26_R_MONO_SFT 5 +#define VUL26_R_MONO_MASK 0x1 +#define VUL26_R_MONO_MASK_SFT (0x1 << 5) +#define VUL26_MONO_SFT 4 +#define VUL26_MONO_MASK 0x1 +#define VUL26_MONO_MASK_SFT (0x1 << 4) +#define VUL26_NORMAL_MODE_SFT 3 +#define VUL26_NORMAL_MODE_MASK 0x1 +#define VUL26_NORMAL_MODE_MASK_SFT (0x1 << 3) +#define VUL26_HALIGN_SFT 2 +#define VUL26_HALIGN_MASK 0x1 +#define VUL26_HALIGN_MASK_SFT (0x1 << 2) +#define VUL26_HD_MODE_SFT 0 +#define VUL26_HD_MODE_MASK 0x3 +#define VUL26_HD_MODE_MASK_SFT (0x3 << 0) + +/* AFE_VUL_CM0_BASE_MSB */ +#define VUL_CM0_BASE_ADDR_MSB_SFT 0 +#define VUL_CM0_BASE_ADDR_MSB_MASK 0x1ff +#define VUL_CM0_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_VUL_CM0_BASE */ +#define VUL_CM0_BASE_ADDR_SFT 4 +#define VUL_CM0_BASE_ADDR_MASK 0xfffffff +#define VUL_CM0_BASE_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_VUL_CM0_CUR_MSB */ +#define VUL_CM0_CUR_PTR_MSB_SFT 0 +#define VUL_CM0_CUR_PTR_MSB_MASK 0x1ff +#define VUL_CM0_CUR_PTR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_VUL_CM0_CUR */ +#define VUL_CM0_CUR_PTR_SFT 0 +#define VUL_CM0_CUR_PTR_MASK 0xffffffff +#define VUL_CM0_CUR_PTR_MASK_SFT (0xffffffff << 0) + +/* AFE_VUL_CM0_END_MSB */ +#define VUL_CM0_END_ADDR_MSB_SFT 0 +#define VUL_CM0_END_ADDR_MSB_MASK 0x1ff +#define VUL_CM0_END_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_VUL_CM0_END */ +#define VUL_CM0_END_ADDR_SFT 4 +#define VUL_CM0_END_ADDR_MASK 0xfffffff +#define VUL_CM0_END_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_VUL_CM0_CON0 */ +#define VUL_CM0_ON_SFT 28 +#define VUL_CM0_ON_MASK 0x1 +#define VUL_CM0_ON_MASK_SFT (0x1 << 28) +#define VUL_CM0_REG_CH_SHIFT_MODE_SFT 26 +#define VUL_CM0_REG_CH_SHIFT_MODE_MASK 0x1 +#define VUL_CM0_REG_CH_SHIFT_MODE_MASK_SFT (0x1 << 26) +#define VUL_CM0_RG_FORCE_NO_MASK_EXTRA_SFT 25 +#define VUL_CM0_RG_FORCE_NO_MASK_EXTRA_MASK 0x1 +#define VUL_CM0_RG_FORCE_NO_MASK_EXTRA_MASK_SFT (0x1 << 25) +#define VUL_CM0_SW_CLEAR_BUF_FULL_SFT 24 +#define VUL_CM0_SW_CLEAR_BUF_FULL_MASK 0x1 +#define VUL_CM0_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 24) +#define VUL_CM0_ULTRA_TH_SFT 20 +#define VUL_CM0_ULTRA_TH_MASK 0xf +#define VUL_CM0_ULTRA_TH_MASK_SFT (0xf << 20) +#define VUL_CM0_NORMAL_MODE_SFT 17 +#define VUL_CM0_NORMAL_MODE_MASK 0x1 +#define VUL_CM0_NORMAL_MODE_MASK_SFT (0x1 << 17) +#define VUL_CM0_ODD_USE_EVEN_SFT 16 +#define VUL_CM0_ODD_USE_EVEN_MASK 0x1 +#define VUL_CM0_ODD_USE_EVEN_MASK_SFT (0x1 << 16) +#define VUL_CM0_AXI_REQ_MAXLEN_SFT 12 +#define VUL_CM0_AXI_REQ_MAXLEN_MASK 0x3 +#define VUL_CM0_AXI_REQ_MAXLEN_MASK_SFT (0x3 << 12) +#define VUL_CM0_AXI_REQ_MINLEN_SFT 8 +#define VUL_CM0_AXI_REQ_MINLEN_MASK 0x3 +#define VUL_CM0_AXI_REQ_MINLEN_MASK_SFT (0x3 << 8) +#define VUL_CM0_HALIGN_SFT 7 +#define VUL_CM0_HALIGN_MASK 0x1 +#define VUL_CM0_HALIGN_MASK_SFT (0x1 << 7) +#define VUL_CM0_SIGN_EXT_SFT 6 +#define VUL_CM0_SIGN_EXT_MASK 0x1 +#define VUL_CM0_SIGN_EXT_MASK_SFT (0x1 << 6) +#define VUL_CM0_HD_MODE_SFT 4 +#define VUL_CM0_HD_MODE_MASK 0x3 +#define VUL_CM0_HD_MODE_MASK_SFT (0x3 << 4) +#define VUL_CM0_MAKE_EXTRA_UPDATE_SFT 3 +#define VUL_CM0_MAKE_EXTRA_UPDATE_MASK 0x1 +#define VUL_CM0_MAKE_EXTRA_UPDATE_MASK_SFT (0x1 << 3) +#define VUL_CM0_AGENT_FREE_RUN_SFT 2 +#define VUL_CM0_AGENT_FREE_RUN_MASK 0x1 +#define VUL_CM0_AGENT_FREE_RUN_MASK_SFT (0x1 << 2) +#define VUL_CM0_USE_INT_ODD_SFT 1 +#define VUL_CM0_USE_INT_ODD_MASK 0x1 +#define VUL_CM0_USE_INT_ODD_MASK_SFT (0x1 << 1) +#define VUL_CM0_INT_ODD_FLAG_SFT 0 +#define VUL_CM0_INT_ODD_FLAG_MASK 0x1 +#define VUL_CM0_INT_ODD_FLAG_MASK_SFT (0x1 << 0) + +/* AFE_VUL_CM1_BASE_MSB */ +#define VUL_CM1_BASE_ADDR_MSB_SFT 0 +#define VUL_CM1_BASE_ADDR_MSB_MASK 0x1ff +#define VUL_CM1_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_VUL_CM1_BASE */ +#define VUL_CM1_BASE_ADDR_SFT 4 +#define VUL_CM1_BASE_ADDR_MASK 0xfffffff +#define VUL_CM1_BASE_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_VUL_CM1_CUR_MSB */ +#define VUL_CM1_CUR_PTR_MSB_SFT 0 +#define VUL_CM1_CUR_PTR_MSB_MASK 0x1ff +#define VUL_CM1_CUR_PTR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_VUL_CM1_CUR */ +#define VUL_CM1_CUR_PTR_SFT 0 +#define VUL_CM1_CUR_PTR_MASK 0xffffffff +#define VUL_CM1_CUR_PTR_MASK_SFT (0xffffffff << 0) + +/* AFE_VUL_CM1_END_MSB */ +#define VUL_CM1_END_ADDR_MSB_SFT 0 +#define VUL_CM1_END_ADDR_MSB_MASK 0x1ff +#define VUL_CM1_END_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_VUL_CM1_END */ +#define VUL_CM1_END_ADDR_SFT 4 +#define VUL_CM1_END_ADDR_MASK 0xfffffff +#define VUL_CM1_END_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_VUL_CM1_CON0 */ +#define VUL_CM1_ON_SFT 28 +#define VUL_CM1_ON_MASK 0x1 +#define VUL_CM1_ON_MASK_SFT (0x1 << 28) +#define VUL_CM1_REG_CH_SHIFT_MODE_SFT 26 +#define VUL_CM1_REG_CH_SHIFT_MODE_MASK 0x1 +#define VUL_CM1_REG_CH_SHIFT_MODE_MASK_SFT (0x1 << 26) +#define VUL_CM1_RG_FORCE_NO_MASK_EXTRA_SFT 25 +#define VUL_CM1_RG_FORCE_NO_MASK_EXTRA_MASK 0x1 +#define VUL_CM1_RG_FORCE_NO_MASK_EXTRA_MASK_SFT (0x1 << 25) +#define VUL_CM1_SW_CLEAR_BUF_FULL_SFT 24 +#define VUL_CM1_SW_CLEAR_BUF_FULL_MASK 0x1 +#define VUL_CM1_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 24) +#define VUL_CM1_ULTRA_TH_SFT 20 +#define VUL_CM1_ULTRA_TH_MASK 0xf +#define VUL_CM1_ULTRA_TH_MASK_SFT (0xf << 20) +#define VUL_CM1_NORMAL_MODE_SFT 17 +#define VUL_CM1_NORMAL_MODE_MASK 0x1 +#define VUL_CM1_NORMAL_MODE_MASK_SFT (0x1 << 17) +#define VUL_CM1_ODD_USE_EVEN_SFT 16 +#define VUL_CM1_ODD_USE_EVEN_MASK 0x1 +#define VUL_CM1_ODD_USE_EVEN_MASK_SFT (0x1 << 16) +#define VUL_CM1_AXI_REQ_MAXLEN_SFT 12 +#define VUL_CM1_AXI_REQ_MAXLEN_MASK 0x3 +#define VUL_CM1_AXI_REQ_MAXLEN_MASK_SFT (0x3 << 12) +#define VUL_CM1_AXI_REQ_MINLEN_SFT 8 +#define VUL_CM1_AXI_REQ_MINLEN_MASK 0x3 +#define VUL_CM1_AXI_REQ_MINLEN_MASK_SFT (0x3 << 8) +#define VUL_CM1_HALIGN_SFT 7 +#define VUL_CM1_HALIGN_MASK 0x1 +#define VUL_CM1_HALIGN_MASK_SFT (0x1 << 7) +#define VUL_CM1_SIGN_EXT_SFT 6 +#define VUL_CM1_SIGN_EXT_MASK 0x1 +#define VUL_CM1_SIGN_EXT_MASK_SFT (0x1 << 6) +#define VUL_CM1_HD_MODE_SFT 4 +#define VUL_CM1_HD_MODE_MASK 0x3 +#define VUL_CM1_HD_MODE_MASK_SFT (0x3 << 4) +#define VUL_CM1_MAKE_EXTRA_UPDATE_SFT 3 +#define VUL_CM1_MAKE_EXTRA_UPDATE_MASK 0x1 +#define VUL_CM1_MAKE_EXTRA_UPDATE_MASK_SFT (0x1 << 3) +#define VUL_CM1_AGENT_FREE_RUN_SFT 2 +#define VUL_CM1_AGENT_FREE_RUN_MASK 0x1 +#define VUL_CM1_AGENT_FREE_RUN_MASK_SFT (0x1 << 2) +#define VUL_CM1_USE_INT_ODD_SFT 1 +#define VUL_CM1_USE_INT_ODD_MASK 0x1 +#define VUL_CM1_USE_INT_ODD_MASK_SFT (0x1 << 1) +#define VUL_CM1_INT_ODD_FLAG_SFT 0 +#define VUL_CM1_INT_ODD_FLAG_MASK 0x1 +#define VUL_CM1_INT_ODD_FLAG_MASK_SFT (0x1 << 0) + +/* AFE_VUL_CM2_BASE_MSB */ +#define VUL_CM2_BASE_ADDR_MSB_SFT 0 +#define VUL_CM2_BASE_ADDR_MSB_MASK 0x1ff +#define VUL_CM2_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_VUL_CM2_BASE */ +#define VUL_CM2_BASE_ADDR_SFT 4 +#define VUL_CM2_BASE_ADDR_MASK 0xfffffff +#define VUL_CM2_BASE_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_VUL_CM2_CUR_MSB */ +#define VUL_CM2_CUR_PTR_MSB_SFT 0 +#define VUL_CM2_CUR_PTR_MSB_MASK 0x1ff +#define VUL_CM2_CUR_PTR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_VUL_CM2_CUR */ +#define VUL_CM2_CUR_PTR_SFT 0 +#define VUL_CM2_CUR_PTR_MASK 0xffffffff +#define VUL_CM2_CUR_PTR_MASK_SFT (0xffffffff << 0) + +/* AFE_VUL_CM2_END_MSB */ +#define VUL_CM2_END_ADDR_MSB_SFT 0 +#define VUL_CM2_END_ADDR_MSB_MASK 0x1ff +#define VUL_CM2_END_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_VUL_CM2_END */ +#define VUL_CM2_END_ADDR_SFT 4 +#define VUL_CM2_END_ADDR_MASK 0xfffffff +#define VUL_CM2_END_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_VUL_CM2_CON0 */ +#define VUL_CM2_ON_SFT 28 +#define VUL_CM2_ON_MASK 0x1 +#define VUL_CM2_ON_MASK_SFT (0x1 << 28) +#define VUL_CM2_REG_CH_SHIFT_MODE_SFT 26 +#define VUL_CM2_REG_CH_SHIFT_MODE_MASK 0x1 +#define VUL_CM2_REG_CH_SHIFT_MODE_MASK_SFT (0x1 << 26) +#define VUL_CM2_RG_FORCE_NO_MASK_EXTRA_SFT 25 +#define VUL_CM2_RG_FORCE_NO_MASK_EXTRA_MASK 0x1 +#define VUL_CM2_RG_FORCE_NO_MASK_EXTRA_MASK_SFT (0x1 << 25) +#define VUL_CM2_SW_CLEAR_BUF_FULL_SFT 24 +#define VUL_CM2_SW_CLEAR_BUF_FULL_MASK 0x1 +#define VUL_CM2_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 24) +#define VUL_CM2_ULTRA_TH_SFT 20 +#define VUL_CM2_ULTRA_TH_MASK 0xf +#define VUL_CM2_ULTRA_TH_MASK_SFT (0xf << 20) +#define VUL_CM2_NORMAL_MODE_SFT 17 +#define VUL_CM2_NORMAL_MODE_MASK 0x1 +#define VUL_CM2_NORMAL_MODE_MASK_SFT (0x1 << 17) +#define VUL_CM2_ODD_USE_EVEN_SFT 16 +#define VUL_CM2_ODD_USE_EVEN_MASK 0x1 +#define VUL_CM2_ODD_USE_EVEN_MASK_SFT (0x1 << 16) +#define VUL_CM2_AXI_REQ_MAXLEN_SFT 12 +#define VUL_CM2_AXI_REQ_MAXLEN_MASK 0x3 +#define VUL_CM2_AXI_REQ_MAXLEN_MASK_SFT (0x3 << 12) +#define VUL_CM2_AXI_REQ_MINLEN_SFT 8 +#define VUL_CM2_AXI_REQ_MINLEN_MASK 0x3 +#define VUL_CM2_AXI_REQ_MINLEN_MASK_SFT (0x3 << 8) +#define VUL_CM2_HALIGN_SFT 7 +#define VUL_CM2_HALIGN_MASK 0x1 +#define VUL_CM2_HALIGN_MASK_SFT (0x1 << 7) +#define VUL_CM2_SIGN_EXT_SFT 6 +#define VUL_CM2_SIGN_EXT_MASK 0x1 +#define VUL_CM2_SIGN_EXT_MASK_SFT (0x1 << 6) +#define VUL_CM2_HD_MODE_SFT 4 +#define VUL_CM2_HD_MODE_MASK 0x3 +#define VUL_CM2_HD_MODE_MASK_SFT (0x3 << 4) +#define VUL_CM2_MAKE_EXTRA_UPDATE_SFT 3 +#define VUL_CM2_MAKE_EXTRA_UPDATE_MASK 0x1 +#define VUL_CM2_MAKE_EXTRA_UPDATE_MASK_SFT (0x1 << 3) +#define VUL_CM2_AGENT_FREE_RUN_SFT 2 +#define VUL_CM2_AGENT_FREE_RUN_MASK 0x1 +#define VUL_CM2_AGENT_FREE_RUN_MASK_SFT (0x1 << 2) +#define VUL_CM2_USE_INT_ODD_SFT 1 +#define VUL_CM2_USE_INT_ODD_MASK 0x1 +#define VUL_CM2_USE_INT_ODD_MASK_SFT (0x1 << 1) +#define VUL_CM2_INT_ODD_FLAG_SFT 0 +#define VUL_CM2_INT_ODD_FLAG_MASK 0x1 +#define VUL_CM2_INT_ODD_FLAG_MASK_SFT (0x1 << 0) + +/* AFE_ETDM_IN0_BASE_MSB */ +#define ETDM_IN0_BASE_ADDR_MSB_SFT 0 +#define ETDM_IN0_BASE_ADDR_MSB_MASK 0x1ff +#define ETDM_IN0_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_ETDM_IN0_BASE */ +#define ETDM_IN0_BASE_ADDR_SFT 4 +#define ETDM_IN0_BASE_ADDR_MASK 0xfffffff +#define ETDM_IN0_BASE_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_ETDM_IN0_CUR_MSB */ +#define ETDM_IN0_CUR_PTR_MSB_SFT 0 +#define ETDM_IN0_CUR_PTR_MSB_MASK 0x1ff +#define ETDM_IN0_CUR_PTR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_ETDM_IN0_CUR */ +#define ETDM_IN0_CUR_PTR_SFT 0 +#define ETDM_IN0_CUR_PTR_MASK 0xffffffff +#define ETDM_IN0_CUR_PTR_MASK_SFT (0xffffffff << 0) + +/* AFE_ETDM_IN0_END_MSB */ +#define ETDM_IN0_END_ADDR_MSB_SFT 0 +#define ETDM_IN0_END_ADDR_MSB_MASK 0x1ff +#define ETDM_IN0_END_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_ETDM_IN0_END */ +#define ETDM_IN0_END_ADDR_SFT 4 +#define ETDM_IN0_END_ADDR_MASK 0xfffffff +#define ETDM_IN0_END_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_ETDM_IN0_CON0 */ +#define ETDM_IN0_CH_NUM_SFT 28 +#define ETDM_IN0_CH_NUM_MASK 0xf +#define ETDM_IN0_CH_NUM_MASK_SFT (0xf << 28) +#define ETDM_IN0_ON_SFT 27 +#define ETDM_IN0_ON_MASK 0x1 +#define ETDM_IN0_ON_MASK_SFT (0x1 << 27) +#define ETDM_IN0_REG_CH_SHIFT_MODE_SFT 26 +#define ETDM_IN0_REG_CH_SHIFT_MODE_MASK 0x1 +#define ETDM_IN0_REG_CH_SHIFT_MODE_MASK_SFT (0x1 << 26) +#define ETDM_IN0_RG_FORCE_NO_MASK_EXTRA_SFT 25 +#define ETDM_IN0_RG_FORCE_NO_MASK_EXTRA_MASK 0x1 +#define ETDM_IN0_RG_FORCE_NO_MASK_EXTRA_MASK_SFT (0x1 << 25) +#define ETDM_IN0_SW_CLEAR_BUF_FULL_SFT 24 +#define ETDM_IN0_SW_CLEAR_BUF_FULL_MASK 0x1 +#define ETDM_IN0_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 24) +#define ETDM_IN0_ULTRA_TH_SFT 20 +#define ETDM_IN0_ULTRA_TH_MASK 0xf +#define ETDM_IN0_ULTRA_TH_MASK_SFT (0xf << 20) +#define ETDM_IN0_NORMAL_MODE_SFT 17 +#define ETDM_IN0_NORMAL_MODE_MASK 0x1 +#define ETDM_IN0_NORMAL_MODE_MASK_SFT (0x1 << 17) +#define ETDM_IN0_ODD_USE_EVEN_SFT 16 +#define ETDM_IN0_ODD_USE_EVEN_MASK 0x1 +#define ETDM_IN0_ODD_USE_EVEN_MASK_SFT (0x1 << 16) +#define ETDM_IN0_AXI_REQ_MAXLEN_SFT 12 +#define ETDM_IN0_AXI_REQ_MAXLEN_MASK 0x3 +#define ETDM_IN0_AXI_REQ_MAXLEN_MASK_SFT (0x3 << 12) +#define ETDM_IN0_AXI_REQ_MINLEN_SFT 8 +#define ETDM_IN0_AXI_REQ_MINLEN_MASK 0x3 +#define ETDM_IN0_AXI_REQ_MINLEN_MASK_SFT (0x3 << 8) +#define ETDM_IN0_HALIGN_SFT 7 +#define ETDM_IN0_HALIGN_MASK 0x1 +#define ETDM_IN0_HALIGN_MASK_SFT (0x1 << 7) +#define ETDM_IN0_SIGN_EXT_SFT 6 +#define ETDM_IN0_SIGN_EXT_MASK 0x1 +#define ETDM_IN0_SIGN_EXT_MASK_SFT (0x1 << 6) +#define ETDM_IN0_HD_MODE_SFT 4 +#define ETDM_IN0_HD_MODE_MASK 0x3 +#define ETDM_IN0_HD_MODE_MASK_SFT (0x3 << 4) +#define ETDM_IN0_MAKE_EXTRA_UPDATE_SFT 3 +#define ETDM_IN0_MAKE_EXTRA_UPDATE_MASK 0x1 +#define ETDM_IN0_MAKE_EXTRA_UPDATE_MASK_SFT (0x1 << 3) +#define ETDM_IN0_AGENT_FREE_RUN_SFT 2 +#define ETDM_IN0_AGENT_FREE_RUN_MASK 0x1 +#define ETDM_IN0_AGENT_FREE_RUN_MASK_SFT (0x1 << 2) +#define ETDM_IN0_USE_INT_ODD_SFT 1 +#define ETDM_IN0_USE_INT_ODD_MASK 0x1 +#define ETDM_IN0_USE_INT_ODD_MASK_SFT (0x1 << 1) +#define ETDM_IN0_INT_ODD_FLAG_SFT 0 +#define ETDM_IN0_INT_ODD_FLAG_MASK 0x1 +#define ETDM_IN0_INT_ODD_FLAG_MASK_SFT (0x1 << 0) + +/* AFE_ETDM_IN1_BASE_MSB */ +#define ETDM_IN1_BASE_ADDR_MSB_SFT 0 +#define ETDM_IN1_BASE_ADDR_MSB_MASK 0x1ff +#define ETDM_IN1_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_ETDM_IN1_BASE */ +#define ETDM_IN1_BASE_ADDR_SFT 4 +#define ETDM_IN1_BASE_ADDR_MASK 0xfffffff +#define ETDM_IN1_BASE_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_ETDM_IN1_CUR_MSB */ +#define ETDM_IN1_CUR_PTR_MSB_SFT 0 +#define ETDM_IN1_CUR_PTR_MSB_MASK 0x1ff +#define ETDM_IN1_CUR_PTR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_ETDM_IN1_CUR */ +#define ETDM_IN1_CUR_PTR_SFT 0 +#define ETDM_IN1_CUR_PTR_MASK 0xffffffff +#define ETDM_IN1_CUR_PTR_MASK_SFT (0xffffffff << 0) + +/* AFE_ETDM_IN1_END_MSB */ +#define ETDM_IN1_END_ADDR_MSB_SFT 0 +#define ETDM_IN1_END_ADDR_MSB_MASK 0x1ff +#define ETDM_IN1_END_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_ETDM_IN1_END */ +#define ETDM_IN1_END_ADDR_SFT 4 +#define ETDM_IN1_END_ADDR_MASK 0xfffffff +#define ETDM_IN1_END_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_ETDM_IN1_CON0 */ +#define ETDM_IN1_CH_NUM_SFT 28 +#define ETDM_IN1_CH_NUM_MASK 0xf +#define ETDM_IN1_CH_NUM_MASK_SFT (0xf << 28) +#define ETDM_IN1_ON_SFT 27 +#define ETDM_IN1_ON_MASK 0x1 +#define ETDM_IN1_ON_MASK_SFT (0x1 << 27) +#define ETDM_IN1_REG_CH_SHIFT_MODE_SFT 26 +#define ETDM_IN1_REG_CH_SHIFT_MODE_MASK 0x1 +#define ETDM_IN1_REG_CH_SHIFT_MODE_MASK_SFT (0x1 << 26) +#define ETDM_IN1_RG_FORCE_NO_MASK_EXTRA_SFT 25 +#define ETDM_IN1_RG_FORCE_NO_MASK_EXTRA_MASK 0x1 +#define ETDM_IN1_RG_FORCE_NO_MASK_EXTRA_MASK_SFT (0x1 << 25) +#define ETDM_IN1_SW_CLEAR_BUF_FULL_SFT 24 +#define ETDM_IN1_SW_CLEAR_BUF_FULL_MASK 0x1 +#define ETDM_IN1_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 24) +#define ETDM_IN1_ULTRA_TH_SFT 20 +#define ETDM_IN1_ULTRA_TH_MASK 0xf +#define ETDM_IN1_ULTRA_TH_MASK_SFT (0xf << 20) +#define ETDM_IN1_NORMAL_MODE_SFT 17 +#define ETDM_IN1_NORMAL_MODE_MASK 0x1 +#define ETDM_IN1_NORMAL_MODE_MASK_SFT (0x1 << 17) +#define ETDM_IN1_ODD_USE_EVEN_SFT 16 +#define ETDM_IN1_ODD_USE_EVEN_MASK 0x1 +#define ETDM_IN1_ODD_USE_EVEN_MASK_SFT (0x1 << 16) +#define ETDM_IN1_AXI_REQ_MAXLEN_SFT 12 +#define ETDM_IN1_AXI_REQ_MAXLEN_MASK 0x3 +#define ETDM_IN1_AXI_REQ_MAXLEN_MASK_SFT (0x3 << 12) +#define ETDM_IN1_AXI_REQ_MINLEN_SFT 8 +#define ETDM_IN1_AXI_REQ_MINLEN_MASK 0x3 +#define ETDM_IN1_AXI_REQ_MINLEN_MASK_SFT (0x3 << 8) +#define ETDM_IN1_HALIGN_SFT 7 +#define ETDM_IN1_HALIGN_MASK 0x1 +#define ETDM_IN1_HALIGN_MASK_SFT (0x1 << 7) +#define ETDM_IN1_SIGN_EXT_SFT 6 +#define ETDM_IN1_SIGN_EXT_MASK 0x1 +#define ETDM_IN1_SIGN_EXT_MASK_SFT (0x1 << 6) +#define ETDM_IN1_HD_MODE_SFT 4 +#define ETDM_IN1_HD_MODE_MASK 0x3 +#define ETDM_IN1_HD_MODE_MASK_SFT (0x3 << 4) +#define ETDM_IN1_MAKE_EXTRA_UPDATE_SFT 3 +#define ETDM_IN1_MAKE_EXTRA_UPDATE_MASK 0x1 +#define ETDM_IN1_MAKE_EXTRA_UPDATE_MASK_SFT (0x1 << 3) +#define ETDM_IN1_AGENT_FREE_RUN_SFT 2 +#define ETDM_IN1_AGENT_FREE_RUN_MASK 0x1 +#define ETDM_IN1_AGENT_FREE_RUN_MASK_SFT (0x1 << 2) +#define ETDM_IN1_USE_INT_ODD_SFT 1 +#define ETDM_IN1_USE_INT_ODD_MASK 0x1 +#define ETDM_IN1_USE_INT_ODD_MASK_SFT (0x1 << 1) +#define ETDM_IN1_INT_ODD_FLAG_SFT 0 +#define ETDM_IN1_INT_ODD_FLAG_MASK 0x1 +#define ETDM_IN1_INT_ODD_FLAG_MASK_SFT (0x1 << 0) + +/* AFE_ETDM_IN2_BASE_MSB */ +#define ETDM_IN2_BASE_ADDR_MSB_SFT 0 +#define ETDM_IN2_BASE_ADDR_MSB_MASK 0x1ff +#define ETDM_IN2_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_ETDM_IN2_BASE */ +#define ETDM_IN2_BASE_ADDR_SFT 4 +#define ETDM_IN2_BASE_ADDR_MASK 0xfffffff +#define ETDM_IN2_BASE_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_ETDM_IN2_CUR_MSB */ +#define ETDM_IN2_CUR_PTR_MSB_SFT 0 +#define ETDM_IN2_CUR_PTR_MSB_MASK 0x1ff +#define ETDM_IN2_CUR_PTR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_ETDM_IN2_CUR */ +#define ETDM_IN2_CUR_PTR_SFT 0 +#define ETDM_IN2_CUR_PTR_MASK 0xffffffff +#define ETDM_IN2_CUR_PTR_MASK_SFT (0xffffffff << 0) + +/* AFE_ETDM_IN2_END_MSB */ +#define ETDM_IN2_END_ADDR_MSB_SFT 0 +#define ETDM_IN2_END_ADDR_MSB_MASK 0x1ff +#define ETDM_IN2_END_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_ETDM_IN2_END */ +#define ETDM_IN2_END_ADDR_SFT 4 +#define ETDM_IN2_END_ADDR_MASK 0xfffffff +#define ETDM_IN2_END_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_ETDM_IN2_CON0 */ +#define ETDM_IN2_CH_NUM_SFT 28 +#define ETDM_IN2_CH_NUM_MASK 0xf +#define ETDM_IN2_CH_NUM_MASK_SFT (0xf << 28) +#define ETDM_IN2_ON_SFT 27 +#define ETDM_IN2_ON_MASK 0x1 +#define ETDM_IN2_ON_MASK_SFT (0x1 << 27) +#define ETDM_IN2_REG_CH_SHIFT_MODE_SFT 26 +#define ETDM_IN2_REG_CH_SHIFT_MODE_MASK 0x1 +#define ETDM_IN2_REG_CH_SHIFT_MODE_MASK_SFT (0x1 << 26) +#define ETDM_IN2_RG_FORCE_NO_MASK_EXTRA_SFT 25 +#define ETDM_IN2_RG_FORCE_NO_MASK_EXTRA_MASK 0x1 +#define ETDM_IN2_RG_FORCE_NO_MASK_EXTRA_MASK_SFT (0x1 << 25) +#define ETDM_IN2_SW_CLEAR_BUF_FULL_SFT 24 +#define ETDM_IN2_SW_CLEAR_BUF_FULL_MASK 0x1 +#define ETDM_IN2_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 24) +#define ETDM_IN2_ULTRA_TH_SFT 20 +#define ETDM_IN2_ULTRA_TH_MASK 0xf +#define ETDM_IN2_ULTRA_TH_MASK_SFT (0xf << 20) +#define ETDM_IN2_NORMAL_MODE_SFT 17 +#define ETDM_IN2_NORMAL_MODE_MASK 0x1 +#define ETDM_IN2_NORMAL_MODE_MASK_SFT (0x1 << 17) +#define ETDM_IN2_ODD_USE_EVEN_SFT 16 +#define ETDM_IN2_ODD_USE_EVEN_MASK 0x1 +#define ETDM_IN2_ODD_USE_EVEN_MASK_SFT (0x1 << 16) +#define ETDM_IN2_AXI_REQ_MAXLEN_SFT 12 +#define ETDM_IN2_AXI_REQ_MAXLEN_MASK 0x3 +#define ETDM_IN2_AXI_REQ_MAXLEN_MASK_SFT (0x3 << 12) +#define ETDM_IN2_AXI_REQ_MINLEN_SFT 8 +#define ETDM_IN2_AXI_REQ_MINLEN_MASK 0x3 +#define ETDM_IN2_AXI_REQ_MINLEN_MASK_SFT (0x3 << 8) +#define ETDM_IN2_HALIGN_SFT 7 +#define ETDM_IN2_HALIGN_MASK 0x1 +#define ETDM_IN2_HALIGN_MASK_SFT (0x1 << 7) +#define ETDM_IN2_SIGN_EXT_SFT 6 +#define ETDM_IN2_SIGN_EXT_MASK 0x1 +#define ETDM_IN2_SIGN_EXT_MASK_SFT (0x1 << 6) +#define ETDM_IN2_HD_MODE_SFT 4 +#define ETDM_IN2_HD_MODE_MASK 0x3 +#define ETDM_IN2_HD_MODE_MASK_SFT (0x3 << 4) +#define ETDM_IN2_MAKE_EXTRA_UPDATE_SFT 3 +#define ETDM_IN2_MAKE_EXTRA_UPDATE_MASK 0x1 +#define ETDM_IN2_MAKE_EXTRA_UPDATE_MASK_SFT (0x1 << 3) +#define ETDM_IN2_AGENT_FREE_RUN_SFT 2 +#define ETDM_IN2_AGENT_FREE_RUN_MASK 0x1 +#define ETDM_IN2_AGENT_FREE_RUN_MASK_SFT (0x1 << 2) +#define ETDM_IN2_USE_INT_ODD_SFT 1 +#define ETDM_IN2_USE_INT_ODD_MASK 0x1 +#define ETDM_IN2_USE_INT_ODD_MASK_SFT (0x1 << 1) +#define ETDM_IN2_INT_ODD_FLAG_SFT 0 +#define ETDM_IN2_INT_ODD_FLAG_MASK 0x1 +#define ETDM_IN2_INT_ODD_FLAG_MASK_SFT (0x1 << 0) + +/* AFE_ETDM_IN3_BASE_MSB */ +#define ETDM_IN3_BASE_ADDR_MSB_SFT 0 +#define ETDM_IN3_BASE_ADDR_MSB_MASK 0x1ff +#define ETDM_IN3_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_ETDM_IN3_BASE */ +#define ETDM_IN3_BASE_ADDR_SFT 4 +#define ETDM_IN3_BASE_ADDR_MASK 0xfffffff +#define ETDM_IN3_BASE_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_ETDM_IN3_CUR_MSB */ +#define ETDM_IN3_CUR_PTR_MSB_SFT 0 +#define ETDM_IN3_CUR_PTR_MSB_MASK 0x1ff +#define ETDM_IN3_CUR_PTR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_ETDM_IN3_CUR */ +#define ETDM_IN3_CUR_PTR_SFT 0 +#define ETDM_IN3_CUR_PTR_MASK 0xffffffff +#define ETDM_IN3_CUR_PTR_MASK_SFT (0xffffffff << 0) + +/* AFE_ETDM_IN3_END_MSB */ +#define ETDM_IN3_END_ADDR_MSB_SFT 0 +#define ETDM_IN3_END_ADDR_MSB_MASK 0x1ff +#define ETDM_IN3_END_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_ETDM_IN3_END */ +#define ETDM_IN3_END_ADDR_SFT 4 +#define ETDM_IN3_END_ADDR_MASK 0xfffffff +#define ETDM_IN3_END_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_ETDM_IN3_CON0 */ +#define ETDM_IN3_CH_NUM_SFT 28 +#define ETDM_IN3_CH_NUM_MASK 0xf +#define ETDM_IN3_CH_NUM_MASK_SFT (0xf << 28) +#define ETDM_IN3_ON_SFT 27 +#define ETDM_IN3_ON_MASK 0x1 +#define ETDM_IN3_ON_MASK_SFT (0x1 << 27) +#define ETDM_IN3_REG_CH_SHIFT_MODE_SFT 26 +#define ETDM_IN3_REG_CH_SHIFT_MODE_MASK 0x1 +#define ETDM_IN3_REG_CH_SHIFT_MODE_MASK_SFT (0x1 << 26) +#define ETDM_IN3_RG_FORCE_NO_MASK_EXTRA_SFT 25 +#define ETDM_IN3_RG_FORCE_NO_MASK_EXTRA_MASK 0x1 +#define ETDM_IN3_RG_FORCE_NO_MASK_EXTRA_MASK_SFT (0x1 << 25) +#define ETDM_IN3_SW_CLEAR_BUF_FULL_SFT 24 +#define ETDM_IN3_SW_CLEAR_BUF_FULL_MASK 0x1 +#define ETDM_IN3_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 24) +#define ETDM_IN3_ULTRA_TH_SFT 20 +#define ETDM_IN3_ULTRA_TH_MASK 0xf +#define ETDM_IN3_ULTRA_TH_MASK_SFT (0xf << 20) +#define ETDM_IN3_NORMAL_MODE_SFT 17 +#define ETDM_IN3_NORMAL_MODE_MASK 0x1 +#define ETDM_IN3_NORMAL_MODE_MASK_SFT (0x1 << 17) +#define ETDM_IN3_ODD_USE_EVEN_SFT 16 +#define ETDM_IN3_ODD_USE_EVEN_MASK 0x1 +#define ETDM_IN3_ODD_USE_EVEN_MASK_SFT (0x1 << 16) +#define ETDM_IN3_AXI_REQ_MAXLEN_SFT 12 +#define ETDM_IN3_AXI_REQ_MAXLEN_MASK 0x3 +#define ETDM_IN3_AXI_REQ_MAXLEN_MASK_SFT (0x3 << 12) +#define ETDM_IN3_AXI_REQ_MINLEN_SFT 8 +#define ETDM_IN3_AXI_REQ_MINLEN_MASK 0x3 +#define ETDM_IN3_AXI_REQ_MINLEN_MASK_SFT (0x3 << 8) +#define ETDM_IN3_HALIGN_SFT 7 +#define ETDM_IN3_HALIGN_MASK 0x1 +#define ETDM_IN3_HALIGN_MASK_SFT (0x1 << 7) +#define ETDM_IN3_SIGN_EXT_SFT 6 +#define ETDM_IN3_SIGN_EXT_MASK 0x1 +#define ETDM_IN3_SIGN_EXT_MASK_SFT (0x1 << 6) +#define ETDM_IN3_HD_MODE_SFT 4 +#define ETDM_IN3_HD_MODE_MASK 0x3 +#define ETDM_IN3_HD_MODE_MASK_SFT (0x3 << 4) +#define ETDM_IN3_MAKE_EXTRA_UPDATE_SFT 3 +#define ETDM_IN3_MAKE_EXTRA_UPDATE_MASK 0x1 +#define ETDM_IN3_MAKE_EXTRA_UPDATE_MASK_SFT (0x1 << 3) +#define ETDM_IN3_AGENT_FREE_RUN_SFT 2 +#define ETDM_IN3_AGENT_FREE_RUN_MASK 0x1 +#define ETDM_IN3_AGENT_FREE_RUN_MASK_SFT (0x1 << 2) +#define ETDM_IN3_USE_INT_ODD_SFT 1 +#define ETDM_IN3_USE_INT_ODD_MASK 0x1 +#define ETDM_IN3_USE_INT_ODD_MASK_SFT (0x1 << 1) +#define ETDM_IN3_INT_ODD_FLAG_SFT 0 +#define ETDM_IN3_INT_ODD_FLAG_MASK 0x1 +#define ETDM_IN3_INT_ODD_FLAG_MASK_SFT (0x1 << 0) + +/* AFE_ETDM_IN4_BASE_MSB */ +#define ETDM_IN4_BASE_ADDR_MSB_SFT 0 +#define ETDM_IN4_BASE_ADDR_MSB_MASK 0x1ff +#define ETDM_IN4_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_ETDM_IN4_BASE */ +#define ETDM_IN4_BASE_ADDR_SFT 4 +#define ETDM_IN4_BASE_ADDR_MASK 0xfffffff +#define ETDM_IN4_BASE_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_ETDM_IN4_CUR_MSB */ +#define ETDM_IN4_CUR_PTR_MSB_SFT 0 +#define ETDM_IN4_CUR_PTR_MSB_MASK 0x1ff +#define ETDM_IN4_CUR_PTR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_ETDM_IN4_CUR */ +#define ETDM_IN4_CUR_PTR_SFT 0 +#define ETDM_IN4_CUR_PTR_MASK 0xffffffff +#define ETDM_IN4_CUR_PTR_MASK_SFT (0xffffffff << 0) + +/* AFE_ETDM_IN4_END_MSB */ +#define ETDM_IN4_END_ADDR_MSB_SFT 0 +#define ETDM_IN4_END_ADDR_MSB_MASK 0x1ff +#define ETDM_IN4_END_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_ETDM_IN4_END */ +#define ETDM_IN4_END_ADDR_SFT 4 +#define ETDM_IN4_END_ADDR_MASK 0xfffffff +#define ETDM_IN4_END_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_ETDM_IN4_CON0 */ +#define ETDM_IN4_CH_NUM_SFT 28 +#define ETDM_IN4_CH_NUM_MASK 0xf +#define ETDM_IN4_CH_NUM_MASK_SFT (0xf << 28) +#define ETDM_IN4_ON_SFT 27 +#define ETDM_IN4_ON_MASK 0x1 +#define ETDM_IN4_ON_MASK_SFT (0x1 << 27) +#define ETDM_IN4_REG_CH_SHIFT_MODE_SFT 26 +#define ETDM_IN4_REG_CH_SHIFT_MODE_MASK 0x1 +#define ETDM_IN4_REG_CH_SHIFT_MODE_MASK_SFT (0x1 << 26) +#define ETDM_IN4_RG_FORCE_NO_MASK_EXTRA_SFT 25 +#define ETDM_IN4_RG_FORCE_NO_MASK_EXTRA_MASK 0x1 +#define ETDM_IN4_RG_FORCE_NO_MASK_EXTRA_MASK_SFT (0x1 << 25) +#define ETDM_IN4_SW_CLEAR_BUF_FULL_SFT 24 +#define ETDM_IN4_SW_CLEAR_BUF_FULL_MASK 0x1 +#define ETDM_IN4_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 24) +#define ETDM_IN4_ULTRA_TH_SFT 20 +#define ETDM_IN4_ULTRA_TH_MASK 0xf +#define ETDM_IN4_ULTRA_TH_MASK_SFT (0xf << 20) +#define ETDM_IN4_NORMAL_MODE_SFT 17 +#define ETDM_IN4_NORMAL_MODE_MASK 0x1 +#define ETDM_IN4_NORMAL_MODE_MASK_SFT (0x1 << 17) +#define ETDM_IN4_ODD_USE_EVEN_SFT 16 +#define ETDM_IN4_ODD_USE_EVEN_MASK 0x1 +#define ETDM_IN4_ODD_USE_EVEN_MASK_SFT (0x1 << 16) +#define ETDM_IN4_AXI_REQ_MAXLEN_SFT 12 +#define ETDM_IN4_AXI_REQ_MAXLEN_MASK 0x3 +#define ETDM_IN4_AXI_REQ_MAXLEN_MASK_SFT (0x3 << 12) +#define ETDM_IN4_AXI_REQ_MINLEN_SFT 8 +#define ETDM_IN4_AXI_REQ_MINLEN_MASK 0x3 +#define ETDM_IN4_AXI_REQ_MINLEN_MASK_SFT (0x3 << 8) +#define ETDM_IN4_HALIGN_SFT 7 +#define ETDM_IN4_HALIGN_MASK 0x1 +#define ETDM_IN4_HALIGN_MASK_SFT (0x1 << 7) +#define ETDM_IN4_SIGN_EXT_SFT 6 +#define ETDM_IN4_SIGN_EXT_MASK 0x1 +#define ETDM_IN4_SIGN_EXT_MASK_SFT (0x1 << 6) +#define ETDM_IN4_HD_MODE_SFT 4 +#define ETDM_IN4_HD_MODE_MASK 0x3 +#define ETDM_IN4_HD_MODE_MASK_SFT (0x3 << 4) +#define ETDM_IN4_MAKE_EXTRA_UPDATE_SFT 3 +#define ETDM_IN4_MAKE_EXTRA_UPDATE_MASK 0x1 +#define ETDM_IN4_MAKE_EXTRA_UPDATE_MASK_SFT (0x1 << 3) +#define ETDM_IN4_AGENT_FREE_RUN_SFT 2 +#define ETDM_IN4_AGENT_FREE_RUN_MASK 0x1 +#define ETDM_IN4_AGENT_FREE_RUN_MASK_SFT (0x1 << 2) +#define ETDM_IN4_USE_INT_ODD_SFT 1 +#define ETDM_IN4_USE_INT_ODD_MASK 0x1 +#define ETDM_IN4_USE_INT_ODD_MASK_SFT (0x1 << 1) +#define ETDM_IN4_INT_ODD_FLAG_SFT 0 +#define ETDM_IN4_INT_ODD_FLAG_MASK 0x1 +#define ETDM_IN4_INT_ODD_FLAG_MASK_SFT (0x1 << 0) + +/* AFE_ETDM_IN5_BASE_MSB */ +#define ETDM_IN5_BASE_ADDR_MSB_SFT 0 +#define ETDM_IN5_BASE_ADDR_MSB_MASK 0x1ff +#define ETDM_IN5_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_ETDM_IN5_BASE */ +#define ETDM_IN5_BASE_ADDR_SFT 4 +#define ETDM_IN5_BASE_ADDR_MASK 0xfffffff +#define ETDM_IN5_BASE_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_ETDM_IN5_CUR_MSB */ +#define ETDM_IN5_CUR_PTR_MSB_SFT 0 +#define ETDM_IN5_CUR_PTR_MSB_MASK 0x1ff +#define ETDM_IN5_CUR_PTR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_ETDM_IN5_CUR */ +#define ETDM_IN5_CUR_PTR_SFT 0 +#define ETDM_IN5_CUR_PTR_MASK 0xffffffff +#define ETDM_IN5_CUR_PTR_MASK_SFT (0xffffffff << 0) + +/* AFE_ETDM_IN5_END_MSB */ +#define ETDM_IN5_END_ADDR_MSB_SFT 0 +#define ETDM_IN5_END_ADDR_MSB_MASK 0x1ff +#define ETDM_IN5_END_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_ETDM_IN5_END */ +#define ETDM_IN5_END_ADDR_SFT 4 +#define ETDM_IN5_END_ADDR_MASK 0xfffffff +#define ETDM_IN5_END_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_ETDM_IN5_CON0 */ +#define ETDM_IN5_CH_NUM_SFT 28 +#define ETDM_IN5_CH_NUM_MASK 0xf +#define ETDM_IN5_CH_NUM_MASK_SFT (0xf << 28) +#define ETDM_IN5_ON_SFT 27 +#define ETDM_IN5_ON_MASK 0x1 +#define ETDM_IN5_ON_MASK_SFT (0x1 << 27) +#define ETDM_IN5_REG_CH_SHIFT_MODE_SFT 26 +#define ETDM_IN5_REG_CH_SHIFT_MODE_MASK 0x1 +#define ETDM_IN5_REG_CH_SHIFT_MODE_MASK_SFT (0x1 << 26) +#define ETDM_IN5_RG_FORCE_NO_MASK_EXTRA_SFT 25 +#define ETDM_IN5_RG_FORCE_NO_MASK_EXTRA_MASK 0x1 +#define ETDM_IN5_RG_FORCE_NO_MASK_EXTRA_MASK_SFT (0x1 << 25) +#define ETDM_IN5_SW_CLEAR_BUF_FULL_SFT 24 +#define ETDM_IN5_SW_CLEAR_BUF_FULL_MASK 0x1 +#define ETDM_IN5_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 24) +#define ETDM_IN5_ULTRA_TH_SFT 20 +#define ETDM_IN5_ULTRA_TH_MASK 0xf +#define ETDM_IN5_ULTRA_TH_MASK_SFT (0xf << 20) +#define ETDM_IN5_NORMAL_MODE_SFT 17 +#define ETDM_IN5_NORMAL_MODE_MASK 0x1 +#define ETDM_IN5_NORMAL_MODE_MASK_SFT (0x1 << 17) +#define ETDM_IN5_ODD_USE_EVEN_SFT 16 +#define ETDM_IN5_ODD_USE_EVEN_MASK 0x1 +#define ETDM_IN5_ODD_USE_EVEN_MASK_SFT (0x1 << 16) +#define ETDM_IN5_AXI_REQ_MAXLEN_SFT 12 +#define ETDM_IN5_AXI_REQ_MAXLEN_MASK 0x3 +#define ETDM_IN5_AXI_REQ_MAXLEN_MASK_SFT (0x3 << 12) +#define ETDM_IN5_AXI_REQ_MINLEN_SFT 8 +#define ETDM_IN5_AXI_REQ_MINLEN_MASK 0x3 +#define ETDM_IN5_AXI_REQ_MINLEN_MASK_SFT (0x3 << 8) +#define ETDM_IN5_HALIGN_SFT 7 +#define ETDM_IN5_HALIGN_MASK 0x1 +#define ETDM_IN5_HALIGN_MASK_SFT (0x1 << 7) +#define ETDM_IN5_SIGN_EXT_SFT 6 +#define ETDM_IN5_SIGN_EXT_MASK 0x1 +#define ETDM_IN5_SIGN_EXT_MASK_SFT (0x1 << 6) +#define ETDM_IN5_HD_MODE_SFT 4 +#define ETDM_IN5_HD_MODE_MASK 0x3 +#define ETDM_IN5_HD_MODE_MASK_SFT (0x3 << 4) +#define ETDM_IN5_MAKE_EXTRA_UPDATE_SFT 3 +#define ETDM_IN5_MAKE_EXTRA_UPDATE_MASK 0x1 +#define ETDM_IN5_MAKE_EXTRA_UPDATE_MASK_SFT (0x1 << 3) +#define ETDM_IN5_AGENT_FREE_RUN_SFT 2 +#define ETDM_IN5_AGENT_FREE_RUN_MASK 0x1 +#define ETDM_IN5_AGENT_FREE_RUN_MASK_SFT (0x1 << 2) +#define ETDM_IN5_USE_INT_ODD_SFT 1 +#define ETDM_IN5_USE_INT_ODD_MASK 0x1 +#define ETDM_IN5_USE_INT_ODD_MASK_SFT (0x1 << 1) +#define ETDM_IN5_INT_ODD_FLAG_SFT 0 +#define ETDM_IN5_INT_ODD_FLAG_MASK 0x1 +#define ETDM_IN5_INT_ODD_FLAG_MASK_SFT (0x1 << 0) + +/* AFE_ETDM_IN6_BASE_MSB */ +#define ETDM_IN6_BASE_ADDR_MSB_SFT 0 +#define ETDM_IN6_BASE_ADDR_MSB_MASK 0x1ff +#define ETDM_IN6_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_ETDM_IN6_BASE */ +#define ETDM_IN6_BASE_ADDR_SFT 4 +#define ETDM_IN6_BASE_ADDR_MASK 0xfffffff +#define ETDM_IN6_BASE_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_ETDM_IN6_CUR_MSB */ +#define ETDM_IN6_CUR_PTR_MSB_SFT 0 +#define ETDM_IN6_CUR_PTR_MSB_MASK 0x1ff +#define ETDM_IN6_CUR_PTR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_ETDM_IN6_CUR */ +#define ETDM_IN6_CUR_PTR_SFT 0 +#define ETDM_IN6_CUR_PTR_MASK 0xffffffff +#define ETDM_IN6_CUR_PTR_MASK_SFT (0xffffffff << 0) + +/* AFE_ETDM_IN6_END_MSB */ +#define ETDM_IN6_END_ADDR_MSB_SFT 0 +#define ETDM_IN6_END_ADDR_MSB_MASK 0x1ff +#define ETDM_IN6_END_ADDR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_ETDM_IN6_END */ +#define ETDM_IN6_END_ADDR_SFT 4 +#define ETDM_IN6_END_ADDR_MASK 0xfffffff +#define ETDM_IN6_END_ADDR_MASK_SFT (0xfffffff << 4) + +/* AFE_ETDM_IN6_CON0 */ +#define ETDM_IN6_CH_NUM_SFT 28 +#define ETDM_IN6_CH_NUM_MASK 0xf +#define ETDM_IN6_CH_NUM_MASK_SFT (0xf << 28) +#define ETDM_IN6_ON_SFT 27 +#define ETDM_IN6_ON_MASK 0x1 +#define ETDM_IN6_ON_MASK_SFT (0x1 << 27) +#define ETDM_IN6_REG_CH_SHIFT_MODE_SFT 26 +#define ETDM_IN6_REG_CH_SHIFT_MODE_MASK 0x1 +#define ETDM_IN6_REG_CH_SHIFT_MODE_MASK_SFT (0x1 << 26) +#define ETDM_IN6_RG_FORCE_NO_MASK_EXTRA_SFT 25 +#define ETDM_IN6_RG_FORCE_NO_MASK_EXTRA_MASK 0x1 +#define ETDM_IN6_RG_FORCE_NO_MASK_EXTRA_MASK_SFT (0x1 << 25) +#define ETDM_IN6_SW_CLEAR_BUF_FULL_SFT 24 +#define ETDM_IN6_SW_CLEAR_BUF_FULL_MASK 0x1 +#define ETDM_IN6_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 24) +#define ETDM_IN6_ULTRA_TH_SFT 20 +#define ETDM_IN6_ULTRA_TH_MASK 0xf +#define ETDM_IN6_ULTRA_TH_MASK_SFT (0xf << 20) +#define ETDM_IN6_NORMAL_MODE_SFT 17 +#define ETDM_IN6_NORMAL_MODE_MASK 0x1 +#define ETDM_IN6_NORMAL_MODE_MASK_SFT (0x1 << 17) +#define ETDM_IN6_ODD_USE_EVEN_SFT 16 +#define ETDM_IN6_ODD_USE_EVEN_MASK 0x1 +#define ETDM_IN6_ODD_USE_EVEN_MASK_SFT (0x1 << 16) +#define ETDM_IN6_AXI_REQ_MAXLEN_SFT 12 +#define ETDM_IN6_AXI_REQ_MAXLEN_MASK 0x3 +#define ETDM_IN6_AXI_REQ_MAXLEN_MASK_SFT (0x3 << 12) +#define ETDM_IN6_AXI_REQ_MINLEN_SFT 8 +#define ETDM_IN6_AXI_REQ_MINLEN_MASK 0x3 +#define ETDM_IN6_AXI_REQ_MINLEN_MASK_SFT (0x3 << 8) +#define ETDM_IN6_HALIGN_SFT 7 +#define ETDM_IN6_HALIGN_MASK 0x1 +#define ETDM_IN6_HALIGN_MASK_SFT (0x1 << 7) +#define ETDM_IN6_SIGN_EXT_SFT 6 +#define ETDM_IN6_SIGN_EXT_MASK 0x1 +#define ETDM_IN6_SIGN_EXT_MASK_SFT (0x1 << 6) +#define ETDM_IN6_HD_MODE_SFT 4 +#define ETDM_IN6_HD_MODE_MASK 0x3 +#define ETDM_IN6_HD_MODE_MASK_SFT (0x3 << 4) +#define ETDM_IN6_MAKE_EXTRA_UPDATE_SFT 3 +#define ETDM_IN6_MAKE_EXTRA_UPDATE_MASK 0x1 +#define ETDM_IN6_MAKE_EXTRA_UPDATE_MASK_SFT (0x1 << 3) +#define ETDM_IN6_AGENT_FREE_RUN_SFT 2 +#define ETDM_IN6_AGENT_FREE_RUN_MASK 0x1 +#define ETDM_IN6_AGENT_FREE_RUN_MASK_SFT (0x1 << 2) +#define ETDM_IN6_USE_INT_ODD_SFT 1 +#define ETDM_IN6_USE_INT_ODD_MASK 0x1 +#define ETDM_IN6_USE_INT_ODD_MASK_SFT (0x1 << 1) +#define ETDM_IN6_INT_ODD_FLAG_SFT 0 +#define ETDM_IN6_INT_ODD_FLAG_MASK 0x1 +#define ETDM_IN6_INT_ODD_FLAG_MASK_SFT (0x1 << 0) + +/* AFE_HDMI_OUT_BASE_MSB */ +#define AFE_HDMI_OUT_BASE_MSB_SFT 0 +#define AFE_HDMI_OUT_BASE_MSB_MASK 0x1ff +#define AFE_HDMI_OUT_BASE_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_HDMI_OUT_BASE */ +#define AFE_HDMI_OUT_BASE_SFT 4 +#define AFE_HDMI_OUT_BASE_MASK 0xfffffff +#define AFE_HDMI_OUT_BASE_MASK_SFT (0xfffffff << 4) + +/* AFE_HDMI_OUT_CUR_MSB */ +#define AFE_HDMI_OUT_CUR_MSB_SFT 0 +#define AFE_HDMI_OUT_CUR_MSB_MASK 0x1ff +#define AFE_HDMI_OUT_CUR_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_HDMI_OUT_CUR */ +#define AFE_HDMI_OUT_CUR_SFT 0 +#define AFE_HDMI_OUT_CUR_MASK 0xffffffff +#define AFE_HDMI_OUT_CUR_MASK_SFT (0xffffffff << 0) + +/* AFE_HDMI_OUT_END_MSB */ +#define AFE_HDMI_OUT_END_MSB_SFT 0 +#define AFE_HDMI_OUT_END_MSB_MASK 0x1ff +#define AFE_HDMI_OUT_END_MSB_MASK_SFT (0x1ff << 0) + +/* AFE_HDMI_OUT_END */ +#define AFE_HDMI_OUT_END_SFT 4 +#define AFE_HDMI_OUT_END_MASK 0xfffffff +#define AFE_HDMI_OUT_END_MASK_SFT (0xfffffff << 4) +#define AFE_HDMI_OUT_END_LSB_SFT 0 +#define AFE_HDMI_OUT_END_LSB_MASK 0xf +#define AFE_HDMI_OUT_END_LSB_MASK_SFT (0xf << 0) + +/* AFE_HDMI_OUT_CON0 */ +#define HDMI_OUT_ON_SFT 28 +#define HDMI_OUT_ON_MASK 0x1 +#define HDMI_OUT_ON_MASK_SFT (0x1 << 28) +#define HDMI_CH_NUM_SFT 24 +#define HDMI_CH_NUM_MASK 0xf +#define HDMI_CH_NUM_MASK_SFT (0xf << 24) +#define HDMI_OUT_ONE_HEART_SEL_SFT 22 +#define HDMI_OUT_ONE_HEART_SEL_MASK 0x3 +#define HDMI_OUT_ONE_HEART_SEL_MASK_SFT (0x3 << 22) +#define HDMI_OUT_MINLEN_SFT 20 +#define HDMI_OUT_MINLEN_MASK 0x3 +#define HDMI_OUT_MINLEN_MASK_SFT (0x3 << 20) +#define HDMI_OUT_MAXLEN_SFT 16 +#define HDMI_OUT_MAXLEN_MASK 0x3 +#define HDMI_OUT_MAXLEN_MASK_SFT (0x3 << 16) +#define HDMI_OUT_SW_CLEAR_BUF_EMPTY_SFT 15 +#define HDMI_OUT_SW_CLEAR_BUF_EMPTY_MASK 0x1 +#define HDMI_OUT_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 15) +#define HDMI_OUT_PBUF_SIZE_SFT 12 +#define HDMI_OUT_PBUF_SIZE_MASK 0x3 +#define HDMI_OUT_PBUF_SIZE_MASK_SFT (0x3 << 12) +#define HDMI_OUT_SW_CLEAR_HDMI_BUF_EMPTY_SFT 7 +#define HDMI_OUT_SW_CLEAR_HDMI_BUF_EMPTY_MASK 0x1 +#define HDMI_OUT_SW_CLEAR_HDMI_BUF_EMPTY_MASK_SFT (0x1 << 7) +#define HDMI_OUT_NORMAL_MODE_SFT 5 +#define HDMI_OUT_NORMAL_MODE_MASK 0x1 +#define HDMI_OUT_NORMAL_MODE_MASK_SFT (0x1 << 5) +#define HDMI_OUT_HALIGN_SFT 4 +#define HDMI_OUT_HALIGN_MASK 0x1 +#define HDMI_OUT_HALIGN_MASK_SFT (0x1 << 4) +#define HDMI_OUT_HD_MODE_SFT 0 +#define HDMI_OUT_HD_MODE_MASK 0x3 +#define HDMI_OUT_HD_MODE_MASK_SFT (0x3 << 0) + +/* AFE_VUL24_RCH_MON */ +#define VUL24_RCH_DATA_SFT 0 +#define VUL24_RCH_DATA_MASK 0xffffffff +#define VUL24_RCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_VUL24_LCH_MON */ +#define VUL24_LCH_DATA_SFT 0 +#define VUL24_LCH_DATA_MASK 0xffffffff +#define VUL24_LCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_VUL25_RCH_MON */ +#define VUL25_RCH_DATA_SFT 0 +#define VUL25_RCH_DATA_MASK 0xffffffff +#define VUL25_RCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_VUL25_LCH_MON */ +#define VUL25_LCH_DATA_SFT 0 +#define VUL25_LCH_DATA_MASK 0xffffffff +#define VUL25_LCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_VUL26_RCH_MON */ +#define VUL26_RCH_DATA_SFT 0 +#define VUL26_RCH_DATA_MASK 0xffffffff +#define VUL26_RCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_VUL26_LCH_MON */ +#define VUL26_LCH_DATA_SFT 0 +#define VUL26_LCH_DATA_MASK 0xffffffff +#define VUL26_LCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_VUL_CM0_RCH_MON */ +#define VUL_CM0_RCH_DATA_SFT 0 +#define VUL_CM0_RCH_DATA_MASK 0xffffffff +#define VUL_CM0_RCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_VUL_CM0_LCH_MON */ +#define VUL_CM0_LCH_DATA_SFT 0 +#define VUL_CM0_LCH_DATA_MASK 0xffffffff +#define VUL_CM0_LCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_VUL_CM1_RCH_MON */ +#define VUL_CM1_RCH_DATA_SFT 0 +#define VUL_CM1_RCH_DATA_MASK 0xffffffff +#define VUL_CM1_RCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_VUL_CM1_LCH_MON */ +#define VUL_CM1_LCH_DATA_SFT 0 +#define VUL_CM1_LCH_DATA_MASK 0xffffffff +#define VUL_CM1_LCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_VUL_CM2_RCH_MON */ +#define VUL_CM2_RCH_DATA_SFT 0 +#define VUL_CM2_RCH_DATA_MASK 0xffffffff +#define VUL_CM2_RCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_VUL_CM2_LCH_MON */ +#define VUL_CM2_LCH_DATA_SFT 0 +#define VUL_CM2_LCH_DATA_MASK 0xffffffff +#define VUL_CM2_LCH_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_DL_4CH_CH0_MON */ +#define DL_4CH_CH0_DATA_SFT 0 +#define DL_4CH_CH0_DATA_MASK 0xffffffff +#define DL_4CH_CH0_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_DL_4CH_CH1_MON */ +#define DL_4CH_CH1_DATA_SFT 0 +#define DL_4CH_CH1_DATA_MASK 0xffffffff +#define DL_4CH_CH1_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_DL_4CH_CH2_MON */ +#define DL_4CH_CH2_DATA_SFT 0 +#define DL_4CH_CH2_DATA_MASK 0xffffffff +#define DL_4CH_CH2_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_DL_4CH_CH3_MON */ +#define DL_4CH_CH3_DATA_SFT 0 +#define DL_4CH_CH3_DATA_MASK 0xffffffff +#define DL_4CH_CH3_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_DL_24CH_CH0_MON */ +#define DL_24CH_CH0_DATA_SFT 0 +#define DL_24CH_CH0_DATA_MASK 0xffffffff +#define DL_24CH_CH0_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_DL_24CH_CH1_MON */ +#define DL_24CH_CH1_DATA_SFT 0 +#define DL_24CH_CH1_DATA_MASK 0xffffffff +#define DL_24CH_CH1_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_DL_24CH_CH2_MON */ +#define DL_24CH_CH2_DATA_SFT 0 +#define DL_24CH_CH2_DATA_MASK 0xffffffff +#define DL_24CH_CH2_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_DL_24CH_CH3_MON */ +#define DL_24CH_CH3_DATA_SFT 0 +#define DL_24CH_CH3_DATA_MASK 0xffffffff +#define DL_24CH_CH3_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_DL_24CH_CH4_MON */ +#define DL_24CH_CH4_DATA_SFT 0 +#define DL_24CH_CH4_DATA_MASK 0xffffffff +#define DL_24CH_CH4_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_DL_24CH_CH5_MON */ +#define DL_24CH_CH5_DATA_SFT 0 +#define DL_24CH_CH5_DATA_MASK 0xffffffff +#define DL_24CH_CH5_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_DL_24CH_CH6_MON */ +#define DL_24CH_CH6_DATA_SFT 0 +#define DL_24CH_CH6_DATA_MASK 0xffffffff +#define DL_24CH_CH6_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_DL_24CH_CH7_MON */ +#define DL_24CH_CH7_DATA_SFT 0 +#define DL_24CH_CH7_DATA_MASK 0xffffffff +#define DL_24CH_CH7_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_DL_24CH_CH8_MON */ +#define DL_24CH_CH8_DATA_SFT 0 +#define DL_24CH_CH8_DATA_MASK 0xffffffff +#define DL_24CH_CH8_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_DL_24CH_CH9_MON */ +#define DL_24CH_CH9_DATA_SFT 0 +#define DL_24CH_CH9_DATA_MASK 0xffffffff +#define DL_24CH_CH9_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_DL_24CH_CH10_MON */ +#define DL_24CH_CH10_DATA_SFT 0 +#define DL_24CH_CH10_DATA_MASK 0xffffffff +#define DL_24CH_CH10_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_DL_24CH_CH11_MON */ +#define DL_24CH_CH11_DATA_SFT 0 +#define DL_24CH_CH11_DATA_MASK 0xffffffff +#define DL_24CH_CH11_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_DL_24CH_CH12_MON */ +#define DL_24CH_CH12_DATA_SFT 0 +#define DL_24CH_CH12_DATA_MASK 0xffffffff +#define DL_24CH_CH12_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_DL_24CH_CH13_MON */ +#define DL_24CH_CH13_DATA_SFT 0 +#define DL_24CH_CH13_DATA_MASK 0xffffffff +#define DL_24CH_CH13_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_DL_24CH_CH14_MON */ +#define DL_24CH_CH14_DATA_SFT 0 +#define DL_24CH_CH14_DATA_MASK 0xffffffff +#define DL_24CH_CH14_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_DL_24CH_CH15_MON */ +#define DL_24CH_CH15_DATA_SFT 0 +#define DL_24CH_CH15_DATA_MASK 0xffffffff +#define DL_24CH_CH15_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_SRAM_BOUND */ +#define SECURE_BIT_SFT 19 +#define SECURE_BIT_MASK 0x1 +#define SECURE_BIT_MASK_SFT (0x1 << 19) +#define SECURE_SRAM_BOUND_SFT 0 +#define SECURE_SRAM_BOUND_MASK 0x7ffff +#define SECURE_SRAM_BOUND_MASK_SFT (0x7ffff << 0) + +/* AFE_SECURE_CON0 */ +#define READ_EN15_NS_SFT 31 +#define READ_EN15_NS_MASK 0x1 +#define READ_EN15_NS_MASK_SFT (0x1 << 31) +#define WRITE_EN15_NS_SFT 30 +#define WRITE_EN15_NS_MASK 0x1 +#define WRITE_EN15_NS_MASK_SFT (0x1 << 30) +#define READ_EN14_NS_SFT 29 +#define READ_EN14_NS_MASK 0x1 +#define READ_EN14_NS_MASK_SFT (0x1 << 29) +#define WRITE_EN14_NS_SFT 28 +#define WRITE_EN14_NS_MASK 0x1 +#define WRITE_EN14_NS_MASK_SFT (0x1 << 28) +#define READ_EN13_NS_SFT 27 +#define READ_EN13_NS_MASK 0x1 +#define READ_EN13_NS_MASK_SFT (0x1 << 27) +#define WRITE_EN13_NS_SFT 26 +#define WRITE_EN13_NS_MASK 0x1 +#define WRITE_EN13_NS_MASK_SFT (0x1 << 26) +#define READ_EN12_NS_SFT 25 +#define READ_EN12_NS_MASK 0x1 +#define READ_EN12_NS_MASK_SFT (0x1 << 25) +#define WRITE_EN12_NS_SFT 24 +#define WRITE_EN12_NS_MASK 0x1 +#define WRITE_EN12_NS_MASK_SFT (0x1 << 24) +#define READ_EN11_NS_SFT 23 +#define READ_EN11_NS_MASK 0x1 +#define READ_EN11_NS_MASK_SFT (0x1 << 23) +#define WRITE_EN11_NS_SFT 22 +#define WRITE_EN11_NS_MASK 0x1 +#define WRITE_EN11_NS_MASK_SFT (0x1 << 22) +#define READ_EN10_NS_SFT 21 +#define READ_EN10_NS_MASK 0x1 +#define READ_EN10_NS_MASK_SFT (0x1 << 21) +#define WRITE_EN10_NS_SFT 20 +#define WRITE_EN10_NS_MASK 0x1 +#define WRITE_EN10_NS_MASK_SFT (0x1 << 20) +#define READ_EN9_NS_SFT 19 +#define READ_EN9_NS_MASK 0x1 +#define READ_EN9_NS_MASK_SFT (0x1 << 19) +#define WRITE_EN9_NS_SFT 18 +#define WRITE_EN9_NS_MASK 0x1 +#define WRITE_EN9_NS_MASK_SFT (0x1 << 18) +#define READ_EN8_NS_SFT 17 +#define READ_EN8_NS_MASK 0x1 +#define READ_EN8_NS_MASK_SFT (0x1 << 17) +#define WRITE_EN8_NS_SFT 16 +#define WRITE_EN8_NS_MASK 0x1 +#define WRITE_EN8_NS_MASK_SFT (0x1 << 16) +#define READ_EN7_NS_SFT 15 +#define READ_EN7_NS_MASK 0x1 +#define READ_EN7_NS_MASK_SFT (0x1 << 15) +#define WRITE_EN7_NS_SFT 14 +#define WRITE_EN7_NS_MASK 0x1 +#define WRITE_EN7_NS_MASK_SFT (0x1 << 14) +#define READ_EN6_NS_SFT 13 +#define READ_EN6_NS_MASK 0x1 +#define READ_EN6_NS_MASK_SFT (0x1 << 13) +#define WRITE_EN6_NS_SFT 12 +#define WRITE_EN6_NS_MASK 0x1 +#define WRITE_EN6_NS_MASK_SFT (0x1 << 12) +#define READ_EN5_NS_SFT 11 +#define READ_EN5_NS_MASK 0x1 +#define READ_EN5_NS_MASK_SFT (0x1 << 11) +#define WRITE_EN5_NS_SFT 10 +#define WRITE_EN5_NS_MASK 0x1 +#define WRITE_EN5_NS_MASK_SFT (0x1 << 10) +#define READ_EN4_NS_SFT 9 +#define READ_EN4_NS_MASK 0x1 +#define READ_EN4_NS_MASK_SFT (0x1 << 9) +#define WRITE_EN4_NS_SFT 8 +#define WRITE_EN4_NS_MASK 0x1 +#define WRITE_EN4_NS_MASK_SFT (0x1 << 8) +#define READ_EN3_NS_SFT 7 +#define READ_EN3_NS_MASK 0x1 +#define READ_EN3_NS_MASK_SFT (0x1 << 7) +#define WRITE_EN3_NS_SFT 6 +#define WRITE_EN3_NS_MASK 0x1 +#define WRITE_EN3_NS_MASK_SFT (0x1 << 6) +#define READ_EN2_NS_SFT 5 +#define READ_EN2_NS_MASK 0x1 +#define READ_EN2_NS_MASK_SFT (0x1 << 5) +#define WRITE_EN2_NS_SFT 4 +#define WRITE_EN2_NS_MASK 0x1 +#define WRITE_EN2_NS_MASK_SFT (0x1 << 4) +#define READ_EN1_NS_SFT 3 +#define READ_EN1_NS_MASK 0x1 +#define READ_EN1_NS_MASK_SFT (0x1 << 3) +#define WRITE_EN1_NS_SFT 2 +#define WRITE_EN1_NS_MASK 0x1 +#define WRITE_EN1_NS_MASK_SFT (0x1 << 2) +#define READ_EN0_NS_SFT 1 +#define READ_EN0_NS_MASK 0x1 +#define READ_EN0_NS_MASK_SFT (0x1 << 1) +#define WRITE_EN0_NS_SFT 0 +#define WRITE_EN0_NS_MASK 0x1 +#define WRITE_EN0_NS_MASK_SFT (0x1 << 0) + +/* AFE_SECURE_CON1 */ +#define READ_EN15_S_SFT 31 +#define READ_EN15_S_MASK 0x1 +#define READ_EN15_S_MASK_SFT (0x1 << 31) +#define WRITE_EN15_S_SFT 30 +#define WRITE_EN15_S_MASK 0x1 +#define WRITE_EN15_S_MASK_SFT (0x1 << 30) +#define READ_EN14_S_SFT 29 +#define READ_EN14_S_MASK 0x1 +#define READ_EN14_S_MASK_SFT (0x1 << 29) +#define WRITE_EN14_S_SFT 28 +#define WRITE_EN14_S_MASK 0x1 +#define WRITE_EN14_S_MASK_SFT (0x1 << 28) +#define READ_EN13_S_SFT 27 +#define READ_EN13_S_MASK 0x1 +#define READ_EN13_S_MASK_SFT (0x1 << 27) +#define WRITE_EN13_S_SFT 26 +#define WRITE_EN13_S_MASK 0x1 +#define WRITE_EN13_S_MASK_SFT (0x1 << 26) +#define READ_EN12_S_SFT 25 +#define READ_EN12_S_MASK 0x1 +#define READ_EN12_S_MASK_SFT (0x1 << 25) +#define WRITE_EN12_S_SFT 24 +#define WRITE_EN12_S_MASK 0x1 +#define WRITE_EN12_S_MASK_SFT (0x1 << 24) +#define READ_EN11_S_SFT 23 +#define READ_EN11_S_MASK 0x1 +#define READ_EN11_S_MASK_SFT (0x1 << 23) +#define WRITE_EN11_S_SFT 22 +#define WRITE_EN11_S_MASK 0x1 +#define WRITE_EN11_S_MASK_SFT (0x1 << 22) +#define READ_EN10_S_SFT 21 +#define READ_EN10_S_MASK 0x1 +#define READ_EN10_S_MASK_SFT (0x1 << 21) +#define WRITE_EN10_S_SFT 20 +#define WRITE_EN10_S_MASK 0x1 +#define WRITE_EN10_S_MASK_SFT (0x1 << 20) +#define READ_EN9_S_SFT 19 +#define READ_EN9_S_MASK 0x1 +#define READ_EN9_S_MASK_SFT (0x1 << 19) +#define WRITE_EN9_S_SFT 18 +#define WRITE_EN9_S_MASK 0x1 +#define WRITE_EN9_S_MASK_SFT (0x1 << 18) +#define READ_EN8_S_SFT 17 +#define READ_EN8_S_MASK 0x1 +#define READ_EN8_S_MASK_SFT (0x1 << 17) +#define WRITE_EN8_S_SFT 16 +#define WRITE_EN8_S_MASK 0x1 +#define WRITE_EN8_S_MASK_SFT (0x1 << 16) +#define READ_EN7_S_SFT 15 +#define READ_EN7_S_MASK 0x1 +#define READ_EN7_S_MASK_SFT (0x1 << 15) +#define WRITE_EN7_S_SFT 14 +#define WRITE_EN7_S_MASK 0x1 +#define WRITE_EN7_S_MASK_SFT (0x1 << 14) +#define READ_EN6_S_SFT 13 +#define READ_EN6_S_MASK 0x1 +#define READ_EN6_S_MASK_SFT (0x1 << 13) +#define WRITE_EN6_S_SFT 12 +#define WRITE_EN6_S_MASK 0x1 +#define WRITE_EN6_S_MASK_SFT (0x1 << 12) +#define READ_EN5_S_SFT 11 +#define READ_EN5_S_MASK 0x1 +#define READ_EN5_S_MASK_SFT (0x1 << 11) +#define WRITE_EN5_S_SFT 10 +#define WRITE_EN5_S_MASK 0x1 +#define WRITE_EN5_S_MASK_SFT (0x1 << 10) +#define READ_EN4_S_SFT 9 +#define READ_EN4_S_MASK 0x1 +#define READ_EN4_S_MASK_SFT (0x1 << 9) +#define WRITE_EN4_S_SFT 8 +#define WRITE_EN4_S_MASK 0x1 +#define WRITE_EN4_S_MASK_SFT (0x1 << 8) +#define READ_EN3_S_SFT 7 +#define READ_EN3_S_MASK 0x1 +#define READ_EN3_S_MASK_SFT (0x1 << 7) +#define WRITE_EN3_S_SFT 6 +#define WRITE_EN3_S_MASK 0x1 +#define WRITE_EN3_S_MASK_SFT (0x1 << 6) +#define READ_EN2_S_SFT 5 +#define READ_EN2_S_MASK 0x1 +#define READ_EN2_S_MASK_SFT (0x1 << 5) +#define WRITE_EN2_S_SFT 4 +#define WRITE_EN2_S_MASK 0x1 +#define WRITE_EN2_S_MASK_SFT (0x1 << 4) +#define READ_EN1_S_SFT 3 +#define READ_EN1_S_MASK 0x1 +#define READ_EN1_S_MASK_SFT (0x1 << 3) +#define WRITE_EN1_S_SFT 2 +#define WRITE_EN1_S_MASK 0x1 +#define WRITE_EN1_S_MASK_SFT (0x1 << 2) +#define READ_EN0_S_SFT 1 +#define READ_EN0_S_MASK 0x1 +#define READ_EN0_S_MASK_SFT (0x1 << 1) +#define WRITE_EN0_S_SFT 0 +#define WRITE_EN0_S_MASK 0x1 +#define WRITE_EN0_S_MASK_SFT (0x1 << 0) + +/* AFE_SE_SECURE_CON0 */ +#define AFE_HDMI_SE_SECURE_BIT_SFT 11 +#define AFE_HDMI_SE_SECURE_BIT_MASK 0x1 +#define AFE_HDMI_SE_SECURE_BIT_MASK_SFT (0x1 << 11) +#define AFE_SPDIF2_OUT_SE_SECURE_BIT_SFT 10 +#define AFE_SPDIF2_OUT_SE_SECURE_BIT_MASK 0x1 +#define AFE_SPDIF2_OUT_SE_SECURE_BIT_MASK_SFT (0x1 << 10) +#define AFE_SPDIF_OUT_SE_SECURE_BIT_SFT 9 +#define AFE_SPDIF_OUT_SE_SECURE_BIT_MASK 0x1 +#define AFE_SPDIF_OUT_SE_SECURE_BIT_MASK_SFT (0x1 << 9) +#define AFE_DL8_SE_SECURE_BIT_SFT 8 +#define AFE_DL8_SE_SECURE_BIT_MASK 0x1 +#define AFE_DL8_SE_SECURE_BIT_MASK_SFT (0x1 << 8) +#define AFE_DL7_SE_SECURE_BIT_SFT 7 +#define AFE_DL7_SE_SECURE_BIT_MASK 0x1 +#define AFE_DL7_SE_SECURE_BIT_MASK_SFT (0x1 << 7) +#define AFE_DL6_SE_SECURE_BIT_SFT 6 +#define AFE_DL6_SE_SECURE_BIT_MASK 0x1 +#define AFE_DL6_SE_SECURE_BIT_MASK_SFT (0x1 << 6) +#define AFE_DL5_SE_SECURE_BIT_SFT 5 +#define AFE_DL5_SE_SECURE_BIT_MASK 0x1 +#define AFE_DL5_SE_SECURE_BIT_MASK_SFT (0x1 << 5) +#define AFE_DL4_SE_SECURE_BIT_SFT 4 +#define AFE_DL4_SE_SECURE_BIT_MASK 0x1 +#define AFE_DL4_SE_SECURE_BIT_MASK_SFT (0x1 << 4) +#define AFE_DL3_SE_SECURE_BIT_SFT 3 +#define AFE_DL3_SE_SECURE_BIT_MASK 0x1 +#define AFE_DL3_SE_SECURE_BIT_MASK_SFT (0x1 << 3) +#define AFE_DL2_SE_SECURE_BIT_SFT 2 +#define AFE_DL2_SE_SECURE_BIT_MASK 0x1 +#define AFE_DL2_SE_SECURE_BIT_MASK_SFT (0x1 << 2) +#define AFE_DL1_SE_SECURE_BIT_SFT 1 +#define AFE_DL1_SE_SECURE_BIT_MASK 0x1 +#define AFE_DL1_SE_SECURE_BIT_MASK_SFT (0x1 << 1) +#define AFE_DL0_SE_SECURE_BIT_SFT 0 +#define AFE_DL0_SE_SECURE_BIT_MASK 0x1 +#define AFE_DL0_SE_SECURE_BIT_MASK_SFT (0x1 << 0) + +/* AFE_SE_SECURE_CON1 */ +#define AFE_DL46_SE_SECURE_BIT_SFT 26 +#define AFE_DL46_SE_SECURE_BIT_MASK 0x1 +#define AFE_DL46_SE_SECURE_BIT_MASK_SFT (0x1 << 26) +#define AFE_DL45_SE_SECURE_BIT_SFT 25 +#define AFE_DL45_SE_SECURE_BIT_MASK 0x1 +#define AFE_DL45_SE_SECURE_BIT_MASK_SFT (0x1 << 25) +#define AFE_DL44_SE_SECURE_BIT_SFT 24 +#define AFE_DL44_SE_SECURE_BIT_MASK 0x1 +#define AFE_DL44_SE_SECURE_BIT_MASK_SFT (0x1 << 24) +#define AFE_DL43_SE_SECURE_BIT_SFT 23 +#define AFE_DL43_SE_SECURE_BIT_MASK 0x1 +#define AFE_DL43_SE_SECURE_BIT_MASK_SFT (0x1 << 23) +#define AFE_DL42_SE_SECURE_BIT_SFT 22 +#define AFE_DL42_SE_SECURE_BIT_MASK 0x1 +#define AFE_DL42_SE_SECURE_BIT_MASK_SFT (0x1 << 22) +#define AFE_DL41_SE_SECURE_BIT_SFT 21 +#define AFE_DL41_SE_SECURE_BIT_MASK 0x1 +#define AFE_DL41_SE_SECURE_BIT_MASK_SFT (0x1 << 21) +#define AFE_DL40_SE_SECURE_BIT_SFT 20 +#define AFE_DL40_SE_SECURE_BIT_MASK 0x1 +#define AFE_DL40_SE_SECURE_BIT_MASK_SFT (0x1 << 20) +#define AFE_DL39_SE_SECURE_BIT_SFT 19 +#define AFE_DL39_SE_SECURE_BIT_MASK 0x1 +#define AFE_DL39_SE_SECURE_BIT_MASK_SFT (0x1 << 19) +#define AFE_DL38_SE_SECURE_BIT_SFT 18 +#define AFE_DL38_SE_SECURE_BIT_MASK 0x1 +#define AFE_DL38_SE_SECURE_BIT_MASK_SFT (0x1 << 18) +#define AFE_DL37_SE_SECURE_BIT_SFT 17 +#define AFE_DL37_SE_SECURE_BIT_MASK 0x1 +#define AFE_DL37_SE_SECURE_BIT_MASK_SFT (0x1 << 17) +#define AFE_DL36_SE_SECURE_BIT_SFT 16 +#define AFE_DL36_SE_SECURE_BIT_MASK 0x1 +#define AFE_DL36_SE_SECURE_BIT_MASK_SFT (0x1 << 16) +#define AFE_DL35_SE_SECURE_BIT_SFT 15 +#define AFE_DL35_SE_SECURE_BIT_MASK 0x1 +#define AFE_DL35_SE_SECURE_BIT_MASK_SFT (0x1 << 15) +#define AFE_DL34_SE_SECURE_BIT_SFT 14 +#define AFE_DL34_SE_SECURE_BIT_MASK 0x1 +#define AFE_DL34_SE_SECURE_BIT_MASK_SFT (0x1 << 14) +#define AFE_DL33_SE_SECURE_BIT_SFT 13 +#define AFE_DL33_SE_SECURE_BIT_MASK 0x1 +#define AFE_DL33_SE_SECURE_BIT_MASK_SFT (0x1 << 13) +#define AFE_DL32_SE_SECURE_BIT_SFT 12 +#define AFE_DL32_SE_SECURE_BIT_MASK 0x1 +#define AFE_DL32_SE_SECURE_BIT_MASK_SFT (0x1 << 12) +#define AFE_DL31_SE_SECURE_BIT_SFT 11 +#define AFE_DL31_SE_SECURE_BIT_MASK 0x1 +#define AFE_DL31_SE_SECURE_BIT_MASK_SFT (0x1 << 11) +#define AFE_DL30_SE_SECURE_BIT_SFT 10 +#define AFE_DL30_SE_SECURE_BIT_MASK 0x1 +#define AFE_DL30_SE_SECURE_BIT_MASK_SFT (0x1 << 10) +#define AFE_DL29_SE_SECURE_BIT_SFT 9 +#define AFE_DL29_SE_SECURE_BIT_MASK 0x1 +#define AFE_DL29_SE_SECURE_BIT_MASK_SFT (0x1 << 9) +#define AFE_DL28_SE_SECURE_BIT_SFT 8 +#define AFE_DL28_SE_SECURE_BIT_MASK 0x1 +#define AFE_DL28_SE_SECURE_BIT_MASK_SFT (0x1 << 8) +#define AFE_DL27_SE_SECURE_BIT_SFT 7 +#define AFE_DL27_SE_SECURE_BIT_MASK 0x1 +#define AFE_DL27_SE_SECURE_BIT_MASK_SFT (0x1 << 7) +#define AFE_DL26_SE_SECURE_BIT_SFT 6 +#define AFE_DL26_SE_SECURE_BIT_MASK 0x1 +#define AFE_DL26_SE_SECURE_BIT_MASK_SFT (0x1 << 6) +#define AFE_DL25_SE_SECURE_BIT_SFT 5 +#define AFE_DL25_SE_SECURE_BIT_MASK 0x1 +#define AFE_DL25_SE_SECURE_BIT_MASK_SFT (0x1 << 5) +#define AFE_DL24_SE_SECURE_BIT_SFT 4 +#define AFE_DL24_SE_SECURE_BIT_MASK 0x1 +#define AFE_DL24_SE_SECURE_BIT_MASK_SFT (0x1 << 4) +#define AFE_DL23_SE_SECURE_BIT_SFT 3 +#define AFE_DL23_SE_SECURE_BIT_MASK 0x1 +#define AFE_DL23_SE_SECURE_BIT_MASK_SFT (0x1 << 3) +#define AFE_DL_48CH_SE_SECURE_BIT_SFT 2 +#define AFE_DL_48CH_SE_SECURE_BIT_MASK 0x1 +#define AFE_DL_48CH_SE_SECURE_BIT_MASK_SFT (0x1 << 2) +#define AFE_DL_24CH_SE_SECURE_BIT_SFT 1 +#define AFE_DL_24CH_SE_SECURE_BIT_MASK 0x1 +#define AFE_DL_24CH_SE_SECURE_BIT_MASK_SFT (0x1 << 1) +#define AFE_DL_4CH_SE_SECURE_BIT_SFT 0 +#define AFE_DL_4CH_SE_SECURE_BIT_MASK 0x1 +#define AFE_DL_4CH_SE_SECURE_BIT_MASK_SFT (0x1 << 0) + +/* AFE_SE_SECURE_CON2 */ +#define AFE_VUL38_SE_SECURE_BIT_SFT 28 +#define AFE_VUL38_SE_SECURE_BIT_MASK 0x1 +#define AFE_VUL38_SE_SECURE_BIT_MASK_SFT (0x1 << 28) +#define AFE_VUL37_SE_SECURE_BIT_SFT 27 +#define AFE_VUL37_SE_SECURE_BIT_MASK 0x1 +#define AFE_VUL37_SE_SECURE_BIT_MASK_SFT (0x1 << 27) +#define AFE_VUL36_SE_SECURE_BIT_SFT 26 +#define AFE_VUL36_SE_SECURE_BIT_MASK 0x1 +#define AFE_VUL36_SE_SECURE_BIT_MASK_SFT (0x1 << 26) +#define AFE_VUL35_SE_SECURE_BIT_SFT 25 +#define AFE_VUL35_SE_SECURE_BIT_MASK 0x1 +#define AFE_VUL35_SE_SECURE_BIT_MASK_SFT (0x1 << 25) +#define AFE_VUL34_SE_SECURE_BIT_SFT 24 +#define AFE_VUL34_SE_SECURE_BIT_MASK 0x1 +#define AFE_VUL34_SE_SECURE_BIT_MASK_SFT (0x1 << 24) +#define AFE_VUL33_SE_SECURE_BIT_SFT 23 +#define AFE_VUL33_SE_SECURE_BIT_MASK 0x1 +#define AFE_VUL33_SE_SECURE_BIT_MASK_SFT (0x1 << 23) +#define AFE_VUL32_SE_SECURE_BIT_SFT 22 +#define AFE_VUL32_SE_SECURE_BIT_MASK 0x1 +#define AFE_VUL32_SE_SECURE_BIT_MASK_SFT (0x1 << 22) +#define AFE_VUL31_SE_SECURE_BIT_SFT 21 +#define AFE_VUL31_SE_SECURE_BIT_MASK 0x1 +#define AFE_VUL31_SE_SECURE_BIT_MASK_SFT (0x1 << 21) +#define AFE_VUL30_SE_SECURE_BIT_SFT 20 +#define AFE_VUL30_SE_SECURE_BIT_MASK 0x1 +#define AFE_VUL30_SE_SECURE_BIT_MASK_SFT (0x1 << 20) +#define AFE_VUL29_SE_SECURE_BIT_SFT 19 +#define AFE_VUL29_SE_SECURE_BIT_MASK 0x1 +#define AFE_VUL29_SE_SECURE_BIT_MASK_SFT (0x1 << 19) +#define AFE_VUL28_SE_SECURE_BIT_SFT 18 +#define AFE_VUL28_SE_SECURE_BIT_MASK 0x1 +#define AFE_VUL28_SE_SECURE_BIT_MASK_SFT (0x1 << 18) +#define AFE_VUL27_SE_SECURE_BIT_SFT 17 +#define AFE_VUL27_SE_SECURE_BIT_MASK 0x1 +#define AFE_VUL27_SE_SECURE_BIT_MASK_SFT (0x1 << 17) +#define AFE_VUL26_SE_SECURE_BIT_SFT 16 +#define AFE_VUL26_SE_SECURE_BIT_MASK 0x1 +#define AFE_VUL26_SE_SECURE_BIT_MASK_SFT (0x1 << 16) +#define AFE_VUL25_SE_SECURE_BIT_SFT 15 +#define AFE_VUL25_SE_SECURE_BIT_MASK 0x1 +#define AFE_VUL25_SE_SECURE_BIT_MASK_SFT (0x1 << 15) +#define AFE_VUL24_SE_SECURE_BIT_SFT 14 +#define AFE_VUL24_SE_SECURE_BIT_MASK 0x1 +#define AFE_VUL24_SE_SECURE_BIT_MASK_SFT (0x1 << 14) +#define AFE_VUL_CM2_SE_SECURE_BIT_SFT 13 +#define AFE_VUL_CM2_SE_SECURE_BIT_MASK 0x1 +#define AFE_VUL_CM2_SE_SECURE_BIT_MASK_SFT (0x1 << 13) +#define AFE_VUL_CM1_SE_SECURE_BIT_SFT 12 +#define AFE_VUL_CM1_SE_SECURE_BIT_MASK 0x1 +#define AFE_VUL_CM1_SE_SECURE_BIT_MASK_SFT (0x1 << 12) +#define AFE_VUL_CM0_SE_SECURE_BIT_SFT 11 +#define AFE_VUL_CM0_SE_SECURE_BIT_MASK 0x1 +#define AFE_VUL_CM0_SE_SECURE_BIT_MASK_SFT (0x1 << 11) +#define AFE_VUL10_SE_SECURE_BIT_SFT 10 +#define AFE_VUL10_SE_SECURE_BIT_MASK 0x1 +#define AFE_VUL10_SE_SECURE_BIT_MASK_SFT (0x1 << 10) +#define AFE_VUL9_SE_SECURE_BIT_SFT 9 +#define AFE_VUL9_SE_SECURE_BIT_MASK 0x1 +#define AFE_VUL9_SE_SECURE_BIT_MASK_SFT (0x1 << 9) +#define AFE_VUL8_SE_SECURE_BIT_SFT 8 +#define AFE_VUL8_SE_SECURE_BIT_MASK 0x1 +#define AFE_VUL8_SE_SECURE_BIT_MASK_SFT (0x1 << 8) +#define AFE_VUL7_SE_SECURE_BIT_SFT 7 +#define AFE_VUL7_SE_SECURE_BIT_MASK 0x1 +#define AFE_VUL7_SE_SECURE_BIT_MASK_SFT (0x1 << 7) +#define AFE_VUL6_SE_SECURE_BIT_SFT 6 +#define AFE_VUL6_SE_SECURE_BIT_MASK 0x1 +#define AFE_VUL6_SE_SECURE_BIT_MASK_SFT (0x1 << 6) +#define AFE_VUL5_SE_SECURE_BIT_SFT 5 +#define AFE_VUL5_SE_SECURE_BIT_MASK 0x1 +#define AFE_VUL5_SE_SECURE_BIT_MASK_SFT (0x1 << 5) +#define AFE_VUL4_SE_SECURE_BIT_SFT 4 +#define AFE_VUL4_SE_SECURE_BIT_MASK 0x1 +#define AFE_VUL4_SE_SECURE_BIT_MASK_SFT (0x1 << 4) +#define AFE_VUL3_SE_SECURE_BIT_SFT 3 +#define AFE_VUL3_SE_SECURE_BIT_MASK 0x1 +#define AFE_VUL3_SE_SECURE_BIT_MASK_SFT (0x1 << 3) +#define AFE_VUL2_SE_SECURE_BIT_SFT 2 +#define AFE_VUL2_SE_SECURE_BIT_MASK 0x1 +#define AFE_VUL2_SE_SECURE_BIT_MASK_SFT (0x1 << 2) +#define AFE_VUL1_SE_SECURE_BIT_SFT 1 +#define AFE_VUL1_SE_SECURE_BIT_MASK 0x1 +#define AFE_VUL1_SE_SECURE_BIT_MASK_SFT (0x1 << 1) +#define AFE_VUL0_SE_SECURE_BIT_SFT 0 +#define AFE_VUL0_SE_SECURE_BIT_MASK 0x1 +#define AFE_VUL0_SE_SECURE_BIT_MASK_SFT (0x1 << 0) + +/* AFE_SE_SECURE_CON3 */ +#define AFE_SPDIFIN_SE_SECURE_BIT_SFT 10 +#define AFE_SPDIFIN_SE_SECURE_BIT_MASK 0x1 +#define AFE_SPDIFIN_SE_SECURE_BIT_MASK_SFT (0x1 << 10) +#define AFE_TDM_IN_SE_SECURE_BIT_SFT 9 +#define AFE_TDM_IN_SE_SECURE_BIT_MASK 0x1 +#define AFE_TDM_IN_SE_SECURE_BIT_MASK_SFT (0x1 << 9) +#define AFE_MPHONE_EARC_SE_SECURE_BIT_SFT 8 +#define AFE_MPHONE_EARC_SE_SECURE_BIT_MASK 0x1 +#define AFE_MPHONE_EARC_SE_SECURE_BIT_MASK_SFT (0x1 << 8) +#define AFE_MPHONE_SPDIF_SE_SECURE_BIT_SFT 7 +#define AFE_MPHONE_SPDIF_SE_SECURE_BIT_MASK 0x1 +#define AFE_MPHONE_SPDIF_SE_SECURE_BIT_MASK_SFT (0x1 << 7) +#define AFE_ETDM_IN6_SE_SECURE_BIT_SFT 6 +#define AFE_ETDM_IN6_SE_SECURE_BIT_MASK 0x1 +#define AFE_ETDM_IN6_SE_SECURE_BIT_MASK_SFT (0x1 << 6) +#define AFE_ETDM_IN5_SE_SECURE_BIT_SFT 5 +#define AFE_ETDM_IN5_SE_SECURE_BIT_MASK 0x1 +#define AFE_ETDM_IN5_SE_SECURE_BIT_MASK_SFT (0x1 << 5) +#define AFE_ETDM_IN4_SE_SECURE_BIT_SFT 4 +#define AFE_ETDM_IN4_SE_SECURE_BIT_MASK 0x1 +#define AFE_ETDM_IN4_SE_SECURE_BIT_MASK_SFT (0x1 << 4) +#define AFE_ETDM_IN3_SE_SECURE_BIT_SFT 3 +#define AFE_ETDM_IN3_SE_SECURE_BIT_MASK 0x1 +#define AFE_ETDM_IN3_SE_SECURE_BIT_MASK_SFT (0x1 << 3) +#define AFE_ETDM_IN2_SE_SECURE_BIT_SFT 2 +#define AFE_ETDM_IN2_SE_SECURE_BIT_MASK 0x1 +#define AFE_ETDM_IN2_SE_SECURE_BIT_MASK_SFT (0x1 << 2) +#define AFE_ETDM_IN1_SE_SECURE_BIT_SFT 1 +#define AFE_ETDM_IN1_SE_SECURE_BIT_MASK 0x1 +#define AFE_ETDM_IN1_SE_SECURE_BIT_MASK_SFT (0x1 << 1) +#define AFE_ETDM_IN0_SE_SECURE_BIT_SFT 0 +#define AFE_ETDM_IN0_SE_SECURE_BIT_MASK 0x1 +#define AFE_ETDM_IN0_SE_SECURE_BIT_MASK_SFT (0x1 << 0) + +/* AFE_SE_PROT_SIDEBAND0 */ +#define HDMI_HPROT_SFT 11 +#define HDMI_HPROT_MASK 0x1 +#define HDMI_HPROT_MASK_SFT (0x1 << 11) +#define SPDIF2_OUT_HPROT_SFT 10 +#define SPDIF2_OUT_HPROT_MASK 0x1 +#define SPDIF2_OUT_HPROT_MASK_SFT (0x1 << 10) +#define SPDIF_OUT_HPROT_SFT 9 +#define SPDIF_OUT_HPROT_MASK 0x1 +#define SPDIF_OUT_HPROT_MASK_SFT (0x1 << 9) +#define DL8_HPROT_SFT 8 +#define DL8_HPROT_MASK 0x1 +#define DL8_HPROT_MASK_SFT (0x1 << 8) +#define DL7_HPROT_SFT 7 +#define DL7_HPROT_MASK 0x1 +#define DL7_HPROT_MASK_SFT (0x1 << 7) +#define DL6_HPROT_SFT 6 +#define DL6_HPROT_MASK 0x1 +#define DL6_HPROT_MASK_SFT (0x1 << 6) +#define DL5_HPROT_SFT 5 +#define DL5_HPROT_MASK 0x1 +#define DL5_HPROT_MASK_SFT (0x1 << 5) +#define DL4_HPROT_SFT 4 +#define DL4_HPROT_MASK 0x1 +#define DL4_HPROT_MASK_SFT (0x1 << 4) +#define DL3_HPROT_SFT 3 +#define DL3_HPROT_MASK 0x1 +#define DL3_HPROT_MASK_SFT (0x1 << 3) +#define DL2_HPROT_SFT 2 +#define DL2_HPROT_MASK 0x1 +#define DL2_HPROT_MASK_SFT (0x1 << 2) +#define DL1_HPROT_SFT 1 +#define DL1_HPROT_MASK 0x1 +#define DL1_HPROT_MASK_SFT (0x1 << 1) +#define DL0_HPROT_SFT 0 +#define DL0_HPROT_MASK 0x1 +#define DL0_HPROT_MASK_SFT (0x1 << 0) + +/* AFE_SE_PROT_SIDEBAND1 */ +#define DL46_HPROT_SFT 26 +#define DL46_HPROT_MASK 0x1 +#define DL46_HPROT_MASK_SFT (0x1 << 26) +#define DL45_HPROT_SFT 25 +#define DL45_HPROT_MASK 0x1 +#define DL45_HPROT_MASK_SFT (0x1 << 25) +#define DL44_HPROT_SFT 24 +#define DL44_HPROT_MASK 0x1 +#define DL44_HPROT_MASK_SFT (0x1 << 24) +#define DL43_HPROT_SFT 23 +#define DL43_HPROT_MASK 0x1 +#define DL43_HPROT_MASK_SFT (0x1 << 23) +#define DL42_HPROT_SFT 22 +#define DL42_HPROT_MASK 0x1 +#define DL42_HPROT_MASK_SFT (0x1 << 22) +#define DL41_HPROT_SFT 21 +#define DL41_HPROT_MASK 0x1 +#define DL41_HPROT_MASK_SFT (0x1 << 21) +#define DL40_HPROT_SFT 20 +#define DL40_HPROT_MASK 0x1 +#define DL40_HPROT_MASK_SFT (0x1 << 20) +#define DL39_HPROT_SFT 19 +#define DL39_HPROT_MASK 0x1 +#define DL39_HPROT_MASK_SFT (0x1 << 19) +#define DL38_HPROT_SFT 18 +#define DL38_HPROT_MASK 0x1 +#define DL38_HPROT_MASK_SFT (0x1 << 18) +#define DL37_HPROT_SFT 17 +#define DL37_HPROT_MASK 0x1 +#define DL37_HPROT_MASK_SFT (0x1 << 17) +#define DL36_HPROT_SFT 16 +#define DL36_HPROT_MASK 0x1 +#define DL36_HPROT_MASK_SFT (0x1 << 16) +#define DL35_HPROT_SFT 15 +#define DL35_HPROT_MASK 0x1 +#define DL35_HPROT_MASK_SFT (0x1 << 15) +#define DL34_HPROT_SFT 14 +#define DL34_HPROT_MASK 0x1 +#define DL34_HPROT_MASK_SFT (0x1 << 14) +#define DL33_HPROT_SFT 13 +#define DL33_HPROT_MASK 0x1 +#define DL33_HPROT_MASK_SFT (0x1 << 13) +#define DL32_HPROT_SFT 12 +#define DL32_HPROT_MASK 0x1 +#define DL32_HPROT_MASK_SFT (0x1 << 12) +#define DL31_HPROT_SFT 11 +#define DL31_HPROT_MASK 0x1 +#define DL31_HPROT_MASK_SFT (0x1 << 11) +#define DL30_HPROT_SFT 10 +#define DL30_HPROT_MASK 0x1 +#define DL30_HPROT_MASK_SFT (0x1 << 10) +#define DL29_HPROT_SFT 9 +#define DL29_HPROT_MASK 0x1 +#define DL29_HPROT_MASK_SFT (0x1 << 9) +#define DL28_HPROT_SFT 8 +#define DL28_HPROT_MASK 0x1 +#define DL28_HPROT_MASK_SFT (0x1 << 8) +#define DL27_HPROT_SFT 7 +#define DL27_HPROT_MASK 0x1 +#define DL27_HPROT_MASK_SFT (0x1 << 7) +#define DL26_HPROT_SFT 6 +#define DL26_HPROT_MASK 0x1 +#define DL26_HPROT_MASK_SFT (0x1 << 6) +#define DL25_HPROT_SFT 5 +#define DL25_HPROT_MASK 0x1 +#define DL25_HPROT_MASK_SFT (0x1 << 5) +#define DL24_HPROT_SFT 4 +#define DL24_HPROT_MASK 0x1 +#define DL24_HPROT_MASK_SFT (0x1 << 4) +#define DL23_HPROT_SFT 3 +#define DL23_HPROT_MASK 0x1 +#define DL23_HPROT_MASK_SFT (0x1 << 3) +#define DL_48CH_PROT_SFT 2 +#define DL_48CH_PROT_MASK 0x1 +#define DL_48CH_PROT_MASK_SFT (0x1 << 2) +#define DL_24CH_PROT_SFT 1 +#define DL_24CH_PROT_MASK 0x1 +#define DL_24CH_PROT_MASK_SFT (0x1 << 1) +#define DL_4CH_PROT_SFT 0 +#define DL_4CH_PROT_MASK 0x1 +#define DL_4CH_PROT_MASK_SFT (0x1 << 0) + +/* AFE_SE_PROT_SIDEBAND2 */ +#define VUL38_HPROT_SFT 28 +#define VUL38_HPROT_MASK 0x1 +#define VUL38_HPROT_MASK_SFT (0x1 << 28) +#define VUL37_HPROT_SFT 27 +#define VUL37_HPROT_MASK 0x1 +#define VUL37_HPROT_MASK_SFT (0x1 << 27) +#define VUL36_HPROT_SFT 26 +#define VUL36_HPROT_MASK 0x1 +#define VUL36_HPROT_MASK_SFT (0x1 << 26) +#define VUL35_HPROT_SFT 25 +#define VUL35_HPROT_MASK 0x1 +#define VUL35_HPROT_MASK_SFT (0x1 << 25) +#define VUL34_HPROT_SFT 24 +#define VUL34_HPROT_MASK 0x1 +#define VUL34_HPROT_MASK_SFT (0x1 << 24) +#define VUL33_HPROT_SFT 23 +#define VUL33_HPROT_MASK 0x1 +#define VUL33_HPROT_MASK_SFT (0x1 << 23) +#define VUL32_HPROT_SFT 22 +#define VUL32_HPROT_MASK 0x1 +#define VUL32_HPROT_MASK_SFT (0x1 << 22) +#define VUL31_HPROT_SFT 21 +#define VUL31_HPROT_MASK 0x1 +#define VUL31_HPROT_MASK_SFT (0x1 << 21) +#define VUL30_HPROT_SFT 20 +#define VUL30_HPROT_MASK 0x1 +#define VUL30_HPROT_MASK_SFT (0x1 << 20) +#define VUL29_HPROT_SFT 19 +#define VUL29_HPROT_MASK 0x1 +#define VUL29_HPROT_MASK_SFT (0x1 << 19) +#define VUL28_HPROT_SFT 18 +#define VUL28_HPROT_MASK 0x1 +#define VUL28_HPROT_MASK_SFT (0x1 << 18) +#define VUL27_HPROT_SFT 17 +#define VUL27_HPROT_MASK 0x1 +#define VUL27_HPROT_MASK_SFT (0x1 << 17) +#define VUL26_HPROT_SFT 16 +#define VUL26_HPROT_MASK 0x1 +#define VUL26_HPROT_MASK_SFT (0x1 << 16) +#define VUL25_HPROT_SFT 15 +#define VUL25_HPROT_MASK 0x1 +#define VUL25_HPROT_MASK_SFT (0x1 << 15) +#define VUL24_HPROT_SFT 14 +#define VUL24_HPROT_MASK 0x1 +#define VUL24_HPROT_MASK_SFT (0x1 << 14) +#define VUL_CM2_HPROT_SFT 13 +#define VUL_CM2_HPROT_MASK 0x1 +#define VUL_CM2_HPROT_MASK_SFT (0x1 << 13) +#define VUL_CM1_HPROT_SFT 12 +#define VUL_CM1_HPROT_MASK 0x1 +#define VUL_CM1_HPROT_MASK_SFT (0x1 << 12) +#define VUL_CM0_HPROT_SFT 11 +#define VUL_CM0_HPROT_MASK 0x1 +#define VUL_CM0_HPROT_MASK_SFT (0x1 << 11) +#define VUL10_HPROT_SFT 10 +#define VUL10_HPROT_MASK 0x1 +#define VUL10_HPROT_MASK_SFT (0x1 << 10) +#define VUL9_HPROT_SFT 9 +#define VUL9_HPROT_MASK 0x1 +#define VUL9_HPROT_MASK_SFT (0x1 << 9) +#define VUL8_HPROT_SFT 8 +#define VUL8_HPROT_MASK 0x1 +#define VUL8_HPROT_MASK_SFT (0x1 << 8) +#define VUL7_HPROT_SFT 7 +#define VUL7_HPROT_MASK 0x1 +#define VUL7_HPROT_MASK_SFT (0x1 << 7) +#define VUL6_HPROT_SFT 6 +#define VUL6_HPROT_MASK 0x1 +#define VUL6_HPROT_MASK_SFT (0x1 << 6) +#define VUL5_HPROT_SFT 5 +#define VUL5_HPROT_MASK 0x1 +#define VUL5_HPROT_MASK_SFT (0x1 << 5) +#define VUL4_HPROT_SFT 4 +#define VUL4_HPROT_MASK 0x1 +#define VUL4_HPROT_MASK_SFT (0x1 << 4) +#define VUL3_HPROT_SFT 3 +#define VUL3_HPROT_MASK 0x1 +#define VUL3_HPROT_MASK_SFT (0x1 << 3) +#define VUL2_HPROT_SFT 2 +#define VUL2_HPROT_MASK 0x1 +#define VUL2_HPROT_MASK_SFT (0x1 << 2) +#define VUL1_HPROT_SFT 1 +#define VUL1_HPROT_MASK 0x1 +#define VUL1_HPROT_MASK_SFT (0x1 << 1) +#define VUL0_HPROT_SFT 0 +#define VUL0_HPROT_MASK 0x1 +#define VUL0_HPROT_MASK_SFT (0x1 << 0) + +/* AFE_SE_PROT_SIDEBAND3 */ +#define MPHONE_EARC_HPROT_SFT 10 +#define MPHONE_EARC_HPROT_MASK 0x1 +#define MPHONE_EARC_HPROT_MASK_SFT (0x1 << 10) +#define MPHONE_SPDIF_HPROT_SFT 9 +#define MPHONE_SPDIF_HPROT_MASK 0x1 +#define MPHONE_SPDIF_HPROT_MASK_SFT (0x1 << 9) +#define SPDIFIN_HPROT_SFT 8 +#define SPDIFIN_HPROT_MASK 0x1 +#define SPDIFIN_HPROT_MASK_SFT (0x1 << 8) +#define TDMIN_HPROT_SFT 7 +#define TDMIN_HPROT_MASK 0x1 +#define TDMIN_HPROT_MASK_SFT (0x1 << 7) +#define ETDM_IN6_HPROT_SFT 6 +#define ETDM_IN6_HPROT_MASK 0x1 +#define ETDM_IN6_HPROT_MASK_SFT (0x1 << 6) +#define ETDM_IN5_HPROT_SFT 5 +#define ETDM_IN5_HPROT_MASK 0x1 +#define ETDM_IN5_HPROT_MASK_SFT (0x1 << 5) +#define ETDM_IN4_HPROT_SFT 4 +#define ETDM_IN4_HPROT_MASK 0x1 +#define ETDM_IN4_HPROT_MASK_SFT (0x1 << 4) +#define ETDM_IN3_HPROT_SFT 3 +#define ETDM_IN3_HPROT_MASK 0x1 +#define ETDM_IN3_HPROT_MASK_SFT (0x1 << 3) +#define ETDM_IN2_HPROT_SFT 2 +#define ETDM_IN2_HPROT_MASK 0x1 +#define ETDM_IN2_HPROT_MASK_SFT (0x1 << 2) +#define ETDM_IN1_HPROT_SFT 1 +#define ETDM_IN1_HPROT_MASK 0x1 +#define ETDM_IN1_HPROT_MASK_SFT (0x1 << 1) +#define ETDM_IN0_HPROT_SFT 0 +#define ETDM_IN0_HPROT_MASK 0x1 +#define ETDM_IN0_HPROT_MASK_SFT (0x1 << 0) + +/* AFE_SE_DOMAIN_SIDEBAND0 */ +#define DL7_HDOMAIN_SFT 28 +#define DL7_HDOMAIN_MASK 0xf +#define DL7_HDOMAIN_MASK_SFT (0xf << 28) +#define DL6_HDOMAIN_SFT 24 +#define DL6_HDOMAIN_MASK 0xf +#define DL6_HDOMAIN_MASK_SFT (0xf << 24) +#define DL5_HDOMAIN_SFT 20 +#define DL5_HDOMAIN_MASK 0xf +#define DL5_HDOMAIN_MASK_SFT (0xf << 20) +#define DL4_HDOMAIN_SFT 16 +#define DL4_HDOMAIN_MASK 0xf +#define DL4_HDOMAIN_MASK_SFT (0xf << 16) +#define DL3_HDOMAIN_SFT 12 +#define DL3_HDOMAIN_MASK 0xf +#define DL3_HDOMAIN_MASK_SFT (0xf << 12) +#define DL2_HDOMAIN_SFT 8 +#define DL2_HDOMAIN_MASK 0xf +#define DL2_HDOMAIN_MASK_SFT (0xf << 8) +#define DL1_HDOMAIN_SFT 4 +#define DL1_HDOMAIN_MASK 0xf +#define DL1_HDOMAIN_MASK_SFT (0xf << 4) +#define DL0_HDOMAIN_SFT 0 +#define DL0_HDOMAIN_MASK 0xf +#define DL0_HDOMAIN_MASK_SFT (0xf << 0) + +/* AFE_SE_DOMAIN_SIDEBAND1 */ +#define DL_48CH_HDOMAIN_SFT 24 +#define DL_48CH_HDOMAIN_MASK 0xf +#define DL_48CH_HDOMAIN_MASK_SFT (0xf << 24) +#define DL_24CH_HDOMAIN_SFT 20 +#define DL_24CH_HDOMAIN_MASK 0xf +#define DL_24CH_HDOMAIN_MASK_SFT (0xf << 20) +#define DL_4CH_HDOMAIN_SFT 16 +#define DL_4CH_HDOMAIN_MASK 0xf +#define DL_4CH_HDOMAIN_MASK_SFT (0xf << 16) +#define HDMI_HDOMAIN_SFT 12 +#define HDMI_HDOMAIN_MASK 0xf +#define HDMI_HDOMAIN_MASK_SFT (0xf << 12) +#define SPDIF2_OUT_HDOMAIN_SFT 8 +#define SPDIF2_OUT_HDOMAIN_MASK 0xf +#define SPDIF2_OUT_HDOMAIN_MASK_SFT (0xf << 8) +#define SPDIF_OUT_HDOMAIN_SFT 4 +#define SPDIF_OUT_HDOMAIN_MASK 0xf +#define SPDIF_OUT_HDOMAIN_MASK_SFT (0xf << 4) +#define DL8_HDOMAIN_SFT 0 +#define DL8_HDOMAIN_MASK 0xf +#define DL8_HDOMAIN_MASK_SFT (0xf << 0) + +/* AFE_SE_DOMAIN_SIDEBAND2 */ +#define DL30_HDOMAIN_SFT 28 +#define DL30_HDOMAIN_MASK 0xf +#define DL30_HDOMAIN_MASK_SFT (0xf << 28) +#define DL29_HDOMAIN_SFT 24 +#define DL29_HDOMAIN_MASK 0xf +#define DL29_HDOMAIN_MASK_SFT (0xf << 24) +#define DL28_HDOMAIN_SFT 20 +#define DL28_HDOMAIN_MASK 0xf +#define DL28_HDOMAIN_MASK_SFT (0xf << 20) +#define DL27_HDOMAIN_SFT 16 +#define DL27_HDOMAIN_MASK 0xf +#define DL27_HDOMAIN_MASK_SFT (0xf << 16) +#define DL26_HDOMAIN_SFT 12 +#define DL26_HDOMAIN_MASK 0xf +#define DL26_HDOMAIN_MASK_SFT (0xf << 12) +#define DL25_HDOMAIN_SFT 8 +#define DL25_HDOMAIN_MASK 0xf +#define DL25_HDOMAIN_MASK_SFT (0xf << 8) +#define DL24_HDOMAIN_SFT 4 +#define DL24_HDOMAIN_MASK 0xf +#define DL24_HDOMAIN_MASK_SFT (0xf << 4) +#define DL23_HDOMAIN_SFT 0 +#define DL23_HDOMAIN_MASK 0xf +#define DL23_HDOMAIN_MASK_SFT (0xf << 0) + +/* AFE_SE_DOMAIN_SIDEBAND3 */ +#define DL38_HDOMAIN_SFT 28 +#define DL38_HDOMAIN_MASK 0xf +#define DL38_HDOMAIN_MASK_SFT (0xf << 28) +#define DL37_HDOMAIN_SFT 24 +#define DL37_HDOMAIN_MASK 0xf +#define DL37_HDOMAIN_MASK_SFT (0xf << 24) +#define DL36_HDOMAIN_SFT 20 +#define DL36_HDOMAIN_MASK 0xf +#define DL36_HDOMAIN_MASK_SFT (0xf << 20) +#define DL35_HDOMAIN_SFT 16 +#define DL35_HDOMAIN_MASK 0xf +#define DL35_HDOMAIN_MASK_SFT (0xf << 16) +#define DL34_HDOMAIN_SFT 12 +#define DL34_HDOMAIN_MASK 0xf +#define DL34_HDOMAIN_MASK_SFT (0xf << 12) +#define DL33_HDOMAIN_SFT 8 +#define DL33_HDOMAIN_MASK 0xf +#define DL33_HDOMAIN_MASK_SFT (0xf << 8) +#define DL32_HDOMAIN_SFT 4 +#define DL32_HDOMAIN_MASK 0xf +#define DL32_HDOMAIN_MASK_SFT (0xf << 4) +#define DL31_HDOMAIN_SFT 0 +#define DL31_HDOMAIN_MASK 0xf +#define DL31_HDOMAIN_MASK_SFT (0xf << 0) + +/* AFE_SE_DOMAIN_SIDEBAND4 */ +#define DL46_HDOMAIN_SFT 28 +#define DL46_HDOMAIN_MASK 0xf +#define DL46_HDOMAIN_MASK_SFT (0xf << 28) +#define DL45_HDOMAIN_SFT 24 +#define DL45_HDOMAIN_MASK 0xf +#define DL45_HDOMAIN_MASK_SFT (0xf << 24) +#define DL44_HDOMAIN_SFT 20 +#define DL44_HDOMAIN_MASK 0xf +#define DL44_HDOMAIN_MASK_SFT (0xf << 20) +#define DL43_HDOMAIN_SFT 16 +#define DL43_HDOMAIN_MASK 0xf +#define DL43_HDOMAIN_MASK_SFT (0xf << 16) +#define DL42_HDOMAIN_SFT 12 +#define DL42_HDOMAIN_MASK 0xf +#define DL42_HDOMAIN_MASK_SFT (0xf << 12) +#define DL41_HDOMAIN_SFT 8 +#define DL41_HDOMAIN_MASK 0xf +#define DL41_HDOMAIN_MASK_SFT (0xf << 8) +#define DL40_HDOMAIN_SFT 4 +#define DL40_HDOMAIN_MASK 0xf +#define DL40_HDOMAIN_MASK_SFT (0xf << 4) +#define DL39_HDOMAIN_SFT 0 +#define DL39_HDOMAIN_MASK 0xf +#define DL39_HDOMAIN_MASK_SFT (0xf << 0) + +/* AFE_SE_DOMAIN_SIDEBAND5 */ +#define VUL7_HDOMAIN_SFT 28 +#define VUL7_HDOMAIN_MASK 0xf +#define VUL7_HDOMAIN_MASK_SFT (0xf << 28) +#define VUL6_HDOMAIN_SFT 24 +#define VUL6_HDOMAIN_MASK 0xf +#define VUL6_HDOMAIN_MASK_SFT (0xf << 24) +#define VUL5_HDOMAIN_SFT 20 +#define VUL5_HDOMAIN_MASK 0xf +#define VUL5_HDOMAIN_MASK_SFT (0xf << 20) +#define VUL4_HDOMAIN_SFT 16 +#define VUL4_HDOMAIN_MASK 0xf +#define VUL4_HDOMAIN_MASK_SFT (0xf << 16) +#define VUL3_HDOMAIN_SFT 12 +#define VUL3_HDOMAIN_MASK 0xf +#define VUL3_HDOMAIN_MASK_SFT (0xf << 12) +#define VUL2_HDOMAIN_SFT 8 +#define VUL2_HDOMAIN_MASK 0xf +#define VUL2_HDOMAIN_MASK_SFT (0xf << 8) +#define VUL1_HDOMAIN_SFT 4 +#define VUL1_HDOMAIN_MASK 0xf +#define VUL1_HDOMAIN_MASK_SFT (0xf << 4) +#define VUL0_HDOMAIN_SFT 0 +#define VUL0_HDOMAIN_MASK 0xf +#define VUL0_HDOMAIN_MASK_SFT (0xf << 0) + +/* AFE_SE_DOMAIN_SIDEBAND6 */ +#define VU25_HDOMAIN_SFT 28 +#define VU25_HDOMAIN_MASK 0xf +#define VU25_HDOMAIN_MASK_SFT (0xf << 28) +#define VUL24_HDOMAIN_SFT 24 +#define VUL24_HDOMAIN_MASK 0xf +#define VUL24_HDOMAIN_MASK_SFT (0xf << 24) +#define VUL_CM2_HDOMAIN_SFT 20 +#define VUL_CM2_HDOMAIN_MASK 0xf +#define VUL_CM2_HDOMAIN_MASK_SFT (0xf << 20) +#define VUL_CM1_HDOMAIN_SFT 16 +#define VUL_CM1_HDOMAIN_MASK 0xf +#define VUL_CM1_HDOMAIN_MASK_SFT (0xf << 16) +#define VUL_CM0_HDOMAIN_SFT 12 +#define VUL_CM0_HDOMAIN_MASK 0xf +#define VUL_CM0_HDOMAIN_MASK_SFT (0xf << 12) +#define VUL10_HDOMAIN_SFT 8 +#define VUL10_HDOMAIN_MASK 0xf +#define VUL10_HDOMAIN_MASK_SFT (0xf << 8) +#define VUL9_HDOMAIN_SFT 4 +#define VUL9_HDOMAIN_MASK 0xf +#define VUL9_HDOMAIN_MASK_SFT (0xf << 4) +#define VUL8_HDOMAIN_SFT 0 +#define VUL8_HDOMAIN_MASK 0xf +#define VUL8_HDOMAIN_MASK_SFT (0xf << 0) + +/* AFE_SE_DOMAIN_SIDEBAND7 */ +#define VUL33_HDOMAIN_SFT 28 +#define VUL33_HDOMAIN_MASK 0xf +#define VUL33_HDOMAIN_MASK_SFT (0xf << 28) +#define VUL32_HDOMAIN_SFT 24 +#define VUL32_HDOMAIN_MASK 0xf +#define VUL32_HDOMAIN_MASK_SFT (0xf << 24) +#define VUL31_HDOMAIN_SFT 20 +#define VUL31_HDOMAIN_MASK 0xf +#define VUL31_HDOMAIN_MASK_SFT (0xf << 20) +#define VUL30_HDOMAIN_SFT 16 +#define VUL30_HDOMAIN_MASK 0xf +#define VUL30_HDOMAIN_MASK_SFT (0xf << 16) +#define VUL29_HDOMAIN_SFT 12 +#define VUL29_HDOMAIN_MASK 0xf +#define VUL29_HDOMAIN_MASK_SFT (0xf << 12) +#define VUL28_HDOMAIN_SFT 8 +#define VUL28_HDOMAIN_MASK 0xf +#define VUL28_HDOMAIN_MASK_SFT (0xf << 8) +#define VUL27_HDOMAIN_SFT 4 +#define VUL27_HDOMAIN_MASK 0xf +#define VUL27_HDOMAIN_MASK_SFT (0xf << 4) +#define VUL26_HDOMAIN_SFT 0 +#define VUL26_HDOMAIN_MASK 0xf +#define VUL26_HDOMAIN_MASK_SFT (0xf << 0) + +/* AFE_SE_DOMAIN_SIDEBAND8 */ +#define ETDM_IN2_HDOMAIN_SFT 28 +#define ETDM_IN2_HDOMAIN_MASK 0xf +#define ETDM_IN2_HDOMAIN_MASK_SFT (0xf << 28) +#define ETDM_IN1_HDOMAIN_SFT 24 +#define ETDM_IN1_HDOMAIN_MASK 0xf +#define ETDM_IN1_HDOMAIN_MASK_SFT (0xf << 24) +#define ETDM_IN0_HDOMAIN_SFT 20 +#define ETDM_IN0_HDOMAIN_MASK 0xf +#define ETDM_IN0_HDOMAIN_MASK_SFT (0xf << 20) +#define VUL38_HDOMAIN_SFT 16 +#define VUL38_HDOMAIN_MASK 0xf +#define VUL38_HDOMAIN_MASK_SFT (0xf << 16) +#define VUL37_HDOMAIN_SFT 12 +#define VUL37_HDOMAIN_MASK 0xf +#define VUL37_HDOMAIN_MASK_SFT (0xf << 12) +#define VUL36_HDOMAIN_SFT 8 +#define VUL36_HDOMAIN_MASK 0xf +#define VUL36_HDOMAIN_MASK_SFT (0xf << 8) +#define VUL35_HDOMAIN_SFT 4 +#define VUL35_HDOMAIN_MASK 0xf +#define VUL35_HDOMAIN_MASK_SFT (0xf << 4) +#define VUL34_HDOMAIN_SFT 0 +#define VUL34_HDOMAIN_MASK 0xf +#define VUL34_HDOMAIN_MASK_SFT (0xf << 0) + +/* AFE_SE_DOMAIN_SIDEBAND9 */ +#define MPHONE_EARC_HDOMAIN_SFT 28 +#define MPHONE_EARC_HDOMAIN_MASK 0xf +#define MPHONE_EARC_HDOMAIN_MASK_SFT (0xf << 28) +#define MPHONE_SPDIF_HDOMAIN_SFT 24 +#define MPHONE_SPDIF_HDOMAIN_MASK 0xf +#define MPHONE_SPDIF_HDOMAIN_MASK_SFT (0xf << 24) +#define SPDIFIN_HDOMAIN_SFT 20 +#define SPDIFIN_HDOMAIN_MASK 0xf +#define SPDIFIN_HDOMAIN_MASK_SFT (0xf << 20) +#define TDMIN_HDOMAIN_SFT 16 +#define TDMIN_HDOMAIN_MASK 0xf +#define TDMIN_HDOMAIN_MASK_SFT (0xf << 16) +#define ETDM_IN6_HDOMAIN_SFT 12 +#define ETDM_IN6_HDOMAIN_MASK 0xf +#define ETDM_IN6_HDOMAIN_MASK_SFT (0xf << 12) +#define ETDM_IN5_HDOMAIN_SFT 8 +#define ETDM_IN5_HDOMAIN_MASK 0xf +#define ETDM_IN5_HDOMAIN_MASK_SFT (0xf << 8) +#define ETDM_IN4_HDOMAIN_SFT 4 +#define ETDM_IN4_HDOMAIN_MASK 0xf +#define ETDM_IN4_HDOMAIN_MASK_SFT (0xf << 4) +#define ETDM_IN3_HDOMAIN_SFT 0 +#define ETDM_IN3_HDOMAIN_MASK 0xf +#define ETDM_IN3_HDOMAIN_MASK_SFT (0xf << 0) + +/* AFE_PROT_SIDEBAND0_MON */ +#define AFE_DOMAIN_SIDEBAN0_MON_SFT 0 +#define AFE_DOMAIN_SIDEBAN0_MON_MASK 0xffffffff +#define AFE_DOMAIN_SIDEBAN0_MON_MASK_SFT (0xffffffff << 0) + +/* AFE_PROT_SIDEBAND1_MON */ +#define AFE_DOMAIN_SIDEBAN1_MON_SFT 0 +#define AFE_DOMAIN_SIDEBAN1_MON_MASK 0xffffffff +#define AFE_DOMAIN_SIDEBAN1_MON_MASK_SFT (0xffffffff << 0) + +/* AFE_PROT_SIDEBAND2_MON */ +#define AFE_DOMAIN_SIDEBAN2_MON_SFT 0 +#define AFE_DOMAIN_SIDEBAN2_MON_MASK 0xffffffff +#define AFE_DOMAIN_SIDEBAN2_MON_MASK_SFT (0xffffffff << 0) + +/* AFE_PROT_SIDEBAND3_MON */ +#define AFE_DOMAIN_SIDEBAN3_MON_SFT 0 +#define AFE_DOMAIN_SIDEBAN3_MON_MASK 0xffffffff +#define AFE_DOMAIN_SIDEBAN3_MON_MASK_SFT (0xffffffff << 0) + +/* AFE_DOMAIN_SIDEBAND0_MON */ +#define AFE_DOMAIN_SIDEBAN0_MON_SFT 0 +#define AFE_DOMAIN_SIDEBAN0_MON_MASK 0xffffffff +#define AFE_DOMAIN_SIDEBAN0_MON_MASK_SFT (0xffffffff << 0) + +/* AFE_DOMAIN_SIDEBAND1_MON */ +#define AFE_DOMAIN_SIDEBAN1_MON_SFT 0 +#define AFE_DOMAIN_SIDEBAN1_MON_MASK 0xffffffff +#define AFE_DOMAIN_SIDEBAN1_MON_MASK_SFT (0xffffffff << 0) + +/* AFE_DOMAIN_SIDEBAND2_MON */ +#define AFE_DOMAIN_SIDEBAN2_MON_SFT 0 +#define AFE_DOMAIN_SIDEBAN2_MON_MASK 0xffffffff +#define AFE_DOMAIN_SIDEBAN2_MON_MASK_SFT (0xffffffff << 0) + +/* AFE_DOMAIN_SIDEBAND3_MON */ +#define AFE_DOMAIN_SIDEBAN3_MON_SFT 0 +#define AFE_DOMAIN_SIDEBAN3_MON_MASK 0xffffffff +#define AFE_DOMAIN_SIDEBAN3_MON_MASK_SFT (0xffffffff << 0) + +/* AFE_DOMAIN_SIDEBAND4_MON */ +#define AFE_DOMAIN_SIDEBAN0_MON_SFT 0 +#define AFE_DOMAIN_SIDEBAN0_MON_MASK 0xffffffff +#define AFE_DOMAIN_SIDEBAN0_MON_MASK_SFT (0xffffffff << 0) + +/* AFE_DOMAIN_SIDEBAND5_MON */ +#define AFE_DOMAIN_SIDEBAN1_MON_SFT 0 +#define AFE_DOMAIN_SIDEBAN1_MON_MASK 0xffffffff +#define AFE_DOMAIN_SIDEBAN1_MON_MASK_SFT (0xffffffff << 0) + +/* AFE_DOMAIN_SIDEBAND6_MON */ +#define AFE_DOMAIN_SIDEBAN2_MON_SFT 0 +#define AFE_DOMAIN_SIDEBAN2_MON_MASK 0xffffffff +#define AFE_DOMAIN_SIDEBAN2_MON_MASK_SFT (0xffffffff << 0) + +/* AFE_DOMAIN_SIDEBAND7_MON */ +#define AFE_DOMAIN_SIDEBAN3_MON_SFT 0 +#define AFE_DOMAIN_SIDEBAN3_MON_MASK 0xffffffff +#define AFE_DOMAIN_SIDEBAN3_MON_MASK_SFT (0xffffffff << 0) + +/* AFE_DOMAIN_SIDEBAND8_MON */ +#define AFE_DOMAIN_SIDEBAN2_MON_SFT 0 +#define AFE_DOMAIN_SIDEBAN2_MON_MASK 0xffffffff +#define AFE_DOMAIN_SIDEBAN2_MON_MASK_SFT (0xffffffff << 0) + +/* AFE_DOMAIN_SIDEBAND9_MON */ +#define AFE_DOMAIN_SIDEBAN3_MON_SFT 0 +#define AFE_DOMAIN_SIDEBAN3_MON_MASK 0xffffffff +#define AFE_DOMAIN_SIDEBAN3_MON_MASK_SFT (0xffffffff << 0) + +/* AFE_SECURE_CONN0 */ +#define AFE_SPDIFIN_LPBK_CON_MASK_S_SFT 26 +#define AFE_SPDIFIN_LPBK_CON_MASK_S_MASK 0x3 +#define AFE_SPDIFIN_LPBK_CON_MASK_S_MASK_SFT (0x3 << 26) +#define AFE_ADDA_DMIC1_SRC_CON0_MASK_S_SFT 25 +#define AFE_ADDA_DMIC1_SRC_CON0_MASK_S_MASK 0x1 +#define AFE_ADDA_DMIC1_SRC_CON0_MASK_S_MASK_SFT (0x1 << 25) +#define AFE_ADDA_DMIC0_SRC_CON0_MASK_S_SFT 24 +#define AFE_ADDA_DMIC0_SRC_CON0_MASK_S_MASK 0x1 +#define AFE_ADDA_DMIC0_SRC_CON0_MASK_S_MASK_SFT (0x1 << 24) +#define AFE_ADDA_UL3_SRC_CON0_MASK_S_SFT 23 +#define AFE_ADDA_UL3_SRC_CON0_MASK_S_MASK 0x1 +#define AFE_ADDA_UL3_SRC_CON0_MASK_S_MASK_SFT (0x1 << 23) +#define AFE_ADDA_UL2_SRC_CON0_MASK_S_SFT 22 +#define AFE_ADDA_UL2_SRC_CON0_MASK_S_MASK 0x1 +#define AFE_ADDA_UL2_SRC_CON0_MASK_S_MASK_SFT (0x1 << 22) +#define AFE_ADDA_UL1_SRC_CON0_MASK_S_SFT 21 +#define AFE_ADDA_UL1_SRC_CON0_MASK_S_MASK 0x1 +#define AFE_ADDA_UL1_SRC_CON0_MASK_S_MASK_SFT (0x1 << 21) +#define AFE_ADDA_UL0_SRC_CON0_MASK_S_SFT 20 +#define AFE_ADDA_UL0_SRC_CON0_MASK_S_MASK 0x1 +#define AFE_ADDA_UL0_SRC_CON0_MASK_S_MASK_SFT (0x1 << 20) +#define AFE_MRKAIF1_CFG0_MASK_S_SFT 19 +#define AFE_MRKAIF1_CFG0_MASK_S_MASK 0x1 +#define AFE_MRKAIF1_CFG0_MASK_S_MASK_SFT (0x1 << 19) +#define AFE_MRKAIF0_CFG0_MASK_S_SFT 18 +#define AFE_MRKAIF0_CFG0_MASK_S_MASK 0x1 +#define AFE_MRKAIF0_CFG0_MASK_S_MASK_SFT (0x1 << 18) +#define AFE_TDMIN_CON1_MASK_S_SFT 17 +#define AFE_TDMIN_CON1_MASK_S_MASK 0x1 +#define AFE_TDMIN_CON1_MASK_S_MASK_SFT (0x1 << 17) +#define AFE_TDM_CON2_MASK_S_SFT 16 +#define AFE_TDM_CON2_MASK_S_MASK 0x1 +#define AFE_TDM_CON2_MASK_S_MASK_SFT (0x1 << 16) +#define AFE_DAIBT_CON_MASK_S_SFT 14 +#define AFE_DAIBT_CON_MASK_S_MASK 0x3 +#define AFE_DAIBT_CON_MASK_S_MASK_SFT (0x3 << 14) +#define AFE_MRGIF_CON_MASK_S_SFT 12 +#define AFE_MRGIF_CON_MASK_S_MASK 0x3 +#define AFE_MRGIF_CON_MASK_S_MASK_SFT (0x3 << 12) +#define AFE_CONNSYS_I2S_CON_MASK_S_SFT 11 +#define AFE_CONNSYS_I2S_CON_MASK_S_MASK 0x1 +#define AFE_CONNSYS_I2S_CON_MASK_S_MASK_SFT (0x1 << 11) +#define AFE_PCM1_INFT_CON0_MASK_S_SFT 6 +#define AFE_PCM1_INFT_CON0_MASK_S_MASK 0x1f +#define AFE_PCM1_INFT_CON0_MASK_S_MASK_SFT (0x1f << 6) +#define AFE_PCM0_INTF_CON1_MASK_S_SFT 0 +#define AFE_PCM0_INTF_CON1_MASK_S_MASK 0x3f +#define AFE_PCM0_INTF_CON1_MASK_S_MASK_SFT (0x3f << 0) + +/* AFE_SECURE_CONN_ETDM0 */ +#define ETDM_0_3_COWORK_CON2_OUT3_DATA_SEL_SFT 28 +#define ETDM_0_3_COWORK_CON2_OUT3_DATA_SEL_MASK 0xf +#define ETDM_0_3_COWORK_CON2_OUT3_DATA_SEL_MASK_SFT (0xf << 28) +#define ETDM_0_3_COWORK_CON2_OUT2_DATA_SEL_SFT 24 +#define ETDM_0_3_COWORK_CON2_OUT2_DATA_SEL_MASK 0xf +#define ETDM_0_3_COWORK_CON2_OUT2_DATA_SEL_MASK_SFT (0xf << 24) +#define ETDM_0_3_COWORK_CON2_IN1_SDATA1_15_SEL_SFT 20 +#define ETDM_0_3_COWORK_CON2_IN1_SDATA1_15_SEL_MASK 0xf +#define ETDM_0_3_COWORK_CON2_IN1_SDATA1_15_SEL_MASK_SFT (0xf << 20) +#define ETDM_0_3_COWORK_CON2_IN1_SDATA0_SEL_SFT 16 +#define ETDM_0_3_COWORK_CON2_IN1_SDATA0_SEL_MASK 0xf +#define ETDM_0_3_COWORK_CON2_IN1_SDATA0_SEL_MASK_SFT (0xf << 16) +#define ETDM_0_3_COWORK_CON2_IN0_SDATA1_15_SEL_SFT 12 +#define ETDM_0_3_COWORK_CON2_IN0_SDATA1_15_SEL_MASK 0xf +#define ETDM_0_3_COWORK_CON2_IN0_SDATA1_15_SEL_MASK_SFT (0xf << 12) +#define ETDM_0_3_COWORK_CON2_IN0_SDATA0_SEL_SFT 8 +#define ETDM_0_3_COWORK_CON2_IN0_SDATA0_SEL_MASK 0xf +#define ETDM_0_3_COWORK_CON2_IN0_SDATA0_SEL_MASK_SFT (0xf << 8) +#define ETDM_0_3_COWORK_CON2_OUT1_DATA_SEL_SFT 4 +#define ETDM_0_3_COWORK_CON2_OUT1_DATA_SEL_MASK 0xf +#define ETDM_0_3_COWORK_CON2_OUT1_DATA_SEL_MASK_SFT (0xf << 4) +#define ETDM_0_3_COWORK_CON2_OUT0_DATA_SEL_SFT 0 +#define ETDM_0_3_COWORK_CON2_OUT0_DATA_SEL_MASK 0xf +#define ETDM_0_3_COWORK_CON2_OUT0_DATA_SEL_MASK_SFT (0xf << 0) + +/* AFE_SECURE_CONN_ETDM1 */ +#define ETDM_4_7_COWORK_CON1_IN4_SDATA1_15_SEL_SFT 28 +#define ETDM_4_7_COWORK_CON1_IN4_SDATA1_15_SEL_MASK 0xf +#define ETDM_4_7_COWORK_CON1_IN4_SDATA1_15_SEL_MASK_SFT (0xf << 28) +#define ETDM_4_7_COWORK_CON1_IN4_SDATA0_SEL_SFT 24 +#define ETDM_4_7_COWORK_CON1_IN4_SDATA0_SEL_MASK 0xf +#define ETDM_4_7_COWORK_CON1_IN4_SDATA0_SEL_MASK_SFT (0xf << 24) +#define ETDM_4_7_COWORK_CON1_OUT5_DATA_SEL_SFT 20 +#define ETDM_4_7_COWORK_CON1_OUT5_DATA_SEL_MASK 0xf +#define ETDM_4_7_COWORK_CON1_OUT5_DATA_SEL_MASK_SFT (0xf << 20) +#define ETDM_4_7_COWORK_CON1_OUT4_DATA_SEL_SFT 16 +#define ETDM_4_7_COWORK_CON1_OUT4_DATA_SEL_MASK 0xf +#define ETDM_4_7_COWORK_CON1_OUT4_DATA_SEL_MASK_SFT (0xf << 16) +#define ETDM_4_7_COWORK_CON1_IN3_SDATA1_15_SEL_SFT 12 +#define ETDM_4_7_COWORK_CON1_IN3_SDATA1_15_SEL_MASK 0xf +#define ETDM_4_7_COWORK_CON1_IN3_SDATA1_15_SEL_MASK_SFT (0xf << 12) +#define ETDM_4_7_COWORK_CON1_IN3_SDATA0_SEL_SFT 8 +#define ETDM_4_7_COWORK_CON1_IN3_SDATA0_SEL_MASK 0xf +#define ETDM_4_7_COWORK_CON1_IN3_SDATA0_SEL_MASK_SFT (0xf << 8) +#define ETDM_4_7_COWORK_CON1_IN2_SDATA1_15_SEL_SFT 4 +#define ETDM_4_7_COWORK_CON1_IN2_SDATA1_15_SEL_MASK 0xf +#define ETDM_4_7_COWORK_CON1_IN2_SDATA1_15_SEL_MASK_SFT (0xf << 4) +#define ETDM_4_7_COWORK_CON1_IN2_SDATA0_SEL_SFT 0 +#define ETDM_4_7_COWORK_CON1_IN2_SDATA0_SEL_MASK 0xf +#define ETDM_4_7_COWORK_CON1_IN2_SDATA0_SEL_MASK_SFT (0xf << 0) + +/* AFE_SECURE_CONN_ETDM2 */ +#define ETDM_4_7_COWORK_CON3_IN7_SDATA1_15_SEL_SFT 28 +#define ETDM_4_7_COWORK_CON3_IN7_SDATA1_15_SEL_MASK 0xf +#define ETDM_4_7_COWORK_CON3_IN7_SDATA1_15_SEL_MASK_SFT (0xf << 28) +#define ETDM_4_7_COWORK_CON3_IN7_SDATA0_SEL_SFT 24 +#define ETDM_4_7_COWORK_CON3_IN7_SDATA0_SEL_MASK 0xf +#define ETDM_4_7_COWORK_CON3_IN7_SDATA0_SEL_MASK_SFT (0xf << 24) +#define ETDM_4_7_COWORK_CON3_IN6_SDATA1_15_SEL_SFT 20 +#define ETDM_4_7_COWORK_CON3_IN6_SDATA1_15_SEL_MASK 0xf +#define ETDM_4_7_COWORK_CON3_IN6_SDATA1_15_SEL_MASK_SFT (0xf << 20) +#define ETDM_4_7_COWORK_CON3_IN6_SDATA0_SEL_SFT 16 +#define ETDM_4_7_COWORK_CON3_IN6_SDATA0_SEL_MASK 0xf +#define ETDM_4_7_COWORK_CON3_IN6_SDATA0_SEL_MASK_SFT (0xf << 16) +#define ETDM_4_7_COWORK_CON3_OUT7_DATA_SEL_SFT 12 +#define ETDM_4_7_COWORK_CON3_OUT7_DATA_SEL_MASK 0xf +#define ETDM_4_7_COWORK_CON3_OUT7_DATA_SEL_MASK_SFT (0xf << 12) +#define ETDM_4_7_COWORK_CON3_OUT6_DATA_SEL_SFT 8 +#define ETDM_4_7_COWORK_CON3_OUT6_DATA_SEL_MASK 0xf +#define ETDM_4_7_COWORK_CON3_OUT6_DATA_SEL_MASK_SFT (0xf << 8) +#define ETDM_4_7_COWORK_CON3_IN5_SDATA1_15_SEL_SFT 4 +#define ETDM_4_7_COWORK_CON3_IN5_SDATA1_15_SEL_MASK 0xf +#define ETDM_4_7_COWORK_CON3_IN5_SDATA1_15_SEL_MASK_SFT (0xf << 4) +#define ETDM_4_7_COWORK_CON3_IN5_SDATA0_SEL_SFT 0 +#define ETDM_4_7_COWORK_CON3_IN5_SDATA0_SEL_MASK 0xf +#define ETDM_4_7_COWORK_CON3_IN5_SDATA0_SEL_MASK_SFT (0xf << 0) + +/* AFE_SECURE_SRAM_CON0 */ +#define SRAM_READ_EN15_NS_SFT 31 +#define SRAM_READ_EN15_NS_MASK 0x1 +#define SRAM_READ_EN15_NS_MASK_SFT (0x1 << 31) +#define SRAM_WRITE_EN15_NS_SFT 30 +#define SRAM_WRITE_EN15_NS_MASK 0x1 +#define SRAM_WRITE_EN15_NS_MASK_SFT (0x1 << 30) +#define SRAM_READ_EN14_NS_SFT 29 +#define SRAM_READ_EN14_NS_MASK 0x1 +#define SRAM_READ_EN14_NS_MASK_SFT (0x1 << 29) +#define SRAM_WRITE_EN14_NS_SFT 28 +#define SRAM_WRITE_EN14_NS_MASK 0x1 +#define SRAM_WRITE_EN14_NS_MASK_SFT (0x1 << 28) +#define SRAM_READ_EN13_NS_SFT 27 +#define SRAM_READ_EN13_NS_MASK 0x1 +#define SRAM_READ_EN13_NS_MASK_SFT (0x1 << 27) +#define SRAM_WRITE_EN13_NS_SFT 26 +#define SRAM_WRITE_EN13_NS_MASK 0x1 +#define SRAM_WRITE_EN13_NS_MASK_SFT (0x1 << 26) +#define SRAM_READ_EN12_NS_SFT 25 +#define SRAM_READ_EN12_NS_MASK 0x1 +#define SRAM_READ_EN12_NS_MASK_SFT (0x1 << 25) +#define SRAM_WRITE_EN12_NS_SFT 24 +#define SRAM_WRITE_EN12_NS_MASK 0x1 +#define SRAM_WRITE_EN12_NS_MASK_SFT (0x1 << 24) +#define SRAM_READ_EN11_NS_SFT 23 +#define SRAM_READ_EN11_NS_MASK 0x1 +#define SRAM_READ_EN11_NS_MASK_SFT (0x1 << 23) +#define SRAM_WRITE_EN11_NS_SFT 22 +#define SRAM_WRITE_EN11_NS_MASK 0x1 +#define SRAM_WRITE_EN11_NS_MASK_SFT (0x1 << 22) +#define SRAM_READ_EN10_NS_SFT 21 +#define SRAM_READ_EN10_NS_MASK 0x1 +#define SRAM_READ_EN10_NS_MASK_SFT (0x1 << 21) +#define SRAM_WRITE_EN10_NS_SFT 20 +#define SRAM_WRITE_EN10_NS_MASK 0x1 +#define SRAM_WRITE_EN10_NS_MASK_SFT (0x1 << 20) +#define SRAM_READ_EN9_NS_SFT 19 +#define SRAM_READ_EN9_NS_MASK 0x1 +#define SRAM_READ_EN9_NS_MASK_SFT (0x1 << 19) +#define SRAM_WRITE_EN9_NS_SFT 18 +#define SRAM_WRITE_EN9_NS_MASK 0x1 +#define SRAM_WRITE_EN9_NS_MASK_SFT (0x1 << 18) +#define SRAM_READ_EN8_NS_SFT 17 +#define SRAM_READ_EN8_NS_MASK 0x1 +#define SRAM_READ_EN8_NS_MASK_SFT (0x1 << 17) +#define SRAM_WRITE_EN8_NS_SFT 16 +#define SRAM_WRITE_EN8_NS_MASK 0x1 +#define SRAM_WRITE_EN8_NS_MASK_SFT (0x1 << 16) +#define SRAM_READ_EN7_NS_SFT 15 +#define SRAM_READ_EN7_NS_MASK 0x1 +#define SRAM_READ_EN7_NS_MASK_SFT (0x1 << 15) +#define SRAM_WRITE_EN7_NS_SFT 14 +#define SRAM_WRITE_EN7_NS_MASK 0x1 +#define SRAM_WRITE_EN7_NS_MASK_SFT (0x1 << 14) +#define SRAM_READ_EN6_NS_SFT 13 +#define SRAM_READ_EN6_NS_MASK 0x1 +#define SRAM_READ_EN6_NS_MASK_SFT (0x1 << 13) +#define SRAM_WRITE_EN6_NS_SFT 12 +#define SRAM_WRITE_EN6_NS_MASK 0x1 +#define SRAM_WRITE_EN6_NS_MASK_SFT (0x1 << 12) +#define SRAM_READ_EN5_NS_SFT 11 +#define SRAM_READ_EN5_NS_MASK 0x1 +#define SRAM_READ_EN5_NS_MASK_SFT (0x1 << 11) +#define SRAM_WRITE_EN5_NS_SFT 10 +#define SRAM_WRITE_EN5_NS_MASK 0x1 +#define SRAM_WRITE_EN5_NS_MASK_SFT (0x1 << 10) +#define SRAM_READ_EN4_NS_SFT 9 +#define SRAM_READ_EN4_NS_MASK 0x1 +#define SRAM_READ_EN4_NS_MASK_SFT (0x1 << 9) +#define SRAM_WRITE_EN4_NS_SFT 8 +#define SRAM_WRITE_EN4_NS_MASK 0x1 +#define SRAM_WRITE_EN4_NS_MASK_SFT (0x1 << 8) +#define SRAM_READ_EN3_NS_SFT 7 +#define SRAM_READ_EN3_NS_MASK 0x1 +#define SRAM_READ_EN3_NS_MASK_SFT (0x1 << 7) +#define SRAM_WRITE_EN3_NS_SFT 6 +#define SRAM_WRITE_EN3_NS_MASK 0x1 +#define SRAM_WRITE_EN3_NS_MASK_SFT (0x1 << 6) +#define SRAM_READ_EN2_NS_SFT 5 +#define SRAM_READ_EN2_NS_MASK 0x1 +#define SRAM_READ_EN2_NS_MASK_SFT (0x1 << 5) +#define SRAM_WRITE_EN2_NS_SFT 4 +#define SRAM_WRITE_EN2_NS_MASK 0x1 +#define SRAM_WRITE_EN2_NS_MASK_SFT (0x1 << 4) +#define SRAM_READ_EN1_NS_SFT 3 +#define SRAM_READ_EN1_NS_MASK 0x1 +#define SRAM_READ_EN1_NS_MASK_SFT (0x1 << 3) +#define SRAM_WRITE_EN1_NS_SFT 2 +#define SRAM_WRITE_EN1_NS_MASK 0x1 +#define SRAM_WRITE_EN1_NS_MASK_SFT (0x1 << 2) +#define SRAM_READ_EN0_NS_SFT 1 +#define SRAM_READ_EN0_NS_MASK 0x1 +#define SRAM_READ_EN0_NS_MASK_SFT (0x1 << 1) +#define SRAM_WRITE_EN0_NS_SFT 0 +#define SRAM_WRITE_EN0_NS_MASK 0x1 +#define SRAM_WRITE_EN0_NS_MASK_SFT (0x1 << 0) + +/* AFE_SECURE_SRAM_CON1 */ +#define SRAM_READ_EN15_S_SFT 31 +#define SRAM_READ_EN15_S_MASK 0x1 +#define SRAM_READ_EN15_S_MASK_SFT (0x1 << 31) +#define SRAM_WRITE_EN15_S_SFT 30 +#define SRAM_WRITE_EN15_S_MASK 0x1 +#define SRAM_WRITE_EN15_S_MASK_SFT (0x1 << 30) +#define SRAM_READ_EN14_S_SFT 29 +#define SRAM_READ_EN14_S_MASK 0x1 +#define SRAM_READ_EN14_S_MASK_SFT (0x1 << 29) +#define SRAM_WRITE_EN14_S_SFT 28 +#define SRAM_WRITE_EN14_S_MASK 0x1 +#define SRAM_WRITE_EN14_S_MASK_SFT (0x1 << 28) +#define SRAM_READ_EN13_S_SFT 27 +#define SRAM_READ_EN13_S_MASK 0x1 +#define SRAM_READ_EN13_S_MASK_SFT (0x1 << 27) +#define SRAM_WRITE_EN13_S_SFT 26 +#define SRAM_WRITE_EN13_S_MASK 0x1 +#define SRAM_WRITE_EN13_S_MASK_SFT (0x1 << 26) +#define SRAM_READ_EN12_S_SFT 25 +#define SRAM_READ_EN12_S_MASK 0x1 +#define SRAM_READ_EN12_S_MASK_SFT (0x1 << 25) +#define SRAM_WRITE_EN12_S_SFT 24 +#define SRAM_WRITE_EN12_S_MASK 0x1 +#define SRAM_WRITE_EN12_S_MASK_SFT (0x1 << 24) +#define SRAM_READ_EN11_S_SFT 23 +#define SRAM_READ_EN11_S_MASK 0x1 +#define SRAM_READ_EN11_S_MASK_SFT (0x1 << 23) +#define SRAM_WRITE_EN11_S_SFT 22 +#define SRAM_WRITE_EN11_S_MASK 0x1 +#define SRAM_WRITE_EN11_S_MASK_SFT (0x1 << 22) +#define SRAM_READ_EN10_S_SFT 21 +#define SRAM_READ_EN10_S_MASK 0x1 +#define SRAM_READ_EN10_S_MASK_SFT (0x1 << 21) +#define SRAM_WRITE_EN10_S_SFT 20 +#define SRAM_WRITE_EN10_S_MASK 0x1 +#define SRAM_WRITE_EN10_S_MASK_SFT (0x1 << 20) +#define SRAM_READ_EN9_S_SFT 19 +#define SRAM_READ_EN9_S_MASK 0x1 +#define SRAM_READ_EN9_S_MASK_SFT (0x1 << 19) +#define SRAM_WRITE_EN9_S_SFT 18 +#define SRAM_WRITE_EN9_S_MASK 0x1 +#define SRAM_WRITE_EN9_S_MASK_SFT (0x1 << 18) +#define SRAM_READ_EN8_S_SFT 17 +#define SRAM_READ_EN8_S_MASK 0x1 +#define SRAM_READ_EN8_S_MASK_SFT (0x1 << 17) +#define SRAM_WRITE_EN8_S_SFT 16 +#define SRAM_WRITE_EN8_S_MASK 0x1 +#define SRAM_WRITE_EN8_S_MASK_SFT (0x1 << 16) +#define SRAM_READ_EN7_S_SFT 15 +#define SRAM_READ_EN7_S_MASK 0x1 +#define SRAM_READ_EN7_S_MASK_SFT (0x1 << 15) +#define SRAM_WRITE_EN7_S_SFT 14 +#define SRAM_WRITE_EN7_S_MASK 0x1 +#define SRAM_WRITE_EN7_S_MASK_SFT (0x1 << 14) +#define SRAM_READ_EN6_S_SFT 13 +#define SRAM_READ_EN6_S_MASK 0x1 +#define SRAM_READ_EN6_S_MASK_SFT (0x1 << 13) +#define SRAM_WRITE_EN6_S_SFT 12 +#define SRAM_WRITE_EN6_S_MASK 0x1 +#define SRAM_WRITE_EN6_S_MASK_SFT (0x1 << 12) +#define SRAM_READ_EN5_S_SFT 11 +#define SRAM_READ_EN5_S_MASK 0x1 +#define SRAM_READ_EN5_S_MASK_SFT (0x1 << 11) +#define SRAM_WRITE_EN5_S_SFT 10 +#define SRAM_WRITE_EN5_S_MASK 0x1 +#define SRAM_WRITE_EN5_S_MASK_SFT (0x1 << 10) +#define SRAM_READ_EN4_S_SFT 9 +#define SRAM_READ_EN4_S_MASK 0x1 +#define SRAM_READ_EN4_S_MASK_SFT (0x1 << 9) +#define SRAM_WRITE_EN4_S_SFT 8 +#define SRAM_WRITE_EN4_S_MASK 0x1 +#define SRAM_WRITE_EN4_S_MASK_SFT (0x1 << 8) +#define SRAM_READ_EN3_S_SFT 7 +#define SRAM_READ_EN3_S_MASK 0x1 +#define SRAM_READ_EN3_S_MASK_SFT (0x1 << 7) +#define SRAM_WRITE_EN3_S_SFT 6 +#define SRAM_WRITE_EN3_S_MASK 0x1 +#define SRAM_WRITE_EN3_S_MASK_SFT (0x1 << 6) +#define SRAM_READ_EN2_S_SFT 5 +#define SRAM_READ_EN2_S_MASK 0x1 +#define SRAM_READ_EN2_S_MASK_SFT (0x1 << 5) +#define SRAM_WRITE_EN2_S_SFT 4 +#define SRAM_WRITE_EN2_S_MASK 0x1 +#define SRAM_WRITE_EN2_S_MASK_SFT (0x1 << 4) +#define SRAM_READ_EN1_S_SFT 3 +#define SRAM_READ_EN1_S_MASK 0x1 +#define SRAM_READ_EN1_S_MASK_SFT (0x1 << 3) +#define SRAM_WRITE_EN1_S_SFT 2 +#define SRAM_WRITE_EN1_S_MASK 0x1 +#define SRAM_WRITE_EN1_S_MASK_SFT (0x1 << 2) +#define SRAM_READ_EN0_S_SFT 1 +#define SRAM_READ_EN0_S_MASK 0x1 +#define SRAM_READ_EN0_S_MASK_SFT (0x1 << 1) +#define SRAM_WRITE_EN0_S_SFT 0 +#define SRAM_WRITE_EN0_S_MASK 0x1 +#define SRAM_WRITE_EN0_S_MASK_SFT (0x1 << 0) + +/* AFE_SE_CONN_INPUT_MASK0 */ +#define SECURE_INTRCONN_I0_I31_S_SFT 0 +#define SECURE_INTRCONN_I0_I31_S_MASK 0xffffffff +#define SECURE_INTRCONN_I0_I31_S_MASK_SFT (0xffffffff << 0) + +/* AFE_SE_CONN_INPUT_MASK1 */ +#define SECURE_INTRCONN_I32_I63_S_SFT 0 +#define SECURE_INTRCONN_I32_I63_S_MASK 0xffffffff +#define SECURE_INTRCONN_I32_I63_S_MASK_SFT (0xffffffff << 0) + +/* AFE_SE_CONN_INPUT_MASK2 */ +#define SECURE_INTRCONN_I64_I95_S_SFT 0 +#define SECURE_INTRCONN_I64_I95_S_MASK 0xffffffff +#define SECURE_INTRCONN_I64_I95_S_MASK_SFT (0xffffffff << 0) + +/* AFE_SE_CONN_INPUT_MASK3 */ +#define SECURE_INTRCONN_I96_I127_S_SFT 0 +#define SECURE_INTRCONN_I96_I127_S_MASK 0xffffffff +#define SECURE_INTRCONN_I96_I127_S_MASK_SFT (0xffffffff << 0) + +/* AFE_SE_CONN_INPUT_MASK4 */ +#define SECURE_INTRCONN_I128_I159_S_SFT 0 +#define SECURE_INTRCONN_I128_I159_S_MASK 0xffffffff +#define SECURE_INTRCONN_I128_I159_S_MASK_SFT (0xffffffff << 0) + +/* AFE_SE_CONN_INPUT_MASK5 */ +#define SECURE_INTRCONN_I160_I191_S_SFT 0 +#define SECURE_INTRCONN_I160_I191_S_MASK 0xffffffff +#define SECURE_INTRCONN_I160_I191_S_MASK_SFT (0xffffffff << 0) + +/* AFE_SE_CONN_INPUT_MASK6 */ +#define SECURE_INTRCONN_I192_I223_S_SFT 0 +#define SECURE_INTRCONN_I192_I223_S_MASK 0xffffffff +#define SECURE_INTRCONN_I192_I223_S_MASK_SFT (0xffffffff << 0) + +/* AFE_SE_CONN_INPUT_MASK7 */ +#define SECURE_INTRCONN_I224_I256_S_SFT 0 +#define SECURE_INTRCONN_I224_I256_S_MASK 0xffffffff +#define SECURE_INTRCONN_I224_I256_S_MASK_SFT (0xffffffff << 0) + +/* AFE_NON_SE_CONN_INPUT_MASK0 */ +#define NORMAL_INTRCONN_I0_I31_S_SFT 0 +#define NORMAL_INTRCONN_I0_I31_S_MASK 0xffffffff +#define NORMAL_INTRCONN_I0_I31_S_MASK_SFT (0xffffffff << 0) + +/* AFE_NON_SE_CONN_INPUT_MASK1 */ +#define NORMAL_INTRCONN_I32_I63_S_SFT 0 +#define NORMAL_INTRCONN_I32_I63_S_MASK 0xffffffff +#define NORMAL_INTRCONN_I32_I63_S_MASK_SFT (0xffffffff << 0) + +/* AFE_NON_SE_CONN_INPUT_MASK2 */ +#define NORMAL_INTRCONN_I64_I95_S_SFT 0 +#define NORMAL_INTRCONN_I64_I95_S_MASK 0xffffffff +#define NORMAL_INTRCONN_I64_I95_S_MASK_SFT (0xffffffff << 0) + +/* AFE_NON_SE_CONN_INPUT_MASK3 */ +#define NORMAL_INTRCONN_I96_I127_S_SFT 0 +#define NORMAL_INTRCONN_I96_I127_S_MASK 0xffffffff +#define NORMAL_INTRCONN_I96_I127_S_MASK_SFT (0xffffffff << 0) + +/* AFE_NON_SE_CONN_INPUT_MASK4 */ +#define NORMAL_INTRCONN_I128_I159_S_SFT 0 +#define NORMAL_INTRCONN_I128_I159_S_MASK 0xffffffff +#define NORMAL_INTRCONN_I128_I159_S_MASK_SFT (0xffffffff << 0) + +/* AFE_NON_SE_CONN_INPUT_MASK5 */ +#define NORMAL_INTRCONN_I160_I191_S_SFT 0 +#define NORMAL_INTRCONN_I160_I191_S_MASK 0xffffffff +#define NORMAL_INTRCONN_I160_I191_S_MASK_SFT (0xffffffff << 0) + +/* AFE_NON_SE_CONN_INPUT_MASK6 */ +#define NORMAL_INTRCONN_I192_I223_S_SFT 0 +#define NORMAL_INTRCONN_I192_I223_S_MASK 0xffffffff +#define NORMAL_INTRCONN_I192_I223_S_MASK_SFT (0xffffffff << 0) + +/* AFE_NON_SE_CONN_INPUT_MASK7 */ +#define NORMAL_INTRCONN_I224_I256_S_SFT 0 +#define NORMAL_INTRCONN_I224_I256_S_MASK 0xffffffff +#define NORMAL_INTRCONN_I224_I256_S_MASK_SFT (0xffffffff << 0) + +/* AFE_SE_CONN_OUTPUT_SEL0 */ +#define SECURE_INTRCONN_O0_O31_S_SFT 0 +#define SECURE_INTRCONN_O0_O31_S_MASK 0xffffffff +#define SECURE_INTRCONN_O0_O31_S_MASK_SFT (0xffffffff << 0) + +/* AFE_SE_CONN_OUTPUT_SEL1 */ +#define SECURE_INTRCONN_O32_O63_S_SFT 0 +#define SECURE_INTRCONN_O32_O63_S_MASK 0xffffffff +#define SECURE_INTRCONN_O32_O63_S_MASK_SFT (0xffffffff << 0) + +/* AFE_SE_CONN_OUTPUT_SEL2 */ +#define SECURE_INTRCONN_O64_O95_S_SFT 0 +#define SECURE_INTRCONN_O64_O95_S_MASK 0xffffffff +#define SECURE_INTRCONN_O64_O95_S_MASK_SFT (0xffffffff << 0) + +/* AFE_SE_CONN_OUTPUT_SEL3 */ +#define SECURE_INTRCONN_O96_O127_S_SFT 0 +#define SECURE_INTRCONN_O96_O127_S_MASK 0xffffffff +#define SECURE_INTRCONN_O96_O127_S_MASK_SFT (0xffffffff << 0) + +/* AFE_SE_CONN_OUTPUT_SEL4 */ +#define SECURE_INTRCONN_O128_O159_S_SFT 0 +#define SECURE_INTRCONN_O128_O159_S_MASK 0xffffffff +#define SECURE_INTRCONN_O128_O159_S_MASK_SFT (0xffffffff << 0) + +/* AFE_SE_CONN_OUTPUT_SEL5 */ +#define SECURE_INTRCONN_O160_O191_S_SFT 0 +#define SECURE_INTRCONN_O160_O191_S_MASK 0xffffffff +#define SECURE_INTRCONN_O160_O191_S_MASK_SFT (0xffffffff << 0) + +/* AFE_SE_CONN_OUTPUT_SEL6 */ +#define SECURE_INTRCONN_O192_O223_S_SFT 0 +#define SECURE_INTRCONN_O192_O223_S_MASK 0xffffffff +#define SECURE_INTRCONN_O192_O223_S_MASK_SFT (0xffffffff << 0) + +/* AFE_SE_CONN_OUTPUT_SEL7 */ +#define SECURE_INTRCONN_O224_O256_S_SFT 0 +#define SECURE_INTRCONN_O224_O256_S_MASK 0xffffffff +#define SECURE_INTRCONN_O224_O256_S_MASK_SFT (0xffffffff << 0) + +/* AFE_PCM0_INTF_CON1_MASK_MON */ +#define AFE_PCM0_INTF_CON1_MASK_MON_SFT 0 +#define AFE_PCM0_INTF_CON1_MASK_MON_MASK 0xffffffff +#define AFE_PCM0_INTF_CON1_MASK_MON_MASK_SFT (0xffffffff << 0) + +/* AFE_PCM0_INTF_CON0_MASK_MON */ +#define AFE_PCM0_INTF_CON0_MASK_MON_SFT 0 +#define AFE_PCM0_INTF_CON0_MASK_MON_MASK 0xffffffff +#define AFE_PCM0_INTF_CON0_MASK_MON_MASK_SFT (0xffffffff << 0) + +/* AFE_CONNSYS_I2S_CON_MASK_MON */ +#define AFE_CONNSYS_I2S_CON_MASK_MON_SFT 0 +#define AFE_CONNSYS_I2S_CON_MASK_MON_MASK 0xffffffff +#define AFE_CONNSYS_I2S_CON_MASK_MON_MASK_SFT (0xffffffff << 0) + +/* AFE_TDM_CON2_MASK_MON */ +#define AFE_TDM_CON2_MASK_MON_SFT 0 +#define AFE_TDM_CON2_MASK_MON_MASK 0xffffffff +#define AFE_TDM_CON2_MASK_MON_MASK_SFT (0xffffffff << 0) + +/* AFE_MTKAIF0_CFG0_MASK_MON */ +#define AFE_MTKAIF0_CFG0_MASK_MON_SFT 0 +#define AFE_MTKAIF0_CFG0_MASK_MON_MASK 0xffffffff +#define AFE_MTKAIF0_CFG0_MASK_MON_MASK_SFT (0xffffffff << 0) + +/* AFE_MTKAIF1_CFG0_MASK_MON */ +#define AFE_MTKAIF1_CFG0_MASK_MON_SFT 0 +#define AFE_MTKAIF1_CFG0_MASK_MON_MASK 0xffffffff +#define AFE_MTKAIF1_CFG0_MASK_MON_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL0_SRC_CON0_MASK_MON */ +#define AFE_ADDA_UL0_SRC_CON0_MASK_MON_SFT 0 +#define AFE_ADDA_UL0_SRC_CON0_MASK_MON_MASK 0xffffffff +#define AFE_ADDA_UL0_SRC_CON0_MASK_MON_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL1_SRC_CON0_MASK_MON */ +#define AFE_ADDA_UL1_SRC_CON0_MASK_MON_SFT 0 +#define AFE_ADDA_UL1_SRC_CON0_MASK_MON_MASK 0xffffffff +#define AFE_ADDA_UL1_SRC_CON0_MASK_MON_MASK_SFT (0xffffffff << 0) + +/* AFE_ADDA_UL2_SRC_CON0_MASK_MON */ +#define AFE_ADDA_UL2_SRC_CON0_MASK_MON_SFT 0 +#define AFE_ADDA_UL2_SRC_CON0_MASK_MON_MASK 0xffffffff +#define AFE_ADDA_UL2_SRC_CON0_MASK_MON_MASK_SFT (0xffffffff << 0) + +/* AFE_ASRC_NEW_CON0 */ +#define ONE_HEART_SFT 31 +#define ONE_HEART_MASK 0x1 +#define ONE_HEART_MASK_SFT (0x1 << 31) +#define CHSET0_OFS_ONE_HEART_DISABLE_SFT 30 +#define CHSET0_OFS_ONE_HEART_DISABLE_MASK 0x1 +#define CHSET0_OFS_ONE_HEART_DISABLE_MASK_SFT (0x1 << 30) +#define USE_SHORT_DELAY_COEFF_SFT 29 +#define USE_SHORT_DELAY_COEFF_MASK 0x1 +#define USE_SHORT_DELAY_COEFF_MASK_SFT (0x1 << 29) +#define CHSET0_O16BIT_SFT 19 +#define CHSET0_O16BIT_MASK 0x1 +#define CHSET0_O16BIT_MASK_SFT (0x1 << 19) +#define CHSET0_CLR_IIR_HISTORY_SFT 17 +#define CHSET0_CLR_IIR_HISTORY_MASK 0x1 +#define CHSET0_CLR_IIR_HISTORY_MASK_SFT (0x1 << 17) +#define CHSET0_IS_MONO_SFT 16 +#define CHSET0_IS_MONO_MASK 0x1 +#define CHSET0_IS_MONO_MASK_SFT (0x1 << 16) +#define CHSET0_OFS_SEL_SFT 14 +#define CHSET0_OFS_SEL_MASK 0x3 +#define CHSET0_OFS_SEL_MASK_SFT (0x3 << 14) +#define CHSET0_IFS_SEL_SFT 12 +#define CHSET0_IFS_SEL_MASK 0x3 +#define CHSET0_IFS_SEL_MASK_SFT (0x3 << 12) +#define CHSET0_IIR_EN_SFT 11 +#define CHSET0_IIR_EN_MASK 0x1 +#define CHSET0_IIR_EN_MASK_SFT (0x1 << 11) +#define CHSET0_IIR_STAGE_SFT 8 +#define CHSET0_IIR_STAGE_MASK 0x7 +#define CHSET0_IIR_STAGE_MASK_SFT (0x7 << 8) +#define ASM_ON_MOD_SFT 7 +#define ASM_ON_MOD_MASK 0x1 +#define ASM_ON_MOD_MASK_SFT (0x1 << 7) +#define CHSET_STR_CLR_SFT 4 +#define CHSET_STR_CLR_MASK 0x1 +#define CHSET_STR_CLR_MASK_SFT (0x1 << 4) +#define CHSET_ON_SFT 2 +#define CHSET_ON_MASK 0x1 +#define CHSET_ON_MASK_SFT (0x1 << 2) +#define COEFF_SRAM_CTRL_SFT 1 +#define COEFF_SRAM_CTRL_MASK 0x1 +#define COEFF_SRAM_CTRL_MASK_SFT (0x1 << 1) +#define ASM_ON_SFT 0 +#define ASM_ON_MASK 0x1 +#define ASM_ON_MASK_SFT (0x1 << 0) + +/* AFE_ASRC_NEW_CON1 */ +#define ASM_FREQ_0_SFT 0 +#define ASM_FREQ_0_MASK 0xffffff +#define ASM_FREQ_0_MASK_SFT (0xffffff << 0) + +/* AFE_ASRC_NEW_CON2 */ +#define ASM_FREQ_1_SFT 0 +#define ASM_FREQ_1_MASK 0xffffff +#define ASM_FREQ_1_MASK_SFT (0xffffff << 0) + +/* AFE_ASRC_NEW_CON3 */ +#define ASM_FREQ_2_SFT 0 +#define ASM_FREQ_2_MASK 0xffffff +#define ASM_FREQ_2_MASK_SFT (0xffffff << 0) + +/* AFE_ASRC_NEW_CON4 */ +#define ASM_FREQ_3_SFT 0 +#define ASM_FREQ_3_MASK 0xffffff +#define ASM_FREQ_3_MASK_SFT (0xffffff << 0) + +/* AFE_ASRC_NEW_CON5 */ +#define OUT_EN_SEL_DOMAIN_SFT 29 +#define OUT_EN_SEL_DOMAIN_MASK 0x7 +#define OUT_EN_SEL_DOMAIN_MASK_SFT (0x7 << 29) +#define OUT_EN_SEL_FS_SFT 24 +#define OUT_EN_SEL_FS_MASK 0x1f +#define OUT_EN_SEL_FS_MASK_SFT (0x1f << 24) +#define IN_EN_SEL_DOMAIN_SFT 21 +#define IN_EN_SEL_DOMAIN_MASK 0x7 +#define IN_EN_SEL_DOMAIN_MASK_SFT (0x7 << 21) +#define IN_EN_SEL_FS_SFT 16 +#define IN_EN_SEL_FS_MASK 0x1f +#define IN_EN_SEL_FS_MASK_SFT (0x1f << 16) +#define RESULT_SEL_SFT 8 +#define RESULT_SEL_MASK 0x7 +#define RESULT_SEL_MASK_SFT (0x7 << 8) +#define CALI_CK_SEL_SFT 4 +#define CALI_CK_SEL_MASK 0x7 +#define CALI_CK_SEL_MASK_SFT (0x7 << 4) +#define CALI_LRCK_SEL_SFT 1 +#define CALI_LRCK_SEL_MASK 0x7 +#define CALI_LRCK_SEL_MASK_SFT (0x7 << 1) +#define SOFT_RESET_SFT 0 +#define SOFT_RESET_MASK 0x1 +#define SOFT_RESET_MASK_SFT (0x1 << 0) + +/* AFE_ASRC_NEW_CON6 */ +#define FREQ_CALI_CYCLE_SFT 16 +#define FREQ_CALI_CYCLE_MASK 0xffff +#define FREQ_CALI_CYCLE_MASK_SFT (0xffff << 16) +#define FREQ_CALI_AUTORST_EN_SFT 15 +#define FREQ_CALI_AUTORST_EN_MASK 0x1 +#define FREQ_CALI_AUTORST_EN_MASK_SFT (0x1 << 15) +#define CALI_AUTORST_DETECT_SFT 14 +#define CALI_AUTORST_DETECT_MASK 0x1 +#define CALI_AUTORST_DETECT_MASK_SFT (0x1 << 14) +#define FREQ_CALC_RUNNING_SFT 13 +#define FREQ_CALC_RUNNING_MASK 0x1 +#define FREQ_CALC_RUNNING_MASK_SFT (0x1 << 13) +#define AUTO_TUNE_FREQ3_SFT 12 +#define AUTO_TUNE_FREQ3_MASK 0x1 +#define AUTO_TUNE_FREQ3_MASK_SFT (0x1 << 12) +#define COMP_FREQ_RES_EN_SFT 11 +#define COMP_FREQ_RES_EN_MASK 0x1 +#define COMP_FREQ_RES_EN_MASK_SFT (0x1 << 11) +#define FREQ_CALI_SEL_SFT 8 +#define FREQ_CALI_SEL_MASK 0x3 +#define FREQ_CALI_SEL_MASK_SFT (0x3 << 8) +#define FREQ_CALI_BP_DGL_SFT 7 +#define FREQ_CALI_BP_DGL_MASK 0x1 +#define FREQ_CALI_BP_DGL_MASK_SFT (0x1 << 7) +#define FREQ_CALI_MAX_GWIDTH_SFT 4 +#define FREQ_CALI_MAX_GWIDTH_MASK 0x7 +#define FREQ_CALI_MAX_GWIDTH_MASK_SFT (0x7 << 4) +#define AUTO_TUNE_FREQ2_SFT 3 +#define AUTO_TUNE_FREQ2_MASK 0x1 +#define AUTO_TUNE_FREQ2_MASK_SFT (0x1 << 3) +#define FREQ_CALI_AUTO_RESTART_SFT 2 +#define FREQ_CALI_AUTO_RESTART_MASK 0x1 +#define FREQ_CALI_AUTO_RESTART_MASK_SFT (0x1 << 2) +#define CALI_USE_FREQ_OUT_SFT 1 +#define CALI_USE_FREQ_OUT_MASK 0x1 +#define CALI_USE_FREQ_OUT_MASK_SFT (0x1 << 1) +#define CALI_EN_SFT 0 +#define CALI_EN_MASK 0x1 +#define CALI_EN_MASK_SFT (0x1 << 0) + +/* AFE_ASRC_NEW_CON7 */ +#define FREQ_CALC_DENOMINATOR_SFT 0 +#define FREQ_CALC_DENOMINATOR_MASK 0xffffff +#define FREQ_CALC_DENOMINATOR_MASK_SFT (0xffffff << 0) + +/* AFE_ASRC_NEW_CON8 */ +#define PRD_CALI_RESULT_RECORD_SFT 0 +#define PRD_CALI_RESULT_RECORD_MASK 0xffffff +#define PRD_CALI_RESULT_RECORD_MASK_SFT (0xffffff << 0) + +/* AFE_ASRC_NEW_CON9 */ +#define FREQ_CALI_RESULT_SFT 0 +#define FREQ_CALI_RESULT_MASK 0xffffff +#define FREQ_CALI_RESULT_MASK_SFT (0xffffff << 0) + +/* AFE_ASRC_NEW_CON10 */ +#define COEFF_SRAM_DATA_SFT 0 +#define COEFF_SRAM_DATA_MASK 0xffffffff +#define COEFF_SRAM_DATA_MASK_SFT (0xffffffff << 0) + +/* AFE_ASRC_NEW_CON11 */ +#define COEFF_SRAM_ADR_SFT 0 +#define COEFF_SRAM_ADR_MASK 0x3f +#define COEFF_SRAM_ADR_MASK_SFT (0x3f << 0) + +/* AFE_ASRC_NEW_CON12 */ +#define RING_DBG_RD_SFT 0 +#define RING_DBG_RD_MASK 0x3ffffff +#define RING_DBG_RD_MASK_SFT (0x3ffffff << 0) + +/* AFE_ASRC_NEW_CON13 */ +#define FREQ_CALI_AUTORST_TH_HIGH_SFT 0 +#define FREQ_CALI_AUTORST_TH_HIGH_MASK 0xffffff +#define FREQ_CALI_AUTORST_TH_HIGH_MASK_SFT (0xffffff << 0) + +/* AFE_ASRC_NEW_CON14 */ +#define FREQ_CALI_AUTORST_TH_LOW_SFT 0 +#define FREQ_CALI_AUTORST_TH_LOW_MASK 0xffffff +#define FREQ_CALI_AUTORST_TH_LOW_MASK_SFT (0xffffff << 0) + +/* AFE_ASRC_NEW_IP_VERSION */ +#define IP_VERSION_SFT 0 +#define IP_VERSION_MASK 0xffffffff +#define IP_VERSION_MASK_SFT (0xffffffff << 0) + +#define AUDIO_TOP_CON0 0x0 +#define AUDIO_TOP_CON1 0x4 +#define AUDIO_TOP_CON2 0x8 +#define AUDIO_TOP_CON3 0xc +#define AUDIO_TOP_CON4 0x10 +#define AUDIO_ENGEN_CON0 0x14 +#define AUDIO_ENGEN_CON0_USER1 0x18 +#define AUDIO_ENGEN_CON0_USER2 0x1c +#define AFE_SINEGEN_CON0 0x20 +#define AFE_SINEGEN_CON1 0x24 +#define AFE_SINEGEN_CON2 0x28 +#define AFE_SINEGEN_CON3 0x2c +#define AFE_APLL1_TUNER_CFG 0x30 +#define AFE_APLL1_TUNER_MON0 0x34 +#define AFE_APLL2_TUNER_CFG 0x38 +#define AFE_APLL2_TUNER_MON0 0x3c +#define AUDIO_TOP_RG0 0x4c +#define AUDIO_TOP_RG1 0x50 +#define AUDIO_TOP_RG2 0x54 +#define AUDIO_TOP_RG3 0x58 +#define AUDIO_TOP_RG4 0x5c +#define AFE_SPM_CONTROL_REQ 0x60 +#define AFE_SPM_CONTROL_ACK 0x64 +#define AUD_TOP_CFG_VCORE_RG 0x68 +#define AUDIO_TOP_IP_VERSION 0x6c +#define AUDIO_ENGEN_CON0_MON 0x7c +#define AUD_TOP_CFG_VLP_RG 0x98 +#define AUD_TOP_MON_RG 0x9c +#define AUDIO_USE_DEFAULT_DELSEL0 0xa0 +#define AUDIO_USE_DEFAULT_DELSEL1 0xa4 +#define AUDIO_USE_DEFAULT_DELSEL2 0xa8 +#define AFE_CONNSYS_I2S_IPM_VER_MON 0xb0 +#define AFE_CONNSYS_I2S_MON_SEL 0xb4 +#define AFE_CONNSYS_I2S_MON 0xb8 +#define AFE_CONNSYS_I2S_CON 0xbc +#define AFE_PCM0_INTF_CON0 0xc0 +#define AFE_PCM0_INTF_CON1 0xc4 +#define AFE_PCM_INTF_MON 0xc8 +#define AFE_PCM1_INTF_CON0 0xd0 +#define AFE_PCM1_INTF_CON1 0xd4 +#define AFE_PCM_TOP_IP_VERSION 0xe8 +#define AFE_IRQ_MCU_EN 0x100 +#define AFE_IRQ_MCU_DSP_EN 0x104 +#define AFE_IRQ_MCU_DSP2_EN 0x108 +#define AFE_IRQ_MCU_SCP_EN 0x10c +#define AFE_CUSTOM_IRQ_MCU_EN 0x110 +#define AFE_CUSTOM_IRQ_MCU_DSP_EN 0x114 +#define AFE_CUSTOM_IRQ_MCU_DSP2_EN 0x118 +#define AFE_CUSTOM_IRQ_MCU_SCP_EN 0x11c +#define AFE_IRQ_MCU_STATUS 0x120 +#define AFE_CUSTOM_IRQ_MCU_STATUS 0x124 +#define AFE_IRQ0_MCU_CFG0 0x140 +#define AFE_IRQ0_MCU_CFG1 0x144 +#define AFE_IRQ1_MCU_CFG0 0x148 +#define AFE_IRQ1_MCU_CFG1 0x14c +#define AFE_IRQ2_MCU_CFG0 0x150 +#define AFE_IRQ2_MCU_CFG1 0x154 +#define AFE_IRQ3_MCU_CFG0 0x158 +#define AFE_IRQ3_MCU_CFG1 0x15c +#define AFE_IRQ4_MCU_CFG0 0x160 +#define AFE_IRQ4_MCU_CFG1 0x164 +#define AFE_IRQ5_MCU_CFG0 0x168 +#define AFE_IRQ5_MCU_CFG1 0x16c +#define AFE_IRQ6_MCU_CFG0 0x170 +#define AFE_IRQ6_MCU_CFG1 0x174 +#define AFE_IRQ7_MCU_CFG0 0x178 +#define AFE_IRQ7_MCU_CFG1 0x17c +#define AFE_IRQ8_MCU_CFG0 0x180 +#define AFE_IRQ8_MCU_CFG1 0x184 +#define AFE_IRQ9_MCU_CFG0 0x188 +#define AFE_IRQ9_MCU_CFG1 0x18c +#define AFE_IRQ10_MCU_CFG0 0x190 +#define AFE_IRQ10_MCU_CFG1 0x194 +#define AFE_IRQ11_MCU_CFG0 0x198 +#define AFE_IRQ11_MCU_CFG1 0x19c +#define AFE_IRQ12_MCU_CFG0 0x1a0 +#define AFE_IRQ12_MCU_CFG1 0x1a4 +#define AFE_IRQ13_MCU_CFG0 0x1a8 +#define AFE_IRQ13_MCU_CFG1 0x1ac +#define AFE_IRQ14_MCU_CFG0 0x1b0 +#define AFE_IRQ14_MCU_CFG1 0x1b4 +#define AFE_IRQ15_MCU_CFG0 0x1b8 +#define AFE_IRQ15_MCU_CFG1 0x1bc +#define AFE_IRQ16_MCU_CFG0 0x1c0 +#define AFE_IRQ16_MCU_CFG1 0x1c4 +#define AFE_IRQ17_MCU_CFG0 0x1c8 +#define AFE_IRQ17_MCU_CFG1 0x1cc +#define AFE_IRQ18_MCU_CFG0 0x1d0 +#define AFE_IRQ18_MCU_CFG1 0x1d4 +#define AFE_IRQ19_MCU_CFG0 0x1d8 +#define AFE_IRQ19_MCU_CFG1 0x1dc +#define AFE_IRQ20_MCU_CFG0 0x1e0 +#define AFE_IRQ20_MCU_CFG1 0x1e4 +#define AFE_IRQ21_MCU_CFG0 0x1e8 +#define AFE_IRQ21_MCU_CFG1 0x1ec +#define AFE_IRQ22_MCU_CFG0 0x1f0 +#define AFE_IRQ22_MCU_CFG1 0x1f4 +#define AFE_IRQ23_MCU_CFG0 0x1f8 +#define AFE_IRQ23_MCU_CFG1 0x1fc +#define AFE_IRQ24_MCU_CFG0 0x200 +#define AFE_IRQ24_MCU_CFG1 0x204 +#define AFE_IRQ25_MCU_CFG0 0x208 +#define AFE_IRQ25_MCU_CFG1 0x20c +#define AFE_IRQ26_MCU_CFG0 0x210 +#define AFE_IRQ26_MCU_CFG1 0x214 +#define AFE_CUSTOM_IRQ0_MCU_CFG0 0x268 +#define AFE_IRQ_MCU_MON0 0x300 +#define AFE_IRQ_MCU_MON1 0x304 +#define AFE_IRQ_MCU_MON2 0x308 +#define AFE_IRQ0_CNT_MON 0x310 +#define AFE_IRQ1_CNT_MON 0x314 +#define AFE_IRQ2_CNT_MON 0x318 +#define AFE_IRQ3_CNT_MON 0x31c +#define AFE_IRQ4_CNT_MON 0x320 +#define AFE_IRQ5_CNT_MON 0x324 +#define AFE_IRQ6_CNT_MON 0x328 +#define AFE_IRQ7_CNT_MON 0x32c +#define AFE_IRQ8_CNT_MON 0x330 +#define AFE_IRQ9_CNT_MON 0x334 +#define AFE_IRQ10_CNT_MON 0x338 +#define AFE_IRQ11_CNT_MON 0x33c +#define AFE_IRQ12_CNT_MON 0x340 +#define AFE_IRQ13_CNT_MON 0x344 +#define AFE_IRQ14_CNT_MON 0x348 +#define AFE_IRQ15_CNT_MON 0x34c +#define AFE_IRQ16_CNT_MON 0x350 +#define AFE_IRQ17_CNT_MON 0x354 +#define AFE_IRQ18_CNT_MON 0x358 +#define AFE_IRQ19_CNT_MON 0x35c +#define AFE_IRQ20_CNT_MON 0x360 +#define AFE_IRQ21_CNT_MON 0x364 +#define AFE_IRQ22_CNT_MON 0x368 +#define AFE_IRQ23_CNT_MON 0x36c +#define AFE_IRQ24_CNT_MON 0x370 +#define AFE_IRQ25_CNT_MON 0x374 +#define AFE_IRQ26_CNT_MON 0x378 +#define AFE_CUSTOM_IRQ0_CNT_MON 0x390 +#define AFE_CUSTOM_IRQ0_MCU_CFG1 0x3dc +#define AFE_GAIN0_CON0 0x400 +#define AFE_GAIN0_CON1_R 0x404 +#define AFE_GAIN0_CON1_L 0x408 +#define AFE_GAIN0_CON2 0x40c +#define AFE_GAIN0_CON3 0x410 +#define AFE_GAIN0_CUR_R 0x414 +#define AFE_GAIN0_CUR_L 0x418 +#define AFE_GAIN1_CON0 0x41c +#define AFE_GAIN1_CON1_R 0x420 +#define AFE_GAIN1_CON1_L 0x424 +#define AFE_GAIN1_CON2 0x428 +#define AFE_GAIN1_CON3 0x42c +#define AFE_GAIN1_CUR_R 0x430 +#define AFE_GAIN1_CUR_L 0x434 +#define AFE_GAIN2_CON0 0x438 +#define AFE_GAIN2_CON1_R 0x43c +#define AFE_GAIN2_CON1_L 0x440 +#define AFE_GAIN2_CON2 0x444 +#define AFE_GAIN2_CON3 0x448 +#define AFE_GAIN2_CUR_R 0x44c +#define AFE_GAIN2_CUR_L 0x450 +#define AFE_GAIN3_CON0 0x454 +#define AFE_GAIN3_CON1_R 0x458 +#define AFE_GAIN3_CON1_L 0x45c +#define AFE_GAIN3_CON2 0x460 +#define AFE_GAIN3_CON3 0x464 +#define AFE_GAIN3_CUR_R 0x468 +#define AFE_GAIN3_CUR_L 0x46c +#define AFE_STF_CON0 0xb80 +#define AFE_STF_CON1 0xb84 +#define AFE_STF_COEFF 0xb88 +#define AFE_STF_GAIN 0xb8c +#define AFE_STF_MON 0xb90 +#define AFE_STF_IP_VERSION 0xb94 +#define AFE_CM0_CON0 0xba0 +#define AFE_CM0_MON 0xba4 +#define AFE_CM0_IP_VERSION 0xba8 +#define AFE_CM1_CON0 0xbb0 +#define AFE_CM1_MON 0xbb4 +#define AFE_CM1_IP_VERSION 0xbb8 +#define AFE_CM2_CON0 0xbc0 +#define AFE_CM2_MON 0xbc4 +#define AFE_CM2_IP_VERSION 0xbc8 +#define AFE_ADDA_UL0_SRC_CON0 0xbd0 +#define AFE_ADDA_UL0_SRC_CON1 0xbd4 +#define AFE_ADDA_UL0_SRC_CON2 0xbd8 +#define AFE_ADDA_UL0_SRC_DEBUG 0xbdc +#define AFE_ADDA_UL0_SRC_DEBUG_MON0 0xbe0 +#define AFE_ADDA_UL0_SRC_MON0 0xbe4 +#define AFE_ADDA_UL0_SRC_MON1 0xbe8 +#define AFE_ADDA_UL0_IIR_COEF_02_01 0xbec +#define AFE_ADDA_UL0_IIR_COEF_04_03 0xbf0 +#define AFE_ADDA_UL0_IIR_COEF_06_05 0xbf4 +#define AFE_ADDA_UL0_IIR_COEF_08_07 0xbf8 +#define AFE_ADDA_UL0_IIR_COEF_10_09 0xbfc +#define AFE_ADDA_UL0_ULCF_CFG_02_01 0xc00 +#define AFE_ADDA_UL0_ULCF_CFG_04_03 0xc04 +#define AFE_ADDA_UL0_ULCF_CFG_06_05 0xc08 +#define AFE_ADDA_UL0_ULCF_CFG_08_07 0xc0c +#define AFE_ADDA_UL0_ULCF_CFG_10_09 0xc10 +#define AFE_ADDA_UL0_ULCF_CFG_12_11 0xc14 +#define AFE_ADDA_UL0_ULCF_CFG_14_13 0xc18 +#define AFE_ADDA_UL0_ULCF_CFG_16_15 0xc1c +#define AFE_ADDA_UL0_ULCF_CFG_18_17 0xc20 +#define AFE_ADDA_UL0_ULCF_CFG_20_19 0xc24 +#define AFE_ADDA_UL0_ULCF_CFG_22_21 0xc28 +#define AFE_ADDA_UL0_ULCF_CFG_24_23 0xc2c +#define AFE_ADDA_UL0_ULCF_CFG_26_25 0xc30 +#define AFE_ADDA_UL0_ULCF_CFG_28_27 0xc34 +#define AFE_ADDA_UL0_ULCF_CFG_30_29 0xc38 +#define AFE_ADDA_UL0_ULCF_CFG_32_31 0xc3c +#define AFE_ADDA_UL0_IP_VERSION 0xc4c +#define AFE_ADDA_UL1_SRC_CON0 0xc50 +#define AFE_ADDA_UL1_SRC_CON1 0xc54 +#define AFE_ADDA_UL1_SRC_CON2 0xc58 +#define AFE_ADDA_UL1_SRC_DEBUG 0xc5c +#define AFE_ADDA_UL1_SRC_DEBUG_MON0 0xc60 +#define AFE_ADDA_UL1_SRC_MON0 0xc64 +#define AFE_ADDA_UL1_SRC_MON1 0xc68 +#define AFE_ADDA_UL1_IIR_COEF_02_01 0xc6c +#define AFE_ADDA_UL1_IIR_COEF_04_03 0xc70 +#define AFE_ADDA_UL1_IIR_COEF_06_05 0xc74 +#define AFE_ADDA_UL1_IIR_COEF_08_07 0xc78 +#define AFE_ADDA_UL1_IIR_COEF_10_09 0xc7c +#define AFE_ADDA_UL1_ULCF_CFG_02_01 0xc80 +#define AFE_ADDA_UL1_ULCF_CFG_04_03 0xc84 +#define AFE_ADDA_UL1_ULCF_CFG_06_05 0xc88 +#define AFE_ADDA_UL1_ULCF_CFG_08_07 0xc8c +#define AFE_ADDA_UL1_ULCF_CFG_10_09 0xc90 +#define AFE_ADDA_UL1_ULCF_CFG_12_11 0xc94 +#define AFE_ADDA_UL1_ULCF_CFG_14_13 0xc98 +#define AFE_ADDA_UL1_ULCF_CFG_16_15 0xc9c +#define AFE_ADDA_UL1_ULCF_CFG_18_17 0xca0 +#define AFE_ADDA_UL1_ULCF_CFG_20_19 0xca4 +#define AFE_ADDA_UL1_ULCF_CFG_22_21 0xca8 +#define AFE_ADDA_UL1_ULCF_CFG_24_23 0xcac +#define AFE_ADDA_UL1_ULCF_CFG_26_25 0xcb0 +#define AFE_ADDA_UL1_ULCF_CFG_28_27 0xcb4 +#define AFE_ADDA_UL1_ULCF_CFG_30_29 0xcb8 +#define AFE_ADDA_UL1_ULCF_CFG_32_31 0xcbc +#define AFE_ADDA_UL1_IP_VERSION 0xccc +#define AFE_ADDA_UL2_SRC_CON0 0xcd0 +#define AFE_ADDA_UL2_SRC_CON1 0xcd4 +#define AFE_ADDA_UL2_SRC_CON2 0xcd8 +#define AFE_ADDA_UL2_SRC_DEBUG 0xcdc +#define AFE_ADDA_UL2_SRC_DEBUG_MON0 0xce0 +#define AFE_ADDA_UL2_SRC_MON0 0xce4 +#define AFE_ADDA_UL2_SRC_MON1 0xce8 +#define AFE_ADDA_UL2_IIR_COEF_02_01 0xcec +#define AFE_ADDA_UL2_IIR_COEF_04_03 0xcf0 +#define AFE_ADDA_UL2_IIR_COEF_06_05 0xcf4 +#define AFE_ADDA_UL2_IIR_COEF_08_07 0xcf8 +#define AFE_ADDA_UL2_IIR_COEF_10_09 0xcfc +#define AFE_ADDA_UL2_ULCF_CFG_02_01 0xd00 +#define AFE_ADDA_UL2_ULCF_CFG_04_03 0xd04 +#define AFE_ADDA_UL2_ULCF_CFG_06_05 0xd08 +#define AFE_ADDA_UL2_ULCF_CFG_08_07 0xd0c +#define AFE_ADDA_UL2_ULCF_CFG_10_09 0xd10 +#define AFE_ADDA_UL2_ULCF_CFG_12_11 0xd14 +#define AFE_ADDA_UL2_ULCF_CFG_14_13 0xd18 +#define AFE_ADDA_UL2_ULCF_CFG_16_15 0xd1c +#define AFE_ADDA_UL2_ULCF_CFG_18_17 0xd20 +#define AFE_ADDA_UL2_ULCF_CFG_20_19 0xd24 +#define AFE_ADDA_UL2_ULCF_CFG_22_21 0xd28 +#define AFE_ADDA_UL2_ULCF_CFG_24_23 0xd2c +#define AFE_ADDA_UL2_ULCF_CFG_26_25 0xd30 +#define AFE_ADDA_UL2_ULCF_CFG_28_27 0xd34 +#define AFE_ADDA_UL2_ULCF_CFG_30_29 0xd38 +#define AFE_ADDA_UL2_ULCF_CFG_32_31 0xd3c +#define AFE_ADDA_UL2_IP_VERSION 0xd4c +#define AFE_ADDA_PROXIMITY_CON0 0xed0 +#define AFE_ADDA_ULSRC_PHASE_CON0 0xf00 +#define AFE_ADDA_ULSRC_PHASE_CON1 0xf04 +#define AFE_ADDA_ULSRC_PHASE_CON2 0xf08 +#define AFE_ADDA_ULSRC_PHASE_CON3 0xf0c +#define AFE_MTKAIF_IPM_VER_MON 0x1180 +#define AFE_MTKAIF_MON_SEL 0x1184 +#define AFE_MTKAIF_MON 0x1188 +#define AFE_MTKAIF0_CFG0 0x1190 +#define AFE_MTKAIF0_TX_CFG0 0x1194 +#define AFE_MTKAIF0_RX_CFG0 0x1198 +#define AFE_MTKAIF0_RX_CFG1 0x119c +#define AFE_MTKAIF0_RX_CFG2 0x11a0 +#define AFE_MTKAIF1_CFG0 0x11f0 +#define AFE_MTKAIF1_TX_CFG0 0x11f4 +#define AFE_MTKAIF1_RX_CFG0 0x11f8 +#define AFE_MTKAIF1_RX_CFG1 0x11fc +#define AFE_MTKAIF1_RX_CFG2 0x1200 +#define AFE_AUD_PAD_TOP_CFG0 0x1204 +#define AFE_AUD_PAD_TOP_MON 0x1208 +#define AFE_ADDA_MTKAIFV4_TX_CFG0 0x1280 +#define AFE_ADDA6_MTKAIFV4_TX_CFG0 0x1284 +#define AFE_ADDA_MTKAIFV4_RX_CFG0 0x1288 +#define AFE_ADDA_MTKAIFV4_RX_CFG1 0x128c +#define AFE_ADDA6_MTKAIFV4_RX_CFG0 0x1290 +#define AFE_ADDA6_MTKAIFV4_RX_CFG1 0x1294 +#define AFE_ADDA_MTKAIFV4_TX_SYNCWORD_CFG 0x1298 +#define AFE_ADDA_MTKAIFV4_RX_SYNCWORD_CFG 0x129c +#define AFE_ADDA_MTKAIFV4_MON0 0x12a0 +#define AFE_ADDA_MTKAIFV4_MON1 0x12a4 +#define AFE_ADDA6_MTKAIFV4_MON0 0x12a8 +#define ETDM_IN0_CON0 0x1300 +#define ETDM_IN0_CON1 0x1304 +#define ETDM_IN0_CON2 0x1308 +#define ETDM_IN0_CON3 0x130c +#define ETDM_IN0_CON4 0x1310 +#define ETDM_IN0_CON5 0x1314 +#define ETDM_IN0_CON6 0x1318 +#define ETDM_IN0_CON7 0x131c +#define ETDM_IN0_CON8 0x1320 +#define ETDM_IN0_CON9 0x1324 +#define ETDM_IN0_MON 0x1328 +#define ETDM_IN1_CON0 0x1330 +#define ETDM_IN1_CON1 0x1334 +#define ETDM_IN1_CON2 0x1338 +#define ETDM_IN1_CON3 0x133c +#define ETDM_IN1_CON4 0x1340 +#define ETDM_IN1_CON5 0x1344 +#define ETDM_IN1_CON6 0x1348 +#define ETDM_IN1_CON7 0x134c +#define ETDM_IN1_CON8 0x1350 +#define ETDM_IN1_CON9 0x1354 +#define ETDM_IN1_MON 0x1358 +#define ETDM_IN2_CON0 0x1360 +#define ETDM_IN2_CON1 0x1364 +#define ETDM_IN2_CON2 0x1368 +#define ETDM_IN2_CON3 0x136c +#define ETDM_IN2_CON4 0x1370 +#define ETDM_IN2_CON5 0x1374 +#define ETDM_IN2_CON6 0x1378 +#define ETDM_IN2_CON7 0x137c +#define ETDM_IN2_CON8 0x1380 +#define ETDM_IN2_CON9 0x1384 +#define ETDM_IN2_MON 0x1388 +#define ETDM_IN3_CON0 0x1390 +#define ETDM_IN3_CON1 0x1394 +#define ETDM_IN3_CON2 0x1398 +#define ETDM_IN3_CON3 0x139c +#define ETDM_IN3_CON4 0x13a0 +#define ETDM_IN3_CON5 0x13a4 +#define ETDM_IN3_CON6 0x13a8 +#define ETDM_IN3_CON7 0x13ac +#define ETDM_IN3_CON8 0x13b0 +#define ETDM_IN3_CON9 0x13b4 +#define ETDM_IN3_MON 0x13b8 +#define ETDM_IN4_CON0 0x13c0 +#define ETDM_IN4_CON1 0x13c4 +#define ETDM_IN4_CON2 0x13c8 +#define ETDM_IN4_CON3 0x13cc +#define ETDM_IN4_CON4 0x13d0 +#define ETDM_IN4_CON5 0x13d4 +#define ETDM_IN4_CON6 0x13d8 +#define ETDM_IN4_CON7 0x13dc +#define ETDM_IN4_CON8 0x13e0 +#define ETDM_IN4_CON9 0x13e4 +#define ETDM_IN4_MON 0x13e8 +#define ETDM_IN5_CON0 0x13f0 +#define ETDM_IN5_CON1 0x13f4 +#define ETDM_IN5_CON2 0x13f8 +#define ETDM_IN5_CON3 0x13fc +#define ETDM_IN5_CON4 0x1400 +#define ETDM_IN5_CON5 0x1404 +#define ETDM_IN5_CON6 0x1408 +#define ETDM_IN5_CON7 0x140c +#define ETDM_IN5_CON8 0x1410 +#define ETDM_IN5_CON9 0x1414 +#define ETDM_IN5_MON 0x1418 +#define ETDM_IN6_CON0 0x1420 +#define ETDM_IN6_CON1 0x1424 +#define ETDM_IN6_CON2 0x1428 +#define ETDM_IN6_CON3 0x142c +#define ETDM_IN6_CON4 0x1430 +#define ETDM_IN6_CON5 0x1434 +#define ETDM_IN6_CON6 0x1438 +#define ETDM_IN6_CON7 0x143c +#define ETDM_IN6_CON8 0x1440 +#define ETDM_IN6_CON9 0x1444 +#define ETDM_IN6_MON 0x1448 +#define ETDM_OUT0_CON0 0x1480 +#define ETDM_OUT0_CON1 0x1484 +#define ETDM_OUT0_CON2 0x1488 +#define ETDM_OUT0_CON3 0x148c +#define ETDM_OUT0_CON4 0x1490 +#define ETDM_OUT0_CON5 0x1494 +#define ETDM_OUT0_CON6 0x1498 +#define ETDM_OUT0_CON7 0x149c +#define ETDM_OUT0_CON8 0x14a0 +#define ETDM_OUT0_CON9 0x14a4 +#define ETDM_OUT0_MON 0x14a8 +#define ETDM_OUT1_CON0 0x14c0 +#define ETDM_OUT1_CON1 0x14c4 +#define ETDM_OUT1_CON2 0x14c8 +#define ETDM_OUT1_CON3 0x14cc +#define ETDM_OUT1_CON4 0x14d0 +#define ETDM_OUT1_CON5 0x14d4 +#define ETDM_OUT1_CON6 0x14d8 +#define ETDM_OUT1_CON7 0x14dc +#define ETDM_OUT1_CON8 0x14e0 +#define ETDM_OUT1_CON9 0x14e4 +#define ETDM_OUT1_MON 0x14e8 +#define ETDM_OUT2_CON0 0x1500 +#define ETDM_OUT2_CON1 0x1504 +#define ETDM_OUT2_CON2 0x1508 +#define ETDM_OUT2_CON3 0x150c +#define ETDM_OUT2_CON4 0x1510 +#define ETDM_OUT2_CON5 0x1514 +#define ETDM_OUT2_CON6 0x1518 +#define ETDM_OUT2_CON7 0x151c +#define ETDM_OUT2_CON8 0x1520 +#define ETDM_OUT2_CON9 0x1524 +#define ETDM_OUT2_MON 0x1528 +#define ETDM_OUT3_CON0 0x1540 +#define ETDM_OUT3_CON1 0x1544 +#define ETDM_OUT3_CON2 0x1548 +#define ETDM_OUT3_CON3 0x154c +#define ETDM_OUT3_CON4 0x1550 +#define ETDM_OUT3_CON5 0x1554 +#define ETDM_OUT3_CON6 0x1558 +#define ETDM_OUT3_CON7 0x155c +#define ETDM_OUT3_CON8 0x1560 +#define ETDM_OUT3_CON9 0x1564 +#define ETDM_OUT3_MON 0x1568 +#define ETDM_OUT4_CON0 0x1580 +#define ETDM_OUT4_CON1 0x1584 +#define ETDM_OUT4_CON2 0x1588 +#define ETDM_OUT4_CON3 0x158c +#define ETDM_OUT4_CON4 0x1590 +#define ETDM_OUT4_CON5 0x1594 +#define ETDM_OUT4_CON6 0x1598 +#define ETDM_OUT4_CON7 0x159c +#define ETDM_OUT4_CON8 0x15a0 +#define ETDM_OUT4_CON9 0x15a4 +#define ETDM_OUT4_MON 0x15a8 +#define ETDM_OUT5_CON0 0x15c0 +#define ETDM_OUT5_CON1 0x15c4 +#define ETDM_OUT5_CON2 0x15c8 +#define ETDM_OUT5_CON3 0x15cc +#define ETDM_OUT5_CON4 0x15d0 +#define ETDM_OUT5_CON5 0x15d4 +#define ETDM_OUT5_CON6 0x15d8 +#define ETDM_OUT5_CON7 0x15dc +#define ETDM_OUT5_CON8 0x15e0 +#define ETDM_OUT5_CON9 0x15e4 +#define ETDM_OUT5_MON 0x15e8 +#define ETDM_OUT6_CON0 0x1600 +#define ETDM_OUT6_CON1 0x1604 +#define ETDM_OUT6_CON2 0x1608 +#define ETDM_OUT6_CON3 0x160c +#define ETDM_OUT6_CON4 0x1610 +#define ETDM_OUT6_CON5 0x1614 +#define ETDM_OUT6_CON6 0x1618 +#define ETDM_OUT6_CON7 0x161c +#define ETDM_OUT6_CON8 0x1620 +#define ETDM_OUT6_CON9 0x1624 +#define ETDM_OUT6_MON 0x1628 +#define ETDM_0_3_COWORK_CON0 0x1680 +#define ETDM_0_3_COWORK_CON1 0x1684 +#define ETDM_0_3_COWORK_CON2 0x1688 +#define ETDM_0_3_COWORK_CON3 0x168c +#define ETDM_4_7_COWORK_CON0 0x1690 +#define ETDM_4_7_COWORK_CON1 0x1694 +#define ETDM_4_7_COWORK_CON2 0x1698 +#define ETDM_4_7_COWORK_CON3 0x169c +#define AFE_DPTX_CON 0x2040 +#define AFE_DPTX_MON 0x2044 +#define AFE_TDM_CON1 0x2048 +#define AFE_TDM_CON2 0x204c +#define AFE_TDM_CON3 0x2050 +#define AFE_TDM_OUT_MON 0x2054 +#define AFE_HDMI_CONN0 0x2078 +#define AFE_TDM_TOP_IP_VERSION 0x207c +#define AFE_CONN004_0 0x2100 +#define AFE_CONN004_1 0x2104 +#define AFE_CONN004_2 0x2108 +#define AFE_CONN004_4 0x2110 +#define AFE_CONN004_5 0x2114 +#define AFE_CONN004_6 0x2118 +#define AFE_CONN004_7 0x211c +#define AFE_CONN005_0 0x2120 +#define AFE_CONN005_1 0x2124 +#define AFE_CONN005_2 0x2128 +#define AFE_CONN005_4 0x2130 +#define AFE_CONN005_5 0x2134 +#define AFE_CONN005_6 0x2138 +#define AFE_CONN005_7 0x213c +#define AFE_CONN006_0 0x2140 +#define AFE_CONN006_1 0x2144 +#define AFE_CONN006_2 0x2148 +#define AFE_CONN006_4 0x2150 +#define AFE_CONN006_5 0x2154 +#define AFE_CONN006_6 0x2158 +#define AFE_CONN006_7 0x215c +#define AFE_CONN007_0 0x2160 +#define AFE_CONN007_1 0x2164 +#define AFE_CONN007_2 0x2168 +#define AFE_CONN007_4 0x2170 +#define AFE_CONN007_5 0x2174 +#define AFE_CONN007_6 0x2178 +#define AFE_CONN007_7 0x217c +#define AFE_CONN008_0 0x2180 +#define AFE_CONN008_1 0x2184 +#define AFE_CONN008_2 0x2188 +#define AFE_CONN008_4 0x2190 +#define AFE_CONN008_5 0x2194 +#define AFE_CONN008_6 0x2198 +#define AFE_CONN008_7 0x219c +#define AFE_CONN009_0 0x21a0 +#define AFE_CONN009_1 0x21a4 +#define AFE_CONN009_2 0x21a8 +#define AFE_CONN009_4 0x21b0 +#define AFE_CONN009_5 0x21b4 +#define AFE_CONN009_6 0x21b8 +#define AFE_CONN009_7 0x21bc +#define AFE_CONN010_0 0x21c0 +#define AFE_CONN010_1 0x21c4 +#define AFE_CONN010_2 0x21c8 +#define AFE_CONN010_4 0x21d0 +#define AFE_CONN010_5 0x21d4 +#define AFE_CONN010_6 0x21d8 +#define AFE_CONN010_7 0x21dc +#define AFE_CONN011_0 0x21e0 +#define AFE_CONN011_1 0x21e4 +#define AFE_CONN011_2 0x21e8 +#define AFE_CONN011_4 0x21f0 +#define AFE_CONN011_5 0x21f4 +#define AFE_CONN011_6 0x21f8 +#define AFE_CONN011_7 0x21fc +#define AFE_CONN012_0 0x2200 +#define AFE_CONN012_1 0x2204 +#define AFE_CONN012_2 0x2208 +#define AFE_CONN012_4 0x2210 +#define AFE_CONN012_5 0x2214 +#define AFE_CONN012_6 0x2218 +#define AFE_CONN012_7 0x221c +#define AFE_CONN014_0 0x2240 +#define AFE_CONN014_1 0x2244 +#define AFE_CONN014_2 0x2248 +#define AFE_CONN014_4 0x2250 +#define AFE_CONN014_5 0x2254 +#define AFE_CONN014_6 0x2258 +#define AFE_CONN014_7 0x225c +#define AFE_CONN015_0 0x2260 +#define AFE_CONN015_1 0x2264 +#define AFE_CONN015_2 0x2268 +#define AFE_CONN015_4 0x2270 +#define AFE_CONN015_5 0x2274 +#define AFE_CONN015_6 0x2278 +#define AFE_CONN015_7 0x227c +#define AFE_CONN016_0 0x2280 +#define AFE_CONN016_1 0x2284 +#define AFE_CONN016_2 0x2288 +#define AFE_CONN016_4 0x2290 +#define AFE_CONN016_5 0x2294 +#define AFE_CONN016_6 0x2298 +#define AFE_CONN016_7 0x229c +#define AFE_CONN017_0 0x22a0 +#define AFE_CONN017_1 0x22a4 +#define AFE_CONN017_2 0x22a8 +#define AFE_CONN017_4 0x22b0 +#define AFE_CONN017_5 0x22b4 +#define AFE_CONN017_6 0x22b8 +#define AFE_CONN017_7 0x22bc +#define AFE_CONN018_0 0x22c0 +#define AFE_CONN018_1 0x22c4 +#define AFE_CONN018_2 0x22c8 +#define AFE_CONN018_4 0x22d0 +#define AFE_CONN018_5 0x22d4 +#define AFE_CONN018_6 0x22d8 +#define AFE_CONN018_7 0x22dc +#define AFE_CONN019_0 0x22e0 +#define AFE_CONN019_1 0x22e4 +#define AFE_CONN019_2 0x22e8 +#define AFE_CONN019_4 0x22f0 +#define AFE_CONN019_5 0x22f4 +#define AFE_CONN019_6 0x22f8 +#define AFE_CONN019_7 0x22fc +#define AFE_CONN020_0 0x2300 +#define AFE_CONN020_1 0x2304 +#define AFE_CONN020_2 0x2308 +#define AFE_CONN020_4 0x2310 +#define AFE_CONN020_5 0x2314 +#define AFE_CONN020_6 0x2318 +#define AFE_CONN020_7 0x231c +#define AFE_CONN021_0 0x2320 +#define AFE_CONN021_1 0x2324 +#define AFE_CONN021_2 0x2328 +#define AFE_CONN021_4 0x2330 +#define AFE_CONN021_5 0x2334 +#define AFE_CONN021_6 0x2338 +#define AFE_CONN021_7 0x233c +#define AFE_CONN022_0 0x2340 +#define AFE_CONN022_1 0x2344 +#define AFE_CONN022_2 0x2348 +#define AFE_CONN022_4 0x2350 +#define AFE_CONN022_5 0x2354 +#define AFE_CONN022_6 0x2358 +#define AFE_CONN022_7 0x235c +#define AFE_CONN023_0 0x2360 +#define AFE_CONN023_1 0x2364 +#define AFE_CONN023_2 0x2368 +#define AFE_CONN023_4 0x2370 +#define AFE_CONN023_5 0x2374 +#define AFE_CONN023_6 0x2378 +#define AFE_CONN023_7 0x237c +#define AFE_CONN024_0 0x2380 +#define AFE_CONN024_1 0x2384 +#define AFE_CONN024_2 0x2388 +#define AFE_CONN024_4 0x2390 +#define AFE_CONN024_5 0x2394 +#define AFE_CONN024_6 0x2398 +#define AFE_CONN024_7 0x239c +#define AFE_CONN025_0 0x23a0 +#define AFE_CONN025_1 0x23a4 +#define AFE_CONN025_2 0x23a8 +#define AFE_CONN025_4 0x23b0 +#define AFE_CONN025_5 0x23b4 +#define AFE_CONN025_6 0x23b8 +#define AFE_CONN025_7 0x23bc +#define AFE_CONN026_0 0x23c0 +#define AFE_CONN026_1 0x23c4 +#define AFE_CONN026_2 0x23c8 +#define AFE_CONN026_4 0x23d0 +#define AFE_CONN026_5 0x23d4 +#define AFE_CONN026_6 0x23d8 +#define AFE_CONN026_7 0x23dc +#define AFE_CONN027_0 0x23e0 +#define AFE_CONN027_1 0x23e4 +#define AFE_CONN027_2 0x23e8 +#define AFE_CONN027_4 0x23f0 +#define AFE_CONN027_5 0x23f4 +#define AFE_CONN027_6 0x23f8 +#define AFE_CONN027_7 0x23fc +#define AFE_CONN028_0 0x2400 +#define AFE_CONN028_1 0x2404 +#define AFE_CONN028_2 0x2408 +#define AFE_CONN028_4 0x2410 +#define AFE_CONN028_5 0x2414 +#define AFE_CONN028_6 0x2418 +#define AFE_CONN028_7 0x241c +#define AFE_CONN029_0 0x2420 +#define AFE_CONN029_1 0x2424 +#define AFE_CONN029_2 0x2428 +#define AFE_CONN029_4 0x2430 +#define AFE_CONN029_5 0x2434 +#define AFE_CONN029_6 0x2438 +#define AFE_CONN029_7 0x243c +#define AFE_CONN030_0 0x2440 +#define AFE_CONN030_1 0x2444 +#define AFE_CONN030_2 0x2448 +#define AFE_CONN030_4 0x2450 +#define AFE_CONN030_5 0x2454 +#define AFE_CONN030_6 0x2458 +#define AFE_CONN030_7 0x245c +#define AFE_CONN031_0 0x2460 +#define AFE_CONN031_1 0x2464 +#define AFE_CONN031_2 0x2468 +#define AFE_CONN031_4 0x2470 +#define AFE_CONN031_5 0x2474 +#define AFE_CONN031_6 0x2478 +#define AFE_CONN031_7 0x247c +#define AFE_CONN032_0 0x2480 +#define AFE_CONN032_1 0x2484 +#define AFE_CONN032_2 0x2488 +#define AFE_CONN032_4 0x2490 +#define AFE_CONN032_5 0x2494 +#define AFE_CONN032_6 0x2498 +#define AFE_CONN032_7 0x249c +#define AFE_CONN033_0 0x24a0 +#define AFE_CONN033_1 0x24a4 +#define AFE_CONN033_2 0x24a8 +#define AFE_CONN033_4 0x24b0 +#define AFE_CONN033_5 0x24b4 +#define AFE_CONN033_6 0x24b8 +#define AFE_CONN033_7 0x24bc +#define AFE_CONN034_0 0x24c0 +#define AFE_CONN034_1 0x24c4 +#define AFE_CONN034_2 0x24c8 +#define AFE_CONN034_4 0x24d0 +#define AFE_CONN034_5 0x24d4 +#define AFE_CONN034_6 0x24d8 +#define AFE_CONN034_7 0x24dc +#define AFE_CONN035_0 0x24e0 +#define AFE_CONN035_1 0x24e4 +#define AFE_CONN035_2 0x24e8 +#define AFE_CONN035_4 0x24f0 +#define AFE_CONN035_5 0x24f4 +#define AFE_CONN035_6 0x24f8 +#define AFE_CONN035_7 0x24fc +#define AFE_CONN036_0 0x2500 +#define AFE_CONN036_1 0x2504 +#define AFE_CONN036_2 0x2508 +#define AFE_CONN036_4 0x2510 +#define AFE_CONN036_5 0x2514 +#define AFE_CONN036_6 0x2518 +#define AFE_CONN036_7 0x251c +#define AFE_CONN037_0 0x2520 +#define AFE_CONN037_1 0x2524 +#define AFE_CONN037_2 0x2528 +#define AFE_CONN037_4 0x2530 +#define AFE_CONN037_5 0x2534 +#define AFE_CONN037_6 0x2538 +#define AFE_CONN037_7 0x253c +#define AFE_CONN038_0 0x2540 +#define AFE_CONN038_1 0x2544 +#define AFE_CONN038_2 0x2548 +#define AFE_CONN038_4 0x2550 +#define AFE_CONN038_5 0x2554 +#define AFE_CONN038_6 0x2558 +#define AFE_CONN038_7 0x255c +#define AFE_CONN039_0 0x2560 +#define AFE_CONN039_1 0x2564 +#define AFE_CONN039_2 0x2568 +#define AFE_CONN039_4 0x2570 +#define AFE_CONN039_5 0x2574 +#define AFE_CONN039_6 0x2578 +#define AFE_CONN039_7 0x257c +#define AFE_CONN040_0 0x2580 +#define AFE_CONN040_1 0x2584 +#define AFE_CONN040_2 0x2588 +#define AFE_CONN040_4 0x2590 +#define AFE_CONN040_5 0x2594 +#define AFE_CONN040_6 0x2598 +#define AFE_CONN040_7 0x259c +#define AFE_CONN041_0 0x25a0 +#define AFE_CONN041_1 0x25a4 +#define AFE_CONN041_2 0x25a8 +#define AFE_CONN041_4 0x25b0 +#define AFE_CONN041_5 0x25b4 +#define AFE_CONN041_6 0x25b8 +#define AFE_CONN041_7 0x25bc +#define AFE_CONN042_0 0x25c0 +#define AFE_CONN042_1 0x25c4 +#define AFE_CONN042_2 0x25c8 +#define AFE_CONN042_4 0x25d0 +#define AFE_CONN042_5 0x25d4 +#define AFE_CONN042_6 0x25d8 +#define AFE_CONN042_7 0x25dc +#define AFE_CONN043_0 0x25e0 +#define AFE_CONN043_1 0x25e4 +#define AFE_CONN043_2 0x25e8 +#define AFE_CONN043_4 0x25f0 +#define AFE_CONN043_5 0x25f4 +#define AFE_CONN043_6 0x25f8 +#define AFE_CONN043_7 0x25fc +#define AFE_CONN044_0 0x2600 +#define AFE_CONN044_1 0x2604 +#define AFE_CONN044_2 0x2608 +#define AFE_CONN044_4 0x2610 +#define AFE_CONN044_5 0x2614 +#define AFE_CONN044_6 0x2618 +#define AFE_CONN044_7 0x261c +#define AFE_CONN045_0 0x2620 +#define AFE_CONN045_1 0x2624 +#define AFE_CONN045_2 0x2628 +#define AFE_CONN045_4 0x2630 +#define AFE_CONN045_5 0x2634 +#define AFE_CONN045_6 0x2638 +#define AFE_CONN045_7 0x263c +#define AFE_CONN046_0 0x2640 +#define AFE_CONN046_1 0x2644 +#define AFE_CONN046_2 0x2648 +#define AFE_CONN046_4 0x2650 +#define AFE_CONN046_5 0x2654 +#define AFE_CONN046_6 0x2658 +#define AFE_CONN046_7 0x265c +#define AFE_CONN047_0 0x2660 +#define AFE_CONN047_1 0x2664 +#define AFE_CONN047_2 0x2668 +#define AFE_CONN047_4 0x2670 +#define AFE_CONN047_5 0x2674 +#define AFE_CONN047_6 0x2678 +#define AFE_CONN047_7 0x267c +#define AFE_CONN048_0 0x2680 +#define AFE_CONN048_1 0x2684 +#define AFE_CONN048_2 0x2688 +#define AFE_CONN048_4 0x2690 +#define AFE_CONN048_5 0x2694 +#define AFE_CONN048_6 0x2698 +#define AFE_CONN048_7 0x269c +#define AFE_CONN049_0 0x26a0 +#define AFE_CONN049_1 0x26a4 +#define AFE_CONN049_2 0x26a8 +#define AFE_CONN049_4 0x26b0 +#define AFE_CONN049_5 0x26b4 +#define AFE_CONN049_6 0x26b8 +#define AFE_CONN049_7 0x26bc +#define AFE_CONN050_0 0x26c0 +#define AFE_CONN050_1 0x26c4 +#define AFE_CONN050_2 0x26c8 +#define AFE_CONN050_4 0x26d0 +#define AFE_CONN050_5 0x26d4 +#define AFE_CONN050_6 0x26d8 +#define AFE_CONN050_7 0x26dc +#define AFE_CONN051_0 0x26e0 +#define AFE_CONN051_1 0x26e4 +#define AFE_CONN051_2 0x26e8 +#define AFE_CONN051_4 0x26f0 +#define AFE_CONN051_5 0x26f4 +#define AFE_CONN051_6 0x26f8 +#define AFE_CONN051_7 0x26fc +#define AFE_CONN052_0 0x2700 +#define AFE_CONN052_1 0x2704 +#define AFE_CONN052_2 0x2708 +#define AFE_CONN052_4 0x2710 +#define AFE_CONN052_5 0x2714 +#define AFE_CONN052_6 0x2718 +#define AFE_CONN052_7 0x271c +#define AFE_CONN053_0 0x2720 +#define AFE_CONN053_1 0x2724 +#define AFE_CONN053_2 0x2728 +#define AFE_CONN053_4 0x2730 +#define AFE_CONN053_5 0x2734 +#define AFE_CONN053_6 0x2738 +#define AFE_CONN053_7 0x273c +#define AFE_CONN054_0 0x2740 +#define AFE_CONN054_1 0x2744 +#define AFE_CONN054_2 0x2748 +#define AFE_CONN054_4 0x2750 +#define AFE_CONN054_5 0x2754 +#define AFE_CONN054_6 0x2758 +#define AFE_CONN054_7 0x275c +#define AFE_CONN055_0 0x2760 +#define AFE_CONN055_1 0x2764 +#define AFE_CONN055_2 0x2768 +#define AFE_CONN055_4 0x2770 +#define AFE_CONN055_5 0x2774 +#define AFE_CONN055_6 0x2778 +#define AFE_CONN055_7 0x277c +#define AFE_CONN056_0 0x2780 +#define AFE_CONN056_1 0x2784 +#define AFE_CONN056_2 0x2788 +#define AFE_CONN056_4 0x2790 +#define AFE_CONN056_5 0x2794 +#define AFE_CONN056_6 0x2798 +#define AFE_CONN056_7 0x279c +#define AFE_CONN057_0 0x27a0 +#define AFE_CONN057_1 0x27a4 +#define AFE_CONN057_2 0x27a8 +#define AFE_CONN057_4 0x27b0 +#define AFE_CONN057_5 0x27b4 +#define AFE_CONN057_6 0x27b8 +#define AFE_CONN057_7 0x27bc +#define AFE_CONN058_0 0x27c0 +#define AFE_CONN058_1 0x27c4 +#define AFE_CONN058_2 0x27c8 +#define AFE_CONN058_4 0x27d0 +#define AFE_CONN058_5 0x27d4 +#define AFE_CONN058_6 0x27d8 +#define AFE_CONN058_7 0x27dc +#define AFE_CONN059_0 0x27e0 +#define AFE_CONN059_1 0x27e4 +#define AFE_CONN059_2 0x27e8 +#define AFE_CONN059_4 0x27f0 +#define AFE_CONN059_5 0x27f4 +#define AFE_CONN059_6 0x27f8 +#define AFE_CONN059_7 0x27fc +#define AFE_CONN060_0 0x2800 +#define AFE_CONN060_1 0x2804 +#define AFE_CONN060_2 0x2808 +#define AFE_CONN060_4 0x2810 +#define AFE_CONN060_5 0x2814 +#define AFE_CONN060_6 0x2818 +#define AFE_CONN060_7 0x281c +#define AFE_CONN061_0 0x2820 +#define AFE_CONN061_1 0x2824 +#define AFE_CONN061_2 0x2828 +#define AFE_CONN061_4 0x2830 +#define AFE_CONN061_5 0x2834 +#define AFE_CONN061_6 0x2838 +#define AFE_CONN061_7 0x283c +#define AFE_CONN062_0 0x2840 +#define AFE_CONN062_1 0x2844 +#define AFE_CONN062_2 0x2848 +#define AFE_CONN062_4 0x2850 +#define AFE_CONN062_5 0x2854 +#define AFE_CONN062_6 0x2858 +#define AFE_CONN062_7 0x285c +#define AFE_CONN063_0 0x2860 +#define AFE_CONN063_1 0x2864 +#define AFE_CONN063_2 0x2868 +#define AFE_CONN063_4 0x2870 +#define AFE_CONN063_5 0x2874 +#define AFE_CONN063_6 0x2878 +#define AFE_CONN063_7 0x287c +#define AFE_CONN064_0 0x2880 +#define AFE_CONN064_1 0x2884 +#define AFE_CONN064_2 0x2888 +#define AFE_CONN064_4 0x2890 +#define AFE_CONN064_5 0x2894 +#define AFE_CONN064_6 0x2898 +#define AFE_CONN064_7 0x289c +#define AFE_CONN065_0 0x28a0 +#define AFE_CONN065_1 0x28a4 +#define AFE_CONN065_2 0x28a8 +#define AFE_CONN065_4 0x28b0 +#define AFE_CONN065_5 0x28b4 +#define AFE_CONN065_6 0x28b8 +#define AFE_CONN065_7 0x28bc +#define AFE_CONN066_0 0x28c0 +#define AFE_CONN066_1 0x28c4 +#define AFE_CONN066_2 0x28c8 +#define AFE_CONN066_4 0x28d0 +#define AFE_CONN066_5 0x28d4 +#define AFE_CONN066_6 0x28d8 +#define AFE_CONN066_7 0x28dc +#define AFE_CONN067_0 0x28e0 +#define AFE_CONN067_1 0x28e4 +#define AFE_CONN067_2 0x28e8 +#define AFE_CONN067_4 0x28f0 +#define AFE_CONN067_5 0x28f4 +#define AFE_CONN067_6 0x28f8 +#define AFE_CONN067_7 0x28fc +#define AFE_CONN068_0 0x2900 +#define AFE_CONN068_1 0x2904 +#define AFE_CONN068_2 0x2908 +#define AFE_CONN068_4 0x2910 +#define AFE_CONN068_5 0x2914 +#define AFE_CONN068_6 0x2918 +#define AFE_CONN068_7 0x291c +#define AFE_CONN069_0 0x2920 +#define AFE_CONN069_1 0x2924 +#define AFE_CONN069_2 0x2928 +#define AFE_CONN069_4 0x2930 +#define AFE_CONN069_5 0x2934 +#define AFE_CONN069_6 0x2938 +#define AFE_CONN069_7 0x293c +#define AFE_CONN070_0 0x2940 +#define AFE_CONN070_1 0x2944 +#define AFE_CONN070_2 0x2948 +#define AFE_CONN070_4 0x2950 +#define AFE_CONN070_5 0x2954 +#define AFE_CONN070_6 0x2958 +#define AFE_CONN070_7 0x295c +#define AFE_CONN071_0 0x2960 +#define AFE_CONN071_1 0x2964 +#define AFE_CONN071_2 0x2968 +#define AFE_CONN071_4 0x2970 +#define AFE_CONN071_5 0x2974 +#define AFE_CONN071_6 0x2978 +#define AFE_CONN071_7 0x297c +#define AFE_CONN072_0 0x2980 +#define AFE_CONN072_1 0x2984 +#define AFE_CONN072_2 0x2988 +#define AFE_CONN072_4 0x2990 +#define AFE_CONN072_5 0x2994 +#define AFE_CONN072_6 0x2998 +#define AFE_CONN072_7 0x299c +#define AFE_CONN073_0 0x29a0 +#define AFE_CONN073_1 0x29a4 +#define AFE_CONN073_2 0x29a8 +#define AFE_CONN073_4 0x29b0 +#define AFE_CONN073_5 0x29b4 +#define AFE_CONN073_6 0x29b8 +#define AFE_CONN073_7 0x29bc +#define AFE_CONN074_0 0x29c0 +#define AFE_CONN074_1 0x29c4 +#define AFE_CONN074_2 0x29c8 +#define AFE_CONN074_4 0x29d0 +#define AFE_CONN074_5 0x29d4 +#define AFE_CONN074_6 0x29d8 +#define AFE_CONN074_7 0x29dc +#define AFE_CONN075_0 0x29e0 +#define AFE_CONN075_1 0x29e4 +#define AFE_CONN075_2 0x29e8 +#define AFE_CONN075_4 0x29f0 +#define AFE_CONN075_5 0x29f4 +#define AFE_CONN075_6 0x29f8 +#define AFE_CONN075_7 0x29fc +#define AFE_CONN076_0 0x2a00 +#define AFE_CONN076_1 0x2a04 +#define AFE_CONN076_2 0x2a08 +#define AFE_CONN076_4 0x2a10 +#define AFE_CONN076_5 0x2a14 +#define AFE_CONN076_6 0x2a18 +#define AFE_CONN076_7 0x2a1c +#define AFE_CONN077_0 0x2a20 +#define AFE_CONN077_1 0x2a24 +#define AFE_CONN077_2 0x2a28 +#define AFE_CONN077_4 0x2a30 +#define AFE_CONN077_5 0x2a34 +#define AFE_CONN077_6 0x2a38 +#define AFE_CONN077_7 0x2a3c +#define AFE_CONN078_0 0x2a40 +#define AFE_CONN078_1 0x2a44 +#define AFE_CONN078_2 0x2a48 +#define AFE_CONN078_4 0x2a50 +#define AFE_CONN078_5 0x2a54 +#define AFE_CONN078_6 0x2a58 +#define AFE_CONN078_7 0x2a5c +#define AFE_CONN079_0 0x2a60 +#define AFE_CONN079_1 0x2a64 +#define AFE_CONN079_2 0x2a68 +#define AFE_CONN079_4 0x2a70 +#define AFE_CONN079_5 0x2a74 +#define AFE_CONN079_6 0x2a78 +#define AFE_CONN079_7 0x2a7c +#define AFE_CONN080_0 0x2a80 +#define AFE_CONN080_1 0x2a84 +#define AFE_CONN080_2 0x2a88 +#define AFE_CONN080_4 0x2a90 +#define AFE_CONN080_5 0x2a94 +#define AFE_CONN080_6 0x2a98 +#define AFE_CONN080_7 0x2a9c +#define AFE_CONN081_0 0x2aa0 +#define AFE_CONN081_1 0x2aa4 +#define AFE_CONN081_2 0x2aa8 +#define AFE_CONN081_4 0x2ab0 +#define AFE_CONN081_5 0x2ab4 +#define AFE_CONN081_6 0x2ab8 +#define AFE_CONN081_7 0x2abc +#define AFE_CONN082_0 0x2ac0 +#define AFE_CONN082_1 0x2ac4 +#define AFE_CONN082_2 0x2ac8 +#define AFE_CONN082_4 0x2ad0 +#define AFE_CONN082_5 0x2ad4 +#define AFE_CONN082_6 0x2ad8 +#define AFE_CONN082_7 0x2adc +#define AFE_CONN083_0 0x2ae0 +#define AFE_CONN083_1 0x2ae4 +#define AFE_CONN083_2 0x2ae8 +#define AFE_CONN083_4 0x2af0 +#define AFE_CONN083_5 0x2af4 +#define AFE_CONN083_6 0x2af8 +#define AFE_CONN083_7 0x2afc +#define AFE_CONN084_0 0x2b00 +#define AFE_CONN084_1 0x2b04 +#define AFE_CONN084_2 0x2b08 +#define AFE_CONN084_4 0x2b10 +#define AFE_CONN084_5 0x2b14 +#define AFE_CONN084_6 0x2b18 +#define AFE_CONN084_7 0x2b1c +#define AFE_CONN085_0 0x2b20 +#define AFE_CONN085_1 0x2b24 +#define AFE_CONN085_2 0x2b28 +#define AFE_CONN085_4 0x2b30 +#define AFE_CONN085_5 0x2b34 +#define AFE_CONN085_6 0x2b38 +#define AFE_CONN085_7 0x2b3c +#define AFE_CONN086_0 0x2b40 +#define AFE_CONN086_1 0x2b44 +#define AFE_CONN086_2 0x2b48 +#define AFE_CONN086_4 0x2b50 +#define AFE_CONN086_5 0x2b54 +#define AFE_CONN086_6 0x2b58 +#define AFE_CONN086_7 0x2b5c +#define AFE_CONN087_0 0x2b60 +#define AFE_CONN087_1 0x2b64 +#define AFE_CONN087_2 0x2b68 +#define AFE_CONN087_4 0x2b70 +#define AFE_CONN087_5 0x2b74 +#define AFE_CONN087_6 0x2b78 +#define AFE_CONN087_7 0x2b7c +#define AFE_CONN088_0 0x2b80 +#define AFE_CONN088_1 0x2b84 +#define AFE_CONN088_2 0x2b88 +#define AFE_CONN088_4 0x2b90 +#define AFE_CONN088_5 0x2b94 +#define AFE_CONN088_6 0x2b98 +#define AFE_CONN088_7 0x2b9c +#define AFE_CONN089_0 0x2ba0 +#define AFE_CONN089_1 0x2ba4 +#define AFE_CONN089_2 0x2ba8 +#define AFE_CONN089_4 0x2bb0 +#define AFE_CONN089_5 0x2bb4 +#define AFE_CONN089_6 0x2bb8 +#define AFE_CONN089_7 0x2bbc +#define AFE_CONN090_0 0x2bc0 +#define AFE_CONN090_1 0x2bc4 +#define AFE_CONN090_2 0x2bc8 +#define AFE_CONN090_4 0x2bd0 +#define AFE_CONN090_5 0x2bd4 +#define AFE_CONN090_6 0x2bd8 +#define AFE_CONN090_7 0x2bdc +#define AFE_CONN091_0 0x2be0 +#define AFE_CONN091_1 0x2be4 +#define AFE_CONN091_2 0x2be8 +#define AFE_CONN091_4 0x2bf0 +#define AFE_CONN091_5 0x2bf4 +#define AFE_CONN091_6 0x2bf8 +#define AFE_CONN091_7 0x2bfc +#define AFE_CONN092_0 0x2c00 +#define AFE_CONN092_1 0x2c04 +#define AFE_CONN092_2 0x2c08 +#define AFE_CONN092_4 0x2c10 +#define AFE_CONN092_5 0x2c14 +#define AFE_CONN092_6 0x2c18 +#define AFE_CONN092_7 0x2c1c +#define AFE_CONN093_0 0x2c20 +#define AFE_CONN093_1 0x2c24 +#define AFE_CONN093_2 0x2c28 +#define AFE_CONN093_4 0x2c30 +#define AFE_CONN093_5 0x2c34 +#define AFE_CONN093_6 0x2c38 +#define AFE_CONN093_7 0x2c3c +#define AFE_CONN094_0 0x2c40 +#define AFE_CONN094_1 0x2c44 +#define AFE_CONN094_2 0x2c48 +#define AFE_CONN094_4 0x2c50 +#define AFE_CONN094_5 0x2c54 +#define AFE_CONN094_6 0x2c58 +#define AFE_CONN094_7 0x2c5c +#define AFE_CONN095_0 0x2c60 +#define AFE_CONN095_1 0x2c64 +#define AFE_CONN095_2 0x2c68 +#define AFE_CONN095_4 0x2c70 +#define AFE_CONN095_5 0x2c74 +#define AFE_CONN095_6 0x2c78 +#define AFE_CONN095_7 0x2c7c +#define AFE_CONN096_0 0x2c80 +#define AFE_CONN096_1 0x2c84 +#define AFE_CONN096_2 0x2c88 +#define AFE_CONN096_4 0x2c90 +#define AFE_CONN096_5 0x2c94 +#define AFE_CONN096_6 0x2c98 +#define AFE_CONN096_7 0x2c9c +#define AFE_CONN097_0 0x2ca0 +#define AFE_CONN097_1 0x2ca4 +#define AFE_CONN097_2 0x2ca8 +#define AFE_CONN097_4 0x2cb0 +#define AFE_CONN097_5 0x2cb4 +#define AFE_CONN097_6 0x2cb8 +#define AFE_CONN097_7 0x2cbc +#define AFE_CONN098_0 0x2cc0 +#define AFE_CONN098_1 0x2cc4 +#define AFE_CONN098_2 0x2cc8 +#define AFE_CONN098_4 0x2cd0 +#define AFE_CONN098_5 0x2cd4 +#define AFE_CONN098_6 0x2cd8 +#define AFE_CONN098_7 0x2cdc +#define AFE_CONN099_0 0x2ce0 +#define AFE_CONN099_1 0x2ce4 +#define AFE_CONN099_2 0x2ce8 +#define AFE_CONN099_4 0x2cf0 +#define AFE_CONN099_5 0x2cf4 +#define AFE_CONN099_6 0x2cf8 +#define AFE_CONN099_7 0x2cfc +#define AFE_CONN100_0 0x2d00 +#define AFE_CONN100_1 0x2d04 +#define AFE_CONN100_2 0x2d08 +#define AFE_CONN100_4 0x2d10 +#define AFE_CONN100_5 0x2d14 +#define AFE_CONN100_6 0x2d18 +#define AFE_CONN100_7 0x2d1c +#define AFE_CONN102_0 0x2d40 +#define AFE_CONN102_1 0x2d44 +#define AFE_CONN102_2 0x2d48 +#define AFE_CONN102_4 0x2d50 +#define AFE_CONN102_5 0x2d54 +#define AFE_CONN102_6 0x2d58 +#define AFE_CONN102_7 0x2d5c +#define AFE_CONN103_0 0x2d60 +#define AFE_CONN103_1 0x2d64 +#define AFE_CONN103_2 0x2d68 +#define AFE_CONN103_4 0x2d70 +#define AFE_CONN103_5 0x2d74 +#define AFE_CONN103_6 0x2d78 +#define AFE_CONN103_7 0x2d7c +#define AFE_CONN104_0 0x2d80 +#define AFE_CONN104_1 0x2d84 +#define AFE_CONN104_2 0x2d88 +#define AFE_CONN104_4 0x2d90 +#define AFE_CONN104_5 0x2d94 +#define AFE_CONN104_6 0x2d98 +#define AFE_CONN104_7 0x2d9c +#define AFE_CONN105_0 0x2da0 +#define AFE_CONN105_1 0x2da4 +#define AFE_CONN105_2 0x2da8 +#define AFE_CONN105_4 0x2db0 +#define AFE_CONN105_5 0x2db4 +#define AFE_CONN105_6 0x2db8 +#define AFE_CONN105_7 0x2dbc +#define AFE_CONN106_0 0x2dc0 +#define AFE_CONN106_1 0x2dc4 +#define AFE_CONN106_2 0x2dc8 +#define AFE_CONN106_4 0x2dd0 +#define AFE_CONN106_5 0x2dd4 +#define AFE_CONN106_6 0x2dd8 +#define AFE_CONN106_7 0x2ddc +#define AFE_CONN108_0 0x2e00 +#define AFE_CONN108_1 0x2e04 +#define AFE_CONN108_2 0x2e08 +#define AFE_CONN108_4 0x2e10 +#define AFE_CONN108_5 0x2e14 +#define AFE_CONN108_6 0x2e18 +#define AFE_CONN108_7 0x2e1c +#define AFE_CONN109_0 0x2e20 +#define AFE_CONN109_1 0x2e24 +#define AFE_CONN109_2 0x2e28 +#define AFE_CONN109_4 0x2e30 +#define AFE_CONN109_5 0x2e34 +#define AFE_CONN109_6 0x2e38 +#define AFE_CONN109_7 0x2e3c +#define AFE_CONN110_0 0x2e40 +#define AFE_CONN110_1 0x2e44 +#define AFE_CONN110_2 0x2e48 +#define AFE_CONN110_4 0x2e50 +#define AFE_CONN110_5 0x2e54 +#define AFE_CONN110_6 0x2e58 +#define AFE_CONN110_7 0x2e5c +#define AFE_CONN111_0 0x2e60 +#define AFE_CONN111_1 0x2e64 +#define AFE_CONN111_2 0x2e68 +#define AFE_CONN111_4 0x2e70 +#define AFE_CONN111_5 0x2e74 +#define AFE_CONN111_6 0x2e78 +#define AFE_CONN111_7 0x2e7c +#define AFE_CONN112_0 0x2e80 +#define AFE_CONN112_1 0x2e84 +#define AFE_CONN112_2 0x2e88 +#define AFE_CONN112_4 0x2e90 +#define AFE_CONN112_5 0x2e94 +#define AFE_CONN112_6 0x2e98 +#define AFE_CONN112_7 0x2e9c +#define AFE_CONN113_0 0x2ea0 +#define AFE_CONN113_1 0x2ea4 +#define AFE_CONN113_2 0x2ea8 +#define AFE_CONN113_4 0x2eb0 +#define AFE_CONN113_5 0x2eb4 +#define AFE_CONN113_6 0x2eb8 +#define AFE_CONN113_7 0x2ebc +#define AFE_CONN114_0 0x2ec0 +#define AFE_CONN114_1 0x2ec4 +#define AFE_CONN114_2 0x2ec8 +#define AFE_CONN114_4 0x2ed0 +#define AFE_CONN114_5 0x2ed4 +#define AFE_CONN114_6 0x2ed8 +#define AFE_CONN114_7 0x2edc +#define AFE_CONN115_0 0x2ee0 +#define AFE_CONN115_1 0x2ee4 +#define AFE_CONN115_2 0x2ee8 +#define AFE_CONN115_4 0x2ef0 +#define AFE_CONN115_5 0x2ef4 +#define AFE_CONN115_6 0x2ef8 +#define AFE_CONN115_7 0x2efc +#define AFE_CONN116_0 0x2f00 +#define AFE_CONN116_1 0x2f04 +#define AFE_CONN116_2 0x2f08 +#define AFE_CONN116_4 0x2f10 +#define AFE_CONN116_5 0x2f14 +#define AFE_CONN116_6 0x2f18 +#define AFE_CONN116_7 0x2f1c +#define AFE_CONN117_0 0x2f20 +#define AFE_CONN117_1 0x2f24 +#define AFE_CONN117_2 0x2f28 +#define AFE_CONN117_4 0x2f30 +#define AFE_CONN117_5 0x2f34 +#define AFE_CONN117_6 0x2f38 +#define AFE_CONN117_7 0x2f3c +#define AFE_CONN118_0 0x2f40 +#define AFE_CONN118_1 0x2f44 +#define AFE_CONN118_2 0x2f48 +#define AFE_CONN118_4 0x2f50 +#define AFE_CONN118_5 0x2f54 +#define AFE_CONN118_6 0x2f58 +#define AFE_CONN118_7 0x2f5c +#define AFE_CONN119_0 0x2f60 +#define AFE_CONN119_1 0x2f64 +#define AFE_CONN119_2 0x2f68 +#define AFE_CONN119_4 0x2f70 +#define AFE_CONN119_5 0x2f74 +#define AFE_CONN119_6 0x2f78 +#define AFE_CONN119_7 0x2f7c +#define AFE_CONN120_0 0x2f80 +#define AFE_CONN120_1 0x2f84 +#define AFE_CONN120_2 0x2f88 +#define AFE_CONN120_4 0x2f90 +#define AFE_CONN120_5 0x2f94 +#define AFE_CONN120_6 0x2f98 +#define AFE_CONN120_7 0x2f9c +#define AFE_CONN121_0 0x2fa0 +#define AFE_CONN121_1 0x2fa4 +#define AFE_CONN121_2 0x2fa8 +#define AFE_CONN121_4 0x2fb0 +#define AFE_CONN121_5 0x2fb4 +#define AFE_CONN121_6 0x2fb8 +#define AFE_CONN121_7 0x2fbc +#define AFE_CONN122_0 0x2fc0 +#define AFE_CONN122_1 0x2fc4 +#define AFE_CONN122_2 0x2fc8 +#define AFE_CONN122_4 0x2fd0 +#define AFE_CONN122_5 0x2fd4 +#define AFE_CONN122_6 0x2fd8 +#define AFE_CONN122_7 0x2fdc +#define AFE_CONN123_0 0x2fe0 +#define AFE_CONN123_1 0x2fe4 +#define AFE_CONN123_2 0x2fe8 +#define AFE_CONN123_4 0x2ff0 +#define AFE_CONN123_5 0x2ff4 +#define AFE_CONN123_6 0x2ff8 +#define AFE_CONN123_7 0x2ffc +#define AFE_CONN124_0 0x3000 +#define AFE_CONN124_1 0x3004 +#define AFE_CONN124_2 0x3008 +#define AFE_CONN124_4 0x3010 +#define AFE_CONN124_5 0x3014 +#define AFE_CONN124_6 0x3018 +#define AFE_CONN124_7 0x301c +#define AFE_CONN125_0 0x3020 +#define AFE_CONN125_1 0x3024 +#define AFE_CONN125_2 0x3028 +#define AFE_CONN125_4 0x3030 +#define AFE_CONN125_5 0x3034 +#define AFE_CONN125_6 0x3038 +#define AFE_CONN125_7 0x303c +#define AFE_CONN126_0 0x3040 +#define AFE_CONN126_1 0x3044 +#define AFE_CONN126_2 0x3048 +#define AFE_CONN126_4 0x3050 +#define AFE_CONN126_5 0x3054 +#define AFE_CONN126_6 0x3058 +#define AFE_CONN126_7 0x305c +#define AFE_CONN127_0 0x3060 +#define AFE_CONN127_1 0x3064 +#define AFE_CONN127_2 0x3068 +#define AFE_CONN127_4 0x3070 +#define AFE_CONN127_5 0x3074 +#define AFE_CONN127_6 0x3078 +#define AFE_CONN127_7 0x307c +#define AFE_CONN128_0 0x3080 +#define AFE_CONN128_1 0x3084 +#define AFE_CONN128_2 0x3088 +#define AFE_CONN128_4 0x3090 +#define AFE_CONN128_5 0x3094 +#define AFE_CONN128_6 0x3098 +#define AFE_CONN128_7 0x309c +#define AFE_CONN129_0 0x30a0 +#define AFE_CONN129_1 0x30a4 +#define AFE_CONN129_2 0x30a8 +#define AFE_CONN129_4 0x30b0 +#define AFE_CONN129_5 0x30b4 +#define AFE_CONN129_6 0x30b8 +#define AFE_CONN129_7 0x30bc +#define AFE_CONN130_0 0x30c0 +#define AFE_CONN130_1 0x30c4 +#define AFE_CONN130_2 0x30c8 +#define AFE_CONN130_4 0x30d0 +#define AFE_CONN130_5 0x30d4 +#define AFE_CONN130_6 0x30d8 +#define AFE_CONN130_7 0x30dc +#define AFE_CONN131_0 0x30e0 +#define AFE_CONN131_1 0x30e4 +#define AFE_CONN131_2 0x30e8 +#define AFE_CONN131_4 0x30f0 +#define AFE_CONN131_5 0x30f4 +#define AFE_CONN131_6 0x30f8 +#define AFE_CONN131_7 0x30fc +#define AFE_CONN132_0 0x3100 +#define AFE_CONN132_1 0x3104 +#define AFE_CONN132_2 0x3108 +#define AFE_CONN132_4 0x3110 +#define AFE_CONN132_5 0x3114 +#define AFE_CONN132_6 0x3118 +#define AFE_CONN132_7 0x311c +#define AFE_CONN133_0 0x3120 +#define AFE_CONN133_1 0x3124 +#define AFE_CONN133_2 0x3128 +#define AFE_CONN133_4 0x3130 +#define AFE_CONN133_5 0x3134 +#define AFE_CONN133_6 0x3138 +#define AFE_CONN133_7 0x313c +#define AFE_CONN134_0 0x3140 +#define AFE_CONN134_1 0x3144 +#define AFE_CONN134_2 0x3148 +#define AFE_CONN134_4 0x3150 +#define AFE_CONN134_5 0x3154 +#define AFE_CONN134_6 0x3158 +#define AFE_CONN134_7 0x315c +#define AFE_CONN135_0 0x3160 +#define AFE_CONN135_1 0x3164 +#define AFE_CONN135_2 0x3168 +#define AFE_CONN135_4 0x3170 +#define AFE_CONN135_5 0x3174 +#define AFE_CONN135_6 0x3178 +#define AFE_CONN135_7 0x317c +#define AFE_CONN136_0 0x3180 +#define AFE_CONN136_1 0x3184 +#define AFE_CONN136_2 0x3188 +#define AFE_CONN136_4 0x3190 +#define AFE_CONN136_5 0x3194 +#define AFE_CONN136_6 0x3198 +#define AFE_CONN136_7 0x319c +#define AFE_CONN137_0 0x31a0 +#define AFE_CONN137_1 0x31a4 +#define AFE_CONN137_2 0x31a8 +#define AFE_CONN137_4 0x31b0 +#define AFE_CONN137_5 0x31b4 +#define AFE_CONN137_6 0x31b8 +#define AFE_CONN137_7 0x31bc +#define AFE_CONN138_0 0x31c0 +#define AFE_CONN138_1 0x31c4 +#define AFE_CONN138_2 0x31c8 +#define AFE_CONN138_4 0x31d0 +#define AFE_CONN138_5 0x31d4 +#define AFE_CONN138_6 0x31d8 +#define AFE_CONN138_7 0x31dc +#define AFE_CONN139_0 0x31e0 +#define AFE_CONN139_1 0x31e4 +#define AFE_CONN139_2 0x31e8 +#define AFE_CONN139_4 0x31f0 +#define AFE_CONN139_5 0x31f4 +#define AFE_CONN139_6 0x31f8 +#define AFE_CONN139_7 0x31fc +#define AFE_CONN148_0 0x3300 +#define AFE_CONN148_1 0x3304 +#define AFE_CONN148_2 0x3308 +#define AFE_CONN148_4 0x3310 +#define AFE_CONN148_5 0x3314 +#define AFE_CONN148_6 0x3318 +#define AFE_CONN148_7 0x331c +#define AFE_CONN149_0 0x3320 +#define AFE_CONN149_1 0x3324 +#define AFE_CONN149_2 0x3328 +#define AFE_CONN149_4 0x3330 +#define AFE_CONN149_5 0x3334 +#define AFE_CONN149_6 0x3338 +#define AFE_CONN149_7 0x333c +#define AFE_CONN180_0 0x3700 +#define AFE_CONN180_1 0x3704 +#define AFE_CONN180_2 0x3708 +#define AFE_CONN180_4 0x3710 +#define AFE_CONN180_5 0x3714 +#define AFE_CONN180_6 0x3718 +#define AFE_CONN180_7 0x371c +#define AFE_CONN181_0 0x3720 +#define AFE_CONN181_1 0x3724 +#define AFE_CONN181_2 0x3728 +#define AFE_CONN181_4 0x3730 +#define AFE_CONN181_5 0x3734 +#define AFE_CONN181_6 0x3738 +#define AFE_CONN181_7 0x373c +#define AFE_CONN182_0 0x3740 +#define AFE_CONN182_1 0x3744 +#define AFE_CONN182_2 0x3748 +#define AFE_CONN182_4 0x3750 +#define AFE_CONN182_5 0x3754 +#define AFE_CONN182_6 0x3758 +#define AFE_CONN182_7 0x375c +#define AFE_CONN183_0 0x3760 +#define AFE_CONN183_1 0x3764 +#define AFE_CONN183_2 0x3768 +#define AFE_CONN183_4 0x3770 +#define AFE_CONN183_5 0x3774 +#define AFE_CONN183_6 0x3778 +#define AFE_CONN183_7 0x377c +#define AFE_CONN184_0 0x3780 +#define AFE_CONN184_1 0x3784 +#define AFE_CONN184_2 0x3788 +#define AFE_CONN184_4 0x3790 +#define AFE_CONN184_5 0x3794 +#define AFE_CONN184_6 0x3798 +#define AFE_CONN184_7 0x379c +#define AFE_CONN185_0 0x37a0 +#define AFE_CONN185_1 0x37a4 +#define AFE_CONN185_2 0x37a8 +#define AFE_CONN185_4 0x37b0 +#define AFE_CONN185_5 0x37b4 +#define AFE_CONN185_6 0x37b8 +#define AFE_CONN185_7 0x37bc +#define AFE_CONN186_0 0x37c0 +#define AFE_CONN186_1 0x37c4 +#define AFE_CONN186_2 0x37c8 +#define AFE_CONN186_4 0x37d0 +#define AFE_CONN186_5 0x37d4 +#define AFE_CONN186_6 0x37d8 +#define AFE_CONN186_7 0x37dc +#define AFE_CONN187_0 0x37e0 +#define AFE_CONN187_1 0x37e4 +#define AFE_CONN187_2 0x37e8 +#define AFE_CONN187_4 0x37f0 +#define AFE_CONN187_5 0x37f4 +#define AFE_CONN187_6 0x37f8 +#define AFE_CONN187_7 0x37fc +#define AFE_CONN188_0 0x3800 +#define AFE_CONN188_1 0x3804 +#define AFE_CONN188_2 0x3808 +#define AFE_CONN188_4 0x3810 +#define AFE_CONN188_5 0x3814 +#define AFE_CONN188_6 0x3818 +#define AFE_CONN188_7 0x381c +#define AFE_CONN189_0 0x3820 +#define AFE_CONN189_1 0x3824 +#define AFE_CONN189_2 0x3828 +#define AFE_CONN189_4 0x3830 +#define AFE_CONN189_5 0x3834 +#define AFE_CONN189_6 0x3838 +#define AFE_CONN189_7 0x383c +#define AFE_CONN190_0 0x3840 +#define AFE_CONN190_1 0x3844 +#define AFE_CONN190_2 0x3848 +#define AFE_CONN190_4 0x3850 +#define AFE_CONN190_5 0x3854 +#define AFE_CONN190_6 0x3858 +#define AFE_CONN190_7 0x385c +#define AFE_CONN191_0 0x3860 +#define AFE_CONN191_1 0x3864 +#define AFE_CONN191_2 0x3868 +#define AFE_CONN191_4 0x3870 +#define AFE_CONN191_5 0x3874 +#define AFE_CONN191_6 0x3878 +#define AFE_CONN191_7 0x387c +#define AFE_CONN192_0 0x3880 +#define AFE_CONN192_1 0x3884 +#define AFE_CONN192_2 0x3888 +#define AFE_CONN192_4 0x3890 +#define AFE_CONN192_5 0x3894 +#define AFE_CONN192_6 0x3898 +#define AFE_CONN192_7 0x389c +#define AFE_CONN193_0 0x38a0 +#define AFE_CONN193_1 0x38a4 +#define AFE_CONN193_2 0x38a8 +#define AFE_CONN193_4 0x38b0 +#define AFE_CONN193_5 0x38b4 +#define AFE_CONN193_6 0x38b8 +#define AFE_CONN193_7 0x38bc +#define AFE_CONN194_0 0x38c0 +#define AFE_CONN194_1 0x38c4 +#define AFE_CONN194_2 0x38c8 +#define AFE_CONN194_4 0x38d0 +#define AFE_CONN194_5 0x38d4 +#define AFE_CONN194_6 0x38d8 +#define AFE_CONN194_7 0x38dc +#define AFE_CONN195_0 0x38e0 +#define AFE_CONN195_1 0x38e4 +#define AFE_CONN195_2 0x38e8 +#define AFE_CONN195_4 0x38f0 +#define AFE_CONN195_5 0x38f4 +#define AFE_CONN195_6 0x38f8 +#define AFE_CONN195_7 0x38fc +#define AFE_CONN196_0 0x3900 +#define AFE_CONN196_1 0x3904 +#define AFE_CONN196_2 0x3908 +#define AFE_CONN196_4 0x3910 +#define AFE_CONN196_5 0x3914 +#define AFE_CONN196_6 0x3918 +#define AFE_CONN196_7 0x391c +#define AFE_CONN197_0 0x3920 +#define AFE_CONN197_1 0x3924 +#define AFE_CONN197_2 0x3928 +#define AFE_CONN197_4 0x3930 +#define AFE_CONN197_5 0x3934 +#define AFE_CONN197_6 0x3938 +#define AFE_CONN197_7 0x393c +#define AFE_CONN198_0 0x3940 +#define AFE_CONN198_1 0x3944 +#define AFE_CONN198_2 0x3948 +#define AFE_CONN198_4 0x3950 +#define AFE_CONN198_5 0x3954 +#define AFE_CONN198_6 0x3958 +#define AFE_CONN198_7 0x395c +#define AFE_CONN199_0 0x3960 +#define AFE_CONN199_1 0x3964 +#define AFE_CONN199_2 0x3968 +#define AFE_CONN199_4 0x3970 +#define AFE_CONN199_5 0x3974 +#define AFE_CONN199_6 0x3978 +#define AFE_CONN199_7 0x397c +#define AFE_CONN200_0 0x3980 +#define AFE_CONN200_1 0x3984 +#define AFE_CONN200_2 0x3988 +#define AFE_CONN200_4 0x3990 +#define AFE_CONN200_5 0x3994 +#define AFE_CONN200_6 0x3998 +#define AFE_CONN200_7 0x399c +#define AFE_CONN201_0 0x39a0 +#define AFE_CONN201_1 0x39a4 +#define AFE_CONN201_2 0x39a8 +#define AFE_CONN201_4 0x39b0 +#define AFE_CONN201_5 0x39b4 +#define AFE_CONN201_6 0x39b8 +#define AFE_CONN201_7 0x39bc +#define AFE_CONN202_0 0x39c0 +#define AFE_CONN202_1 0x39c4 +#define AFE_CONN202_2 0x39c8 +#define AFE_CONN202_4 0x39d0 +#define AFE_CONN202_5 0x39d4 +#define AFE_CONN202_6 0x39d8 +#define AFE_CONN202_7 0x39dc +#define AFE_CONN203_0 0x39e0 +#define AFE_CONN203_1 0x39e4 +#define AFE_CONN203_2 0x39e8 +#define AFE_CONN203_4 0x39f0 +#define AFE_CONN203_5 0x39f4 +#define AFE_CONN203_6 0x39f8 +#define AFE_CONN203_7 0x39fc +#define AFE_CONN204_0 0x3a00 +#define AFE_CONN204_1 0x3a04 +#define AFE_CONN204_2 0x3a08 +#define AFE_CONN204_4 0x3a10 +#define AFE_CONN204_5 0x3a14 +#define AFE_CONN204_6 0x3a18 +#define AFE_CONN204_7 0x3a1c +#define AFE_CONN205_0 0x3a20 +#define AFE_CONN205_1 0x3a24 +#define AFE_CONN205_2 0x3a28 +#define AFE_CONN205_4 0x3a30 +#define AFE_CONN205_5 0x3a34 +#define AFE_CONN205_6 0x3a38 +#define AFE_CONN205_7 0x3a3c +#define AFE_CONN206_0 0x3a40 +#define AFE_CONN206_1 0x3a44 +#define AFE_CONN206_2 0x3a48 +#define AFE_CONN206_4 0x3a50 +#define AFE_CONN206_5 0x3a54 +#define AFE_CONN206_6 0x3a58 +#define AFE_CONN206_7 0x3a5c +#define AFE_CONN207_0 0x3a60 +#define AFE_CONN207_1 0x3a64 +#define AFE_CONN207_2 0x3a68 +#define AFE_CONN207_4 0x3a70 +#define AFE_CONN207_5 0x3a74 +#define AFE_CONN207_6 0x3a78 +#define AFE_CONN207_7 0x3a7c +#define AFE_CONN208_0 0x3a80 +#define AFE_CONN208_1 0x3a84 +#define AFE_CONN208_2 0x3a88 +#define AFE_CONN208_4 0x3a90 +#define AFE_CONN208_5 0x3a94 +#define AFE_CONN208_6 0x3a98 +#define AFE_CONN208_7 0x3a9c +#define AFE_CONN209_0 0x3aa0 +#define AFE_CONN209_1 0x3aa4 +#define AFE_CONN209_2 0x3aa8 +#define AFE_CONN209_4 0x3ab0 +#define AFE_CONN209_5 0x3ab4 +#define AFE_CONN209_6 0x3ab8 +#define AFE_CONN209_7 0x3abc +#define AFE_CONN210_0 0x3ac0 +#define AFE_CONN210_1 0x3ac4 +#define AFE_CONN210_2 0x3ac8 +#define AFE_CONN210_4 0x3ad0 +#define AFE_CONN210_5 0x3ad4 +#define AFE_CONN210_6 0x3ad8 +#define AFE_CONN210_7 0x3adc +#define AFE_CONN211_0 0x3ae0 +#define AFE_CONN211_1 0x3ae4 +#define AFE_CONN211_2 0x3ae8 +#define AFE_CONN211_4 0x3af0 +#define AFE_CONN211_5 0x3af4 +#define AFE_CONN211_6 0x3af8 +#define AFE_CONN211_7 0x3afc +#define AFE_CONN_MON_CFG 0x4080 +#define AFE_CONN_MON0 0x4084 +#define AFE_CONN_MON1 0x4088 +#define AFE_CONN_MON2 0x408c +#define AFE_CONN_MON3 0x4090 +#define AFE_CONN_MON4 0x4094 +#define AFE_CONN_MON5 0x4098 +#define AFE_CONN_RS_0 0x40a0 +#define AFE_CONN_RS_1 0x40a4 +#define AFE_CONN_RS_2 0x40a8 +#define AFE_CONN_RS_3 0x40ac +#define AFE_CONN_RS_4 0x40b0 +#define AFE_CONN_RS_5 0x40b4 +#define AFE_CONN_RS_6 0x40b8 +#define AFE_CONN_DI_0 0x40c0 +#define AFE_CONN_DI_1 0x40c4 +#define AFE_CONN_DI_2 0x40c8 +#define AFE_CONN_DI_3 0x40cc +#define AFE_CONN_DI_4 0x40d0 +#define AFE_CONN_DI_5 0x40d4 +#define AFE_CONN_DI_6 0x40d8 +#define AFE_CONN_16BIT_0 0x40e0 +#define AFE_CONN_16BIT_1 0x40e4 +#define AFE_CONN_16BIT_2 0x40e8 +#define AFE_CONN_16BIT_3 0x40ec +#define AFE_CONN_16BIT_4 0x40f0 +#define AFE_CONN_16BIT_5 0x40f4 +#define AFE_CONN_16BIT_6 0x40f8 +#define AFE_CONN_24BIT_0 0x4100 +#define AFE_CONN_24BIT_1 0x4104 +#define AFE_CONN_24BIT_2 0x4108 +#define AFE_CONN_24BIT_3 0x410c +#define AFE_CONN_24BIT_4 0x4110 +#define AFE_CONN_24BIT_5 0x4114 +#define AFE_CONN_24BIT_6 0x4118 +#define AFE_CBIP_CFG0 0x4380 +#define AFE_CBIP_SLV_DECODER_MON0 0x4384 +#define AFE_CBIP_SLV_DECODER_MON1 0x4388 +#define AFE_CBIP_SLV_MUX_MON_CFG 0x438c +#define AFE_CBIP_SLV_MUX_MON0 0x4390 +#define AFE_CBIP_SLV_MUX_MON1 0x4394 +#define AFE_MEMIF_CON0 0x4400 +#define AFE_MEMIF_ONE_HEART 0x4420 +#define AFE_DL0_BASE_MSB 0x4440 +#define AFE_DL0_BASE 0x4444 +#define AFE_DL0_CUR_MSB 0x4448 +#define AFE_DL0_CUR 0x444c +#define AFE_DL0_END_MSB 0x4450 +#define AFE_DL0_END 0x4454 +#define AFE_DL0_RCH_MON 0x4458 +#define AFE_DL0_LCH_MON 0x445c +#define AFE_DL0_CON0 0x4460 +#define AFE_DL0_MON0 0x4464 +#define AFE_DL1_BASE_MSB 0x4470 +#define AFE_DL1_BASE 0x4474 +#define AFE_DL1_CUR_MSB 0x4478 +#define AFE_DL1_CUR 0x447c +#define AFE_DL1_END_MSB 0x4480 +#define AFE_DL1_END 0x4484 +#define AFE_DL1_RCH_MON 0x4488 +#define AFE_DL1_LCH_MON 0x448c +#define AFE_DL1_CON0 0x4490 +#define AFE_DL1_MON0 0x4494 +#define AFE_DL2_BASE_MSB 0x44a0 +#define AFE_DL2_BASE 0x44a4 +#define AFE_DL2_CUR_MSB 0x44a8 +#define AFE_DL2_CUR 0x44ac +#define AFE_DL2_END_MSB 0x44b0 +#define AFE_DL2_END 0x44b4 +#define AFE_DL2_RCH_MON 0x44b8 +#define AFE_DL2_LCH_MON 0x44bc +#define AFE_DL2_CON0 0x44c0 +#define AFE_DL2_MON0 0x44c4 +#define AFE_DL3_BASE_MSB 0x44d0 +#define AFE_DL3_BASE 0x44d4 +#define AFE_DL3_CUR_MSB 0x44d8 +#define AFE_DL3_CUR 0x44dc +#define AFE_DL3_END_MSB 0x44e0 +#define AFE_DL3_END 0x44e4 +#define AFE_DL3_RCH_MON 0x44e8 +#define AFE_DL3_LCH_MON 0x44ec +#define AFE_DL3_CON0 0x44f0 +#define AFE_DL3_MON0 0x44f4 +#define AFE_DL4_BASE_MSB 0x4500 +#define AFE_DL4_BASE 0x4504 +#define AFE_DL4_CUR_MSB 0x4508 +#define AFE_DL4_CUR 0x450c +#define AFE_DL4_END_MSB 0x4510 +#define AFE_DL4_END 0x4514 +#define AFE_DL4_RCH_MON 0x4518 +#define AFE_DL4_LCH_MON 0x451c +#define AFE_DL4_CON0 0x4520 +#define AFE_DL4_MON0 0x4524 +#define AFE_DL5_BASE_MSB 0x4530 +#define AFE_DL5_BASE 0x4534 +#define AFE_DL5_CUR_MSB 0x4538 +#define AFE_DL5_CUR 0x453c +#define AFE_DL5_END_MSB 0x4540 +#define AFE_DL5_END 0x4544 +#define AFE_DL5_RCH_MON 0x4548 +#define AFE_DL5_LCH_MON 0x454c +#define AFE_DL5_CON0 0x4550 +#define AFE_DL5_MON0 0x4554 +#define AFE_DL6_BASE_MSB 0x4560 +#define AFE_DL6_BASE 0x4564 +#define AFE_DL6_CUR_MSB 0x4568 +#define AFE_DL6_CUR 0x456c +#define AFE_DL6_END_MSB 0x4570 +#define AFE_DL6_END 0x4574 +#define AFE_DL6_RCH_MON 0x4578 +#define AFE_DL6_LCH_MON 0x457c +#define AFE_DL6_CON0 0x4580 +#define AFE_DL6_MON0 0x4584 +#define AFE_DL7_BASE_MSB 0x4590 +#define AFE_DL7_BASE 0x4594 +#define AFE_DL7_CUR_MSB 0x4598 +#define AFE_DL7_CUR 0x459c +#define AFE_DL7_END_MSB 0x45a0 +#define AFE_DL7_END 0x45a4 +#define AFE_DL7_RCH_MON 0x45a8 +#define AFE_DL7_LCH_MON 0x45ac +#define AFE_DL7_CON0 0x45b0 +#define AFE_DL7_MON0 0x45b4 +#define AFE_DL8_BASE_MSB 0x45c0 +#define AFE_DL8_BASE 0x45c4 +#define AFE_DL8_CUR_MSB 0x45c8 +#define AFE_DL8_CUR 0x45cc +#define AFE_DL8_END_MSB 0x45d0 +#define AFE_DL8_END 0x45d4 +#define AFE_DL8_RCH_MON 0x45d8 +#define AFE_DL8_LCH_MON 0x45dc +#define AFE_DL8_CON0 0x45e0 +#define AFE_DL8_MON0 0x45e4 +#define AFE_DL_4CH_BASE_MSB 0x45f0 +#define AFE_DL_4CH_BASE 0x45f4 +#define AFE_DL_4CH_CUR_MSB 0x45f8 +#define AFE_DL_4CH_CUR 0x45fc +#define AFE_DL_4CH_END_MSB 0x4600 +#define AFE_DL_4CH_END 0x4604 +#define AFE_DL_4CH_CON0 0x4610 +#define AFE_DL_4CH_MON0 0x4618 +#define AFE_DL_24CH_BASE_MSB 0x4620 +#define AFE_DL_24CH_BASE 0x4624 +#define AFE_DL_24CH_CUR_MSB 0x4628 +#define AFE_DL_24CH_CUR 0x462c +#define AFE_DL_24CH_END_MSB 0x4630 +#define AFE_DL_24CH_END 0x4634 +#define AFE_DL_24CH_CON0 0x4640 +#define AFE_DL_24CH_MON0 0x4648 +#define AFE_DL23_BASE_MSB 0x4680 +#define AFE_DL23_BASE 0x4684 +#define AFE_DL23_CUR_MSB 0x4688 +#define AFE_DL23_CUR 0x468c +#define AFE_DL23_END_MSB 0x4690 +#define AFE_DL23_END 0x4694 +#define AFE_DL23_RCH_MON 0x4698 +#define AFE_DL23_LCH_MON 0x469c +#define AFE_DL23_CON0 0x46a0 +#define AFE_DL23_MON0 0x46a4 +#define AFE_DL24_BASE_MSB 0x46b0 +#define AFE_DL24_BASE 0x46b4 +#define AFE_DL24_CUR_MSB 0x46b8 +#define AFE_DL24_CUR 0x46bc +#define AFE_DL24_END_MSB 0x46c0 +#define AFE_DL24_END 0x46c4 +#define AFE_DL24_RCH_MON 0x46c8 +#define AFE_DL24_LCH_MON 0x46cc +#define AFE_DL24_CON0 0x46d0 +#define AFE_DL24_MON0 0x46d4 +#define AFE_DL25_BASE_MSB 0x46e0 +#define AFE_DL25_BASE 0x46e4 +#define AFE_DL25_CUR_MSB 0x46e8 +#define AFE_DL25_CUR 0x46ec +#define AFE_DL25_END_MSB 0x46f0 +#define AFE_DL25_END 0x46f4 +#define AFE_DL25_RCH_MON 0x46f8 +#define AFE_DL25_LCH_MON 0x46fc +#define AFE_DL25_CON0 0x4700 +#define AFE_DL25_MON0 0x4704 +#define AFE_DL26_BASE_MSB 0x4710 +#define AFE_DL26_BASE 0x4714 +#define AFE_DL26_CUR_MSB 0x4718 +#define AFE_DL26_CUR 0x471c +#define AFE_DL26_END_MSB 0x4720 +#define AFE_DL26_END 0x4724 +#define AFE_DL26_RCH_MON 0x4728 +#define AFE_DL26_LCH_MON 0x472c +#define AFE_DL26_CON0 0x4730 +#define AFE_DL26_MON0 0x4734 +#define AFE_VUL0_BASE_MSB 0x4d60 +#define AFE_VUL0_BASE 0x4d64 +#define AFE_VUL0_CUR_MSB 0x4d68 +#define AFE_VUL0_CUR 0x4d6c +#define AFE_VUL0_END_MSB 0x4d70 +#define AFE_VUL0_END 0x4d74 +#define AFE_VUL0_RCH_MON 0x4d78 +#define AFE_VUL0_LCH_MON 0x4d7c +#define AFE_VUL0_CON0 0x4d80 +#define AFE_VUL0_MON0 0x4d84 +#define AFE_VUL1_BASE_MSB 0x4d90 +#define AFE_VUL1_BASE 0x4d94 +#define AFE_VUL1_CUR_MSB 0x4d98 +#define AFE_VUL1_CUR 0x4d9c +#define AFE_VUL1_END_MSB 0x4da0 +#define AFE_VUL1_END 0x4da4 +#define AFE_VUL1_RCH_MON 0x4da8 +#define AFE_VUL1_LCH_MON 0x4dac +#define AFE_VUL1_CON0 0x4db0 +#define AFE_VUL1_MON0 0x4db4 +#define AFE_VUL2_BASE_MSB 0x4dc0 +#define AFE_VUL2_BASE 0x4dc4 +#define AFE_VUL2_CUR_MSB 0x4dc8 +#define AFE_VUL2_CUR 0x4dcc +#define AFE_VUL2_END_MSB 0x4dd0 +#define AFE_VUL2_END 0x4dd4 +#define AFE_VUL2_RCH_MON 0x4dd8 +#define AFE_VUL2_LCH_MON 0x4ddc +#define AFE_VUL2_CON0 0x4de0 +#define AFE_VUL2_MON0 0x4de4 +#define AFE_VUL3_BASE_MSB 0x4df0 +#define AFE_VUL3_BASE 0x4df4 +#define AFE_VUL3_CUR_MSB 0x4df8 +#define AFE_VUL3_CUR 0x4dfc +#define AFE_VUL3_END_MSB 0x4e00 +#define AFE_VUL3_END 0x4e04 +#define AFE_VUL3_RCH_MON 0x4e08 +#define AFE_VUL3_LCH_MON 0x4e0c +#define AFE_VUL3_CON0 0x4e10 +#define AFE_VUL3_MON0 0x4e14 +#define AFE_VUL4_BASE_MSB 0x4e20 +#define AFE_VUL4_BASE 0x4e24 +#define AFE_VUL4_CUR_MSB 0x4e28 +#define AFE_VUL4_CUR 0x4e2c +#define AFE_VUL4_END_MSB 0x4e30 +#define AFE_VUL4_END 0x4e34 +#define AFE_VUL4_RCH_MON 0x4e38 +#define AFE_VUL4_LCH_MON 0x4e3c +#define AFE_VUL4_CON0 0x4e40 +#define AFE_VUL4_MON0 0x4e44 +#define AFE_VUL5_BASE_MSB 0x4e50 +#define AFE_VUL5_BASE 0x4e54 +#define AFE_VUL5_CUR_MSB 0x4e58 +#define AFE_VUL5_CUR 0x4e5c +#define AFE_VUL5_END_MSB 0x4e60 +#define AFE_VUL5_END 0x4e64 +#define AFE_VUL5_RCH_MON 0x4e68 +#define AFE_VUL5_LCH_MON 0x4e6c +#define AFE_VUL5_CON0 0x4e70 +#define AFE_VUL5_MON0 0x4e74 +#define AFE_VUL6_BASE_MSB 0x4e80 +#define AFE_VUL6_BASE 0x4e84 +#define AFE_VUL6_CUR_MSB 0x4e88 +#define AFE_VUL6_CUR 0x4e8c +#define AFE_VUL6_END_MSB 0x4e90 +#define AFE_VUL6_END 0x4e94 +#define AFE_VUL6_RCH_MON 0x4e98 +#define AFE_VUL6_LCH_MON 0x4e9c +#define AFE_VUL6_CON0 0x4ea0 +#define AFE_VUL6_MON0 0x4ea4 +#define AFE_VUL7_BASE_MSB 0x4eb0 +#define AFE_VUL7_BASE 0x4eb4 +#define AFE_VUL7_CUR_MSB 0x4eb8 +#define AFE_VUL7_CUR 0x4ebc +#define AFE_VUL7_END_MSB 0x4ec0 +#define AFE_VUL7_END 0x4ec4 +#define AFE_VUL7_RCH_MON 0x4ec8 +#define AFE_VUL7_LCH_MON 0x4ecc +#define AFE_VUL7_CON0 0x4ed0 +#define AFE_VUL7_MON0 0x4ed4 +#define AFE_VUL8_BASE_MSB 0x4ee0 +#define AFE_VUL8_BASE 0x4ee4 +#define AFE_VUL8_CUR_MSB 0x4ee8 +#define AFE_VUL8_CUR 0x4eec +#define AFE_VUL8_END_MSB 0x4ef0 +#define AFE_VUL8_END 0x4ef4 +#define AFE_VUL8_RCH_MON 0x4ef8 +#define AFE_VUL8_LCH_MON 0x4efc +#define AFE_VUL8_CON0 0x4f00 +#define AFE_VUL8_MON0 0x4f04 +#define AFE_VUL9_BASE_MSB 0x4f10 +#define AFE_VUL9_BASE 0x4f14 +#define AFE_VUL9_CUR_MSB 0x4f18 +#define AFE_VUL9_CUR 0x4f1c +#define AFE_VUL9_END_MSB 0x4f20 +#define AFE_VUL9_END 0x4f24 +#define AFE_VUL9_RCH_MON 0x4f28 +#define AFE_VUL9_LCH_MON 0x4f2c +#define AFE_VUL9_CON0 0x4f30 +#define AFE_VUL9_MON0 0x4f34 +#define AFE_VUL10_BASE_MSB 0x4f40 +#define AFE_VUL10_BASE 0x4f44 +#define AFE_VUL10_CUR_MSB 0x4f48 +#define AFE_VUL10_CUR 0x4f4c +#define AFE_VUL10_END_MSB 0x4f50 +#define AFE_VUL10_END 0x4f54 +#define AFE_VUL10_RCH_MON 0x4f58 +#define AFE_VUL10_LCH_MON 0x4f5c +#define AFE_VUL10_CON0 0x4f60 +#define AFE_VUL10_MON0 0x4f64 +#define AFE_VUL24_BASE_MSB 0x4fa0 +#define AFE_VUL24_BASE 0x4fa4 +#define AFE_VUL24_CUR_MSB 0x4fa8 +#define AFE_VUL24_CUR 0x4fac +#define AFE_VUL24_END_MSB 0x4fb0 +#define AFE_VUL24_END 0x4fb4 +#define AFE_VUL24_CON0 0x4fb8 +#define AFE_VUL24_MON0 0x4fbc +#define AFE_VUL25_BASE_MSB 0x4fc0 +#define AFE_VUL25_BASE 0x4fc4 +#define AFE_VUL25_CUR_MSB 0x4fc8 +#define AFE_VUL25_CUR 0x4fcc +#define AFE_VUL25_END_MSB 0x4fd0 +#define AFE_VUL25_END 0x4fd4 +#define AFE_VUL25_CON0 0x4fd8 +#define AFE_VUL25_MON0 0x4fdc +#define AFE_VUL26_BASE_MSB 0x4fe0 +#define AFE_VUL26_BASE 0x4fe4 +#define AFE_VUL26_CUR_MSB 0x4fe8 +#define AFE_VUL26_CUR 0x4fec +#define AFE_VUL26_END_MSB 0x4ff0 +#define AFE_VUL26_END 0x4ff4 +#define AFE_VUL26_CON0 0x4ff8 +#define AFE_VUL26_MON0 0x4ffc +#define AFE_VUL_CM0_BASE_MSB 0x51c0 +#define AFE_VUL_CM0_BASE 0x51c4 +#define AFE_VUL_CM0_CUR_MSB 0x51c8 +#define AFE_VUL_CM0_CUR 0x51cc +#define AFE_VUL_CM0_END_MSB 0x51d0 +#define AFE_VUL_CM0_END 0x51d4 +#define AFE_VUL_CM0_CON0 0x51d8 +#define AFE_VUL_CM1_BASE_MSB 0x51e0 +#define AFE_VUL_CM1_BASE 0x51e4 +#define AFE_VUL_CM1_CUR_MSB 0x51e8 +#define AFE_VUL_CM1_CUR 0x51ec +#define AFE_VUL_CM1_END_MSB 0x51f0 +#define AFE_VUL_CM1_END 0x51f4 +#define AFE_VUL_CM1_CON0 0x51f8 +#define AFE_VUL_CM2_BASE_MSB 0x5200 +#define AFE_VUL_CM2_BASE 0x5204 +#define AFE_VUL_CM2_CUR_MSB 0x5208 +#define AFE_VUL_CM2_CUR 0x520c +#define AFE_VUL_CM2_END_MSB 0x5210 +#define AFE_VUL_CM2_END 0x5214 +#define AFE_VUL_CM2_CON0 0x5218 +#define AFE_ETDM_IN0_BASE_MSB 0x5220 +#define AFE_ETDM_IN0_BASE 0x5224 +#define AFE_ETDM_IN0_CUR_MSB 0x5228 +#define AFE_ETDM_IN0_CUR 0x522c +#define AFE_ETDM_IN0_END_MSB 0x5230 +#define AFE_ETDM_IN0_END 0x5234 +#define AFE_ETDM_IN0_CON0 0x5238 +#define AFE_ETDM_IN1_BASE_MSB 0x5240 +#define AFE_ETDM_IN1_BASE 0x5244 +#define AFE_ETDM_IN1_CUR_MSB 0x5248 +#define AFE_ETDM_IN1_CUR 0x524c +#define AFE_ETDM_IN1_END_MSB 0x5250 +#define AFE_ETDM_IN1_END 0x5254 +#define AFE_ETDM_IN1_CON0 0x5258 +#define AFE_ETDM_IN2_BASE_MSB 0x5260 +#define AFE_ETDM_IN2_BASE 0x5264 +#define AFE_ETDM_IN2_CUR_MSB 0x5268 +#define AFE_ETDM_IN2_CUR 0x526c +#define AFE_ETDM_IN2_END_MSB 0x5270 +#define AFE_ETDM_IN2_END 0x5274 +#define AFE_ETDM_IN2_CON0 0x5278 +#define AFE_ETDM_IN3_BASE_MSB 0x5280 +#define AFE_ETDM_IN3_BASE 0x5284 +#define AFE_ETDM_IN3_CUR_MSB 0x5288 +#define AFE_ETDM_IN3_CUR 0x528c +#define AFE_ETDM_IN3_END_MSB 0x5290 +#define AFE_ETDM_IN3_END 0x5294 +#define AFE_ETDM_IN3_CON0 0x5298 +#define AFE_ETDM_IN4_BASE_MSB 0x52a0 +#define AFE_ETDM_IN4_BASE 0x52a4 +#define AFE_ETDM_IN4_CUR_MSB 0x52a8 +#define AFE_ETDM_IN4_CUR 0x52ac +#define AFE_ETDM_IN4_END_MSB 0x52b0 +#define AFE_ETDM_IN4_END 0x52b4 +#define AFE_ETDM_IN4_CON0 0x52b8 +#define AFE_ETDM_IN5_BASE_MSB 0x52c0 +#define AFE_ETDM_IN5_BASE 0x52c4 +#define AFE_ETDM_IN5_CUR_MSB 0x52c8 +#define AFE_ETDM_IN5_CUR 0x52cc +#define AFE_ETDM_IN5_END_MSB 0x52d0 +#define AFE_ETDM_IN5_END 0x52d4 +#define AFE_ETDM_IN5_CON0 0x52d8 +#define AFE_ETDM_IN6_BASE_MSB 0x52e0 +#define AFE_ETDM_IN6_BASE 0x52e4 +#define AFE_ETDM_IN6_CUR_MSB 0x52e8 +#define AFE_ETDM_IN6_CUR 0x52ec +#define AFE_ETDM_IN6_END_MSB 0x52f0 +#define AFE_ETDM_IN6_END 0x52f4 +#define AFE_ETDM_IN6_CON0 0x52f8 +#define AFE_HDMI_OUT_BASE_MSB 0x5360 +#define AFE_HDMI_OUT_BASE 0x5364 +#define AFE_HDMI_OUT_CUR_MSB 0x5368 +#define AFE_HDMI_OUT_CUR 0x536c +#define AFE_HDMI_OUT_END_MSB 0x5370 +#define AFE_HDMI_OUT_END 0x5374 +#define AFE_HDMI_OUT_CON0 0x5378 +#define AFE_VUL24_RCH_MON 0x53e0 +#define AFE_VUL24_LCH_MON 0x53e4 +#define AFE_VUL25_RCH_MON 0x53e8 +#define AFE_VUL25_LCH_MON 0x53ec +#define AFE_VUL26_RCH_MON 0x53f0 +#define AFE_VUL26_LCH_MON 0x53f4 +#define AFE_VUL_CM0_RCH_MON 0x5458 +#define AFE_VUL_CM0_LCH_MON 0x545c +#define AFE_VUL_CM1_RCH_MON 0x5460 +#define AFE_VUL_CM1_LCH_MON 0x5464 +#define AFE_VUL_CM2_RCH_MON 0x5468 +#define AFE_VUL_CM2_LCH_MON 0x546c +#define AFE_DL_4CH_CH0_MON 0x54f4 +#define AFE_DL_4CH_CH1_MON 0x54f8 +#define AFE_DL_4CH_CH2_MON 0x54fc +#define AFE_DL_4CH_CH3_MON 0x5500 +#define AFE_DL_24CH_CH0_MON 0x5504 +#define AFE_DL_24CH_CH1_MON 0x5508 +#define AFE_DL_24CH_CH2_MON 0x550c +#define AFE_DL_24CH_CH3_MON 0x5510 +#define AFE_DL_24CH_CH4_MON 0x5514 +#define AFE_DL_24CH_CH5_MON 0x5518 +#define AFE_DL_24CH_CH6_MON 0x551c +#define AFE_DL_24CH_CH7_MON 0x5520 +#define AFE_DL_24CH_CH8_MON 0x5524 +#define AFE_DL_24CH_CH9_MON 0x5528 +#define AFE_DL_24CH_CH10_MON 0x552c +#define AFE_DL_24CH_CH11_MON 0x5530 +#define AFE_DL_24CH_CH12_MON 0x5534 +#define AFE_DL_24CH_CH13_MON 0x5538 +#define AFE_DL_24CH_CH14_MON 0x553c +#define AFE_DL_24CH_CH15_MON 0x5540 +#define AFE_SRAM_BOUND 0x5620 +#define AFE_SECURE_CON0 0x5624 +#define AFE_SECURE_CON1 0x5628 +#define AFE_SE_SECURE_CON0 0x5630 +#define AFE_SE_SECURE_CON1 0x5634 +#define AFE_SE_SECURE_CON2 0x5638 +#define AFE_SE_SECURE_CON3 0x563c +#define AFE_SE_PROT_SIDEBAND0 0x5640 +#define AFE_SE_PROT_SIDEBAND1 0x5644 +#define AFE_SE_PROT_SIDEBAND2 0x5648 +#define AFE_SE_PROT_SIDEBAND3 0x564c +#define AFE_SE_DOMAIN_SIDEBAND0 0x5650 +#define AFE_SE_DOMAIN_SIDEBAND1 0x5654 +#define AFE_SE_DOMAIN_SIDEBAND2 0x5658 +#define AFE_SE_DOMAIN_SIDEBAND3 0x565c +#define AFE_SE_DOMAIN_SIDEBAND4 0x5660 +#define AFE_SE_DOMAIN_SIDEBAND5 0x5664 +#define AFE_SE_DOMAIN_SIDEBAND6 0x5668 +#define AFE_SE_DOMAIN_SIDEBAND7 0x566c +#define AFE_SE_DOMAIN_SIDEBAND8 0x5670 +#define AFE_SE_DOMAIN_SIDEBAND9 0x5674 +#define AFE_PROT_SIDEBAND0_MON 0x5678 +#define AFE_PROT_SIDEBAND1_MON 0x567c +#define AFE_PROT_SIDEBAND2_MON 0x5680 +#define AFE_PROT_SIDEBAND3_MON 0x5684 +#define AFE_DOMAIN_SIDEBAND0_MON 0x5688 +#define AFE_DOMAIN_SIDEBAND1_MON 0x568c +#define AFE_DOMAIN_SIDEBAND2_MON 0x5690 +#define AFE_DOMAIN_SIDEBAND3_MON 0x5694 +#define AFE_DOMAIN_SIDEBAND4_MON 0x5698 +#define AFE_DOMAIN_SIDEBAND5_MON 0x569c +#define AFE_DOMAIN_SIDEBAND6_MON 0x56a0 +#define AFE_DOMAIN_SIDEBAND7_MON 0x56a4 +#define AFE_DOMAIN_SIDEBAND8_MON 0x56a8 +#define AFE_DOMAIN_SIDEBAND9_MON 0x56ac +#define AFE_SECURE_CONN0 0x56b0 +#define AFE_SECURE_CONN_ETDM0 0x56b4 +#define AFE_SECURE_CONN_ETDM1 0x56b8 +#define AFE_SECURE_CONN_ETDM2 0x56bc +#define AFE_SECURE_SRAM_CON0 0x56c0 +#define AFE_SECURE_SRAM_CON1 0x56c4 +#define AFE_SE_CONN_INPUT_MASK0 0x56d0 +#define AFE_SE_CONN_INPUT_MASK1 0x56d4 +#define AFE_SE_CONN_INPUT_MASK2 0x56d8 +#define AFE_SE_CONN_INPUT_MASK3 0x56dc +#define AFE_SE_CONN_INPUT_MASK4 0x56e0 +#define AFE_SE_CONN_INPUT_MASK5 0x56e4 +#define AFE_SE_CONN_INPUT_MASK6 0x56e8 +#define AFE_SE_CONN_INPUT_MASK7 0x56ec +#define AFE_NON_SE_CONN_INPUT_MASK0 0x56f0 +#define AFE_NON_SE_CONN_INPUT_MASK1 0x56f4 +#define AFE_NON_SE_CONN_INPUT_MASK2 0x56f8 +#define AFE_NON_SE_CONN_INPUT_MASK3 0x56fc +#define AFE_NON_SE_CONN_INPUT_MASK4 0x5700 +#define AFE_NON_SE_CONN_INPUT_MASK5 0x5704 +#define AFE_NON_SE_CONN_INPUT_MASK6 0x5708 +#define AFE_NON_SE_CONN_INPUT_MASK7 0x570c +#define AFE_SE_CONN_OUTPUT_SEL0 0x5710 +#define AFE_SE_CONN_OUTPUT_SEL1 0x5714 +#define AFE_SE_CONN_OUTPUT_SEL2 0x5718 +#define AFE_SE_CONN_OUTPUT_SEL3 0x571c +#define AFE_SE_CONN_OUTPUT_SEL4 0x5720 +#define AFE_SE_CONN_OUTPUT_SEL5 0x5724 +#define AFE_SE_CONN_OUTPUT_SEL6 0x5728 +#define AFE_SE_CONN_OUTPUT_SEL7 0x572c +#define AFE_PCM0_INTF_CON1_MASK_MON 0x5730 +#define AFE_PCM0_INTF_CON0_MASK_MON 0x5734 +#define AFE_CONNSYS_I2S_CON_MASK_MON 0x5738 +#define AFE_TDM_CON2_MASK_MON 0x5744 +#define AFE_MTKAIF0_CFG0_MASK_MON 0x574c +#define AFE_MTKAIF1_CFG0_MASK_MON 0x5750 +#define AFE_ADDA_UL0_SRC_CON0_MASK_MON 0x5754 +#define AFE_ADDA_UL1_SRC_CON0_MASK_MON 0x5758 +#define AFE_ADDA_UL2_SRC_CON0_MASK_MON 0x575c +#define AFE_ASRC_NEW_CON0 0x7800 +#define AFE_ASRC_NEW_CON1 0x7804 +#define AFE_ASRC_NEW_CON2 0x7808 +#define AFE_ASRC_NEW_CON3 0x780c +#define AFE_ASRC_NEW_CON4 0x7810 +#define AFE_ASRC_NEW_CON5 0x7814 +#define AFE_ASRC_NEW_CON6 0x7818 +#define AFE_ASRC_NEW_CON7 0x781c +#define AFE_ASRC_NEW_CON8 0x7820 +#define AFE_ASRC_NEW_CON9 0x7824 +#define AFE_ASRC_NEW_CON10 0x7828 +#define AFE_ASRC_NEW_CON11 0x782c +#define AFE_ASRC_NEW_CON12 0x7830 +#define AFE_ASRC_NEW_CON13 0x7834 +#define AFE_ASRC_NEW_CON14 0x7838 +#define AFE_ASRC_NEW_IP_VERSION 0x783c +#define AFE_GASRC0_NEW_CON0 0x7840 +#define AFE_GASRC0_NEW_CON1 0x7844 +#define AFE_GASRC0_NEW_CON2 0x7848 +#define AFE_GASRC0_NEW_CON3 0x784c +#define AFE_GASRC0_NEW_CON4 0x7850 +#define AFE_GASRC0_NEW_CON5 0x7854 +#define AFE_GASRC0_NEW_CON6 0x7858 +#define AFE_GASRC0_NEW_CON7 0x785c +#define AFE_GASRC0_NEW_CON8 0x7860 +#define AFE_GASRC0_NEW_CON9 0x7864 +#define AFE_GASRC0_NEW_CON10 0x7868 +#define AFE_GASRC0_NEW_CON11 0x786c +#define AFE_GASRC0_NEW_CON12 0x7870 +#define AFE_GASRC0_NEW_CON13 0x7874 +#define AFE_GASRC0_NEW_CON14 0x7878 +#define AFE_GASRC0_NEW_IP_VERSION 0x787c +#define AFE_GASRC1_NEW_CON0 0x7880 +#define AFE_GASRC1_NEW_CON1 0x7884 +#define AFE_GASRC1_NEW_CON2 0x7888 +#define AFE_GASRC1_NEW_CON3 0x788c +#define AFE_GASRC1_NEW_CON4 0x7890 +#define AFE_GASRC1_NEW_CON5 0x7894 +#define AFE_GASRC1_NEW_CON6 0x7898 +#define AFE_GASRC1_NEW_CON7 0x789c +#define AFE_GASRC1_NEW_CON8 0x78a0 +#define AFE_GASRC1_NEW_CON9 0x78a4 +#define AFE_GASRC1_NEW_CON10 0x78a8 +#define AFE_GASRC1_NEW_CON11 0x78ac +#define AFE_GASRC1_NEW_CON12 0x78b0 +#define AFE_GASRC1_NEW_CON13 0x78b4 +#define AFE_GASRC1_NEW_CON14 0x78b8 +#define AFE_GASRC1_NEW_IP_VERSION 0x78bc +#define AFE_GASRC2_NEW_CON0 0x78c0 +#define AFE_GASRC2_NEW_CON1 0x78c4 +#define AFE_GASRC2_NEW_CON2 0x78c8 +#define AFE_GASRC2_NEW_CON3 0x78cc +#define AFE_GASRC2_NEW_CON4 0x78d0 +#define AFE_GASRC2_NEW_CON5 0x78d4 +#define AFE_GASRC2_NEW_CON6 0x78d8 +#define AFE_GASRC2_NEW_CON7 0x78dc +#define AFE_GASRC2_NEW_CON8 0x78e0 +#define AFE_GASRC2_NEW_CON9 0x78e4 +#define AFE_GASRC2_NEW_CON10 0x78e8 +#define AFE_GASRC2_NEW_CON11 0x78ec +#define AFE_GASRC2_NEW_CON12 0x78f0 +#define AFE_GASRC2_NEW_CON13 0x78f4 +#define AFE_GASRC2_NEW_CON14 0x78f8 +#define AFE_GASRC2_NEW_IP_VERSION 0x78fc +#define AFE_GASRC3_NEW_CON0 0x7900 +#define AFE_GASRC3_NEW_CON1 0x7904 +#define AFE_GASRC3_NEW_CON2 0x7908 +#define AFE_GASRC3_NEW_CON3 0x790c +#define AFE_GASRC3_NEW_CON4 0x7910 +#define AFE_GASRC3_NEW_CON5 0x7914 +#define AFE_GASRC3_NEW_CON6 0x7918 +#define AFE_GASRC3_NEW_CON7 0x791c +#define AFE_GASRC3_NEW_CON8 0x7920 +#define AFE_GASRC3_NEW_CON9 0x7924 +#define AFE_GASRC3_NEW_CON10 0x7928 +#define AFE_GASRC3_NEW_CON11 0x792c +#define AFE_GASRC3_NEW_CON12 0x7930 +#define AFE_GASRC3_NEW_CON13 0x7934 +#define AFE_GASRC3_NEW_CON14 0x7938 +#define AFE_GASRC3_NEW_IP_VERSION 0x793c +#define AFE_GASRC4_NEW_CON0 0x7940 +#define AFE_GASRC4_NEW_CON1 0x7944 +#define AFE_GASRC4_NEW_CON2 0x7948 +#define AFE_GASRC4_NEW_CON3 0x794c +#define AFE_GASRC4_NEW_CON4 0x7950 +#define AFE_GASRC4_NEW_CON5 0x7954 +#define AFE_GASRC4_NEW_CON6 0x7958 +#define AFE_GASRC4_NEW_CON7 0x795c +#define AFE_GASRC4_NEW_CON8 0x7960 +#define AFE_GASRC4_NEW_CON9 0x7964 +#define AFE_GASRC4_NEW_CON10 0x7968 +#define AFE_GASRC4_NEW_CON11 0x796c +#define AFE_GASRC4_NEW_CON12 0x7970 +#define AFE_GASRC4_NEW_CON13 0x7974 +#define AFE_GASRC4_NEW_CON14 0x7978 +#define AFE_GASRC4_NEW_IP_VERSION 0x797c +#define AFE_GASRC5_NEW_CON0 0x7980 +#define AFE_GASRC5_NEW_CON1 0x7984 +#define AFE_GASRC5_NEW_CON2 0x7988 +#define AFE_GASRC5_NEW_CON3 0x798c +#define AFE_GASRC5_NEW_CON4 0x7990 +#define AFE_GASRC5_NEW_CON5 0x7994 +#define AFE_GASRC5_NEW_CON6 0x7998 +#define AFE_GASRC5_NEW_CON7 0x799c +#define AFE_GASRC5_NEW_CON8 0x79a0 +#define AFE_GASRC5_NEW_CON9 0x79a4 +#define AFE_GASRC5_NEW_CON10 0x79a8 +#define AFE_GASRC5_NEW_CON11 0x79ac +#define AFE_GASRC5_NEW_CON12 0x79b0 +#define AFE_GASRC5_NEW_CON13 0x79b4 +#define AFE_GASRC5_NEW_CON14 0x79b8 +#define AFE_GASRC5_NEW_IP_VERSION 0x79bc +#define AFE_GASRC6_NEW_CON0 0x79c0 +#define AFE_GASRC6_NEW_CON1 0x79c4 +#define AFE_GASRC6_NEW_CON2 0x79c8 +#define AFE_GASRC6_NEW_CON3 0x79cc +#define AFE_GASRC6_NEW_CON4 0x79d0 +#define AFE_GASRC6_NEW_CON5 0x79d4 +#define AFE_GASRC6_NEW_CON6 0x79d8 +#define AFE_GASRC6_NEW_CON7 0x79dc +#define AFE_GASRC6_NEW_CON8 0x79e0 +#define AFE_GASRC6_NEW_CON9 0x79e4 +#define AFE_GASRC6_NEW_CON10 0x79e8 +#define AFE_GASRC6_NEW_CON11 0x79ec +#define AFE_GASRC6_NEW_CON12 0x79f0 +#define AFE_GASRC6_NEW_CON13 0x79f4 +#define AFE_GASRC6_NEW_CON14 0x79f8 +#define AFE_GASRC6_NEW_IP_VERSION 0x79fc +#define AFE_GASRC7_NEW_CON0 0x7a00 +#define AFE_GASRC7_NEW_CON1 0x7a04 +#define AFE_GASRC7_NEW_CON2 0x7a08 +#define AFE_GASRC7_NEW_CON3 0x7a0c +#define AFE_GASRC7_NEW_CON4 0x7a10 +#define AFE_GASRC7_NEW_CON5 0x7a14 +#define AFE_GASRC7_NEW_CON6 0x7a18 +#define AFE_GASRC7_NEW_CON7 0x7a1c +#define AFE_GASRC7_NEW_CON8 0x7a20 +#define AFE_GASRC7_NEW_CON9 0x7a24 +#define AFE_GASRC7_NEW_CON10 0x7a28 +#define AFE_GASRC7_NEW_CON11 0x7a2c +#define AFE_GASRC7_NEW_CON12 0x7a30 +#define AFE_GASRC7_NEW_CON13 0x7a34 +#define AFE_GASRC7_NEW_CON14 0x7a38 +#define AFE_GASRC7_NEW_IP_VERSION 0x7a3c +#define AFE_GASRC8_NEW_CON0 0x7a40 +#define AFE_GASRC8_NEW_CON1 0x7a44 +#define AFE_GASRC8_NEW_CON2 0x7a48 +#define AFE_GASRC8_NEW_CON3 0x7a4c +#define AFE_GASRC8_NEW_CON4 0x7a50 +#define AFE_GASRC8_NEW_CON5 0x7a54 +#define AFE_GASRC8_NEW_CON6 0x7a58 +#define AFE_GASRC8_NEW_CON7 0x7a5c +#define AFE_GASRC8_NEW_CON8 0x7a60 +#define AFE_GASRC8_NEW_CON9 0x7a64 +#define AFE_GASRC8_NEW_CON10 0x7a68 +#define AFE_GASRC8_NEW_CON11 0x7a6c +#define AFE_GASRC8_NEW_CON12 0x7a70 +#define AFE_GASRC8_NEW_CON13 0x7a74 +#define AFE_GASRC8_NEW_CON14 0x7a78 +#define AFE_GASRC8_NEW_IP_VERSION 0x7a7c +#define AFE_GASRC9_NEW_CON0 0x7a80 +#define AFE_GASRC9_NEW_CON1 0x7a84 +#define AFE_GASRC9_NEW_CON2 0x7a88 +#define AFE_GASRC9_NEW_CON3 0x7a8c +#define AFE_GASRC9_NEW_CON4 0x7a90 +#define AFE_GASRC9_NEW_CON5 0x7a94 +#define AFE_GASRC9_NEW_CON6 0x7a98 +#define AFE_GASRC9_NEW_CON7 0x7a9c +#define AFE_GASRC9_NEW_CON8 0x7aa0 +#define AFE_GASRC9_NEW_CON9 0x7aa4 +#define AFE_GASRC9_NEW_CON10 0x7aa8 +#define AFE_GASRC9_NEW_CON11 0x7aac +#define AFE_GASRC9_NEW_CON12 0x7ab0 +#define AFE_GASRC9_NEW_CON13 0x7ab4 +#define AFE_GASRC9_NEW_CON14 0x7ab8 +#define AFE_GASRC9_NEW_IP_VERSION 0x7abc +#define AFE_GASRC10_NEW_CON0 0x7ac0 +#define AFE_GASRC10_NEW_CON1 0x7ac4 +#define AFE_GASRC10_NEW_CON2 0x7ac8 +#define AFE_GASRC10_NEW_CON3 0x7acc +#define AFE_GASRC10_NEW_CON4 0x7ad0 +#define AFE_GASRC10_NEW_CON5 0x7ad4 +#define AFE_GASRC10_NEW_CON6 0x7ad8 +#define AFE_GASRC10_NEW_CON7 0x7adc +#define AFE_GASRC10_NEW_CON8 0x7ae0 +#define AFE_GASRC10_NEW_CON9 0x7ae4 +#define AFE_GASRC10_NEW_CON10 0x7ae8 +#define AFE_GASRC10_NEW_CON11 0x7aec +#define AFE_GASRC10_NEW_CON12 0x7af0 +#define AFE_GASRC10_NEW_CON13 0x7af4 +#define AFE_GASRC10_NEW_CON14 0x7af8 +#define AFE_GASRC10_NEW_IP_VERSION 0x7afc +#define AFE_GASRC11_NEW_CON0 0x7b00 +#define AFE_GASRC11_NEW_CON1 0x7b04 +#define AFE_GASRC11_NEW_CON2 0x7b08 +#define AFE_GASRC11_NEW_CON3 0x7b0c +#define AFE_GASRC11_NEW_CON4 0x7b10 +#define AFE_GASRC11_NEW_CON5 0x7b14 +#define AFE_GASRC11_NEW_CON6 0x7b18 +#define AFE_GASRC11_NEW_CON7 0x7b1c +#define AFE_GASRC11_NEW_CON8 0x7b20 +#define AFE_GASRC11_NEW_CON9 0x7b24 +#define AFE_GASRC11_NEW_CON10 0x7b28 +#define AFE_GASRC11_NEW_CON11 0x7b2c +#define AFE_GASRC11_NEW_CON12 0x7b30 +#define AFE_GASRC11_NEW_CON13 0x7b34 +#define AFE_GASRC11_NEW_CON14 0x7b38 +#define AFE_GASRC11_NEW_IP_VERSION 0x7b3c +#define AFE_GASRC12_NEW_CON0 0x7b40 +#define AFE_GASRC12_NEW_CON1 0x7b44 +#define AFE_GASRC12_NEW_CON2 0x7b48 +#define AFE_GASRC12_NEW_CON3 0x7b4c +#define AFE_GASRC12_NEW_CON4 0x7b50 +#define AFE_GASRC12_NEW_CON5 0x7b54 +#define AFE_GASRC12_NEW_CON6 0x7b58 +#define AFE_GASRC12_NEW_CON7 0x7b5c +#define AFE_GASRC12_NEW_CON8 0x7b60 +#define AFE_GASRC12_NEW_CON9 0x7b64 +#define AFE_GASRC12_NEW_CON10 0x7b68 +#define AFE_GASRC12_NEW_CON11 0x7b6c +#define AFE_GASRC12_NEW_CON12 0x7b70 +#define AFE_GASRC12_NEW_CON13 0x7b74 +#define AFE_GASRC12_NEW_CON14 0x7b78 +#define AFE_GASRC12_NEW_IP_VERSION 0x7b7c +#define AFE_GASRC13_NEW_CON0 0x7b80 +#define AFE_GASRC13_NEW_CON1 0x7b84 +#define AFE_GASRC13_NEW_CON2 0x7b88 +#define AFE_GASRC13_NEW_CON3 0x7b8c +#define AFE_GASRC13_NEW_CON4 0x7b90 +#define AFE_GASRC13_NEW_CON5 0x7b94 +#define AFE_GASRC13_NEW_CON6 0x7b98 +#define AFE_GASRC13_NEW_CON7 0x7b9c +#define AFE_GASRC13_NEW_CON8 0x7ba0 +#define AFE_GASRC13_NEW_CON9 0x7ba4 +#define AFE_GASRC13_NEW_CON10 0x7ba8 +#define AFE_GASRC13_NEW_CON11 0x7bac +#define AFE_GASRC13_NEW_CON12 0x7bb0 +#define AFE_GASRC13_NEW_CON13 0x7bb4 +#define AFE_GASRC13_NEW_CON14 0x7bb8 +#define AFE_GASRC13_NEW_IP_VERSION 0x7bbc +#define AFE_GASRC14_NEW_CON0 0x7bc0 +#define AFE_GASRC14_NEW_CON1 0x7bc4 +#define AFE_GASRC14_NEW_CON2 0x7bc8 +#define AFE_GASRC14_NEW_CON3 0x7bcc +#define AFE_GASRC14_NEW_CON4 0x7bd0 +#define AFE_GASRC14_NEW_CON5 0x7bd4 +#define AFE_GASRC14_NEW_CON6 0x7bd8 +#define AFE_GASRC14_NEW_CON7 0x7bdc +#define AFE_GASRC14_NEW_CON8 0x7be0 +#define AFE_GASRC14_NEW_CON9 0x7be4 +#define AFE_GASRC14_NEW_CON10 0x7be8 +#define AFE_GASRC14_NEW_CON11 0x7bec +#define AFE_GASRC14_NEW_CON12 0x7bf0 +#define AFE_GASRC14_NEW_CON13 0x7bf4 +#define AFE_GASRC14_NEW_CON14 0x7bf8 +#define AFE_GASRC14_NEW_IP_VERSION 0x7bfc +#define AFE_GASRC15_NEW_CON0 0x7c00 +#define AFE_GASRC15_NEW_CON1 0x7c04 +#define AFE_GASRC15_NEW_CON2 0x7c08 +#define AFE_GASRC15_NEW_CON3 0x7c0c +#define AFE_GASRC15_NEW_CON4 0x7c10 +#define AFE_GASRC15_NEW_CON5 0x7c14 +#define AFE_GASRC15_NEW_CON6 0x7c18 +#define AFE_GASRC15_NEW_CON7 0x7c1c +#define AFE_GASRC15_NEW_CON8 0x7c20 +#define AFE_GASRC15_NEW_CON9 0x7c24 +#define AFE_GASRC15_NEW_CON10 0x7c28 +#define AFE_GASRC15_NEW_CON11 0x7c2c +#define AFE_GASRC15_NEW_CON12 0x7c30 +#define AFE_GASRC15_NEW_CON13 0x7c34 +#define AFE_GASRC15_NEW_CON14 0x7c38 +#define AFE_GASRC15_NEW_IP_VERSION 0x7c3c + +#define AFE_MAX_REGISTER AFE_GASRC15_NEW_IP_VERSION + +#define AFE_IRQ_STATUS_BITS 0x87FFFFFF +#define AFE_IRQ_CNT_SHIFT 0 +#define AFE_IRQ_CNT_MASK 0xffffff +#endif + From patchwork Mon Apr 7 12:06:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 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mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 501099966; Mon, 07 Apr 2025 20:10:55 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by MTKMBS09N1.mediatek.inc (172.21.101.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Mon, 7 Apr 2025 20:10:54 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Mon, 7 Apr 2025 20:10:53 +0800 From: Darren.Ye To: Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Jaroslav Kysela , Takashi Iwai , Linus Walleij , Bartosz Golaszewski CC: , , , , , , Darren Ye Subject: [PATCH v2 04/11] ASoC: mediatek: mt8196: support audio clock control Date: Mon, 7 Apr 2025 20:06:28 +0800 Message-ID: <20250407120708.26495-5-darren.ye@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250407120708.26495-1-darren.ye@mediatek.com> References: <20250407120708.26495-1-darren.ye@mediatek.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N From: Darren Ye Add audio clock wrapper and audio tuner control. Signed-off-by: Darren Ye --- sound/soc/mediatek/mt8196/mt8196-afe-clk.c | 729 +++++++++++++++++++++ sound/soc/mediatek/mt8196/mt8196-afe-clk.h | 78 +++ 2 files changed, 807 insertions(+) create mode 100644 sound/soc/mediatek/mt8196/mt8196-afe-clk.c create mode 100644 sound/soc/mediatek/mt8196/mt8196-afe-clk.h diff --git a/sound/soc/mediatek/mt8196/mt8196-afe-clk.c b/sound/soc/mediatek/mt8196/mt8196-afe-clk.c new file mode 100644 index 000000000000..10383f0abd9a --- /dev/null +++ b/sound/soc/mediatek/mt8196/mt8196-afe-clk.c @@ -0,0 +1,729 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * mt8196-afe-clk.c -- Mediatek 8196 afe clock ctrl + * + * Copyright (c) 2024 MediaTek Inc. + * Author: Darren Ye + */ + +#include +#include +#include +#include "mt8196-afe-common.h" +#include "mt8196-afe-clk.h" + +/* vlp apll1 tuner default value*/ +#define VLP_APLL1_TUNER_CON0_VALUE 0x6f28bd4d + +/* vlp apll2 tuner default value + 1*/ +#define VLP_APLL2_TUNER_CON0_VALUE 0x78fd5265 + +static DEFINE_MUTEX(mutex_request_dram); + +static const char *aud_clks[CLK_NUM] = { + /* afe clk */ + [CLK_HOPPING] = "aud_hopping_clk", + [CLK_F26M] = "aud_f26m_clk", + [CLK_APLL1] = "aud_apll1_clk", + [CLK_APLL2] = "aud_apll2_clk", + [CLK_APLL1_TUNER] = "aud_apll_tuner1_clk", + [CLK_APLL2_TUNER] = "aud_apll_tuner2_clk", + /* vlp clk */ + [CLK_VLP_MUX_AUDIOINTBUS] = "vlp_mux_audio_int", + [CLK_VLP_MUX_AUD_ENG1] = "vlp_mux_aud_eng1", + [CLK_VLP_MUX_AUD_ENG2] = "vlp_mux_aud_eng2", + [CLK_VLP_MUX_AUDIO_H] = "vlp_mux_audio_h", + [CLK_VLP_CLK26M] = "vlp_clk26m_clk", + /* ck clk */ + [CLK_CK_MAINPLL_D4_D4] = "ck_mainpll_d4_d4", + [CLK_CK_MUX_AUD_1] = "ck_mux_aud_1", + [CLK_CK_APLL1_CK] = "ck_apll1_ck", + [CLK_CK_MUX_AUD_2] = "ck_mux_aud_2", + [CLK_CK_APLL2_CK] = "ck_apll2_ck", + [CLK_CK_APLL1_D4] = "ck_apll1_d4", + [CLK_CK_APLL2_D4] = "ck_apll2_d4", + [CLK_CK_I2SIN0_M_SEL] = "ck_i2sin0_m_sel", + [CLK_CK_I2SIN1_M_SEL] = "ck_i2sin1_m_sel", + [CLK_CK_FMI2S_M_SEL] = "ck_fmi2s_m_sel", + [CLK_CK_TDMOUT_M_SEL] = "ck_tdmout_m_sel", + [CLK_CK_APLL12_DIV_I2SIN0] = "ck_apll12_div_i2sin0", + [CLK_CK_APLL12_DIV_I2SIN1] = "ck_apll12_div_i2sin1", + [CLK_CK_APLL12_DIV_FMI2S] = "ck_apll12_div_fmi2s", + [CLK_CK_APLL12_DIV_TDMOUT_M] = "ck_apll12_div_tdmout_m", + [CLK_CK_APLL12_DIV_TDMOUT_B] = "ck_apll12_div_tdmout_b", + [CLK_CK_ADSP_SEL] = "ck_adsp_sel", + [CLK_CLK26M] = "ck_clk26m_clk", +}; + +static int mt8196_set_audio_int_bus_parent(struct mtk_base_afe *afe, + int clk_id, bool int_bus) +{ + struct mt8196_afe_private *afe_priv = afe->platform_priv; + struct clk *clk; + int ret; + + if (clk_id >= CLK_NUM || clk_id < 0) + return -EINVAL; + + clk = int_bus ? afe_priv->clk[CLK_VLP_MUX_AUDIOINTBUS] : + afe_priv->clk[CLK_VLP_MUX_AUDIO_H]; + ret = clk_set_parent(clk, afe_priv->clk[clk_id]); + if (ret) { + dev_err(afe->dev, "clk_set_parent %s fail, int_bus %d\n", + aud_clks[clk_id], int_bus); + return ret; + } + return 0; +} + +static int apll1_mux_setting(struct mtk_base_afe *afe, bool enable) +{ + struct mt8196_afe_private *afe_priv = afe->platform_priv; + int ret = 0; + + dev_dbg(afe->dev, "enable: %d\n", enable); + + if (enable) { + ret = clk_prepare_enable(afe_priv->clk[CLK_CK_MUX_AUD_1]); + if (ret) { + dev_err(afe->dev, "clk_prepare_enable %s fail %d\n", + aud_clks[CLK_CK_MUX_AUD_1], ret); + return ret; + } + ret = clk_set_parent(afe_priv->clk[CLK_CK_MUX_AUD_1], + afe_priv->clk[CLK_CK_APLL1_CK]); + if (ret) { + dev_err(afe->dev, "clk_set_parent %s-%s fail %d\n", + aud_clks[CLK_CK_MUX_AUD_1], + aud_clks[CLK_CK_APLL1_CK], ret); + return ret; + } + + /* 180.6336 / 4 = 45.1584MHz */ + ret = clk_prepare_enable(afe_priv->clk[CLK_VLP_MUX_AUD_ENG1]); + if (ret) { + dev_err(afe->dev, "clk_prepare_enable %s fail %d\n", + aud_clks[CLK_VLP_MUX_AUD_ENG1], ret); + return ret; + } + ret = clk_set_parent(afe_priv->clk[CLK_VLP_MUX_AUD_ENG1], + afe_priv->clk[CLK_CK_APLL1_D4]); + if (ret) { + dev_err(afe->dev, "clk_set_parent %s-%s fail %d\n", + aud_clks[CLK_VLP_MUX_AUD_ENG1], + aud_clks[CLK_CK_APLL1_D4], ret); + return ret; + } + ret = clk_prepare_enable(afe_priv->clk[CLK_VLP_MUX_AUDIO_H]); + if (ret) { + dev_err(afe->dev, "clk_prepare_enable %s fail %d\n", + aud_clks[CLK_VLP_MUX_AUDIO_H], ret); + return ret; + } + + mt8196_set_audio_int_bus_parent(afe, CLK_CK_APLL1_CK, false); + } else { + ret = clk_set_parent(afe_priv->clk[CLK_VLP_MUX_AUD_ENG1], + afe_priv->clk[CLK_VLP_CLK26M]); + if (ret) { + dev_err(afe->dev, "clk_set_parent %s-%s fail %d\n", + aud_clks[CLK_VLP_MUX_AUD_ENG1], + aud_clks[CLK_VLP_CLK26M], ret); + return ret; + } + clk_disable_unprepare(afe_priv->clk[CLK_VLP_MUX_AUD_ENG1]); + + ret = clk_set_parent(afe_priv->clk[CLK_CK_MUX_AUD_1], + afe_priv->clk[CLK_CLK26M]); + if (ret) { + dev_err(afe->dev, "clk_set_parent %s-%s fail %d\n", + aud_clks[CLK_CK_MUX_AUD_1], + aud_clks[CLK_CLK26M], ret); + return ret; + } + clk_disable_unprepare(afe_priv->clk[CLK_CK_MUX_AUD_1]); + + mt8196_set_audio_int_bus_parent(afe, CLK_VLP_CLK26M, false); + clk_disable_unprepare(afe_priv->clk[CLK_VLP_MUX_AUDIO_H]); + } + + return 0; +} + +static int apll2_mux_setting(struct mtk_base_afe *afe, bool enable) +{ + struct mt8196_afe_private *afe_priv = afe->platform_priv; + int ret = 0; + + dev_dbg(afe->dev, "enable: %d\n", enable); + + if (enable) { + ret = clk_prepare_enable(afe_priv->clk[CLK_CK_MUX_AUD_2]); + if (ret) { + dev_err(afe->dev, "clk_prepare_enable %s fail %d\n", + aud_clks[CLK_CK_MUX_AUD_2], ret); + return ret; + } + ret = clk_set_parent(afe_priv->clk[CLK_CK_MUX_AUD_2], + afe_priv->clk[CLK_CK_APLL2_CK]); + if (ret) { + dev_err(afe->dev, "clk_set_parent %s-%s fail %d\n", + aud_clks[CLK_CK_MUX_AUD_2], + aud_clks[CLK_CK_APLL2_CK], ret); + return ret; + } + + /* 196.608 / 4 = 49.152MHz */ + ret = clk_prepare_enable(afe_priv->clk[CLK_VLP_MUX_AUD_ENG2]); + if (ret) { + dev_err(afe->dev, "clk_prepare_enable %s fail %d\n", + aud_clks[CLK_VLP_MUX_AUD_ENG2], ret); + return ret; + } + ret = clk_set_parent(afe_priv->clk[CLK_VLP_MUX_AUD_ENG2], + afe_priv->clk[CLK_CK_APLL2_D4]); + if (ret) { + dev_err(afe->dev, "clk_set_parent %s-%s fail %d\n", + aud_clks[CLK_VLP_MUX_AUD_ENG2], + aud_clks[CLK_CK_APLL2_D4], ret); + return ret; + } + ret = clk_prepare_enable(afe_priv->clk[CLK_VLP_MUX_AUDIO_H]); + if (ret) { + dev_err(afe->dev, "clk_prepare_enable %s fail %d\n", + aud_clks[CLK_VLP_MUX_AUDIO_H], ret); + return ret; + } + + mt8196_set_audio_int_bus_parent(afe, CLK_CK_APLL2_CK, false); + } else { + ret = clk_set_parent(afe_priv->clk[CLK_VLP_MUX_AUD_ENG2], + afe_priv->clk[CLK_VLP_CLK26M]); + if (ret) { + dev_err(afe->dev, "clk_set_parent %s-%s fail %d\n", + aud_clks[CLK_VLP_MUX_AUD_ENG2], + aud_clks[CLK_VLP_CLK26M], ret); + return ret; + } + clk_disable_unprepare(afe_priv->clk[CLK_VLP_MUX_AUD_ENG2]); + + ret = clk_set_parent(afe_priv->clk[CLK_CK_MUX_AUD_2], + afe_priv->clk[CLK_CLK26M]); + if (ret) { + dev_err(afe->dev, "clk_set_parent %s-%s fail %d\n", + aud_clks[CLK_CK_MUX_AUD_2], + aud_clks[CLK_CLK26M], ret); + return ret; + } + clk_disable_unprepare(afe_priv->clk[CLK_CK_MUX_AUD_2]); + + mt8196_set_audio_int_bus_parent(afe, CLK_VLP_CLK26M, false); + clk_disable_unprepare(afe_priv->clk[CLK_VLP_MUX_AUDIO_H]); + } + + return 0; +} + +static int mt8196_afe_disable_apll(struct mtk_base_afe *afe) +{ + struct mt8196_afe_private *afe_priv = afe->platform_priv; + int ret = 0; + + ret = clk_prepare_enable(afe_priv->clk[CLK_VLP_MUX_AUDIO_H]); + if (ret) { + dev_err(afe->dev, "clk_prepare_enable %s fail %d\n", + aud_clks[CLK_VLP_MUX_AUDIO_H], ret); + return ret; + } + + ret = clk_prepare_enable(afe_priv->clk[CLK_CK_MUX_AUD_1]); + if (ret) { + dev_err(afe->dev, "clk_prepare_enable %s fail %d\n", + aud_clks[CLK_CK_MUX_AUD_1], ret); + goto clk_ck_mux_aud1_err; + } + + ret = clk_set_parent(afe_priv->clk[CLK_CK_MUX_AUD_1], + afe_priv->clk[CLK_CLK26M]); + if (ret) { + dev_err(afe->dev, "clk_set_parent %s-%s fail %d\n", + aud_clks[CLK_CK_MUX_AUD_1], + aud_clks[CLK_CLK26M], ret); + goto clk_ck_mux_aud1_parent_err; + } + ret = clk_prepare_enable(afe_priv->clk[CLK_CK_MUX_AUD_2]); + if (ret) { + dev_err(afe->dev, "clk_prepare_enable %s fail %d\n", + aud_clks[CLK_CK_MUX_AUD_2], ret); + goto clk_ck_mux_aud2_err; + } + + ret = clk_set_parent(afe_priv->clk[CLK_CK_MUX_AUD_2], + afe_priv->clk[CLK_CLK26M]); + if (ret) { + dev_err(afe->dev, "clk_set_parent %s-%s fail %d\n", + aud_clks[CLK_CK_MUX_AUD_2], + aud_clks[CLK_CLK26M], ret); + goto clk_ck_mux_aud2_parent_err; + } + + clk_disable_unprepare(afe_priv->clk[CLK_CK_MUX_AUD_1]); + clk_disable_unprepare(afe_priv->clk[CLK_CK_MUX_AUD_2]); + mt8196_set_audio_int_bus_parent(afe, CLK_VLP_CLK26M, false); + clk_disable_unprepare(afe_priv->clk[CLK_VLP_MUX_AUDIO_H]); + + return 0; + +clk_ck_mux_aud2_parent_err: + clk_disable_unprepare(afe_priv->clk[CLK_CK_MUX_AUD_2]); +clk_ck_mux_aud2_err: + clk_set_parent(afe_priv->clk[CLK_CK_MUX_AUD_1], + afe_priv->clk[CLK_CK_APLL1_CK]); +clk_ck_mux_aud1_parent_err: + clk_disable_unprepare(afe_priv->clk[CLK_CK_MUX_AUD_1]); +clk_ck_mux_aud1_err: + clk_disable_unprepare(afe_priv->clk[CLK_VLP_MUX_AUDIO_H]); + + return ret; +} + +static void mt8196_afe_apll_init(struct mtk_base_afe *afe) +{ + struct mt8196_afe_private *afe_priv = afe->platform_priv; + + if (afe_priv->vlp_ck) { + regmap_write(afe_priv->vlp_ck, VLP_APLL1_TUNER_CON0, VLP_APLL1_TUNER_CON0_VALUE); + regmap_write(afe_priv->vlp_ck, VLP_APLL2_TUNER_CON0, VLP_APLL2_TUNER_CON0_VALUE); + } else { + dev_warn(afe->dev, "vlp_ck regmap is null ptr\n"); + } +} + +int mt8196_afe_enable_clock(struct mtk_base_afe *afe) +{ + struct mt8196_afe_private *afe_priv = afe->platform_priv; + int ret = 0; + + ret = clk_prepare_enable(afe_priv->clk[CLK_CK_ADSP_SEL]); + if (ret) { + dev_err(afe->dev, "clk_prepare_enable %s fail %d\n", + aud_clks[CLK_CK_ADSP_SEL], ret); + goto CLK_CK_ADSP_SEL_ERR; + } + + ret = clk_prepare_enable(afe_priv->clk[CLK_VLP_MUX_AUDIOINTBUS]); + if (ret) { + dev_err(afe->dev, "clk_prepare_enable %s fail %d\n", + aud_clks[CLK_VLP_MUX_AUDIOINTBUS], ret); + goto CLK_MUX_AUDIO_INTBUS_ERR; + } + ret = mt8196_set_audio_int_bus_parent(afe, CLK_VLP_CLK26M, true); + + ret = clk_prepare_enable(afe_priv->clk[CLK_VLP_MUX_AUDIO_H]); + if (ret) { + dev_err(afe->dev, "clk_prepare_enable %s fail %d\n", + aud_clks[CLK_VLP_MUX_AUDIO_H], ret); + goto CLK_AUDIO_H_ERR; + } + mt8196_set_audio_int_bus_parent(afe, CLK_VLP_CLK26M, false); + + /* IPM2.0: USE HOPPING & 26M */ + ret = clk_prepare_enable(afe_priv->clk[CLK_HOPPING]); + if (ret) { + dev_err(afe->dev, "clk_prepare_enable %s fail %d\n", + aud_clks[CLK_HOPPING], ret); + goto CLK_AFE_ERR; + } + ret = clk_prepare_enable(afe_priv->clk[CLK_F26M]); + if (ret) { + dev_err(afe->dev, "clk_prepare_enable %s fail %d\n", + aud_clks[CLK_F26M], ret); + goto CLK_AFE_ERR; + } + + return 0; + +CLK_AFE_ERR: + /* IPM2.0: Use HOPPING & 26M */ + clk_disable_unprepare(afe_priv->clk[CLK_HOPPING]); + clk_disable_unprepare(afe_priv->clk[CLK_F26M]); +CLK_AUDIO_H_ERR: + clk_disable_unprepare(afe_priv->clk[CLK_VLP_MUX_AUDIO_H]); +CLK_MUX_AUDIO_INTBUS_ERR: + clk_disable_unprepare(afe_priv->clk[CLK_VLP_MUX_AUDIOINTBUS]); +CLK_CK_ADSP_SEL_ERR: + clk_disable_unprepare(afe_priv->clk[CLK_CK_ADSP_SEL]); + return ret; +} + +void mt8196_afe_disable_clock(struct mtk_base_afe *afe) +{ + struct mt8196_afe_private *afe_priv = afe->platform_priv; + + /* IPM2.0: Use HOPPING & 26M */ + clk_disable_unprepare(afe_priv->clk[CLK_HOPPING]); + clk_disable_unprepare(afe_priv->clk[CLK_F26M]); + mt8196_set_audio_int_bus_parent(afe, CLK_VLP_CLK26M, false); + clk_disable_unprepare(afe_priv->clk[CLK_VLP_MUX_AUDIO_H]); + mt8196_set_audio_int_bus_parent(afe, CLK_VLP_CLK26M, true); + clk_disable_unprepare(afe_priv->clk[CLK_VLP_MUX_AUDIOINTBUS]); + clk_disable_unprepare(afe_priv->clk[CLK_CK_ADSP_SEL]); +} + +int mt8196_afe_dram_request(struct device *dev) +{ + struct mtk_base_afe *afe = dev_get_drvdata(dev); + struct mt8196_afe_private *afe_priv = afe->platform_priv; + + mutex_lock(&mutex_request_dram); + + afe_priv->dram_resource_counter++; + mutex_unlock(&mutex_request_dram); + + return 0; +} + +int mt8196_afe_dram_release(struct device *dev) +{ + struct mtk_base_afe *afe = dev_get_drvdata(dev); + struct mt8196_afe_private *afe_priv = afe->platform_priv; + + mutex_lock(&mutex_request_dram); + afe_priv->dram_resource_counter--; + + if (afe_priv->dram_resource_counter < 0) { + dev_warn(dev, "dram_resource_counter %d\n", + afe_priv->dram_resource_counter); + afe_priv->dram_resource_counter = 0; + } + mutex_unlock(&mutex_request_dram); + return 0; +} + +int mt8196_apll1_enable(struct mtk_base_afe *afe) +{ + struct mt8196_afe_private *afe_priv = afe->platform_priv; + int ret; + + /* setting for APLL */ + apll1_mux_setting(afe, true); + + ret = clk_prepare_enable(afe_priv->clk[CLK_APLL1]); + if (ret) { + dev_err(afe->dev, "clk_prepare_enable %s fail %d\n", + aud_clks[CLK_APLL1], ret); + goto ERR_CLK_APLL1; + } + + ret = clk_prepare_enable(afe_priv->clk[CLK_APLL1_TUNER]); + if (ret) { + dev_err(afe->dev, "clk_prepare_enable %s fail %d\n", + aud_clks[CLK_APLL1_TUNER], ret); + goto ERR_CLK_APLL1_TUNER; + } + + /* sel 44.1kHz:1, apll_div:7, upper bound:3 */ + regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, + XTAL_EN_128FS_SEL_MASK_SFT | APLL_DIV_MASK_SFT | UPPER_BOUND_MASK_SFT, + (0x1 << XTAL_EN_128FS_SEL_SFT) | (7 << APLL_DIV_SFT) | + (3 << UPPER_BOUND_SFT)); + + /* apll1 freq tuner enable */ + regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, + FREQ_TUNER_EN_MASK_SFT, + 0x1 << FREQ_TUNER_EN_SFT); + + /* audio apll1 on */ + regmap_update_bits(afe->regmap, AUDIO_ENGEN_CON0, + AUDIO_APLL1_EN_ON_MASK_SFT, + 0x1 << AUDIO_APLL1_EN_ON_SFT); + + return 0; + +ERR_CLK_APLL1_TUNER: + clk_disable_unprepare(afe_priv->clk[CLK_APLL1_TUNER]); +ERR_CLK_APLL1: + clk_disable_unprepare(afe_priv->clk[CLK_APLL1]); + + return ret; +} + +void mt8196_apll1_disable(struct mtk_base_afe *afe) +{ + struct mt8196_afe_private *afe_priv = afe->platform_priv; + + /* audio apll1 off */ + regmap_update_bits(afe->regmap, AUDIO_ENGEN_CON0, + AUDIO_APLL1_EN_ON_MASK_SFT, + 0x0); + + /* apll1 freq tuner disable */ + regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, + FREQ_TUNER_EN_MASK_SFT, + 0x0); + + clk_disable_unprepare(afe_priv->clk[CLK_APLL1_TUNER]); + clk_disable_unprepare(afe_priv->clk[CLK_APLL1]); + + apll1_mux_setting(afe, false); +} + +int mt8196_apll2_enable(struct mtk_base_afe *afe) +{ + struct mt8196_afe_private *afe_priv = afe->platform_priv; + int ret; + + /* setting for APLL */ + apll2_mux_setting(afe, true); + + ret = clk_prepare_enable(afe_priv->clk[CLK_APLL2]); + if (ret) { + dev_err(afe->dev, "clk_prepare_enable %s fail %d\n", + aud_clks[CLK_APLL2], ret); + goto ERR_CLK_APLL2; + } + + ret = clk_prepare_enable(afe_priv->clk[CLK_APLL2_TUNER]); + if (ret) { + dev_err(afe->dev, "clk_prepare_enable %s fail %d\n", + aud_clks[CLK_APLL2_TUNER], ret); + goto ERR_CLK_APLL2_TUNER; + } + + /* sel 48kHz: 2, apll_div: 7, upper bound: 3*/ + regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, + XTAL_EN_128FS_SEL_MASK_SFT | APLL_DIV_MASK_SFT | UPPER_BOUND_MASK_SFT, + (0x2 << XTAL_EN_128FS_SEL_SFT) | (7 << APLL_DIV_SFT) | + (3 << UPPER_BOUND_SFT)); + + /* apll2 freq tuner enable */ + regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, + FREQ_TUNER_EN_MASK_SFT, + 0x1 << FREQ_TUNER_EN_SFT); + + /* audio apll2 on */ + regmap_update_bits(afe->regmap, AUDIO_ENGEN_CON0, + AUDIO_APLL2_EN_ON_MASK_SFT, + 0x1 << AUDIO_APLL2_EN_ON_SFT); + + return 0; + +ERR_CLK_APLL2_TUNER: + clk_disable_unprepare(afe_priv->clk[CLK_APLL2_TUNER]); +ERR_CLK_APLL2: + clk_disable_unprepare(afe_priv->clk[CLK_APLL2]); + + return ret; + + return 0; +} + +void mt8196_apll2_disable(struct mtk_base_afe *afe) +{ + struct mt8196_afe_private *afe_priv = afe->platform_priv; + + /* audio apll2 off */ + regmap_update_bits(afe->regmap, AUDIO_ENGEN_CON0, + AUDIO_APLL2_EN_ON_MASK_SFT, + 0x0); + + /* apll2 freq tuner disable */ + regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, + FREQ_TUNER_EN_MASK_SFT, + 0x0); + + clk_disable_unprepare(afe_priv->clk[CLK_APLL2_TUNER]); + clk_disable_unprepare(afe_priv->clk[CLK_APLL2]); + + apll2_mux_setting(afe, false); +} + +int mt8196_get_apll_rate(struct mtk_base_afe *afe, int apll) +{ + struct mt8196_afe_private *afe_priv = afe->platform_priv; + int clk_id = 0; + + if (apll < MT8196_APLL1 || apll > MT8196_APLL2) { + dev_warn(afe->dev, "invalid clk id\n"); + return 0; + } + + if (apll == MT8196_APLL1) + clk_id = CLK_CK_APLL1_CK; + else + clk_id = CLK_CK_APLL2_CK; + + return clk_get_rate(afe_priv->clk[clk_id]); +} + +int mt8196_get_apll_by_rate(struct mtk_base_afe *afe, int rate) +{ + return ((rate % 8000) == 0) ? MT8196_APLL2 : MT8196_APLL1; +} + +int mt8196_get_apll_by_name(struct mtk_base_afe *afe, const char *name) +{ + if (strcmp(name, APLL1_W_NAME) == 0) + return MT8196_APLL1; + else + return MT8196_APLL2; +} + +/* mck */ +struct mt8196_mck_div { + int m_sel_id; + int div_clk_id; +}; + +static const struct mt8196_mck_div mck_div[MT8196_MCK_NUM] = { + [MT8196_I2SIN0_MCK] = { + .m_sel_id = CLK_CK_I2SIN0_M_SEL, + .div_clk_id = CLK_CK_APLL12_DIV_I2SIN0, + }, + [MT8196_I2SIN1_MCK] = { + .m_sel_id = CLK_CK_I2SIN1_M_SEL, + .div_clk_id = CLK_CK_APLL12_DIV_I2SIN1, + }, + [MT8196_FMI2S_MCK] = { + .m_sel_id = CLK_CK_FMI2S_M_SEL, + .div_clk_id = CLK_CK_APLL12_DIV_FMI2S, + }, + [MT8196_TDMOUT_MCK] = { + .m_sel_id = CLK_CK_TDMOUT_M_SEL, + .div_clk_id = CLK_CK_APLL12_DIV_TDMOUT_M, + }, + [MT8196_TDMOUT_BCK] = { + .m_sel_id = -1, + .div_clk_id = CLK_CK_APLL12_DIV_TDMOUT_B, + }, +}; + +int mt8196_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate) +{ + struct mt8196_afe_private *afe_priv = afe->platform_priv; + int apll = mt8196_get_apll_by_rate(afe, rate); + int apll_clk_id = apll == MT8196_APLL1 ? + CLK_CK_MUX_AUD_1 : CLK_CK_MUX_AUD_2; + int m_sel_id = 0; + int div_clk_id = 0; + int ret = 0; + + dev_dbg(afe->dev, "mck_id: %d, rate: %d\n", mck_id, rate); + + if (mck_id >= MT8196_MCK_NUM || mck_id < 0) + return -EINVAL; + + m_sel_id = mck_div[mck_id].m_sel_id; + div_clk_id = mck_div[mck_id].div_clk_id; + + /* select apll */ + if (m_sel_id >= 0) { + ret = clk_prepare_enable(afe_priv->clk[m_sel_id]); + if (ret) { + dev_err(afe->dev, "clk_prepare_enable %s fail %d\n", + aud_clks[m_sel_id], ret); + return ret; + } + ret = clk_set_parent(afe_priv->clk[m_sel_id], + afe_priv->clk[apll_clk_id]); + if (ret) { + dev_err(afe->dev, "clk_set_parent %s-%s fail %d\n", + aud_clks[m_sel_id], + aud_clks[apll_clk_id], ret); + return ret; + } + } + + /* enable div, set rate */ + if (div_clk_id < 0) { + dev_err(afe->dev, "invalid div_clk_id %d\n", div_clk_id); + return -EINVAL; + } + if (div_clk_id == CLK_CK_APLL12_DIV_TDMOUT_B) + rate = rate * 16; + ret = clk_prepare_enable(afe_priv->clk[div_clk_id]); + if (ret) { + dev_err(afe->dev, "clk_prepare_enable %s fail %d\n", + aud_clks[div_clk_id], ret); + return ret; + } + ret = clk_set_rate(afe_priv->clk[div_clk_id], rate); + if (ret) { + dev_err(afe->dev, "clk_set_rate %s, rate %d, fail %d\n", + aud_clks[div_clk_id], + rate, ret); + return ret; + } + return 0; +} + +int mt8196_mck_disable(struct mtk_base_afe *afe, int mck_id) +{ + struct mt8196_afe_private *afe_priv = afe->platform_priv; + int m_sel_id = 0; + int div_clk_id = 0; + + dev_dbg(afe->dev, "mck_id: %d.\n", mck_id); + + if (mck_id < 0) { + dev_err(afe->dev, "mck_id = %d < 0\n", mck_id); + return -EINVAL; + } + + m_sel_id = mck_div[mck_id].m_sel_id; + div_clk_id = mck_div[mck_id].div_clk_id; + + if (div_clk_id < 0) { + dev_err(afe->dev, "div_clk_id = %d < 0\n", + div_clk_id); + return -EINVAL; + } + clk_disable_unprepare(afe_priv->clk[div_clk_id]); + + if (m_sel_id >= 0) + clk_disable_unprepare(afe_priv->clk[m_sel_id]); + + return 0; +} + +int mt8196_init_clock(struct mtk_base_afe *afe) +{ + struct mt8196_afe_private *afe_priv = afe->platform_priv; + int ret = 0; + int i = 0; + + afe_priv->clk = devm_kcalloc(afe->dev, CLK_NUM, sizeof(*afe_priv->clk), + GFP_KERNEL); + if (!afe_priv->clk) + return -ENOMEM; + + for (i = 0; i < CLK_NUM; i++) { + afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]); + if (IS_ERR(afe_priv->clk[i])) { + dev_err(afe->dev, "devm_clk_get %s fail\n", aud_clks[i]); + return PTR_ERR(afe_priv->clk[i]); + } + } + + afe_priv->vlp_ck = syscon_regmap_lookup_by_phandle(afe->dev->of_node, + "vlpcksys"); + if (IS_ERR(afe_priv->vlp_ck)) { + dev_err(afe->dev, "Cannot find vlpcksys\n"); + return PTR_ERR(afe_priv->vlp_ck); + } + + afe_priv->cksys_ck = syscon_regmap_lookup_by_phandle(afe->dev->of_node, + "cksys"); + if (IS_ERR(afe_priv->cksys_ck)) { + dev_err(afe->dev, "Cannot find cksys controller\n"); + return PTR_ERR(afe_priv->cksys_ck); + } + + mt8196_afe_apll_init(afe); + + ret = mt8196_afe_disable_apll(afe); + if (ret) + return ret; + + return 0; +} diff --git a/sound/soc/mediatek/mt8196/mt8196-afe-clk.h b/sound/soc/mediatek/mt8196/mt8196-afe-clk.h new file mode 100644 index 000000000000..e2427e499027 --- /dev/null +++ b/sound/soc/mediatek/mt8196/mt8196-afe-clk.h @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * mt8196-afe-clk.h -- Mediatek 8196 afe clock ctrl definition + * + * Copyright (c) 2024 MediaTek Inc. + * Author: Darren Ye + */ + +#ifndef _MT8196_AFE_CLOCK_CTRL_H_ +#define _MT8196_AFE_CLOCK_CTRL_H_ + +/* vlp_cksys_clk: 0x1c016000 */ +#define VLP_APLL1_TUNER_CON0 0x02a4 +#define VLP_APLL2_TUNER_CON0 0x02a8 + +/* APLL */ +#define APLL1_W_NAME "APLL1" +#define APLL2_W_NAME "APLL2" + +enum { + MT8196_APLL1 = 0, + MT8196_APLL2, +}; + +enum { + /* afe clk */ + CLK_HOPPING = 0, + CLK_F26M, + CLK_APLL1, + CLK_APLL2, + CLK_APLL1_TUNER, + CLK_APLL2_TUNER, + /* vlp clk */ + CLK_VLP_MUX_AUDIOINTBUS, + CLK_VLP_MUX_AUD_ENG1, + CLK_VLP_MUX_AUD_ENG2, + CLK_VLP_MUX_AUDIO_H, + CLK_VLP_CLK26M, + /* ck clk */ + CLK_CK_MAINPLL_D4_D4, + CLK_CK_MUX_AUD_1, + CLK_CK_APLL1_CK, + CLK_CK_MUX_AUD_2, + CLK_CK_APLL2_CK, + CLK_CK_APLL1_D4, + CLK_CK_APLL2_D4, + CLK_CK_I2SIN0_M_SEL, + CLK_CK_I2SIN1_M_SEL, + CLK_CK_FMI2S_M_SEL, + CLK_CK_TDMOUT_M_SEL, + CLK_CK_APLL12_DIV_I2SIN0, + CLK_CK_APLL12_DIV_I2SIN1, + CLK_CK_APLL12_DIV_FMI2S, + CLK_CK_APLL12_DIV_TDMOUT_M, + CLK_CK_APLL12_DIV_TDMOUT_B, + CLK_CK_ADSP_SEL, + CLK_CLK26M, + CLK_NUM +}; + +struct mtk_base_afe; + +int mt8196_init_clock(struct mtk_base_afe *afe); +int mt8196_afe_enable_clock(struct mtk_base_afe *afe); +void mt8196_afe_disable_clock(struct mtk_base_afe *afe); +int mt8196_afe_dram_request(struct device *dev); +int mt8196_afe_dram_release(struct device *dev); +int mt8196_apll1_enable(struct mtk_base_afe *afe); +void mt8196_apll1_disable(struct mtk_base_afe *afe); +int mt8196_apll2_enable(struct mtk_base_afe *afe); +void mt8196_apll2_disable(struct mtk_base_afe *afe); +int mt8196_get_apll_rate(struct mtk_base_afe *afe, int apll); +int mt8196_get_apll_by_rate(struct mtk_base_afe *afe, int rate); +int mt8196_get_apll_by_name(struct mtk_base_afe *afe, const char *name); +int mt8196_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate); +int mt8196_mck_disable(struct mtk_base_afe *afe, int mck_id); + +#endif From patchwork Mon Apr 7 12:06:29 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Darren.Ye" X-Patchwork-Id: 879155 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 22AE924A045; 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Mon, 07 Apr 2025 20:11:01 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Mon, 7 Apr 2025 20:11:00 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Mon, 7 Apr 2025 20:10:59 +0800 From: Darren.Ye To: Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Jaroslav Kysela , Takashi Iwai , Linus Walleij , Bartosz Golaszewski CC: , , , , , , Darren Ye Subject: [PATCH v2 05/11] ASoC: mediatek: mt8196: support ADDA in platform driver Date: Mon, 7 Apr 2025 20:06:29 +0800 Message-ID: <20250407120708.26495-6-darren.ye@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250407120708.26495-1-darren.ye@mediatek.com> References: <20250407120708.26495-1-darren.ye@mediatek.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N From: Darren Ye Add mt8196 ADDA DAI driver support. Signed-off-by: Darren Ye --- sound/soc/mediatek/mt8196/mt8196-dai-adda.c | 918 ++++++++++++++++++++ 1 file changed, 918 insertions(+) create mode 100644 sound/soc/mediatek/mt8196/mt8196-dai-adda.c diff --git a/sound/soc/mediatek/mt8196/mt8196-dai-adda.c b/sound/soc/mediatek/mt8196/mt8196-dai-adda.c new file mode 100644 index 000000000000..1ccffd0030c3 --- /dev/null +++ b/sound/soc/mediatek/mt8196/mt8196-dai-adda.c @@ -0,0 +1,918 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MediaTek ALSA SoC Audio DAI ADDA Control + * + * Copyright (c) 2024 MediaTek Inc. + * Author: Darren Ye + */ + +#include +#include +#include "mt8196-afe-clk.h" +#include "mt8196-afe-common.h" +#include "mt8196-interconnection.h" + +#define MTKAIF4 + +enum { + UL_IIR_SW = 0, + UL_IIR_5HZ, + UL_IIR_10HZ, + UL_IIR_25HZ, + UL_IIR_50HZ, + UL_IIR_75HZ, +}; + +enum { + MTK_AFE_ADDA_UL_RATE_8K = 0, + MTK_AFE_ADDA_UL_RATE_16K = 1, + MTK_AFE_ADDA_UL_RATE_32K = 2, + MTK_AFE_ADDA_UL_RATE_48K = 3, + MTK_AFE_ADDA_UL_RATE_96K = 4, + MTK_AFE_ADDA_UL_RATE_192K = 5, + MTK_AFE_ADDA_UL_RATE_48K_HD = 6, +}; + +#ifdef MTKAIF4 +enum { + MTK_AFE_MTKAIF_RATE_8K = 0x0, + MTK_AFE_MTKAIF_RATE_12K = 0x1, + MTK_AFE_MTKAIF_RATE_16K = 0x2, + MTK_AFE_MTKAIF_RATE_24K = 0x3, + MTK_AFE_MTKAIF_RATE_32K = 0x4, + MTK_AFE_MTKAIF_RATE_48K = 0x5, + MTK_AFE_MTKAIF_RATE_64K = 0x6, + MTK_AFE_MTKAIF_RATE_96K = 0x7, + MTK_AFE_MTKAIF_RATE_128K = 0x8, + MTK_AFE_MTKAIF_RATE_192K = 0x9, + MTK_AFE_MTKAIF_RATE_256K = 0xa, + MTK_AFE_MTKAIF_RATE_384K = 0xb, + MTK_AFE_MTKAIF_RATE_11K = 0x10, + MTK_AFE_MTKAIF_RATE_22K = 0x11, + MTK_AFE_MTKAIF_RATE_44K = 0x12, + MTK_AFE_MTKAIF_RATE_88K = 0x13, + MTK_AFE_MTKAIF_RATE_176K = 0x14, + MTK_AFE_MTKAIF_RATE_352K = 0x15, +}; +#endif + +struct mtk_afe_adda_priv { + int dl_rate; + int ul_rate; +}; + +static unsigned int adda_ul_rate_transform(struct mtk_base_afe *afe, + unsigned int rate) +{ + switch (rate) { + case 8000: + return MTK_AFE_ADDA_UL_RATE_8K; + case 16000: + return MTK_AFE_ADDA_UL_RATE_16K; + case 32000: + return MTK_AFE_ADDA_UL_RATE_32K; + case 48000: + return MTK_AFE_ADDA_UL_RATE_48K; + case 96000: + return MTK_AFE_ADDA_UL_RATE_96K; + case 192000: + return MTK_AFE_ADDA_UL_RATE_192K; + default: + dev_info(afe->dev, "rate %d invalid, use 48kHz!!!\n", rate); + return MTK_AFE_ADDA_UL_RATE_48K; + } +} + +#ifdef MTKAIF4 +static unsigned int mtkaif_rate_transform(struct mtk_base_afe *afe, + unsigned int rate) +{ + switch (rate) { + case 8000: + return MTK_AFE_MTKAIF_RATE_8K; + case 11025: + return MTK_AFE_MTKAIF_RATE_11K; + case 12000: + return MTK_AFE_MTKAIF_RATE_12K; + case 16000: + return MTK_AFE_MTKAIF_RATE_16K; + case 22050: + return MTK_AFE_MTKAIF_RATE_22K; + case 24000: + return MTK_AFE_MTKAIF_RATE_24K; + case 32000: + return MTK_AFE_MTKAIF_RATE_32K; + case 44100: + return MTK_AFE_MTKAIF_RATE_44K; + case 48000: + return MTK_AFE_MTKAIF_RATE_48K; + case 96000: + return MTK_AFE_MTKAIF_RATE_96K; + case 192000: + return MTK_AFE_MTKAIF_RATE_192K; + default: + dev_info(afe->dev, "rate %d invalid, use 48kHz!!!\n", rate); + return MTK_AFE_MTKAIF_RATE_48K; + } +} +#endif + +enum { + SUPPLY_SEQ_ADDA_AFE_ON, + SUPPLY_SEQ_ADDA_FIFO, + SUPPLY_SEQ_ADDA_AP_DMIC, + SUPPLY_SEQ_ADDA_UL_ON, +}; + +static int mtk_adda_ul_src_dmic_phase_sync(struct mtk_base_afe *afe) +{ + dev_dbg(afe->dev, "set dmic phase sync\n"); + // ul0~1 + regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON1, + UL0_PHASE_SYNC_HCLK_SET_MASK_SFT, + 0x1 << UL0_PHASE_SYNC_HCLK_SET_SFT); + regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON1, + UL0_PHASE_SYNC_FCLK_SET_MASK_SFT, + 0x1 << UL0_PHASE_SYNC_FCLK_SET_SFT); + regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON1, + UL1_PHASE_SYNC_HCLK_SET_MASK_SFT, + 0x1 << UL1_PHASE_SYNC_HCLK_SET_SFT); + regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON1, + UL1_PHASE_SYNC_FCLK_SET_MASK_SFT, + 0x1 << UL1_PHASE_SYNC_FCLK_SET_SFT); + // dmic 0 + regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON1, + DMIC0_PHASE_SYNC_FCLK_SET_MASK_SFT, + 0x1 << DMIC0_PHASE_SYNC_FCLK_SET_SFT); + regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON1, + DMIC0_PHASE_SYNC_HCLK_SET_MASK_SFT, + 0x1 << DMIC0_PHASE_SYNC_HCLK_SET_SFT); + // dmic 1 + regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON1, + DMIC1_PHASE_SYNC_FCLK_SET_MASK_SFT, + 0x1 << DMIC1_PHASE_SYNC_FCLK_SET_SFT); + regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON1, + DMIC1_PHASE_SYNC_HCLK_SET_MASK_SFT, + 0x1 << DMIC1_PHASE_SYNC_HCLK_SET_SFT); + // ul0~1 phase sync clock + regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON0, + DMIC1_PHASE_HCLK_SEL_MASK_SFT, + 0x1 << DMIC1_PHASE_HCLK_SEL_SFT); + regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON0, + DMIC1_PHASE_FCLK_SEL_MASK_SFT, + 0x1 << DMIC1_PHASE_FCLK_SEL_SFT); + regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON0, + DMIC0_PHASE_HCLK_SEL_MASK_SFT, + 0x1 << DMIC0_PHASE_HCLK_SEL_SFT); + regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON0, + DMIC0_PHASE_FCLK_SEL_MASK_SFT, + 0x1 << DMIC0_PHASE_FCLK_SEL_SFT); + // dmic 0 + regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON0, + UL1_PHASE_HCLK_SEL_MASK_SFT, + 0x2 << UL1_PHASE_HCLK_SEL_SFT); + regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON0, + UL1_PHASE_FCLK_SEL_MASK_SFT, + 0x2 << UL1_PHASE_FCLK_SEL_SFT); + // dmic 1 + regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON0, + UL0_PHASE_HCLK_SEL_MASK_SFT, + 0x2 << UL0_PHASE_HCLK_SEL_SFT); + regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON0, + UL0_PHASE_FCLK_SEL_MASK_SFT, + 0x2 << UL0_PHASE_FCLK_SEL_SFT); + + return 0; +} + +static int mtk_adda_ul_src_dmic_phase_sync_clock(struct mtk_base_afe *afe) +{ + dev_dbg(afe->dev, "dmic turn on phase sync clk\n"); + regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON0, + UL_PHASE_SYNC_HCLK_1_ON_MASK_SFT, + 0x1 << UL_PHASE_SYNC_HCLK_1_ON_SFT); + regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON0, + UL_PHASE_SYNC_HCLK_0_ON_MASK_SFT, + 0x1 << UL_PHASE_SYNC_HCLK_0_ON_SFT); + + regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON0, + UL_PHASE_SYNC_FCLK_1_ON_MASK_SFT, + 0x1 << UL_PHASE_SYNC_FCLK_1_ON_SFT); + regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON0, + UL_PHASE_SYNC_FCLK_0_ON_MASK_SFT, + 0x1 << UL_PHASE_SYNC_FCLK_0_ON_SFT); + + return 0; +} + +static int mtk_adda_ul_src_dmic(struct mtk_base_afe *afe, int id) +{ + unsigned int reg_con0 = 0, reg_con1 = 0; + + dev_dbg(afe->dev, "id: %d\n", id); + + switch (id) { + case MT8196_DAI_ADDA: + case MT8196_DAI_AP_DMIC: + reg_con0 = AFE_ADDA_UL0_SRC_CON0; + reg_con1 = AFE_ADDA_UL0_SRC_CON1; + break; + case MT8196_DAI_ADDA_CH34: + case MT8196_DAI_AP_DMIC_CH34: + reg_con0 = AFE_ADDA_UL1_SRC_CON0; + reg_con1 = AFE_ADDA_UL1_SRC_CON1; + break; + default: + return -EINVAL; + } + + switch (id) { + case MT8196_DAI_AP_DMIC: + dev_dbg(afe->dev, "clear mtkaifv4 ul ch1ch2 mux\n"); + regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_RX_CFG0, + MTKAIFV4_UL_CH1CH2_IN_EN_SEL_MASK_SFT, + 0x0 << MTKAIFV4_UL_CH1CH2_IN_EN_SEL_SFT); + break; + case MT8196_DAI_AP_DMIC_CH34: + dev_dbg(afe->dev, "clear mtkaifv4 ul ch3ch4 mux\n"); + regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_RX_CFG0, + MTKAIFV4_UL_CH3CH4_IN_EN_SEL_MASK_SFT, + 0x0 << MTKAIFV4_UL_CH3CH4_IN_EN_SEL_SFT); + break; + default: + return -EINVAL; + } + + /* choose Phase */ + regmap_update_bits(afe->regmap, reg_con0, + UL_DMIC_PHASE_SEL_CH1_MASK_SFT, + 0x0 << UL_DMIC_PHASE_SEL_CH1_SFT); + regmap_update_bits(afe->regmap, reg_con0, + UL_DMIC_PHASE_SEL_CH2_MASK_SFT, + 0x4 << UL_DMIC_PHASE_SEL_CH2_SFT); + + /* dmic mode, 3.25M*/ + regmap_update_bits(afe->regmap, reg_con0, + DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT, + 0x0); + regmap_update_bits(afe->regmap, reg_con0, + DMIC_LOW_POWER_MODE_CTL_MASK_SFT, + 0x0); + + /* turn on dmic, ch1, ch2 */ + regmap_update_bits(afe->regmap, reg_con0, + UL_SDM_3_LEVEL_CTL_MASK_SFT, + 0x1 << UL_SDM_3_LEVEL_CTL_SFT); + regmap_update_bits(afe->regmap, reg_con0, + UL_MODE_3P25M_CH1_CTL_MASK_SFT, + 0x1 << UL_MODE_3P25M_CH1_CTL_SFT); + regmap_update_bits(afe->regmap, reg_con0, + UL_MODE_3P25M_CH2_CTL_MASK_SFT, + 0x1 << UL_MODE_3P25M_CH2_CTL_SFT); + + /* ul gain: gain = 0x7fff/positive_gain = 0x0/gain_mode = 0x10 */ + regmap_update_bits(afe->regmap, reg_con1, + ADDA_UL_GAIN_VALUE_MASK_SFT, + 0x7fff << ADDA_UL_GAIN_VALUE_SFT); + regmap_update_bits(afe->regmap, reg_con1, + ADDA_UL_POSTIVEGAIN_MASK_SFT, + 0x0 << ADDA_UL_POSTIVEGAIN_SFT); + /* gain_mode = 0x10: Add 0.5 gain at CIC output */ + regmap_update_bits(afe->regmap, reg_con1, + GAIN_MODE_MASK_SFT, + 0x02 << GAIN_MODE_SFT); + return 0; +} + +static int mtk_adda_ul_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); + + dev_dbg(afe->dev, "name %s, event 0x%x\n", w->name, event); + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + break; + case SND_SOC_DAPM_POST_PMD: + /* should delayed 1/fs(smallest is 8k) = 125us before afe off */ + usleep_range(120, 130); + break; + default: + break; + } + + return 0; +} + +static int mtk_adda_ch34_ul_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); + + dev_dbg(afe->dev, "name %s, event 0x%x\n", w->name, event); + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + break; + case SND_SOC_DAPM_POST_PMD: + /* should delayed 1/fs(smallest is 8k) = 125us before afe off */ + usleep_range(120, 130); + break; + default: + break; + } + + return 0; +} + +static int mtk_adda_ul_ap_dmic_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); + + dev_info(afe->dev, "name %s, event 0x%x\n", w->name, event); + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + break; + case SND_SOC_DAPM_POST_PMD: + /* should delayed 1/fs(smallest is 8k) = 125us before afe off */ + usleep_range(120, 130); + break; + default: + break; + } + + return 0; +} + +static int mtk_adda_ch34_ul_ap_dmic_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); + + dev_dbg(afe->dev, "name %s, event 0x%x\n", w->name, event); + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + break; + case SND_SOC_DAPM_POST_PMD: + /* should delayed 1/fs(smallest is 8k) = 125us before afe off */ + usleep_range(120, 130); + break; + default: + break; + } + + return 0; +} + +/* mtkaif dmic */ +static const char *const mt8196_adda_off_on_str[] = { + "Off", "On" +}; + +static const struct soc_enum mt8196_adda_enum[] = { + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mt8196_adda_off_on_str), + mt8196_adda_off_on_str), +}; + +static const struct snd_kcontrol_new mtk_adda_controls[] = { +}; + +/* ADDA UL MUX */ +#define ADDA_UL_MUX_MASK 0x3 +enum { + ADDA_UL_MUX_MTKAIF = 0, + ADDA_UL_MUX_AP_DMIC, + ADDA_UL_MUX_AP_DMIC_MULTICH, +}; + +static const char *const adda_ul_mux_map[] = { + "MTKAIF", "AP_DMIC", "AP_DMIC_MULTI_CH", +}; + +static int adda_ul_map_value[] = { + ADDA_UL_MUX_MTKAIF, + ADDA_UL_MUX_AP_DMIC, + ADDA_UL_MUX_AP_DMIC_MULTICH, +}; + +static SOC_VALUE_ENUM_SINGLE_DECL(adda_ul_mux_map_enum, + SND_SOC_NOPM, + 0, + ADDA_UL_MUX_MASK, + adda_ul_mux_map, + adda_ul_map_value); + +static const struct snd_kcontrol_new adda_ul_mux_control = + SOC_DAPM_ENUM("ADDA_UL_MUX Select", adda_ul_mux_map_enum); + +static const struct snd_kcontrol_new adda_ch34_ul_mux_control = + SOC_DAPM_ENUM("ADDA_CH34_UL_MUX Select", adda_ul_mux_map_enum); + +static const struct snd_soc_dapm_widget mtk_dai_adda_widgets[] = { + /* inter-connections */ + SND_SOC_DAPM_SUPPLY_S("ADDA Enable", SUPPLY_SEQ_ADDA_AFE_ON, + AUDIO_ENGEN_CON0, AUDIO_F3P25M_EN_ON_SFT, 0, + NULL, 0), + SND_SOC_DAPM_SUPPLY_S("ADDA Capture Enable", SUPPLY_SEQ_ADDA_UL_ON, + AFE_ADDA_UL0_SRC_CON0, + UL_SRC_ON_TMP_CTL_SFT, 0, + mtk_adda_ul_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_SUPPLY_S("ADDA CH34 Capture Enable", SUPPLY_SEQ_ADDA_UL_ON, + AFE_ADDA_UL1_SRC_CON0, + UL_SRC_ON_TMP_CTL_SFT, 0, + mtk_adda_ch34_ul_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_SUPPLY_S("AP_DMIC_EN", SUPPLY_SEQ_ADDA_AP_DMIC, + AFE_ADDA_UL0_SRC_CON0, + UL_AP_DMIC_ON_SFT, 0, + mtk_adda_ul_ap_dmic_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_SUPPLY_S("AP_DMIC_CH34_EN", SUPPLY_SEQ_ADDA_AP_DMIC, + AFE_ADDA_UL1_SRC_CON0, + UL_AP_DMIC_ON_SFT, 0, + mtk_adda_ch34_ul_ap_dmic_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_SUPPLY_S("ADDA_FIFO", SUPPLY_SEQ_ADDA_FIFO, + AFE_ADDA_UL0_SRC_CON1, + FIFO_SOFT_RST_SFT, 1, + NULL, 0), + SND_SOC_DAPM_SUPPLY_S("ADDA_CH34_FIFO", SUPPLY_SEQ_ADDA_FIFO, + AFE_ADDA_UL1_SRC_CON1, + FIFO_SOFT_RST_SFT, 1, + NULL, 0), + SND_SOC_DAPM_MUX("ADDA_UL_Mux", SND_SOC_NOPM, 0, 0, + &adda_ul_mux_control), + SND_SOC_DAPM_MUX("ADDA_CH34_UL_Mux", SND_SOC_NOPM, 0, 0, + &adda_ch34_ul_mux_control), + SND_SOC_DAPM_INPUT("AP_DMIC_INPUT"), + SND_SOC_DAPM_INPUT("AP_DMIC_CH34_INPUT"), +}; + +static const struct snd_soc_dapm_route mtk_dai_adda_routes[] = { + /* capture */ + {"ADDA_UL_Mux", "MTKAIF", "ADDA Capture"}, + {"ADDA_UL_Mux", "AP_DMIC", "AP DMIC Capture"}, + {"ADDA_UL_Mux", "AP_DMIC_MULTI_CH", "AP DMIC MULTICH Capture"}, + + {"ADDA_CH34_UL_Mux", "MTKAIF", "ADDA CH34 Capture"}, + {"ADDA_CH34_UL_Mux", "AP_DMIC", "AP DMIC CH34 Capture"}, + {"ADDA_CH34_UL_Mux", "AP_DMIC_MULTI_CH", "AP DMIC MULTICH Capture"}, + + {"AP DMIC Capture", NULL, "ADDA Enable"}, + {"AP DMIC Capture", NULL, "ADDA Capture Enable"}, + {"AP DMIC Capture", NULL, "ADDA_FIFO"}, + {"AP DMIC Capture", NULL, "AP_DMIC_EN"}, + + {"AP DMIC CH34 Capture", NULL, "ADDA Enable"}, + {"AP DMIC CH34 Capture", NULL, "ADDA CH34 Capture Enable"}, + {"AP DMIC CH34 Capture", NULL, "ADDA_CH34_FIFO"}, + {"AP DMIC CH34 Capture", NULL, "AP_DMIC_CH34_EN"}, + + {"AP DMIC MULTICH Capture", NULL, "ADDA Enable"}, + {"AP DMIC MULTICH Capture", NULL, "ADDA Capture Enable"}, + {"AP DMIC MULTICH Capture", NULL, "ADDA CH34 Capture Enable"}, + {"AP DMIC MULTICH Capture", NULL, "ADDA_FIFO"}, + {"AP DMIC MULTICH Capture", NULL, "ADDA_CH34_FIFO"}, + {"AP DMIC MULTICH Capture", NULL, "AP_DMIC_EN"}, + {"AP DMIC MULTICH Capture", NULL, "AP_DMIC_CH34_EN"}, + {"AP DMIC Capture", NULL, "AP_DMIC_INPUT"}, + {"AP DMIC CH34 Capture", NULL, "AP_DMIC_CH34_INPUT"}, + {"AP DMIC MULTICH Capture", NULL, "AP_DMIC_INPUT"}, +}; + +/* dai ops */ +static int mtk_dai_adda_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); + struct mt8196_afe_private *afe_priv = afe->platform_priv; + unsigned int rate = params_rate(params); +#ifdef MTKAIF4 + unsigned int mtkaif_rate = 0; +#endif + int id = dai->id; + struct mtk_afe_adda_priv *adda_priv; + + if (id >= MT8196_DAI_NUM || id < 0) + return -EINVAL; + + adda_priv = afe_priv->dai_priv[id]; + + dev_info(afe->dev, "id %d, stream %d, rate %d\n", + id, + substream->stream, + rate); + + if (!adda_priv) + return -EINVAL; + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + adda_priv->dl_rate = rate; + +#ifdef MTKAIF4 + /* get mtkaif dl rate */ + mtkaif_rate = + mtkaif_rate_transform(afe, adda_priv->dl_rate); +#endif + if (id == MT8196_DAI_ADDA) { +#ifdef MTKAIF4 + /* MTKAIF sample rate config */ + regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_TX_CFG0, + MTKAIFV4_TXIF_INPUT_MODE_MASK_SFT, + mtkaif_rate << MTKAIFV4_TXIF_INPUT_MODE_SFT); + /* AFE_ADDA_MTKAIFV4_TX_CFG0 */ + regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_TX_CFG0, + MTKAIFV4_TXIF_FOUR_CHANNEL_MASK_SFT, + 0x0 << MTKAIFV4_TXIF_FOUR_CHANNEL_SFT); + regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_TX_CFG0, + MTKAIFV4_ADDA_OUT_EN_SEL_MASK_SFT, + 0x1 << MTKAIFV4_ADDA_OUT_EN_SEL_SFT); + regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_TX_CFG0, + MTKAIFV4_ADDA6_OUT_EN_SEL_MASK_SFT, + 0x1 << MTKAIFV4_ADDA6_OUT_EN_SEL_SFT); + regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_TX_CFG0, + MTKAIFV4_TXIF_V4_MASK_SFT, + 0x1 << MTKAIFV4_TXIF_V4_SFT); + regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_TX_CFG0, + MTKAIFV4_TXIF_EN_SEL_MASK_SFT, + 0x0 << MTKAIFV4_TXIF_EN_SEL_SFT); +#endif + /* clean predistortion */ + } else { +#ifdef MTKAIF4 + /* MTKAIF sample rate config */ + regmap_update_bits(afe->regmap, AFE_ADDA6_MTKAIFV4_TX_CFG0, + ADDA6_MTKAIFV4_TXIF_INPUT_MODE_MASK_SFT, + mtkaif_rate << ADDA6_MTKAIFV4_TXIF_INPUT_MODE_SFT); + /* AFE_ADDA6_MTKAIFV4_TX_CFG0 */ + regmap_update_bits(afe->regmap, AFE_ADDA6_MTKAIFV4_TX_CFG0, + ADDA6_MTKAIFV4_TXIF_FOUR_CHANNEL_MASK_SFT, + 0x0 << ADDA6_MTKAIFV4_TXIF_FOUR_CHANNEL_SFT); + regmap_update_bits(afe->regmap, AFE_ADDA6_MTKAIFV4_TX_CFG0, + ADDA6_MTKAIFV4_TXIF_EN_SEL_MASK_SFT, + 0x1 << ADDA6_MTKAIFV4_TXIF_EN_SEL_SFT); +#endif + } + } else { + unsigned int voice_mode = 0; + unsigned int ul_src_con0 = 0; /* default value */ + + adda_priv->ul_rate = rate; + +#ifdef MTKAIF4 + /* get mtkaif dl rate */ + mtkaif_rate = + mtkaif_rate_transform(afe, adda_priv->ul_rate); +#endif + + voice_mode = adda_ul_rate_transform(afe, rate); + + ul_src_con0 |= (voice_mode << 17) & (0x7 << 17); + + /* enable iir */ + ul_src_con0 |= (1 << UL_IIR_ON_TMP_CTL_SFT) & + UL_IIR_ON_TMP_CTL_MASK_SFT; + ul_src_con0 |= (UL_IIR_SW << UL_IIRMODE_CTL_SFT) & + UL_IIRMODE_CTL_MASK_SFT; + + regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_RX_CFG0, + MTKAIFV4_RXIF_INPUT_MODE_MASK_SFT, + mtkaif_rate << MTKAIFV4_RXIF_INPUT_MODE_SFT); + + regmap_update_bits(afe->regmap, AFE_ADDA6_MTKAIFV4_RX_CFG0, + ADDA6_MTKAIFV4_RXIF_INPUT_MODE_MASK_SFT, + mtkaif_rate << ADDA6_MTKAIFV4_RXIF_INPUT_MODE_SFT); + + switch (id) { + case MT8196_DAI_ADDA: + case MT8196_DAI_AP_DMIC: + case MT8196_DAI_AP_DMIC_MULTICH: +#ifdef MTKAIF4 + regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_RX_CFG0, + MTKAIFV4_RXIF_INPUT_MODE_MASK_SFT, + mtkaif_rate << MTKAIFV4_RXIF_INPUT_MODE_SFT); + /* AFE_ADDA_MTKAIFV4_RX_CFG0 */ + regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_RX_CFG0, + MTKAIFV4_RXIF_FOUR_CHANNEL_MASK_SFT, + 0x1 << MTKAIFV4_RXIF_FOUR_CHANNEL_SFT); + regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_RX_CFG0, + MTKAIFV4_RXIF_EN_SEL_MASK_SFT, + 0x0 << MTKAIFV4_RXIF_EN_SEL_SFT); + /* [28] loopback mode + * 0: loopback adda tx to adda rx + * 1: loopback adda6 tx to adda rx + */ + regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_RX_CFG0, + MTKAIFV4_TXIF_EN_SEL_MASK_SFT, + 0x0 << MTKAIFV4_TXIF_EN_SEL_SFT); + + regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_RX_CFG0, + MTKAIFV4_UL_CH1CH2_IN_EN_SEL_MASK_SFT, + 0x1 << MTKAIFV4_UL_CH1CH2_IN_EN_SEL_SFT); + regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_RX_CFG0, + MTKAIFV4_UL_CH3CH4_IN_EN_SEL_MASK_SFT, + 0x1 << MTKAIFV4_UL_CH3CH4_IN_EN_SEL_SFT); +#endif + + /* 35Hz @ 48k */ + regmap_write(afe->regmap, + AFE_ADDA_UL1_IIR_COEF_02_01, 0x00000000); + regmap_write(afe->regmap, + AFE_ADDA_UL1_IIR_COEF_04_03, 0x00003FB8); + regmap_write(afe->regmap, + AFE_ADDA_UL1_IIR_COEF_06_05, 0x3FB80000); + regmap_write(afe->regmap, + AFE_ADDA_UL1_IIR_COEF_08_07, 0x3FB80000); + regmap_write(afe->regmap, + AFE_ADDA_UL1_IIR_COEF_10_09, 0x0000C048); + + regmap_write(afe->regmap, + AFE_ADDA_UL1_SRC_CON0, ul_src_con0); + + /* mtkaif_rxif_data_mode = 0, amic */ + regmap_update_bits(afe->regmap, + AFE_MTKAIF1_RX_CFG0, + 0x1 << 0, + 0x0 << 0); + + /* 35Hz @ 48k */ + regmap_write(afe->regmap, + AFE_ADDA_UL0_IIR_COEF_02_01, 0x00000000); + regmap_write(afe->regmap, + AFE_ADDA_UL0_IIR_COEF_04_03, 0x00003FB8); + regmap_write(afe->regmap, + AFE_ADDA_UL0_IIR_COEF_06_05, 0x3FB80000); + regmap_write(afe->regmap, + AFE_ADDA_UL0_IIR_COEF_08_07, 0x3FB80000); + regmap_write(afe->regmap, + AFE_ADDA_UL0_IIR_COEF_10_09, 0x0000C048); + + regmap_write(afe->regmap, + AFE_ADDA_UL0_SRC_CON0, ul_src_con0); + + /* mtkaif_rxif_data_mode = 0, amic */ + regmap_update_bits(afe->regmap, + AFE_MTKAIF0_RX_CFG0, + 0x1 << 0, + 0x0 << 0); + break; + case MT8196_DAI_ADDA_CH34: + case MT8196_DAI_AP_DMIC_CH34: +#ifdef MTKAIF4 + /* AFE_ADDA_MTKAIFV4_RX_CFG0 */ + regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_RX_CFG0, + MTKAIFV4_RXIF_FOUR_CHANNEL_MASK_SFT, + 0x1 << MTKAIFV4_RXIF_FOUR_CHANNEL_SFT); + regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_RX_CFG0, + MTKAIFV4_RXIF_EN_SEL_MASK_SFT, + 0x0 << MTKAIFV4_RXIF_EN_SEL_SFT); + + regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_RX_CFG0, + MTKAIFV4_UL_CH1CH2_IN_EN_SEL_MASK_SFT, + 0x1 << MTKAIFV4_UL_CH1CH2_IN_EN_SEL_SFT); + regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_RX_CFG0, + MTKAIFV4_UL_CH3CH4_IN_EN_SEL_MASK_SFT, + 0x1 << MTKAIFV4_UL_CH3CH4_IN_EN_SEL_SFT); + +#endif + /* 35Hz @ 48k */ + regmap_write(afe->regmap, + AFE_ADDA_UL1_IIR_COEF_02_01, 0x00000000); + regmap_write(afe->regmap, + AFE_ADDA_UL1_IIR_COEF_04_03, 0x00003FB8); + regmap_write(afe->regmap, + AFE_ADDA_UL1_IIR_COEF_06_05, 0x3FB80000); + regmap_write(afe->regmap, + AFE_ADDA_UL1_IIR_COEF_08_07, 0x3FB80000); + regmap_write(afe->regmap, + AFE_ADDA_UL1_IIR_COEF_10_09, 0x0000C048); + + regmap_write(afe->regmap, + AFE_ADDA_UL1_SRC_CON0, ul_src_con0); + + /* mtkaif_rxif_data_mode = 0, amic */ + regmap_update_bits(afe->regmap, + AFE_MTKAIF1_RX_CFG0, + 0x1 << 0, + 0x0 << 0); + + break; + case MT8196_DAI_ADDA_CH56: + regmap_update_bits(afe->regmap, AFE_ADDA6_MTKAIFV4_RX_CFG0, + ADDA6_MTKAIFV4_RXIF_INPUT_MODE_MASK_SFT, + mtkaif_rate << ADDA6_MTKAIFV4_RXIF_INPUT_MODE_SFT); + /* AFE_ADDA6_MTKAIFV4_RX_CFG0 */ + regmap_update_bits(afe->regmap, AFE_ADDA6_MTKAIFV4_RX_CFG0, + ADDA6_MTKAIFV4_RXIF_FOUR_CHANNEL_MASK_SFT, + 0x1 << ADDA6_MTKAIFV4_RXIF_FOUR_CHANNEL_SFT); + regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_RX_CFG0, + MTKAIFV4_UL_CH5CH6_IN_EN_SEL_MASK_SFT, + 0x1 << MTKAIFV4_UL_CH5CH6_IN_EN_SEL_SFT); + regmap_update_bits(afe->regmap, AFE_ADDA6_MTKAIFV4_RX_CFG0, + ADDA6_MTKAIFV4_RXIF_EN_SEL_MASK_SFT, + 0x1 << ADDA6_MTKAIFV4_RXIF_EN_SEL_SFT); + break; + default: + break; + } + + /* ap dmic */ + switch (id) { + case MT8196_DAI_AP_DMIC: + case MT8196_DAI_AP_DMIC_CH34: + mtk_adda_ul_src_dmic(afe, id); + break; + case MT8196_DAI_AP_DMIC_MULTICH: + regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON1, + DMIC_CLK_PHASE_SYNC_SET_MASK_SFT, + 0x1 << DMIC_CLK_PHASE_SYNC_SET_SFT); + mtk_adda_ul_src_dmic_phase_sync(afe); + mtk_adda_ul_src_dmic(afe, MT8196_DAI_AP_DMIC); + mtk_adda_ul_src_dmic(afe, MT8196_DAI_AP_DMIC_CH34); + mtk_adda_ul_src_dmic_phase_sync_clock(afe); + break; + default: + break; + } + } + + return 0; +} + +static const struct snd_soc_dai_ops mtk_dai_adda_ops = { + .hw_params = mtk_dai_adda_hw_params, +}; + +/* dai driver */ +#define MTK_ADDA_PLAYBACK_RATES (SNDRV_PCM_RATE_8000_48000 |\ + SNDRV_PCM_RATE_96000 |\ + SNDRV_PCM_RATE_192000) + +#define MTK_ADDA_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\ + SNDRV_PCM_RATE_16000 |\ + SNDRV_PCM_RATE_32000 |\ + SNDRV_PCM_RATE_48000 |\ + SNDRV_PCM_RATE_96000 |\ + SNDRV_PCM_RATE_192000) + +#define MTK_ADDA_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ + SNDRV_PCM_FMTBIT_S24_LE |\ + SNDRV_PCM_FMTBIT_S32_LE) + +static struct snd_soc_dai_driver mtk_dai_adda_driver[] = { + { + .name = "ADDA", + .id = MT8196_DAI_ADDA, + .playback = { + .stream_name = "ADDA Playback", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_ADDA_PLAYBACK_RATES, + .formats = MTK_ADDA_FORMATS, + }, + .capture = { + .stream_name = "ADDA Capture", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_ADDA_CAPTURE_RATES, + .formats = MTK_ADDA_FORMATS, + }, + .ops = &mtk_dai_adda_ops, + }, + { + .name = "ADDA_CH34", + .id = MT8196_DAI_ADDA_CH34, + .playback = { + .stream_name = "ADDA CH34 Playback", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_ADDA_PLAYBACK_RATES, + .formats = MTK_ADDA_FORMATS, + }, + .capture = { + .stream_name = "ADDA CH34 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_ADDA_CAPTURE_RATES, + .formats = MTK_ADDA_FORMATS, + }, + .ops = &mtk_dai_adda_ops, + }, + { + .name = "ADDA_CH56", + .id = MT8196_DAI_ADDA_CH56, + .capture = { + .stream_name = "ADDA CH56 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_ADDA_CAPTURE_RATES, + .formats = MTK_ADDA_FORMATS, + }, + .ops = &mtk_dai_adda_ops, + }, + { + .name = "AP_DMIC", + .id = MT8196_DAI_AP_DMIC, + .capture = { + .stream_name = "AP DMIC Capture", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_ADDA_CAPTURE_RATES, + .formats = MTK_ADDA_FORMATS, + }, + .ops = &mtk_dai_adda_ops, + }, + { + .name = "AP_DMIC_CH34", + .id = MT8196_DAI_AP_DMIC_CH34, + .capture = { + .stream_name = "AP DMIC CH34 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_ADDA_CAPTURE_RATES, + .formats = MTK_ADDA_FORMATS, + }, + .ops = &mtk_dai_adda_ops, + }, + { + .name = "AP_DMIC_MULTICH", + .id = MT8196_DAI_AP_DMIC_MULTICH, + .capture = { + .stream_name = "AP DMIC MULTICH Capture", + .channels_min = 1, + .channels_max = 4, + .rates = MTK_ADDA_CAPTURE_RATES, + .formats = MTK_ADDA_FORMATS, + }, + .ops = &mtk_dai_adda_ops, + }, +}; + +static int init_adda_priv_data(struct mtk_base_afe *afe) +{ + struct mt8196_afe_private *afe_priv = afe->platform_priv; + struct mtk_afe_adda_priv *adda_priv; + static const int adda_dai_list[] = { + MT8196_DAI_ADDA, + MT8196_DAI_ADDA_CH34, + MT8196_DAI_ADDA_CH56, + MT8196_DAI_AP_DMIC_MULTICH + }; + int i; + + for (i = 0; i < ARRAY_SIZE(adda_dai_list); i++) { + adda_priv = devm_kzalloc(afe->dev, + sizeof(struct mtk_afe_adda_priv), + GFP_KERNEL); + if (!adda_priv) + return -ENOMEM; + + afe_priv->dai_priv[adda_dai_list[i]] = adda_priv; + } + + /* ap dmic priv share with adda */ + afe_priv->dai_priv[MT8196_DAI_AP_DMIC] = + afe_priv->dai_priv[MT8196_DAI_ADDA]; + afe_priv->dai_priv[MT8196_DAI_AP_DMIC_CH34] = + afe_priv->dai_priv[MT8196_DAI_ADDA_CH34]; + + return 0; +} + +int mt8196_dai_adda_register(struct mtk_base_afe *afe) +{ + struct mtk_base_afe_dai *dai; + + dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL); + if (!dai) + return -ENOMEM; + + list_add(&dai->list, &afe->sub_dais); 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Mon, 07 Apr 2025 20:11:04 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by MTKMBS09N1.mediatek.inc (172.21.101.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Mon, 7 Apr 2025 20:11:03 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Mon, 7 Apr 2025 20:11:02 +0800 From: Darren.Ye To: Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Jaroslav Kysela , Takashi Iwai , Linus Walleij , Bartosz Golaszewski CC: , , , , , , Darren Ye Subject: [PATCH v2 06/11] ASoC: mediatek: mt8196: support I2S in platform driver Date: Mon, 7 Apr 2025 20:06:30 +0800 Message-ID: <20250407120708.26495-7-darren.ye@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250407120708.26495-1-darren.ye@mediatek.com> References: <20250407120708.26495-1-darren.ye@mediatek.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N From: Darren Ye Add mt8196 I2S DAI driver support. Signed-off-by: Darren Ye --- sound/soc/mediatek/mt8196/mt8196-dai-i2s.c | 4080 ++++++++++++++++++++ 1 file changed, 4080 insertions(+) create mode 100644 sound/soc/mediatek/mt8196/mt8196-dai-i2s.c diff --git a/sound/soc/mediatek/mt8196/mt8196-dai-i2s.c b/sound/soc/mediatek/mt8196/mt8196-dai-i2s.c new file mode 100644 index 000000000000..1e3bcb586ec5 --- /dev/null +++ b/sound/soc/mediatek/mt8196/mt8196-dai-i2s.c @@ -0,0 +1,4080 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MediaTek ALSA SoC Audio DAI I2S Control + * + * Copyright (c) 2024 MediaTek Inc. + * Author: Darren Ye + */ + +#include +#include +#include +#include "mt8196-afe-clk.h" +#include "mt8196-afe-common.h" +#include "mt8196-interconnection.h" +#include "mtk-afe-fe-dai.h" + +#define ETDM_22M_CLOCK_THRES 11289600 + +#define FM_SRC_CAIL +enum { + ETDM_CLK_SOURCE_H26M = 0, + ETDM_CLK_SOURCE_APLL = 1, + ETDM_CLK_SOURCE_SPDIF = 2, + ETDM_CLK_SOURCE_HDMI = 3, + ETDM_CLK_SOURCE_EARC = 4, + ETDM_CLK_SOURCE_LINEIN = 5, +}; + +enum { + ETDM_RELATCH_SEL_H26M = 0, + ETDM_RELATCH_SEL_APLL = 1, +}; + +enum { + ETDM_RATE_8K = 0, + ETDM_RATE_12K = 1, + ETDM_RATE_16K = 2, + ETDM_RATE_24K = 3, + ETDM_RATE_32K = 4, + ETDM_RATE_48K = 5, + ETDM_RATE_64K = 6, //not support + ETDM_RATE_96K = 7, + ETDM_RATE_128K = 8, //not support + ETDM_RATE_192K = 9, + ETDM_RATE_256K = 10, //not support + ETDM_RATE_384K = 11, + ETDM_RATE_11025 = 16, + ETDM_RATE_22050 = 17, + ETDM_RATE_44100 = 18, + ETDM_RATE_88200 = 19, + ETDM_RATE_176400 = 20, + ETDM_RATE_352800 = 21, +}; + +enum { + ETDM_CONN_8K = 0, + ETDM_CONN_11K = 1, + ETDM_CONN_12K = 2, + ETDM_CONN_16K = 4, + ETDM_CONN_22K = 5, + ETDM_CONN_24K = 6, + ETDM_CONN_32K = 8, + ETDM_CONN_44K = 9, + ETDM_CONN_48K = 10, + ETDM_CONN_88K = 13, + ETDM_CONN_96K = 14, + ETDM_CONN_176K = 17, + ETDM_CONN_192K = 18, + ETDM_CONN_352K = 21, + ETDM_CONN_384K = 22, +}; + +enum { + ETDM_WLEN_8_BIT = 0x7, + ETDM_WLEN_16_BIT = 0xf, + ETDM_WLEN_32_BIT = 0x1f, +}; + +enum { + ETDM_SLAVE_SEL_ETDMIN0_MASTER = 0, + ETDM_SLAVE_SEL_ETDMIN0_SLAVE = 1, + ETDM_SLAVE_SEL_ETDMIN1_MASTER = 2, + ETDM_SLAVE_SEL_ETDMIN1_SLAVE = 3, + ETDM_SLAVE_SEL_ETDMIN2_MASTER = 4, + ETDM_SLAVE_SEL_ETDMIN2_SLAVE = 5, + ETDM_SLAVE_SEL_ETDMIN3_MASTER = 6, + ETDM_SLAVE_SEL_ETDMIN3_SLAVE = 7, + ETDM_SLAVE_SEL_ETDMOUT0_MASTER = 8, + ETDM_SLAVE_SEL_ETDMOUT0_SLAVE = 9, + ETDM_SLAVE_SEL_ETDMOUT1_MASTER = 10, + ETDM_SLAVE_SEL_ETDMOUT1_SLAVE = 11, + ETDM_SLAVE_SEL_ETDMOUT2_MASTER = 12, + ETDM_SLAVE_SEL_ETDMOUT2_SLAVE = 13, + ETDM_SLAVE_SEL_ETDMOUT3_MASTER = 14, + ETDM_SLAVE_SEL_ETDMOUT3_SLAVE = 15, +}; + +enum { + ETDM_SLAVE_SEL_ETDMIN4_MASTER = 0, + ETDM_SLAVE_SEL_ETDMIN4_SLAVE = 1, + ETDM_SLAVE_SEL_ETDMIN5_MASTER = 2, + ETDM_SLAVE_SEL_ETDMIN5_SLAVE = 3, + ETDM_SLAVE_SEL_ETDMIN6_MASTER = 4, + ETDM_SLAVE_SEL_ETDMIN6_SLAVE = 5, + ETDM_SLAVE_SEL_ETDMIN7_MASTER = 6, + ETDM_SLAVE_SEL_ETDMIN7_SLAVE = 7, + ETDM_SLAVE_SEL_ETDMOUT4_MASTER = 8, + ETDM_SLAVE_SEL_ETDMOUT4_SLAVE = 9, + ETDM_SLAVE_SEL_ETDMOUT5_MASTER = 10, + ETDM_SLAVE_SEL_ETDMOUT5_SLAVE = 11, + ETDM_SLAVE_SEL_ETDMOUT6_MASTER = 12, + ETDM_SLAVE_SEL_ETDMOUT6_SLAVE = 13, + ETDM_SLAVE_SEL_ETDMOUT7_MASTER = 14, + ETDM_SLAVE_SEL_ETDMOUT7_SLAVE = 15, +}; + +enum { + MTK_DAI_ETDM_FORMAT_I2S = 0, + MTK_DAI_ETDM_FORMAT_LJ, + MTK_DAI_ETDM_FORMAT_RJ, + MTK_DAI_ETDM_FORMAT_EIAJ, + MTK_DAI_ETDM_FORMAT_DSPA, + MTK_DAI_ETDM_FORMAT_DSPB, +}; + +static unsigned int get_etdm_wlen(snd_pcm_format_t format) +{ + unsigned int wlen = 0; + + /* The reg_word_length should be >= reg_bit_length */ + wlen = snd_pcm_format_physical_width(format); + + if (wlen < 16) + return ETDM_WLEN_16_BIT; + else + return ETDM_WLEN_32_BIT; +} + +static unsigned int get_etdm_lrck_width(snd_pcm_format_t format) +{ + /* The valid data bit number should be large than 7 due to hardware limitation. */ + return snd_pcm_format_physical_width(format) - 1; +} + +static unsigned int get_etdm_rate(unsigned int rate) +{ + switch (rate) { + case 8000: + return ETDM_RATE_8K; + case 12000: + return ETDM_RATE_12K; + case 16000: + return ETDM_RATE_16K; + case 24000: + return ETDM_RATE_24K; + case 32000: + return ETDM_RATE_32K; + case 48000: + return ETDM_RATE_48K; + case 64000: + return ETDM_RATE_64K; + case 96000: + return ETDM_RATE_96K; + case 128000: + return ETDM_RATE_128K; + case 192000: + return ETDM_RATE_192K; + case 256000: + return ETDM_RATE_256K; + case 384000: + return ETDM_RATE_384K; + case 11025: + return ETDM_RATE_11025; + case 22050: + return ETDM_RATE_22050; + case 44100: + return ETDM_RATE_44100; + case 88200: + return ETDM_RATE_88200; + case 176400: + return ETDM_RATE_176400; + case 352800: + return ETDM_RATE_352800; + default: + return 0; + } +} + +static unsigned int get_etdm_inconn_rate(unsigned int rate) +{ + switch (rate) { + case 8000: + return ETDM_CONN_8K; + case 12000: + return ETDM_CONN_12K; + case 16000: + return ETDM_CONN_16K; + case 24000: + return ETDM_CONN_24K; + case 32000: + return ETDM_CONN_32K; + case 48000: + return ETDM_CONN_48K; + case 96000: + return ETDM_CONN_96K; + case 192000: + return ETDM_CONN_192K; + case 384000: + return ETDM_CONN_384K; + case 11025: + return ETDM_CONN_11K; + case 22050: + return ETDM_CONN_22K; + case 44100: + return ETDM_CONN_44K; + case 88200: + return ETDM_CONN_88K; + case 176400: + return ETDM_CONN_176K; + case 352800: + return ETDM_CONN_352K; + default: + return 0; + } +} + +struct mtk_afe_i2s_priv { + int id; + int rate; /* for determine which apll to use */ + int low_jitter_en; + + const char *share_property_name; + int share_i2s_id; + + int mclk_id; + int mclk_rate; + int mclk_apll; + + int ch_num; + int sync; + int ip_mode; + int lpbk_mode; + unsigned int format; +}; + +/* this enum is merely for mtk_afe_i2s_priv & mtk_base_etdm_data declare */ +enum { + DAI_I2SIN0 = 0, + DAI_I2SIN1, + DAI_I2SIN2, + DAI_I2SIN3, + DAI_I2SIN4, + DAI_I2SIN6, + DAI_I2SOUT0, + DAI_I2SOUT1, + DAI_I2SOUT2, + DAI_I2SOUT3, + DAI_I2SOUT4, + DAI_I2SOUT6, + DAI_FMI2S_MASTER, + DAI_I2S_NUM, +}; + +static bool is_etdm_in_pad_top(unsigned int dai_num) +{ + if (dai_num >= DAI_I2S_NUM) + return false; + + switch (dai_num) { + case DAI_I2SOUT4: + case DAI_I2SIN4: + return true; + default: + return false; + } +} + +struct mtk_base_etdm_data { + int enable_reg; + int enable_mask; + int enable_shift; + int sync_reg; + int sync_mask; + int sync_shift; + int ch_reg; + int ch_mask; + int ch_shift; + int ip_mode_reg; + int ip_mode_mask; + int ip_mode_shift; + int init_count_reg; + int init_count_mask; + int init_count_shift; + int init_point_reg; + int init_point_mask; + int init_point_shift; + int lrck_reset_reg; + int lrck_reset_mask; + int lrck_reset_shift; + int clk_source_reg; + int clk_source_mask; + int clk_source_shift; + int ck_en_sel_reg; + int ck_en_sel_mask; + int ck_en_sel_shift; + int fs_timing_reg; + int fs_timing_mask; + int fs_timing_shift; + int relatch_en_sel_reg; + int relatch_en_sel_mask; + int relatch_en_sel_shift; + int use_afifo_reg; + int use_afifo_mask; + int use_afifo_shift; + int afifo_mode_reg; + int afifo_mode_mask; + int afifo_mode_shift; + int almost_end_ch_reg; + int almost_end_ch_mask; + int almost_end_ch_shift; + int almost_end_bit_reg; + int almost_end_bit_mask; + int almost_end_bit_shift; + int out2latch_time_reg; + int out2latch_time_mask; + int out2latch_time_shift; + int tdm_mode_reg; + int tdm_mode_mask; + int tdm_mode_shift; + int relatch_domain_sel_reg; + int relatch_domain_sel_mask; + int relatch_domain_sel_shift; + int bit_length_reg; + int bit_length_mask; + int bit_length_shift; + int word_length_reg; + int word_length_mask; + int word_length_shift; + int cowork_reg; + int cowork_mask; + int cowork_shift; + int cowork_val; + int in2latch_time_reg; + int in2latch_time_mask; + int in2latch_time_shift; + int pad_top_ck_en_reg; + int pad_top_ck_en_mask; + int pad_top_ck_en_shift; + int master_latch_reg; + int master_latch_mask; + int master_latch_shift; +}; + +const struct mtk_base_etdm_data mtk_etdm_data[DAI_I2S_NUM] = { + [DAI_I2SIN0] = { + .enable_reg = ETDM_IN0_CON0, + .enable_mask = REG_ETDM_IN_EN_MASK, + .enable_shift = REG_ETDM_IN_EN_SFT, + .sync_reg = ETDM_IN0_CON0, + .sync_mask = REG_SYNC_MODE_MASK, + .sync_shift = REG_SYNC_MODE_SFT, + .ch_reg = ETDM_IN0_CON0, + .ch_mask = REG_CH_NUM_MASK, + .ch_shift = REG_CH_NUM_SFT, + .ip_mode_reg = ETDM_IN0_CON2, + .ip_mode_mask = REG_MULTI_IP_MODE_MASK, + .ip_mode_shift = REG_MULTI_IP_MODE_SFT, + .init_count_reg = ETDM_IN0_CON1, + .init_count_mask = REG_INITIAL_COUNT_MASK, + .init_count_shift = REG_INITIAL_COUNT_SFT, + .init_point_reg = ETDM_IN0_CON1, + .init_point_mask = REG_INITIAL_POINT_MASK, + .init_point_shift = REG_INITIAL_POINT_SFT, + .lrck_reset_reg = ETDM_IN0_CON1, + .lrck_reset_mask = REG_LRCK_RESET_MASK, + .lrck_reset_shift = REG_LRCK_RESET_SFT, + .clk_source_reg = ETDM_IN0_CON2, + .clk_source_mask = REG_CLOCK_SOURCE_SEL_MASK, + .clk_source_shift = REG_CLOCK_SOURCE_SEL_SFT, + .ck_en_sel_reg = ETDM_IN0_CON2, + .ck_en_sel_mask = REG_CK_EN_SEL_AUTO_MASK, + .ck_en_sel_shift = REG_CK_EN_SEL_AUTO_SFT, + .fs_timing_reg = ETDM_IN0_CON3, + .fs_timing_mask = REG_FS_TIMING_SEL_MASK, + .fs_timing_shift = REG_FS_TIMING_SEL_SFT, + .relatch_en_sel_reg = ETDM_IN0_CON4, + .relatch_en_sel_mask = REG_RELATCH_1X_EN_SEL_MASK, + .relatch_en_sel_shift = REG_RELATCH_1X_EN_SEL_SFT, + .use_afifo_reg = ETDM_IN0_CON8, + .use_afifo_mask = REG_ETDM_USE_AFIFO_MASK, + .use_afifo_shift = REG_ETDM_USE_AFIFO_SFT, + .afifo_mode_reg = ETDM_IN0_CON8, + .afifo_mode_mask = REG_AFIFO_MODE_MASK, + .afifo_mode_shift = REG_AFIFO_MODE_SFT, + .almost_end_ch_reg = ETDM_IN0_CON9, + .almost_end_ch_mask = REG_ALMOST_END_CH_COUNT_MASK, + .almost_end_ch_shift = REG_ALMOST_END_CH_COUNT_SFT, + .almost_end_bit_reg = ETDM_IN0_CON9, + .almost_end_bit_mask = REG_ALMOST_END_BIT_COUNT_MASK, + .almost_end_bit_shift = REG_ALMOST_END_BIT_COUNT_SFT, + .out2latch_time_reg = ETDM_IN0_CON9, + .out2latch_time_mask = REG_OUT2LATCH_TIME_MASK, + .out2latch_time_shift = REG_OUT2LATCH_TIME_SFT, + .tdm_mode_reg = ETDM_IN0_CON0, + .tdm_mode_mask = REG_FMT_MASK, + .tdm_mode_shift = REG_FMT_SFT, + .relatch_domain_sel_reg = ETDM_IN0_CON0, + .relatch_domain_sel_mask = REG_RELATCH_1X_EN_DOMAIN_SEL_MASK, + .relatch_domain_sel_shift = REG_RELATCH_1X_EN_DOMAIN_SEL_SFT, + .bit_length_reg = ETDM_IN0_CON0, + .bit_length_mask = REG_BIT_LENGTH_MASK, + .bit_length_shift = REG_BIT_LENGTH_SFT, + .word_length_reg = ETDM_IN0_CON0, + .word_length_mask = REG_WORD_LENGTH_MASK, + .word_length_shift = REG_WORD_LENGTH_SFT, + .cowork_reg = ETDM_0_3_COWORK_CON0, + .cowork_mask = ETDM_IN0_SLAVE_SEL_MASK, + .cowork_shift = ETDM_IN0_SLAVE_SEL_SFT, + .cowork_val = ETDM_SLAVE_SEL_ETDMOUT0_MASTER, + .pad_top_ck_en_reg = -1, + .master_latch_reg = -1, + }, + [DAI_I2SIN1] = { + .enable_reg = ETDM_IN1_CON0, + .enable_mask = REG_ETDM_IN_EN_MASK, + .enable_shift = REG_ETDM_IN_EN_SFT, + .sync_reg = ETDM_IN1_CON0, + .sync_mask = REG_SYNC_MODE_MASK, + .sync_shift = REG_SYNC_MODE_SFT, + .ch_reg = ETDM_IN1_CON0, + .ch_mask = REG_CH_NUM_MASK, + .ch_shift = REG_CH_NUM_SFT, + .ip_mode_reg = ETDM_IN1_CON2, + .ip_mode_mask = REG_MULTI_IP_MODE_MASK, + .ip_mode_shift = REG_MULTI_IP_MODE_SFT, + .init_count_reg = ETDM_IN1_CON1, + .init_count_mask = REG_INITIAL_COUNT_MASK, + .init_count_shift = REG_INITIAL_COUNT_SFT, + .init_point_reg = ETDM_IN1_CON1, + .init_point_mask = REG_INITIAL_POINT_MASK, + .init_point_shift = REG_INITIAL_POINT_SFT, + .lrck_reset_reg = ETDM_IN1_CON1, + .lrck_reset_mask = REG_LRCK_RESET_MASK, + .lrck_reset_shift = REG_LRCK_RESET_SFT, + .clk_source_reg = ETDM_IN1_CON2, + .clk_source_mask = REG_CLOCK_SOURCE_SEL_MASK, + .clk_source_shift = REG_CLOCK_SOURCE_SEL_SFT, + .ck_en_sel_reg = ETDM_IN1_CON2, + .ck_en_sel_mask = REG_CK_EN_SEL_AUTO_MASK, + .ck_en_sel_shift = REG_CK_EN_SEL_AUTO_SFT, + .fs_timing_reg = ETDM_IN1_CON3, + .fs_timing_mask = REG_FS_TIMING_SEL_MASK, + .fs_timing_shift = REG_FS_TIMING_SEL_SFT, + .relatch_en_sel_reg = ETDM_IN1_CON4, + .relatch_en_sel_mask = REG_RELATCH_1X_EN_SEL_MASK, + .relatch_en_sel_shift = REG_RELATCH_1X_EN_SEL_SFT, + .use_afifo_reg = ETDM_IN1_CON8, + .use_afifo_mask = REG_ETDM_USE_AFIFO_MASK, + .use_afifo_shift = REG_ETDM_USE_AFIFO_SFT, + .afifo_mode_reg = ETDM_IN1_CON8, + .afifo_mode_mask = REG_AFIFO_MODE_MASK, + .afifo_mode_shift = REG_AFIFO_MODE_SFT, + .almost_end_ch_reg = ETDM_IN1_CON9, + .almost_end_ch_mask = REG_ALMOST_END_CH_COUNT_MASK, + .almost_end_ch_shift = REG_ALMOST_END_CH_COUNT_SFT, + .almost_end_bit_reg = ETDM_IN1_CON9, + .almost_end_bit_mask = REG_ALMOST_END_BIT_COUNT_MASK, + .almost_end_bit_shift = REG_ALMOST_END_BIT_COUNT_SFT, + .out2latch_time_reg = ETDM_IN1_CON9, + .out2latch_time_mask = REG_OUT2LATCH_TIME_MASK, + .out2latch_time_shift = REG_OUT2LATCH_TIME_SFT, + .tdm_mode_reg = ETDM_IN1_CON0, + .tdm_mode_mask = REG_FMT_MASK, + .tdm_mode_shift = REG_FMT_SFT, + .relatch_domain_sel_reg = ETDM_IN1_CON0, + .relatch_domain_sel_mask = REG_RELATCH_1X_EN_DOMAIN_SEL_MASK, + .relatch_domain_sel_shift = REG_RELATCH_1X_EN_DOMAIN_SEL_SFT, + .bit_length_reg = ETDM_IN1_CON0, + .bit_length_mask = REG_BIT_LENGTH_MASK, + .bit_length_shift = REG_BIT_LENGTH_SFT, + .word_length_reg = ETDM_IN1_CON0, + .word_length_mask = REG_WORD_LENGTH_MASK, + .word_length_shift = REG_WORD_LENGTH_SFT, + .cowork_reg = ETDM_0_3_COWORK_CON1, + .cowork_mask = ETDM_IN1_SLAVE_SEL_MASK, + .cowork_shift = ETDM_IN1_SLAVE_SEL_SFT, + .cowork_val = ETDM_SLAVE_SEL_ETDMOUT1_MASTER, + .pad_top_ck_en_reg = -1, + .master_latch_reg = -1, + }, + [DAI_I2SIN2] = { + .enable_reg = ETDM_IN2_CON0, + .enable_mask = REG_ETDM_IN_EN_MASK, + .enable_shift = REG_ETDM_IN_EN_SFT, + .sync_reg = ETDM_IN2_CON0, + .sync_mask = REG_SYNC_MODE_MASK, + .sync_shift = REG_SYNC_MODE_SFT, + .ch_reg = ETDM_IN2_CON0, + .ch_mask = REG_CH_NUM_MASK, + .ch_shift = REG_CH_NUM_SFT, + .ip_mode_reg = ETDM_IN2_CON2, + .ip_mode_mask = REG_MULTI_IP_MODE_MASK, + .ip_mode_shift = REG_MULTI_IP_MODE_SFT, + .init_count_reg = ETDM_IN2_CON1, + .init_count_mask = REG_INITIAL_COUNT_MASK, + .init_count_shift = REG_INITIAL_COUNT_SFT, + .init_point_reg = ETDM_IN2_CON1, + .init_point_mask = REG_INITIAL_POINT_MASK, + .init_point_shift = REG_INITIAL_POINT_SFT, + .lrck_reset_reg = ETDM_IN2_CON1, + .lrck_reset_mask = REG_LRCK_RESET_MASK, + .lrck_reset_shift = REG_LRCK_RESET_SFT, + .clk_source_reg = ETDM_IN2_CON2, + .clk_source_mask = REG_CLOCK_SOURCE_SEL_MASK, + .clk_source_shift = REG_CLOCK_SOURCE_SEL_SFT, + .ck_en_sel_reg = ETDM_IN2_CON2, + .ck_en_sel_mask = REG_CK_EN_SEL_AUTO_MASK, + .ck_en_sel_shift = REG_CK_EN_SEL_AUTO_SFT, + .fs_timing_reg = ETDM_IN2_CON3, + .fs_timing_mask = REG_FS_TIMING_SEL_MASK, + .fs_timing_shift = REG_FS_TIMING_SEL_SFT, + .relatch_en_sel_reg = ETDM_IN2_CON4, + .relatch_en_sel_mask = REG_RELATCH_1X_EN_SEL_MASK, + .relatch_en_sel_shift = REG_RELATCH_1X_EN_SEL_SFT, + .use_afifo_reg = ETDM_IN2_CON8, + .use_afifo_mask = REG_ETDM_USE_AFIFO_MASK, + .use_afifo_shift = REG_ETDM_USE_AFIFO_SFT, + .afifo_mode_reg = ETDM_IN2_CON8, + .afifo_mode_mask = REG_AFIFO_MODE_MASK, + .afifo_mode_shift = REG_AFIFO_MODE_SFT, + .almost_end_ch_reg = ETDM_IN2_CON9, + .almost_end_ch_mask = REG_ALMOST_END_CH_COUNT_MASK, + .almost_end_ch_shift = REG_ALMOST_END_CH_COUNT_SFT, + .almost_end_bit_reg = ETDM_IN2_CON9, + .almost_end_bit_mask = REG_ALMOST_END_BIT_COUNT_MASK, + .almost_end_bit_shift = REG_ALMOST_END_BIT_COUNT_SFT, + .out2latch_time_reg = ETDM_IN2_CON9, + .out2latch_time_mask = REG_OUT2LATCH_TIME_MASK, + .out2latch_time_shift = REG_OUT2LATCH_TIME_SFT, + .tdm_mode_reg = ETDM_IN2_CON0, + .tdm_mode_mask = REG_FMT_MASK, + .tdm_mode_shift = REG_FMT_SFT, + .relatch_domain_sel_reg = ETDM_IN2_CON0, + .relatch_domain_sel_mask = REG_RELATCH_1X_EN_DOMAIN_SEL_MASK, + .relatch_domain_sel_shift = REG_RELATCH_1X_EN_DOMAIN_SEL_SFT, + .bit_length_reg = ETDM_IN2_CON0, + .bit_length_mask = REG_BIT_LENGTH_MASK, + .bit_length_shift = REG_BIT_LENGTH_SFT, + .word_length_reg = ETDM_IN2_CON0, + .word_length_mask = REG_WORD_LENGTH_MASK, + .word_length_shift = REG_WORD_LENGTH_SFT, + .cowork_reg = ETDM_0_3_COWORK_CON2, + .cowork_mask = ETDM_IN2_SLAVE_SEL_MASK, + .cowork_shift = ETDM_IN2_SLAVE_SEL_SFT, + .cowork_val = ETDM_SLAVE_SEL_ETDMOUT2_MASTER, + .pad_top_ck_en_reg = -1, + .master_latch_reg = -1, + }, + [DAI_I2SIN3] = { + .enable_reg = ETDM_IN3_CON0, + .enable_mask = REG_ETDM_IN_EN_MASK, + .enable_shift = REG_ETDM_IN_EN_SFT, + .sync_reg = ETDM_IN3_CON0, + .sync_mask = REG_SYNC_MODE_MASK, + .sync_shift = REG_SYNC_MODE_SFT, + .ch_reg = ETDM_IN3_CON0, + .ch_mask = REG_CH_NUM_MASK, + .ch_shift = REG_CH_NUM_SFT, + .ip_mode_reg = ETDM_IN3_CON2, + .ip_mode_mask = REG_MULTI_IP_MODE_MASK, + .ip_mode_shift = REG_MULTI_IP_MODE_SFT, + .init_count_reg = ETDM_IN3_CON1, + .init_count_mask = REG_INITIAL_COUNT_MASK, + .init_count_shift = REG_INITIAL_COUNT_SFT, + .init_point_reg = ETDM_IN3_CON1, + .init_point_mask = REG_INITIAL_POINT_MASK, + .init_point_shift = REG_INITIAL_POINT_SFT, + .lrck_reset_reg = ETDM_IN3_CON1, + .lrck_reset_mask = REG_LRCK_RESET_MASK, + .lrck_reset_shift = REG_LRCK_RESET_SFT, + .clk_source_reg = ETDM_IN3_CON2, + .clk_source_mask = REG_CLOCK_SOURCE_SEL_MASK, + .clk_source_shift = REG_CLOCK_SOURCE_SEL_SFT, + .ck_en_sel_reg = ETDM_IN3_CON2, + .ck_en_sel_mask = REG_CK_EN_SEL_AUTO_MASK, + .ck_en_sel_shift = REG_CK_EN_SEL_AUTO_SFT, + .fs_timing_reg = ETDM_IN3_CON3, + .fs_timing_mask = REG_FS_TIMING_SEL_MASK, + .fs_timing_shift = REG_FS_TIMING_SEL_SFT, + .relatch_en_sel_reg = ETDM_IN3_CON4, + .relatch_en_sel_mask = REG_RELATCH_1X_EN_SEL_MASK, + .relatch_en_sel_shift = REG_RELATCH_1X_EN_SEL_SFT, + .use_afifo_reg = ETDM_IN3_CON8, + .use_afifo_mask = REG_ETDM_USE_AFIFO_MASK, + .use_afifo_shift = REG_ETDM_USE_AFIFO_SFT, + .afifo_mode_reg = ETDM_IN3_CON8, + .afifo_mode_mask = REG_AFIFO_MODE_MASK, + .afifo_mode_shift = REG_AFIFO_MODE_SFT, + .almost_end_ch_reg = ETDM_IN3_CON9, + .almost_end_ch_mask = REG_ALMOST_END_CH_COUNT_MASK, + .almost_end_ch_shift = REG_ALMOST_END_CH_COUNT_SFT, + .almost_end_bit_reg = ETDM_IN3_CON9, + .almost_end_bit_mask = REG_ALMOST_END_BIT_COUNT_MASK, + .almost_end_bit_shift = REG_ALMOST_END_BIT_COUNT_SFT, + .out2latch_time_reg = ETDM_IN3_CON9, + .out2latch_time_mask = REG_OUT2LATCH_TIME_MASK, + .out2latch_time_shift = REG_OUT2LATCH_TIME_SFT, + .tdm_mode_reg = ETDM_IN3_CON0, + .tdm_mode_mask = REG_FMT_MASK, + .tdm_mode_shift = REG_FMT_SFT, + .relatch_domain_sel_reg = ETDM_IN3_CON0, + .relatch_domain_sel_mask = REG_RELATCH_1X_EN_DOMAIN_SEL_MASK, + .relatch_domain_sel_shift = REG_RELATCH_1X_EN_DOMAIN_SEL_SFT, + .bit_length_reg = ETDM_IN3_CON0, + .bit_length_mask = REG_BIT_LENGTH_MASK, + .bit_length_shift = REG_BIT_LENGTH_SFT, + .word_length_reg = ETDM_IN3_CON0, + .word_length_mask = REG_WORD_LENGTH_MASK, + .word_length_shift = REG_WORD_LENGTH_SFT, + .cowork_reg = ETDM_0_3_COWORK_CON3, + .cowork_mask = ETDM_IN3_SLAVE_SEL_MASK, + .cowork_shift = ETDM_IN3_SLAVE_SEL_SFT, + .cowork_val = ETDM_SLAVE_SEL_ETDMOUT3_MASTER, + .pad_top_ck_en_reg = -1, + .master_latch_reg = -1, + }, + [DAI_I2SIN4] = { + .enable_reg = ETDM_IN4_CON0, + .enable_mask = REG_ETDM_IN_EN_MASK, + .enable_shift = REG_ETDM_IN_EN_SFT, + .sync_reg = ETDM_IN4_CON0, + .sync_mask = REG_SYNC_MODE_MASK, + .sync_shift = REG_SYNC_MODE_SFT, + .ch_reg = ETDM_IN4_CON0, + .ch_mask = REG_CH_NUM_MASK, + .ch_shift = REG_CH_NUM_SFT, + .ip_mode_reg = ETDM_IN4_CON2, + .ip_mode_mask = REG_MULTI_IP_MODE_MASK, + .ip_mode_shift = REG_MULTI_IP_MODE_SFT, + .init_count_reg = ETDM_IN4_CON1, + .init_count_mask = REG_INITIAL_COUNT_MASK, + .init_count_shift = REG_INITIAL_COUNT_SFT, + .init_point_reg = ETDM_IN4_CON1, + .init_point_mask = REG_INITIAL_POINT_MASK, + .init_point_shift = REG_INITIAL_POINT_SFT, + .lrck_reset_reg = ETDM_IN4_CON1, + .lrck_reset_mask = REG_LRCK_RESET_MASK, + .lrck_reset_shift = REG_LRCK_RESET_SFT, + .clk_source_reg = ETDM_IN4_CON2, + .clk_source_mask = REG_CLOCK_SOURCE_SEL_MASK, + .clk_source_shift = REG_CLOCK_SOURCE_SEL_SFT, + .ck_en_sel_reg = ETDM_IN4_CON2, + .ck_en_sel_mask = REG_CK_EN_SEL_AUTO_MASK, + .ck_en_sel_shift = REG_CK_EN_SEL_AUTO_SFT, + .fs_timing_reg = ETDM_IN4_CON3, + .fs_timing_mask = REG_FS_TIMING_SEL_MASK, + .fs_timing_shift = REG_FS_TIMING_SEL_SFT, + .relatch_en_sel_reg = ETDM_IN4_CON4, + .relatch_en_sel_mask = REG_RELATCH_1X_EN_SEL_MASK, + .relatch_en_sel_shift = REG_RELATCH_1X_EN_SEL_SFT, + .use_afifo_reg = ETDM_IN4_CON8, + .use_afifo_mask = REG_ETDM_USE_AFIFO_MASK, + .use_afifo_shift = REG_ETDM_USE_AFIFO_SFT, + .afifo_mode_reg = ETDM_IN4_CON8, + .afifo_mode_mask = REG_AFIFO_MODE_MASK, + .afifo_mode_shift = REG_AFIFO_MODE_SFT, + .almost_end_ch_reg = ETDM_IN4_CON9, + .almost_end_ch_mask = REG_ALMOST_END_CH_COUNT_MASK, + .almost_end_ch_shift = REG_ALMOST_END_CH_COUNT_SFT, + .almost_end_bit_reg = ETDM_IN4_CON9, + .almost_end_bit_mask = REG_ALMOST_END_BIT_COUNT_MASK, + .almost_end_bit_shift = REG_ALMOST_END_BIT_COUNT_SFT, + .out2latch_time_reg = ETDM_IN4_CON9, + .out2latch_time_mask = REG_OUT2LATCH_TIME_MASK, + .out2latch_time_shift = REG_OUT2LATCH_TIME_SFT, + .tdm_mode_reg = ETDM_IN4_CON0, + .tdm_mode_mask = REG_FMT_MASK, + .tdm_mode_shift = REG_FMT_SFT, + .relatch_domain_sel_reg = ETDM_IN4_CON0, + .relatch_domain_sel_mask = REG_RELATCH_1X_EN_DOMAIN_SEL_MASK, + .relatch_domain_sel_shift = REG_RELATCH_1X_EN_DOMAIN_SEL_SFT, + .bit_length_reg = ETDM_IN4_CON0, + .bit_length_mask = REG_BIT_LENGTH_MASK, + .bit_length_shift = REG_BIT_LENGTH_SFT, + .word_length_reg = ETDM_IN4_CON0, + .word_length_mask = REG_WORD_LENGTH_MASK, + .word_length_shift = REG_WORD_LENGTH_SFT, + .cowork_reg = ETDM_4_7_COWORK_CON0, + .cowork_mask = ETDM_IN4_SLAVE_SEL_MASK, + .cowork_shift = ETDM_IN4_SLAVE_SEL_SFT, + .cowork_val = ETDM_SLAVE_SEL_ETDMOUT4_MASTER, + .pad_top_ck_en_reg = AUD_TOP_CFG_VLP_RG, + .pad_top_ck_en_mask = RG_I2S4_PAD_TOP_CK_EN_MASK, + .pad_top_ck_en_shift = RG_I2S4_PAD_TOP_CK_EN_SFT, + .master_latch_reg = AUD_TOP_CFG_VLP_RG, + .master_latch_mask = RG_I2S4_IN_BCK_NEG_EG_LATCH_MASK, + .master_latch_shift = RG_I2S4_IN_BCK_NEG_EG_LATCH_SFT, + }, + [DAI_I2SIN6] = { + .enable_reg = ETDM_IN6_CON0, + .enable_mask = REG_ETDM_IN_EN_MASK, + .enable_shift = REG_ETDM_IN_EN_SFT, + .sync_reg = ETDM_IN6_CON0, + .sync_mask = REG_SYNC_MODE_MASK, + .sync_shift = REG_SYNC_MODE_SFT, + .ch_reg = ETDM_IN6_CON0, + .ch_mask = REG_CH_NUM_MASK, + .ch_shift = REG_CH_NUM_SFT, + .ip_mode_reg = ETDM_IN6_CON2, + .ip_mode_mask = REG_MULTI_IP_MODE_MASK, + .ip_mode_shift = REG_MULTI_IP_MODE_SFT, + .init_count_reg = ETDM_IN6_CON1, + .init_count_mask = REG_INITIAL_COUNT_MASK, + .init_count_shift = REG_INITIAL_COUNT_SFT, + .init_point_reg = ETDM_IN6_CON1, + .init_point_mask = REG_INITIAL_POINT_MASK, + .init_point_shift = REG_INITIAL_POINT_SFT, + .lrck_reset_reg = ETDM_IN6_CON1, + .lrck_reset_mask = REG_LRCK_RESET_MASK, + .lrck_reset_shift = REG_LRCK_RESET_SFT, + .clk_source_reg = ETDM_IN6_CON2, + .clk_source_mask = REG_CLOCK_SOURCE_SEL_MASK, + .clk_source_shift = REG_CLOCK_SOURCE_SEL_SFT, + .ck_en_sel_reg = ETDM_IN6_CON2, + .ck_en_sel_mask = REG_CK_EN_SEL_AUTO_MASK, + .ck_en_sel_shift = REG_CK_EN_SEL_AUTO_SFT, + .fs_timing_reg = ETDM_IN6_CON3, + .fs_timing_mask = REG_FS_TIMING_SEL_MASK, + .fs_timing_shift = REG_FS_TIMING_SEL_SFT, + .relatch_en_sel_reg = ETDM_IN6_CON4, + .relatch_en_sel_mask = REG_RELATCH_1X_EN_SEL_MASK, + .relatch_en_sel_shift = REG_RELATCH_1X_EN_SEL_SFT, + .use_afifo_reg = ETDM_IN6_CON8, + .use_afifo_mask = REG_ETDM_USE_AFIFO_MASK, + .use_afifo_shift = REG_ETDM_USE_AFIFO_SFT, + .afifo_mode_reg = ETDM_IN6_CON8, + .afifo_mode_mask = REG_AFIFO_MODE_MASK, + .afifo_mode_shift = REG_AFIFO_MODE_SFT, + .almost_end_ch_reg = ETDM_IN6_CON9, + .almost_end_ch_mask = REG_ALMOST_END_CH_COUNT_MASK, + .almost_end_ch_shift = REG_ALMOST_END_CH_COUNT_SFT, + .almost_end_bit_reg = ETDM_IN6_CON9, + .almost_end_bit_mask = REG_ALMOST_END_BIT_COUNT_MASK, + .almost_end_bit_shift = REG_ALMOST_END_BIT_COUNT_SFT, + .out2latch_time_reg = ETDM_IN6_CON9, + .out2latch_time_mask = REG_OUT2LATCH_TIME_MASK, + .out2latch_time_shift = REG_OUT2LATCH_TIME_SFT, + .tdm_mode_reg = ETDM_IN6_CON0, + .tdm_mode_mask = REG_FMT_MASK, + .tdm_mode_shift = REG_FMT_SFT, + .relatch_domain_sel_reg = ETDM_IN6_CON0, + .relatch_domain_sel_mask = REG_RELATCH_1X_EN_DOMAIN_SEL_MASK, + .relatch_domain_sel_shift = REG_RELATCH_1X_EN_DOMAIN_SEL_SFT, + .bit_length_reg = ETDM_IN6_CON0, + .bit_length_mask = REG_BIT_LENGTH_MASK, + .bit_length_shift = REG_BIT_LENGTH_SFT, + .word_length_reg = ETDM_IN6_CON0, + .word_length_mask = REG_WORD_LENGTH_MASK, + .word_length_shift = REG_WORD_LENGTH_SFT, + .cowork_reg = ETDM_4_7_COWORK_CON2, + .cowork_mask = ETDM_IN6_SLAVE_SEL_MASK, + .cowork_shift = ETDM_IN6_SLAVE_SEL_SFT, + .cowork_val = ETDM_SLAVE_SEL_ETDMOUT6_MASTER, + .pad_top_ck_en_reg = -1, + .master_latch_reg = -1, + }, + [DAI_I2SOUT0] = { + .enable_reg = ETDM_OUT0_CON0, + .enable_mask = OUT_REG_ETDM_OUT_EN_MASK, + .enable_shift = OUT_REG_ETDM_OUT_EN_SFT, + .sync_reg = ETDM_OUT0_CON0, + .sync_mask = REG_SYNC_MODE_MASK, + .sync_shift = REG_SYNC_MODE_SFT, + .ch_reg = ETDM_OUT0_CON0, + .ch_mask = REG_CH_NUM_MASK, + .ch_shift = REG_CH_NUM_SFT, + .init_count_reg = ETDM_OUT0_CON1, + .init_count_mask = OUT_REG_INITIAL_COUNT_MASK, + .init_count_shift = OUT_REG_INITIAL_COUNT_SFT, + .init_point_reg = ETDM_OUT0_CON1, + .init_point_mask = OUT_REG_INITIAL_POINT_MASK, + .init_point_shift = OUT_REG_INITIAL_POINT_SFT, + .lrck_reset_reg = ETDM_OUT0_CON1, + .lrck_reset_mask = OUT_REG_LRCK_RESET_MASK, + .lrck_reset_shift = OUT_REG_LRCK_RESET_SFT, + .clk_source_reg = ETDM_OUT0_CON4, + .clk_source_mask = OUT_REG_CLOCK_SOURCE_SEL_MASK, + .clk_source_shift = OUT_REG_CLOCK_SOURCE_SEL_SFT, + .fs_timing_reg = ETDM_OUT0_CON4, + .fs_timing_mask = OUT_REG_FS_TIMING_SEL_MASK, + .fs_timing_shift = OUT_REG_FS_TIMING_SEL_SFT, + .relatch_en_sel_reg = ETDM_OUT0_CON4, + .relatch_en_sel_mask = OUT_REG_RELATCH_EN_SEL_MASK, + .relatch_en_sel_shift = OUT_REG_RELATCH_EN_SEL_SFT, + .tdm_mode_reg = ETDM_OUT0_CON0, + .tdm_mode_mask = OUT_REG_FMT_MASK, + .tdm_mode_shift = OUT_REG_FMT_SFT, + .relatch_domain_sel_reg = ETDM_OUT0_CON0, + .relatch_domain_sel_mask = OUT_REG_RELATCH_DOMAIN_SEL_MASK, + .relatch_domain_sel_shift = OUT_REG_RELATCH_DOMAIN_SEL_SFT, + .bit_length_reg = ETDM_OUT0_CON0, + .bit_length_mask = OUT_REG_BIT_LENGTH_MASK, + .bit_length_shift = OUT_REG_BIT_LENGTH_SFT, + .word_length_reg = ETDM_OUT0_CON0, + .word_length_mask = OUT_REG_WORD_LENGTH_MASK, + .word_length_shift = OUT_REG_WORD_LENGTH_SFT, + .cowork_reg = ETDM_0_3_COWORK_CON0, + .cowork_mask = ETDM_OUT0_SLAVE_SEL_MASK, + .cowork_shift = ETDM_OUT0_SLAVE_SEL_SFT, + .cowork_val = ETDM_SLAVE_SEL_ETDMIN0_MASTER, + .in2latch_time_reg = ETDM_OUT0_CON2, + .in2latch_time_mask = OUT_REG_IN2LATCH_TIME_MASK, + .in2latch_time_shift = OUT_REG_IN2LATCH_TIME_SFT, + .pad_top_ck_en_reg = -1, + .master_latch_reg = -1, + }, + [DAI_I2SOUT1] = { + .enable_reg = ETDM_OUT1_CON0, + .enable_mask = OUT_REG_ETDM_OUT_EN_MASK, + .enable_shift = OUT_REG_ETDM_OUT_EN_SFT, + .sync_reg = ETDM_OUT1_CON0, + .sync_mask = REG_SYNC_MODE_MASK, + .sync_shift = REG_SYNC_MODE_SFT, + .ch_reg = ETDM_OUT1_CON0, + .ch_mask = REG_CH_NUM_MASK, + .ch_shift = REG_CH_NUM_SFT, + .init_count_reg = ETDM_OUT1_CON1, + .init_count_mask = OUT_REG_INITIAL_COUNT_MASK, + .init_count_shift = OUT_REG_INITIAL_COUNT_SFT, + .init_point_reg = ETDM_OUT1_CON1, + .init_point_mask = OUT_REG_INITIAL_POINT_MASK, + .init_point_shift = OUT_REG_INITIAL_POINT_SFT, + .lrck_reset_reg = ETDM_OUT1_CON1, + .lrck_reset_mask = OUT_REG_LRCK_RESET_MASK, + .lrck_reset_shift = OUT_REG_LRCK_RESET_SFT, + .clk_source_reg = ETDM_OUT1_CON4, + .clk_source_mask = OUT_REG_CLOCK_SOURCE_SEL_MASK, + .clk_source_shift = OUT_REG_CLOCK_SOURCE_SEL_SFT, + .fs_timing_reg = ETDM_OUT1_CON4, + .fs_timing_mask = OUT_REG_FS_TIMING_SEL_MASK, + .fs_timing_shift = OUT_REG_FS_TIMING_SEL_SFT, + .relatch_en_sel_reg = ETDM_OUT1_CON4, + .relatch_en_sel_mask = OUT_REG_RELATCH_EN_SEL_MASK, + .relatch_en_sel_shift = OUT_REG_RELATCH_EN_SEL_SFT, + .tdm_mode_reg = ETDM_OUT1_CON0, + .tdm_mode_mask = OUT_REG_FMT_MASK, + .tdm_mode_shift = OUT_REG_FMT_SFT, + .relatch_domain_sel_reg = ETDM_OUT1_CON0, + .relatch_domain_sel_mask = OUT_REG_RELATCH_DOMAIN_SEL_MASK, + .relatch_domain_sel_shift = OUT_REG_RELATCH_DOMAIN_SEL_SFT, + .bit_length_reg = ETDM_OUT1_CON0, + .bit_length_mask = OUT_REG_BIT_LENGTH_MASK, + .bit_length_shift = OUT_REG_BIT_LENGTH_SFT, + .word_length_reg = ETDM_OUT1_CON0, + .word_length_mask = OUT_REG_WORD_LENGTH_MASK, + .word_length_shift = OUT_REG_WORD_LENGTH_SFT, + .cowork_reg = ETDM_0_3_COWORK_CON0, + .cowork_mask = ETDM_OUT1_SLAVE_SEL_MASK, + .cowork_shift = ETDM_OUT1_SLAVE_SEL_SFT, + .cowork_val = ETDM_SLAVE_SEL_ETDMIN1_MASTER, + .in2latch_time_reg = ETDM_OUT1_CON2, + .in2latch_time_mask = OUT_REG_IN2LATCH_TIME_MASK, + .in2latch_time_shift = OUT_REG_IN2LATCH_TIME_SFT, + .pad_top_ck_en_reg = -1, + .master_latch_reg = -1, + }, + [DAI_I2SOUT2] = { + .enable_reg = ETDM_OUT2_CON0, + .enable_mask = OUT_REG_ETDM_OUT_EN_MASK, + .enable_shift = OUT_REG_ETDM_OUT_EN_SFT, + .sync_reg = ETDM_OUT2_CON0, + .sync_mask = REG_SYNC_MODE_MASK, + .sync_shift = REG_SYNC_MODE_SFT, + .ch_reg = ETDM_OUT2_CON0, + .ch_mask = REG_CH_NUM_MASK, + .ch_shift = REG_CH_NUM_SFT, + .init_count_reg = ETDM_OUT2_CON1, + .init_count_mask = OUT_REG_INITIAL_COUNT_MASK, + .init_count_shift = OUT_REG_INITIAL_COUNT_SFT, + .init_point_reg = ETDM_OUT2_CON1, + .init_point_mask = OUT_REG_INITIAL_POINT_MASK, + .init_point_shift = OUT_REG_INITIAL_POINT_SFT, + .lrck_reset_reg = ETDM_OUT2_CON1, + .lrck_reset_mask = OUT_REG_LRCK_RESET_MASK, + .lrck_reset_shift = OUT_REG_LRCK_RESET_SFT, + .clk_source_reg = ETDM_OUT2_CON4, + .clk_source_mask = OUT_REG_CLOCK_SOURCE_SEL_MASK, + .clk_source_shift = OUT_REG_CLOCK_SOURCE_SEL_SFT, + .fs_timing_reg = ETDM_OUT2_CON4, + .fs_timing_mask = OUT_REG_FS_TIMING_SEL_MASK, + .fs_timing_shift = OUT_REG_FS_TIMING_SEL_SFT, + .relatch_en_sel_reg = ETDM_OUT2_CON4, + .relatch_en_sel_mask = OUT_REG_RELATCH_EN_SEL_MASK, + .relatch_en_sel_shift = OUT_REG_RELATCH_EN_SEL_SFT, + .tdm_mode_reg = ETDM_OUT2_CON0, + .tdm_mode_mask = OUT_REG_FMT_MASK, + .tdm_mode_shift = OUT_REG_FMT_SFT, + .relatch_domain_sel_reg = ETDM_OUT2_CON0, + .relatch_domain_sel_mask = OUT_REG_RELATCH_DOMAIN_SEL_MASK, + .relatch_domain_sel_shift = OUT_REG_RELATCH_DOMAIN_SEL_SFT, + .bit_length_reg = ETDM_OUT2_CON0, + .bit_length_mask = OUT_REG_BIT_LENGTH_MASK, + .bit_length_shift = OUT_REG_BIT_LENGTH_SFT, + .word_length_reg = ETDM_OUT2_CON0, + .word_length_mask = OUT_REG_WORD_LENGTH_MASK, + .word_length_shift = OUT_REG_WORD_LENGTH_SFT, + .cowork_reg = ETDM_0_3_COWORK_CON2, + .cowork_mask = ETDM_OUT2_SLAVE_SEL_MASK, + .cowork_shift = ETDM_OUT2_SLAVE_SEL_SFT, + .cowork_val = ETDM_SLAVE_SEL_ETDMIN2_MASTER, + .in2latch_time_reg = ETDM_OUT2_CON2, + .in2latch_time_mask = OUT_REG_IN2LATCH_TIME_MASK, + .in2latch_time_shift = OUT_REG_IN2LATCH_TIME_SFT, + .pad_top_ck_en_reg = -1, + .master_latch_reg = -1, + }, + [DAI_I2SOUT3] = { + .enable_reg = ETDM_OUT3_CON0, + .enable_mask = OUT_REG_ETDM_OUT_EN_MASK, + .enable_shift = OUT_REG_ETDM_OUT_EN_SFT, + .sync_reg = ETDM_OUT3_CON0, + .sync_mask = REG_SYNC_MODE_MASK, + .sync_shift = REG_SYNC_MODE_SFT, + .ch_reg = ETDM_OUT3_CON0, + .ch_mask = REG_CH_NUM_MASK, + .ch_shift = REG_CH_NUM_SFT, + .init_count_reg = ETDM_OUT3_CON1, + .init_count_mask = OUT_REG_INITIAL_COUNT_MASK, + .init_count_shift = OUT_REG_INITIAL_COUNT_SFT, + .init_point_reg = ETDM_OUT3_CON1, + .init_point_mask = OUT_REG_INITIAL_POINT_MASK, + .init_point_shift = OUT_REG_INITIAL_POINT_SFT, + .lrck_reset_reg = ETDM_OUT3_CON1, + .lrck_reset_mask = OUT_REG_LRCK_RESET_MASK, + .lrck_reset_shift = OUT_REG_LRCK_RESET_SFT, + .clk_source_reg = ETDM_OUT3_CON4, + .clk_source_mask = OUT_REG_CLOCK_SOURCE_SEL_MASK, + .clk_source_shift = OUT_REG_CLOCK_SOURCE_SEL_SFT, + .fs_timing_reg = ETDM_OUT3_CON4, + .fs_timing_mask = OUT_REG_FS_TIMING_SEL_MASK, + .fs_timing_shift = OUT_REG_FS_TIMING_SEL_SFT, + .relatch_en_sel_reg = ETDM_OUT3_CON4, + .relatch_en_sel_mask = OUT_REG_RELATCH_EN_SEL_MASK, + .relatch_en_sel_shift = OUT_REG_RELATCH_EN_SEL_SFT, + .tdm_mode_reg = ETDM_OUT3_CON0, + .tdm_mode_mask = OUT_REG_FMT_MASK, + .tdm_mode_shift = OUT_REG_FMT_SFT, + .relatch_domain_sel_reg = ETDM_OUT3_CON0, + .relatch_domain_sel_mask = OUT_REG_RELATCH_DOMAIN_SEL_MASK, + .relatch_domain_sel_shift = OUT_REG_RELATCH_DOMAIN_SEL_SFT, + .bit_length_reg = ETDM_OUT3_CON0, + .bit_length_mask = OUT_REG_BIT_LENGTH_MASK, + .bit_length_shift = OUT_REG_BIT_LENGTH_SFT, + .word_length_reg = ETDM_OUT3_CON0, + .word_length_mask = OUT_REG_WORD_LENGTH_MASK, + .word_length_shift = OUT_REG_WORD_LENGTH_SFT, + .cowork_reg = ETDM_0_3_COWORK_CON2, + .cowork_mask = ETDM_OUT3_SLAVE_SEL_MASK, + .cowork_shift = ETDM_OUT3_SLAVE_SEL_SFT, + .cowork_val = ETDM_SLAVE_SEL_ETDMIN3_MASTER, + .in2latch_time_reg = ETDM_OUT3_CON2, + .in2latch_time_mask = OUT_REG_IN2LATCH_TIME_MASK, + .in2latch_time_shift = OUT_REG_IN2LATCH_TIME_SFT, + .pad_top_ck_en_reg = -1, + .master_latch_reg = -1, + }, + [DAI_I2SOUT4] = { + .enable_reg = ETDM_OUT4_CON0, + .enable_mask = OUT_REG_ETDM_OUT_EN_MASK, + .enable_shift = OUT_REG_ETDM_OUT_EN_SFT, + .sync_reg = ETDM_OUT4_CON0, + .sync_mask = REG_SYNC_MODE_MASK, + .sync_shift = REG_SYNC_MODE_SFT, + .ch_reg = ETDM_OUT4_CON0, + .ch_mask = REG_CH_NUM_MASK, + .ch_shift = REG_CH_NUM_SFT, + .init_count_reg = ETDM_OUT4_CON1, + .init_count_mask = OUT_REG_INITIAL_COUNT_MASK, + .init_count_shift = OUT_REG_INITIAL_COUNT_SFT, + .init_point_reg = ETDM_OUT4_CON1, + .init_point_mask = OUT_REG_INITIAL_POINT_MASK, + .init_point_shift = OUT_REG_INITIAL_POINT_SFT, + .lrck_reset_reg = ETDM_OUT4_CON1, + .lrck_reset_mask = OUT_REG_LRCK_RESET_MASK, + .lrck_reset_shift = OUT_REG_LRCK_RESET_SFT, + .clk_source_reg = ETDM_OUT4_CON4, + .clk_source_mask = OUT_REG_CLOCK_SOURCE_SEL_MASK, + .clk_source_shift = OUT_REG_CLOCK_SOURCE_SEL_SFT, + .fs_timing_reg = ETDM_OUT4_CON4, + .fs_timing_mask = OUT_REG_FS_TIMING_SEL_MASK, + .fs_timing_shift = OUT_REG_FS_TIMING_SEL_SFT, + .relatch_en_sel_reg = ETDM_OUT4_CON4, + .relatch_en_sel_mask = OUT_REG_RELATCH_EN_SEL_MASK, + .relatch_en_sel_shift = OUT_REG_RELATCH_EN_SEL_SFT, + .tdm_mode_reg = ETDM_OUT4_CON0, + .tdm_mode_mask = OUT_REG_FMT_MASK, + .tdm_mode_shift = OUT_REG_FMT_SFT, + .relatch_domain_sel_reg = ETDM_OUT4_CON0, + .relatch_domain_sel_mask = OUT_REG_RELATCH_DOMAIN_SEL_MASK, + .relatch_domain_sel_shift = OUT_REG_RELATCH_DOMAIN_SEL_SFT, + .bit_length_reg = ETDM_OUT4_CON0, + .bit_length_mask = OUT_REG_BIT_LENGTH_MASK, + .bit_length_shift = OUT_REG_BIT_LENGTH_SFT, + .word_length_reg = ETDM_OUT4_CON0, + .word_length_mask = OUT_REG_WORD_LENGTH_MASK, + .word_length_shift = OUT_REG_WORD_LENGTH_SFT, + .cowork_reg = ETDM_4_7_COWORK_CON0, + .cowork_mask = ETDM_OUT4_SLAVE_SEL_MASK, + .cowork_shift = ETDM_OUT4_SLAVE_SEL_SFT, + .cowork_val = ETDM_SLAVE_SEL_ETDMIN4_MASTER, + .in2latch_time_reg = ETDM_OUT4_CON2, + .in2latch_time_mask = OUT_REG_IN2LATCH_TIME_MASK, + .in2latch_time_shift = OUT_REG_IN2LATCH_TIME_SFT, + .pad_top_ck_en_reg = AUD_TOP_CFG_VLP_RG, + .pad_top_ck_en_mask = RG_I2S4_PAD_TOP_CK_EN_MASK, + .pad_top_ck_en_shift = RG_I2S4_PAD_TOP_CK_EN_SFT, + .master_latch_reg = AUD_TOP_CFG_VLP_RG, + .master_latch_mask = RG_I2S4_OUT_BCK_NEG_EG_LATCH_MASK, + .master_latch_shift = RG_I2S4_OUT_BCK_NEG_EG_LATCH_SFT, + }, + [DAI_I2SOUT6] = { + .enable_reg = ETDM_OUT6_CON0, + .enable_mask = OUT_REG_ETDM_OUT_EN_MASK, + .enable_shift = OUT_REG_ETDM_OUT_EN_SFT, + .sync_reg = ETDM_OUT6_CON0, + .sync_mask = REG_SYNC_MODE_MASK, + .sync_shift = REG_SYNC_MODE_SFT, + .ch_reg = ETDM_OUT6_CON0, + .ch_mask = REG_CH_NUM_MASK, + .ch_shift = REG_CH_NUM_SFT, + .init_count_reg = ETDM_OUT6_CON1, + .init_count_mask = OUT_REG_INITIAL_COUNT_MASK, + .init_count_shift = OUT_REG_INITIAL_COUNT_SFT, + .init_point_reg = ETDM_OUT6_CON1, + .init_point_mask = OUT_REG_INITIAL_POINT_MASK, + .init_point_shift = OUT_REG_INITIAL_POINT_SFT, + .lrck_reset_reg = ETDM_OUT6_CON1, + .lrck_reset_mask = OUT_REG_LRCK_RESET_MASK, + .lrck_reset_shift = OUT_REG_LRCK_RESET_SFT, + .clk_source_reg = ETDM_OUT6_CON4, + .clk_source_mask = OUT_REG_CLOCK_SOURCE_SEL_MASK, + .clk_source_shift = OUT_REG_CLOCK_SOURCE_SEL_SFT, + .fs_timing_reg = ETDM_OUT6_CON4, + .fs_timing_mask = OUT_REG_FS_TIMING_SEL_MASK, + .fs_timing_shift = OUT_REG_FS_TIMING_SEL_SFT, + .relatch_en_sel_reg = ETDM_OUT6_CON4, + .relatch_en_sel_mask = OUT_REG_RELATCH_EN_SEL_MASK, + .relatch_en_sel_shift = OUT_REG_RELATCH_EN_SEL_SFT, + .tdm_mode_reg = ETDM_OUT6_CON0, + .tdm_mode_mask = OUT_REG_FMT_MASK, + .tdm_mode_shift = OUT_REG_FMT_SFT, + .relatch_domain_sel_reg = ETDM_OUT6_CON0, + .relatch_domain_sel_mask = OUT_REG_RELATCH_DOMAIN_SEL_MASK, + .relatch_domain_sel_shift = OUT_REG_RELATCH_DOMAIN_SEL_SFT, + .bit_length_reg = ETDM_OUT6_CON0, + .bit_length_mask = OUT_REG_BIT_LENGTH_MASK, + .bit_length_shift = OUT_REG_BIT_LENGTH_SFT, + .word_length_reg = ETDM_OUT6_CON0, + .word_length_mask = OUT_REG_WORD_LENGTH_MASK, + .word_length_shift = OUT_REG_WORD_LENGTH_SFT, + .cowork_reg = ETDM_4_7_COWORK_CON2, + .cowork_mask = ETDM_OUT6_SLAVE_SEL_MASK, + .cowork_shift = ETDM_OUT6_SLAVE_SEL_SFT, + .cowork_val = ETDM_SLAVE_SEL_ETDMIN6_MASTER, + .in2latch_time_reg = ETDM_OUT6_CON2, + .in2latch_time_mask = OUT_REG_IN2LATCH_TIME_MASK, + .in2latch_time_shift = OUT_REG_IN2LATCH_TIME_SFT, + .pad_top_ck_en_reg = -1, + .master_latch_reg = -1, + }, + +}; + +/* lpbk */ +static const int etdm_lpbk_idx_0[] = { + 0x0, 0x8, +}; + +static const int etdm_lpbk_idx_1[] = { + 0x2, 0xa, +}; + +static const int etdm_lpbk_idx_2[] = { + 0x4, 0xc, +}; + +static const int etdm_lpbk_idx_3[] = { + 0x6, 0xe, +}; + +static int etdm_lpbk_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); + unsigned int value = 0; + unsigned int value_ipmode = 0; + unsigned int reg = 0; + unsigned int mask = 0; + unsigned int shift = 0; + + if (!strcmp(kcontrol->id.name, "I2SIN0_LPBK")) { + reg = ETDM_0_3_COWORK_CON1; + mask = ETDM_IN0_SDATA0_SEL_MASK_SFT; + shift = ETDM_IN0_SDATA0_SEL_SFT; + } else if (!strcmp(kcontrol->id.name, "I2SIN1_LPBK")) { + reg = ETDM_0_3_COWORK_CON1; + mask = ETDM_IN1_SDATA0_SEL_MASK_SFT; + shift = ETDM_IN1_SDATA0_SEL_SFT; + } else if (!strcmp(kcontrol->id.name, "I2SIN2_LPBK")) { + reg = ETDM_0_3_COWORK_CON3; + mask = ETDM_IN2_SDATA0_SEL_MASK_SFT; + shift = ETDM_IN2_SDATA0_SEL_SFT; + } else if (!strcmp(kcontrol->id.name, "I2SIN3_LPBK")) { + reg = ETDM_0_3_COWORK_CON3; + mask = ETDM_IN3_SDATA0_SEL_MASK_SFT; + shift = ETDM_IN3_SDATA0_SEL_SFT; + } else if (!strcmp(kcontrol->id.name, "I2SIN4_LPBK")) { + reg = ETDM_4_7_COWORK_CON1; + + // Get I2SIN4 multi-ip mode + regmap_read(afe->regmap, ETDM_IN4_CON2, &value_ipmode); + value_ipmode &= REG_MULTI_IP_MODE_MASK_SFT; + value_ipmode >>= REG_MULTI_IP_MODE_SFT; + + if (value_ipmode) { + mask = ETDM_IN4_SDATA1_15_SEL_MASK_SFT; + shift = ETDM_IN4_SDATA1_15_SEL_SFT; + } else { + mask = ETDM_IN4_SDATA0_SEL_MASK_SFT; + shift = ETDM_IN4_SDATA0_SEL_SFT; + } + } else if (!strcmp(kcontrol->id.name, "I2SIN6_LPBK")) { + reg = ETDM_4_7_COWORK_CON3; + mask = ETDM_IN6_SDATA0_SEL_MASK_SFT; + shift = ETDM_IN6_SDATA0_SEL_SFT; + } + + if (reg) + regmap_read(afe->regmap, reg, &value); + + value &= mask; + value >>= shift; + ucontrol->value.enumerated.item[0] = value; + + if (value == 0x8 || value == 0xa || value == 0xc || value == 0xe) + ucontrol->value.enumerated.item[0] = 1; + else + ucontrol->value.enumerated.item[0] = 0; + + return 0; +} + +static int etdm_lpbk_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); + unsigned int value = ucontrol->value.integer.value[0]; + unsigned int value_ipmode = 0; + unsigned int reg = 0; + unsigned int val = 0; + unsigned int mask = 0; + + if (value >= ARRAY_SIZE(etdm_lpbk_idx_0)) + return -EINVAL; + + if (!strcmp(kcontrol->id.name, "I2SIN0_LPBK")) { + reg = ETDM_0_3_COWORK_CON1; + mask = ETDM_IN0_SDATA0_SEL_MASK_SFT; + val = etdm_lpbk_idx_0[value] << ETDM_IN0_SDATA0_SEL_SFT; + } else if (!strcmp(kcontrol->id.name, "I2SIN1_LPBK")) { + reg = ETDM_0_3_COWORK_CON1; + mask = ETDM_IN1_SDATA0_SEL_MASK_SFT; + val = etdm_lpbk_idx_1[value] << ETDM_IN1_SDATA0_SEL_SFT; + } else if (!strcmp(kcontrol->id.name, "I2SIN2_LPBK")) { + reg = ETDM_0_3_COWORK_CON3; + mask = ETDM_IN2_SDATA0_SEL_MASK_SFT; + val = etdm_lpbk_idx_2[value] << ETDM_IN2_SDATA0_SEL_SFT; + } else if (!strcmp(kcontrol->id.name, "I2SIN3_LPBK")) { + reg = ETDM_0_3_COWORK_CON3; + mask = ETDM_IN3_SDATA0_SEL_MASK_SFT; + val = etdm_lpbk_idx_3[value] << ETDM_IN3_SDATA0_SEL_SFT; + } else if (!strcmp(kcontrol->id.name, "I2SIN4_LPBK")) { + reg = ETDM_4_7_COWORK_CON1; + + // Get I2SIN4 multi-ip mode + regmap_read(afe->regmap, ETDM_IN4_CON2, &value_ipmode); + value_ipmode &= REG_MULTI_IP_MODE_MASK_SFT; + value_ipmode >>= REG_MULTI_IP_MODE_SFT; + + if (!value) { + mask = ETDM_IN4_SDATA1_15_SEL_MASK_SFT | + ETDM_IN4_SDATA0_SEL_MASK_SFT; + val = (etdm_lpbk_idx_0[value] << ETDM_IN4_SDATA1_15_SEL_SFT) | + (etdm_lpbk_idx_0[value] << ETDM_IN4_SDATA0_SEL_SFT); + } else if (value_ipmode) { + mask = ETDM_IN4_SDATA1_15_SEL_MASK_SFT; + val = etdm_lpbk_idx_0[value] << ETDM_IN4_SDATA1_15_SEL_SFT; + } else { + mask = ETDM_IN4_SDATA0_SEL_MASK_SFT; + val = etdm_lpbk_idx_0[value] << ETDM_IN4_SDATA0_SEL_SFT; + } + } else { + reg = ETDM_4_7_COWORK_CON3; + mask = ETDM_IN6_SDATA0_SEL_MASK_SFT; + val = etdm_lpbk_idx_2[value] << ETDM_IN6_SDATA0_SEL_SFT; + } + + if (reg) + regmap_update_bits(afe->regmap, reg, mask, val); + + return 0; +} + +static const char *const etdm_lpbk_map[] = { + "Off", "On", +}; + +static SOC_ENUM_SINGLE_EXT_DECL(etdm_lpbk_map_enum, + etdm_lpbk_map); +/* lpbk */ + +/* multi-ip mode */ +static const int etdm_ip_mode_idx[] = { + 0x0, 0x1, +}; + +static int etdm_ip_mode_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); + struct mt8196_afe_private *afe_priv = afe->platform_priv; + struct mtk_afe_i2s_priv *i2sin4_priv = afe_priv->dai_priv[MT8196_DAI_I2S_IN4]; + + ucontrol->value.enumerated.item[0] = i2sin4_priv->ip_mode; + + return 0; +} + +static int etdm_ip_mode_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); + struct mt8196_afe_private *afe_priv = afe->platform_priv; + struct mtk_afe_i2s_priv *i2sin4_priv = afe_priv->dai_priv[MT8196_DAI_I2S_IN4]; + unsigned int value = ucontrol->value.integer.value[0]; + + if (value >= ARRAY_SIZE(etdm_ip_mode_idx)) + return -EINVAL; + + /* 0: One IP multi-channel 1: Multi-IP 2-channel */ + i2sin4_priv->ip_mode = etdm_ip_mode_idx[value]; + + return 0; +} + +static const char *const etdm_ip_mode_map[] = { + "Off", "On", +}; + +static SOC_ENUM_SINGLE_EXT_DECL(etdm_ip_mode_map_enum, + etdm_ip_mode_map); +/* multi-ip mode */ + +/* ch num */ +static const int etdm_ch_num_idx[] = { + 0x2, 0x4, 0x6, 0x8, +}; + +static int etdm_ch_num_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); + struct mt8196_afe_private *afe_priv = afe->platform_priv; + struct mtk_afe_i2s_priv *i2sin4_priv = afe_priv->dai_priv[MT8196_DAI_I2S_IN4]; + struct mtk_afe_i2s_priv *i2sout4_priv = afe_priv->dai_priv[MT8196_DAI_I2S_OUT4]; + unsigned int value = 0; + + if (!strcmp(kcontrol->id.name, "I2SIN4_CH_NUM")) + value = i2sin4_priv->ch_num; + else if (!strcmp(kcontrol->id.name, "I2SOUT4_CH_NUM")) + value = i2sout4_priv->ch_num; + + if (value == 0x2) + ucontrol->value.enumerated.item[0] = 0; + else if (value == 0x4) + ucontrol->value.enumerated.item[0] = 1; + else if (value == 0x6) + ucontrol->value.enumerated.item[0] = 2; + else + ucontrol->value.enumerated.item[0] = 3; + + return 0; +} + +static int etdm_ch_num_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); + struct mt8196_afe_private *afe_priv = afe->platform_priv; + struct mtk_afe_i2s_priv *i2sin4_priv = afe_priv->dai_priv[MT8196_DAI_I2S_IN4]; + struct mtk_afe_i2s_priv *i2sout4_priv = afe_priv->dai_priv[MT8196_DAI_I2S_OUT4]; + unsigned int value = ucontrol->value.integer.value[0]; + + if (value >= ARRAY_SIZE(etdm_ch_num_idx)) + return -EINVAL; + + if (!strcmp(kcontrol->id.name, "I2SIN4_CH_NUM")) + i2sin4_priv->ch_num = etdm_ch_num_idx[value]; + else if (!strcmp(kcontrol->id.name, "I2SOUT4_CH_NUM")) + i2sout4_priv->ch_num = etdm_ch_num_idx[value]; + + return 0; +} + +static const char *const etdm_ch_num_map[] = { + "2CH", "4CH", "6CH", "8CH", +}; + +static SOC_ENUM_SINGLE_EXT_DECL(etdm_ch_num_map_enum, + etdm_ch_num_map); +/* ch num */ + +enum { + I2S_FMT_EIAJ = 0, + I2S_FMT_I2S = 1, +}; + +enum { + I2S_WLEN_16_BIT = 0, + I2S_WLEN_32_BIT = 1, +}; + +enum { + I2S_HD_NORMAL = 0, + I2S_HD_LOW_JITTER = 1, +}; + +enum { + I2S1_SEL_O28_O29 = 0, + I2S1_SEL_O03_O04 = 1, +}; + +enum { + I2S_IN_PAD_CONNSYS = 0, + I2S_IN_PAD_IO_MUX = 1, +}; + +static unsigned int get_i2s_wlen(snd_pcm_format_t format) +{ + return snd_pcm_format_physical_width(format) <= 16 ? + I2S_WLEN_16_BIT : I2S_WLEN_32_BIT; +} + +#define MTK_AFE_I2SIN0_KCONTROL_NAME "I2SIN0_HD_Mux" +#define MTK_AFE_I2SIN1_KCONTROL_NAME "I2SIN1_HD_Mux" +#define MTK_AFE_I2SIN2_KCONTROL_NAME "I2SIN2_HD_Mux" +#define MTK_AFE_I2SIN4_KCONTROL_NAME "I2SIN4_HD_Mux" +#define MTK_AFE_I2SIN6_KCONTROL_NAME "I2SIN6_HD_Mux" +#define MTK_AFE_I2SOUT0_KCONTROL_NAME "I2SOUT0_HD_Mux" +#define MTK_AFE_I2SOUT1_KCONTROL_NAME "I2SOUT1_HD_Mux" +#define MTK_AFE_I2SOUT2_KCONTROL_NAME "I2SOUT2_HD_Mux" +#define MTK_AFE_I2SOUT4_KCONTROL_NAME "I2SOUT4_HD_Mux" +#define MTK_AFE_I2SOUT6_KCONTROL_NAME "I2SOUT6_HD_Mux" +#define MTK_AFE_FMI2S_MASTER_KCONTROL_NAME "FMI2S_MASTER_HD_Mux" + +#define I2SIN0_HD_EN_W_NAME "I2SIN0_HD_EN" +#define I2SIN1_HD_EN_W_NAME "I2SIN1_HD_EN" +#define I2SIN2_HD_EN_W_NAME "I2SIN2_HD_EN" +#define I2SIN3_HD_EN_W_NAME "I2SIN3_HD_EN" +#define I2SIN4_HD_EN_W_NAME "I2SIN4_HD_EN" +#define I2SIN6_HD_EN_W_NAME "I2SIN6_HD_EN" +#define I2SOUT0_HD_EN_W_NAME "I2SOUT0_HD_EN" +#define I2SOUT1_HD_EN_W_NAME "I2SOUT1_HD_EN" +#define I2SOUT2_HD_EN_W_NAME "I2SOUT2_HD_EN" +#define I2SOUT3_HD_EN_W_NAME "I2SOUT3_HD_EN" +#define I2SOUT4_HD_EN_W_NAME "I2SOUT4_HD_EN" +#define I2SOUT6_HD_EN_W_NAME "I2SOUT6_HD_EN" +#define FMI2S_MASTER_HD_EN_W_NAME "FMI2S_MASTER_HD_EN" + +#define I2SIN0_MCLK_EN_W_NAME "I2SIN0_MCLK_EN" +#define I2SIN1_MCLK_EN_W_NAME "I2SIN1_MCLK_EN" +#define I2SIN2_MCLK_EN_W_NAME "I2SIN2_MCLK_EN" +#define I2SIN3_MCLK_EN_W_NAME "I2SIN3_MCLK_EN" +#define I2SIN4_MCLK_EN_W_NAME "I2SIN4_MCLK_EN" +#define I2SIN6_MCLK_EN_W_NAME "I2SIN6_MCLK_EN" +#define I2SOUT0_MCLK_EN_W_NAME "I2SOUT0_MCLK_EN" +#define I2SOUT1_MCLK_EN_W_NAME "I2SOUT1_MCLK_EN" +#define I2SOUT2_MCLK_EN_W_NAME "I2SOUT2_MCLK_EN" +#define I2SOUT3_MCLK_EN_W_NAME "I2SOUT3_MCLK_EN" +#define I2SOUT4_MCLK_EN_W_NAME "I2SOUT4_MCLK_EN" +#define I2SOUT6_MCLK_EN_W_NAME "I2SOUT6_MCLK_EN" +#define FMI2S_MASTER_MCLK_EN_W_NAME "FMI2S_MASTER_MCLK_EN" + +static int get_i2s_id_by_name(struct mtk_base_afe *afe, + const char *name) +{ + if (strncmp(name, "I2SIN0", 6) == 0) + return MT8196_DAI_I2S_IN0; + else if (strncmp(name, "I2SIN1", 6) == 0) + return MT8196_DAI_I2S_IN1; + else if (strncmp(name, "I2SIN2", 6) == 0) + return MT8196_DAI_I2S_IN2; + else if (strncmp(name, "I2SIN3", 6) == 0) + return MT8196_DAI_I2S_IN3; + else if (strncmp(name, "I2SIN4", 6) == 0) + return MT8196_DAI_I2S_IN4; + else if (strncmp(name, "I2SIN6", 6) == 0) + return MT8196_DAI_I2S_IN6; + else if (strncmp(name, "I2SOUT0", 7) == 0) + return MT8196_DAI_I2S_OUT0; + else if (strncmp(name, "I2SOUT1", 7) == 0) + return MT8196_DAI_I2S_OUT1; + else if (strncmp(name, "I2SOUT2", 7) == 0) + return MT8196_DAI_I2S_OUT2; + else if (strncmp(name, "I2SOUT3", 7) == 0) + return MT8196_DAI_I2S_OUT3; + else if (strncmp(name, "I2SOUT4", 7) == 0) + return MT8196_DAI_I2S_OUT4; + else if (strncmp(name, "I2SOUT6", 7) == 0) + return MT8196_DAI_I2S_OUT6; + else if (strncmp(name, "FMI2S_MASTER", 12) == 0) + return MT8196_DAI_FM_I2S_MASTER; + else + return -EINVAL; +} + +static struct mtk_afe_i2s_priv *get_i2s_priv_by_name(struct mtk_base_afe *afe, + const char *name) +{ + struct mt8196_afe_private *afe_priv = afe->platform_priv; + int dai_id = get_i2s_id_by_name(afe, name); + + if (dai_id < 0) + return NULL; + + return afe_priv->dai_priv[dai_id]; +} + +/* + * bit mask for i2s low power control + * such as bit0 for i2s0, bit1 for i2s1... + * if set 1, means i2s low power mode + * if set 0, means i2s low jitter mode + * 0 for all i2s bit in default + */ +static unsigned int i2s_low_power_mask; +static int mtk_i2s_low_power_mask_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s(), mask: %x\n", __func__, i2s_low_power_mask); + ucontrol->value.integer.value[0] = i2s_low_power_mask; + return 0; +} + +static int mtk_i2s_low_power_mask_set(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + i2s_low_power_mask = ucontrol->value.integer.value[0]; + return 0; +} + +static int mtk_is_i2s_low_power(int i2s_num) +{ + int i2s_bit_shift; + + i2s_bit_shift = i2s_num - MT8196_DAI_I2S_IN0; + if (i2s_bit_shift < 0 || i2s_bit_shift > MT8196_DAI_I2S_MAX_NUM) + return 0; + + return (i2s_low_power_mask >> i2s_bit_shift) & 0x1; +} + +/* low jitter control */ +static const char *const mt8196_i2s_hd_str[] = { + "Normal", "Low_Jitter" +}; + +static const struct soc_enum mt8196_i2s_enum[] = { + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mt8196_i2s_hd_str), + mt8196_i2s_hd_str), +}; + +static int mt8196_i2s_hd_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); + struct mtk_afe_i2s_priv *i2s_priv; + + i2s_priv = get_i2s_priv_by_name(afe, kcontrol->id.name); + + if (!i2s_priv) + return -EINVAL; + + ucontrol->value.integer.value[0] = i2s_priv->low_jitter_en; + + return 0; +} + +static int mt8196_i2s_hd_set(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); + struct mtk_afe_i2s_priv *i2s_priv; + struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; + int hd_en; + + if (ucontrol->value.enumerated.item[0] >= e->items) + return -EINVAL; + + hd_en = ucontrol->value.integer.value[0]; + + dev_dbg(afe->dev, "kcontrol name %s, hd_en %d\n", kcontrol->id.name, hd_en); + + i2s_priv = get_i2s_priv_by_name(afe, kcontrol->id.name); + + if (!i2s_priv) + return -EINVAL; + + i2s_priv->low_jitter_en = hd_en; + + return 0; +} + +static const struct snd_kcontrol_new mtk_dai_i2s_controls[] = { + SOC_ENUM_EXT(MTK_AFE_I2SIN0_KCONTROL_NAME, mt8196_i2s_enum[0], + mt8196_i2s_hd_get, mt8196_i2s_hd_set), + SOC_ENUM_EXT(MTK_AFE_I2SIN1_KCONTROL_NAME, mt8196_i2s_enum[0], + mt8196_i2s_hd_get, mt8196_i2s_hd_set), + SOC_ENUM_EXT(MTK_AFE_I2SIN2_KCONTROL_NAME, mt8196_i2s_enum[0], + mt8196_i2s_hd_get, mt8196_i2s_hd_set), + SOC_ENUM_EXT(MTK_AFE_I2SIN4_KCONTROL_NAME, mt8196_i2s_enum[0], + mt8196_i2s_hd_get, mt8196_i2s_hd_set), + SOC_ENUM_EXT(MTK_AFE_I2SIN6_KCONTROL_NAME, mt8196_i2s_enum[0], + mt8196_i2s_hd_get, mt8196_i2s_hd_set), + SOC_ENUM_EXT(MTK_AFE_I2SOUT0_KCONTROL_NAME, mt8196_i2s_enum[0], + mt8196_i2s_hd_get, mt8196_i2s_hd_set), + SOC_ENUM_EXT(MTK_AFE_I2SOUT1_KCONTROL_NAME, mt8196_i2s_enum[0], + mt8196_i2s_hd_get, mt8196_i2s_hd_set), + SOC_ENUM_EXT(MTK_AFE_I2SOUT2_KCONTROL_NAME, mt8196_i2s_enum[0], + mt8196_i2s_hd_get, mt8196_i2s_hd_set), + SOC_ENUM_EXT(MTK_AFE_I2SOUT4_KCONTROL_NAME, mt8196_i2s_enum[0], + mt8196_i2s_hd_get, mt8196_i2s_hd_set), + SOC_ENUM_EXT(MTK_AFE_I2SOUT6_KCONTROL_NAME, mt8196_i2s_enum[0], + mt8196_i2s_hd_get, mt8196_i2s_hd_set), + SOC_ENUM_EXT(MTK_AFE_FMI2S_MASTER_KCONTROL_NAME, mt8196_i2s_enum[0], + mt8196_i2s_hd_get, mt8196_i2s_hd_set), + SOC_SINGLE_EXT("i2s_low_power_mask", SND_SOC_NOPM, 0, 0xffff, 0, + mtk_i2s_low_power_mask_get, + mtk_i2s_low_power_mask_set), + + SOC_ENUM_EXT("I2SIN0_LPBK", etdm_lpbk_map_enum, + etdm_lpbk_get, etdm_lpbk_put), + SOC_ENUM_EXT("I2SIN1_LPBK", etdm_lpbk_map_enum, + etdm_lpbk_get, etdm_lpbk_put), + SOC_ENUM_EXT("I2SIN2_LPBK", etdm_lpbk_map_enum, + etdm_lpbk_get, etdm_lpbk_put), + SOC_ENUM_EXT("I2SIN3_LPBK", etdm_lpbk_map_enum, + etdm_lpbk_get, etdm_lpbk_put), + SOC_ENUM_EXT("I2SIN4_LPBK", etdm_lpbk_map_enum, + etdm_lpbk_get, etdm_lpbk_put), + SOC_ENUM_EXT("I2SIN6_LPBK", etdm_lpbk_map_enum, + etdm_lpbk_get, etdm_lpbk_put), + SOC_ENUM_EXT("I2SIN4_IP_MODE", etdm_ip_mode_map_enum, + etdm_ip_mode_get, etdm_ip_mode_put), + SOC_ENUM_EXT("I2SIN4_CH_NUM", etdm_ch_num_map_enum, + etdm_ch_num_get, etdm_ch_num_put), + SOC_ENUM_EXT("I2SOUT4_CH_NUM", etdm_ch_num_map_enum, + etdm_ch_num_get, etdm_ch_num_put), +}; + +/* dai component */ +/* i2s virtual mux to output widget */ +static const char *const i2s_mux_map[] = { + "Normal", "Dummy_Widget", +}; + +static int i2s_mux_map_value[] = { + 0, 1, +}; + +static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(i2s_mux_map_enum, + SND_SOC_NOPM, + 0, + 1, + i2s_mux_map, + i2s_mux_map_value); + +static const struct snd_kcontrol_new i2s_in0_mux_control = + SOC_DAPM_ENUM("I2S IN0 Select", i2s_mux_map_enum); +static const struct snd_kcontrol_new i2s_in1_mux_control = + SOC_DAPM_ENUM("I2S IN1 Select", i2s_mux_map_enum); +static const struct snd_kcontrol_new i2s_in2_mux_control = + SOC_DAPM_ENUM("I2S IN2 Select", i2s_mux_map_enum); +static const struct snd_kcontrol_new i2s_in3_mux_control = + SOC_DAPM_ENUM("I2S IN3 Select", i2s_mux_map_enum); +static const struct snd_kcontrol_new i2s_in4_mux_control = + SOC_DAPM_ENUM("I2S IN4 Select", i2s_mux_map_enum); +static const struct snd_kcontrol_new i2s_in6_mux_control = + SOC_DAPM_ENUM("I2S IN6 Select", i2s_mux_map_enum); +static const struct snd_kcontrol_new i2s_out0_mux_control = + SOC_DAPM_ENUM("I2S OUT0 Select", i2s_mux_map_enum); +static const struct snd_kcontrol_new i2s_out1_mux_control = + SOC_DAPM_ENUM("I2S OUT1 Select", i2s_mux_map_enum); +static const struct snd_kcontrol_new i2s_out2_mux_control = + SOC_DAPM_ENUM("I2S OUT2 Select", i2s_mux_map_enum); +static const struct snd_kcontrol_new i2s_out3_mux_control = + SOC_DAPM_ENUM("I2S OUT3 Select", i2s_mux_map_enum); +static const struct snd_kcontrol_new i2s_out4_mux_control = + SOC_DAPM_ENUM("I2S OUT4 Select", i2s_mux_map_enum); +static const struct snd_kcontrol_new i2s_out6_mux_control = + SOC_DAPM_ENUM("I2S OUT6 Select", i2s_mux_map_enum); + +/* interconnection */ +static const struct snd_kcontrol_new mtk_i2sout0_ch1_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH1", AFE_CONN108_1, I_DL0_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN108_1, I_DL1_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN108_1, I_DL2_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN108_1, I_DL3_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN108_1, I_DL4_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN108_1, I_DL5_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN108_1, I_DL6_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH1", AFE_CONN108_1, I_DL7_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1", AFE_CONN108_1, I_DL8_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH1", AFE_CONN108_1, I_DL_24CH_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL23_CH1", AFE_CONN108_2, I_DL23_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL24_CH1", AFE_CONN108_2, I_DL24_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH1", AFE_CONN108_0, + I_GAIN0_OUT_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN108_0, + I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN108_0, + I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN108_0, + I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN108_4, + I_PCM_0_CAP_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN108_4, + I_PCM_1_CAP_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_2_OUT_CH1", AFE_CONN108_6, + I_SRC_2_OUT_CH1, 1, 0), +}; + +static const struct snd_kcontrol_new mtk_i2sout0_ch2_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH2", AFE_CONN109_1, I_DL0_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN109_1, I_DL1_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN109_1, I_DL2_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN109_1, I_DL3_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN109_1, I_DL4_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN109_1, I_DL5_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN109_1, I_DL6_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH2", AFE_CONN109_1, I_DL7_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2", AFE_CONN109_1, I_DL8_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH2", AFE_CONN109_1, I_DL_24CH_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL23_CH2", AFE_CONN109_2, I_DL23_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL24_CH2", AFE_CONN109_2, I_DL24_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH2", AFE_CONN109_0, + I_GAIN0_OUT_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN109_0, + I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN109_0, + I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN109_0, + I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN109_4, + I_PCM_0_CAP_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH2", AFE_CONN109_4, + I_PCM_0_CAP_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN109_4, + I_PCM_1_CAP_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN109_4, + I_PCM_1_CAP_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_2_OUT_CH2", AFE_CONN109_6, + I_SRC_2_OUT_CH2, 1, 0), +}; + +static const struct snd_kcontrol_new mtk_i2sout1_ch1_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH1", AFE_CONN110_1, I_DL0_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN110_1, I_DL1_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN110_1, I_DL2_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN110_1, I_DL3_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN110_1, I_DL4_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN110_1, I_DL5_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN110_1, I_DL6_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH1", AFE_CONN110_1, I_DL7_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1", AFE_CONN110_1, I_DL8_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH1", AFE_CONN110_1, I_DL_24CH_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH1", AFE_CONN110_0, + I_GAIN0_OUT_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN110_0, + I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN110_4, + I_PCM_0_CAP_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN110_4, + I_PCM_1_CAP_CH1, 1, 0), +}; + +static const struct snd_kcontrol_new mtk_i2sout1_ch2_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH2", AFE_CONN111_1, I_DL0_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN111_1, I_DL1_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN111_1, I_DL2_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN111_1, I_DL3_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN111_1, I_DL4_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN111_1, I_DL5_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN111_1, I_DL6_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH2", AFE_CONN111_1, I_DL7_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2", AFE_CONN111_1, I_DL8_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH2", AFE_CONN111_1, I_DL_24CH_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH2", AFE_CONN111_0, + I_GAIN0_OUT_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN111_0, + I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN111_4, + I_PCM_0_CAP_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH2", AFE_CONN111_4, + I_PCM_0_CAP_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN111_4, + I_PCM_1_CAP_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN111_4, + I_PCM_1_CAP_CH2, 1, 0), +}; + +static const struct snd_kcontrol_new mtk_i2sout2_ch1_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH1", AFE_CONN112_1, I_DL0_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN112_1, I_DL1_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN112_1, I_DL2_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN112_1, I_DL3_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN112_1, I_DL4_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN112_1, I_DL5_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN112_1, I_DL6_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH1", AFE_CONN112_1, I_DL7_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1", AFE_CONN112_1, I_DL8_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH1", AFE_CONN112_1, I_DL_24CH_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH1", AFE_CONN112_0, + I_GAIN0_OUT_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN112_0, + I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN112_4, + I_PCM_0_CAP_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN112_4, + I_PCM_1_CAP_CH1, 1, 0), +}; + +static const struct snd_kcontrol_new mtk_i2sout2_ch2_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH2", AFE_CONN113_1, I_DL0_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN113_1, I_DL1_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN113_1, I_DL2_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN113_1, I_DL3_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN113_1, I_DL4_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN113_1, I_DL5_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN113_1, I_DL6_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH2", AFE_CONN113_1, I_DL7_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2", AFE_CONN113_1, I_DL8_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH2", AFE_CONN113_1, I_DL_24CH_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH2", AFE_CONN113_0, + I_GAIN0_OUT_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN113_0, + I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN113_4, + I_PCM_0_CAP_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH2", AFE_CONN113_4, + I_PCM_0_CAP_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN113_4, + I_PCM_1_CAP_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN113_4, + I_PCM_1_CAP_CH2, 1, 0), +}; + +static const struct snd_kcontrol_new mtk_i2sout3_ch1_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH1", AFE_CONN114_1, I_DL0_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN114_1, I_DL1_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN114_1, I_DL2_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN114_1, I_DL3_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN114_1, I_DL4_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN114_1, I_DL5_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN114_1, I_DL6_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH1", AFE_CONN114_1, I_DL7_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1", AFE_CONN114_1, I_DL8_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH1", AFE_CONN114_1, I_DL_24CH_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH1", AFE_CONN114_0, + I_GAIN0_OUT_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN114_0, + I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN114_4, + I_PCM_0_CAP_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN114_4, + I_PCM_1_CAP_CH1, 1, 0), +}; + +static const struct snd_kcontrol_new mtk_i2sout3_ch2_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH2", AFE_CONN115_1, I_DL0_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN115_1, I_DL1_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN115_1, I_DL2_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN115_1, I_DL3_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN115_1, I_DL4_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN115_1, I_DL5_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN115_1, I_DL6_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH2", AFE_CONN115_1, I_DL7_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2", AFE_CONN115_1, I_DL8_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH2", AFE_CONN115_1, I_DL_24CH_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH2", AFE_CONN115_0, + I_GAIN0_OUT_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN115_0, + I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH2", AFE_CONN115_4, + I_PCM_0_CAP_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN115_4, + I_PCM_1_CAP_CH2, 1, 0), +}; + +static const struct snd_kcontrol_new mtk_i2sout4_ch1_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH1", AFE_CONN116_1, I_DL0_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN116_1, I_DL1_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN116_1, I_DL2_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN116_1, I_DL3_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN116_1, I_DL4_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN116_1, I_DL5_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN116_1, I_DL6_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH1", AFE_CONN116_1, I_DL7_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1", AFE_CONN116_1, I_DL8_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH1", AFE_CONN116_1, I_DL_24CH_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL24_CH1", AFE_CONN116_2, I_DL24_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH1", AFE_CONN116_0, + I_GAIN0_OUT_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN116_0, + I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN116_0, + I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN116_0, + I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN116_4, + I_PCM_0_CAP_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN116_4, + I_PCM_1_CAP_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_2_OUT_CH1", AFE_CONN116_6, + I_SRC_2_OUT_CH1, 1, 0), +}; + +static const struct snd_kcontrol_new mtk_i2sout4_ch2_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH2", AFE_CONN117_1, I_DL0_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN117_1, I_DL1_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN117_1, I_DL2_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN117_1, I_DL3_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN117_1, I_DL4_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN117_1, I_DL5_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN117_1, I_DL6_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH2", AFE_CONN117_1, I_DL7_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2", AFE_CONN117_1, I_DL8_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH2", AFE_CONN117_1, I_DL_24CH_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL24_CH2", AFE_CONN117_2, I_DL24_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH2", AFE_CONN117_0, + I_GAIN0_OUT_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN117_0, + I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN117_0, + I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN117_0, + I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN117_4, + I_PCM_0_CAP_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH2", AFE_CONN117_4, + I_PCM_0_CAP_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN117_4, + I_PCM_1_CAP_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN117_4, + I_PCM_1_CAP_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_2_OUT_CH2", AFE_CONN117_6, + I_SRC_2_OUT_CH2, 1, 0), +}; + +static const struct snd_kcontrol_new mtk_i2sout4_ch3_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH3", AFE_CONN118_1, I_DL_24CH_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN118_4, + I_PCM_0_CAP_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN118_4, + I_PCM_1_CAP_CH1, 1, 0), +}; + +static const struct snd_kcontrol_new mtk_i2sout4_ch4_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH4", AFE_CONN119_1, I_DL_24CH_CH4, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN118_4, + I_PCM_0_CAP_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN118_4, + I_PCM_1_CAP_CH1, 1, 0), +}; + +static const struct snd_kcontrol_new mtk_i2sout4_ch5_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH5", AFE_CONN120_1, I_DL_24CH_CH5, 1, 0), +}; + +static const struct snd_kcontrol_new mtk_i2sout4_ch6_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH6", AFE_CONN121_1, I_DL_24CH_CH6, 1, 0), +}; + +static const struct snd_kcontrol_new mtk_i2sout4_ch7_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH7", AFE_CONN122_1, I_DL_24CH_CH7, 1, 0), +}; + +static const struct snd_kcontrol_new mtk_i2sout4_ch8_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH8", AFE_CONN123_1, I_DL_24CH_CH8, 1, 0), +}; + +static const struct snd_kcontrol_new mtk_i2sout6_ch1_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH1", AFE_CONN148_1, I_DL0_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN148_1, I_DL1_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN148_1, I_DL2_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN148_1, I_DL3_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN148_1, I_DL4_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN148_1, I_DL5_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN148_1, I_DL6_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH1", AFE_CONN148_1, I_DL7_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1", AFE_CONN148_1, I_DL8_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL23_CH1", AFE_CONN148_2, I_DL23_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH1", AFE_CONN148_1, I_DL_24CH_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH1", AFE_CONN148_0, + I_GAIN0_OUT_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN148_0, + I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN148_4, + I_PCM_0_CAP_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN148_4, + I_PCM_1_CAP_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_1_OUT_CH1", AFE_CONN148_6, + I_SRC_1_OUT_CH1, 1, 0), +}; + +static const struct snd_kcontrol_new mtk_i2sout6_ch2_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH2", AFE_CONN149_1, I_DL0_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN149_1, I_DL1_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN149_1, I_DL2_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN149_1, I_DL3_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN149_1, I_DL4_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN149_1, I_DL5_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN149_1, I_DL6_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH2", AFE_CONN149_1, I_DL7_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2", AFE_CONN149_1, I_DL8_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL23_CH2", AFE_CONN149_2, I_DL23_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH2", AFE_CONN149_1, I_DL_24CH_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH2", AFE_CONN149_0, + I_GAIN0_OUT_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN149_0, + I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN149_4, + I_PCM_0_CAP_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH2", AFE_CONN149_4, + I_PCM_0_CAP_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN149_4, + I_PCM_1_CAP_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN149_4, + I_PCM_1_CAP_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_1_OUT_CH2", AFE_CONN148_6, + I_SRC_1_OUT_CH2, 1, 0), +}; + +enum { + SUPPLY_SEQ_APLL, + SUPPLY_SEQ_I2S_MCLK_EN, + SUPPLY_SEQ_I2S_HD_EN, + SUPPLY_SEQ_I2S_EN, +}; + +static int mtk_i2s_hd_en_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); + + dev_dbg(cmpnt->dev, "name %s, event 0x%x\n", w->name, event); + + return 0; +} + +static int mtk_apll_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); + + dev_dbg(cmpnt->dev, "name %s, event 0x%x\n", w->name, event); + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + if (strcmp(w->name, APLL1_W_NAME) == 0) + mt8196_apll1_enable(afe); + else + mt8196_apll2_enable(afe); + break; + case SND_SOC_DAPM_POST_PMD: + if (strcmp(w->name, APLL1_W_NAME) == 0) + mt8196_apll1_disable(afe); + else + mt8196_apll2_disable(afe); + break; + default: + break; + } + + return 0; +} + +static int mtk_mclk_en_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); + struct mtk_afe_i2s_priv *i2s_priv; + + dev_dbg(cmpnt->dev, "name %s, event 0x%x\n", w->name, event); + + i2s_priv = get_i2s_priv_by_name(afe, w->name); + + if (!i2s_priv) + return -EINVAL; + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + mt8196_mck_enable(afe, i2s_priv->mclk_id, i2s_priv->mclk_rate); + break; + case SND_SOC_DAPM_POST_PMD: + i2s_priv->mclk_rate = 0; + mt8196_mck_disable(afe, i2s_priv->mclk_id); + break; + default: + break; + } + + return 0; +} + +static const struct snd_soc_dapm_widget mtk_dai_i2s_widgets[] = { + SND_SOC_DAPM_MIXER("I2SOUT0_CH1", SND_SOC_NOPM, 0, 0, + mtk_i2sout0_ch1_mix, + ARRAY_SIZE(mtk_i2sout0_ch1_mix)), + SND_SOC_DAPM_MIXER("I2SOUT0_CH2", SND_SOC_NOPM, 0, 0, + mtk_i2sout0_ch2_mix, + ARRAY_SIZE(mtk_i2sout0_ch2_mix)), + + SND_SOC_DAPM_MIXER("I2SOUT1_CH1", SND_SOC_NOPM, 0, 0, + mtk_i2sout1_ch1_mix, + ARRAY_SIZE(mtk_i2sout1_ch1_mix)), + SND_SOC_DAPM_MIXER("I2SOUT1_CH2", SND_SOC_NOPM, 0, 0, + mtk_i2sout1_ch2_mix, + ARRAY_SIZE(mtk_i2sout1_ch2_mix)), + + SND_SOC_DAPM_MIXER("I2SOUT2_CH1", SND_SOC_NOPM, 0, 0, + mtk_i2sout2_ch1_mix, + ARRAY_SIZE(mtk_i2sout2_ch1_mix)), + SND_SOC_DAPM_MIXER("I2SOUT2_CH2", SND_SOC_NOPM, 0, 0, + mtk_i2sout2_ch2_mix, + ARRAY_SIZE(mtk_i2sout2_ch2_mix)), + + SND_SOC_DAPM_MIXER("I2SOUT3_CH1", SND_SOC_NOPM, 0, 0, + mtk_i2sout3_ch1_mix, + ARRAY_SIZE(mtk_i2sout3_ch1_mix)), + SND_SOC_DAPM_MIXER("I2SOUT3_CH2", SND_SOC_NOPM, 0, 0, + mtk_i2sout3_ch2_mix, + ARRAY_SIZE(mtk_i2sout3_ch2_mix)), + + SND_SOC_DAPM_MIXER("I2SOUT4_CH1", SND_SOC_NOPM, 0, 0, + mtk_i2sout4_ch1_mix, + ARRAY_SIZE(mtk_i2sout4_ch1_mix)), + SND_SOC_DAPM_MIXER("I2SOUT4_CH2", SND_SOC_NOPM, 0, 0, + mtk_i2sout4_ch2_mix, + ARRAY_SIZE(mtk_i2sout4_ch2_mix)), + SND_SOC_DAPM_MIXER("I2SOUT4_CH3", SND_SOC_NOPM, 0, 0, + mtk_i2sout4_ch3_mix, + ARRAY_SIZE(mtk_i2sout4_ch3_mix)), + SND_SOC_DAPM_MIXER("I2SOUT4_CH4", SND_SOC_NOPM, 0, 0, + mtk_i2sout4_ch4_mix, + ARRAY_SIZE(mtk_i2sout4_ch4_mix)), + SND_SOC_DAPM_MIXER("I2SOUT4_CH5", SND_SOC_NOPM, 0, 0, + mtk_i2sout4_ch5_mix, + ARRAY_SIZE(mtk_i2sout4_ch5_mix)), + SND_SOC_DAPM_MIXER("I2SOUT4_CH6", SND_SOC_NOPM, 0, 0, + mtk_i2sout4_ch6_mix, + ARRAY_SIZE(mtk_i2sout4_ch6_mix)), + SND_SOC_DAPM_MIXER("I2SOUT4_CH7", SND_SOC_NOPM, 0, 0, + mtk_i2sout4_ch7_mix, + ARRAY_SIZE(mtk_i2sout4_ch7_mix)), + SND_SOC_DAPM_MIXER("I2SOUT4_CH8", SND_SOC_NOPM, 0, 0, + mtk_i2sout4_ch8_mix, + ARRAY_SIZE(mtk_i2sout4_ch8_mix)), + + SND_SOC_DAPM_MIXER("I2SOUT6_CH1", SND_SOC_NOPM, 0, 0, + mtk_i2sout6_ch1_mix, + ARRAY_SIZE(mtk_i2sout6_ch1_mix)), + SND_SOC_DAPM_MIXER("I2SOUT6_CH2", SND_SOC_NOPM, 0, 0, + mtk_i2sout6_ch2_mix, + ARRAY_SIZE(mtk_i2sout6_ch2_mix)), + + /* i2s en*/ + SND_SOC_DAPM_SUPPLY_S("I2SIN0_EN", SUPPLY_SEQ_I2S_EN, + ETDM_IN0_CON0, REG_ETDM_IN_EN_SFT, 0, + NULL, 0), + SND_SOC_DAPM_SUPPLY_S("I2SIN1_EN", SUPPLY_SEQ_I2S_EN, + ETDM_IN1_CON0, REG_ETDM_IN_EN_SFT, 0, + NULL, 0), + SND_SOC_DAPM_SUPPLY_S("I2SIN2_EN", SUPPLY_SEQ_I2S_EN, + ETDM_IN2_CON0, REG_ETDM_IN_EN_SFT, 0, + NULL, 0), + SND_SOC_DAPM_SUPPLY_S("I2SIN3_EN", SUPPLY_SEQ_I2S_EN, + ETDM_IN3_CON0, REG_ETDM_IN_EN_SFT, 0, + NULL, 0), + SND_SOC_DAPM_SUPPLY_S("I2SIN4_EN", SUPPLY_SEQ_I2S_EN, + ETDM_IN4_CON0, REG_ETDM_IN_EN_SFT, 0, + NULL, 0), + SND_SOC_DAPM_SUPPLY_S("I2SIN6_EN", SUPPLY_SEQ_I2S_EN, + ETDM_IN6_CON0, REG_ETDM_IN_EN_SFT, 0, + NULL, 0), + SND_SOC_DAPM_SUPPLY_S("I2SOUT0_EN", SUPPLY_SEQ_I2S_EN, + ETDM_OUT0_CON0, OUT_REG_ETDM_OUT_EN_SFT, 0, + NULL, 0), + SND_SOC_DAPM_SUPPLY_S("I2SOUT1_EN", SUPPLY_SEQ_I2S_EN, + ETDM_OUT1_CON0, OUT_REG_ETDM_OUT_EN_SFT, 0, + NULL, 0), + SND_SOC_DAPM_SUPPLY_S("I2SOUT2_EN", SUPPLY_SEQ_I2S_EN, + ETDM_OUT2_CON0, OUT_REG_ETDM_OUT_EN_SFT, 0, + NULL, 0), + SND_SOC_DAPM_SUPPLY_S("I2SOUT3_EN", SUPPLY_SEQ_I2S_EN, + ETDM_OUT3_CON0, OUT_REG_ETDM_OUT_EN_SFT, 0, + NULL, 0), + SND_SOC_DAPM_SUPPLY_S("I2SOUT4_EN", SUPPLY_SEQ_I2S_EN, + ETDM_OUT4_CON0, OUT_REG_ETDM_OUT_EN_SFT, 0, + NULL, 0), + SND_SOC_DAPM_SUPPLY_S("I2SOUT6_EN", SUPPLY_SEQ_I2S_EN, + ETDM_OUT6_CON0, OUT_REG_ETDM_OUT_EN_SFT, 0, + NULL, 0), + SND_SOC_DAPM_SUPPLY_S("FMI2S_MASTER_EN", SUPPLY_SEQ_I2S_EN, + AFE_CONNSYS_I2S_CON, I2S_EN_SFT, 0, + NULL, 0), + + /* i2s hd en */ + SND_SOC_DAPM_SUPPLY_S(I2SIN0_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN, + SND_SOC_NOPM, 0, 0, + mtk_i2s_hd_en_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_SUPPLY_S(I2SIN1_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN, + SND_SOC_NOPM, 0, 0, + mtk_i2s_hd_en_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_SUPPLY_S(I2SIN2_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN, + SND_SOC_NOPM, 0, 0, + mtk_i2s_hd_en_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_SUPPLY_S(I2SIN3_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN, + SND_SOC_NOPM, 0, 0, + mtk_i2s_hd_en_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_SUPPLY_S(I2SIN4_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN, + SND_SOC_NOPM, 0, 0, + mtk_i2s_hd_en_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_SUPPLY_S(I2SIN6_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN, + SND_SOC_NOPM, 0, 0, + mtk_i2s_hd_en_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_SUPPLY_S(I2SOUT0_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN, + SND_SOC_NOPM, 0, 0, + mtk_i2s_hd_en_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_SUPPLY_S(I2SOUT1_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN, + SND_SOC_NOPM, 0, 0, + mtk_i2s_hd_en_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_SUPPLY_S(I2SOUT2_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN, + SND_SOC_NOPM, 0, 0, + mtk_i2s_hd_en_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_SUPPLY_S(I2SOUT3_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN, + SND_SOC_NOPM, 0, 0, + mtk_i2s_hd_en_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_SUPPLY_S(I2SOUT4_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN, + SND_SOC_NOPM, 0, 0, + mtk_i2s_hd_en_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_SUPPLY_S(I2SOUT6_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN, + SND_SOC_NOPM, 0, 0, + mtk_i2s_hd_en_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_SUPPLY_S(FMI2S_MASTER_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN, + AFE_CONNSYS_I2S_CON, I2S_HDEN_SFT, 0, + mtk_i2s_hd_en_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + + /* i2s mclk en */ + SND_SOC_DAPM_SUPPLY_S(I2SIN0_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN, + SND_SOC_NOPM, 0, 0, + mtk_mclk_en_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_SUPPLY_S(I2SIN1_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN, + SND_SOC_NOPM, 0, 0, + mtk_mclk_en_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_SUPPLY_S(I2SIN2_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN, + SND_SOC_NOPM, 0, 0, + mtk_mclk_en_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_SUPPLY_S(I2SIN3_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN, + SND_SOC_NOPM, 0, 0, + mtk_mclk_en_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_SUPPLY_S(I2SIN4_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN, + SND_SOC_NOPM, 0, 0, + mtk_mclk_en_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_SUPPLY_S(I2SIN6_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN, + SND_SOC_NOPM, 0, 0, + mtk_mclk_en_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_SUPPLY_S(I2SOUT0_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN, + SND_SOC_NOPM, 0, 0, + mtk_mclk_en_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_SUPPLY_S(I2SOUT1_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN, + SND_SOC_NOPM, 0, 0, + mtk_mclk_en_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_SUPPLY_S(I2SOUT2_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN, + SND_SOC_NOPM, 0, 0, + mtk_mclk_en_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_SUPPLY_S(I2SOUT3_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN, + SND_SOC_NOPM, 0, 0, + mtk_mclk_en_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_SUPPLY_S(I2SOUT4_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN, + SND_SOC_NOPM, 0, 0, + mtk_mclk_en_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_SUPPLY_S(I2SOUT6_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN, + SND_SOC_NOPM, 0, 0, + mtk_mclk_en_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_SUPPLY_S(FMI2S_MASTER_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN, + SND_SOC_NOPM, 0, 0, + mtk_mclk_en_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + + /* apll */ + SND_SOC_DAPM_SUPPLY_S(APLL1_W_NAME, SUPPLY_SEQ_APLL, + SND_SOC_NOPM, 0, 0, + mtk_apll_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_SUPPLY_S(APLL2_W_NAME, SUPPLY_SEQ_APLL, + SND_SOC_NOPM, 0, 0, + mtk_apll_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + + /* allow i2s on without codec on */ + SND_SOC_DAPM_OUTPUT("I2S_DUMMY_OUT"), + SND_SOC_DAPM_MUX("I2S_OUT0_Mux", + SND_SOC_NOPM, 0, 0, &i2s_out0_mux_control), + SND_SOC_DAPM_MUX("I2S_OUT1_Mux", + SND_SOC_NOPM, 0, 0, &i2s_out1_mux_control), + SND_SOC_DAPM_MUX("I2S_OUT2_Mux", + SND_SOC_NOPM, 0, 0, &i2s_out2_mux_control), + SND_SOC_DAPM_MUX("I2S_OUT3_Mux", + SND_SOC_NOPM, 0, 0, &i2s_out3_mux_control), + SND_SOC_DAPM_MUX("I2S_OUT4_Mux", + SND_SOC_NOPM, 0, 0, &i2s_out4_mux_control), + SND_SOC_DAPM_MUX("I2S_OUT6_Mux", + SND_SOC_NOPM, 0, 0, &i2s_out6_mux_control), + + SND_SOC_DAPM_INPUT("I2S_DUMMY_IN"), + SND_SOC_DAPM_MUX("I2S_IN0_Mux", + SND_SOC_NOPM, 0, 0, &i2s_in0_mux_control), + SND_SOC_DAPM_MUX("I2S_IN1_Mux", + SND_SOC_NOPM, 0, 0, &i2s_in1_mux_control), + SND_SOC_DAPM_MUX("I2S_IN2_Mux", + SND_SOC_NOPM, 0, 0, &i2s_in2_mux_control), + SND_SOC_DAPM_MUX("I2S_IN3_Mux", + SND_SOC_NOPM, 0, 0, &i2s_in3_mux_control), + SND_SOC_DAPM_MUX("I2S_IN4_Mux", + SND_SOC_NOPM, 0, 0, &i2s_in4_mux_control), + SND_SOC_DAPM_MUX("I2S_IN6_Mux", + SND_SOC_NOPM, 0, 0, &i2s_in6_mux_control), + + SND_SOC_DAPM_MIXER("SOF_DMA_DL_24CH", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_MIXER("SOF_DMA_DL1", SND_SOC_NOPM, 0, 0, NULL, 0), +}; + +static int mtk_afe_i2s_share_connect(struct snd_soc_dapm_widget *source, + struct snd_soc_dapm_widget *sink) +{ + struct snd_soc_dapm_widget *w = sink; + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); + struct mtk_afe_i2s_priv *i2s_priv; + int ret = 0; + + i2s_priv = get_i2s_priv_by_name(afe, sink->name); + + if (!i2s_priv) + return 0; + + if (i2s_priv->share_i2s_id < 0) + return 0; + + ret = (i2s_priv->share_i2s_id == get_i2s_id_by_name(afe, source->name)) ? 1 : 0; + + return ret; +} + +static int mtk_afe_i2s_hd_connect(struct snd_soc_dapm_widget *source, + struct snd_soc_dapm_widget *sink) +{ + struct snd_soc_dapm_widget *w = sink; + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); + struct mtk_afe_i2s_priv *i2s_priv; + int i2s_num; + + i2s_priv = get_i2s_priv_by_name(afe, sink->name); + + if (!i2s_priv) + return 0; + + i2s_num = get_i2s_id_by_name(afe, source->name); + if (get_i2s_id_by_name(afe, sink->name) == i2s_num) + return !mtk_is_i2s_low_power(i2s_num) || + i2s_priv->low_jitter_en; + + /* check if share i2s need hd en */ + if (i2s_priv->share_i2s_id < 0) + return 0; + + if (i2s_priv->share_i2s_id == i2s_num) + return !mtk_is_i2s_low_power(i2s_num) || + i2s_priv->low_jitter_en; + + return 0; +} + +static int mtk_afe_i2s_apll_connect(struct snd_soc_dapm_widget *source, + struct snd_soc_dapm_widget *sink) +{ + struct snd_soc_dapm_widget *w = sink; + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); + struct mtk_afe_i2s_priv *i2s_priv; + int cur_apll; + int i2s_need_apll; + + i2s_priv = get_i2s_priv_by_name(afe, w->name); + + if (!i2s_priv) + return 0; + + /* which apll */ + cur_apll = mt8196_get_apll_by_name(afe, source->name); + + /* choose APLL from i2s rate */ + i2s_need_apll = mt8196_get_apll_by_rate(afe, i2s_priv->rate); + + return (i2s_need_apll == cur_apll) ? 1 : 0; +} + +static int mtk_afe_i2s_mclk_connect(struct snd_soc_dapm_widget *source, + struct snd_soc_dapm_widget *sink) +{ + struct snd_soc_dapm_widget *w = sink; + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); + struct mtk_afe_i2s_priv *i2s_priv; + + i2s_priv = get_i2s_priv_by_name(afe, sink->name); + + if (!i2s_priv) + return 0; + + if (get_i2s_id_by_name(afe, sink->name) == + get_i2s_id_by_name(afe, source->name)) + return (i2s_priv->mclk_rate > 0) ? 1 : 0; + + /* check if share i2s need mclk */ + if (i2s_priv->share_i2s_id < 0) + return 0; + + if (i2s_priv->share_i2s_id == get_i2s_id_by_name(afe, source->name)) + return (i2s_priv->mclk_rate > 0) ? 1 : 0; + + return 0; +} + +static int mtk_afe_mclk_apll_connect(struct snd_soc_dapm_widget *source, + struct snd_soc_dapm_widget *sink) +{ + struct snd_soc_dapm_widget *w = sink; + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); + struct mtk_afe_i2s_priv *i2s_priv; + int cur_apll; + + i2s_priv = get_i2s_priv_by_name(afe, w->name); + + if (!i2s_priv) + return 0; + + /* which apll */ + cur_apll = mt8196_get_apll_by_name(afe, source->name); + + return (i2s_priv->mclk_apll == cur_apll) ? 1 : 0; +} + +static const struct snd_soc_dapm_route mtk_dai_i2s_routes[] = { + /* i2sin0 */ + {"I2SIN0", NULL, "I2SIN0_EN"}, + {"I2SIN0", NULL, "I2SIN1_EN", mtk_afe_i2s_share_connect}, + {"I2SIN0", NULL, "I2SIN2_EN", mtk_afe_i2s_share_connect}, + {"I2SIN0", NULL, "I2SIN3_EN", mtk_afe_i2s_share_connect}, + {"I2SIN0", NULL, "I2SIN4_EN", mtk_afe_i2s_share_connect}, + {"I2SIN0", NULL, "I2SIN6_EN", mtk_afe_i2s_share_connect}, + {"I2SIN0", NULL, "I2SOUT0_EN", mtk_afe_i2s_share_connect}, + {"I2SIN0", NULL, "I2SOUT1_EN", mtk_afe_i2s_share_connect}, + {"I2SIN0", NULL, "I2SOUT2_EN", mtk_afe_i2s_share_connect}, + {"I2SIN0", NULL, "I2SOUT3_EN", mtk_afe_i2s_share_connect}, + {"I2SIN0", NULL, "I2SOUT4_EN", mtk_afe_i2s_share_connect}, + {"I2SIN0", NULL, "I2SOUT6_EN", mtk_afe_i2s_share_connect}, + {"I2SIN0", NULL, "FMI2S_MASTER_EN", mtk_afe_i2s_share_connect}, + + {"I2SIN0", NULL, I2SIN0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN0", NULL, I2SIN1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN0", NULL, I2SIN2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN0", NULL, I2SIN3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN0", NULL, I2SIN4_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN0", NULL, I2SIN6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN0", NULL, I2SOUT0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN0", NULL, I2SOUT1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN0", NULL, I2SOUT2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN0", NULL, I2SOUT3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN0", NULL, I2SOUT4_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN0", NULL, I2SOUT6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN0", NULL, FMI2S_MASTER_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {I2SIN0_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect}, + {I2SIN0_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect}, + + {"I2SIN0", NULL, I2SIN0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN0", NULL, I2SIN1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN0", NULL, I2SIN2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN0", NULL, I2SIN3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN0", NULL, I2SIN4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN0", NULL, I2SIN6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN0", NULL, I2SOUT0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN0", NULL, I2SOUT1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN0", NULL, I2SOUT2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN0", NULL, I2SOUT3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN0", NULL, I2SOUT4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN0", NULL, I2SOUT6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN0", NULL, FMI2S_MASTER_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {I2SIN0_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, + {I2SIN0_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, + + /* i2sin1 */ + {"I2SIN1", NULL, "I2SIN0_EN", mtk_afe_i2s_share_connect}, + {"I2SIN1", NULL, "I2SIN1_EN"}, + {"I2SIN1", NULL, "I2SIN2_EN", mtk_afe_i2s_share_connect}, + {"I2SIN1", NULL, "I2SIN3_EN", mtk_afe_i2s_share_connect}, + {"I2SIN1", NULL, "I2SIN4_EN", mtk_afe_i2s_share_connect}, + {"I2SIN1", NULL, "I2SIN6_EN", mtk_afe_i2s_share_connect}, + {"I2SIN1", NULL, "I2SOUT0_EN", mtk_afe_i2s_share_connect}, + {"I2SIN1", NULL, "I2SOUT1_EN", mtk_afe_i2s_share_connect}, + {"I2SIN1", NULL, "I2SOUT2_EN", mtk_afe_i2s_share_connect}, + {"I2SIN1", NULL, "I2SOUT3_EN", mtk_afe_i2s_share_connect}, + {"I2SIN1", NULL, "I2SOUT4_EN", mtk_afe_i2s_share_connect}, + {"I2SIN1", NULL, "I2SOUT6_EN", mtk_afe_i2s_share_connect}, + {"I2SIN1", NULL, "FMI2S_MASTER_EN", mtk_afe_i2s_share_connect}, + + {"I2SIN1", NULL, I2SIN0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN1", NULL, I2SIN1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN1", NULL, I2SIN2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN1", NULL, I2SIN3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN1", NULL, I2SIN4_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN1", NULL, I2SIN6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN1", NULL, I2SOUT0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN1", NULL, I2SOUT1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN1", NULL, I2SOUT2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN1", NULL, I2SOUT3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN1", NULL, I2SOUT4_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN1", NULL, I2SOUT6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN1", NULL, FMI2S_MASTER_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {I2SIN1_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect}, + {I2SIN1_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect}, + + {"I2SIN1", NULL, I2SIN0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN1", NULL, I2SIN1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN1", NULL, I2SIN2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN1", NULL, I2SIN3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN1", NULL, I2SIN4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN1", NULL, I2SIN6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN1", NULL, I2SOUT0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN1", NULL, I2SOUT1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN1", NULL, I2SOUT2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN1", NULL, I2SOUT3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN1", NULL, I2SOUT4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN1", NULL, I2SOUT6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN1", NULL, FMI2S_MASTER_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {I2SIN1_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, + {I2SIN1_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, + + /* i2sin2 */ + {"I2SIN2", NULL, "I2SIN0_EN", mtk_afe_i2s_share_connect}, + {"I2SIN2", NULL, "I2SIN1_EN", mtk_afe_i2s_share_connect}, + {"I2SIN2", NULL, "I2SIN2_EN"}, + {"I2SIN2", NULL, "I2SIN3_EN", mtk_afe_i2s_share_connect}, + {"I2SIN2", NULL, "I2SIN4_EN", mtk_afe_i2s_share_connect}, + {"I2SIN2", NULL, "I2SIN6_EN", mtk_afe_i2s_share_connect}, + {"I2SIN2", NULL, "I2SOUT0_EN", mtk_afe_i2s_share_connect}, + {"I2SIN2", NULL, "I2SOUT1_EN", mtk_afe_i2s_share_connect}, + {"I2SIN2", NULL, "I2SOUT2_EN", mtk_afe_i2s_share_connect}, + {"I2SIN2", NULL, "I2SOUT3_EN", mtk_afe_i2s_share_connect}, + {"I2SIN2", NULL, "I2SOUT4_EN", mtk_afe_i2s_share_connect}, + {"I2SIN2", NULL, "I2SOUT6_EN", mtk_afe_i2s_share_connect}, + {"I2SIN2", NULL, "FMI2S_MASTER_EN", mtk_afe_i2s_share_connect}, + + {"I2SIN2", NULL, I2SIN0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN2", NULL, I2SIN1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN2", NULL, I2SIN2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN2", NULL, I2SIN3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN2", NULL, I2SIN4_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN2", NULL, I2SIN6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN2", NULL, I2SOUT0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN2", NULL, I2SOUT1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN2", NULL, I2SOUT2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN2", NULL, I2SOUT3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN2", NULL, I2SOUT4_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN2", NULL, I2SOUT6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN2", NULL, FMI2S_MASTER_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {I2SIN2_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect}, + {I2SIN2_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect}, + + {"I2SIN2", NULL, I2SIN0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN2", NULL, I2SIN1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN2", NULL, I2SIN2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN2", NULL, I2SIN3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN2", NULL, I2SIN4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN2", NULL, I2SIN6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN2", NULL, I2SOUT0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN2", NULL, I2SOUT1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN2", NULL, I2SOUT2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN2", NULL, I2SOUT3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN2", NULL, I2SOUT4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN2", NULL, I2SOUT6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN2", NULL, FMI2S_MASTER_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {I2SIN2_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, + {I2SIN2_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, + + /* i2sin3 */ + {"I2SIN3", NULL, "I2SIN0_EN", mtk_afe_i2s_share_connect}, + {"I2SIN3", NULL, "I2SIN1_EN", mtk_afe_i2s_share_connect}, + {"I2SIN3", NULL, "I2SIN2_EN", mtk_afe_i2s_share_connect}, + {"I2SIN3", NULL, "I2SIN3_EN"}, + {"I2SIN3", NULL, "I2SIN4_EN", mtk_afe_i2s_share_connect}, + {"I2SIN3", NULL, "I2SIN6_EN", mtk_afe_i2s_share_connect}, + {"I2SIN3", NULL, "I2SOUT0_EN", mtk_afe_i2s_share_connect}, + {"I2SIN3", NULL, "I2SOUT1_EN", mtk_afe_i2s_share_connect}, + {"I2SIN3", NULL, "I2SOUT2_EN", mtk_afe_i2s_share_connect}, + {"I2SIN3", NULL, "I2SOUT3_EN", mtk_afe_i2s_share_connect}, + {"I2SIN3", NULL, "I2SOUT4_EN", mtk_afe_i2s_share_connect}, + {"I2SIN3", NULL, "I2SOUT6_EN", mtk_afe_i2s_share_connect}, + {"I2SIN3", NULL, "FMI2S_MASTER_EN", mtk_afe_i2s_share_connect}, + + {"I2SIN3", NULL, I2SIN0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN3", NULL, I2SIN1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN3", NULL, I2SIN2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN3", NULL, I2SIN3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN3", NULL, I2SIN4_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN3", NULL, I2SIN6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN3", NULL, I2SOUT0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN3", NULL, I2SOUT1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN3", NULL, I2SOUT2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN3", NULL, I2SOUT3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN3", NULL, I2SOUT4_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN3", NULL, I2SOUT6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN3", NULL, FMI2S_MASTER_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {I2SIN3_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect}, + {I2SIN3_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect}, + + {"I2SIN3", NULL, I2SIN0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN3", NULL, I2SIN1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN3", NULL, I2SIN2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN3", NULL, I2SIN3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN3", NULL, I2SIN4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN3", NULL, I2SIN6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN3", NULL, I2SOUT0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN3", NULL, I2SOUT1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN3", NULL, I2SOUT2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN3", NULL, I2SOUT3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN3", NULL, I2SOUT4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN3", NULL, I2SOUT6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN3", NULL, FMI2S_MASTER_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {I2SIN3_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, + {I2SIN3_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, + + /* i2sin4 */ + {"I2SIN4", NULL, "I2SIN0_EN", mtk_afe_i2s_share_connect}, + {"I2SIN4", NULL, "I2SIN1_EN", mtk_afe_i2s_share_connect}, + {"I2SIN4", NULL, "I2SIN2_EN", mtk_afe_i2s_share_connect}, + {"I2SIN4", NULL, "I2SIN3_EN", mtk_afe_i2s_share_connect}, + {"I2SIN4", NULL, "I2SIN4_EN"}, + {"I2SIN4", NULL, "I2SIN6_EN", mtk_afe_i2s_share_connect}, + {"I2SIN4", NULL, "I2SOUT0_EN", mtk_afe_i2s_share_connect}, + {"I2SIN4", NULL, "I2SOUT1_EN", mtk_afe_i2s_share_connect}, + {"I2SIN4", NULL, "I2SOUT2_EN", mtk_afe_i2s_share_connect}, + {"I2SIN4", NULL, "I2SOUT3_EN", mtk_afe_i2s_share_connect}, + {"I2SIN4", NULL, "I2SOUT4_EN", mtk_afe_i2s_share_connect}, + {"I2SIN4", NULL, "I2SOUT6_EN", mtk_afe_i2s_share_connect}, + {"I2SIN4", NULL, "FMI2S_MASTER_EN", mtk_afe_i2s_share_connect}, + + {"I2SIN4", NULL, I2SIN0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN4", NULL, I2SIN1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN4", NULL, I2SIN2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN4", NULL, I2SIN3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN4", NULL, I2SIN4_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN4", NULL, I2SIN6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN4", NULL, I2SOUT0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN4", NULL, I2SOUT1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN4", NULL, I2SOUT2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN4", NULL, I2SOUT3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN4", NULL, I2SOUT4_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN4", NULL, I2SOUT6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN4", NULL, FMI2S_MASTER_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {I2SIN4_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect}, + {I2SIN4_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect}, + + {"I2SIN4", NULL, I2SIN0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN4", NULL, I2SIN1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN4", NULL, I2SIN2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN4", NULL, I2SIN3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN4", NULL, I2SIN4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN4", NULL, I2SIN6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN4", NULL, I2SOUT0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN4", NULL, I2SOUT1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN4", NULL, I2SOUT2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN4", NULL, I2SOUT3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN4", NULL, I2SOUT4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN4", NULL, I2SOUT6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN4", NULL, FMI2S_MASTER_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {I2SIN4_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, + {I2SIN4_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, + + /* i2sin6 */ + {"I2SIN6", NULL, "I2SIN0_EN", mtk_afe_i2s_share_connect}, + {"I2SIN6", NULL, "I2SIN1_EN", mtk_afe_i2s_share_connect}, + {"I2SIN6", NULL, "I2SIN2_EN", mtk_afe_i2s_share_connect}, + {"I2SIN6", NULL, "I2SIN3_EN", mtk_afe_i2s_share_connect}, + {"I2SIN6", NULL, "I2SIN4_EN", mtk_afe_i2s_share_connect}, + {"I2SIN6", NULL, "I2SIN6_EN"}, + {"I2SIN6", NULL, "I2SOUT0_EN", mtk_afe_i2s_share_connect}, + {"I2SIN6", NULL, "I2SOUT1_EN", mtk_afe_i2s_share_connect}, + {"I2SIN6", NULL, "I2SOUT2_EN", mtk_afe_i2s_share_connect}, + {"I2SIN6", NULL, "I2SOUT3_EN", mtk_afe_i2s_share_connect}, + {"I2SIN6", NULL, "I2SOUT4_EN", mtk_afe_i2s_share_connect}, + {"I2SIN6", NULL, "I2SOUT6_EN", mtk_afe_i2s_share_connect}, + {"I2SIN6", NULL, "FMI2S_MASTER_EN", mtk_afe_i2s_share_connect}, + + {"I2SIN6", NULL, I2SIN0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN6", NULL, I2SIN1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN6", NULL, I2SIN2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN6", NULL, I2SIN3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN6", NULL, I2SIN4_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN6", NULL, I2SIN6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN6", NULL, I2SOUT0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN6", NULL, I2SOUT1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN6", NULL, I2SOUT2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN6", NULL, I2SOUT3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN6", NULL, I2SOUT4_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN6", NULL, I2SOUT6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SIN6", NULL, FMI2S_MASTER_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {I2SIN6_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect}, + {I2SIN6_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect}, + + {"I2SIN6", NULL, I2SIN0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN6", NULL, I2SIN1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN6", NULL, I2SIN2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN6", NULL, I2SIN3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN6", NULL, I2SIN4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN6", NULL, I2SIN6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN6", NULL, I2SOUT0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN6", NULL, I2SOUT1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN6", NULL, I2SOUT2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN6", NULL, I2SOUT3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN6", NULL, I2SOUT4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN6", NULL, I2SOUT6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SIN6", NULL, FMI2S_MASTER_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {I2SIN6_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, + {I2SIN6_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, + + /* i2sout0 */ + {"I2SOUT0_CH1", "DL0_CH1", "DL0"}, + {"I2SOUT0_CH2", "DL0_CH2", "DL0"}, + {"I2SOUT0_CH1", "DL1_CH1", "DL1"}, + {"I2SOUT0_CH2", "DL1_CH2", "DL1"}, + {"I2SOUT0_CH1", "DL2_CH1", "DL2"}, + {"I2SOUT0_CH2", "DL2_CH2", "DL2"}, + {"I2SOUT0_CH1", "DL3_CH1", "DL3"}, + {"I2SOUT0_CH2", "DL3_CH2", "DL3"}, + {"I2SOUT0_CH1", "DL4_CH1", "DL4"}, + {"I2SOUT0_CH2", "DL4_CH2", "DL4"}, + {"I2SOUT0_CH1", "DL5_CH1", "DL5"}, + {"I2SOUT0_CH2", "DL5_CH2", "DL5"}, + {"I2SOUT0_CH1", "DL6_CH1", "DL6"}, + {"I2SOUT0_CH2", "DL6_CH2", "DL6"}, + {"I2SOUT0_CH1", "DL7_CH1", "DL7"}, + {"I2SOUT0_CH2", "DL7_CH2", "DL7"}, + {"I2SOUT0_CH1", "DL8_CH1", "DL8"}, + {"I2SOUT0_CH2", "DL8_CH2", "DL8"}, + {"I2SOUT0_CH1", "DL23_CH1", "DL23"}, + {"I2SOUT0_CH2", "DL23_CH2", "DL23"}, + {"I2SOUT0_CH1", "DL_24CH_CH1", "DL_24CH"}, + {"I2SOUT0_CH2", "DL_24CH_CH2", "DL_24CH"}, + + {"I2SOUT0_CH1", "DL24_CH1", "DL24"}, + {"I2SOUT0_CH2", "DL24_CH2", "DL24"}, + + {"I2SOUT0", NULL, "I2SOUT0_CH1"}, + {"I2SOUT0", NULL, "I2SOUT0_CH2"}, + + {"I2SOUT0", NULL, "I2SIN0_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT0", NULL, "I2SIN1_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT0", NULL, "I2SIN2_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT0", NULL, "I2SIN3_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT0", NULL, "I2SIN4_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT0", NULL, "I2SIN6_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT0", NULL, "I2SOUT0_EN"}, + {"I2SOUT0", NULL, "I2SOUT1_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT0", NULL, "I2SOUT2_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT0", NULL, "I2SOUT3_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT0", NULL, "I2SOUT4_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT0", NULL, "I2SOUT6_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT0", NULL, "FMI2S_MASTER_EN", mtk_afe_i2s_share_connect}, + + {"I2SOUT0", NULL, I2SIN0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT0", NULL, I2SIN1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT0", NULL, I2SIN2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT0", NULL, I2SIN3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT0", NULL, I2SIN4_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT0", NULL, I2SIN6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT0", NULL, I2SOUT0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT0", NULL, I2SOUT1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT0", NULL, I2SOUT2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT0", NULL, I2SOUT3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT0", NULL, I2SOUT4_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT0", NULL, I2SOUT6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT0", NULL, FMI2S_MASTER_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {I2SOUT0_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect}, + {I2SOUT0_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect}, + + {"I2SOUT0", NULL, I2SIN0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT0", NULL, I2SIN1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT0", NULL, I2SIN2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT0", NULL, I2SIN3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT0", NULL, I2SIN4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT0", NULL, I2SIN6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT0", NULL, I2SOUT0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT0", NULL, I2SOUT1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT0", NULL, I2SOUT2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT0", NULL, I2SOUT3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT0", NULL, I2SOUT4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT0", NULL, I2SOUT6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT0", NULL, FMI2S_MASTER_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {I2SOUT0_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, + {I2SOUT0_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, + + /* i2sout1 */ + {"I2SOUT1_CH1", "DL0_CH1", "DL0"}, + {"I2SOUT1_CH2", "DL0_CH2", "DL0"}, + {"I2SOUT1_CH1", "DL1_CH1", "DL1"}, + {"I2SOUT1_CH2", "DL1_CH2", "DL1"}, + {"I2SOUT1_CH1", "DL2_CH1", "DL2"}, + {"I2SOUT1_CH2", "DL2_CH2", "DL2"}, + {"I2SOUT1_CH1", "DL3_CH1", "DL3"}, + {"I2SOUT1_CH2", "DL3_CH2", "DL3"}, + {"I2SOUT1_CH1", "DL4_CH1", "DL4"}, + {"I2SOUT1_CH2", "DL4_CH2", "DL4"}, + {"I2SOUT1_CH1", "DL5_CH1", "DL5"}, + {"I2SOUT1_CH2", "DL5_CH2", "DL5"}, + {"I2SOUT1_CH1", "DL6_CH1", "DL6"}, + {"I2SOUT1_CH2", "DL6_CH2", "DL6"}, + {"I2SOUT1_CH1", "DL7_CH1", "DL7"}, + {"I2SOUT1_CH2", "DL7_CH2", "DL7"}, + {"I2SOUT1_CH1", "DL8_CH1", "DL8"}, + {"I2SOUT1_CH2", "DL8_CH2", "DL8"}, + {"I2SOUT1_CH1", "DL_24CH_CH1", "DL_24CH"}, + {"I2SOUT1_CH2", "DL_24CH_CH2", "DL_24CH"}, + + {"I2SOUT1", NULL, "I2SOUT1_CH1"}, + {"I2SOUT1", NULL, "I2SOUT1_CH2"}, + + {"I2SOUT1", NULL, "I2SIN0_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT1", NULL, "I2SIN1_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT1", NULL, "I2SIN2_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT1", NULL, "I2SIN3_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT1", NULL, "I2SIN4_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT1", NULL, "I2SIN6_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT1", NULL, "I2SOUT0_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT1", NULL, "I2SOUT1_EN"}, + {"I2SOUT1", NULL, "I2SOUT2_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT1", NULL, "I2SOUT3_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT1", NULL, "I2SOUT4_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT1", NULL, "I2SOUT6_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT1", NULL, "FMI2S_MASTER_EN", mtk_afe_i2s_share_connect}, + + {"I2SOUT1", NULL, I2SIN0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT1", NULL, I2SIN1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT1", NULL, I2SIN2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT1", NULL, I2SIN3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT1", NULL, I2SIN4_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT1", NULL, I2SIN6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT1", NULL, I2SOUT0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT1", NULL, I2SOUT1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT1", NULL, I2SOUT2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT1", NULL, I2SOUT3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT1", NULL, I2SOUT4_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT1", NULL, I2SOUT6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT1", NULL, FMI2S_MASTER_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {I2SOUT1_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect}, + {I2SOUT1_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect}, + + {"I2SOUT1", NULL, I2SIN0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT1", NULL, I2SIN1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT1", NULL, I2SIN2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT1", NULL, I2SIN3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT1", NULL, I2SIN4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT1", NULL, I2SIN6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT1", NULL, I2SOUT0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT1", NULL, I2SOUT1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT1", NULL, I2SOUT2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT1", NULL, I2SOUT3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT1", NULL, I2SOUT4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT1", NULL, I2SOUT6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT1", NULL, FMI2S_MASTER_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {I2SOUT1_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, + {I2SOUT1_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, + + /* i2sout2 */ + {"I2SOUT2_CH1", "DL0_CH1", "DL0"}, + {"I2SOUT2_CH2", "DL0_CH2", "DL0"}, + {"I2SOUT2_CH1", "DL1_CH1", "DL1"}, + {"I2SOUT2_CH2", "DL1_CH2", "DL1"}, + {"I2SOUT2_CH1", "DL2_CH1", "DL2"}, + {"I2SOUT2_CH2", "DL2_CH2", "DL2"}, + {"I2SOUT2_CH1", "DL3_CH1", "DL3"}, + {"I2SOUT2_CH2", "DL3_CH2", "DL3"}, + {"I2SOUT2_CH1", "DL4_CH1", "DL4"}, + {"I2SOUT2_CH2", "DL4_CH2", "DL4"}, + {"I2SOUT2_CH1", "DL5_CH1", "DL5"}, + {"I2SOUT2_CH2", "DL5_CH2", "DL5"}, + {"I2SOUT2_CH1", "DL6_CH1", "DL6"}, + {"I2SOUT2_CH2", "DL6_CH2", "DL6"}, + {"I2SOUT2_CH1", "DL7_CH1", "DL7"}, + {"I2SOUT2_CH2", "DL7_CH2", "DL7"}, + {"I2SOUT2_CH1", "DL8_CH1", "DL8"}, + {"I2SOUT2_CH2", "DL8_CH2", "DL8"}, + {"I2SOUT2_CH1", "DL_24CH_CH1", "DL_24CH"}, + {"I2SOUT2_CH2", "DL_24CH_CH2", "DL_24CH"}, + + {"I2SOUT2", NULL, "I2SOUT2_CH1"}, + {"I2SOUT2", NULL, "I2SOUT2_CH2"}, + + {"I2SOUT2", NULL, "I2SIN0_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT2", NULL, "I2SIN1_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT2", NULL, "I2SIN2_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT2", NULL, "I2SIN3_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT2", NULL, "I2SIN4_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT2", NULL, "I2SIN6_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT2", NULL, "I2SOUT0_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT2", NULL, "I2SOUT1_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT2", NULL, "I2SOUT2_EN"}, + {"I2SOUT2", NULL, "I2SOUT3_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT2", NULL, "I2SOUT4_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT2", NULL, "I2SOUT6_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT2", NULL, "FMI2S_MASTER_EN", mtk_afe_i2s_share_connect}, + + {"I2SOUT2", NULL, I2SIN0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT2", NULL, I2SIN1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT2", NULL, I2SIN2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT2", NULL, I2SIN3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT2", NULL, I2SIN4_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT2", NULL, I2SIN6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT2", NULL, I2SOUT0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT2", NULL, I2SOUT1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT2", NULL, I2SOUT2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT2", NULL, I2SOUT3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT2", NULL, I2SOUT4_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT2", NULL, I2SOUT6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT2", NULL, FMI2S_MASTER_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {I2SOUT2_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect}, + {I2SOUT2_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect}, + + {"I2SOUT2", NULL, I2SIN0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT2", NULL, I2SIN1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT2", NULL, I2SIN2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT2", NULL, I2SIN3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT2", NULL, I2SIN4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT2", NULL, I2SIN6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT2", NULL, I2SOUT0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT2", NULL, I2SOUT1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT2", NULL, I2SOUT2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT2", NULL, I2SOUT3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT2", NULL, I2SOUT4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT2", NULL, I2SOUT6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT2", NULL, FMI2S_MASTER_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {I2SOUT2_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, + {I2SOUT2_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, + + /* i2sout3 */ + {"I2SOUT3_CH1", "DL0_CH1", "DL0"}, + {"I2SOUT3_CH2", "DL0_CH2", "DL0"}, + {"I2SOUT3_CH1", "DL1_CH1", "DL1"}, + {"I2SOUT3_CH2", "DL1_CH2", "DL1"}, + {"I2SOUT3_CH1", "DL2_CH1", "DL2"}, + {"I2SOUT3_CH2", "DL2_CH2", "DL2"}, + {"I2SOUT3_CH1", "DL3_CH1", "DL3"}, + {"I2SOUT3_CH2", "DL3_CH2", "DL3"}, + {"I2SOUT3_CH1", "DL4_CH1", "DL4"}, + {"I2SOUT3_CH2", "DL4_CH2", "DL4"}, + {"I2SOUT3_CH1", "DL5_CH1", "DL5"}, + {"I2SOUT3_CH2", "DL5_CH2", "DL5"}, + {"I2SOUT3_CH1", "DL6_CH1", "DL6"}, + {"I2SOUT3_CH2", "DL6_CH2", "DL6"}, + {"I2SOUT3_CH1", "DL7_CH1", "DL7"}, + {"I2SOUT3_CH2", "DL7_CH2", "DL7"}, + {"I2SOUT3_CH1", "DL8_CH1", "DL8"}, + {"I2SOUT3_CH2", "DL8_CH2", "DL8"}, + {"I2SOUT3_CH1", "DL_24CH_CH1", "DL_24CH"}, + {"I2SOUT3_CH2", "DL_24CH_CH2", "DL_24CH"}, + + {"I2SOUT3", NULL, "I2SOUT3_CH1"}, + {"I2SOUT3", NULL, "I2SOUT3_CH2"}, + + {"I2SOUT3", NULL, "I2SIN0_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT3", NULL, "I2SIN1_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT3", NULL, "I2SIN2_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT3", NULL, "I2SIN3_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT3", NULL, "I2SIN4_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT3", NULL, "I2SIN6_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT3", NULL, "I2SOUT0_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT3", NULL, "I2SOUT1_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT3", NULL, "I2SOUT2_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT3", NULL, "I2SOUT3_EN"}, + {"I2SOUT3", NULL, "I2SOUT4_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT3", NULL, "I2SOUT6_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT3", NULL, "FMI2S_MASTER_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT3", NULL, I2SIN0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT3", NULL, I2SIN1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT3", NULL, I2SIN2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT3", NULL, I2SIN3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT3", NULL, I2SIN4_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT3", NULL, I2SIN6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT3", NULL, I2SOUT0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT3", NULL, I2SOUT1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT3", NULL, I2SOUT2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT3", NULL, I2SOUT3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT3", NULL, I2SOUT4_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT3", NULL, I2SOUT6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT3", NULL, FMI2S_MASTER_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {I2SOUT3_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect}, + {I2SOUT3_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect}, + + {"I2SOUT3", NULL, I2SIN0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT3", NULL, I2SIN1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT3", NULL, I2SIN2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT3", NULL, I2SIN3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT3", NULL, I2SIN4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT3", NULL, I2SIN6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT3", NULL, I2SOUT0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT3", NULL, I2SOUT1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT3", NULL, I2SOUT2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT3", NULL, I2SOUT3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT3", NULL, I2SOUT4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT3", NULL, I2SOUT6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT3", NULL, FMI2S_MASTER_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {I2SOUT3_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, + {I2SOUT3_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, + + /* i2sout4 */ + {"I2SOUT4_CH1", "DL0_CH1", "DL0"}, + {"I2SOUT4_CH2", "DL0_CH2", "DL0"}, + {"I2SOUT4_CH1", "DL1_CH1", "DL1"}, + {"I2SOUT4_CH2", "DL1_CH2", "DL1"}, + {"I2SOUT4_CH1", "DL2_CH1", "DL2"}, + {"I2SOUT4_CH2", "DL2_CH2", "DL2"}, + {"I2SOUT4_CH1", "DL3_CH1", "DL3"}, + {"I2SOUT4_CH2", "DL3_CH2", "DL3"}, + {"I2SOUT4_CH1", "DL4_CH1", "DL4"}, + {"I2SOUT4_CH2", "DL4_CH2", "DL4"}, + {"I2SOUT4_CH1", "DL5_CH1", "DL5"}, + {"I2SOUT4_CH2", "DL5_CH2", "DL5"}, + {"I2SOUT4_CH1", "DL6_CH1", "DL6"}, + {"I2SOUT4_CH2", "DL6_CH2", "DL6"}, + {"I2SOUT4_CH1", "DL7_CH1", "DL7"}, + {"I2SOUT4_CH2", "DL7_CH2", "DL7"}, + {"I2SOUT4_CH1", "DL8_CH1", "DL8"}, + {"I2SOUT4_CH2", "DL8_CH2", "DL8"}, + {"I2SOUT4_CH1", "DL_24CH_CH1", "DL_24CH"}, + {"I2SOUT4_CH2", "DL_24CH_CH2", "DL_24CH"}, + {"I2SOUT4_CH3", "DL_24CH_CH3", "DL_24CH"}, + {"I2SOUT4_CH4", "DL_24CH_CH4", "DL_24CH"}, + {"I2SOUT4_CH5", "DL_24CH_CH5", "DL_24CH"}, + {"I2SOUT4_CH6", "DL_24CH_CH6", "DL_24CH"}, + {"I2SOUT4_CH7", "DL_24CH_CH7", "DL_24CH"}, + {"I2SOUT4_CH8", "DL_24CH_CH8", "DL_24CH"}, + {"I2SOUT4_CH1", "DL24_CH1", "DL24"}, + {"I2SOUT4_CH2", "DL24_CH2", "DL24"}, + + /* SOF Downlink */ + {"I2SOUT4_CH1", "DL_24CH_CH1", "SOF_DMA_DL_24CH"}, + {"I2SOUT4_CH2", "DL_24CH_CH2", "SOF_DMA_DL_24CH"}, + {"I2SOUT4_CH3", "DL_24CH_CH3", "SOF_DMA_DL_24CH"}, + {"I2SOUT4_CH4", "DL_24CH_CH4", "SOF_DMA_DL_24CH"}, + + {"I2SOUT4", NULL, "I2SOUT4_CH1"}, + {"I2SOUT4", NULL, "I2SOUT4_CH2"}, + {"I2SOUT4", NULL, "I2SOUT4_CH3"}, + {"I2SOUT4", NULL, "I2SOUT4_CH4"}, + {"I2SOUT4", NULL, "I2SOUT4_CH5"}, + {"I2SOUT4", NULL, "I2SOUT4_CH6"}, + {"I2SOUT4", NULL, "I2SOUT4_CH7"}, + {"I2SOUT4", NULL, "I2SOUT4_CH8"}, + + {"I2SOUT4", NULL, "I2SIN0_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT4", NULL, "I2SIN1_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT4", NULL, "I2SIN2_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT4", NULL, "I2SIN3_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT4", NULL, "I2SIN4_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT4", NULL, "I2SIN6_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT4", NULL, "I2SOUT0_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT4", NULL, "I2SOUT1_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT4", NULL, "I2SOUT2_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT4", NULL, "I2SOUT3_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT4", NULL, "I2SOUT4_EN"}, + {"I2SOUT4", NULL, "I2SOUT6_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT4", NULL, "FMI2S_MASTER_EN", mtk_afe_i2s_share_connect}, + + {"I2SOUT4", NULL, I2SIN0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT4", NULL, I2SIN1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT4", NULL, I2SIN2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT4", NULL, I2SIN3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT4", NULL, I2SIN4_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT4", NULL, I2SIN6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT4", NULL, I2SOUT0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT4", NULL, I2SOUT1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT4", NULL, I2SOUT2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT4", NULL, I2SOUT3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT4", NULL, I2SOUT4_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT4", NULL, I2SOUT6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT4", NULL, FMI2S_MASTER_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {I2SOUT4_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect}, + {I2SOUT4_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect}, + + {"I2SOUT4", NULL, I2SIN0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT4", NULL, I2SIN1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT4", NULL, I2SIN2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT4", NULL, I2SIN3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT4", NULL, I2SIN4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT4", NULL, I2SIN6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT4", NULL, I2SOUT0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT4", NULL, I2SOUT1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT4", NULL, I2SOUT2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT4", NULL, I2SOUT3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT4", NULL, I2SOUT4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT4", NULL, I2SOUT6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT4", NULL, FMI2S_MASTER_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {I2SOUT4_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, + {I2SOUT4_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, + + /* i2sout6 */ + {"I2SOUT6_CH1", "DL0_CH1", "DL0"}, + {"I2SOUT6_CH2", "DL0_CH2", "DL0"}, + {"I2SOUT6_CH1", "DL1_CH1", "DL1"}, + {"I2SOUT6_CH2", "DL1_CH2", "DL1"}, + {"I2SOUT6_CH1", "DL2_CH1", "DL2"}, + {"I2SOUT6_CH2", "DL2_CH2", "DL2"}, + {"I2SOUT6_CH1", "DL3_CH1", "DL3"}, + {"I2SOUT6_CH2", "DL3_CH2", "DL3"}, + {"I2SOUT6_CH1", "DL4_CH1", "DL4"}, + {"I2SOUT6_CH2", "DL4_CH2", "DL4"}, + {"I2SOUT6_CH1", "DL5_CH1", "DL5"}, + {"I2SOUT6_CH2", "DL5_CH2", "DL5"}, + {"I2SOUT6_CH1", "DL6_CH1", "DL6"}, + {"I2SOUT6_CH2", "DL6_CH2", "DL6"}, + {"I2SOUT6_CH1", "DL7_CH1", "DL7"}, + {"I2SOUT6_CH2", "DL7_CH2", "DL7"}, + {"I2SOUT6_CH1", "DL8_CH1", "DL8"}, + {"I2SOUT6_CH2", "DL8_CH2", "DL8"}, + {"I2SOUT6_CH1", "DL23_CH1", "DL23"}, + {"I2SOUT6_CH2", "DL23_CH2", "DL23"}, + {"I2SOUT6_CH1", "DL_24CH_CH1", "DL_24CH"}, + {"I2SOUT6_CH2", "DL_24CH_CH2", "DL_24CH"}, + + /* SOF Downlink */ + {"I2SOUT6_CH1", "DL1_CH1", "SOF_DMA_DL1"}, + {"I2SOUT6_CH2", "DL1_CH2", "SOF_DMA_DL1"}, + {"I2SOUT6_CH1", "DL_24CH_CH1", "SOF_DMA_DL_24CH"}, + {"I2SOUT6_CH2", "DL_24CH_CH2", "SOF_DMA_DL_24CH"}, + + {"I2SOUT6", NULL, "I2SOUT6_CH1"}, + {"I2SOUT6", NULL, "I2SOUT6_CH2"}, + + {"I2SOUT6", NULL, "I2SIN0_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT6", NULL, "I2SIN1_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT6", NULL, "I2SIN2_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT6", NULL, "I2SIN3_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT6", NULL, "I2SIN4_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT6", NULL, "I2SIN6_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT6", NULL, "I2SOUT0_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT6", NULL, "I2SOUT1_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT6", NULL, "I2SOUT2_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT6", NULL, "I2SOUT3_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT6", NULL, "I2SOUT4_EN", mtk_afe_i2s_share_connect}, + {"I2SOUT6", NULL, "I2SOUT6_EN"}, + {"I2SOUT6", NULL, "FMI2S_MASTER_EN", mtk_afe_i2s_share_connect}, + + {"I2SOUT6", NULL, I2SIN0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT6", NULL, I2SIN1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT6", NULL, I2SIN2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT6", NULL, I2SIN3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT6", NULL, I2SIN4_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT6", NULL, I2SIN6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT6", NULL, I2SOUT0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT6", NULL, I2SOUT1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT6", NULL, I2SOUT2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT6", NULL, I2SOUT3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT6", NULL, I2SOUT4_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT6", NULL, I2SOUT6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2SOUT6", NULL, FMI2S_MASTER_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {I2SOUT6_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect}, + {I2SOUT6_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect}, + + {"I2SOUT6", NULL, I2SIN0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT6", NULL, I2SIN1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT6", NULL, I2SIN2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT6", NULL, I2SIN3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT6", NULL, I2SIN4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT6", NULL, I2SIN6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT6", NULL, I2SOUT0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT6", NULL, I2SOUT1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT6", NULL, I2SOUT2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT6", NULL, I2SOUT3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT6", NULL, I2SOUT4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT6", NULL, I2SOUT6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2SOUT6", NULL, FMI2S_MASTER_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {I2SOUT6_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, + {I2SOUT6_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, + + /* fmi2s */ + {"FMI2S_MASTER", NULL, "I2SIN0_EN", mtk_afe_i2s_share_connect}, + {"FMI2S_MASTER", NULL, "I2SIN1_EN", mtk_afe_i2s_share_connect}, + {"FMI2S_MASTER", NULL, "I2SIN2_EN", mtk_afe_i2s_share_connect}, + {"FMI2S_MASTER", NULL, "I2SIN3_EN", mtk_afe_i2s_share_connect}, + {"FMI2S_MASTER", NULL, "I2SIN4_EN", mtk_afe_i2s_share_connect}, + {"FMI2S_MASTER", NULL, "I2SIN6_EN", mtk_afe_i2s_share_connect}, + {"FMI2S_MASTER", NULL, "I2SOUT0_EN", mtk_afe_i2s_share_connect}, + {"FMI2S_MASTER", NULL, "I2SOUT1_EN", mtk_afe_i2s_share_connect}, + {"FMI2S_MASTER", NULL, "I2SOUT2_EN", mtk_afe_i2s_share_connect}, + {"FMI2S_MASTER", NULL, "I2SOUT3_EN", mtk_afe_i2s_share_connect}, + {"FMI2S_MASTER", NULL, "I2SOUT4_EN", mtk_afe_i2s_share_connect}, + {"FMI2S_MASTER", NULL, "I2SOUT6_EN", mtk_afe_i2s_share_connect}, + {"FMI2S_MASTER", NULL, "FMI2S_MASTER_EN"}, + + {"FMI2S_MASTER", NULL, I2SIN0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"FMI2S_MASTER", NULL, I2SIN1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"FMI2S_MASTER", NULL, I2SIN2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"FMI2S_MASTER", NULL, I2SIN3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"FMI2S_MASTER", NULL, I2SIN4_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"FMI2S_MASTER", NULL, I2SIN6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"FMI2S_MASTER", NULL, I2SOUT0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"FMI2S_MASTER", NULL, I2SOUT1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"FMI2S_MASTER", NULL, I2SOUT2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"FMI2S_MASTER", NULL, I2SOUT3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"FMI2S_MASTER", NULL, I2SOUT4_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"FMI2S_MASTER", NULL, I2SOUT6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"FMI2S_MASTER", NULL, FMI2S_MASTER_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {FMI2S_MASTER_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect}, + {FMI2S_MASTER_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect}, + + {"FMI2S_MASTER", NULL, I2SIN0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"FMI2S_MASTER", NULL, I2SIN1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"FMI2S_MASTER", NULL, I2SIN2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"FMI2S_MASTER", NULL, I2SIN3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"FMI2S_MASTER", NULL, I2SIN4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"FMI2S_MASTER", NULL, I2SIN6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"FMI2S_MASTER", NULL, I2SOUT0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"FMI2S_MASTER", NULL, I2SOUT1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"FMI2S_MASTER", NULL, I2SOUT2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"FMI2S_MASTER", NULL, I2SOUT3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"FMI2S_MASTER", NULL, I2SOUT4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"FMI2S_MASTER", NULL, I2SOUT6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"FMI2S_MASTER", NULL, FMI2S_MASTER_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {FMI2S_MASTER_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, + {FMI2S_MASTER_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, + + /* allow i2s on without codec on */ + {"I2SIN0", NULL, "I2S_IN0_Mux"}, + {"I2S_IN0_Mux", "Dummy_Widget", "I2S_DUMMY_IN"}, + + {"I2SIN1", NULL, "I2S_IN1_Mux"}, + {"I2S_IN1_Mux", "Dummy_Widget", "I2S_DUMMY_IN"}, + + {"I2SIN2", NULL, "I2S_IN2_Mux"}, + {"I2S_IN2_Mux", "Dummy_Widget", "I2S_DUMMY_IN"}, + + {"I2SIN3", NULL, "I2S_IN3_Mux"}, + {"I2S_IN3_Mux", "Dummy_Widget", "I2S_DUMMY_IN"}, + + {"I2SIN4", NULL, "I2S_IN4_Mux"}, + {"I2S_IN4_Mux", "Dummy_Widget", "I2S_DUMMY_IN"}, + + {"I2SIN6", NULL, "I2S_IN6_Mux"}, + {"I2S_IN6_Mux", "Dummy_Widget", "I2S_DUMMY_IN"}, + + {"I2S_OUT0_Mux", "Dummy_Widget", "I2SOUT0"}, + {"I2S_DUMMY_OUT", NULL, "I2S_OUT0_Mux"}, + + {"I2S_OUT1_Mux", "Dummy_Widget", "I2SOUT1"}, + {"I2S_DUMMY_OUT", NULL, "I2S_OUT1_Mux"}, + + {"I2S_OUT2_Mux", "Dummy_Widget", "I2SOUT2"}, + {"I2S_DUMMY_OUT", NULL, "I2S_OUT2_Mux"}, + + {"I2S_OUT3_Mux", "Dummy_Widget", "I2SOUT3"}, + {"I2S_DUMMY_OUT", NULL, "I2S_OUT3_Mux"}, + {"I2S_OUT4_Mux", "Dummy_Widget", "I2SOUT4"}, + {"I2S_DUMMY_OUT", NULL, "I2S_OUT4_Mux"}, + + {"I2S_OUT6_Mux", "Dummy_Widget", "I2SOUT6"}, + {"I2S_DUMMY_OUT", NULL, "I2S_OUT6_Mux"}, +}; + +/* i2s dai ops*/ +static int mtk_dai_i2s_config(struct mtk_base_afe *afe, + struct snd_pcm_hw_params *params, + int i2s_id) +{ + struct mt8196_afe_private *afe_priv = afe->platform_priv; + struct mtk_afe_i2s_priv *i2s_priv; + struct mtk_afe_i2s_priv *i2sin_priv = NULL; + int id = i2s_id - MT8196_DAI_I2S_IN0; //47 + struct mtk_base_etdm_data etdm_data; + unsigned int rate = params_rate(params); + unsigned int rate_reg = get_etdm_inconn_rate(rate); + snd_pcm_format_t format = params_format(params); + unsigned int channels = params_channels(params); + unsigned int i2s_con = 0; + int ret = 0; + int pad_top = 0; + + if (i2s_id >= MT8196_DAI_NUM || i2s_id < 0) + return -EINVAL; + i2s_priv = afe_priv->dai_priv[i2s_id]; + + if (i2s_priv) + i2s_priv->rate = rate; + + dev_info(afe->dev, "id: %d, rate: %d, pcm_fmt: %d, fmt: %d, ch: %d\n", + i2s_id, rate, format, i2s_priv->format, channels); + + if (id < 0 || id >= DAI_I2S_NUM) { + dev_err(afe->dev, "i2s id is invalid\n"); + return -EINVAL; + } + etdm_data = mtk_etdm_data[id]; + + if (is_etdm_in_pad_top(id)) + pad_top = 0x3; + else + pad_top = 0x5; + + switch (id) { + case DAI_FMI2S_MASTER: + i2s_con = I2S_IN_PAD_IO_MUX << I2SIN_PAD_SEL_SFT; + i2s_con |= rate_reg << I2S_MODE_SFT; + i2s_con |= I2S_FMT_I2S << I2S_FMT_SFT; + i2s_con |= get_i2s_wlen(format) << I2S_WLEN_SFT; + regmap_update_bits(afe->regmap, AFE_CONNSYS_I2S_CON, + 0xffffeffe, i2s_con); + break; + case DAI_I2SIN0: + case DAI_I2SIN1: + case DAI_I2SIN2: + case DAI_I2SIN3: + case DAI_I2SIN4: + case DAI_I2SIN6: + /* ---etdm in --- */ + regmap_update_bits(afe->regmap, + etdm_data.init_count_reg, + etdm_data.init_count_mask << etdm_data.init_count_shift, + 0x5 << etdm_data.init_count_shift); + + /* 3: pad top 5: no pad top */ + regmap_update_bits(afe->regmap, + etdm_data.init_point_reg, + etdm_data.init_point_mask << etdm_data.init_point_shift, + pad_top << etdm_data.init_point_shift); + + regmap_update_bits(afe->regmap, + etdm_data.lrck_reset_reg, + etdm_data.lrck_reset_mask << etdm_data.lrck_reset_shift, + 0x1 << etdm_data.lrck_reset_shift); + + regmap_update_bits(afe->regmap, + etdm_data.clk_source_reg, + etdm_data.clk_source_mask << etdm_data.clk_source_shift, + ETDM_CLK_SOURCE_APLL << etdm_data.clk_source_shift); + + /* 0: manual 1: auto */ + regmap_update_bits(afe->regmap, + etdm_data.ck_en_sel_reg, + etdm_data.ck_en_sel_mask << etdm_data.ck_en_sel_shift, + 0x1 << etdm_data.ck_en_sel_shift); + + regmap_update_bits(afe->regmap, + etdm_data.fs_timing_reg, + etdm_data.fs_timing_mask << etdm_data.fs_timing_shift, + get_etdm_rate(rate) << etdm_data.fs_timing_shift); + + regmap_update_bits(afe->regmap, + etdm_data.relatch_en_sel_reg, + etdm_data.relatch_en_sel_mask << etdm_data.relatch_en_sel_shift, + get_etdm_inconn_rate(rate) << etdm_data.relatch_en_sel_shift); + + regmap_update_bits(afe->regmap, + etdm_data.use_afifo_reg, + etdm_data.use_afifo_mask << etdm_data.use_afifo_shift, + 0x0 << etdm_data.use_afifo_shift); + + regmap_update_bits(afe->regmap, + etdm_data.afifo_mode_reg, + etdm_data.afifo_mode_mask << etdm_data.afifo_mode_shift, + 0x0 << etdm_data.afifo_mode_shift); + + regmap_update_bits(afe->regmap, + etdm_data.almost_end_ch_reg, + etdm_data.almost_end_ch_mask << etdm_data.almost_end_ch_shift, + 0x0 << etdm_data.almost_end_ch_shift); + + regmap_update_bits(afe->regmap, + etdm_data.almost_end_bit_reg, + etdm_data.almost_end_bit_mask << etdm_data.almost_end_bit_shift, + 0x0 << etdm_data.almost_end_bit_shift); + + if (is_etdm_in_pad_top(id)) { + regmap_update_bits(afe->regmap, + etdm_data.out2latch_time_reg, + etdm_data.out2latch_time_mask << + etdm_data.out2latch_time_shift, + 0x6 << etdm_data.out2latch_time_shift); + } else { + regmap_update_bits(afe->regmap, + etdm_data.out2latch_time_reg, + etdm_data.out2latch_time_mask << + etdm_data.out2latch_time_shift, + 0x4 << etdm_data.out2latch_time_shift); + } + + if (id == DAI_I2SIN4) { + dev_dbg(afe->dev, "i2sin4, id: %d, fmt: %d, ch: %d, ip_mode: %d, sync: %d\n", + id, + i2s_priv->format, + i2s_priv->ch_num, + i2s_priv->ip_mode, + i2s_priv->sync); + + /* Fmt Mode: 0x00 i2s, 0x04 adsp_a, DSP_A mode for multi-channel */ + regmap_update_bits(afe->regmap, + etdm_data.tdm_mode_reg, + etdm_data.tdm_mode_mask << etdm_data.tdm_mode_shift, + i2s_priv->format << etdm_data.tdm_mode_shift); + + /* set etdm ch */ + regmap_update_bits(afe->regmap, + etdm_data.ch_reg, + etdm_data.ch_mask << etdm_data.ch_shift, + (i2s_priv->ch_num - 1) << etdm_data.ch_shift); + + /* set etdm ip mode */ + regmap_update_bits(afe->regmap, + etdm_data.ip_mode_reg, + etdm_data.ip_mode_mask << etdm_data.ip_mode_shift, + i2s_priv->ip_mode << etdm_data.ip_mode_shift); + + /* set etdm sync */ + regmap_update_bits(afe->regmap, + etdm_data.sync_reg, + etdm_data.sync_mask << etdm_data.sync_shift, + i2s_priv->sync << etdm_data.sync_shift); + } else { + /* default i2s */ + regmap_update_bits(afe->regmap, + etdm_data.tdm_mode_reg, + etdm_data.tdm_mode_mask << etdm_data.tdm_mode_shift, + 0x0 << etdm_data.tdm_mode_shift); + + /* set etdm sync */ + regmap_update_bits(afe->regmap, + etdm_data.sync_reg, + etdm_data.sync_mask << etdm_data.sync_shift, + 0x0 << etdm_data.sync_shift); + } + + /* APLL */ + regmap_update_bits(afe->regmap, + etdm_data.relatch_domain_sel_reg, + etdm_data.relatch_domain_sel_mask << + etdm_data.relatch_domain_sel_shift, + ETDM_RELATCH_SEL_APLL << etdm_data.relatch_domain_sel_shift); + + regmap_update_bits(afe->regmap, + etdm_data.bit_length_reg, + etdm_data.bit_length_mask << etdm_data.bit_length_shift, + get_etdm_lrck_width(format) << etdm_data.bit_length_shift); + + regmap_update_bits(afe->regmap, + etdm_data.word_length_reg, + etdm_data.word_length_mask << etdm_data.word_length_shift, + get_etdm_wlen(format) << etdm_data.word_length_shift); + + /* ---etdm cowork --- */ + regmap_update_bits(afe->regmap, + etdm_data.cowork_reg, + etdm_data.cowork_mask << etdm_data.cowork_shift, + etdm_data.cowork_val << etdm_data.cowork_shift); + + /* i2s with pad top setting */ + if (is_etdm_in_pad_top(id) && etdm_data.pad_top_ck_en_reg != -1) { + regmap_update_bits(afe->regmap, + etdm_data.pad_top_ck_en_reg, + etdm_data.pad_top_ck_en_mask << + etdm_data.pad_top_ck_en_shift, + 0x1 << etdm_data.pad_top_ck_en_shift); + + regmap_update_bits(afe->regmap, + etdm_data.master_latch_reg, + etdm_data.master_latch_mask << + etdm_data.master_latch_shift, + 0x0 << etdm_data.master_latch_shift); + } + break; + case DAI_I2SOUT0: + case DAI_I2SOUT1: + case DAI_I2SOUT2: + case DAI_I2SOUT3: + case DAI_I2SOUT4: + case DAI_I2SOUT6: + /* ---etdm out --- */ + regmap_update_bits(afe->regmap, + etdm_data.init_count_reg, + etdm_data.init_count_mask << etdm_data.init_count_shift, + 0x5 << etdm_data.init_count_shift); + + regmap_update_bits(afe->regmap, + etdm_data.init_point_reg, + etdm_data.init_point_mask << etdm_data.init_point_shift, + 0x6 << etdm_data.init_point_shift); + + // clock speed > 22M need to set relatch time to avoid duplicate porint + if (rate * channels * (get_etdm_wlen(format) + 1) >= ETDM_22M_CLOCK_THRES && + get_etdm_wlen(format) >= 2) { + regmap_update_bits(afe->regmap, + etdm_data.in2latch_time_reg, + etdm_data.in2latch_time_mask << + etdm_data.in2latch_time_shift, + (get_etdm_wlen(format) - 2) << + etdm_data.in2latch_time_shift); + } else { + regmap_update_bits(afe->regmap, + etdm_data.in2latch_time_reg, + etdm_data.in2latch_time_mask << + etdm_data.in2latch_time_shift, + 0x6 << etdm_data.in2latch_time_shift); + } + + regmap_update_bits(afe->regmap, + etdm_data.lrck_reset_reg, + etdm_data.lrck_reset_mask << etdm_data.lrck_reset_shift, + 0x1 << etdm_data.lrck_reset_shift); + + regmap_update_bits(afe->regmap, + etdm_data.fs_timing_reg, + etdm_data.fs_timing_mask << etdm_data.fs_timing_shift, + get_etdm_rate(rate) << etdm_data.fs_timing_shift); + + regmap_update_bits(afe->regmap, + etdm_data.clk_source_reg, + etdm_data.clk_source_mask << etdm_data.clk_source_shift, + ETDM_CLK_SOURCE_APLL << etdm_data.clk_source_shift); + + regmap_update_bits(afe->regmap, + etdm_data.relatch_en_sel_reg, + etdm_data.relatch_en_sel_mask << etdm_data.relatch_en_sel_shift, + get_etdm_inconn_rate(rate) << etdm_data.relatch_en_sel_shift); + + if (id == DAI_I2SOUT4) { + dev_dbg(afe->dev, "i2sout4, id: %d fmt: %d, ch: %d, sync: %d\n", + id, i2s_priv->format, i2s_priv->ch_num, i2s_priv->sync); + + /* Fmt Mode: 0x00 i2s, 0x04 adsp_a, DSP_A mode for multi-channel */ + regmap_update_bits(afe->regmap, + etdm_data.tdm_mode_reg, + etdm_data.tdm_mode_mask << etdm_data.tdm_mode_shift, + i2s_priv->format << etdm_data.tdm_mode_shift); + + /* set etdm ch */ + regmap_update_bits(afe->regmap, + etdm_data.ch_reg, + etdm_data.ch_mask << etdm_data.ch_shift, + (i2s_priv->ch_num - 1) << etdm_data.ch_shift); + + /* set etdm sync */ + regmap_update_bits(afe->regmap, + etdm_data.sync_reg, + etdm_data.sync_mask << etdm_data.sync_shift, + i2s_priv->sync << etdm_data.sync_shift); + } else { + regmap_update_bits(afe->regmap, + etdm_data.tdm_mode_reg, + etdm_data.tdm_mode_mask << etdm_data.tdm_mode_shift, + 0x0 << etdm_data.tdm_mode_shift); + } + + /* APLL */ + regmap_update_bits(afe->regmap, + etdm_data.relatch_domain_sel_reg, + etdm_data.relatch_domain_sel_mask << + etdm_data.relatch_domain_sel_shift, + ETDM_RELATCH_SEL_APLL << etdm_data.relatch_domain_sel_shift); + + regmap_update_bits(afe->regmap, + etdm_data.bit_length_reg, + etdm_data.bit_length_mask << etdm_data.bit_length_shift, + get_etdm_lrck_width(format) << etdm_data.bit_length_shift); + + regmap_update_bits(afe->regmap, + etdm_data.word_length_reg, + etdm_data.word_length_mask << etdm_data.word_length_shift, + get_etdm_wlen(format) << etdm_data.word_length_shift); + + /* ---etdm cowork --- */ + regmap_update_bits(afe->regmap, + etdm_data.cowork_reg, + etdm_data.cowork_mask << etdm_data.cowork_shift, + etdm_data.cowork_val << etdm_data.cowork_shift); + + /* i2s with pad top setting */ + if (is_etdm_in_pad_top(id) && etdm_data.pad_top_ck_en_reg != -1) { + regmap_update_bits(afe->regmap, + etdm_data.pad_top_ck_en_reg, + etdm_data.cowork_mask << etdm_data.pad_top_ck_en_shift, + 0x1 << etdm_data.pad_top_ck_en_shift); + + regmap_update_bits(afe->regmap, + etdm_data.master_latch_reg, + etdm_data.master_latch_mask << + etdm_data.master_latch_shift, + 0x0 << etdm_data.master_latch_shift); + } + break; + default: + dev_err(afe->dev, "id %d not support\n", id); + return -EINVAL; + } + + /* set share i2s */ + if (i2s_priv && i2s_priv->share_i2s_id >= 0) { + i2sin_priv = afe_priv->dai_priv[i2s_priv->share_i2s_id]; + i2sin_priv->format = i2s_priv->format; + ret = mtk_dai_i2s_config(afe, params, i2s_priv->share_i2s_id); + } + + return ret; +} + +static int mtk_dai_i2s_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); + + return mtk_dai_i2s_config(afe, params, dai->id); +} + +static int mtk_dai_i2s_set_sysclk(struct snd_soc_dai *dai, + int clk_id, unsigned int freq, int dir) +{ + struct mtk_base_afe *afe = dev_get_drvdata(dai->dev); + struct mt8196_afe_private *afe_priv = afe->platform_priv; + struct mtk_afe_i2s_priv *i2s_priv; + int apll; + int apll_rate; + + if (dai->id >= MT8196_DAI_NUM || dai->id < 0) + return -EINVAL; + i2s_priv = afe_priv->dai_priv[dai->id]; + + dev_dbg(afe->dev, "freq: %u\n", freq); + + if (!i2s_priv) + return -EINVAL; + + if (dir != SND_SOC_CLOCK_OUT) + return -EINVAL; + + apll = mt8196_get_apll_by_rate(afe, freq); + apll_rate = mt8196_get_apll_rate(afe, apll); + + if (freq > apll_rate) + return -EINVAL; + + if (apll_rate % freq != 0) + return -EINVAL; + + i2s_priv->mclk_rate = freq; + i2s_priv->mclk_apll = apll; + + if (i2s_priv->share_i2s_id > 0) { + struct mtk_afe_i2s_priv *share_i2s_priv; + + share_i2s_priv = afe_priv->dai_priv[i2s_priv->share_i2s_id]; + if (!share_i2s_priv) + return -EINVAL; + + share_i2s_priv->mclk_rate = i2s_priv->mclk_rate; + share_i2s_priv->mclk_apll = i2s_priv->mclk_apll; + } + return 0; +} + +static int mtk_dai_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) +{ + struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); + struct mt8196_afe_private *afe_priv = afe->platform_priv; + struct mtk_afe_i2s_priv *i2s_priv; + + if (dai->id >= MT8196_DAI_NUM || dai->id < 0) + return -EINVAL; + + i2s_priv = afe_priv->dai_priv[dai->id]; + + dev_dbg(afe->dev, "dai->id: %d, fmt: 0x%x\n", dai->id, fmt); + + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + i2s_priv->format = MTK_DAI_ETDM_FORMAT_I2S; + break; + case SND_SOC_DAIFMT_LEFT_J: + i2s_priv->format = MTK_DAI_ETDM_FORMAT_LJ; + break; + case SND_SOC_DAIFMT_RIGHT_J: + i2s_priv->format = MTK_DAI_ETDM_FORMAT_RJ; + break; + case SND_SOC_DAIFMT_DSP_A: + i2s_priv->format = MTK_DAI_ETDM_FORMAT_DSPA; + break; + case SND_SOC_DAIFMT_DSP_B: + i2s_priv->format = MTK_DAI_ETDM_FORMAT_DSPB; + break; + default: + return -EINVAL; + } + + dev_dbg(afe->dev, "dai->id: %d, i2s_priv->format: 0x%x\n", + dai->id, i2s_priv->format); + + return 0; +} + +static const struct snd_soc_dai_ops mtk_dai_i2s_ops = { + .hw_params = mtk_dai_i2s_hw_params, + .set_sysclk = mtk_dai_i2s_set_sysclk, + .set_fmt = mtk_dai_i2s_set_fmt, +}; + +/* dai driver */ +#define MTK_ETDM_RATES (SNDRV_PCM_RATE_8000_384000) +#define MTK_ETDM_FORMATS (SNDRV_PCM_FMTBIT_S8 |\ + SNDRV_PCM_FMTBIT_S16_LE |\ + SNDRV_PCM_FMTBIT_S24_LE |\ + SNDRV_PCM_FMTBIT_S32_LE) + +#define MTK_I2S_RATES (SNDRV_PCM_RATE_8000_48000 |\ + SNDRV_PCM_RATE_88200 |\ + SNDRV_PCM_RATE_96000 |\ + SNDRV_PCM_RATE_176400 |\ + SNDRV_PCM_RATE_192000) +#define MTK_I2S_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ + SNDRV_PCM_FMTBIT_S24_LE |\ + SNDRV_PCM_FMTBIT_S32_LE) + +static struct snd_soc_dai_driver mtk_dai_i2s_driver[] = { + { + .name = "I2SIN0", + .id = MT8196_DAI_I2S_IN0, + .capture = { + .stream_name = "I2SIN0", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_ETDM_RATES, + .formats = MTK_ETDM_FORMATS, + }, + .ops = &mtk_dai_i2s_ops, + }, + { + .name = "I2SIN1", + .id = MT8196_DAI_I2S_IN1, + .capture = { + .stream_name = "I2SIN1", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_ETDM_RATES, + .formats = MTK_ETDM_FORMATS, + }, + .ops = &mtk_dai_i2s_ops, + }, + { + .name = "I2SIN2", + .id = MT8196_DAI_I2S_IN2, + .capture = { + .stream_name = "I2SIN2", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_ETDM_RATES, + .formats = MTK_ETDM_FORMATS, + }, + .ops = &mtk_dai_i2s_ops, + }, + { + .name = "I2SIN3", + .id = MT8196_DAI_I2S_IN3, + .capture = { + .stream_name = "I2SIN3", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_ETDM_RATES, + .formats = MTK_ETDM_FORMATS, + }, + .ops = &mtk_dai_i2s_ops, + }, + { + .name = "I2SIN4", + .id = MT8196_DAI_I2S_IN4, + .capture = { + .stream_name = "I2SIN4", + .channels_min = 1, + .channels_max = 32, + .rates = MTK_ETDM_RATES, + .formats = MTK_ETDM_FORMATS, + }, + .ops = &mtk_dai_i2s_ops, + }, + { + .name = "I2SIN6", + .id = MT8196_DAI_I2S_IN6, + .capture = { + .stream_name = "I2SIN6", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_ETDM_RATES, + .formats = MTK_ETDM_FORMATS, + }, + .ops = &mtk_dai_i2s_ops, + }, + { + .name = "I2SOUT0", + .id = MT8196_DAI_I2S_OUT0, + .playback = { + .stream_name = "I2SOUT0", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_ETDM_RATES, + .formats = MTK_ETDM_FORMATS, + }, + .ops = &mtk_dai_i2s_ops, + }, + { + .name = "I2SOUT1", + .id = MT8196_DAI_I2S_OUT1, + .playback = { + .stream_name = "I2SOUT1", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_ETDM_RATES, + .formats = MTK_ETDM_FORMATS, + }, + .ops = &mtk_dai_i2s_ops, + }, + { + .name = "I2SOUT2", + .id = MT8196_DAI_I2S_OUT2, + .playback = { + .stream_name = "I2SOUT2", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_ETDM_RATES, + .formats = MTK_ETDM_FORMATS, + }, + .ops = &mtk_dai_i2s_ops, + }, + { + .name = "I2SOUT3", + .id = MT8196_DAI_I2S_OUT3, + .playback = { + .stream_name = "I2SOUT3", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_ETDM_RATES, + .formats = MTK_ETDM_FORMATS, + }, + .ops = &mtk_dai_i2s_ops, + }, + { + .name = "I2SOUT4", + .id = MT8196_DAI_I2S_OUT4, + .playback = { + .stream_name = "I2SOUT4", + .channels_min = 1, + .channels_max = 8, + .rates = MTK_ETDM_RATES, + .formats = MTK_ETDM_FORMATS, + }, + .ops = &mtk_dai_i2s_ops, + }, + { + .name = "I2SOUT6", + .id = MT8196_DAI_I2S_OUT6, + .playback = { + .stream_name = "I2SOUT6", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_ETDM_RATES, + .formats = MTK_ETDM_FORMATS, + }, + .ops = &mtk_dai_i2s_ops, + }, + { + .name = "FMI2S_MASTER", + .id = MT8196_DAI_FM_I2S_MASTER, + .capture = { + .stream_name = "FMI2S_MASTER", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_I2S_RATES, + .formats = MTK_I2S_FORMATS, + }, + .ops = &mtk_dai_i2s_ops, + }, +}; + +static const struct mtk_afe_i2s_priv mt8196_i2s_priv[DAI_I2S_NUM] = { + [DAI_I2SIN0] = { + .id = MT8196_DAI_I2S_IN0, + .mclk_id = MT8196_I2SIN0_MCK, + .share_property_name = "i2sin0-share", + .share_i2s_id = -1, + }, + [DAI_I2SIN1] = { + .id = MT8196_DAI_I2S_IN1, + .mclk_id = MT8196_I2SIN1_MCK, + .share_property_name = "i2sin1-share", + .share_i2s_id = -1, + }, + [DAI_I2SIN2] = { + .id = MT8196_DAI_I2S_IN2, + .mclk_id = MT8196_I2SIN0_MCK, + .share_property_name = "i2sin2-share", + .share_i2s_id = -1, + }, + [DAI_I2SIN3] = { + .id = MT8196_DAI_I2S_IN3, + .mclk_id = MT8196_I2SIN0_MCK, + .share_property_name = "i2sin3-share", + .share_i2s_id = -1, + }, + [DAI_I2SIN4] = { + .id = MT8196_DAI_I2S_IN4, + .mclk_id = MT8196_I2SIN0_MCK, + .share_property_name = "i2sin4-share", + .share_i2s_id = -1, + }, + [DAI_I2SIN6] = { + .id = MT8196_DAI_I2S_IN6, + .mclk_id = MT8196_I2SIN0_MCK, + .share_property_name = "i2sout6-share", + .share_i2s_id = -1, + }, + [DAI_I2SOUT0] = { + .id = MT8196_DAI_I2S_OUT0, + .mclk_id = MT8196_I2SIN0_MCK, + .share_property_name = "i2sout0-share", + .share_i2s_id = MT8196_DAI_I2S_IN0, + }, + [DAI_I2SOUT1] = { + .id = MT8196_DAI_I2S_OUT1, + .mclk_id = MT8196_I2SIN1_MCK, + .share_property_name = "i2sout1-share", + .share_i2s_id = MT8196_DAI_I2S_IN1, + }, + [DAI_I2SOUT2] = { + .id = MT8196_DAI_I2S_OUT2, + .mclk_id = MT8196_I2SIN0_MCK, + .share_property_name = "i2sout2-share", + .share_i2s_id = MT8196_DAI_I2S_IN2, + }, + [DAI_I2SOUT3] = { + .id = MT8196_DAI_I2S_OUT3, + .mclk_id = MT8196_I2SIN0_MCK, + .share_property_name = "i2sout3-share", + .share_i2s_id = MT8196_DAI_I2S_IN3, + }, + [DAI_I2SOUT4] = { + .id = MT8196_DAI_I2S_OUT4, + .mclk_id = MT8196_I2SIN0_MCK, + .share_property_name = "i2sout4-share", + .share_i2s_id = MT8196_DAI_I2S_IN4, + }, + [DAI_I2SOUT6] = { + .id = MT8196_DAI_I2S_OUT6, + .mclk_id = MT8196_I2SIN0_MCK, + .share_property_name = "i2sout6-share", + .share_i2s_id = MT8196_DAI_I2S_IN6, + }, + [DAI_FMI2S_MASTER] = { + .id = MT8196_DAI_FM_I2S_MASTER, + .mclk_id = MT8196_FMI2S_MCK, + .share_property_name = "fmi2s-share", + .share_i2s_id = -1, + }, +}; + +static int etdm_parse_dt(struct mtk_base_afe *afe) +{ + int ret; + struct mt8196_afe_private *afe_priv = afe->platform_priv; + struct mtk_afe_i2s_priv *i2sin4_priv = afe_priv->dai_priv[MT8196_DAI_I2S_IN4]; + struct mtk_afe_i2s_priv *i2sout4_priv = afe_priv->dai_priv[MT8196_DAI_I2S_OUT4]; + unsigned int ch_num_in; + unsigned int ch_num_out; + unsigned int sync_in; + unsigned int sync_out; + unsigned int ip_mode; + + /* get etdm ch */ + ret = of_property_read_u32(afe->dev->of_node, "mediatek,etdm4-out-ch", &ch_num_out); + if (ret) { + dev_warn(afe->dev, "failed to read mediatek,etdm4-out-ch, default ch:2\n"); + i2sout4_priv->ch_num = 2; + } + i2sout4_priv->ch_num = ch_num_out; + + ret = of_property_read_u32(afe->dev->of_node, "mediatek,etdm4-in-ch", &ch_num_in); + if (ret) { + dev_warn(afe->dev, "failed to read mediatek,etdm4-in-ch, default ch:2\n"); + i2sin4_priv->ch_num = 2; + } + i2sin4_priv->ch_num = ch_num_in; + + /* get etdm sync */ + ret = of_property_read_u32(afe->dev->of_node, "mediatek,etdm4-out-sync", &sync_out); + if (ret) { + dev_warn(afe->dev, "failed to read mediatek,etdm4-out-sync, default sync:0\n"); + i2sout4_priv->sync = 0; + } + i2sout4_priv->sync = sync_out; + + ret = of_property_read_u32(afe->dev->of_node, "mediatek,etdm4-in-sync", &sync_in); + if (ret) { + dev_warn(afe->dev, "failed to read mediatek,etdm4-in-sync, default sync:0\n"); + i2sin4_priv->sync = 0; + } + i2sin4_priv->sync = sync_in; + + /* get etdm ip mode */ + ret = of_property_read_u32(afe->dev->of_node, "mediatek,etdm4-ip-mode", &ip_mode); + if (ret) { + dev_warn(afe->dev, "failed to read mediatek,etdm4-ip-mode, default ip-mode:0\n"); + i2sin4_priv->ip_mode = 0; + } + i2sin4_priv->ip_mode = ip_mode; + + return 0; +} + +static int mt8196_dai_i2s_get_share(struct mtk_base_afe *afe) +{ + struct mt8196_afe_private *afe_priv = afe->platform_priv; + const struct device_node *of_node = afe->dev->of_node; + const char *of_str; + const char *property_name; + struct mtk_afe_i2s_priv *i2s_priv; + int i; + + for (i = 0; i < DAI_I2S_NUM; i++) { + i2s_priv = afe_priv->dai_priv[mt8196_i2s_priv[i].id]; + property_name = mt8196_i2s_priv[i].share_property_name; + if (of_property_read_string(of_node, property_name, &of_str)) + continue; + i2s_priv->share_i2s_id = get_i2s_id_by_name(afe, of_str); + } + return 0; +} + +static int init_i2s_priv_data(struct mtk_base_afe *afe) +{ + struct mt8196_afe_private *afe_priv = afe->platform_priv; + struct mtk_afe_i2s_priv *i2s_priv; + int size; + int id; + int i; + + for (i = 0; i < DAI_I2S_NUM; i++) { + if (&mt8196_i2s_priv[i]) { + id = mt8196_i2s_priv[i].id; + size = sizeof(struct mtk_afe_i2s_priv); + + if (id >= MT8196_DAI_NUM || id < 0) + return -EINVAL; + + i2s_priv = devm_kzalloc(afe->dev, size, GFP_KERNEL); + if (!i2s_priv) + return -ENOMEM; + + memcpy(i2s_priv, &mt8196_i2s_priv[i], size); + + afe_priv->dai_priv[id] = i2s_priv; + } + } + + return 0; +} + +int mt8196_dai_i2s_register(struct mtk_base_afe *afe) +{ + struct mtk_base_afe_dai *dai; + int ret; + + dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL); + if (!dai) + return -ENOMEM; + + list_add(&dai->list, &afe->sub_dais); + + dai->dai_drivers = mtk_dai_i2s_driver; + dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_i2s_driver); + + dai->controls = mtk_dai_i2s_controls; + dai->num_controls = ARRAY_SIZE(mtk_dai_i2s_controls); + dai->dapm_widgets = mtk_dai_i2s_widgets; + dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_i2s_widgets); + dai->dapm_routes = mtk_dai_i2s_routes; + dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_i2s_routes); + + /* set all dai i2s private data */ + ret = init_i2s_priv_data(afe); + if (ret) + return ret; + + /* parse share i2s */ + ret = mt8196_dai_i2s_get_share(afe); + if (ret) + return ret; + + /* for customer to change ch_num & sync & ipmode from dts */ + ret = etdm_parse_dt(afe); + if (ret) + return ret; + + return 0; +} From patchwork Mon Apr 7 12:06:31 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Darren.Ye" X-Patchwork-Id: 878791 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9C12624C081; Mon, 7 Apr 2025 12:11:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none 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(10.17.3.154) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Mon, 7 Apr 2025 20:11:04 +0800 From: Darren.Ye To: Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Jaroslav Kysela , Takashi Iwai , Linus Walleij , Bartosz Golaszewski CC: , , , , , , Darren Ye Subject: [PATCH v2 07/11] ASoC: mediatek: mt8196: support TDM in platform driver Date: Mon, 7 Apr 2025 20:06:31 +0800 Message-ID: <20250407120708.26495-8-darren.ye@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250407120708.26495-1-darren.ye@mediatek.com> References: <20250407120708.26495-1-darren.ye@mediatek.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N From: Darren Ye Add mt8196 TDM DAI driver support. Signed-off-by: Darren Ye --- sound/soc/mediatek/mt8196/mt8196-dai-tdm.c | 825 +++++++++++++++++++++ 1 file changed, 825 insertions(+) create mode 100644 sound/soc/mediatek/mt8196/mt8196-dai-tdm.c diff --git a/sound/soc/mediatek/mt8196/mt8196-dai-tdm.c b/sound/soc/mediatek/mt8196/mt8196-dai-tdm.c new file mode 100644 index 000000000000..b1ff8480907f --- /dev/null +++ b/sound/soc/mediatek/mt8196/mt8196-dai-tdm.c @@ -0,0 +1,825 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MediaTek ALSA SoC Audio DAI TDM Control + * + * Copyright (c) 2024 MediaTek Inc. + * Author: Darren Ye + */ + +#include +#include +#include "mt8196-afe-clk.h" +#include "mt8196-afe-common.h" +#include "mt8196-interconnection.h" + +struct mtk_afe_tdm_priv { + int bck_id; + int bck_rate; + + int mclk_id; + int mclk_multiple; /* according to sample rate */ + int mclk_rate; + int mclk_apll; +}; + +enum { + TDM_WLEN_16_BIT = 1, + TDM_WLEN_32_BIT = 2, +}; + +enum { + TDM_CHANNEL_BCK_16 = 0, + TDM_CHANNEL_BCK_24 = 1, + TDM_CHANNEL_BCK_32 = 2, +}; + +enum { + TDM_CHANNEL_NUM_2 = 0, + TDM_CHANNEL_NUM_4 = 1, + TDM_CHANNEL_NUM_8 = 2, +}; + +enum { + TDM_CH_START_O30_O31 = 0, + TDM_CH_START_O32_O33, + TDM_CH_START_O34_O35, + TDM_CH_START_O36_O37, + TDM_CH_ZERO, +}; + +enum { + DPTX_CHANNEL_2, + DPTX_CHANNEL_8, +}; + +enum { + DPTX_WLEN_24_BIT, + DPTX_WLEN_16_BIT, +}; + +enum { + DPTX_CH_EN_MASK_2CH = 0x3, + DPTX_CH_EN_MASK_4CH = 0xf, + DPTX_CH_EN_MASK_6CH = 0x3f, + DPTX_CH_EN_MASK_8CH = 0xff, +}; + +static unsigned int get_tdm_wlen(snd_pcm_format_t format) +{ + return snd_pcm_format_physical_width(format) <= 16 ? + TDM_WLEN_16_BIT : TDM_WLEN_32_BIT; +} + +static unsigned int get_tdm_channel_bck(snd_pcm_format_t format) +{ + return snd_pcm_format_physical_width(format) <= 16 ? + TDM_CHANNEL_BCK_16 : TDM_CHANNEL_BCK_32; +} + +static unsigned int get_tdm_lrck_width(snd_pcm_format_t format) +{ + return snd_pcm_format_physical_width(format) - 1; +} + +static unsigned int get_tdm_ch(unsigned int ch) +{ + switch (ch) { + case 1: + case 2: + return TDM_CHANNEL_NUM_2; + case 3: + case 4: + return TDM_CHANNEL_NUM_4; + case 5: + case 6: + case 7: + case 8: + default: + return TDM_CHANNEL_NUM_8; + } +} + +static unsigned int get_dptx_ch_enable_mask(unsigned int ch) +{ + switch (ch) { + case 1: + case 2: + return DPTX_CH_EN_MASK_2CH; + case 3: + case 4: + return DPTX_CH_EN_MASK_4CH; + case 5: + case 6: + return DPTX_CH_EN_MASK_6CH; + case 7: + case 8: + return DPTX_CH_EN_MASK_8CH; + default: + pr_info("invalid channel num, default use 2ch\n"); + return DPTX_CH_EN_MASK_2CH; + } +} + +static unsigned int get_dptx_ch(unsigned int ch) +{ + if (ch == 2) + return DPTX_CHANNEL_2; + else + return DPTX_CHANNEL_8; +} + +static unsigned int get_dptx_wlen(snd_pcm_format_t format) +{ + return snd_pcm_format_physical_width(format) <= 16 ? + DPTX_WLEN_16_BIT : DPTX_WLEN_24_BIT; +} + +/* interconnection */ +enum { + HDMI_CONN_CH0 = 0, + HDMI_CONN_CH1, + HDMI_CONN_CH2, + HDMI_CONN_CH3, + HDMI_CONN_CH4, + HDMI_CONN_CH5, + HDMI_CONN_CH6, + HDMI_CONN_CH7, +}; + +static const char *const hdmi_conn_mux_map[] = { + "CH0", "CH1", "CH2", "CH3", + "CH4", "CH5", "CH6", "CH7", +}; + +static int hdmi_conn_mux_map_value[] = { + HDMI_CONN_CH0, + HDMI_CONN_CH1, + HDMI_CONN_CH2, + HDMI_CONN_CH3, + HDMI_CONN_CH4, + HDMI_CONN_CH5, + HDMI_CONN_CH6, + HDMI_CONN_CH7, +}; + +static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch0_mux_map_enum, + AFE_HDMI_CONN0, + HDMI_O_0_SFT, + HDMI_O_0_MASK, + hdmi_conn_mux_map, + hdmi_conn_mux_map_value); + +static const struct snd_kcontrol_new hdmi_ch0_mux_control = + SOC_DAPM_ENUM("HDMI_CH0_MUX", hdmi_ch0_mux_map_enum); + +static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch1_mux_map_enum, + AFE_HDMI_CONN0, + HDMI_O_1_SFT, + HDMI_O_1_MASK, + hdmi_conn_mux_map, + hdmi_conn_mux_map_value); + +static const struct snd_kcontrol_new hdmi_ch1_mux_control = + SOC_DAPM_ENUM("HDMI_CH1_MUX", hdmi_ch1_mux_map_enum); + +static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch2_mux_map_enum, + AFE_HDMI_CONN0, + HDMI_O_2_SFT, + HDMI_O_2_MASK, + hdmi_conn_mux_map, + hdmi_conn_mux_map_value); + +static const struct snd_kcontrol_new hdmi_ch2_mux_control = + SOC_DAPM_ENUM("HDMI_CH2_MUX", hdmi_ch2_mux_map_enum); + +static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch3_mux_map_enum, + AFE_HDMI_CONN0, + HDMI_O_3_SFT, + HDMI_O_3_MASK, + hdmi_conn_mux_map, + hdmi_conn_mux_map_value); + +static const struct snd_kcontrol_new hdmi_ch3_mux_control = + SOC_DAPM_ENUM("HDMI_CH3_MUX", hdmi_ch3_mux_map_enum); + +static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch4_mux_map_enum, + AFE_HDMI_CONN0, + HDMI_O_4_SFT, + HDMI_O_4_MASK, + hdmi_conn_mux_map, + hdmi_conn_mux_map_value); + +static const struct snd_kcontrol_new hdmi_ch4_mux_control = + SOC_DAPM_ENUM("HDMI_CH4_MUX", hdmi_ch4_mux_map_enum); + +static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch5_mux_map_enum, + AFE_HDMI_CONN0, + HDMI_O_5_SFT, + HDMI_O_5_MASK, + hdmi_conn_mux_map, + hdmi_conn_mux_map_value); + +static const struct snd_kcontrol_new hdmi_ch5_mux_control = + SOC_DAPM_ENUM("HDMI_CH5_MUX", hdmi_ch5_mux_map_enum); + +static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch6_mux_map_enum, + AFE_HDMI_CONN0, + HDMI_O_6_SFT, + HDMI_O_6_MASK, + hdmi_conn_mux_map, + hdmi_conn_mux_map_value); + +static const struct snd_kcontrol_new hdmi_ch6_mux_control = + SOC_DAPM_ENUM("HDMI_CH6_MUX", hdmi_ch6_mux_map_enum); + +static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch7_mux_map_enum, + AFE_HDMI_CONN0, + HDMI_O_7_SFT, + HDMI_O_7_MASK, + hdmi_conn_mux_map, + hdmi_conn_mux_map_value); + +static const struct snd_kcontrol_new hdmi_ch7_mux_control = + SOC_DAPM_ENUM("HDMI_CH7_MUX", hdmi_ch7_mux_map_enum); + +static const char *const tdm_out_mux_map[] = { + "Disconnect", "Connect", +}; + +static int tdm_out_mux_map_value[] = { + 0, 1, +}; + +static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(hdmi_out_mux_map_enum, + SND_SOC_NOPM, + 0, + 1, + tdm_out_mux_map, + tdm_out_mux_map_value); +static const struct snd_kcontrol_new hdmi_out_mux_control = + SOC_DAPM_ENUM("HDMI_OUT_MUX", hdmi_out_mux_map_enum); + +static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(dptx_out_mux_map_enum, + SND_SOC_NOPM, + 0, + 1, + tdm_out_mux_map, + tdm_out_mux_map_value); +static const struct snd_kcontrol_new dptx_out_mux_control = + SOC_DAPM_ENUM("DPTX_OUT_MUX", dptx_out_mux_map_enum); + +static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(dptx_virtual_out_mux_map_enum, + SND_SOC_NOPM, + 0, + 1, + tdm_out_mux_map, + tdm_out_mux_map_value); + +static const struct snd_kcontrol_new dptx_virtual_out_mux_control = + SOC_DAPM_ENUM("DPTX_VIRTUAL_OUT_MUX", dptx_virtual_out_mux_map_enum); + +enum { + SUPPLY_SEQ_APLL, + SUPPLY_SEQ_TDM_MCK_EN, + SUPPLY_SEQ_TDM_BCK_EN, + SUPPLY_SEQ_TDM_DPTX_MCK_EN, + SUPPLY_SEQ_TDM_DPTX_BCK_EN, +}; + +static int get_tdm_id_by_name(const char *name) +{ + if (strstr(name, "DPTX")) + return MT8196_DAI_TDM_DPTX; + else + return MT8196_DAI_TDM; +} + +static int mtk_tdm_bck_en_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); + struct mt8196_afe_private *afe_priv = afe->platform_priv; + int dai_id = get_tdm_id_by_name(w->name); + struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[dai_id]; + + dev_dbg(cmpnt->dev, "name %s, event 0x%x, dai_id %d\n", + w->name, event, dai_id); + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + mt8196_mck_enable(afe, tdm_priv->bck_id, tdm_priv->bck_rate); + break; + case SND_SOC_DAPM_POST_PMD: + mt8196_mck_disable(afe, tdm_priv->bck_id); + break; + default: + break; + } + + return 0; +} + +static int mtk_tdm_mck_en_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); + struct mt8196_afe_private *afe_priv = afe->platform_priv; + int dai_id = get_tdm_id_by_name(w->name); + struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[dai_id]; + + dev_dbg(cmpnt->dev, "name %s, event 0x%x, dai_id %d\n", + w->name, event, dai_id); + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + mt8196_mck_enable(afe, tdm_priv->mclk_id, tdm_priv->mclk_rate); + break; + case SND_SOC_DAPM_POST_PMD: + tdm_priv->mclk_rate = 0; + mt8196_mck_disable(afe, tdm_priv->mclk_id); + break; + default: + break; + } + + return 0; +} + +static const struct snd_soc_dapm_widget mtk_dai_tdm_widgets[] = { + SND_SOC_DAPM_MUX("HDMI_CH0_MUX", SND_SOC_NOPM, 0, 0, + &hdmi_ch0_mux_control), + SND_SOC_DAPM_MUX("HDMI_CH1_MUX", SND_SOC_NOPM, 0, 0, + &hdmi_ch1_mux_control), + SND_SOC_DAPM_MUX("HDMI_CH2_MUX", SND_SOC_NOPM, 0, 0, + &hdmi_ch2_mux_control), + SND_SOC_DAPM_MUX("HDMI_CH3_MUX", SND_SOC_NOPM, 0, 0, + &hdmi_ch3_mux_control), + SND_SOC_DAPM_MUX("HDMI_CH4_MUX", SND_SOC_NOPM, 0, 0, + &hdmi_ch4_mux_control), + SND_SOC_DAPM_MUX("HDMI_CH5_MUX", SND_SOC_NOPM, 0, 0, + &hdmi_ch5_mux_control), + SND_SOC_DAPM_MUX("HDMI_CH6_MUX", SND_SOC_NOPM, 0, 0, + &hdmi_ch6_mux_control), + SND_SOC_DAPM_MUX("HDMI_CH7_MUX", SND_SOC_NOPM, 0, 0, + &hdmi_ch7_mux_control), + SND_SOC_DAPM_MUX("HDMI_OUT_MUX", SND_SOC_NOPM, 0, 0, + &hdmi_out_mux_control), + SND_SOC_DAPM_MUX("DPTX_OUT_MUX", SND_SOC_NOPM, 0, 0, + &dptx_out_mux_control), + + SND_SOC_DAPM_SUPPLY_S("TDM_BCK", SUPPLY_SEQ_TDM_BCK_EN, + SND_SOC_NOPM, 0, 0, + mtk_tdm_bck_en_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_SUPPLY_S("TDM_MCK", SUPPLY_SEQ_TDM_MCK_EN, + SND_SOC_NOPM, 0, 0, + mtk_tdm_mck_en_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_SUPPLY_S("TDM_DPTX_BCK", SUPPLY_SEQ_TDM_DPTX_BCK_EN, + SND_SOC_NOPM, 0, 0, + mtk_tdm_bck_en_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_SUPPLY_S("TDM_DPTX_MCK", SUPPLY_SEQ_TDM_DPTX_MCK_EN, + SND_SOC_NOPM, 0, 0, + mtk_tdm_mck_en_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_MUX("DPTX_VIRTUAL_OUT_MUX", + SND_SOC_NOPM, 0, 0, &dptx_virtual_out_mux_control), + SND_SOC_DAPM_OUTPUT("DPTX_VIRTUAL_OUT"), +}; + +static int mtk_afe_tdm_apll_connect(struct snd_soc_dapm_widget *source, + struct snd_soc_dapm_widget *sink) +{ + struct snd_soc_dapm_widget *w = sink; + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); + struct mt8196_afe_private *afe_priv = afe->platform_priv; + int dai_id = get_tdm_id_by_name(w->name); + struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[dai_id]; + int cur_apll; + + /* which apll */ + cur_apll = mt8196_get_apll_by_name(afe, source->name); + + return (tdm_priv->mclk_apll == cur_apll) ? 1 : 0; +} + +static const struct snd_soc_dapm_route mtk_dai_tdm_routes[] = { + {"HDMI_CH0_MUX", "CH0", "HDMI"}, + {"HDMI_CH0_MUX", "CH1", "HDMI"}, + {"HDMI_CH0_MUX", "CH2", "HDMI"}, + {"HDMI_CH0_MUX", "CH3", "HDMI"}, + {"HDMI_CH0_MUX", "CH4", "HDMI"}, + {"HDMI_CH0_MUX", "CH5", "HDMI"}, + {"HDMI_CH0_MUX", "CH6", "HDMI"}, + {"HDMI_CH0_MUX", "CH7", "HDMI"}, + + {"HDMI_CH1_MUX", "CH0", "HDMI"}, + {"HDMI_CH1_MUX", "CH1", "HDMI"}, + {"HDMI_CH1_MUX", "CH2", "HDMI"}, + {"HDMI_CH1_MUX", "CH3", "HDMI"}, + {"HDMI_CH1_MUX", "CH4", "HDMI"}, + {"HDMI_CH1_MUX", "CH5", "HDMI"}, + {"HDMI_CH1_MUX", "CH6", "HDMI"}, + {"HDMI_CH1_MUX", "CH7", "HDMI"}, + + {"HDMI_CH2_MUX", "CH0", "HDMI"}, + {"HDMI_CH2_MUX", "CH1", "HDMI"}, + {"HDMI_CH2_MUX", "CH2", "HDMI"}, + {"HDMI_CH2_MUX", "CH3", "HDMI"}, + {"HDMI_CH2_MUX", "CH4", "HDMI"}, + {"HDMI_CH2_MUX", "CH5", "HDMI"}, + {"HDMI_CH2_MUX", "CH6", "HDMI"}, + {"HDMI_CH2_MUX", "CH7", "HDMI"}, + + {"HDMI_CH3_MUX", "CH0", "HDMI"}, + {"HDMI_CH3_MUX", "CH1", "HDMI"}, + {"HDMI_CH3_MUX", "CH2", "HDMI"}, + {"HDMI_CH3_MUX", "CH3", "HDMI"}, + {"HDMI_CH3_MUX", "CH4", "HDMI"}, + {"HDMI_CH3_MUX", "CH5", "HDMI"}, + {"HDMI_CH3_MUX", "CH6", "HDMI"}, + {"HDMI_CH3_MUX", "CH7", "HDMI"}, + + {"HDMI_CH4_MUX", "CH0", "HDMI"}, + {"HDMI_CH4_MUX", "CH1", "HDMI"}, + {"HDMI_CH4_MUX", "CH2", "HDMI"}, + {"HDMI_CH4_MUX", "CH3", "HDMI"}, + {"HDMI_CH4_MUX", "CH4", "HDMI"}, + {"HDMI_CH4_MUX", "CH5", "HDMI"}, + {"HDMI_CH4_MUX", "CH6", "HDMI"}, + {"HDMI_CH4_MUX", "CH7", "HDMI"}, + + {"HDMI_CH5_MUX", "CH0", "HDMI"}, + {"HDMI_CH5_MUX", "CH1", "HDMI"}, + {"HDMI_CH5_MUX", "CH2", "HDMI"}, + {"HDMI_CH5_MUX", "CH3", "HDMI"}, + {"HDMI_CH5_MUX", "CH4", "HDMI"}, + {"HDMI_CH5_MUX", "CH5", "HDMI"}, + {"HDMI_CH5_MUX", "CH6", "HDMI"}, + {"HDMI_CH5_MUX", "CH7", "HDMI"}, + + {"HDMI_CH6_MUX", "CH0", "HDMI"}, + {"HDMI_CH6_MUX", "CH1", "HDMI"}, + {"HDMI_CH6_MUX", "CH2", "HDMI"}, + {"HDMI_CH6_MUX", "CH3", "HDMI"}, + {"HDMI_CH6_MUX", "CH4", "HDMI"}, + {"HDMI_CH6_MUX", "CH5", "HDMI"}, + {"HDMI_CH6_MUX", "CH6", "HDMI"}, + {"HDMI_CH6_MUX", "CH7", "HDMI"}, + + {"HDMI_CH7_MUX", "CH0", "HDMI"}, + {"HDMI_CH7_MUX", "CH1", "HDMI"}, + {"HDMI_CH7_MUX", "CH2", "HDMI"}, + {"HDMI_CH7_MUX", "CH3", "HDMI"}, + {"HDMI_CH7_MUX", "CH4", "HDMI"}, + {"HDMI_CH7_MUX", "CH5", "HDMI"}, + {"HDMI_CH7_MUX", "CH6", "HDMI"}, + {"HDMI_CH7_MUX", "CH7", "HDMI"}, + + {"HDMI_OUT_MUX", "Connect", "HDMI_CH0_MUX"}, + {"HDMI_OUT_MUX", "Connect", "HDMI_CH1_MUX"}, + {"HDMI_OUT_MUX", "Connect", "HDMI_CH2_MUX"}, + {"HDMI_OUT_MUX", "Connect", "HDMI_CH3_MUX"}, + {"HDMI_OUT_MUX", "Connect", "HDMI_CH4_MUX"}, + {"HDMI_OUT_MUX", "Connect", "HDMI_CH5_MUX"}, + {"HDMI_OUT_MUX", "Connect", "HDMI_CH6_MUX"}, + {"HDMI_OUT_MUX", "Connect", "HDMI_CH7_MUX"}, + + {"DPTX_OUT_MUX", "Connect", "HDMI_CH0_MUX"}, + {"DPTX_OUT_MUX", "Connect", "HDMI_CH1_MUX"}, + {"DPTX_OUT_MUX", "Connect", "HDMI_CH2_MUX"}, + {"DPTX_OUT_MUX", "Connect", "HDMI_CH3_MUX"}, + {"DPTX_OUT_MUX", "Connect", "HDMI_CH4_MUX"}, + {"DPTX_OUT_MUX", "Connect", "HDMI_CH5_MUX"}, + {"DPTX_OUT_MUX", "Connect", "HDMI_CH6_MUX"}, + {"DPTX_OUT_MUX", "Connect", "HDMI_CH7_MUX"}, + + {"TDM", NULL, "HDMI_OUT_MUX"}, + {"TDM", NULL, "TDM_BCK"}, + + {"TDM_DPTX", NULL, "DPTX_OUT_MUX"}, + {"TDM_DPTX", NULL, "TDM_DPTX_BCK"}, + + {"TDM_BCK", NULL, "TDM_MCK"}, + {"TDM_DPTX_BCK", NULL, "TDM_DPTX_MCK"}, + {"TDM_MCK", NULL, APLL1_W_NAME, mtk_afe_tdm_apll_connect}, + {"TDM_MCK", NULL, APLL2_W_NAME, mtk_afe_tdm_apll_connect}, + {"TDM_DPTX_MCK", NULL, APLL1_W_NAME, mtk_afe_tdm_apll_connect}, + {"TDM_DPTX_MCK", NULL, APLL2_W_NAME, mtk_afe_tdm_apll_connect}, + + {"DPTX_VIRTUAL_OUT_MUX", "Connect", "TDM_DPTX"}, + {"DPTX_VIRTUAL_OUT", NULL, "DPTX_VIRTUAL_OUT_MUX"}, +}; + +/* dai ops */ +static int mtk_dai_tdm_cal_mclk(struct mtk_base_afe *afe, + struct mtk_afe_tdm_priv *tdm_priv, + int freq) +{ + int apll; + int apll_rate; + + apll = mt8196_get_apll_by_rate(afe, freq); + apll_rate = mt8196_get_apll_rate(afe, apll); + + if (freq > apll_rate) + return -EINVAL; + + if (apll_rate % freq != 0) + return -EINVAL; + + tdm_priv->mclk_rate = freq; + tdm_priv->mclk_apll = apll; + + return 0; +} + +static int mtk_dai_tdm_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); + struct mt8196_afe_private *afe_priv = afe->platform_priv; + int tdm_id = dai->id; + struct mtk_afe_tdm_priv *tdm_priv; + unsigned int rate = params_rate(params); + unsigned int channels = params_channels(params); + snd_pcm_format_t format = params_format(params); + unsigned int tdm_con = 0; + + if (tdm_id >= MT8196_DAI_NUM || tdm_id < 0) + return -EINVAL; + + tdm_priv = afe_priv->dai_priv[tdm_id]; + + /* calculate mclk_rate, if not set explicitly */ + if (!tdm_priv->mclk_rate) { + tdm_priv->mclk_rate = rate * tdm_priv->mclk_multiple; + mtk_dai_tdm_cal_mclk(afe, + tdm_priv, + tdm_priv->mclk_rate); + } + + /* calculate bck */ + tdm_priv->bck_rate = rate * + channels * + snd_pcm_format_physical_width(format); + + if (tdm_priv->bck_rate > tdm_priv->mclk_rate) + return -EINVAL; + + if (tdm_priv->mclk_rate % tdm_priv->bck_rate != 0) + return -EINVAL; + + dev_info(afe->dev, "id %d, rate %d, channels %d, format %d, mclk_rate %d, bck_rate %d\n", + tdm_id, rate, channels, format, + tdm_priv->mclk_rate, tdm_priv->bck_rate); + + /* set tdm */ + tdm_con = 0 << BCK_INVERSE_SFT; + tdm_con |= 0 << LRCK_INVERSE_SFT; + tdm_con |= 0 << DELAY_DATA_SFT; + tdm_con |= 1 << LEFT_ALIGN_SFT; + tdm_con |= get_tdm_wlen(format) << WLEN_SFT; + tdm_con |= get_tdm_ch(channels) << CHANNEL_NUM_SFT; + tdm_con |= get_tdm_channel_bck(format) << CHANNEL_BCK_CYCLES_SFT; + tdm_con |= get_tdm_lrck_width(format) << LRCK_TDM_WIDTH_SFT; + regmap_write(afe->regmap, AFE_TDM_CON1, tdm_con); + + /* set dptx */ + if (tdm_id == MT8196_DAI_TDM_DPTX) { + regmap_update_bits(afe->regmap, AFE_DPTX_CON, + DPTX_CHANNEL_ENABLE_MASK_SFT, + get_dptx_ch_enable_mask(channels) << + DPTX_CHANNEL_ENABLE_SFT); + regmap_update_bits(afe->regmap, AFE_DPTX_CON, + DPTX_CHANNEL_NUMBER_MASK_SFT, + get_dptx_ch(channels) << + DPTX_CHANNEL_NUMBER_SFT); + regmap_update_bits(afe->regmap, AFE_DPTX_CON, + DPTX_16BIT_MASK_SFT, + get_dptx_wlen(format) << DPTX_16BIT_SFT); + } + switch (channels) { + case 1: + case 2: + tdm_con = TDM_CH_START_O30_O31 << ST_CH_PAIR_SOUT0_SFT; + tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT1_SFT; + tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT2_SFT; + tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT3_SFT; + break; + case 3: + case 4: + tdm_con = TDM_CH_START_O30_O31 << ST_CH_PAIR_SOUT0_SFT; + tdm_con |= TDM_CH_START_O32_O33 << ST_CH_PAIR_SOUT1_SFT; + tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT2_SFT; + tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT3_SFT; + break; + case 5: + case 6: + tdm_con = TDM_CH_START_O30_O31 << ST_CH_PAIR_SOUT0_SFT; + tdm_con |= TDM_CH_START_O32_O33 << ST_CH_PAIR_SOUT1_SFT; + tdm_con |= TDM_CH_START_O34_O35 << ST_CH_PAIR_SOUT2_SFT; + tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT3_SFT; + break; + case 7: + case 8: + tdm_con = TDM_CH_START_O30_O31 << ST_CH_PAIR_SOUT0_SFT; + tdm_con |= TDM_CH_START_O32_O33 << ST_CH_PAIR_SOUT1_SFT; + tdm_con |= TDM_CH_START_O34_O35 << ST_CH_PAIR_SOUT2_SFT; + tdm_con |= TDM_CH_START_O36_O37 << ST_CH_PAIR_SOUT3_SFT; + break; + default: + tdm_con = 0; + } + regmap_write(afe->regmap, AFE_TDM_CON2, tdm_con); + regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0, + HDMI_CH_NUM_MASK_SFT, + channels << HDMI_CH_NUM_SFT); + + return 0; +} + +static int mtk_dai_tdm_trigger(struct snd_pcm_substream *substream, + int cmd, + struct snd_soc_dai *dai) +{ + struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); + int tdm_id = dai->id; + + dev_dbg(afe->dev, "cmd %d, tdm_id %d\n", cmd, tdm_id); + + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + case SNDRV_PCM_TRIGGER_RESUME: + /* enable Out control */ + regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0, + HDMI_OUT_ON_MASK_SFT, + 0x1 << HDMI_OUT_ON_SFT); + + /* enable dptx */ + if (tdm_id == MT8196_DAI_TDM_DPTX) { + regmap_update_bits(afe->regmap, AFE_DPTX_CON, + DPTX_ON_MASK_SFT, 0x1 << + DPTX_ON_SFT); + } + + /* enable tdm */ + regmap_update_bits(afe->regmap, AFE_TDM_CON1, + TDM_EN_MASK_SFT, 0x1 << TDM_EN_SFT); + break; + case SNDRV_PCM_TRIGGER_STOP: + case SNDRV_PCM_TRIGGER_SUSPEND: + /* disable tdm */ + regmap_update_bits(afe->regmap, AFE_TDM_CON1, + TDM_EN_MASK_SFT, 0); + + /* disable dptx */ + if (tdm_id == MT8196_DAI_TDM_DPTX) { + regmap_update_bits(afe->regmap, AFE_DPTX_CON, + DPTX_ON_MASK_SFT, 0); + } + + /* disable Out control */ + regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0, + HDMI_OUT_ON_MASK_SFT, 0); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int mtk_dai_tdm_set_sysclk(struct snd_soc_dai *dai, + int clk_id, unsigned int freq, int dir) +{ + struct mtk_base_afe *afe = dev_get_drvdata(dai->dev); + struct mt8196_afe_private *afe_priv = afe->platform_priv; + struct mtk_afe_tdm_priv *tdm_priv; + + if (dai->id >= MT8196_DAI_NUM || dai->id < 0) + return -EINVAL; + + tdm_priv = afe_priv->dai_priv[dai->id]; + + if (!tdm_priv) + return -EINVAL; + + if (dir != SND_SOC_CLOCK_OUT) + return -EINVAL; + + dev_dbg(afe->dev, "freq %d\n", freq); + + return mtk_dai_tdm_cal_mclk(afe, tdm_priv, freq); +} + +static const struct snd_soc_dai_ops mtk_dai_tdm_ops = { + .hw_params = mtk_dai_tdm_hw_params, + .trigger = mtk_dai_tdm_trigger, + .set_sysclk = mtk_dai_tdm_set_sysclk, +}; + +/* dai driver */ +#define MTK_TDM_RATES (SNDRV_PCM_RATE_8000_48000 |\ + SNDRV_PCM_RATE_88200 |\ + SNDRV_PCM_RATE_96000 |\ + SNDRV_PCM_RATE_176400 |\ + SNDRV_PCM_RATE_192000) + +#define MTK_TDM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ + SNDRV_PCM_FMTBIT_S24_LE |\ + SNDRV_PCM_FMTBIT_S32_LE) + +static struct snd_soc_dai_driver mtk_dai_tdm_driver[] = { + { + .name = "TDM", + .id = MT8196_DAI_TDM, + .playback = { + .stream_name = "TDM", + .channels_min = 2, + .channels_max = 8, + .rates = MTK_TDM_RATES, + .formats = MTK_TDM_FORMATS, + }, + .ops = &mtk_dai_tdm_ops, + }, + { + .name = "TDM_DPTX", + .id = MT8196_DAI_TDM_DPTX, + .playback = { + .stream_name = "TDM_DPTX", + .channels_min = 2, + .channels_max = 8, + .rates = MTK_TDM_RATES, + .formats = MTK_TDM_FORMATS, + }, + .ops = &mtk_dai_tdm_ops, + }, +}; + +static struct mtk_afe_tdm_priv *init_tdm_priv_data(struct mtk_base_afe *afe, + int id) +{ + struct mtk_afe_tdm_priv *tdm_priv; + + tdm_priv = devm_kzalloc(afe->dev, sizeof(struct mtk_afe_tdm_priv), + GFP_KERNEL); + if (!tdm_priv) + return NULL; + + if (id == MT8196_DAI_TDM_DPTX) + tdm_priv->mclk_multiple = 256; + else + tdm_priv->mclk_multiple = 128; + + tdm_priv->bck_id = MT8196_TDMOUT_BCK; + tdm_priv->mclk_id = MT8196_TDMOUT_MCK; + + return tdm_priv; +} + +int mt8196_dai_tdm_register(struct mtk_base_afe *afe) +{ + struct mt8196_afe_private *afe_priv = afe->platform_priv; + struct mtk_afe_tdm_priv *tdm_priv, *tdm_dptx_priv; + struct mtk_base_afe_dai *dai; + + dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL); + if (!dai) + return -ENOMEM; + + list_add(&dai->list, &afe->sub_dais); + + dai->dai_drivers = mtk_dai_tdm_driver; + dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_tdm_driver); + + dai->dapm_widgets = mtk_dai_tdm_widgets; + dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_tdm_widgets); + dai->dapm_routes = mtk_dai_tdm_routes; + dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_tdm_routes); + + tdm_priv = init_tdm_priv_data(afe, MT8196_DAI_TDM); + if (!tdm_priv) + return -ENOMEM; + + tdm_dptx_priv = init_tdm_priv_data(afe, MT8196_DAI_TDM_DPTX); + if (!tdm_dptx_priv) + return -ENOMEM; + + afe_priv->dai_priv[MT8196_DAI_TDM] = tdm_priv; + afe_priv->dai_priv[MT8196_DAI_TDM_DPTX] = tdm_dptx_priv; + + return 0; +} + From patchwork Mon Apr 7 12:06:32 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Darren.Ye" X-Patchwork-Id: 878788 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A99B624DFFC; Mon, 7 Apr 2025 12:11:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; 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Mon, 07 Apr 2025 20:11:09 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by MTKMBS09N2.mediatek.inc (172.21.101.94) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Mon, 7 Apr 2025 20:11:07 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Mon, 7 Apr 2025 20:11:07 +0800 From: Darren.Ye To: Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Jaroslav Kysela , Takashi Iwai , Linus Walleij , Bartosz Golaszewski CC: , , , , , , Darren Ye Subject: [PATCH v2 08/11] ASoC: mediatek: mt8196: add platform driver Date: Mon, 7 Apr 2025 20:06:32 +0800 Message-ID: <20250407120708.26495-9-darren.ye@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250407120708.26495-1-darren.ye@mediatek.com> References: <20250407120708.26495-1-darren.ye@mediatek.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N From: Darren Ye Add mt8196 platform driver. Signed-off-by: Darren Ye --- sound/soc/mediatek/Kconfig | 10 + sound/soc/mediatek/Makefile | 1 + sound/soc/mediatek/mt8196/Makefile | 14 + sound/soc/mediatek/mt8196/mt8196-afe-pcm.c | 5070 ++++++++++++++++++++ 4 files changed, 5095 insertions(+) create mode 100644 sound/soc/mediatek/mt8196/Makefile create mode 100644 sound/soc/mediatek/mt8196/mt8196-afe-pcm.c diff --git a/sound/soc/mediatek/Kconfig b/sound/soc/mediatek/Kconfig index 3033e2d3fe16..606f221e238c 100644 --- a/sound/soc/mediatek/Kconfig +++ b/sound/soc/mediatek/Kconfig @@ -204,6 +204,16 @@ config SND_SOC_MT8186_MT6366 Select Y if you have such device. If unsure select "N". +config SND_SOC_MT8196 + tristate "ASoC support for Mediatek MT8196 chip" + depends on ARCH_MEDIATEK + select SND_SOC_MEDIATEK + help + This adds ASoC driver for Mediatek MT8196 boards + that can be used with other codecs. + Select Y if you have such device. + If unsure select "N". + config SND_SOC_MTK_BTCVSD tristate "ALSA BT SCO CVSD/MSBC Driver" help diff --git a/sound/soc/mediatek/Makefile b/sound/soc/mediatek/Makefile index 4b55434f2168..11d7c484a5d3 100644 --- a/sound/soc/mediatek/Makefile +++ b/sound/soc/mediatek/Makefile @@ -10,3 +10,4 @@ obj-$(CONFIG_SND_SOC_MT8188) += mt8188/ obj-$(CONFIG_SND_SOC_MT8192) += mt8192/ obj-$(CONFIG_SND_SOC_MT8195) += mt8195/ obj-$(CONFIG_SND_SOC_MT8365) += mt8365/ +obj-$(CONFIG_SND_SOC_MT8196) += mt8196/ diff --git a/sound/soc/mediatek/mt8196/Makefile b/sound/soc/mediatek/mt8196/Makefile new file mode 100644 index 000000000000..9bcc09a9a94d --- /dev/null +++ b/sound/soc/mediatek/mt8196/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0 + +# common include path +subdir-ccflags-y += -I$(srctree)/sound/soc/mediatek/common + +# platform driver +obj-$(CONFIG_SND_SOC_MT8196) += snd-soc-mt8196-afe.o +snd-soc-mt8196-afe-objs += \ + mt8196-afe-pcm.o \ + mt8196-afe-clk.o \ + mt8196-dai-adda.o \ + mt8196-dai-i2s.o \ + mt8196-dai-tdm.o + diff --git a/sound/soc/mediatek/mt8196/mt8196-afe-pcm.c b/sound/soc/mediatek/mt8196/mt8196-afe-pcm.c new file mode 100644 index 000000000000..84ccbc7419c7 --- /dev/null +++ b/sound/soc/mediatek/mt8196/mt8196-afe-pcm.c @@ -0,0 +1,5070 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Mediatek ALSA SoC AFE platform driver for 8196 + * + * Copyright (c) 2024 MediaTek Inc. + * Author: Darren Ye + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mt8196-afe-common.h" +#include "mtk-afe-platform-driver.h" +#include "mtk-afe-fe-dai.h" +#include "mt8196-afe-clk.h" +#include "mt8196-interconnection.h" + +static const struct snd_pcm_hardware mt8196_afe_hardware = { + .info = (SNDRV_PCM_INFO_MMAP | + SNDRV_PCM_INFO_NO_PERIOD_WAKEUP | + SNDRV_PCM_INFO_INTERLEAVED | + SNDRV_PCM_INFO_MMAP_VALID), + .formats = (SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S24_LE | + SNDRV_PCM_FMTBIT_S32_LE), + .period_bytes_min = 96, + .period_bytes_max = 4 * 48 * 1024, + .periods_min = 2, + .periods_max = 256, + .buffer_bytes_max = 256 * 1024, + .fifo_size = 0, +}; + +static unsigned int mt8196_rate_transform(struct device *dev, + unsigned int rate) +{ + switch (rate) { + case 8000: + return MTK_AFE_IPM2P0_RATE_8K; + case 11025: + return MTK_AFE_IPM2P0_RATE_11K; + case 12000: + return MTK_AFE_IPM2P0_RATE_12K; + case 16000: + return MTK_AFE_IPM2P0_RATE_16K; + case 22050: + return MTK_AFE_IPM2P0_RATE_22K; + case 24000: + return MTK_AFE_IPM2P0_RATE_24K; + case 32000: + return MTK_AFE_IPM2P0_RATE_32K; + case 44100: + return MTK_AFE_IPM2P0_RATE_44K; + case 48000: + return MTK_AFE_IPM2P0_RATE_48K; + case 88200: + return MTK_AFE_IPM2P0_RATE_88K; + case 96000: + return MTK_AFE_IPM2P0_RATE_96K; + case 176400: + return MTK_AFE_IPM2P0_RATE_176K; + case 192000: + return MTK_AFE_IPM2P0_RATE_192K; + /* not support 260K */ + case 352800: + return MTK_AFE_IPM2P0_RATE_352K; + case 384000: + return MTK_AFE_IPM2P0_RATE_384K; + default: + dev_info(dev, "rate %u invalid, use %d!!!\n", + rate, MTK_AFE_IPM2P0_RATE_48K); + return MTK_AFE_IPM2P0_RATE_48K; + } +} + +static void mt8196_set_cm_rate(struct mtk_base_afe *afe, int id, unsigned int rate) +{ + struct mt8196_afe_private *afe_priv = afe->platform_priv; + + afe_priv->cm_rate[id] = rate; +} + +static int mt8196_convert_cm_ch(unsigned int ch) +{ + return ch - 1; +} + +static unsigned int calculate_cm_update(int rate, int ch) +{ + unsigned int update_val; + + update_val = 26000000 / rate / (ch / 2); + update_val = update_val * 10 / 7; + if (update_val > 100) + update_val = 100; + if (update_val < 7) + update_val = 7; + + return update_val; +} + +static int mt8196_set_cm(struct mtk_base_afe *afe, int id, + bool update, bool swap, unsigned int ch) +{ + unsigned int rate = 0; + unsigned int update_val = 0; + int reg; + struct mt8196_afe_private *afe_priv = afe->platform_priv; + + dev_dbg(afe->dev, "CM%d, rate %d, update %d, swap %d, ch %d\n", + id, rate, update, swap, ch); + + rate = afe_priv->cm_rate[id]; + update_val = update ? calculate_cm_update(rate, (int)ch) : 0x64; + + reg = AFE_CM0_CON0 + 0x10 * id; + /* update cnt */ + regmap_update_bits(afe->regmap, + reg, + AFE_CM_UPDATE_CNT_MASK << AFE_CM_UPDATE_CNT_SFT, + update_val << AFE_CM_UPDATE_CNT_SFT); + + /* rate */ + regmap_update_bits(afe->regmap, + reg, + AFE_CM_1X_EN_SEL_FS_MASK << AFE_CM_1X_EN_SEL_FS_SFT, + rate << AFE_CM_1X_EN_SEL_FS_SFT); + + /* ch num */ + ch = mt8196_convert_cm_ch(ch); + regmap_update_bits(afe->regmap, + reg, + AFE_CM_CH_NUM_MASK << AFE_CM_CH_NUM_SFT, + ch << AFE_CM_CH_NUM_SFT); + + /* swap */ + regmap_update_bits(afe->regmap, + reg, + AFE_CM_BYTE_SWAP_MASK << AFE_CM_BYTE_SWAP_SFT, + swap << AFE_CM_BYTE_SWAP_SFT); + + return 0; +} + +static int mt8196_enable_cm_bypass(struct mtk_base_afe *afe, int id, bool en) +{ + int reg = AFE_CM0_CON0 + 0x10 * id; + + regmap_update_bits(afe->regmap, + reg, + AFE_CM_BYPASS_MODE_MASK << AFE_CM_BYPASS_MODE_SFT, + en << AFE_CM_BYPASS_MODE_SFT); + + return 0; +} + +static int mt8196_fe_startup(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); + struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); + struct snd_pcm_runtime *runtime = substream->runtime; + struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0); + int memif_num = cpu_dai->id; + struct mtk_base_afe_memif *memif = &afe->memif[memif_num]; + const struct snd_pcm_hardware *mtk_afe_hardware = afe->mtk_afe_hardware; + int ret; + + dev_dbg(afe->dev, "memif_num: %d.\n", memif_num); + + memif->substream = substream; + + snd_pcm_hw_constraint_step(substream->runtime, 0, + SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 16); + + snd_soc_set_runtime_hwparams(substream, mtk_afe_hardware); + + ret = snd_pcm_hw_constraint_integer(runtime, + SNDRV_PCM_HW_PARAM_PERIODS); + if (ret < 0) + dev_info(afe->dev, "snd_pcm_hw_constraint_integer failed\n"); + + /* dynamic allocate irq to memif */ + if (memif->irq_usage < 0) { + int irq_id = mtk_dynamic_irq_acquire(afe); + + if (irq_id != afe->irqs_size) { + /* link */ + memif->irq_usage = irq_id; + } else { + dev_err(afe->dev, "no more asys irq\n"); + ret = -EBUSY; + } + } + return ret; +} + +static void mt8196_fe_shutdown(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); + struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); + struct mt8196_afe_private *afe_priv = afe->platform_priv; + struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0); + int memif_num = cpu_dai->id; + struct mtk_base_afe_memif *memif = &afe->memif[memif_num]; + int irq_id = memif->irq_usage; + + dev_dbg(afe->dev, "memif_num: %d.\n", memif_num); + + memif->substream = NULL; + afe_priv->irq_cnt[memif_num] = 0; + afe_priv->xrun_assert[memif_num] = 0; + + if (!memif->const_irq) { + mtk_dynamic_irq_release(afe, irq_id); + memif->irq_usage = -1; + memif->substream = NULL; + } +} + +static int mt8196_fe_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); + unsigned int channels = params_channels(params); + struct mt8196_afe_private *afe_priv = afe->platform_priv; + + afe_priv->cm_channels = channels; + + return mtk_afe_fe_hw_params(substream, params, dai); +} + +static int mt8196_fe_trigger(struct snd_pcm_substream *substream, int cmd, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); + struct snd_pcm_runtime *const runtime = substream->runtime; + struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); + struct mt8196_afe_private *afe_priv = afe->platform_priv; + struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0); + int id = cpu_dai->id; + struct mtk_base_afe_memif *memif = &afe->memif[id]; + int irq_id = memif->irq_usage; + struct mtk_base_afe_irq *irqs = &afe->irqs[irq_id]; + const struct mtk_base_irq_data *irq_data = irqs->irq_data; + unsigned int counter = runtime->period_size; + unsigned int rate = runtime->rate; + int fs; + int ret = 0; + unsigned int tmp_reg = 0; + + dev_info(afe->dev, "%s cmd %d, irq_id %d\n", + memif->data->name, cmd, irq_id); + + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + case SNDRV_PCM_TRIGGER_RESUME: + dev_dbg(afe->dev, "%s cmd %d, id %d\n", + memif->data->name, cmd, id); + ret = mtk_memif_set_enable(afe, id); + if (ret) { + dev_err(afe->dev, "id %d, memif enable fail.\n", id); + return ret; + } + + /* + * for small latency record + * ul memif need read some data before irq enable + */ + if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { + if ((runtime->period_size * 1000) / rate <= 10) + usleep_range(300, 350); + } + + /* set irq counter */ + if (afe_priv->irq_cnt[id] > 0) + counter = afe_priv->irq_cnt[id]; + + regmap_update_bits(afe->regmap, + irq_data->irq_cnt_reg, + irq_data->irq_cnt_maskbit << irq_data->irq_cnt_shift, + counter << irq_data->irq_cnt_shift); + + /* set irq fs */ + fs = afe->irq_fs(substream, runtime->rate); + if (fs < 0) + return -EINVAL; + + if (irq_data->irq_fs_reg >= 0) + regmap_update_bits(afe->regmap, + irq_data->irq_fs_reg, + irq_data->irq_fs_maskbit << irq_data->irq_fs_shift, + fs << irq_data->irq_fs_shift); + + /* enable interrupt */ + regmap_update_bits(afe->regmap, + irq_data->irq_en_reg, + 1 << irq_data->irq_en_shift, + 1 << irq_data->irq_en_shift); + + return 0; + case SNDRV_PCM_TRIGGER_STOP: + case SNDRV_PCM_TRIGGER_SUSPEND: + ret = mtk_memif_set_disable(afe, id); + if (ret) { + dev_warn(afe->dev, + "id %d, memif disable fail\n", id); + } + + /* disable interrupt */ + regmap_update_bits(afe->regmap, + irq_data->irq_en_reg, + 1 << irq_data->irq_en_shift, + 0 << irq_data->irq_en_shift); + + /* clear pending IRQ */ + regmap_read(afe->regmap, irq_data->irq_clr_reg, &tmp_reg); + regmap_update_bits(afe->regmap, irq_data->irq_clr_reg, + AFE_IRQ_CLR_CFG_MASK_SFT | AFE_IRQ_MISS_FLAG_CLR_CFG_MASK_SFT, + tmp_reg ^ (AFE_IRQ_CLR_CFG_MASK_SFT | + AFE_IRQ_MISS_FLAG_CLR_CFG_MASK_SFT)); + + return ret; + default: + return -EINVAL; + } +} + +static int mt8196_memif_fs(struct snd_pcm_substream *substream, + unsigned int rate) +{ + struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); + struct snd_soc_component *component = + snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME); + struct mtk_base_afe *afe = NULL; + struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0); + int id = cpu_dai->id; + unsigned int rate_reg = 0; + int cm = 0; + + if (!component) + return -EINVAL; + + afe = snd_soc_component_get_drvdata(component); + + if (!afe) + return -EINVAL; + + rate_reg = mt8196_rate_transform(afe->dev, rate); + + switch (id) { + case MT8196_MEMIF_VUL8: + case MT8196_MEMIF_VUL_CM0: + cm = CM0; + break; + case MT8196_MEMIF_VUL9: + case MT8196_MEMIF_VUL_CM1: + cm = CM1; + break; + case MT8196_MEMIF_VUL10: + case MT8196_MEMIF_VUL_CM2: + cm = CM2; + break; + default: + cm = CM0; + break; + } + + mt8196_set_cm_rate(afe, cm, rate_reg); + + return rate_reg; +} + +static int mt8196_get_dai_fs(struct mtk_base_afe *afe, + int dai_id, unsigned int rate) +{ + return mt8196_rate_transform(afe->dev, rate); +} + +static int mt8196_irq_fs(struct snd_pcm_substream *substream, unsigned int rate) +{ + struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); + struct snd_soc_component *component = + snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME); + struct mtk_base_afe *afe = NULL; + + if (!component) + return -EINVAL; + afe = snd_soc_component_get_drvdata(component); + return mt8196_rate_transform(afe->dev, rate); +} + +static int mt8196_get_memif_pbuf_size(struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + + if ((runtime->period_size * 1000) / runtime->rate > 10) + return MT8196_MEMIF_PBUF_SIZE_256_BYTES; + else + return MT8196_MEMIF_PBUF_SIZE_32_BYTES; +} + +/* FE DAIs */ +static const struct snd_soc_dai_ops mt8196_memif_dai_ops = { + .startup = mt8196_fe_startup, + .shutdown = mt8196_fe_shutdown, + .hw_params = mt8196_fe_hw_params, + .hw_free = mtk_afe_fe_hw_free, + .prepare = mtk_afe_fe_prepare, + .trigger = mt8196_fe_trigger, +}; + +#define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000 |\ + SNDRV_PCM_RATE_88200 |\ + SNDRV_PCM_RATE_96000 |\ + SNDRV_PCM_RATE_176400 |\ + SNDRV_PCM_RATE_192000) + +#define MTK_PCM_DAI_RATES (SNDRV_PCM_RATE_8000 |\ + SNDRV_PCM_RATE_16000 |\ + SNDRV_PCM_RATE_32000 |\ + SNDRV_PCM_RATE_48000) + +#define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ + SNDRV_PCM_FMTBIT_S24_LE |\ + SNDRV_PCM_FMTBIT_S32_LE) + +static struct snd_soc_dai_driver mt8196_memif_dai_driver[] = { + /* FE DAIs: memory intefaces to CPU */ + { + .name = "DL0", + .id = MT8196_MEMIF_DL0, + .playback = { + .stream_name = "DL0", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_PCM_RATES, + .formats = MTK_PCM_FORMATS, + }, + .ops = &mt8196_memif_dai_ops, + }, + { + .name = "DL1", + .id = MT8196_MEMIF_DL1, + .playback = { + .stream_name = "DL1", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_PCM_RATES, + .formats = MTK_PCM_FORMATS, + }, + .ops = &mt8196_memif_dai_ops, + }, + { + .name = "DL2", + .id = MT8196_MEMIF_DL2, + .playback = { + .stream_name = "DL2", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_PCM_RATES, + .formats = MTK_PCM_FORMATS, + }, + .ops = &mt8196_memif_dai_ops, + }, + { + .name = "DL3", + .id = MT8196_MEMIF_DL3, + .playback = { + .stream_name = "DL3", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_PCM_RATES, + .formats = MTK_PCM_FORMATS, + }, + .ops = &mt8196_memif_dai_ops, + }, + { + .name = "DL4", + .id = MT8196_MEMIF_DL4, + .playback = { + .stream_name = "DL4", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_PCM_RATES, + .formats = MTK_PCM_FORMATS, + }, + .ops = &mt8196_memif_dai_ops, + }, + { + .name = "DL5", + .id = MT8196_MEMIF_DL5, + .playback = { + .stream_name = "DL5", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_PCM_RATES, + .formats = MTK_PCM_FORMATS, + }, + .ops = &mt8196_memif_dai_ops, + }, + { + .name = "DL6", + .id = MT8196_MEMIF_DL6, + .playback = { + .stream_name = "DL6", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_PCM_RATES, + .formats = MTK_PCM_FORMATS, + }, + .ops = &mt8196_memif_dai_ops, + }, + { + .name = "DL7", + .id = MT8196_MEMIF_DL7, + .playback = { + .stream_name = "DL7", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_PCM_RATES, + .formats = MTK_PCM_FORMATS, + }, + .ops = &mt8196_memif_dai_ops, + }, + { + .name = "DL8", + .id = MT8196_MEMIF_DL8, + .playback = { + .stream_name = "DL8", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_PCM_RATES, + .formats = MTK_PCM_FORMATS, + }, + .ops = &mt8196_memif_dai_ops, + }, + { + .name = "DL23", + .id = MT8196_MEMIF_DL23, + .playback = { + .stream_name = "DL23", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_PCM_RATES, + .formats = MTK_PCM_FORMATS, + }, + .ops = &mt8196_memif_dai_ops, + }, + { + .name = "DL24", + .id = MT8196_MEMIF_DL24, + .playback = { + .stream_name = "DL24", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_PCM_RATES, + .formats = MTK_PCM_FORMATS, + }, + .ops = &mt8196_memif_dai_ops, + }, + { + .name = "DL25", + .id = MT8196_MEMIF_DL25, + .playback = { + .stream_name = "DL25", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_PCM_RATES, + .formats = MTK_PCM_FORMATS, + }, + .ops = &mt8196_memif_dai_ops, + }, + { + .name = "DL26", + .id = MT8196_MEMIF_DL26, + .playback = { + .stream_name = "DL26", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_PCM_RATES, + .formats = MTK_PCM_FORMATS, + }, + .ops = &mt8196_memif_dai_ops, + }, + { + .name = "DL_4CH", + .id = MT8196_MEMIF_DL_4CH, + .playback = { + .stream_name = "DL_4CH", + .channels_min = 1, + .channels_max = 4, + .rates = MTK_PCM_RATES, + .formats = MTK_PCM_FORMATS, + }, + .ops = &mt8196_memif_dai_ops, + }, + { + .name = "DL_24CH", + .id = MT8196_MEMIF_DL_24CH, + .playback = { + .stream_name = "DL_24CH", + .channels_min = 1, + .channels_max = 8, + .rates = MTK_PCM_RATES, + .formats = MTK_PCM_FORMATS, + }, + .ops = &mt8196_memif_dai_ops, + }, + { + .name = "UL0", + .id = MT8196_MEMIF_VUL0, + .capture = { + .stream_name = "UL0", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_PCM_RATES, + .formats = MTK_PCM_FORMATS, + }, + .ops = &mt8196_memif_dai_ops, + }, + { + .name = "UL1", + .id = MT8196_MEMIF_VUL1, + .capture = { + .stream_name = "UL1", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_PCM_RATES, + .formats = MTK_PCM_FORMATS, + }, + .ops = &mt8196_memif_dai_ops, + }, + { + .name = "UL2", + .id = MT8196_MEMIF_VUL2, + .capture = { + .stream_name = "UL2", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_PCM_RATES, + .formats = MTK_PCM_FORMATS, + }, + .ops = &mt8196_memif_dai_ops, + }, + { + .name = "UL3", + .id = MT8196_MEMIF_VUL3, + .capture = { + .stream_name = "UL3", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_PCM_RATES, + .formats = MTK_PCM_FORMATS, + }, + .ops = &mt8196_memif_dai_ops, + }, + { + .name = "UL4", + .id = MT8196_MEMIF_VUL4, + .capture = { + .stream_name = "UL4", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_PCM_RATES, + .formats = MTK_PCM_FORMATS, + }, + .ops = &mt8196_memif_dai_ops, + }, + { + .name = "UL5", + .id = MT8196_MEMIF_VUL5, + .capture = { + .stream_name = "UL5", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_PCM_RATES, + .formats = MTK_PCM_FORMATS, + }, + .ops = &mt8196_memif_dai_ops, + }, + { + .name = "UL6", + .id = MT8196_MEMIF_VUL6, + .capture = { + .stream_name = "UL6", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_PCM_RATES, + .formats = MTK_PCM_FORMATS, + }, + .ops = &mt8196_memif_dai_ops, + }, + { + .name = "UL7", + .id = MT8196_MEMIF_VUL7, + .capture = { + .stream_name = "UL7", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_PCM_RATES, + .formats = MTK_PCM_FORMATS, + }, + .ops = &mt8196_memif_dai_ops, + }, + { + .name = "UL8", + .id = MT8196_MEMIF_VUL8, + .capture = { + .stream_name = "UL8", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_PCM_RATES, + .formats = MTK_PCM_FORMATS, + }, + .ops = &mt8196_memif_dai_ops, + }, + { + .name = "UL9", + .id = MT8196_MEMIF_VUL9, + .capture = { + .stream_name = "UL9", + .channels_min = 1, + .channels_max = 16, + .rates = MTK_PCM_RATES, + .formats = MTK_PCM_FORMATS, + }, + .ops = &mt8196_memif_dai_ops, + }, + { + .name = "UL10", + .id = MT8196_MEMIF_VUL10, + .capture = { + .stream_name = "UL10", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_PCM_RATES, + .formats = MTK_PCM_FORMATS, + }, + .ops = &mt8196_memif_dai_ops, + }, + { + .name = "UL24", + .id = MT8196_MEMIF_VUL24, + .capture = { + .stream_name = "UL24", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_PCM_RATES, + .formats = MTK_PCM_FORMATS, + }, + .ops = &mt8196_memif_dai_ops, + }, + { + .name = "UL25", + .id = MT8196_MEMIF_VUL25, + .capture = { + .stream_name = "UL25", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_PCM_RATES, + .formats = MTK_PCM_FORMATS, + }, + .ops = &mt8196_memif_dai_ops, + }, + { + .name = "UL26", + .id = MT8196_MEMIF_VUL26, + .capture = { + .stream_name = "UL26", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_PCM_RATES, + .formats = MTK_PCM_FORMATS, + }, + .ops = &mt8196_memif_dai_ops, + }, + { + .name = "UL_CM0", + .id = MT8196_MEMIF_VUL_CM0, + .capture = { + .stream_name = "UL_CM0", + .channels_min = 1, + .channels_max = 8, + .rates = MTK_PCM_RATES, + .formats = MTK_PCM_FORMATS, + }, + .ops = &mt8196_memif_dai_ops, + }, + { + .name = "UL_CM1", + .id = MT8196_MEMIF_VUL_CM1, + .capture = { + .stream_name = "UL_CM1", + .channels_min = 1, + .channels_max = 16, + .rates = MTK_PCM_RATES, + .formats = MTK_PCM_FORMATS, + }, + .ops = &mt8196_memif_dai_ops, + }, + { + .name = "UL_CM2", + .id = MT8196_MEMIF_VUL_CM2, + .capture = { + .stream_name = "UL_CM2", + .channels_min = 1, + .channels_max = 32, + .rates = MTK_PCM_RATES, + .formats = MTK_PCM_FORMATS, + }, + .ops = &mt8196_memif_dai_ops, + }, + { + .name = "UL_ETDM_IN0", + .id = MT8196_MEMIF_ETDM_IN0, + .capture = { + .stream_name = "UL_ETDM_IN0", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_PCM_RATES, + .formats = MTK_PCM_FORMATS, + }, + .ops = &mt8196_memif_dai_ops, + }, + { + .name = "UL_ETDM_IN1", + .id = MT8196_MEMIF_ETDM_IN1, + .capture = { + .stream_name = "UL_ETDM_IN1", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_PCM_RATES, + .formats = MTK_PCM_FORMATS, + }, + .ops = &mt8196_memif_dai_ops, + }, + { + .name = "UL_ETDM_IN2", + .id = MT8196_MEMIF_ETDM_IN2, + .capture = { + .stream_name = "UL_ETDM_IN2", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_PCM_RATES, + .formats = MTK_PCM_FORMATS, + }, + .ops = &mt8196_memif_dai_ops, + }, + { + .name = "UL_ETDM_IN3", + .id = MT8196_MEMIF_ETDM_IN3, + .capture = { + .stream_name = "UL_ETDM_IN3", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_PCM_RATES, + .formats = MTK_PCM_FORMATS, + }, + .ops = &mt8196_memif_dai_ops, + }, + { + .name = "UL_ETDM_IN4", + .id = MT8196_MEMIF_ETDM_IN4, + .capture = { + .stream_name = "UL_ETDM_IN4", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_PCM_RATES, + .formats = MTK_PCM_FORMATS, + }, + .ops = &mt8196_memif_dai_ops, + }, + { + .name = "UL_ETDM_IN6", + .id = MT8196_MEMIF_ETDM_IN6, + .capture = { + .stream_name = "UL_ETDM_IN6", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_PCM_RATES, + .formats = MTK_PCM_FORMATS, + }, + .ops = &mt8196_memif_dai_ops, + }, + { + .name = "HDMI", + .id = MT8196_MEMIF_HDMI, + .playback = { + .stream_name = "HDMI", + .channels_min = 2, + .channels_max = 8, + .rates = MTK_PCM_RATES, + .formats = MTK_PCM_FORMATS, + }, + .ops = &mt8196_memif_dai_ops, + }, +}; + +static const struct snd_kcontrol_new mt8196_pcm_kcontrols[] = { +}; + +enum { + CM0_MUX_VUL8_2CH, + CM0_MUX_VUL8_8CH, + CM0_MUX_MASK, +}; + +enum { + CM1_MUX_VUL9_2CH, + CM1_MUX_VUL9_16CH, + CM1_MUX_MASK, +}; + +enum { + CM2_MUX_VUL10_2CH, + CM2_MUX_VUL10_32CH, + CM2_MUX_MASK, +}; + +static int ul_cm0_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); + struct mt8196_afe_private *afe_priv = afe->platform_priv; + unsigned int channels = afe_priv->cm_channels; + + dev_dbg(afe->dev, "event 0x%x, name %s, channels %u\n", + event, w->name, channels); + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + mt8196_enable_cm_bypass(afe, CM0, 0x0); + mt8196_set_cm(afe, CM0, true, false, channels); + break; + case SND_SOC_DAPM_PRE_PMD: + mt8196_enable_cm_bypass(afe, CM0, 0x1); + break; + default: + break; + } + return 0; +} + +static int ul_cm1_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); + struct mt8196_afe_private *afe_priv = afe->platform_priv; + unsigned int channels = afe_priv->cm_channels; + + dev_dbg(afe->dev, "event 0x%x, name %s, channels %u\n", + event, w->name, channels); + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + mt8196_enable_cm_bypass(afe, CM1, 0x0); + mt8196_set_cm(afe, CM1, true, false, channels); + break; + case SND_SOC_DAPM_PRE_PMD: + mt8196_enable_cm_bypass(afe, CM1, 0x1); + break; + default: + break; + } + return 0; +} + +static int ul_cm2_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); + struct mt8196_afe_private *afe_priv = afe->platform_priv; + unsigned int channels = afe_priv->cm_channels; + + dev_dbg(afe->dev, "event 0x%x, name %s, channels %u\n", + event, w->name, channels); + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + mt8196_enable_cm_bypass(afe, CM2, 0x0); + mt8196_set_cm(afe, CM2, true, false, channels); + break; + case SND_SOC_DAPM_PRE_PMD: + mt8196_enable_cm_bypass(afe, CM2, 0x1); + break; + default: + break; + } + return 0; +} + +/* dma widget & routes*/ +static const struct snd_kcontrol_new memif_ul0_ch1_mix[] = { + /* Normal record */ + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN018_0, + I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN018_0, + I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN018_0, + I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN018_0, + I_ADDA_UL_CH4, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH5", AFE_CONN018_0, + I_ADDA_UL_CH5, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH6", AFE_CONN018_0, + I_ADDA_UL_CH6, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH1", AFE_CONN018_1, + I_DL0_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN018_1, + I_DL1_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN018_1, + I_DL2_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN018_1, + I_DL3_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN018_1, + I_DL4_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN018_1, + I_DL6_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH1", AFE_CONN018_1, + I_DL7_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL23_CH1", AFE_CONN018_2, + I_DL23_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH1", AFE_CONN018_1, + I_DL_24CH_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("I2SIN0_CH1", AFE_CONN018_4, + I_I2SIN0_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("I2SIN1_CH1", AFE_CONN018_4, + I_I2SIN1_CH1, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul0_ch2_mix[] = { + /* Normal record */ + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN019_0, + I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN019_0, + I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN019_0, + I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN019_0, + I_ADDA_UL_CH4, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH5", AFE_CONN019_0, + I_ADDA_UL_CH5, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH6", AFE_CONN019_0, + I_ADDA_UL_CH6, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH2", AFE_CONN019_1, + I_DL0_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN019_1, + I_DL1_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN019_1, + I_DL2_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN019_1, + I_DL3_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN019_1, + I_DL4_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN019_1, + I_DL6_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH2", AFE_CONN019_1, + I_DL7_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL23_CH2", AFE_CONN019_2, + I_DL23_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH2", AFE_CONN019_1, + I_DL_24CH_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("I2SIN0_CH2", AFE_CONN019_4, + I_I2SIN0_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("I2SIN1_CH2", AFE_CONN019_4, + I_I2SIN1_CH2, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul1_ch1_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN020_0, + I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH1", AFE_CONN020_1, + I_DL0_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN020_1, + I_DL1_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN020_1, + I_DL2_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN020_1, + I_DL3_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN020_1, + I_DL4_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN020_1, + I_DL6_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH1", AFE_CONN020_1, + I_DL7_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL23_CH1", AFE_CONN020_2, + I_DL23_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH1", AFE_CONN020_1, + I_DL_24CH_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("I2SIN0_CH1", AFE_CONN020_4, + I_I2SIN0_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("I2SIN1_CH1", AFE_CONN020_4, + I_I2SIN1_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("I2SIN3_CH1", AFE_CONN020_4, + I_I2SIN3_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("I2SIN4_CH1", AFE_CONN020_4, + I_I2SIN4_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("I2SIN6_CH1", AFE_CONN020_5, + I_I2SIN6_CH1, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul1_ch2_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN021_0, + I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH2", AFE_CONN021_1, + I_DL0_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN021_1, + I_DL1_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN021_1, + I_DL2_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN021_1, + I_DL3_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN021_1, + I_DL4_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN021_1, + I_DL6_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH2", AFE_CONN021_1, + I_DL7_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL23_CH2", AFE_CONN021_2, + I_DL23_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH2", AFE_CONN021_1, + I_DL_24CH_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("I2SIN0_CH2", AFE_CONN021_4, + I_I2SIN0_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("I2SIN1_CH2", AFE_CONN021_4, + I_I2SIN1_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("I2SIN3_CH2", AFE_CONN021_4, + I_I2SIN3_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("I2SIN4_CH2", AFE_CONN021_4, + I_I2SIN4_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("I2SIN6_CH2", AFE_CONN021_5, + I_I2SIN6_CH2, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul2_ch1_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN022_0, + I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN022_0, + I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN022_0, + I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN022_0, + I_ADDA_UL_CH4, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul2_ch2_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN023_0, + I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN023_0, + I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN023_0, + I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN023_0, + I_ADDA_UL_CH4, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul3_ch1_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN024_0, + I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("I2SIN0_CH1", AFE_CONN024_4, + I_I2SIN0_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("I2SIN1_CH1", AFE_CONN024_4, + I_I2SIN1_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("I2SIN3_CH1", AFE_CONN024_4, + I_I2SIN3_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("I2SIN4_CH1", AFE_CONN024_4, + I_I2SIN4_CH1, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul3_ch2_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN025_0, + I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("I2SIN0_CH2", AFE_CONN025_4, + I_I2SIN0_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("I2SIN1_CH2", AFE_CONN025_4, + I_I2SIN1_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("I2SIN3_CH2", AFE_CONN025_4, + I_I2SIN3_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("I2SIN4_CH2", AFE_CONN025_4, + I_I2SIN4_CH2, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul4_ch1_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN026_0, + I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH1", AFE_CONN026_1, + I_DL0_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN026_1, + I_DL1_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN026_1, + I_DL6_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN026_1, + I_DL2_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN026_1, + I_DL3_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH1", AFE_CONN026_1, + I_DL_24CH_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("I2SIN0_CH1", AFE_CONN026_4, + I_I2SIN0_CH1, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul4_ch2_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN027_0, + I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH2", AFE_CONN027_1, + I_DL0_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN027_1, + I_DL1_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN027_1, + I_DL6_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN027_1, + I_DL2_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN027_1, + I_DL3_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH2", AFE_CONN027_1, + I_DL_24CH_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("I2SIN0_CH2", AFE_CONN027_4, + I_I2SIN0_CH2, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul5_ch1_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN028_0, + I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH1", AFE_CONN028_1, + I_DL0_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN028_1, + I_DL1_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN028_1, + I_DL6_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN028_1, + I_DL2_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN028_1, + I_DL3_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH1", AFE_CONN028_1, + I_DL_24CH_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("I2SIN3_CH1", AFE_CONN028_4, + I_I2SIN3_CH1, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul5_ch2_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN029_0, + I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH2", AFE_CONN029_1, + I_DL0_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN029_1, + I_DL1_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN029_1, + I_DL6_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN029_1, + I_DL2_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN029_1, + I_DL3_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH2", AFE_CONN029_1, + I_DL_24CH_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("I2SIN3_CH2", AFE_CONN029_4, + I_I2SIN3_CH2, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul6_ch1_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN030_0, + I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH1", AFE_CONN030_1, + I_DL1_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN030_1, + I_DL2_CH1, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul6_ch2_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN031_0, + I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH2", AFE_CONN031_1, + I_DL1_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN031_1, + I_DL2_CH2, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul7_ch1_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN032_0, + I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN032_0, + I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN032_0, + I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN032_0, + I_ADDA_UL_CH4, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH1", AFE_CONN032_1, + I_DL1_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN032_1, + I_DL2_CH1, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul7_ch2_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN033_0, + I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN033_0, + I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN033_0, + I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN033_0, + I_ADDA_UL_CH4, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH2", AFE_CONN033_1, + I_DL1_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN033_1, + I_DL2_CH2, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul8_ch1_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN034_0, + I_ADDA_UL_CH1, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul8_ch2_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN035_0, + I_ADDA_UL_CH1, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul9_ch1_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN036_0, + I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN036_0, + I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN036_0, + I_ADDA_UL_CH3, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul9_ch2_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN037_0, + I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN037_0, + I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN037_0, + I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN037_0, + I_ADDA_UL_CH4, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul10_ch1_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN038_0, + I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN038_0, + I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN038_0, + I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN038_0, + I_ADDA_UL_CH4, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul10_ch2_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN039_0, + I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN039_0, + I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN039_0, + I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN039_0, + I_ADDA_UL_CH4, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul24_ch1_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN066_0, + I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("I2SIN0_CH1", AFE_CONN066_4, + I_I2SIN0_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("I2SIN6_CH1", AFE_CONN066_5, + I_I2SIN6_CH1, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul24_ch2_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN067_0, + I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("I2SIN0_CH2", AFE_CONN067_4, + I_I2SIN0_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("I2SIN6_CH2", AFE_CONN067_5, + I_I2SIN6_CH2, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul25_ch1_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("I2SIN0_CH1", AFE_CONN068_4, + I_I2SIN0_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("I2SIN6_CH1", AFE_CONN068_5, + I_I2SIN6_CH1, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul25_ch2_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("I2SIN0_CH2", AFE_CONN069_4, + I_I2SIN0_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("I2SIN6_CH2", AFE_CONN069_5, + I_I2SIN6_CH2, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul26_ch1_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("I2SIN0_CH1", AFE_CONN070_4, + I_I2SIN0_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("I2SIN6_CH1", AFE_CONN070_5, + I_I2SIN6_CH1, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul26_ch2_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("I2SIN0_CH2", AFE_CONN071_4, + I_I2SIN0_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("I2SIN6_CH2", AFE_CONN071_5, + I_I2SIN6_CH2, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul_cm0_ch1_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN040_0, + I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN040_0, + I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN040_0, + I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN040_0, + I_ADDA_UL_CH4, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul_cm0_ch2_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN041_0, + I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN041_0, + I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN041_0, + I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN041_0, + I_ADDA_UL_CH4, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul_cm0_ch3_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN042_0, + I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN042_0, + I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN042_0, + I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN042_0, + I_ADDA_UL_CH4, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul_cm0_ch4_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN043_0, + I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN043_0, + I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN043_0, + I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN043_0, + I_ADDA_UL_CH4, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul_cm0_ch5_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN044_0, + I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN044_0, + I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN044_0, + I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN044_0, + I_ADDA_UL_CH4, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul_cm0_ch6_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN045_0, + I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN045_0, + I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN045_0, + I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN045_0, + I_ADDA_UL_CH4, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul_cm0_ch7_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN046_0, + I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN046_0, + I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN046_0, + I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN046_0, + I_ADDA_UL_CH4, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul_cm0_ch8_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN047_0, + I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN047_0, + I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN047_0, + I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN047_0, + I_ADDA_UL_CH4, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul_cm1_ch1_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN048_0, + I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN048_0, + I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN048_0, + I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN048_0, + I_ADDA_UL_CH4, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH5", AFE_CONN048_0, + I_ADDA_UL_CH5, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH6", AFE_CONN048_0, + I_ADDA_UL_CH6, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul_cm1_ch2_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN049_0, + I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN049_0, + I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN049_0, + I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN049_0, + I_ADDA_UL_CH4, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH5", AFE_CONN049_0, + I_ADDA_UL_CH5, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH6", AFE_CONN049_0, + I_ADDA_UL_CH6, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul_cm1_ch3_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN050_0, + I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN050_0, + I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN050_0, + I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN050_0, + I_ADDA_UL_CH4, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH5", AFE_CONN050_0, + I_ADDA_UL_CH5, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH6", AFE_CONN050_0, + I_ADDA_UL_CH6, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul_cm1_ch4_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN051_0, + I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN051_0, + I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN051_0, + I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN051_0, + I_ADDA_UL_CH4, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH5", AFE_CONN051_0, + I_ADDA_UL_CH5, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH6", AFE_CONN051_0, + I_ADDA_UL_CH6, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul_cm1_ch5_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN052_0, + I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN052_0, + I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN052_0, + I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN052_0, + I_ADDA_UL_CH4, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH5", AFE_CONN052_0, + I_ADDA_UL_CH5, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH6", AFE_CONN052_0, + I_ADDA_UL_CH6, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul_cm1_ch6_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN053_0, + I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN053_0, + I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN053_0, + I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN053_0, + I_ADDA_UL_CH4, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH5", AFE_CONN053_0, + I_ADDA_UL_CH5, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH6", AFE_CONN053_0, + I_ADDA_UL_CH6, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul_cm1_ch7_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN054_0, + I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN054_0, + I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN054_0, + I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN054_0, + I_ADDA_UL_CH4, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul_cm1_ch8_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN055_0, + I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN055_0, + I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN055_0, + I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN055_0, + I_ADDA_UL_CH4, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul_cm1_ch9_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN056_0, + I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN056_0, + I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN056_0, + I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN056_0, + I_ADDA_UL_CH4, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul_cm1_ch10_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN057_0, + I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN057_0, + I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN057_0, + I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN057_0, + I_ADDA_UL_CH4, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul_cm1_ch11_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN058_0, + I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN058_0, + I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN058_0, + I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN058_0, + I_ADDA_UL_CH4, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul_cm1_ch12_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN059_0, + I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN059_0, + I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN059_0, + I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN059_0, + I_ADDA_UL_CH4, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul_cm1_ch13_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN060_0, + I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN060_0, + I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN060_0, + I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN060_0, + I_ADDA_UL_CH4, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul_cm1_ch14_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN061_0, + I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN061_0, + I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN061_0, + I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN061_0, + I_ADDA_UL_CH4, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul_cm1_ch15_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN062_0, + I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN062_0, + I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN062_0, + I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN062_0, + I_ADDA_UL_CH4, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul_cm1_ch16_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN063_0, + I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN063_0, + I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN063_0, + I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN063_0, + I_ADDA_UL_CH4, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul_cm2_ch1_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN064_0, I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN064_0, I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN064_0, I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN064_0, I_ADDA_UL_CH4, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH5", AFE_CONN064_0, I_ADDA_UL_CH5, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH6", AFE_CONN064_0, I_ADDA_UL_CH6, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul_cm2_ch2_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN065_0, I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN065_0, I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN065_0, I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN065_0, I_ADDA_UL_CH4, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH5", AFE_CONN065_0, I_ADDA_UL_CH5, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH6", AFE_CONN065_0, I_ADDA_UL_CH6, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul_cm2_ch3_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN066_0, I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN066_0, I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN066_0, I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN066_0, I_ADDA_UL_CH4, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH5", AFE_CONN066_0, I_ADDA_UL_CH5, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH6", AFE_CONN066_0, I_ADDA_UL_CH6, 1, 0) +}; + +static const struct snd_kcontrol_new memif_ul_cm2_ch4_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN067_0, I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN067_0, I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN067_0, I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN067_0, I_ADDA_UL_CH4, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH5", AFE_CONN067_0, I_ADDA_UL_CH5, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH6", AFE_CONN067_0, I_ADDA_UL_CH6, 1, 0) +}; + +static const struct snd_kcontrol_new memif_ul_cm2_ch5_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN068_0, I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN068_0, I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN068_0, I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN068_0, I_ADDA_UL_CH4, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH5", AFE_CONN068_0, I_ADDA_UL_CH5, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH6", AFE_CONN068_0, I_ADDA_UL_CH6, 1, 0) +}; + +static const struct snd_kcontrol_new memif_ul_cm2_ch6_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN069_0, I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN069_0, I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN069_0, I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN069_0, I_ADDA_UL_CH4, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH5", AFE_CONN069_0, I_ADDA_UL_CH5, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH6", AFE_CONN069_0, I_ADDA_UL_CH6, 1, 0) +}; + +static const struct snd_kcontrol_new memif_ul_cm2_ch7_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN070_0, I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN070_0, I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN070_0, I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN070_0, I_ADDA_UL_CH4, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul_cm2_ch8_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN071_0, I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN071_0, I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN071_0, I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN071_0, I_ADDA_UL_CH4, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul_cm2_ch9_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN072_0, I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN072_0, I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN072_0, I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN072_0, I_ADDA_UL_CH4, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul_cm2_ch10_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN073_0, I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN073_0, I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN073_0, I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN073_0, I_ADDA_UL_CH4, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul_cm2_ch11_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN074_0, I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN074_0, I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN074_0, I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN074_0, I_ADDA_UL_CH4, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul_cm2_ch12_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN075_0, I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN075_0, I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN075_0, I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN075_0, I_ADDA_UL_CH4, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul_cm2_ch13_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN076_0, I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN076_0, I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN076_0, I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN076_0, I_ADDA_UL_CH4, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul_cm2_ch14_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN077_0, I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN077_0, I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN077_0, I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN077_0, I_ADDA_UL_CH4, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul_cm2_ch15_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN078_0, I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN078_0, I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN078_0, I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN078_0, I_ADDA_UL_CH4, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul_cm2_ch16_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN079_0, I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN079_0, I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN079_0, I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN079_0, I_ADDA_UL_CH4, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul_cm2_ch17_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN080_0, I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN080_0, I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN080_0, I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN080_0, I_ADDA_UL_CH4, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul_cm2_ch18_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN081_0, I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN081_0, I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN081_0, I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN081_0, I_ADDA_UL_CH4, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul_cm2_ch19_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN082_0, I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN082_0, I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN082_0, I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN082_0, I_ADDA_UL_CH4, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul_cm2_ch20_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN083_0, I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN083_0, I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN083_0, I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN083_0, I_ADDA_UL_CH4, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul_cm2_ch21_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN084_0, I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN084_0, I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN084_0, I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN084_0, I_ADDA_UL_CH4, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul_cm2_ch22_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN085_0, I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN085_0, I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN085_0, I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN085_0, I_ADDA_UL_CH4, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul_cm2_ch23_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN086_0, I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN086_0, I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN086_0, I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN086_0, I_ADDA_UL_CH4, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul_cm2_ch24_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN087_0, I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN087_0, I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN087_0, I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN087_0, I_ADDA_UL_CH4, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul_cm2_ch25_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN088_0, I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN088_0, I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN088_0, I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN088_0, I_ADDA_UL_CH4, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul_cm2_ch26_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN089_0, I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN089_0, I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN089_0, I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN089_0, I_ADDA_UL_CH4, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul_cm2_ch27_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN090_0, I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN090_0, I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN090_0, I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN090_0, I_ADDA_UL_CH4, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul_cm2_ch28_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN091_0, I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN091_0, I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN091_0, I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN091_0, I_ADDA_UL_CH4, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul_cm2_ch29_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN092_0, I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN092_0, I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN092_0, I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN092_0, I_ADDA_UL_CH4, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul_cm2_ch30_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN093_0, I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN093_0, I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN093_0, I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN093_0, I_ADDA_UL_CH4, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul_cm2_ch31_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN094_0, I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN094_0, I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN094_0, I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN094_0, I_ADDA_UL_CH4, 1, 0), +}; + +static const struct snd_kcontrol_new memif_ul_cm2_ch32_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN095_0, I_ADDA_UL_CH1, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN095_0, I_ADDA_UL_CH2, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN095_0, I_ADDA_UL_CH3, 1, 0), + SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN095_0, I_ADDA_UL_CH4, 1, 0), +}; + +static const char * const cm0_mux_map[] = { + "CM0_8CH_PATH", + "CM0_2CH_PATH", +}; + +static const char * const cm1_mux_map[] = { + "CM1_16CH_PATH", + "CM1_2CH_PATH", +}; + +static const char * const cm2_mux_map[] = { + "CM2_32CH_PATH", + "CM2_2CH_PATH", +}; + +static int cm0_mux_map_value[] = { + CM0_MUX_VUL8_8CH, + CM0_MUX_VUL8_2CH, +}; + +static int cm1_mux_map_value[] = { + CM1_MUX_VUL9_16CH, + CM1_MUX_VUL9_2CH, +}; + +static int cm2_mux_map_value[] = { + CM2_MUX_VUL10_32CH, + CM2_MUX_VUL10_2CH, +}; + +static SOC_VALUE_ENUM_SINGLE_DECL(ul_cm0_mux_map_enum, + AFE_CM0_CON0, + AFE_CM0_OUTPUT_MUX_SFT, + AFE_CM0_OUTPUT_MUX_MASK, + cm0_mux_map, + cm0_mux_map_value); +static SOC_VALUE_ENUM_SINGLE_DECL(ul_cm1_mux_map_enum, + AFE_CM1_CON0, + AFE_CM1_OUTPUT_MUX_SFT, + AFE_CM1_OUTPUT_MUX_MASK, + cm1_mux_map, + cm1_mux_map_value); +static SOC_VALUE_ENUM_SINGLE_DECL(ul_cm2_mux_map_enum, + AFE_CM2_CON0, + AFE_CM2_OUTPUT_MUX_SFT, + AFE_CM2_OUTPUT_MUX_MASK, + cm2_mux_map, + cm2_mux_map_value); + +static const struct snd_kcontrol_new ul_cm0_mux_control = + SOC_DAPM_ENUM("CM0_UL_MUX Select", ul_cm0_mux_map_enum); +static const struct snd_kcontrol_new ul_cm1_mux_control = + SOC_DAPM_ENUM("CM1_UL_MUX Select", ul_cm1_mux_map_enum); +static const struct snd_kcontrol_new ul_cm2_mux_control = + SOC_DAPM_ENUM("CM2_UL_MUX Select", ul_cm2_mux_map_enum); + +static const struct snd_soc_dapm_widget mt8196_memif_widgets[] = { + /* inter-connections */ + SND_SOC_DAPM_MIXER("UL0_CH1", SND_SOC_NOPM, 0, 0, + memif_ul0_ch1_mix, ARRAY_SIZE(memif_ul0_ch1_mix)), + SND_SOC_DAPM_MIXER("UL0_CH2", SND_SOC_NOPM, 0, 0, + memif_ul0_ch2_mix, ARRAY_SIZE(memif_ul0_ch2_mix)), + + SND_SOC_DAPM_MIXER("UL1_CH1", SND_SOC_NOPM, 0, 0, + memif_ul1_ch1_mix, ARRAY_SIZE(memif_ul1_ch1_mix)), + SND_SOC_DAPM_MIXER("UL1_CH2", SND_SOC_NOPM, 0, 0, + memif_ul1_ch2_mix, ARRAY_SIZE(memif_ul1_ch2_mix)), + + SND_SOC_DAPM_MIXER("UL2_CH1", SND_SOC_NOPM, 0, 0, + memif_ul2_ch1_mix, ARRAY_SIZE(memif_ul2_ch1_mix)), + SND_SOC_DAPM_MIXER("UL2_CH2", SND_SOC_NOPM, 0, 0, + memif_ul2_ch2_mix, ARRAY_SIZE(memif_ul2_ch2_mix)), + + SND_SOC_DAPM_MIXER("UL3_CH1", SND_SOC_NOPM, 0, 0, + memif_ul3_ch1_mix, ARRAY_SIZE(memif_ul3_ch1_mix)), + SND_SOC_DAPM_MIXER("UL3_CH2", SND_SOC_NOPM, 0, 0, + memif_ul3_ch2_mix, ARRAY_SIZE(memif_ul3_ch2_mix)), + + SND_SOC_DAPM_MIXER("UL4_CH1", SND_SOC_NOPM, 0, 0, + memif_ul4_ch1_mix, ARRAY_SIZE(memif_ul4_ch1_mix)), + SND_SOC_DAPM_MIXER("UL4_CH2", SND_SOC_NOPM, 0, 0, + memif_ul4_ch2_mix, ARRAY_SIZE(memif_ul4_ch2_mix)), + + SND_SOC_DAPM_MIXER("UL5_CH1", SND_SOC_NOPM, 0, 0, + memif_ul5_ch1_mix, ARRAY_SIZE(memif_ul5_ch1_mix)), + SND_SOC_DAPM_MIXER("UL5_CH2", SND_SOC_NOPM, 0, 0, + memif_ul5_ch2_mix, ARRAY_SIZE(memif_ul5_ch2_mix)), + + SND_SOC_DAPM_MIXER("UL6_CH1", SND_SOC_NOPM, 0, 0, + memif_ul6_ch1_mix, ARRAY_SIZE(memif_ul6_ch1_mix)), + SND_SOC_DAPM_MIXER("UL6_CH2", SND_SOC_NOPM, 0, 0, + memif_ul6_ch2_mix, ARRAY_SIZE(memif_ul6_ch2_mix)), + + SND_SOC_DAPM_MIXER("UL7_CH1", SND_SOC_NOPM, 0, 0, + memif_ul7_ch1_mix, ARRAY_SIZE(memif_ul7_ch1_mix)), + SND_SOC_DAPM_MIXER("UL7_CH2", SND_SOC_NOPM, 0, 0, + memif_ul7_ch2_mix, ARRAY_SIZE(memif_ul7_ch2_mix)), + + SND_SOC_DAPM_MIXER("UL8_CH1", SND_SOC_NOPM, 0, 0, + memif_ul8_ch1_mix, ARRAY_SIZE(memif_ul8_ch1_mix)), + SND_SOC_DAPM_MIXER("UL8_CH2", SND_SOC_NOPM, 0, 0, + memif_ul8_ch2_mix, ARRAY_SIZE(memif_ul8_ch2_mix)), + + SND_SOC_DAPM_MIXER("UL9_CH1", SND_SOC_NOPM, 0, 0, + memif_ul9_ch1_mix, ARRAY_SIZE(memif_ul9_ch1_mix)), + SND_SOC_DAPM_MIXER("UL9_CH2", SND_SOC_NOPM, 0, 0, + memif_ul9_ch2_mix, ARRAY_SIZE(memif_ul9_ch2_mix)), + + SND_SOC_DAPM_MIXER("UL10_CH1", SND_SOC_NOPM, 0, 0, + memif_ul10_ch1_mix, ARRAY_SIZE(memif_ul10_ch1_mix)), + SND_SOC_DAPM_MIXER("UL10_CH2", SND_SOC_NOPM, 0, 0, + memif_ul10_ch2_mix, ARRAY_SIZE(memif_ul10_ch2_mix)), + + SND_SOC_DAPM_MIXER("UL24_CH1", SND_SOC_NOPM, 0, 0, + memif_ul24_ch1_mix, ARRAY_SIZE(memif_ul24_ch1_mix)), + SND_SOC_DAPM_MIXER("UL24_CH2", SND_SOC_NOPM, 0, 0, + memif_ul24_ch2_mix, ARRAY_SIZE(memif_ul24_ch2_mix)), + + SND_SOC_DAPM_MIXER("UL25_CH1", SND_SOC_NOPM, 0, 0, + memif_ul25_ch1_mix, ARRAY_SIZE(memif_ul25_ch1_mix)), + SND_SOC_DAPM_MIXER("UL25_CH2", SND_SOC_NOPM, 0, 0, + memif_ul25_ch2_mix, ARRAY_SIZE(memif_ul25_ch2_mix)), + + SND_SOC_DAPM_MIXER("UL26_CH1", SND_SOC_NOPM, 0, 0, + memif_ul26_ch1_mix, ARRAY_SIZE(memif_ul26_ch1_mix)), + SND_SOC_DAPM_MIXER("UL26_CH2", SND_SOC_NOPM, 0, 0, + memif_ul26_ch2_mix, ARRAY_SIZE(memif_ul26_ch2_mix)), + + SND_SOC_DAPM_MIXER("UL_CM0_CH1", SND_SOC_NOPM, 0, 0, + memif_ul_cm0_ch1_mix, ARRAY_SIZE(memif_ul_cm0_ch1_mix)), + SND_SOC_DAPM_MIXER("UL_CM0_CH2", SND_SOC_NOPM, 0, 0, + memif_ul_cm0_ch2_mix, ARRAY_SIZE(memif_ul_cm0_ch2_mix)), + SND_SOC_DAPM_MIXER("UL_CM0_CH3", SND_SOC_NOPM, 0, 0, + memif_ul_cm0_ch3_mix, ARRAY_SIZE(memif_ul_cm0_ch3_mix)), + SND_SOC_DAPM_MIXER("UL_CM0_CH4", SND_SOC_NOPM, 0, 0, + memif_ul_cm0_ch4_mix, ARRAY_SIZE(memif_ul_cm0_ch4_mix)), + SND_SOC_DAPM_MIXER("UL_CM0_CH5", SND_SOC_NOPM, 0, 0, + memif_ul_cm0_ch5_mix, ARRAY_SIZE(memif_ul_cm0_ch5_mix)), + SND_SOC_DAPM_MIXER("UL_CM0_CH6", SND_SOC_NOPM, 0, 0, + memif_ul_cm0_ch6_mix, ARRAY_SIZE(memif_ul_cm0_ch6_mix)), + SND_SOC_DAPM_MIXER("UL_CM0_CH7", SND_SOC_NOPM, 0, 0, + memif_ul_cm0_ch7_mix, ARRAY_SIZE(memif_ul_cm0_ch7_mix)), + SND_SOC_DAPM_MIXER("UL_CM0_CH8", SND_SOC_NOPM, 0, 0, + memif_ul_cm0_ch8_mix, ARRAY_SIZE(memif_ul_cm0_ch8_mix)), + SND_SOC_DAPM_MUX_E("CM0_UL_MUX", SND_SOC_NOPM, 0, 0, + &ul_cm0_mux_control, + ul_cm0_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), + + SND_SOC_DAPM_MIXER("UL_CM1_CH1", SND_SOC_NOPM, 0, 0, + memif_ul_cm1_ch1_mix, ARRAY_SIZE(memif_ul_cm1_ch1_mix)), + SND_SOC_DAPM_MIXER("UL_CM1_CH2", SND_SOC_NOPM, 0, 0, + memif_ul_cm1_ch2_mix, ARRAY_SIZE(memif_ul_cm1_ch2_mix)), + SND_SOC_DAPM_MIXER("UL_CM1_CH3", SND_SOC_NOPM, 0, 0, + memif_ul_cm1_ch3_mix, ARRAY_SIZE(memif_ul_cm1_ch3_mix)), + SND_SOC_DAPM_MIXER("UL_CM1_CH4", SND_SOC_NOPM, 0, 0, + memif_ul_cm1_ch4_mix, ARRAY_SIZE(memif_ul_cm1_ch4_mix)), + SND_SOC_DAPM_MIXER("UL_CM1_CH5", SND_SOC_NOPM, 0, 0, + memif_ul_cm1_ch5_mix, ARRAY_SIZE(memif_ul_cm1_ch5_mix)), + SND_SOC_DAPM_MIXER("UL_CM1_CH6", SND_SOC_NOPM, 0, 0, + memif_ul_cm1_ch6_mix, ARRAY_SIZE(memif_ul_cm1_ch6_mix)), + SND_SOC_DAPM_MIXER("UL_CM1_CH7", SND_SOC_NOPM, 0, 0, + memif_ul_cm1_ch7_mix, ARRAY_SIZE(memif_ul_cm1_ch7_mix)), + SND_SOC_DAPM_MIXER("UL_CM1_CH8", SND_SOC_NOPM, 0, 0, + memif_ul_cm1_ch8_mix, ARRAY_SIZE(memif_ul_cm1_ch8_mix)), + SND_SOC_DAPM_MIXER("UL_CM1_CH9", SND_SOC_NOPM, 0, 0, + memif_ul_cm1_ch9_mix, ARRAY_SIZE(memif_ul_cm1_ch9_mix)), + SND_SOC_DAPM_MIXER("UL_CM1_CH10", SND_SOC_NOPM, 0, 0, + memif_ul_cm1_ch10_mix, ARRAY_SIZE(memif_ul_cm1_ch10_mix)), + SND_SOC_DAPM_MIXER("UL_CM1_CH11", SND_SOC_NOPM, 0, 0, + memif_ul_cm1_ch11_mix, ARRAY_SIZE(memif_ul_cm1_ch11_mix)), + SND_SOC_DAPM_MIXER("UL_CM1_CH12", SND_SOC_NOPM, 0, 0, + memif_ul_cm1_ch12_mix, ARRAY_SIZE(memif_ul_cm1_ch12_mix)), + SND_SOC_DAPM_MIXER("UL_CM1_CH13", SND_SOC_NOPM, 0, 0, + memif_ul_cm1_ch13_mix, ARRAY_SIZE(memif_ul_cm1_ch13_mix)), + SND_SOC_DAPM_MIXER("UL_CM1_CH14", SND_SOC_NOPM, 0, 0, + memif_ul_cm1_ch14_mix, ARRAY_SIZE(memif_ul_cm1_ch14_mix)), + SND_SOC_DAPM_MIXER("UL_CM1_CH15", SND_SOC_NOPM, 0, 0, + memif_ul_cm1_ch15_mix, ARRAY_SIZE(memif_ul_cm1_ch15_mix)), + SND_SOC_DAPM_MIXER("UL_CM1_CH16", SND_SOC_NOPM, 0, 0, + memif_ul_cm1_ch16_mix, ARRAY_SIZE(memif_ul_cm1_ch16_mix)), + SND_SOC_DAPM_MUX("CM1_UL_MUX", SND_SOC_NOPM, 0, 0, + &ul_cm1_mux_control), + SND_SOC_DAPM_MIXER("UL_CM2_CH1", SND_SOC_NOPM, 0, 0, + memif_ul_cm2_ch1_mix, ARRAY_SIZE(memif_ul_cm2_ch1_mix)), + SND_SOC_DAPM_MIXER("UL_CM2_CH2", SND_SOC_NOPM, 0, 0, + memif_ul_cm2_ch2_mix, ARRAY_SIZE(memif_ul_cm2_ch2_mix)), + SND_SOC_DAPM_MIXER("UL_CM2_CH3", SND_SOC_NOPM, 0, 0, + memif_ul_cm2_ch3_mix, ARRAY_SIZE(memif_ul_cm2_ch3_mix)), + SND_SOC_DAPM_MIXER("UL_CM2_CH4", SND_SOC_NOPM, 0, 0, + memif_ul_cm2_ch4_mix, ARRAY_SIZE(memif_ul_cm2_ch4_mix)), + SND_SOC_DAPM_MIXER("UL_CM2_CH5", SND_SOC_NOPM, 0, 0, + memif_ul_cm2_ch5_mix, ARRAY_SIZE(memif_ul_cm2_ch5_mix)), + SND_SOC_DAPM_MIXER("UL_CM2_CH6", SND_SOC_NOPM, 0, 0, + memif_ul_cm2_ch6_mix, ARRAY_SIZE(memif_ul_cm2_ch6_mix)), + SND_SOC_DAPM_MIXER("UL_CM2_CH7", SND_SOC_NOPM, 0, 0, + memif_ul_cm2_ch7_mix, ARRAY_SIZE(memif_ul_cm2_ch7_mix)), + SND_SOC_DAPM_MIXER("UL_CM2_CH8", SND_SOC_NOPM, 0, 0, + memif_ul_cm2_ch8_mix, ARRAY_SIZE(memif_ul_cm2_ch8_mix)), + SND_SOC_DAPM_MIXER("UL_CM2_CH9", SND_SOC_NOPM, 0, 0, + memif_ul_cm2_ch9_mix, ARRAY_SIZE(memif_ul_cm2_ch9_mix)), + SND_SOC_DAPM_MIXER("UL_CM2_CH10", SND_SOC_NOPM, 0, 0, + memif_ul_cm2_ch10_mix, ARRAY_SIZE(memif_ul_cm2_ch10_mix)), + SND_SOC_DAPM_MIXER("UL_CM2_CH11", SND_SOC_NOPM, 0, 0, + memif_ul_cm2_ch11_mix, ARRAY_SIZE(memif_ul_cm2_ch11_mix)), + SND_SOC_DAPM_MIXER("UL_CM2_CH12", SND_SOC_NOPM, 0, 0, + memif_ul_cm2_ch12_mix, ARRAY_SIZE(memif_ul_cm2_ch12_mix)), + SND_SOC_DAPM_MIXER("UL_CM2_CH13", SND_SOC_NOPM, 0, 0, + memif_ul_cm2_ch13_mix, ARRAY_SIZE(memif_ul_cm2_ch13_mix)), + SND_SOC_DAPM_MIXER("UL_CM2_CH14", SND_SOC_NOPM, 0, 0, + memif_ul_cm2_ch14_mix, ARRAY_SIZE(memif_ul_cm2_ch14_mix)), + SND_SOC_DAPM_MIXER("UL_CM2_CH15", SND_SOC_NOPM, 0, 0, + memif_ul_cm2_ch15_mix, ARRAY_SIZE(memif_ul_cm2_ch15_mix)), + SND_SOC_DAPM_MIXER("UL_CM2_CH16", SND_SOC_NOPM, 0, 0, + memif_ul_cm2_ch16_mix, ARRAY_SIZE(memif_ul_cm2_ch16_mix)), + SND_SOC_DAPM_MIXER("UL_CM2_CH17", SND_SOC_NOPM, 0, 0, + memif_ul_cm2_ch17_mix, ARRAY_SIZE(memif_ul_cm2_ch17_mix)), + SND_SOC_DAPM_MIXER("UL_CM2_CH18", SND_SOC_NOPM, 0, 0, + memif_ul_cm2_ch18_mix, ARRAY_SIZE(memif_ul_cm2_ch18_mix)), + SND_SOC_DAPM_MIXER("UL_CM2_CH19", SND_SOC_NOPM, 0, 0, + memif_ul_cm2_ch19_mix, ARRAY_SIZE(memif_ul_cm2_ch19_mix)), + SND_SOC_DAPM_MIXER("UL_CM2_CH20", SND_SOC_NOPM, 0, 0, + memif_ul_cm2_ch20_mix, ARRAY_SIZE(memif_ul_cm2_ch20_mix)), + SND_SOC_DAPM_MIXER("UL_CM2_CH21", SND_SOC_NOPM, 0, 0, + memif_ul_cm2_ch21_mix, ARRAY_SIZE(memif_ul_cm2_ch21_mix)), + SND_SOC_DAPM_MIXER("UL_CM2_CH22", SND_SOC_NOPM, 0, 0, + memif_ul_cm2_ch22_mix, ARRAY_SIZE(memif_ul_cm2_ch22_mix)), + SND_SOC_DAPM_MIXER("UL_CM2_CH23", SND_SOC_NOPM, 0, 0, + memif_ul_cm2_ch23_mix, ARRAY_SIZE(memif_ul_cm2_ch23_mix)), + SND_SOC_DAPM_MIXER("UL_CM2_CH24", SND_SOC_NOPM, 0, 0, + memif_ul_cm2_ch24_mix, ARRAY_SIZE(memif_ul_cm2_ch24_mix)), + SND_SOC_DAPM_MIXER("UL_CM2_CH25", SND_SOC_NOPM, 0, 0, + memif_ul_cm2_ch25_mix, ARRAY_SIZE(memif_ul_cm2_ch25_mix)), + SND_SOC_DAPM_MIXER("UL_CM2_CH26", SND_SOC_NOPM, 0, 0, + memif_ul_cm2_ch26_mix, ARRAY_SIZE(memif_ul_cm2_ch26_mix)), + SND_SOC_DAPM_MIXER("UL_CM2_CH27", SND_SOC_NOPM, 0, 0, + memif_ul_cm2_ch27_mix, ARRAY_SIZE(memif_ul_cm2_ch27_mix)), + SND_SOC_DAPM_MIXER("UL_CM2_CH28", SND_SOC_NOPM, 0, 0, + memif_ul_cm2_ch28_mix, ARRAY_SIZE(memif_ul_cm2_ch28_mix)), + SND_SOC_DAPM_MIXER("UL_CM2_CH29", SND_SOC_NOPM, 0, 0, + memif_ul_cm2_ch29_mix, ARRAY_SIZE(memif_ul_cm2_ch29_mix)), + SND_SOC_DAPM_MIXER("UL_CM2_CH30", SND_SOC_NOPM, 0, 0, + memif_ul_cm2_ch30_mix, ARRAY_SIZE(memif_ul_cm2_ch30_mix)), + SND_SOC_DAPM_MIXER("UL_CM2_CH31", SND_SOC_NOPM, 0, 0, + memif_ul_cm2_ch31_mix, ARRAY_SIZE(memif_ul_cm2_ch31_mix)), + SND_SOC_DAPM_MIXER("UL_CM2_CH32", SND_SOC_NOPM, 0, 0, + memif_ul_cm2_ch32_mix, ARRAY_SIZE(memif_ul_cm2_ch32_mix)), + SND_SOC_DAPM_MUX("CM2_UL_MUX", SND_SOC_NOPM, 0, 0, + &ul_cm2_mux_control), + + SND_SOC_DAPM_SUPPLY("CM0_Enable", + AFE_CM0_CON0, AFE_CM0_ON_SFT, 0, + ul_cm0_event, + SND_SOC_DAPM_PRE_PMU | + SND_SOC_DAPM_PRE_PMD), + + SND_SOC_DAPM_SUPPLY("CM1_Enable", + AFE_CM1_CON0, AFE_CM1_ON_SFT, 0, + ul_cm1_event, + SND_SOC_DAPM_PRE_PMU | + SND_SOC_DAPM_PRE_PMD), + + SND_SOC_DAPM_SUPPLY("CM2_Enable", + AFE_CM2_CON0, AFE_CM2_ON_SFT, 0, + ul_cm2_event, + SND_SOC_DAPM_PRE_PMU | + SND_SOC_DAPM_PRE_PMD), + + SND_SOC_DAPM_MIXER("SOF_DMA_UL0", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_MIXER("SOF_DMA_UL1", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_MIXER("SOF_DMA_UL2", SND_SOC_NOPM, 0, 0, NULL, 0), + + /* dynamic pinctrl */ + SND_SOC_DAPM_PINCTRL("ETDMIN_SPK_PIN", "aud-gpio-i2sin4-on", "aud-gpio-i2sin4-off"), + SND_SOC_DAPM_PINCTRL("ETDMOUT_SPK_PIN", "aud-gpio-i2sout4-on", "aud-gpio-i2sout4-off"), + SND_SOC_DAPM_PINCTRL("ETDMIN_HP_PIN", "aud-gpio-i2sin6-on", "aud-gpio-i2sin6-off"), + SND_SOC_DAPM_PINCTRL("ETDMOUT_HP_PIN", "aud-gpio-i2sout6-on", "aud-gpio-i2sout6-off"), + SND_SOC_DAPM_PINCTRL("ETDMIN_HDMI_PIN", "aud-gpio-i2sin3-on", "aud-gpio-i2sin3-off"), + SND_SOC_DAPM_PINCTRL("ETDMOUT_HDMI_PIN", "aud-gpio-i2sout3-on", "aud-gpio-i2sout3-off"), + SND_SOC_DAPM_PINCTRL("AP_DMIC0_PIN", "aud-gpio-ap-dmic-on", "aud-gpio-ap-dmic-off"), + SND_SOC_DAPM_PINCTRL("AP_DMIC1_PIN", "aud-gpio-ap-dmic1-on", "aud-gpio-ap-dmic1-off"), +}; + +static const struct snd_soc_dapm_route mt8196_memif_routes[] = { + {"UL0", NULL, "UL0_CH1"}, + {"UL0", NULL, "UL0_CH2"}, + /* Normal record */ + {"UL0_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"}, + {"UL0_CH1", "ADDA_UL_CH2", "ADDA_UL_Mux"}, + {"UL0_CH1", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"}, + {"UL0_CH1", "ADDA_UL_CH4", "ADDA_CH34_UL_Mux"}, + {"UL0_CH2", "ADDA_UL_CH1", "ADDA_UL_Mux"}, + {"UL0_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"}, + {"UL0_CH2", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"}, + {"UL0_CH2", "ADDA_UL_CH4", "ADDA_CH34_UL_Mux"}, + + {"UL0_CH1", "I2SIN0_CH1", "I2SIN0"}, + {"UL0_CH2", "I2SIN0_CH2", "I2SIN0"}, + {"UL0_CH1", "I2SIN1_CH1", "I2SIN1"}, + {"UL0_CH2", "I2SIN1_CH2", "I2SIN1"}, + + /* SOF Uplink */ + {"SOF_DMA_UL0", NULL, "UL0_CH1"}, + {"SOF_DMA_UL0", NULL, "UL0_CH2"}, + + {"UL1", NULL, "UL1_CH1"}, + {"UL1", NULL, "UL1_CH2"}, + + {"UL1_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"}, + {"UL1_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"}, + + {"UL1_CH1", "I2SIN0_CH1", "I2SIN0"}, + {"UL1_CH2", "I2SIN0_CH2", "I2SIN0"}, + {"UL1_CH1", "I2SIN1_CH1", "I2SIN1"}, + {"UL1_CH2", "I2SIN1_CH2", "I2SIN1"}, + {"UL1_CH1", "I2SIN3_CH1", "I2SIN3"}, + {"UL1_CH2", "I2SIN3_CH2", "I2SIN3"}, + {"UL1_CH1", "I2SIN4_CH1", "I2SIN4"}, + {"UL1_CH2", "I2SIN4_CH2", "I2SIN4"}, + {"UL1_CH1", "I2SIN6_CH1", "I2SIN6"}, + {"UL1_CH2", "I2SIN6_CH2", "I2SIN6"}, + + /* SOF Uplink */ + {"SOF_DMA_UL1", NULL, "UL1_CH1"}, + {"SOF_DMA_UL1", NULL, "UL1_CH2"}, + + {"UL2", NULL, "UL2_CH1"}, + {"UL2", NULL, "UL2_CH2"}, + {"UL2_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"}, + {"UL2_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"}, + {"UL2_CH1", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"}, + {"UL2_CH2", "ADDA_UL_CH1", "ADDA_UL_Mux"}, + {"UL2_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"}, + {"UL2_CH2", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"}, + {"UL2_CH2", "ADDA_UL_CH4", "ADDA_CH34_UL_Mux"}, + + /* SOF Uplink */ + {"SOF_DMA_UL2", NULL, "UL2_CH1"}, + {"SOF_DMA_UL2", NULL, "UL2_CH2"}, + + {"UL3", NULL, "UL3_CH1"}, + {"UL3", NULL, "UL3_CH2"}, + + {"UL3_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"}, + {"UL3_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"}, + {"UL3_CH1", "I2SIN0_CH1", "I2SIN0"}, + {"UL3_CH2", "I2SIN0_CH2", "I2SIN0"}, + {"UL3_CH1", "I2SIN1_CH1", "I2SIN1"}, + {"UL3_CH2", "I2SIN1_CH2", "I2SIN1"}, + {"UL3_CH1", "I2SIN3_CH1", "I2SIN3"}, + {"UL3_CH2", "I2SIN3_CH2", "I2SIN3"}, + {"UL3_CH1", "I2SIN4_CH1", "I2SIN4"}, + {"UL3_CH2", "I2SIN4_CH2", "I2SIN4"}, + + {"UL4", NULL, "UL4_CH1"}, + {"UL4", NULL, "UL4_CH2"}, + {"UL4_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"}, + {"UL4_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"}, + {"UL4_CH1", "I2SIN0_CH1", "I2SIN0"}, + {"UL4_CH2", "I2SIN0_CH2", "I2SIN0"}, + + {"UL5", NULL, "UL5_CH1"}, + {"UL5", NULL, "UL5_CH2"}, + + {"UL5_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"}, + {"UL5_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"}, + {"UL5_CH1", "I2SIN3_CH1", "I2SIN3"}, + {"UL5_CH2", "I2SIN3_CH2", "I2SIN3"}, + + {"UL6", NULL, "UL6_CH1"}, + {"UL6", NULL, "UL6_CH2"}, + {"UL6_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"}, + {"UL6_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"}, + + {"UL7", NULL, "UL7_CH1"}, + {"UL7", NULL, "UL7_CH2"}, + {"UL7_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"}, + {"UL7_CH1", "ADDA_UL_CH2", "ADDA_UL_Mux"}, + {"UL7_CH1", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"}, + {"UL7_CH2", "ADDA_UL_CH1", "ADDA_UL_Mux"}, + {"UL7_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"}, + {"UL7_CH2", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"}, + {"UL7_CH2", "ADDA_UL_CH4", "ADDA_CH34_UL_Mux"}, + + {"UL8", NULL, "CM0_UL_MUX"}, + {"CM0_UL_MUX", "CM0_2CH_PATH", "UL8_CH1"}, + {"CM0_UL_MUX", "CM0_2CH_PATH", "UL8_CH2"}, + {"CM0_UL_MUX", "CM0_8CH_PATH", "UL_CM0_CH1"}, + {"CM0_UL_MUX", "CM0_8CH_PATH", "UL_CM0_CH2"}, + {"CM0_UL_MUX", "CM0_8CH_PATH", "UL_CM0_CH3"}, + {"CM0_UL_MUX", "CM0_8CH_PATH", "UL_CM0_CH4"}, + {"CM0_UL_MUX", "CM0_8CH_PATH", "UL_CM0_CH5"}, + {"CM0_UL_MUX", "CM0_8CH_PATH", "UL_CM0_CH6"}, + {"CM0_UL_MUX", "CM0_8CH_PATH", "UL_CM0_CH7"}, + {"CM0_UL_MUX", "CM0_8CH_PATH", "UL_CM0_CH8"}, + {"UL_CM0_CH1", NULL, "CM0_Enable"}, + {"UL_CM0_CH2", NULL, "CM0_Enable"}, + {"UL_CM0_CH3", NULL, "CM0_Enable"}, + {"UL_CM0_CH4", NULL, "CM0_Enable"}, + {"UL_CM0_CH5", NULL, "CM0_Enable"}, + {"UL_CM0_CH6", NULL, "CM0_Enable"}, + {"UL_CM0_CH7", NULL, "CM0_Enable"}, + {"UL_CM0_CH8", NULL, "CM0_Enable"}, + + /* UL9 */ + {"UL9", NULL, "CM1_UL_MUX"}, + {"CM1_UL_MUX", "CM1_2CH_PATH", "UL9_CH1"}, + {"CM1_UL_MUX", "CM1_2CH_PATH", "UL9_CH2"}, + {"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH1"}, + {"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH2"}, + {"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH3"}, + {"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH4"}, + {"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH5"}, + {"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH6"}, + {"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH7"}, + {"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH8"}, + {"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH9"}, + {"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH10"}, + {"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH11"}, + {"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH12"}, + {"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH13"}, + {"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH14"}, + {"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH15"}, + {"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH16"}, + + {"UL_CM1_CH1", NULL, "CM1_Enable"}, + {"UL_CM1_CH2", NULL, "CM1_Enable"}, + {"UL_CM1_CH3", NULL, "CM1_Enable"}, + {"UL_CM1_CH4", NULL, "CM1_Enable"}, + {"UL_CM1_CH5", NULL, "CM1_Enable"}, + {"UL_CM1_CH6", NULL, "CM1_Enable"}, + {"UL_CM1_CH7", NULL, "CM1_Enable"}, + {"UL_CM1_CH8", NULL, "CM1_Enable"}, + {"UL_CM1_CH9", NULL, "CM1_Enable"}, + {"UL_CM1_CH10", NULL, "CM1_Enable"}, + {"UL_CM1_CH11", NULL, "CM1_Enable"}, + {"UL_CM1_CH12", NULL, "CM1_Enable"}, + {"UL_CM1_CH13", NULL, "CM1_Enable"}, + {"UL_CM1_CH14", NULL, "CM1_Enable"}, + {"UL_CM1_CH15", NULL, "CM1_Enable"}, + {"UL_CM1_CH16", NULL, "CM1_Enable"}, + + /* UL9 o36o37 <- ADDA */ + {"UL9_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"}, + {"UL9_CH1", "ADDA_UL_CH2", "ADDA_UL_Mux"}, + {"UL9_CH1", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"}, + {"UL9_CH2", "ADDA_UL_CH1", "ADDA_UL_Mux"}, + {"UL9_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"}, + {"UL9_CH2", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"}, + {"UL9_CH2", "ADDA_UL_CH4", "ADDA_CH34_UL_Mux"}, + + {"UL10", NULL, "CM2_UL_MUX"}, + {"CM2_UL_MUX", "CM2_2CH_PATH", "UL10_CH1"}, + {"CM2_UL_MUX", "CM2_2CH_PATH", "UL10_CH2"}, + {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH1"}, + {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH2"}, + {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH3"}, + {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH4"}, + {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH5"}, + {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH6"}, + {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH7"}, + {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH8"}, + {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH9"}, + {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH10"}, + {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH11"}, + {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH12"}, + {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH13"}, + {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH14"}, + {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH15"}, + {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH16"}, + {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH17"}, + {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH18"}, + {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH19"}, + {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH20"}, + {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH21"}, + {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH22"}, + {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH23"}, + {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH24"}, + {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH25"}, + {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH26"}, + {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH27"}, + {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH28"}, + {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH29"}, + {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH30"}, + {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH31"}, + {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH32"}, + {"UL_CM2_CH1", NULL, "CM2_Enable"}, + {"UL_CM2_CH2", NULL, "CM2_Enable"}, + {"UL_CM2_CH3", NULL, "CM2_Enable"}, + {"UL_CM2_CH4", NULL, "CM2_Enable"}, + {"UL_CM2_CH5", NULL, "CM2_Enable"}, + {"UL_CM2_CH6", NULL, "CM2_Enable"}, + {"UL_CM2_CH7", NULL, "CM2_Enable"}, + {"UL_CM2_CH8", NULL, "CM2_Enable"}, + {"UL_CM2_CH9", NULL, "CM2_Enable"}, + {"UL_CM2_CH10", NULL, "CM2_Enable"}, + {"UL_CM2_CH11", NULL, "CM2_Enable"}, + {"UL_CM2_CH12", NULL, "CM2_Enable"}, + {"UL_CM2_CH13", NULL, "CM2_Enable"}, + {"UL_CM2_CH14", NULL, "CM2_Enable"}, + {"UL_CM2_CH15", NULL, "CM2_Enable"}, + {"UL_CM2_CH16", NULL, "CM2_Enable"}, + {"UL_CM2_CH17", NULL, "CM2_Enable"}, + {"UL_CM2_CH18", NULL, "CM2_Enable"}, + {"UL_CM2_CH19", NULL, "CM2_Enable"}, + {"UL_CM2_CH20", NULL, "CM2_Enable"}, + {"UL_CM2_CH21", NULL, "CM2_Enable"}, + {"UL_CM2_CH22", NULL, "CM2_Enable"}, + {"UL_CM2_CH23", NULL, "CM2_Enable"}, + {"UL_CM2_CH24", NULL, "CM2_Enable"}, + {"UL_CM2_CH25", NULL, "CM2_Enable"}, + {"UL_CM2_CH26", NULL, "CM2_Enable"}, + {"UL_CM2_CH27", NULL, "CM2_Enable"}, + {"UL_CM2_CH28", NULL, "CM2_Enable"}, + {"UL_CM2_CH29", NULL, "CM2_Enable"}, + {"UL_CM2_CH30", NULL, "CM2_Enable"}, + {"UL_CM2_CH31", NULL, "CM2_Enable"}, + {"UL_CM2_CH32", NULL, "CM2_Enable"}, + + /* UL10 o38o39 <- ADDA */ + {"UL10_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"}, + {"UL10_CH1", "ADDA_UL_CH2", "ADDA_UL_Mux"}, + {"UL10_CH1", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"}, + {"UL10_CH2", "ADDA_UL_CH1", "ADDA_UL_Mux"}, + {"UL10_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"}, + {"UL10_CH2", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"}, + {"UL10_CH2", "ADDA_UL_CH4", "ADDA_CH34_UL_Mux"}, + + {"UL24", NULL, "UL24_CH1"}, + {"UL24", NULL, "UL24_CH2"}, + {"UL24_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"}, + {"UL24_CH1", "I2SIN6_CH1", "I2SIN6"}, + {"UL24_CH2", "I2SIN6_CH2", "I2SIN6"}, + {"UL24_CH1", "I2SIN0_CH1", "I2SIN0"}, + {"UL24_CH2", "I2SIN0_CH2", "I2SIN0"}, + + {"UL25", NULL, "UL25_CH1"}, + {"UL25", NULL, "UL25_CH2"}, + {"UL25_CH1", "I2SIN6_CH1", "I2SIN6"}, + {"UL25_CH2", "I2SIN6_CH2", "I2SIN6"}, + {"UL25_CH1", "I2SIN0_CH1", "I2SIN0"}, + {"UL25_CH2", "I2SIN0_CH2", "I2SIN0"}, + + {"UL26", NULL, "UL26_CH1"}, + {"UL26", NULL, "UL26_CH2"}, + {"UL26_CH1", "I2SIN6_CH1", "I2SIN6"}, + {"UL26_CH2", "I2SIN6_CH2", "I2SIN6"}, + {"UL26_CH1", "I2SIN0_CH1", "I2SIN0"}, + {"UL26_CH2", "I2SIN0_CH2", "I2SIN0"}, + + {"UL_CM0", NULL, "UL_CM0_CH1"}, + {"UL_CM0", NULL, "UL_CM0_CH2"}, + {"UL_CM0", NULL, "UL_CM0_CH3"}, + {"UL_CM0", NULL, "UL_CM0_CH4"}, + {"UL_CM0", NULL, "UL_CM0_CH5"}, + {"UL_CM0", NULL, "UL_CM0_CH6"}, + {"UL_CM0", NULL, "UL_CM0_CH7"}, + {"UL_CM0", NULL, "UL_CM0_CH8"}, + {"UL_CM0_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"}, + {"UL_CM0_CH1", "ADDA_UL_CH2", "ADDA_UL_Mux"}, + {"UL_CM0_CH1", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"}, + {"UL_CM0_CH1", "ADDA_UL_CH4", "ADDA_CH34_UL_Mux"}, + {"UL_CM0_CH2", "ADDA_UL_CH1", "ADDA_UL_Mux"}, + {"UL_CM0_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"}, + {"UL_CM0_CH2", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"}, + {"UL_CM0_CH2", "ADDA_UL_CH4", "ADDA_CH34_UL_Mux"}, + {"UL_CM0_CH3", "ADDA_UL_CH1", "ADDA_UL_Mux"}, + {"UL_CM0_CH3", "ADDA_UL_CH2", "ADDA_UL_Mux"}, + {"UL_CM0_CH3", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"}, + {"UL_CM0_CH3", "ADDA_UL_CH4", "ADDA_CH34_UL_Mux"}, + {"UL_CM0_CH4", "ADDA_UL_CH1", "ADDA_UL_Mux"}, + {"UL_CM0_CH4", "ADDA_UL_CH2", "ADDA_UL_Mux"}, + {"UL_CM0_CH4", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"}, + {"UL_CM0_CH4", "ADDA_UL_CH4", "ADDA_CH34_UL_Mux"}, + + {"UL_CM1", NULL, "UL_CM1_CH1"}, + {"UL_CM1", NULL, "UL_CM1_CH2"}, + {"UL_CM1", NULL, "UL_CM1_CH3"}, + {"UL_CM1", NULL, "UL_CM1_CH4"}, + {"UL_CM1", NULL, "UL_CM1_CH5"}, + {"UL_CM1", NULL, "UL_CM1_CH6"}, + {"UL_CM1", NULL, "UL_CM1_CH7"}, + {"UL_CM1", NULL, "UL_CM1_CH8"}, + {"UL_CM1", NULL, "UL_CM1_CH9"}, + {"UL_CM1", NULL, "UL_CM1_CH10"}, + {"UL_CM1", NULL, "UL_CM1_CH11"}, + {"UL_CM1", NULL, "UL_CM1_CH12"}, + {"UL_CM1", NULL, "UL_CM1_CH13"}, + {"UL_CM1", NULL, "UL_CM1_CH14"}, + {"UL_CM1", NULL, "UL_CM1_CH15"}, + {"UL_CM1", NULL, "UL_CM1_CH16"}, + {"UL_CM1_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"}, + {"UL_CM1_CH1", "ADDA_UL_CH2", "ADDA_UL_Mux"}, + {"UL_CM1_CH1", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"}, + {"UL_CM1_CH1", "ADDA_UL_CH4", "ADDA_CH34_UL_Mux"}, + {"UL_CM1_CH2", "ADDA_UL_CH1", "ADDA_UL_Mux"}, + {"UL_CM1_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"}, + {"UL_CM1_CH2", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"}, + {"UL_CM1_CH2", "ADDA_UL_CH4", "ADDA_CH34_UL_Mux"}, + {"UL_CM1_CH3", "ADDA_UL_CH1", "ADDA_UL_Mux"}, + {"UL_CM1_CH3", "ADDA_UL_CH2", "ADDA_UL_Mux"}, + {"UL_CM1_CH3", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"}, + {"UL_CM1_CH3", "ADDA_UL_CH4", "ADDA_CH34_UL_Mux"}, + {"UL_CM1_CH4", "ADDA_UL_CH1", "ADDA_UL_Mux"}, + {"UL_CM1_CH4", "ADDA_UL_CH2", "ADDA_UL_Mux"}, + {"UL_CM1_CH4", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"}, + {"UL_CM1_CH4", "ADDA_UL_CH4", "ADDA_CH34_UL_Mux"}, + {"UL_CM1_CH5", "ADDA_UL_CH1", "ADDA_UL_Mux"}, + {"UL_CM1_CH5", "ADDA_UL_CH2", "ADDA_UL_Mux"}, + {"UL_CM1_CH5", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"}, + {"UL_CM1_CH5", "ADDA_UL_CH4", "ADDA_CH34_UL_Mux"}, + {"UL_CM1_CH6", "ADDA_UL_CH1", "ADDA_UL_Mux"}, + {"UL_CM1_CH6", "ADDA_UL_CH2", "ADDA_UL_Mux"}, + {"UL_CM1_CH6", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"}, + {"UL_CM1_CH6", "ADDA_UL_CH4", "ADDA_CH34_UL_Mux"}, + + {"UL_CM2", NULL, "UL_CM2_CH1"}, + {"UL_CM2", NULL, "UL_CM2_CH2"}, + {"UL_CM2", NULL, "UL_CM2_CH3"}, + {"UL_CM2", NULL, "UL_CM2_CH4"}, + {"UL_CM2", NULL, "UL_CM2_CH5"}, + {"UL_CM2", NULL, "UL_CM2_CH6"}, + {"UL_CM2", NULL, "UL_CM2_CH7"}, + {"UL_CM2", NULL, "UL_CM2_CH8"}, + {"UL_CM2", NULL, "UL_CM2_CH9"}, + {"UL_CM2", NULL, "UL_CM2_CH10"}, + {"UL_CM2", NULL, "UL_CM2_CH11"}, + {"UL_CM2", NULL, "UL_CM2_CH12"}, + {"UL_CM2", NULL, "UL_CM2_CH13"}, + {"UL_CM2", NULL, "UL_CM2_CH14"}, + {"UL_CM2", NULL, "UL_CM2_CH15"}, + {"UL_CM2", NULL, "UL_CM2_CH16"}, + {"UL_CM2", NULL, "UL_CM2_CH17"}, + {"UL_CM2", NULL, "UL_CM2_CH18"}, + {"UL_CM2", NULL, "UL_CM2_CH19"}, + {"UL_CM2", NULL, "UL_CM2_CH20"}, + {"UL_CM2", NULL, "UL_CM2_CH21"}, + {"UL_CM2", NULL, "UL_CM2_CH22"}, + {"UL_CM2", NULL, "UL_CM2_CH23"}, + {"UL_CM2", NULL, "UL_CM2_CH24"}, + {"UL_CM2", NULL, "UL_CM2_CH25"}, + {"UL_CM2", NULL, "UL_CM2_CH26"}, + {"UL_CM2", NULL, "UL_CM2_CH27"}, + {"UL_CM2", NULL, "UL_CM2_CH28"}, + {"UL_CM2", NULL, "UL_CM2_CH29"}, + {"UL_CM2", NULL, "UL_CM2_CH30"}, + {"UL_CM2", NULL, "UL_CM2_CH31"}, + {"UL_CM2", NULL, "UL_CM2_CH32"}, + {"UL_CM2_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"}, + {"UL_CM2_CH1", "ADDA_UL_CH2", "ADDA_UL_Mux"}, + {"UL_CM2_CH1", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"}, + {"UL_CM2_CH1", "ADDA_UL_CH4", "ADDA_CH34_UL_Mux"}, + {"UL_CM2_CH2", "ADDA_UL_CH1", "ADDA_UL_Mux"}, + {"UL_CM2_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"}, + {"UL_CM2_CH2", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"}, + {"UL_CM2_CH2", "ADDA_UL_CH4", "ADDA_CH34_UL_Mux"}, + {"UL_CM2_CH3", "ADDA_UL_CH1", "ADDA_UL_Mux"}, + {"UL_CM2_CH3", "ADDA_UL_CH2", "ADDA_UL_Mux"}, + {"UL_CM2_CH3", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"}, + {"UL_CM2_CH3", "ADDA_UL_CH4", "ADDA_CH34_UL_Mux"}, + {"UL_CM2_CH4", "ADDA_UL_CH1", "ADDA_UL_Mux"}, + {"UL_CM2_CH4", "ADDA_UL_CH2", "ADDA_UL_Mux"}, + {"UL_CM2_CH4", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"}, + {"UL_CM2_CH4", "ADDA_UL_CH4", "ADDA_CH34_UL_Mux"}, + {"UL_CM2_CH5", "ADDA_UL_CH1", "ADDA_UL_Mux"}, + {"UL_CM2_CH5", "ADDA_UL_CH2", "ADDA_UL_Mux"}, + {"UL_CM2_CH5", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"}, + {"UL_CM2_CH5", "ADDA_UL_CH4", "ADDA_CH34_UL_Mux"}, + {"UL_CM2_CH6", "ADDA_UL_CH1", "ADDA_UL_Mux"}, + {"UL_CM2_CH6", "ADDA_UL_CH2", "ADDA_UL_Mux"}, + {"UL_CM2_CH6", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"}, + {"UL_CM2_CH6", "ADDA_UL_CH4", "ADDA_CH34_UL_Mux"}, +}; + +static const struct mtk_base_memif_data memif_data[MT8196_MEMIF_NUM] = { + [MT8196_MEMIF_DL0] = { + .name = "DL0", + .id = MT8196_MEMIF_DL0, + .reg_ofs_base = AFE_DL0_BASE, + .reg_ofs_cur = AFE_DL0_CUR, + .reg_ofs_end = AFE_DL0_END, + .reg_ofs_base_msb = AFE_DL0_BASE_MSB, + .reg_ofs_cur_msb = AFE_DL0_CUR_MSB, + .reg_ofs_end_msb = AFE_DL0_END_MSB, + .fs_reg = AFE_DL0_CON0, + .fs_shift = DL0_SEL_FS_SFT, + .fs_maskbit = DL0_SEL_FS_MASK, + .mono_reg = AFE_DL0_CON0, + .mono_shift = DL0_MONO_SFT, + .enable_reg = AFE_DL0_CON0, + .enable_shift = DL0_ON_SFT, + .hd_reg = AFE_DL0_CON0, + .hd_mask = DL0_HD_MODE_MASK, + .hd_shift = DL0_HD_MODE_SFT, + .hd_align_reg = AFE_DL0_CON0, + .hd_align_mshift = DL0_HALIGN_SFT, + .agent_disable_reg = -1, + .agent_disable_shift = -1, + .msb_reg = -1, + .msb_shift = -1, + .pbuf_reg = AFE_DL0_CON0, + .pbuf_mask = DL0_PBUF_SIZE_MASK, + .pbuf_shift = DL0_PBUF_SIZE_SFT, + .minlen_reg = AFE_DL0_CON0, + .minlen_mask = DL0_MINLEN_MASK, + .minlen_shift = DL0_MINLEN_SFT, + .maxlen_reg = AFE_DL0_CON0, + .maxlen_mask = DL0_MAXLEN_MASK, + .maxlen_shift = DL0_MAXLEN_SFT, + }, + [MT8196_MEMIF_DL1] = { + .name = "DL1", + .id = MT8196_MEMIF_DL1, + .reg_ofs_base = AFE_DL1_BASE, + .reg_ofs_cur = AFE_DL1_CUR, + .reg_ofs_end = AFE_DL1_END, + .reg_ofs_base_msb = AFE_DL1_BASE_MSB, + .reg_ofs_cur_msb = AFE_DL1_CUR_MSB, + .reg_ofs_end_msb = AFE_DL1_END_MSB, + .fs_reg = AFE_DL1_CON0, + .fs_shift = DL1_SEL_FS_SFT, + .fs_maskbit = DL1_SEL_FS_MASK, + .mono_reg = AFE_DL1_CON0, + .mono_shift = DL1_MONO_SFT, + .enable_reg = AFE_DL1_CON0, + .enable_shift = DL1_ON_SFT, + .hd_reg = AFE_DL1_CON0, + .hd_mask = DL1_HD_MODE_MASK, + .hd_shift = DL1_HD_MODE_SFT, + .hd_align_reg = AFE_DL1_CON0, + .hd_align_mshift = DL1_HALIGN_SFT, + .agent_disable_reg = -1, + .agent_disable_shift = -1, + .msb_reg = -1, + .msb_shift = -1, + .pbuf_reg = AFE_DL1_CON0, + .pbuf_mask = DL1_PBUF_SIZE_MASK, + .pbuf_shift = DL1_PBUF_SIZE_SFT, + .minlen_reg = AFE_DL1_CON0, + .minlen_mask = DL1_MINLEN_MASK, + .minlen_shift = DL1_MINLEN_SFT, + .maxlen_reg = AFE_DL1_CON0, + .maxlen_mask = DL1_MAXLEN_MASK, + .maxlen_shift = DL1_MAXLEN_SFT, + }, + [MT8196_MEMIF_DL2] = { + .name = "DL2", + .id = MT8196_MEMIF_DL2, + .reg_ofs_base = AFE_DL2_BASE, + .reg_ofs_cur = AFE_DL2_CUR, + .reg_ofs_end = AFE_DL2_END, + .reg_ofs_base_msb = AFE_DL2_BASE_MSB, + .reg_ofs_cur_msb = AFE_DL2_CUR_MSB, + .reg_ofs_end_msb = AFE_DL2_END_MSB, + .fs_reg = AFE_DL2_CON0, + .fs_shift = DL2_SEL_FS_SFT, + .fs_maskbit = DL2_SEL_FS_MASK, + .mono_reg = AFE_DL2_CON0, + .mono_shift = DL2_MONO_SFT, + .enable_reg = AFE_DL2_CON0, + .enable_shift = DL2_ON_SFT, + .hd_reg = AFE_DL2_CON0, + .hd_mask = DL2_HD_MODE_MASK, + .hd_shift = DL2_HD_MODE_SFT, + .hd_align_reg = AFE_DL2_CON0, + .hd_align_mshift = DL2_HALIGN_SFT, + .agent_disable_reg = -1, + .agent_disable_shift = -1, + .msb_reg = -1, + .msb_shift = -1, + .pbuf_reg = AFE_DL2_CON0, + .pbuf_mask = DL2_PBUF_SIZE_MASK, + .pbuf_shift = DL2_PBUF_SIZE_SFT, + .minlen_reg = AFE_DL2_CON0, + .minlen_mask = DL2_MINLEN_MASK, + .minlen_shift = DL2_MINLEN_SFT, + .maxlen_reg = AFE_DL2_CON0, + .maxlen_mask = DL2_MAXLEN_MASK, + .maxlen_shift = DL2_MAXLEN_SFT, + }, + [MT8196_MEMIF_DL3] = { + .name = "DL3", + .id = MT8196_MEMIF_DL3, + .reg_ofs_base = AFE_DL3_BASE, + .reg_ofs_cur = AFE_DL3_CUR, + .reg_ofs_end = AFE_DL3_END, + .reg_ofs_base_msb = AFE_DL3_BASE_MSB, + .reg_ofs_cur_msb = AFE_DL3_CUR_MSB, + .reg_ofs_end_msb = AFE_DL3_END_MSB, + .fs_reg = AFE_DL3_CON0, + .fs_shift = DL3_SEL_FS_SFT, + .fs_maskbit = DL3_SEL_FS_MASK, + .mono_reg = AFE_DL3_CON0, + .mono_shift = DL3_MONO_SFT, + .enable_reg = AFE_DL3_CON0, + .enable_shift = DL3_ON_SFT, + .hd_reg = AFE_DL3_CON0, + .hd_mask = DL3_HD_MODE_MASK, + .hd_shift = DL3_HD_MODE_SFT, + .hd_align_reg = AFE_DL3_CON0, + .hd_align_mshift = DL3_HALIGN_SFT, + .agent_disable_reg = -1, + .agent_disable_shift = -1, + .msb_reg = -1, + .msb_shift = -1, + .pbuf_reg = AFE_DL3_CON0, + .pbuf_mask = DL3_PBUF_SIZE_MASK, + .pbuf_shift = DL3_PBUF_SIZE_SFT, + .minlen_reg = AFE_DL3_CON0, + .minlen_mask = DL3_MINLEN_MASK, + .minlen_shift = DL3_MINLEN_SFT, + .maxlen_reg = AFE_DL3_CON0, + .maxlen_mask = DL3_MAXLEN_MASK, + .maxlen_shift = DL3_MAXLEN_SFT, + }, + [MT8196_MEMIF_DL4] = { + .name = "DL4", + .id = MT8196_MEMIF_DL4, + .reg_ofs_base = AFE_DL4_BASE, + .reg_ofs_cur = AFE_DL4_CUR, + .reg_ofs_end = AFE_DL4_END, + .reg_ofs_base_msb = AFE_DL4_BASE_MSB, + .reg_ofs_cur_msb = AFE_DL4_CUR_MSB, + .reg_ofs_end_msb = AFE_DL4_END_MSB, + .fs_reg = AFE_DL4_CON0, + .fs_shift = DL4_SEL_FS_SFT, + .fs_maskbit = DL4_SEL_FS_MASK, + .mono_reg = AFE_DL4_CON0, + .mono_shift = DL4_MONO_SFT, + .enable_reg = AFE_DL4_CON0, + .enable_shift = DL4_ON_SFT, + .hd_reg = AFE_DL4_CON0, + .hd_mask = DL4_HD_MODE_MASK, + .hd_shift = DL4_HD_MODE_SFT, + .hd_align_reg = AFE_DL4_CON0, + .hd_align_mshift = DL4_HALIGN_SFT, + .agent_disable_reg = -1, + .agent_disable_shift = -1, + .msb_reg = -1, + .msb_shift = -1, + .pbuf_reg = AFE_DL4_CON0, + .pbuf_mask = DL4_PBUF_SIZE_MASK, + .pbuf_shift = DL4_PBUF_SIZE_SFT, + .minlen_reg = AFE_DL4_CON0, + .minlen_mask = DL4_MINLEN_MASK, + .minlen_shift = DL4_MINLEN_SFT, + .maxlen_reg = AFE_DL4_CON0, + .maxlen_mask = DL4_MAXLEN_MASK, + .maxlen_shift = DL4_MAXLEN_SFT, + }, + [MT8196_MEMIF_DL5] = { + .name = "DL5", + .id = MT8196_MEMIF_DL5, + .reg_ofs_base = AFE_DL5_BASE, + .reg_ofs_cur = AFE_DL5_CUR, + .reg_ofs_end = AFE_DL5_END, + .reg_ofs_base_msb = AFE_DL5_BASE_MSB, + .reg_ofs_cur_msb = AFE_DL5_CUR_MSB, + .reg_ofs_end_msb = AFE_DL5_END_MSB, + .fs_reg = AFE_DL5_CON0, + .fs_shift = DL5_SEL_FS_SFT, + .fs_maskbit = DL5_SEL_FS_MASK, + .mono_reg = AFE_DL5_CON0, + .mono_shift = DL5_MONO_SFT, + .enable_reg = AFE_DL5_CON0, + .enable_shift = DL5_ON_SFT, + .hd_reg = AFE_DL5_CON0, + .hd_mask = DL5_HD_MODE_MASK, + .hd_shift = DL5_HD_MODE_SFT, + .hd_align_reg = AFE_DL5_CON0, + .hd_align_mshift = DL5_HALIGN_SFT, + .agent_disable_reg = -1, + .agent_disable_shift = -1, + .msb_reg = -1, + .msb_shift = -1, + .pbuf_reg = AFE_DL5_CON0, + .pbuf_mask = DL5_PBUF_SIZE_MASK, + .pbuf_shift = DL5_PBUF_SIZE_SFT, + .minlen_reg = AFE_DL5_CON0, + .minlen_mask = DL5_MINLEN_MASK, + .minlen_shift = DL5_MINLEN_SFT, + .maxlen_reg = AFE_DL5_CON0, + .maxlen_mask = DL5_MAXLEN_MASK, + .maxlen_shift = DL5_MAXLEN_SFT, + }, + [MT8196_MEMIF_DL6] = { + .name = "DL6", + .id = MT8196_MEMIF_DL6, + .reg_ofs_base = AFE_DL6_BASE, + .reg_ofs_cur = AFE_DL6_CUR, + .reg_ofs_end = AFE_DL6_END, + .reg_ofs_base_msb = AFE_DL6_BASE_MSB, + .reg_ofs_cur_msb = AFE_DL6_CUR_MSB, + .reg_ofs_end_msb = AFE_DL6_END_MSB, + .fs_reg = AFE_DL6_CON0, + .fs_shift = DL6_SEL_FS_SFT, + .fs_maskbit = DL6_SEL_FS_MASK, + .mono_reg = AFE_DL6_CON0, + .mono_shift = DL6_MONO_SFT, + .enable_reg = AFE_DL6_CON0, + .enable_shift = DL6_ON_SFT, + .hd_reg = AFE_DL6_CON0, + .hd_mask = DL6_HD_MODE_MASK, + .hd_shift = DL6_HD_MODE_SFT, + .hd_align_reg = AFE_DL6_CON0, + .hd_align_mshift = DL6_HALIGN_SFT, + .agent_disable_reg = -1, + .agent_disable_shift = -1, + .msb_reg = -1, + .msb_shift = -1, + .pbuf_reg = AFE_DL6_CON0, + .pbuf_mask = DL6_PBUF_SIZE_MASK, + .pbuf_shift = DL6_PBUF_SIZE_SFT, + .minlen_reg = AFE_DL6_CON0, + .minlen_mask = DL6_MINLEN_MASK, + .minlen_shift = DL6_MINLEN_SFT, + .maxlen_reg = AFE_DL6_CON0, + .maxlen_mask = DL6_MAXLEN_MASK, + .maxlen_shift = DL6_MAXLEN_SFT, + }, + [MT8196_MEMIF_DL7] = { + .name = "DL7", + .id = MT8196_MEMIF_DL7, + .reg_ofs_base = AFE_DL7_BASE, + .reg_ofs_cur = AFE_DL7_CUR, + .reg_ofs_end = AFE_DL7_END, + .reg_ofs_base_msb = AFE_DL7_BASE_MSB, + .reg_ofs_cur_msb = AFE_DL7_CUR_MSB, + .reg_ofs_end_msb = AFE_DL7_END_MSB, + .fs_reg = AFE_DL7_CON0, + .fs_shift = DL7_SEL_FS_SFT, + .fs_maskbit = DL7_SEL_FS_MASK, + .mono_reg = AFE_DL7_CON0, + .mono_shift = DL7_MONO_SFT, + .enable_reg = AFE_DL7_CON0, + .enable_shift = DL7_ON_SFT, + .hd_reg = AFE_DL7_CON0, + .hd_mask = DL7_HD_MODE_MASK, + .hd_shift = DL7_HD_MODE_SFT, + .hd_align_reg = AFE_DL7_CON0, + .hd_align_mshift = DL7_HALIGN_SFT, + .agent_disable_reg = -1, + .agent_disable_shift = -1, + .msb_reg = -1, + .msb_shift = -1, + .pbuf_reg = AFE_DL7_CON0, + .pbuf_mask = DL7_PBUF_SIZE_MASK, + .pbuf_shift = DL7_PBUF_SIZE_SFT, + .minlen_reg = AFE_DL7_CON0, + .minlen_mask = DL7_MINLEN_MASK, + .minlen_shift = DL7_MINLEN_SFT, + .maxlen_reg = AFE_DL7_CON0, + .maxlen_mask = DL7_MAXLEN_MASK, + .maxlen_shift = DL7_MAXLEN_SFT, + }, + [MT8196_MEMIF_DL8] = { + .name = "DL8", + .id = MT8196_MEMIF_DL8, + .reg_ofs_base = AFE_DL8_BASE, + .reg_ofs_cur = AFE_DL8_CUR, + .reg_ofs_end = AFE_DL8_END, + .reg_ofs_base_msb = AFE_DL8_BASE_MSB, + .reg_ofs_cur_msb = AFE_DL8_CUR_MSB, + .reg_ofs_end_msb = AFE_DL8_END_MSB, + .fs_reg = AFE_DL8_CON0, + .fs_shift = DL8_SEL_FS_SFT, + .fs_maskbit = DL8_SEL_FS_MASK, + .mono_reg = AFE_DL8_CON0, + .mono_shift = DL8_MONO_SFT, + .enable_reg = AFE_DL8_CON0, + .enable_shift = DL8_ON_SFT, + .hd_reg = AFE_DL8_CON0, + .hd_mask = DL8_HD_MODE_MASK, + .hd_shift = DL8_HD_MODE_SFT, + .hd_align_reg = AFE_DL8_CON0, + .hd_align_mshift = DL8_HALIGN_SFT, + .agent_disable_reg = -1, + .agent_disable_shift = -1, + .msb_reg = -1, + .msb_shift = -1, + .pbuf_reg = AFE_DL8_CON0, + .pbuf_mask = DL8_PBUF_SIZE_MASK, + .pbuf_shift = DL8_PBUF_SIZE_SFT, + .minlen_reg = AFE_DL8_CON0, + .minlen_mask = DL8_MINLEN_MASK, + .minlen_shift = DL8_MINLEN_SFT, + .maxlen_reg = AFE_DL8_CON0, + .maxlen_mask = DL8_MAXLEN_MASK, + .maxlen_shift = DL8_MAXLEN_SFT, + }, + [MT8196_MEMIF_DL23] = { + .name = "DL23", + .id = MT8196_MEMIF_DL23, + .reg_ofs_base = AFE_DL23_BASE, + .reg_ofs_cur = AFE_DL23_CUR, + .reg_ofs_end = AFE_DL23_END, + .reg_ofs_base_msb = AFE_DL23_BASE_MSB, + .reg_ofs_cur_msb = AFE_DL23_CUR_MSB, + .reg_ofs_end_msb = AFE_DL23_END_MSB, + .fs_reg = AFE_DL23_CON0, + .fs_shift = DL23_SEL_FS_SFT, + .fs_maskbit = DL23_SEL_FS_MASK, + .mono_reg = AFE_DL23_CON0, + .mono_shift = DL23_MONO_SFT, + .enable_reg = AFE_DL23_CON0, + .enable_shift = DL23_ON_SFT, + .hd_reg = AFE_DL23_CON0, + .hd_mask = DL23_HD_MODE_MASK, + .hd_shift = DL23_HD_MODE_SFT, + .hd_align_reg = AFE_DL23_CON0, + .hd_align_mshift = DL23_HALIGN_SFT, + .agent_disable_reg = -1, + .agent_disable_shift = -1, + .msb_reg = -1, + .msb_shift = -1, + .pbuf_reg = AFE_DL23_CON0, + .pbuf_mask = DL23_PBUF_SIZE_MASK, + .pbuf_shift = DL23_PBUF_SIZE_SFT, + .minlen_reg = AFE_DL23_CON0, + .minlen_mask = DL23_MINLEN_MASK, + .minlen_shift = DL23_MINLEN_SFT, + .maxlen_reg = AFE_DL23_CON0, + .maxlen_mask = DL23_MAXLEN_MASK, + .maxlen_shift = DL23_MAXLEN_SFT, + }, + [MT8196_MEMIF_DL24] = { + .name = "DL24", + .id = MT8196_MEMIF_DL24, + .reg_ofs_base = AFE_DL24_BASE, + .reg_ofs_cur = AFE_DL24_CUR, + .reg_ofs_end = AFE_DL24_END, + .reg_ofs_base_msb = AFE_DL24_BASE_MSB, + .reg_ofs_cur_msb = AFE_DL24_CUR_MSB, + .reg_ofs_end_msb = AFE_DL24_END_MSB, + .fs_reg = AFE_DL24_CON0, + .fs_shift = DL24_SEL_FS_SFT, + .fs_maskbit = DL24_SEL_FS_MASK, + .mono_reg = AFE_DL24_CON0, + .mono_shift = DL24_MONO_SFT, + .enable_reg = AFE_DL24_CON0, + .enable_shift = DL24_ON_SFT, + .hd_reg = AFE_DL24_CON0, + .hd_mask = DL24_HD_MODE_MASK, + .hd_shift = DL24_HD_MODE_SFT, + .hd_align_reg = AFE_DL24_CON0, + .hd_align_mshift = DL24_HALIGN_SFT, + .agent_disable_reg = -1, + .agent_disable_shift = -1, + .msb_reg = -1, + .msb_shift = -1, + .pbuf_reg = AFE_DL24_CON0, + .pbuf_mask = DL24_PBUF_SIZE_MASK, + .pbuf_shift = DL24_PBUF_SIZE_SFT, + .minlen_reg = AFE_DL24_CON0, + .minlen_mask = DL24_MINLEN_MASK, + .minlen_shift = DL24_MINLEN_SFT, + .maxlen_reg = AFE_DL24_CON0, + .maxlen_mask = DL24_MAXLEN_MASK, + .maxlen_shift = DL24_MAXLEN_SFT, + }, + [MT8196_MEMIF_DL25] = { + .name = "DL25", + .id = MT8196_MEMIF_DL25, + .reg_ofs_base = AFE_DL25_BASE, + .reg_ofs_cur = AFE_DL25_CUR, + .reg_ofs_end = AFE_DL25_END, + .reg_ofs_base_msb = AFE_DL25_BASE_MSB, + .reg_ofs_cur_msb = AFE_DL25_CUR_MSB, + .reg_ofs_end_msb = AFE_DL25_END_MSB, + .fs_reg = AFE_DL25_CON0, + .fs_shift = DL25_SEL_FS_SFT, + .fs_maskbit = DL25_SEL_FS_MASK, + .mono_reg = AFE_DL25_CON0, + .mono_shift = DL25_MONO_SFT, + .enable_reg = AFE_DL25_CON0, + .enable_shift = DL25_ON_SFT, + .hd_reg = AFE_DL25_CON0, + .hd_mask = DL25_HD_MODE_MASK, + .hd_shift = DL25_HD_MODE_SFT, + .hd_align_reg = AFE_DL25_CON0, + .hd_align_mshift = DL25_HALIGN_SFT, + .agent_disable_reg = -1, + .agent_disable_shift = -1, + .msb_reg = -1, + .msb_shift = -1, + .pbuf_reg = AFE_DL25_CON0, + .pbuf_mask = DL25_PBUF_SIZE_MASK, + .pbuf_shift = DL25_PBUF_SIZE_SFT, + .minlen_reg = AFE_DL25_CON0, + .minlen_mask = DL25_MINLEN_MASK, + .minlen_shift = DL25_MINLEN_SFT, + .maxlen_reg = AFE_DL25_CON0, + .maxlen_mask = DL25_MAXLEN_MASK, + .maxlen_shift = DL25_MAXLEN_SFT, + }, + [MT8196_MEMIF_DL26] = { + .name = "DL26", + .id = MT8196_MEMIF_DL26, + .reg_ofs_base = AFE_DL26_BASE, + .reg_ofs_cur = AFE_DL26_CUR, + .reg_ofs_end = AFE_DL26_END, + .reg_ofs_base_msb = AFE_DL26_BASE_MSB, + .reg_ofs_cur_msb = AFE_DL26_CUR_MSB, + .reg_ofs_end_msb = AFE_DL26_END_MSB, + .fs_reg = AFE_DL26_CON0, + .fs_shift = DL26_SEL_FS_SFT, + .fs_maskbit = DL26_SEL_FS_MASK, + .mono_reg = AFE_DL26_CON0, + .mono_shift = DL26_MONO_SFT, + .enable_reg = AFE_DL26_CON0, + .enable_shift = DL26_ON_SFT, + .hd_reg = AFE_DL26_CON0, + .hd_mask = DL26_HD_MODE_MASK, + .hd_shift = DL26_HD_MODE_SFT, + .hd_align_reg = AFE_DL26_CON0, + .hd_align_mshift = DL26_HALIGN_SFT, + .agent_disable_reg = -1, + .agent_disable_shift = -1, + .msb_reg = -1, + .msb_shift = -1, + .pbuf_reg = AFE_DL26_CON0, + .pbuf_mask = DL26_PBUF_SIZE_MASK, + .pbuf_shift = DL26_PBUF_SIZE_SFT, + .minlen_reg = AFE_DL26_CON0, + .minlen_mask = DL26_MINLEN_MASK, + .minlen_shift = DL26_MINLEN_SFT, + .maxlen_reg = AFE_DL26_CON0, + .maxlen_mask = DL26_MAXLEN_MASK, + .maxlen_shift = DL26_MAXLEN_SFT, + }, + [MT8196_MEMIF_DL_4CH] = { + .name = "DL_4CH", + .id = MT8196_MEMIF_DL_4CH, + .reg_ofs_base = AFE_DL_4CH_BASE, + .reg_ofs_cur = AFE_DL_4CH_CUR, + .reg_ofs_end = AFE_DL_4CH_END, + .reg_ofs_base_msb = AFE_DL_4CH_BASE_MSB, + .reg_ofs_cur_msb = AFE_DL_4CH_CUR_MSB, + .reg_ofs_end_msb = AFE_DL_4CH_END_MSB, + .fs_reg = AFE_DL_4CH_CON0, + .fs_shift = DL_4CH_SEL_FS_SFT, + .fs_maskbit = DL_4CH_SEL_FS_MASK, + .mono_reg = -1, + .mono_shift = -1, + .enable_reg = AFE_DL_4CH_CON0, + .enable_shift = DL_4CH_ON_SFT, + .hd_reg = AFE_DL_4CH_CON0, + .hd_mask = DL_4CH_HD_MODE_MASK, + .hd_shift = DL_4CH_HD_MODE_SFT, + .hd_align_reg = AFE_DL_4CH_CON0, + .hd_align_mshift = DL_4CH_HALIGN_SFT, + .agent_disable_reg = -1, + .agent_disable_shift = -1, + .msb_reg = -1, + .msb_shift = -1, + .pbuf_reg = AFE_DL_4CH_CON0, + .pbuf_mask = DL_4CH_PBUF_SIZE_MASK, + .pbuf_shift = DL_4CH_PBUF_SIZE_SFT, + .minlen_reg = AFE_DL_4CH_CON0, + .minlen_mask = DL_4CH_MINLEN_MASK, + .minlen_shift = DL_4CH_MINLEN_SFT, + .maxlen_reg = AFE_DL_4CH_CON0, + .maxlen_mask = DL_4CH_MAXLEN_MASK, + .maxlen_shift = DL_4CH_MAXLEN_SFT, + .ch_num_reg = AFE_DL_4CH_CON0, + .ch_num_maskbit = DL_4CH_NUM_MASK, + .ch_num_shift = DL_4CH_NUM_SFT, + }, + [MT8196_MEMIF_DL_24CH] = { + .name = "DL_24CH", + .id = MT8196_MEMIF_DL_24CH, + .reg_ofs_base = AFE_DL_24CH_BASE, + .reg_ofs_cur = AFE_DL_24CH_CUR, + .reg_ofs_end = AFE_DL_24CH_END, + .reg_ofs_base_msb = AFE_DL_24CH_BASE_MSB, + .reg_ofs_cur_msb = AFE_DL_24CH_CUR_MSB, + .reg_ofs_end_msb = AFE_DL_24CH_END_MSB, + .fs_reg = AFE_DL_24CH_CON0, + .fs_shift = DL_24CH_SEL_FS_SFT, + .fs_maskbit = DL_24CH_SEL_FS_MASK, + .mono_reg = -1, + .mono_shift = -1, + .enable_reg = AFE_DL_24CH_CON0, + .enable_shift = DL_24CH_ON_SFT, + .hd_reg = AFE_DL_24CH_CON0, + .hd_mask = DL_24CH_HD_MODE_MASK, + .hd_shift = DL_24CH_HD_MODE_SFT, + .hd_align_reg = AFE_DL_24CH_CON0, + .hd_align_mshift = DL_24CH_HALIGN_SFT, + .agent_disable_reg = -1, + .agent_disable_shift = -1, + .msb_reg = -1, + .msb_shift = -1, + .pbuf_reg = AFE_DL_24CH_CON0, + .pbuf_mask = DL_24CH_PBUF_SIZE_MASK, + .pbuf_shift = DL_24CH_PBUF_SIZE_SFT, + .minlen_reg = AFE_DL_24CH_CON0, + .minlen_mask = DL_24CH_MINLEN_MASK, + .minlen_shift = DL_24CH_MINLEN_SFT, + .maxlen_reg = AFE_DL_24CH_CON0, + .maxlen_mask = DL_24CH_MAXLEN_MASK, + .maxlen_shift = DL_24CH_MAXLEN_SFT, + .ch_num_reg = AFE_DL_24CH_CON0, + .ch_num_maskbit = DL_24CH_NUM_MASK, + .ch_num_shift = DL_24CH_NUM_SFT, + }, + [MT8196_MEMIF_VUL0] = { + .name = "VUL0", + .id = MT8196_MEMIF_VUL0, + .reg_ofs_base = AFE_VUL0_BASE, + .reg_ofs_cur = AFE_VUL0_CUR, + .reg_ofs_end = AFE_VUL0_END, + .reg_ofs_base_msb = AFE_VUL0_BASE_MSB, + .reg_ofs_cur_msb = AFE_VUL0_CUR_MSB, + .reg_ofs_end_msb = AFE_VUL0_END_MSB, + .fs_reg = AFE_VUL0_CON0, + .fs_shift = VUL0_SEL_FS_SFT, + .fs_maskbit = VUL0_SEL_FS_MASK, + .mono_reg = AFE_VUL0_CON0, + .mono_shift = VUL0_MONO_SFT, + .enable_reg = AFE_VUL0_CON0, + .enable_shift = VUL0_ON_SFT, + .hd_reg = AFE_VUL0_CON0, + .hd_mask = VUL0_HD_MODE_MASK, + .hd_shift = VUL0_HD_MODE_SFT, + .hd_align_reg = AFE_VUL0_CON0, + .hd_align_mshift = VUL0_HALIGN_SFT, + .agent_disable_reg = -1, + .agent_disable_shift = -1, + .msb_reg = -1, + .msb_shift = -1, + }, + [MT8196_MEMIF_VUL1] = { + .name = "VUL1", + .id = MT8196_MEMIF_VUL1, + .reg_ofs_base = AFE_VUL1_BASE, + .reg_ofs_cur = AFE_VUL1_CUR, + .reg_ofs_end = AFE_VUL1_END, + .reg_ofs_base_msb = AFE_VUL1_BASE_MSB, + .reg_ofs_cur_msb = AFE_VUL1_CUR_MSB, + .reg_ofs_end_msb = AFE_VUL1_END_MSB, + .fs_reg = AFE_VUL1_CON0, + .fs_shift = VUL1_SEL_FS_SFT, + .fs_maskbit = VUL1_SEL_FS_MASK, + .mono_reg = AFE_VUL1_CON0, + .mono_shift = VUL1_MONO_SFT, + .enable_reg = AFE_VUL1_CON0, + .enable_shift = VUL1_ON_SFT, + .hd_reg = AFE_VUL1_CON0, + .hd_mask = VUL1_HD_MODE_MASK, + .hd_shift = VUL1_HD_MODE_SFT, + .hd_align_reg = AFE_VUL1_CON0, + .hd_align_mshift = VUL1_HALIGN_SFT, + .agent_disable_reg = -1, + .agent_disable_shift = -1, + .msb_reg = -1, + .msb_shift = -1, + }, + [MT8196_MEMIF_VUL2] = { + .name = "VUL2", + .id = MT8196_MEMIF_VUL2, + .reg_ofs_base = AFE_VUL2_BASE, + .reg_ofs_cur = AFE_VUL2_CUR, + .reg_ofs_end = AFE_VUL2_END, + .reg_ofs_base_msb = AFE_VUL2_BASE_MSB, + .reg_ofs_cur_msb = AFE_VUL2_CUR_MSB, + .reg_ofs_end_msb = AFE_VUL2_END_MSB, + .fs_reg = AFE_VUL2_CON0, + .fs_shift = VUL2_SEL_FS_SFT, + .fs_maskbit = VUL2_SEL_FS_MASK, + .mono_reg = AFE_VUL2_CON0, + .mono_shift = VUL2_MONO_SFT, + .enable_reg = AFE_VUL2_CON0, + .enable_shift = VUL2_ON_SFT, + .hd_reg = AFE_VUL2_CON0, + .hd_mask = VUL2_HD_MODE_MASK, + .hd_shift = VUL2_HD_MODE_SFT, + .hd_align_reg = AFE_VUL2_CON0, + .hd_align_mshift = VUL2_HALIGN_SFT, + .agent_disable_reg = -1, + .agent_disable_shift = -1, + .msb_reg = -1, + .msb_shift = -1, + }, + [MT8196_MEMIF_VUL3] = { + .name = "VUL3", + .id = MT8196_MEMIF_VUL3, + .reg_ofs_base = AFE_VUL3_BASE, + .reg_ofs_cur = AFE_VUL3_CUR, + .reg_ofs_end = AFE_VUL3_END, + .reg_ofs_base_msb = AFE_VUL3_BASE_MSB, + .reg_ofs_cur_msb = AFE_VUL3_CUR_MSB, + .reg_ofs_end_msb = AFE_VUL3_END_MSB, + .fs_reg = AFE_VUL3_CON0, + .fs_shift = VUL3_SEL_FS_SFT, + .fs_maskbit = VUL3_SEL_FS_MASK, + .mono_reg = AFE_VUL3_CON0, + .mono_shift = VUL3_MONO_SFT, + .enable_reg = AFE_VUL3_CON0, + .enable_shift = VUL3_ON_SFT, + .hd_reg = AFE_VUL3_CON0, + .hd_mask = VUL3_HD_MODE_MASK, + .hd_shift = VUL3_HD_MODE_SFT, + .hd_align_reg = AFE_VUL3_CON0, + .hd_align_mshift = VUL3_HALIGN_SFT, + .agent_disable_reg = -1, + .agent_disable_shift = -1, + .msb_reg = -1, + .msb_shift = -1, + }, + [MT8196_MEMIF_VUL4] = { + .name = "VUL4", + .id = MT8196_MEMIF_VUL4, + .reg_ofs_base = AFE_VUL4_BASE, + .reg_ofs_cur = AFE_VUL4_CUR, + .reg_ofs_end = AFE_VUL4_END, + .reg_ofs_base_msb = AFE_VUL4_BASE_MSB, + .reg_ofs_cur_msb = AFE_VUL4_CUR_MSB, + .reg_ofs_end_msb = AFE_VUL4_END_MSB, + .fs_reg = AFE_VUL4_CON0, + .fs_shift = VUL4_SEL_FS_SFT, + .fs_maskbit = VUL4_SEL_FS_MASK, + .mono_reg = AFE_VUL4_CON0, + .mono_shift = VUL4_MONO_SFT, + .enable_reg = AFE_VUL4_CON0, + .enable_shift = VUL4_ON_SFT, + .hd_reg = AFE_VUL4_CON0, + .hd_mask = VUL4_HD_MODE_MASK, + .hd_shift = VUL4_HD_MODE_SFT, + .hd_align_reg = AFE_VUL4_CON0, + .hd_align_mshift = VUL4_HALIGN_SFT, + .agent_disable_reg = -1, + .agent_disable_shift = -1, + .msb_reg = -1, + .msb_shift = -1, + }, + [MT8196_MEMIF_VUL5] = { + .name = "VUL5", + .id = MT8196_MEMIF_VUL5, + .reg_ofs_base = AFE_VUL5_BASE, + .reg_ofs_cur = AFE_VUL5_CUR, + .reg_ofs_end = AFE_VUL5_END, + .reg_ofs_base_msb = AFE_VUL5_BASE_MSB, + .reg_ofs_cur_msb = AFE_VUL5_CUR_MSB, + .reg_ofs_end_msb = AFE_VUL5_END_MSB, + .fs_reg = AFE_VUL5_CON0, + .fs_shift = VUL5_SEL_FS_SFT, + .fs_maskbit = VUL5_SEL_FS_MASK, + .mono_reg = AFE_VUL5_CON0, + .mono_shift = VUL5_MONO_SFT, + .enable_reg = AFE_VUL5_CON0, + .enable_shift = VUL5_ON_SFT, + .hd_reg = AFE_VUL5_CON0, + .hd_mask = VUL5_HD_MODE_MASK, + .hd_shift = VUL5_HD_MODE_SFT, + .hd_align_reg = AFE_VUL5_CON0, + .hd_align_mshift = VUL5_HALIGN_SFT, + .agent_disable_reg = -1, + .agent_disable_shift = -1, + .msb_reg = -1, + .msb_shift = -1, + }, + [MT8196_MEMIF_VUL6] = { + .name = "VUL6", + .id = MT8196_MEMIF_VUL6, + .reg_ofs_base = AFE_VUL6_BASE, + .reg_ofs_cur = AFE_VUL6_CUR, + .reg_ofs_end = AFE_VUL6_END, + .reg_ofs_base_msb = AFE_VUL6_BASE_MSB, + .reg_ofs_cur_msb = AFE_VUL6_CUR_MSB, + .reg_ofs_end_msb = AFE_VUL6_END_MSB, + .fs_reg = AFE_VUL6_CON0, + .fs_shift = VUL6_SEL_FS_SFT, + .fs_maskbit = VUL6_SEL_FS_MASK, + .mono_reg = AFE_VUL6_CON0, + .mono_shift = VUL6_MONO_SFT, + .enable_reg = AFE_VUL6_CON0, + .enable_shift = VUL6_ON_SFT, + .hd_reg = AFE_VUL6_CON0, + .hd_mask = VUL6_HD_MODE_MASK, + .hd_shift = VUL6_HD_MODE_SFT, + .hd_align_reg = AFE_VUL6_CON0, + .hd_align_mshift = VUL6_HALIGN_SFT, + .agent_disable_reg = -1, + .agent_disable_shift = -1, + .msb_reg = -1, + .msb_shift = -1, + }, + [MT8196_MEMIF_VUL7] = { + .name = "VUL7", + .id = MT8196_MEMIF_VUL7, + .reg_ofs_base = AFE_VUL7_BASE, + .reg_ofs_cur = AFE_VUL7_CUR, + .reg_ofs_end = AFE_VUL7_END, + .reg_ofs_base_msb = AFE_VUL7_BASE_MSB, + .reg_ofs_cur_msb = AFE_VUL7_CUR_MSB, + .reg_ofs_end_msb = AFE_VUL7_END_MSB, + .fs_reg = AFE_VUL7_CON0, + .fs_shift = VUL7_SEL_FS_SFT, + .fs_maskbit = VUL7_SEL_FS_MASK, + .mono_reg = AFE_VUL7_CON0, + .mono_shift = VUL7_MONO_SFT, + .enable_reg = AFE_VUL7_CON0, + .enable_shift = VUL7_ON_SFT, + .hd_reg = AFE_VUL7_CON0, + .hd_mask = VUL7_HD_MODE_MASK, + .hd_shift = VUL7_HD_MODE_SFT, + .hd_align_reg = AFE_VUL7_CON0, + .hd_align_mshift = VUL7_HALIGN_SFT, + .agent_disable_reg = -1, + .agent_disable_shift = -1, + .msb_reg = -1, + .msb_shift = -1, + }, + [MT8196_MEMIF_VUL8] = { + .name = "VUL8", + .id = MT8196_MEMIF_VUL8, + .reg_ofs_base = AFE_VUL8_BASE, + .reg_ofs_cur = AFE_VUL8_CUR, + .reg_ofs_end = AFE_VUL8_END, + .reg_ofs_base_msb = AFE_VUL8_BASE_MSB, + .reg_ofs_cur_msb = AFE_VUL8_CUR_MSB, + .reg_ofs_end_msb = AFE_VUL8_END_MSB, + .fs_reg = AFE_VUL8_CON0, + .fs_shift = VUL8_SEL_FS_SFT, + .fs_maskbit = VUL8_SEL_FS_MASK, + .mono_reg = AFE_VUL8_CON0, + .mono_shift = VUL8_MONO_SFT, + .enable_reg = AFE_VUL8_CON0, + .enable_shift = VUL8_ON_SFT, + .hd_reg = AFE_VUL8_CON0, + .hd_mask = VUL8_HD_MODE_MASK, + .hd_shift = VUL8_HD_MODE_SFT, + .hd_align_reg = AFE_VUL8_CON0, + .hd_align_mshift = VUL8_HALIGN_SFT, + .agent_disable_reg = -1, + .agent_disable_shift = -1, + .msb_reg = -1, + .msb_shift = -1, + }, + [MT8196_MEMIF_VUL9] = { + .name = "VUL9", + .id = MT8196_MEMIF_VUL9, + .reg_ofs_base = AFE_VUL9_BASE, + .reg_ofs_cur = AFE_VUL9_CUR, + .reg_ofs_end = AFE_VUL9_END, + .reg_ofs_base_msb = AFE_VUL9_BASE_MSB, + .reg_ofs_cur_msb = AFE_VUL9_CUR_MSB, + .reg_ofs_end_msb = AFE_VUL9_END_MSB, + .fs_reg = AFE_VUL9_CON0, + .fs_shift = VUL9_SEL_FS_SFT, + .fs_maskbit = VUL9_SEL_FS_MASK, + .mono_reg = AFE_VUL9_CON0, + .mono_shift = VUL9_MONO_SFT, + .enable_reg = AFE_VUL9_CON0, + .enable_shift = VUL9_ON_SFT, + .hd_reg = AFE_VUL9_CON0, + .hd_mask = VUL9_HD_MODE_MASK, + .hd_shift = VUL9_HD_MODE_SFT, + .hd_align_reg = AFE_VUL9_CON0, + .hd_align_mshift = VUL9_HALIGN_SFT, + .agent_disable_reg = -1, + .agent_disable_shift = -1, + .msb_reg = -1, + .msb_shift = -1, + }, + [MT8196_MEMIF_VUL10] = { + .name = "VUL10", + .id = MT8196_MEMIF_VUL10, + .reg_ofs_base = AFE_VUL10_BASE, + .reg_ofs_cur = AFE_VUL10_CUR, + .reg_ofs_end = AFE_VUL10_END, + .reg_ofs_base_msb = AFE_VUL10_BASE_MSB, + .reg_ofs_cur_msb = AFE_VUL10_CUR_MSB, + .reg_ofs_end_msb = AFE_VUL10_END_MSB, + .fs_reg = AFE_VUL10_CON0, + .fs_shift = VUL10_SEL_FS_SFT, + .fs_maskbit = VUL10_SEL_FS_MASK, + .mono_reg = AFE_VUL10_CON0, + .mono_shift = VUL10_MONO_SFT, + .enable_reg = AFE_VUL10_CON0, + .enable_shift = VUL10_ON_SFT, + .hd_reg = AFE_VUL10_CON0, + .hd_mask = VUL10_HD_MODE_MASK, + .hd_shift = VUL10_HD_MODE_SFT, + .hd_align_reg = AFE_VUL10_CON0, + .hd_align_mshift = VUL10_HALIGN_SFT, + .agent_disable_reg = -1, + .agent_disable_shift = -1, + .msb_reg = -1, + .msb_shift = -1, + }, + [MT8196_MEMIF_VUL24] = { + .name = "VUL24", + .id = MT8196_MEMIF_VUL24, + .reg_ofs_base = AFE_VUL24_BASE, + .reg_ofs_cur = AFE_VUL24_CUR, + .reg_ofs_end = AFE_VUL24_END, + .reg_ofs_base_msb = AFE_VUL24_BASE_MSB, + .reg_ofs_cur_msb = AFE_VUL24_CUR_MSB, + .reg_ofs_end_msb = AFE_VUL24_END_MSB, + .fs_reg = AFE_VUL24_CON0, + .fs_shift = VUL24_SEL_FS_SFT, + .fs_maskbit = VUL24_SEL_FS_MASK, + .mono_reg = AFE_VUL24_CON0, + .mono_shift = VUL24_MONO_SFT, + .enable_reg = AFE_VUL24_CON0, + .enable_shift = VUL24_ON_SFT, + .hd_reg = AFE_VUL24_CON0, + .hd_mask = VUL24_HD_MODE_MASK, + .hd_shift = VUL24_HD_MODE_SFT, + .hd_align_reg = AFE_VUL24_CON0, + .hd_align_mshift = VUL24_HALIGN_SFT, + .agent_disable_reg = -1, + .agent_disable_shift = -1, + .msb_reg = -1, + .msb_shift = -1, + .out_on_use_reg = AFE_VUL24_CON0, + .out_on_use_mask = OUT_ON_USE_VUL24_MASK, + .out_on_use_shift = OUT_ON_USE_VUL24_SFT, + }, + [MT8196_MEMIF_VUL25] = { + .name = "VUL25", + .id = MT8196_MEMIF_VUL25, + .reg_ofs_base = AFE_VUL25_BASE, + .reg_ofs_cur = AFE_VUL25_CUR, + .reg_ofs_end = AFE_VUL25_END, + .reg_ofs_base_msb = AFE_VUL25_BASE_MSB, + .reg_ofs_cur_msb = AFE_VUL25_CUR_MSB, + .reg_ofs_end_msb = AFE_VUL25_END_MSB, + .fs_reg = AFE_VUL25_CON0, + .fs_shift = VUL25_SEL_FS_SFT, + .fs_maskbit = VUL25_SEL_FS_MASK, + .mono_reg = AFE_VUL25_CON0, + .mono_shift = VUL25_MONO_SFT, + .enable_reg = AFE_VUL25_CON0, + .enable_shift = VUL25_ON_SFT, + .hd_reg = AFE_VUL25_CON0, + .hd_mask = VUL25_HD_MODE_MASK, + .hd_shift = VUL25_HD_MODE_SFT, + .hd_align_reg = AFE_VUL25_CON0, + .hd_align_mshift = VUL25_HALIGN_SFT, + .agent_disable_reg = -1, + .agent_disable_shift = -1, + .msb_reg = -1, + .msb_shift = -1, + .out_on_use_reg = AFE_VUL25_CON0, + .out_on_use_mask = OUT_ON_USE_VUL25_MASK, + .out_on_use_shift = OUT_ON_USE_VUL25_SFT, + }, + [MT8196_MEMIF_VUL26] = { + .name = "VUL26", + .id = MT8196_MEMIF_VUL26, + .reg_ofs_base = AFE_VUL26_BASE, + .reg_ofs_cur = AFE_VUL26_CUR, + .reg_ofs_end = AFE_VUL26_END, + .reg_ofs_base_msb = AFE_VUL26_BASE_MSB, + .reg_ofs_cur_msb = AFE_VUL26_CUR_MSB, + .reg_ofs_end_msb = AFE_VUL26_END_MSB, + .fs_reg = AFE_VUL26_CON0, + .fs_shift = VUL26_SEL_FS_SFT, + .fs_maskbit = VUL26_SEL_FS_MASK, + .mono_reg = AFE_VUL26_CON0, + .mono_shift = VUL26_MONO_SFT, + .enable_reg = AFE_VUL26_CON0, + .enable_shift = VUL26_ON_SFT, + .hd_reg = AFE_VUL26_CON0, + .hd_mask = VUL26_HD_MODE_MASK, + .hd_shift = VUL26_HD_MODE_SFT, + .hd_align_reg = AFE_VUL26_CON0, + .hd_align_mshift = VUL26_HALIGN_SFT, + .agent_disable_reg = -1, + .agent_disable_shift = -1, + .msb_reg = -1, + .msb_shift = -1, + .out_on_use_reg = AFE_VUL26_CON0, + .out_on_use_mask = OUT_ON_USE_VUL26_MASK, + .out_on_use_shift = OUT_ON_USE_VUL26_SFT, + }, + [MT8196_MEMIF_VUL_CM0] = { + .name = "VUL_CM0", + .id = MT8196_MEMIF_VUL_CM0, + .reg_ofs_base = AFE_VUL_CM0_BASE, + .reg_ofs_cur = AFE_VUL_CM0_CUR, + .reg_ofs_end = AFE_VUL_CM0_END, + .reg_ofs_base_msb = AFE_VUL_CM0_BASE_MSB, + .reg_ofs_cur_msb = AFE_VUL_CM0_CUR_MSB, + .reg_ofs_end_msb = AFE_VUL_CM0_END_MSB, + .enable_reg = AFE_VUL_CM0_CON0, + .enable_shift = VUL_CM0_ON_SFT, + .hd_reg = AFE_VUL_CM0_CON0, + .hd_mask = VUL_CM0_HD_MODE_MASK, + .hd_shift = VUL_CM0_HD_MODE_SFT, + .hd_align_reg = AFE_VUL_CM0_CON0, + .hd_align_mshift = VUL_CM0_HALIGN_SFT, + .agent_disable_reg = -1, + .agent_disable_shift = -1, + .msb_reg = -1, + .msb_shift = -1, + }, + [MT8196_MEMIF_VUL_CM1] = { + .name = "VUL_CM1", + .id = MT8196_MEMIF_VUL_CM1, + .reg_ofs_base = AFE_VUL_CM1_BASE, + .reg_ofs_cur = AFE_VUL_CM1_CUR, + .reg_ofs_end = AFE_VUL_CM1_END, + .reg_ofs_base_msb = AFE_VUL_CM1_BASE_MSB, + .reg_ofs_cur_msb = AFE_VUL_CM1_CUR_MSB, + .reg_ofs_end_msb = AFE_VUL_CM1_END_MSB, + .enable_reg = AFE_VUL_CM1_CON0, + .enable_shift = VUL_CM1_ON_SFT, + .hd_reg = AFE_VUL_CM1_CON0, + .hd_mask = VUL_CM1_HD_MODE_MASK, + .hd_shift = VUL_CM1_HD_MODE_SFT, + .hd_align_reg = AFE_VUL_CM1_CON0, + .hd_align_mshift = VUL_CM1_HALIGN_SFT, + .agent_disable_reg = -1, + .agent_disable_shift = -1, + .msb_reg = -1, + .msb_shift = -1, + }, + [MT8196_MEMIF_VUL_CM2] = { + .name = "VUL_CM2", + .id = MT8196_MEMIF_VUL_CM2, + .reg_ofs_base = AFE_VUL_CM2_BASE, + .reg_ofs_cur = AFE_VUL_CM2_CUR, + .reg_ofs_end = AFE_VUL_CM2_END, + .reg_ofs_base_msb = AFE_VUL_CM2_BASE_MSB, + .reg_ofs_cur_msb = AFE_VUL_CM2_CUR_MSB, + .reg_ofs_end_msb = AFE_VUL_CM2_END_MSB, + .enable_reg = AFE_VUL_CM2_CON0, + .enable_shift = VUL_CM2_ON_SFT, + .hd_reg = AFE_VUL_CM2_CON0, + .hd_mask = VUL_CM2_HD_MODE_MASK, + .hd_shift = VUL_CM2_HD_MODE_SFT, + .hd_align_reg = AFE_VUL_CM2_CON0, + .hd_align_mshift = VUL_CM2_HALIGN_SFT, + .agent_disable_reg = -1, + .agent_disable_shift = -1, + .msb_reg = -1, + .msb_shift = -1, + }, + [MT8196_MEMIF_ETDM_IN0] = { + .name = "ETDM_IN0", + .id = MT8196_MEMIF_ETDM_IN0, + .reg_ofs_base = AFE_ETDM_IN0_BASE, + .reg_ofs_cur = AFE_ETDM_IN0_CUR, + .reg_ofs_end = AFE_ETDM_IN0_END, + .reg_ofs_base_msb = AFE_ETDM_IN0_BASE_MSB, + .reg_ofs_cur_msb = AFE_ETDM_IN0_CUR_MSB, + .reg_ofs_end_msb = AFE_ETDM_IN0_END_MSB, + .fs_reg = ETDM_IN0_CON3, + .fs_shift = REG_FS_TIMING_SEL_SFT, + .fs_maskbit = REG_FS_TIMING_SEL_MASK, + .enable_reg = AFE_ETDM_IN0_CON0, + .enable_shift = ETDM_IN0_ON_SFT, + .hd_reg = AFE_ETDM_IN0_CON0, + .hd_mask = ETDM_IN0_HD_MODE_MASK, + .hd_shift = ETDM_IN0_HD_MODE_SFT, + .hd_align_reg = AFE_ETDM_IN0_CON0, + .hd_align_mshift = ETDM_IN0_HALIGN_SFT, + .hd_msb_shift = -1, + .agent_disable_reg = -1, + .agent_disable_shift = -1, + .msb_reg = -1, + .msb_shift = -1, + }, + [MT8196_MEMIF_ETDM_IN1] = { + .name = "ETDM_IN1", + .id = MT8196_MEMIF_ETDM_IN1, + .reg_ofs_base = AFE_ETDM_IN1_BASE, + .reg_ofs_cur = AFE_ETDM_IN1_CUR, + .reg_ofs_end = AFE_ETDM_IN1_END, + .reg_ofs_base_msb = AFE_ETDM_IN1_BASE_MSB, + .reg_ofs_cur_msb = AFE_ETDM_IN1_CUR_MSB, + .reg_ofs_end_msb = AFE_ETDM_IN1_END_MSB, + .fs_reg = ETDM_IN1_CON3, + .fs_shift = REG_FS_TIMING_SEL_SFT, + .fs_maskbit = REG_FS_TIMING_SEL_MASK, + .enable_reg = AFE_ETDM_IN1_CON0, + .enable_shift = ETDM_IN1_ON_SFT, + .hd_reg = AFE_ETDM_IN1_CON0, + .hd_mask = ETDM_IN1_HD_MODE_MASK, + .hd_shift = ETDM_IN1_HD_MODE_SFT, + .hd_align_reg = AFE_ETDM_IN1_CON0, + .hd_align_mshift = ETDM_IN1_HALIGN_SFT, + .hd_msb_shift = -1, + .agent_disable_reg = -1, + .agent_disable_shift = -1, + .msb_reg = -1, + .msb_shift = -1, + }, + [MT8196_MEMIF_ETDM_IN2] = { + .name = "ETDM_IN2", + .id = MT8196_MEMIF_ETDM_IN2, + .reg_ofs_base = AFE_ETDM_IN2_BASE, + .reg_ofs_cur = AFE_ETDM_IN2_CUR, + .reg_ofs_end = AFE_ETDM_IN2_END, + .reg_ofs_base_msb = AFE_ETDM_IN2_BASE_MSB, + .reg_ofs_cur_msb = AFE_ETDM_IN2_CUR_MSB, + .reg_ofs_end_msb = AFE_ETDM_IN2_END_MSB, + .fs_reg = ETDM_IN2_CON3, + .fs_shift = REG_FS_TIMING_SEL_SFT, + .fs_maskbit = REG_FS_TIMING_SEL_MASK, + .enable_reg = AFE_ETDM_IN2_CON0, + .enable_shift = ETDM_IN2_ON_SFT, + .hd_reg = AFE_ETDM_IN2_CON0, + .hd_mask = ETDM_IN2_HD_MODE_MASK, + .hd_shift = ETDM_IN2_HD_MODE_SFT, + .hd_align_reg = AFE_ETDM_IN2_CON0, + .hd_align_mshift = ETDM_IN2_HALIGN_SFT, + .hd_msb_shift = -1, + .agent_disable_reg = -1, + .agent_disable_shift = -1, + .msb_reg = -1, + .msb_shift = -1, + }, + [MT8196_MEMIF_ETDM_IN3] = { + .name = "ETDM_IN3", + .id = MT8196_MEMIF_ETDM_IN3, + .reg_ofs_base = AFE_ETDM_IN3_BASE, + .reg_ofs_cur = AFE_ETDM_IN3_CUR, + .reg_ofs_end = AFE_ETDM_IN3_END, + .reg_ofs_base_msb = AFE_ETDM_IN3_BASE_MSB, + .reg_ofs_cur_msb = AFE_ETDM_IN3_CUR_MSB, + .reg_ofs_end_msb = AFE_ETDM_IN3_END_MSB, + .fs_reg = ETDM_IN3_CON3, + .fs_shift = REG_FS_TIMING_SEL_SFT, + .fs_maskbit = REG_FS_TIMING_SEL_MASK, + .enable_reg = AFE_ETDM_IN3_CON0, + .enable_shift = ETDM_IN3_ON_SFT, + .hd_reg = AFE_ETDM_IN3_CON0, + .hd_mask = ETDM_IN3_HD_MODE_MASK, + .hd_shift = ETDM_IN3_HD_MODE_SFT, + .hd_align_reg = AFE_ETDM_IN3_CON0, + .hd_align_mshift = ETDM_IN3_HALIGN_SFT, + .hd_msb_shift = -1, + .agent_disable_reg = -1, + .agent_disable_shift = -1, + .msb_reg = -1, + .msb_shift = -1, + }, + [MT8196_MEMIF_ETDM_IN4] = { + .name = "ETDM_IN4", + .id = MT8196_MEMIF_ETDM_IN4, + .reg_ofs_base = AFE_ETDM_IN4_BASE, + .reg_ofs_cur = AFE_ETDM_IN4_CUR, + .reg_ofs_end = AFE_ETDM_IN4_END, + .reg_ofs_base_msb = AFE_ETDM_IN4_BASE_MSB, + .reg_ofs_cur_msb = AFE_ETDM_IN4_CUR_MSB, + .reg_ofs_end_msb = AFE_ETDM_IN4_END_MSB, + .fs_reg = ETDM_IN4_CON3, + .fs_shift = REG_FS_TIMING_SEL_SFT, + .fs_maskbit = REG_FS_TIMING_SEL_MASK, + .enable_reg = AFE_ETDM_IN4_CON0, + .enable_shift = ETDM_IN4_ON_SFT, + .hd_reg = AFE_ETDM_IN4_CON0, + .hd_mask = ETDM_IN4_HD_MODE_MASK, + .hd_shift = ETDM_IN4_HD_MODE_SFT, + .hd_align_reg = AFE_ETDM_IN4_CON0, + .hd_align_mshift = ETDM_IN4_HALIGN_SFT, + .hd_msb_shift = -1, + .agent_disable_reg = -1, + .agent_disable_shift = -1, + .msb_reg = -1, + .msb_shift = -1, + }, + [MT8196_MEMIF_ETDM_IN6] = { + .name = "ETDM_IN6", + .id = MT8196_MEMIF_ETDM_IN6, + .reg_ofs_base = AFE_ETDM_IN6_BASE, + .reg_ofs_cur = AFE_ETDM_IN6_CUR, + .reg_ofs_end = AFE_ETDM_IN6_END, + .reg_ofs_base_msb = AFE_ETDM_IN6_BASE_MSB, + .reg_ofs_cur_msb = AFE_ETDM_IN6_CUR_MSB, + .reg_ofs_end_msb = AFE_ETDM_IN6_END_MSB, + .fs_reg = ETDM_IN6_CON3, + .fs_shift = REG_FS_TIMING_SEL_SFT, + .fs_maskbit = REG_FS_TIMING_SEL_MASK, + .enable_reg = AFE_ETDM_IN6_CON0, + .enable_shift = ETDM_IN6_ON_SFT, + .hd_reg = AFE_ETDM_IN6_CON0, + .hd_mask = ETDM_IN6_HD_MODE_MASK, + .hd_shift = ETDM_IN6_HD_MODE_SFT, + .hd_align_reg = AFE_ETDM_IN6_CON0, + .hd_align_mshift = ETDM_IN6_HALIGN_SFT, + .hd_msb_shift = -1, + .agent_disable_reg = -1, + .agent_disable_shift = -1, + .msb_reg = -1, + .msb_shift = -1, + }, + [MT8196_MEMIF_HDMI] = { + .name = "HDMI", + .id = MT8196_MEMIF_HDMI, + .reg_ofs_base = AFE_HDMI_OUT_BASE, + .reg_ofs_cur = AFE_HDMI_OUT_CUR, + .reg_ofs_end = AFE_HDMI_OUT_END, + .reg_ofs_base_msb = AFE_HDMI_OUT_BASE_MSB, + .reg_ofs_cur_msb = AFE_HDMI_OUT_CUR_MSB, + .reg_ofs_end_msb = AFE_HDMI_OUT_END_MSB, + .fs_reg = -1, + .fs_shift = -1, + .fs_maskbit = -1, + .mono_reg = -1, + .mono_shift = -1, + .enable_reg = AFE_HDMI_OUT_CON0, + .enable_shift = HDMI_OUT_ON_SFT, + .hd_reg = AFE_HDMI_OUT_CON0, + .hd_mask = HDMI_OUT_HD_MODE_MASK, + .hd_shift = HDMI_OUT_HD_MODE_SFT, + .hd_align_reg = AFE_HDMI_OUT_CON0, + .hd_align_mshift = HDMI_OUT_HALIGN_SFT, + .hd_msb_shift = -1, + .agent_disable_reg = -1, + .agent_disable_shift = -1, + .msb_reg = -1, + .msb_shift = -1, + .pbuf_reg = AFE_HDMI_OUT_CON0, + .pbuf_mask = HDMI_OUT_PBUF_SIZE_MASK, + .pbuf_shift = HDMI_OUT_PBUF_SIZE_SFT, + .minlen_reg = AFE_HDMI_OUT_CON0, + .minlen_mask = HDMI_OUT_MINLEN_MASK, + .minlen_shift = HDMI_OUT_MINLEN_SFT, + }, +}; + +static const struct mtk_base_irq_data irq_data[MT8196_IRQ_NUM] = { + [MT8196_IRQ_0] = { + .id = MT8196_IRQ_0, + .irq_cnt_reg = AFE_IRQ0_MCU_CFG1, + .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, + .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, + .irq_fs_reg = AFE_IRQ0_MCU_CFG0, + .irq_fs_shift = AFE_IRQ0_MCU_FS_SFT, + .irq_fs_maskbit = AFE_IRQ0_MCU_FS_MASK, + .irq_en_reg = AFE_IRQ0_MCU_CFG0, + .irq_en_shift = AFE_IRQ0_MCU_ON_SFT, + .irq_clr_reg = AFE_IRQ0_MCU_CFG1, + .irq_clr_shift = AFE_IRQ0_CLR_CFG_SFT, + .irq_ap_en_reg = AFE_IRQ_MCU_EN, + .irq_scp_en_reg = AFE_IRQ_MCU_SCP_EN, + .irq_scp_en_shift = IRQ0_MCU_SCP_EN_SFT, + }, + [MT8196_IRQ_1] = { + .id = MT8196_IRQ_1, + .irq_cnt_reg = AFE_IRQ1_MCU_CFG1, + .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, + .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, + .irq_fs_reg = AFE_IRQ1_MCU_CFG0, + .irq_fs_shift = AFE_IRQ1_MCU_FS_SFT, + .irq_fs_maskbit = AFE_IRQ1_MCU_FS_MASK, + .irq_en_reg = AFE_IRQ1_MCU_CFG0, + .irq_en_shift = AFE_IRQ1_MCU_ON_SFT, + .irq_clr_reg = AFE_IRQ1_MCU_CFG1, + .irq_clr_shift = AFE_IRQ1_CLR_CFG_SFT, + .irq_ap_en_reg = AFE_IRQ_MCU_EN, + .irq_scp_en_reg = AFE_IRQ_MCU_SCP_EN, + .irq_scp_en_shift = IRQ1_MCU_SCP_EN_SFT, + }, + [MT8196_IRQ_2] = { + .id = MT8196_IRQ_2, + .irq_cnt_reg = AFE_IRQ2_MCU_CFG1, + .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, + .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, + .irq_fs_reg = AFE_IRQ2_MCU_CFG0, + .irq_fs_shift = AFE_IRQ2_MCU_FS_SFT, + .irq_fs_maskbit = AFE_IRQ2_MCU_FS_MASK, + .irq_en_reg = AFE_IRQ2_MCU_CFG0, + .irq_en_shift = AFE_IRQ2_MCU_ON_SFT, + .irq_clr_reg = AFE_IRQ2_MCU_CFG1, + .irq_clr_shift = AFE_IRQ2_CLR_CFG_SFT, + .irq_ap_en_reg = AFE_IRQ_MCU_EN, + .irq_scp_en_reg = AFE_IRQ_MCU_SCP_EN, + .irq_scp_en_shift = IRQ2_MCU_SCP_EN_SFT, + }, + [MT8196_IRQ_3] = { + .id = MT8196_IRQ_3, + .irq_cnt_reg = AFE_IRQ3_MCU_CFG1, + .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, + .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, + .irq_fs_reg = AFE_IRQ3_MCU_CFG0, + .irq_fs_shift = AFE_IRQ3_MCU_FS_SFT, + .irq_fs_maskbit = AFE_IRQ3_MCU_FS_MASK, + .irq_en_reg = AFE_IRQ3_MCU_CFG0, + .irq_en_shift = AFE_IRQ3_MCU_ON_SFT, + .irq_clr_reg = AFE_IRQ3_MCU_CFG1, + .irq_clr_shift = AFE_IRQ3_CLR_CFG_SFT, + .irq_ap_en_reg = AFE_IRQ_MCU_EN, + .irq_scp_en_reg = AFE_IRQ_MCU_SCP_EN, + .irq_scp_en_shift = IRQ3_MCU_SCP_EN_SFT, + }, + [MT8196_IRQ_4] = { + .id = MT8196_IRQ_4, + .irq_cnt_reg = AFE_IRQ4_MCU_CFG1, + .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, + .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, + .irq_fs_reg = AFE_IRQ4_MCU_CFG0, + .irq_fs_shift = AFE_IRQ4_MCU_FS_SFT, + .irq_fs_maskbit = AFE_IRQ4_MCU_FS_MASK, + .irq_en_reg = AFE_IRQ4_MCU_CFG0, + .irq_en_shift = AFE_IRQ4_MCU_ON_SFT, + .irq_clr_reg = AFE_IRQ4_MCU_CFG1, + .irq_clr_shift = AFE_IRQ4_CLR_CFG_SFT, + .irq_ap_en_reg = AFE_IRQ_MCU_EN, + .irq_scp_en_reg = AFE_IRQ_MCU_SCP_EN, + .irq_scp_en_shift = IRQ4_MCU_SCP_EN_SFT, + }, + [MT8196_IRQ_5] = { + .id = MT8196_IRQ_5, + .irq_cnt_reg = AFE_IRQ5_MCU_CFG1, + .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, + .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, + .irq_fs_reg = AFE_IRQ5_MCU_CFG0, + .irq_fs_shift = AFE_IRQ5_MCU_FS_SFT, + .irq_fs_maskbit = AFE_IRQ5_MCU_FS_MASK, + .irq_en_reg = AFE_IRQ5_MCU_CFG0, + .irq_en_shift = AFE_IRQ5_MCU_ON_SFT, + .irq_clr_reg = AFE_IRQ5_MCU_CFG1, + .irq_clr_shift = AFE_IRQ5_CLR_CFG_SFT, + .irq_ap_en_reg = AFE_IRQ_MCU_EN, + .irq_scp_en_reg = AFE_IRQ_MCU_SCP_EN, + .irq_scp_en_shift = IRQ5_MCU_SCP_EN_SFT, + }, + [MT8196_IRQ_6] = { + .id = MT8196_IRQ_6, + .irq_cnt_reg = AFE_IRQ6_MCU_CFG1, + .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, + .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, + .irq_fs_reg = AFE_IRQ6_MCU_CFG0, + .irq_fs_shift = AFE_IRQ6_MCU_FS_SFT, + .irq_fs_maskbit = AFE_IRQ6_MCU_FS_MASK, + .irq_en_reg = AFE_IRQ6_MCU_CFG0, + .irq_en_shift = AFE_IRQ6_MCU_ON_SFT, + .irq_clr_reg = AFE_IRQ6_MCU_CFG1, + .irq_clr_shift = AFE_IRQ6_CLR_CFG_SFT, + .irq_ap_en_reg = AFE_IRQ_MCU_EN, + .irq_scp_en_reg = AFE_IRQ_MCU_SCP_EN, + .irq_scp_en_shift = IRQ6_MCU_SCP_EN_SFT, + }, + [MT8196_IRQ_7] = { + .id = MT8196_IRQ_7, + .irq_cnt_reg = AFE_IRQ7_MCU_CFG1, + .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, + .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, + .irq_fs_reg = AFE_IRQ7_MCU_CFG0, + .irq_fs_shift = AFE_IRQ7_MCU_FS_SFT, + .irq_fs_maskbit = AFE_IRQ7_MCU_FS_MASK, + .irq_en_reg = AFE_IRQ7_MCU_CFG0, + .irq_en_shift = AFE_IRQ7_MCU_ON_SFT, + .irq_clr_reg = AFE_IRQ7_MCU_CFG1, + .irq_clr_shift = AFE_IRQ7_CLR_CFG_SFT, + .irq_ap_en_reg = AFE_IRQ_MCU_EN, + .irq_scp_en_reg = AFE_IRQ_MCU_SCP_EN, + .irq_scp_en_shift = IRQ7_MCU_SCP_EN_SFT, + }, + [MT8196_IRQ_8] = { + .id = MT8196_IRQ_8, + .irq_cnt_reg = AFE_IRQ8_MCU_CFG1, + .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, + .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, + .irq_fs_reg = AFE_IRQ8_MCU_CFG0, + .irq_fs_shift = AFE_IRQ8_MCU_FS_SFT, + .irq_fs_maskbit = AFE_IRQ8_MCU_FS_MASK, + .irq_en_reg = AFE_IRQ8_MCU_CFG0, + .irq_en_shift = AFE_IRQ8_MCU_ON_SFT, + .irq_clr_reg = AFE_IRQ8_MCU_CFG1, + .irq_clr_shift = AFE_IRQ8_CLR_CFG_SFT, + .irq_ap_en_reg = AFE_IRQ_MCU_EN, + .irq_scp_en_reg = AFE_IRQ_MCU_SCP_EN, + .irq_scp_en_shift = IRQ8_MCU_SCP_EN_SFT, + }, + [MT8196_IRQ_9] = { + .id = MT8196_IRQ_9, + .irq_cnt_reg = AFE_IRQ9_MCU_CFG1, + .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, + .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, + .irq_fs_reg = AFE_IRQ9_MCU_CFG0, + .irq_fs_shift = AFE_IRQ9_MCU_FS_SFT, + .irq_fs_maskbit = AFE_IRQ9_MCU_FS_MASK, + .irq_en_reg = AFE_IRQ9_MCU_CFG0, + .irq_en_shift = AFE_IRQ9_MCU_ON_SFT, + .irq_clr_reg = AFE_IRQ9_MCU_CFG1, + .irq_clr_shift = AFE_IRQ9_CLR_CFG_SFT, + .irq_ap_en_reg = AFE_IRQ_MCU_EN, + .irq_scp_en_reg = AFE_IRQ_MCU_SCP_EN, + .irq_scp_en_shift = IRQ9_MCU_SCP_EN_SFT, + }, + [MT8196_IRQ_10] = { + .id = MT8196_IRQ_10, + .irq_cnt_reg = AFE_IRQ10_MCU_CFG1, + .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, + .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, + .irq_fs_reg = AFE_IRQ10_MCU_CFG0, + .irq_fs_shift = AFE_IRQ10_MCU_FS_SFT, + .irq_fs_maskbit = AFE_IRQ10_MCU_FS_MASK, + .irq_en_reg = AFE_IRQ10_MCU_CFG0, + .irq_en_shift = AFE_IRQ10_MCU_ON_SFT, + .irq_clr_reg = AFE_IRQ10_MCU_CFG1, + .irq_clr_shift = AFE_IRQ10_CLR_CFG_SFT, + .irq_ap_en_reg = AFE_IRQ_MCU_EN, + .irq_scp_en_reg = AFE_IRQ_MCU_SCP_EN, + .irq_scp_en_shift = IRQ10_MCU_SCP_EN_SFT, + }, + [MT8196_IRQ_11] = { + .id = MT8196_IRQ_11, + .irq_cnt_reg = AFE_IRQ11_MCU_CFG1, + .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, + .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, + .irq_fs_reg = AFE_IRQ11_MCU_CFG0, + .irq_fs_shift = AFE_IRQ11_MCU_FS_SFT, + .irq_fs_maskbit = AFE_IRQ11_MCU_FS_MASK, + .irq_en_reg = AFE_IRQ11_MCU_CFG0, + .irq_en_shift = AFE_IRQ11_MCU_ON_SFT, + .irq_clr_reg = AFE_IRQ11_MCU_CFG1, + .irq_clr_shift = AFE_IRQ11_CLR_CFG_SFT, + .irq_ap_en_reg = AFE_IRQ_MCU_EN, + .irq_scp_en_reg = AFE_IRQ_MCU_SCP_EN, + .irq_scp_en_shift = IRQ11_MCU_SCP_EN_SFT, + }, + [MT8196_IRQ_12] = { + .id = MT8196_IRQ_12, + .irq_cnt_reg = AFE_IRQ12_MCU_CFG1, + .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, + .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, + .irq_fs_reg = AFE_IRQ12_MCU_CFG0, + .irq_fs_shift = AFE_IRQ12_MCU_FS_SFT, + .irq_fs_maskbit = AFE_IRQ12_MCU_FS_MASK, + .irq_en_reg = AFE_IRQ12_MCU_CFG0, + .irq_en_shift = AFE_IRQ12_MCU_ON_SFT, + .irq_clr_reg = AFE_IRQ12_MCU_CFG1, + .irq_clr_shift = AFE_IRQ12_CLR_CFG_SFT, + .irq_ap_en_reg = AFE_IRQ_MCU_EN, + .irq_scp_en_reg = AFE_IRQ_MCU_SCP_EN, + .irq_scp_en_shift = IRQ12_MCU_SCP_EN_SFT, + }, + [MT8196_IRQ_13] = { + .id = MT8196_IRQ_13, + .irq_cnt_reg = AFE_IRQ13_MCU_CFG1, + .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, + .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, + .irq_fs_reg = AFE_IRQ13_MCU_CFG0, + .irq_fs_shift = AFE_IRQ13_MCU_FS_SFT, + .irq_fs_maskbit = AFE_IRQ13_MCU_FS_MASK, + .irq_en_reg = AFE_IRQ13_MCU_CFG0, + .irq_en_shift = AFE_IRQ13_MCU_ON_SFT, + .irq_clr_reg = AFE_IRQ13_MCU_CFG1, + .irq_clr_shift = AFE_IRQ13_CLR_CFG_SFT, + .irq_ap_en_reg = AFE_IRQ_MCU_EN, + .irq_scp_en_reg = AFE_IRQ_MCU_SCP_EN, + .irq_scp_en_shift = IRQ13_MCU_SCP_EN_SFT, + }, + [MT8196_IRQ_14] = { + .id = MT8196_IRQ_14, + .irq_cnt_reg = AFE_IRQ14_MCU_CFG1, + .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, + .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, + .irq_fs_reg = AFE_IRQ14_MCU_CFG0, + .irq_fs_shift = AFE_IRQ14_MCU_FS_SFT, + .irq_fs_maskbit = AFE_IRQ14_MCU_FS_MASK, + .irq_en_reg = AFE_IRQ14_MCU_CFG0, + .irq_en_shift = AFE_IRQ14_MCU_ON_SFT, + .irq_clr_reg = AFE_IRQ14_MCU_CFG1, + .irq_clr_shift = AFE_IRQ14_CLR_CFG_SFT, + .irq_ap_en_reg = AFE_IRQ_MCU_EN, + .irq_scp_en_reg = AFE_IRQ_MCU_SCP_EN, + .irq_scp_en_shift = IRQ14_MCU_SCP_EN_SFT, + }, + [MT8196_IRQ_15] = { + .id = MT8196_IRQ_15, + .irq_cnt_reg = AFE_IRQ15_MCU_CFG1, + .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, + .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, + .irq_fs_reg = AFE_IRQ15_MCU_CFG0, + .irq_fs_shift = AFE_IRQ15_MCU_FS_SFT, + .irq_fs_maskbit = AFE_IRQ15_MCU_FS_MASK, + .irq_en_reg = AFE_IRQ15_MCU_CFG0, + .irq_en_shift = AFE_IRQ15_MCU_ON_SFT, + .irq_clr_reg = AFE_IRQ15_MCU_CFG1, + .irq_clr_shift = AFE_IRQ15_CLR_CFG_SFT, + .irq_ap_en_reg = AFE_IRQ_MCU_EN, + .irq_scp_en_reg = AFE_IRQ_MCU_SCP_EN, + .irq_scp_en_shift = IRQ15_MCU_SCP_EN_SFT, + }, + [MT8196_IRQ_16] = { + .id = MT8196_IRQ_16, + .irq_cnt_reg = AFE_IRQ16_MCU_CFG1, + .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, + .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, + .irq_fs_reg = AFE_IRQ16_MCU_CFG0, + .irq_fs_shift = AFE_IRQ16_MCU_FS_SFT, + .irq_fs_maskbit = AFE_IRQ16_MCU_FS_MASK, + .irq_en_reg = AFE_IRQ16_MCU_CFG0, + .irq_en_shift = AFE_IRQ16_MCU_ON_SFT, + .irq_clr_reg = AFE_IRQ16_MCU_CFG1, + .irq_clr_shift = AFE_IRQ16_CLR_CFG_SFT, + .irq_ap_en_reg = AFE_IRQ_MCU_EN, + .irq_scp_en_reg = AFE_IRQ_MCU_SCP_EN, + .irq_scp_en_shift = IRQ16_MCU_SCP_EN_SFT, + }, + [MT8196_IRQ_17] = { + .id = MT8196_IRQ_17, + .irq_cnt_reg = AFE_IRQ17_MCU_CFG1, + .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, + .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, + .irq_fs_reg = AFE_IRQ17_MCU_CFG0, + .irq_fs_shift = AFE_IRQ17_MCU_FS_SFT, + .irq_fs_maskbit = AFE_IRQ17_MCU_FS_MASK, + .irq_en_reg = AFE_IRQ17_MCU_CFG0, + .irq_en_shift = AFE_IRQ17_MCU_ON_SFT, + .irq_clr_reg = AFE_IRQ17_MCU_CFG1, + .irq_clr_shift = AFE_IRQ17_CLR_CFG_SFT, + .irq_ap_en_reg = AFE_IRQ_MCU_EN, + .irq_scp_en_reg = AFE_IRQ_MCU_SCP_EN, + .irq_scp_en_shift = IRQ17_MCU_SCP_EN_SFT, + }, + [MT8196_IRQ_18] = { + .id = MT8196_IRQ_18, + .irq_cnt_reg = AFE_IRQ18_MCU_CFG1, + .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, + .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, + .irq_fs_reg = AFE_IRQ18_MCU_CFG0, + .irq_fs_shift = AFE_IRQ18_MCU_FS_SFT, + .irq_fs_maskbit = AFE_IRQ18_MCU_FS_MASK, + .irq_en_reg = AFE_IRQ18_MCU_CFG0, + .irq_en_shift = AFE_IRQ18_MCU_ON_SFT, + .irq_clr_reg = AFE_IRQ18_MCU_CFG1, + .irq_clr_shift = AFE_IRQ18_CLR_CFG_SFT, + .irq_ap_en_reg = AFE_IRQ_MCU_EN, + .irq_scp_en_reg = AFE_IRQ_MCU_SCP_EN, + .irq_scp_en_shift = IRQ18_MCU_SCP_EN_SFT, + }, + [MT8196_IRQ_19] = { + .id = MT8196_IRQ_19, + .irq_cnt_reg = AFE_IRQ19_MCU_CFG1, + .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, + .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, + .irq_fs_reg = AFE_IRQ19_MCU_CFG0, + .irq_fs_shift = AFE_IRQ19_MCU_FS_SFT, + .irq_fs_maskbit = AFE_IRQ19_MCU_FS_MASK, + .irq_en_reg = AFE_IRQ19_MCU_CFG0, + .irq_en_shift = AFE_IRQ19_MCU_ON_SFT, + .irq_clr_reg = AFE_IRQ19_MCU_CFG1, + .irq_clr_shift = AFE_IRQ19_CLR_CFG_SFT, + .irq_ap_en_reg = AFE_IRQ_MCU_EN, + .irq_scp_en_reg = AFE_IRQ_MCU_SCP_EN, + .irq_scp_en_shift = IRQ19_MCU_SCP_EN_SFT, + }, + [MT8196_IRQ_20] = { + .id = MT8196_IRQ_20, + .irq_cnt_reg = AFE_IRQ20_MCU_CFG1, + .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, + .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, + .irq_fs_reg = AFE_IRQ20_MCU_CFG0, + .irq_fs_shift = AFE_IRQ20_MCU_FS_SFT, + .irq_fs_maskbit = AFE_IRQ20_MCU_FS_MASK, + .irq_en_reg = AFE_IRQ20_MCU_CFG0, + .irq_en_shift = AFE_IRQ20_MCU_ON_SFT, + .irq_clr_reg = AFE_IRQ20_MCU_CFG1, + .irq_clr_shift = AFE_IRQ20_CLR_CFG_SFT, + .irq_ap_en_reg = AFE_IRQ_MCU_EN, + .irq_scp_en_reg = AFE_IRQ_MCU_SCP_EN, + .irq_scp_en_shift = IRQ20_MCU_SCP_EN_SFT, + }, + [MT8196_IRQ_21] = { + .id = MT8196_IRQ_21, + .irq_cnt_reg = AFE_IRQ21_MCU_CFG1, + .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, + .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, + .irq_fs_reg = AFE_IRQ21_MCU_CFG0, + .irq_fs_shift = AFE_IRQ21_MCU_FS_SFT, + .irq_fs_maskbit = AFE_IRQ21_MCU_FS_MASK, + .irq_en_reg = AFE_IRQ21_MCU_CFG0, + .irq_en_shift = AFE_IRQ21_MCU_ON_SFT, + .irq_clr_reg = AFE_IRQ21_MCU_CFG1, + .irq_clr_shift = AFE_IRQ21_CLR_CFG_SFT, + .irq_ap_en_reg = AFE_IRQ_MCU_EN, + .irq_scp_en_reg = AFE_IRQ_MCU_SCP_EN, + .irq_scp_en_shift = IRQ21_MCU_SCP_EN_SFT, + }, + [MT8196_IRQ_22] = { + .id = MT8196_IRQ_22, + .irq_cnt_reg = AFE_IRQ22_MCU_CFG1, + .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, + .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, + .irq_fs_reg = AFE_IRQ22_MCU_CFG0, + .irq_fs_shift = AFE_IRQ22_MCU_FS_SFT, + .irq_fs_maskbit = AFE_IRQ22_MCU_FS_MASK, + .irq_en_reg = AFE_IRQ22_MCU_CFG0, + .irq_en_shift = AFE_IRQ22_MCU_ON_SFT, + .irq_clr_reg = AFE_IRQ22_MCU_CFG1, + .irq_clr_shift = AFE_IRQ22_CLR_CFG_SFT, + .irq_ap_en_reg = AFE_IRQ_MCU_EN, + .irq_scp_en_reg = AFE_IRQ_MCU_SCP_EN, + .irq_scp_en_shift = IRQ22_MCU_SCP_EN_SFT, + }, + [MT8196_IRQ_23] = { + .id = MT8196_IRQ_23, + .irq_cnt_reg = AFE_IRQ23_MCU_CFG1, + .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, + .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, + .irq_fs_reg = AFE_IRQ23_MCU_CFG0, + .irq_fs_shift = AFE_IRQ23_MCU_FS_SFT, + .irq_fs_maskbit = AFE_IRQ23_MCU_FS_MASK, + .irq_en_reg = AFE_IRQ23_MCU_CFG0, + .irq_en_shift = AFE_IRQ23_MCU_ON_SFT, + .irq_clr_reg = AFE_IRQ23_MCU_CFG1, + .irq_clr_shift = AFE_IRQ23_CLR_CFG_SFT, + .irq_ap_en_reg = AFE_IRQ_MCU_EN, + .irq_scp_en_reg = AFE_IRQ_MCU_SCP_EN, + .irq_scp_en_shift = IRQ23_MCU_SCP_EN_SFT, + }, + [MT8196_IRQ_24] = { + .id = MT8196_IRQ_24, + .irq_cnt_reg = AFE_IRQ24_MCU_CFG1, + .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, + .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, + .irq_fs_reg = AFE_IRQ24_MCU_CFG0, + .irq_fs_shift = AFE_IRQ24_MCU_FS_SFT, + .irq_fs_maskbit = AFE_IRQ24_MCU_FS_MASK, + .irq_en_reg = AFE_IRQ24_MCU_CFG0, + .irq_en_shift = AFE_IRQ24_MCU_ON_SFT, + .irq_clr_reg = AFE_IRQ24_MCU_CFG1, + .irq_clr_shift = AFE_IRQ24_CLR_CFG_SFT, + .irq_ap_en_reg = AFE_IRQ_MCU_EN, + .irq_scp_en_reg = AFE_IRQ_MCU_SCP_EN, + .irq_scp_en_shift = IRQ24_MCU_SCP_EN_SFT, + }, + [MT8196_IRQ_25] = { + .id = MT8196_IRQ_25, + .irq_cnt_reg = AFE_IRQ25_MCU_CFG1, + .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, + .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, + .irq_fs_reg = AFE_IRQ25_MCU_CFG0, + .irq_fs_shift = AFE_IRQ25_MCU_FS_SFT, + .irq_fs_maskbit = AFE_IRQ25_MCU_FS_MASK, + .irq_en_reg = AFE_IRQ25_MCU_CFG0, + .irq_en_shift = AFE_IRQ25_MCU_ON_SFT, + .irq_clr_reg = AFE_IRQ25_MCU_CFG1, + .irq_clr_shift = AFE_IRQ25_CLR_CFG_SFT, + .irq_ap_en_reg = AFE_IRQ_MCU_EN, + .irq_scp_en_reg = AFE_IRQ_MCU_SCP_EN, + .irq_scp_en_shift = IRQ25_MCU_SCP_EN_SFT, + }, + [MT8196_IRQ_26] = { + .id = MT8196_IRQ_26, + .irq_cnt_reg = AFE_IRQ26_MCU_CFG1, + .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, + .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, + .irq_fs_reg = AFE_IRQ26_MCU_CFG0, + .irq_fs_shift = AFE_IRQ26_MCU_FS_SFT, + .irq_fs_maskbit = AFE_IRQ26_MCU_FS_MASK, + .irq_en_reg = AFE_IRQ26_MCU_CFG0, + .irq_en_shift = AFE_IRQ26_MCU_ON_SFT, + .irq_clr_reg = AFE_IRQ26_MCU_CFG1, + .irq_clr_shift = AFE_IRQ26_CLR_CFG_SFT, + .irq_ap_en_reg = AFE_IRQ_MCU_EN, + .irq_scp_en_reg = AFE_IRQ_MCU_SCP_EN, + .irq_scp_en_shift = IRQ26_MCU_SCP_EN_SFT, + }, + [MT8196_IRQ_31] = { + .id = MT8196_CUS_IRQ_TDM, + .irq_cnt_reg = AFE_CUSTOM_IRQ0_MCU_CFG1, + .irq_cnt_shift = AFE_CUSTOM_IRQ0_MCU_CNT_SFT, + .irq_cnt_maskbit = AFE_CUSTOM_IRQ0_MCU_CNT_MASK, + .irq_fs_reg = -1, + .irq_fs_shift = -1, + .irq_fs_maskbit = -1, + .irq_en_reg = AFE_CUSTOM_IRQ0_MCU_CFG0, + .irq_en_shift = AFE_CUSTOM_IRQ0_MCU_ON_SFT, + .irq_clr_reg = AFE_CUSTOM_IRQ0_MCU_CFG1, + .irq_clr_shift = AFE_CUSTOM_IRQ0_CLR_CFG_SFT, + .irq_ap_en_reg = AFE_CUSTOM_IRQ_MCU_EN, + .irq_scp_en_reg = AFE_CUSTOM_IRQ_MCU_SCP_EN, + }, +}; + +static const int memif_irq_usage[MT8196_MEMIF_NUM] = { + /* TODO: verify each memif & irq */ + [MT8196_MEMIF_DL0] = MT8196_IRQ_0, + [MT8196_MEMIF_DL1] = MT8196_IRQ_1, + [MT8196_MEMIF_DL2] = MT8196_IRQ_2, + [MT8196_MEMIF_DL3] = MT8196_IRQ_3, + [MT8196_MEMIF_DL4] = MT8196_IRQ_4, + [MT8196_MEMIF_DL5] = MT8196_IRQ_5, + [MT8196_MEMIF_DL6] = MT8196_IRQ_6, + [MT8196_MEMIF_DL7] = MT8196_IRQ_7, + [MT8196_MEMIF_DL8] = MT8196_IRQ_8, + [MT8196_MEMIF_DL23] = MT8196_IRQ_9, + [MT8196_MEMIF_DL24] = MT8196_IRQ_10, + [MT8196_MEMIF_DL25] = MT8196_IRQ_11, + [MT8196_MEMIF_DL26] = MT8196_IRQ_0, + [MT8196_MEMIF_DL_4CH] = MT8196_IRQ_0, + [MT8196_MEMIF_DL_24CH] = MT8196_IRQ_12, + [MT8196_MEMIF_VUL0] = MT8196_IRQ_13, + [MT8196_MEMIF_VUL1] = MT8196_IRQ_14, + [MT8196_MEMIF_VUL2] = MT8196_IRQ_15, + [MT8196_MEMIF_VUL3] = MT8196_IRQ_16, + [MT8196_MEMIF_VUL4] = MT8196_IRQ_17, + [MT8196_MEMIF_VUL5] = MT8196_IRQ_18, + [MT8196_MEMIF_VUL6] = MT8196_IRQ_19, + [MT8196_MEMIF_VUL7] = MT8196_IRQ_20, + [MT8196_MEMIF_VUL8] = MT8196_IRQ_21, + [MT8196_MEMIF_VUL9] = MT8196_IRQ_22, + [MT8196_MEMIF_VUL10] = MT8196_IRQ_23, + [MT8196_MEMIF_VUL24] = MT8196_IRQ_24, + [MT8196_MEMIF_VUL25] = MT8196_IRQ_25, + [MT8196_MEMIF_VUL26] = MT8196_IRQ_0, + [MT8196_MEMIF_VUL_CM0] = MT8196_IRQ_26, + [MT8196_MEMIF_VUL_CM1] = MT8196_IRQ_0, + [MT8196_MEMIF_VUL_CM2] = MT8196_IRQ_0, + [MT8196_MEMIF_ETDM_IN0] = MT8196_IRQ_0, + [MT8196_MEMIF_ETDM_IN1] = MT8196_IRQ_0, + [MT8196_MEMIF_ETDM_IN2] = MT8196_IRQ_0, + [MT8196_MEMIF_ETDM_IN3] = MT8196_IRQ_0, + [MT8196_MEMIF_ETDM_IN4] = MT8196_IRQ_0, + [MT8196_MEMIF_ETDM_IN6] = MT8196_IRQ_0, + [MT8196_MEMIF_HDMI] = MT8196_IRQ_31 +}; + +static bool mt8196_is_volatile_reg(struct device *dev, unsigned int reg) +{ + /* these auto-gen reg has read-only bit, so put it as volatile */ + /* volatile reg cannot be cached, so cannot be set when power off */ + switch (reg) { + case AUDIO_TOP_CON0: /* reg bit controlled by CCF */ + case AUDIO_TOP_CON1: /* reg bit controlled by CCF */ + case AUDIO_TOP_CON2: + case AUDIO_TOP_CON3: + case AUDIO_TOP_CON4: + case AUD_TOP_MON_RG: + case AFE_APLL1_TUNER_MON0: + case AFE_APLL2_TUNER_MON0: + case AFE_SPM_CONTROL_ACK: + case AUDIO_TOP_IP_VERSION: + case AUDIO_ENGEN_CON0_MON: + case AFE_CONNSYS_I2S_IPM_VER_MON: + case AFE_CONNSYS_I2S_MON: + case AFE_PCM_INTF_MON: + case AFE_PCM_TOP_IP_VERSION: + case AFE_IRQ_MCU_STATUS: + case AFE_CUSTOM_IRQ_MCU_STATUS: + case AFE_IRQ_MCU_MON0: + case AFE_IRQ_MCU_MON1: + case AFE_IRQ_MCU_MON2: + case AFE_IRQ0_CNT_MON: + case AFE_IRQ1_CNT_MON: + case AFE_IRQ2_CNT_MON: + case AFE_IRQ3_CNT_MON: + case AFE_IRQ4_CNT_MON: + case AFE_IRQ5_CNT_MON: + case AFE_IRQ6_CNT_MON: + case AFE_IRQ7_CNT_MON: + case AFE_IRQ8_CNT_MON: + case AFE_IRQ9_CNT_MON: + case AFE_IRQ10_CNT_MON: + case AFE_IRQ11_CNT_MON: + case AFE_IRQ12_CNT_MON: + case AFE_IRQ13_CNT_MON: + case AFE_IRQ14_CNT_MON: + case AFE_IRQ15_CNT_MON: + case AFE_IRQ16_CNT_MON: + case AFE_IRQ17_CNT_MON: + case AFE_IRQ18_CNT_MON: + case AFE_IRQ19_CNT_MON: + case AFE_IRQ20_CNT_MON: + case AFE_IRQ21_CNT_MON: + case AFE_IRQ22_CNT_MON: + case AFE_IRQ23_CNT_MON: + case AFE_IRQ24_CNT_MON: + case AFE_IRQ25_CNT_MON: + case AFE_IRQ26_CNT_MON: + case AFE_CUSTOM_IRQ0_CNT_MON: + case AFE_STF_MON: + case AFE_STF_IP_VERSION: + case AFE_CM0_MON: + case AFE_CM0_IP_VERSION: + case AFE_CM1_MON: + case AFE_CM1_IP_VERSION: + case AFE_ADDA_UL0_SRC_DEBUG_MON0: + case AFE_ADDA_UL0_SRC_MON0: + case AFE_ADDA_UL0_SRC_MON1: + case AFE_ADDA_UL0_IP_VERSION: + case AFE_ADDA_UL1_SRC_DEBUG_MON0: + case AFE_ADDA_UL1_SRC_MON0: + case AFE_ADDA_UL1_SRC_MON1: + case AFE_ADDA_UL1_IP_VERSION: + case AFE_MTKAIF_IPM_VER_MON: + case AFE_MTKAIF_MON: + case AFE_AUD_PAD_TOP_MON: + case AFE_ADDA_MTKAIFV4_MON0: + case AFE_ADDA_MTKAIFV4_MON1: + case AFE_ADDA6_MTKAIFV4_MON0: + case ETDM_IN0_MON: + case ETDM_IN1_MON: + case ETDM_IN2_MON: + case ETDM_IN4_MON: + case ETDM_IN6_MON: + case ETDM_OUT0_MON: + case ETDM_OUT1_MON: + case ETDM_OUT2_MON: + case ETDM_OUT4_MON: + case ETDM_OUT6_MON: + case AFE_DPTX_MON: + case AFE_TDM_TOP_IP_VERSION: + case AFE_CONN_MON0: + case AFE_CONN_MON1: + case AFE_CONN_MON2: + case AFE_CONN_MON3: + case AFE_CONN_MON4: + case AFE_CONN_MON5: + case AFE_CBIP_SLV_DECODER_MON0: + case AFE_CBIP_SLV_DECODER_MON1: + case AFE_CBIP_SLV_MUX_MON0: + case AFE_CBIP_SLV_MUX_MON1: + case AFE_DL0_CUR_MSB: + case AFE_DL0_CUR: + case AFE_DL0_RCH_MON: + case AFE_DL0_LCH_MON: + case AFE_DL1_CUR_MSB: + case AFE_DL1_CUR: + case AFE_DL1_RCH_MON: + case AFE_DL1_LCH_MON: + case AFE_DL2_CUR_MSB: + case AFE_DL2_CUR: + case AFE_DL2_RCH_MON: + case AFE_DL2_LCH_MON: + case AFE_DL3_CUR_MSB: + case AFE_DL3_CUR: + case AFE_DL3_RCH_MON: + case AFE_DL3_LCH_MON: + case AFE_DL4_CUR_MSB: + case AFE_DL4_CUR: + case AFE_DL4_RCH_MON: + case AFE_DL4_LCH_MON: + case AFE_DL5_CUR_MSB: + case AFE_DL5_CUR: + case AFE_DL5_RCH_MON: + case AFE_DL5_LCH_MON: + case AFE_DL6_CUR_MSB: + case AFE_DL6_CUR: + case AFE_DL6_RCH_MON: + case AFE_DL6_LCH_MON: + case AFE_DL7_CUR_MSB: + case AFE_DL7_CUR: + case AFE_DL7_RCH_MON: + case AFE_DL7_LCH_MON: + case AFE_DL8_CUR_MSB: + case AFE_DL8_CUR: + case AFE_DL8_RCH_MON: + case AFE_DL8_LCH_MON: + case AFE_DL_24CH_CUR_MSB: + case AFE_DL_24CH_CUR: + case AFE_DL_4CH_CUR_MSB: + case AFE_DL_4CH_CUR: + case AFE_DL23_CUR_MSB: + case AFE_DL23_CUR: + case AFE_DL23_RCH_MON: + case AFE_DL23_LCH_MON: + case AFE_DL24_CUR_MSB: + case AFE_DL24_CUR: + case AFE_DL24_RCH_MON: + case AFE_DL24_LCH_MON: + case AFE_DL25_CUR_MSB: + case AFE_DL25_CUR: + case AFE_DL25_RCH_MON: + case AFE_DL25_LCH_MON: + case AFE_DL26_CUR_MSB: + case AFE_DL26_CUR: + case AFE_DL26_RCH_MON: + case AFE_DL26_LCH_MON: + case AFE_VUL0_CUR_MSB: + case AFE_VUL0_CUR: + case AFE_VUL1_CUR_MSB: + case AFE_VUL1_CUR: + case AFE_VUL2_CUR_MSB: + case AFE_VUL2_CUR: + case AFE_VUL3_CUR_MSB: + case AFE_VUL3_CUR: + case AFE_VUL4_CUR_MSB: + case AFE_VUL4_CUR: + case AFE_VUL5_CUR_MSB: + case AFE_VUL5_CUR: + case AFE_VUL6_CUR_MSB: + case AFE_VUL6_CUR: + case AFE_VUL7_CUR_MSB: + case AFE_VUL7_CUR: + case AFE_VUL8_CUR_MSB: + case AFE_VUL8_CUR: + case AFE_VUL9_CUR_MSB: + case AFE_VUL9_CUR: + case AFE_VUL10_CUR_MSB: + case AFE_VUL10_CUR: + case AFE_VUL24_CUR_MSB: + case AFE_VUL24_CUR: + case AFE_VUL25_CUR_MSB: + case AFE_VUL25_CUR: + case AFE_VUL25_RCH_MON: + case AFE_VUL25_LCH_MON: + case AFE_VUL26_CUR_MSB: + case AFE_VUL26_CUR: + case AFE_VUL_CM0_CUR_MSB: + case AFE_VUL_CM0_CUR: + case AFE_VUL_CM1_CUR_MSB: + case AFE_VUL_CM1_CUR: + case AFE_VUL_CM2_CUR_MSB: + case AFE_VUL_CM2_CUR: + case AFE_ETDM_IN0_CUR_MSB: + case AFE_ETDM_IN0_CUR: + case AFE_ETDM_IN1_CUR_MSB: + case AFE_ETDM_IN1_CUR: + case AFE_ETDM_IN2_CUR_MSB: + case AFE_ETDM_IN2_CUR: + case AFE_ETDM_IN3_CUR_MSB: + case AFE_ETDM_IN3_CUR: + case AFE_ETDM_IN4_CUR_MSB: + case AFE_ETDM_IN4_CUR: + case AFE_ETDM_IN6_CUR_MSB: + case AFE_ETDM_IN6_CUR: + case AFE_HDMI_OUT_CUR_MSB: + case AFE_HDMI_OUT_CUR: + case AFE_HDMI_OUT_END: + case AFE_PROT_SIDEBAND0_MON: + case AFE_PROT_SIDEBAND1_MON: + case AFE_PROT_SIDEBAND2_MON: + case AFE_PROT_SIDEBAND3_MON: + case AFE_DOMAIN_SIDEBAND0_MON: + case AFE_DOMAIN_SIDEBAND1_MON: + case AFE_DOMAIN_SIDEBAND2_MON: + case AFE_DOMAIN_SIDEBAND3_MON: + case AFE_DOMAIN_SIDEBAND4_MON: + case AFE_DOMAIN_SIDEBAND5_MON: + case AFE_DOMAIN_SIDEBAND6_MON: + case AFE_DOMAIN_SIDEBAND7_MON: + case AFE_DOMAIN_SIDEBAND8_MON: + case AFE_DOMAIN_SIDEBAND9_MON: + case AFE_PCM0_INTF_CON1_MASK_MON: + case AFE_PCM0_INTF_CON0_MASK_MON: + case AFE_CONNSYS_I2S_CON_MASK_MON: + case AFE_TDM_CON2_MASK_MON: + case AFE_MTKAIF0_CFG0_MASK_MON: + case AFE_MTKAIF1_CFG0_MASK_MON: + case AFE_ADDA_UL0_SRC_CON0_MASK_MON: + case AFE_ADDA_UL1_SRC_CON0_MASK_MON: + case AFE_ASRC_NEW_CON0: + case AFE_ASRC_NEW_CON6: + case AFE_ASRC_NEW_CON8: + case AFE_ASRC_NEW_CON9: + case AFE_ASRC_NEW_CON12: + case AFE_ASRC_NEW_IP_VERSION: + case AFE_GASRC0_NEW_CON0: + case AFE_GASRC0_NEW_CON6: + case AFE_GASRC0_NEW_CON8: + case AFE_GASRC0_NEW_CON9: + case AFE_GASRC0_NEW_CON10: + case AFE_GASRC0_NEW_CON11: + case AFE_GASRC0_NEW_CON12: + case AFE_GASRC0_NEW_IP_VERSION: + case AFE_GASRC1_NEW_CON0: + case AFE_GASRC1_NEW_CON6: + case AFE_GASRC1_NEW_CON8: + case AFE_GASRC1_NEW_CON9: + case AFE_GASRC1_NEW_CON12: + case AFE_GASRC1_NEW_IP_VERSION: + case AFE_GASRC2_NEW_CON0: + case AFE_GASRC2_NEW_CON6: + case AFE_GASRC2_NEW_CON8: + case AFE_GASRC2_NEW_CON9: + case AFE_GASRC2_NEW_CON12: + case AFE_GASRC2_NEW_IP_VERSION: + case AFE_GASRC3_NEW_CON0: + case AFE_GASRC3_NEW_CON6: + case AFE_GASRC3_NEW_CON8: + case AFE_GASRC3_NEW_CON9: + case AFE_GASRC3_NEW_CON12: + case AFE_GASRC3_NEW_IP_VERSION: + /* these reg would change in adsp */ + case AFE_IRQ_MCU_EN: + case AFE_IRQ_MCU_DSP_EN: + case AFE_IRQ_MCU_DSP2_EN: + case AFE_DL5_CON0: + case AFE_DL6_CON0: + case AFE_DL23_CON0: + case AFE_DL_24CH_CON0: + case AFE_VUL1_CON0: + case AFE_VUL3_CON0: + case AFE_VUL4_CON0: + case AFE_VUL5_CON0: + case AFE_VUL9_CON0: + case AFE_VUL25_CON0: + case AFE_IRQ0_MCU_CFG0: + case AFE_IRQ1_MCU_CFG0: + case AFE_IRQ2_MCU_CFG0: + case AFE_IRQ3_MCU_CFG0: + case AFE_IRQ4_MCU_CFG0: + case AFE_IRQ5_MCU_CFG0: + case AFE_IRQ6_MCU_CFG0: + case AFE_IRQ7_MCU_CFG0: + case AFE_IRQ8_MCU_CFG0: + case AFE_IRQ9_MCU_CFG0: + case AFE_IRQ10_MCU_CFG0: + case AFE_IRQ11_MCU_CFG0: + case AFE_IRQ12_MCU_CFG0: + case AFE_IRQ13_MCU_CFG0: + case AFE_IRQ14_MCU_CFG0: + case AFE_IRQ15_MCU_CFG0: + case AFE_IRQ16_MCU_CFG0: + case AFE_IRQ17_MCU_CFG0: + case AFE_IRQ18_MCU_CFG0: + case AFE_IRQ19_MCU_CFG0: + case AFE_IRQ20_MCU_CFG0: + case AFE_IRQ21_MCU_CFG0: + case AFE_IRQ22_MCU_CFG0: + case AFE_IRQ23_MCU_CFG0: + case AFE_IRQ24_MCU_CFG0: + case AFE_IRQ25_MCU_CFG0: + case AFE_IRQ26_MCU_CFG0: + case AFE_IRQ0_MCU_CFG1: + case AFE_IRQ1_MCU_CFG1: + case AFE_IRQ2_MCU_CFG1: + case AFE_IRQ3_MCU_CFG1: + case AFE_IRQ4_MCU_CFG1: + case AFE_IRQ5_MCU_CFG1: + case AFE_IRQ6_MCU_CFG1: + case AFE_IRQ7_MCU_CFG1: + case AFE_IRQ8_MCU_CFG1: + case AFE_IRQ9_MCU_CFG1: + case AFE_IRQ10_MCU_CFG1: + case AFE_IRQ11_MCU_CFG1: + case AFE_IRQ12_MCU_CFG1: + case AFE_IRQ13_MCU_CFG1: + case AFE_IRQ14_MCU_CFG1: + case AFE_IRQ15_MCU_CFG1: + case AFE_IRQ16_MCU_CFG1: + case AFE_IRQ17_MCU_CFG1: + case AFE_IRQ18_MCU_CFG1: + case AFE_IRQ19_MCU_CFG1: + case AFE_IRQ20_MCU_CFG1: + case AFE_IRQ21_MCU_CFG1: + case AFE_IRQ22_MCU_CFG1: + case AFE_IRQ23_MCU_CFG1: + case AFE_IRQ24_MCU_CFG1: + case AFE_IRQ25_MCU_CFG1: + case AFE_IRQ26_MCU_CFG1: + /* for vow using */ + case AFE_IRQ_MCU_SCP_EN: + case AFE_VUL_CM0_BASE_MSB: + case AFE_VUL_CM0_BASE: + case AFE_VUL_CM0_END_MSB: + case AFE_VUL_CM0_END: + case AFE_VUL_CM0_CON0: + return true; + default: + return false; + }; +} + +static const struct regmap_config mt8196_afe_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + + .volatile_reg = mt8196_is_volatile_reg, + + .max_register = AFE_MAX_REGISTER, + .num_reg_defaults_raw = AFE_MAX_REGISTER, + + .cache_type = REGCACHE_FLAT, +}; + +static irqreturn_t mt8196_afe_irq_handler(int irq_id, void *dev) +{ + struct mtk_base_afe *afe = dev; + struct mtk_base_afe_irq *irq; + unsigned int status = 0; + unsigned int status_mcu; + unsigned int mcu_en = 0; + unsigned int cus_status = 0; + unsigned int cus_status_mcu; + unsigned int cus_mcu_en = 0; + unsigned int tmp_reg = 0; + int ret, cus_ret; + int i; + struct timespec64 ts64; + unsigned long long t1, t2; + /* one interrupt period = 5ms */ + unsigned long long timeout_limit = 5000000; + + /* get irq that is sent to MCU */ + regmap_read(afe->regmap, AFE_IRQ_MCU_EN, &mcu_en); + regmap_read(afe->regmap, AFE_CUSTOM_IRQ_MCU_EN, &cus_mcu_en); + + ret = regmap_read(afe->regmap, AFE_IRQ_MCU_STATUS, &status); + cus_ret = regmap_read(afe->regmap, AFE_CUSTOM_IRQ_MCU_STATUS, &cus_status); + /* only care IRQ which is sent to MCU */ + status_mcu = status & mcu_en & AFE_IRQ_STATUS_BITS; + cus_status_mcu = cus_status & cus_mcu_en & AFE_IRQ_STATUS_BITS; + if ((ret || !status_mcu) && + (cus_ret || !cus_status_mcu)) { + dev_info(afe->dev, "irq status err, ret %d, status 0x%x, mcu_en 0x%x\n", + ret, status, mcu_en); + dev_info(afe->dev, "irq status err, ret %d, cus_status_mcu 0x%x, cus_mcu_en 0x%x\n", + ret, cus_status_mcu, cus_mcu_en); + + goto err_irq; + } + + ktime_get_ts64(&ts64); + t1 = timespec64_to_ns(&ts64); + + for (i = 0; i < MT8196_MEMIF_NUM; i++) { + struct mtk_base_afe_memif *memif = &afe->memif[i]; + + if (!memif->substream) + continue; + + if (memif->irq_usage < 0) + continue; + irq = &afe->irqs[memif->irq_usage]; + + if (i == MT8196_MEMIF_HDMI) { + if (cus_status_mcu & (0x1 << irq->irq_data->id)) + snd_pcm_period_elapsed(memif->substream); + } else { + if (status_mcu & (0x1 << irq->irq_data->id)) + snd_pcm_period_elapsed(memif->substream); + } + } + + ktime_get_ts64(&ts64); + t2 = timespec64_to_ns(&ts64); + t2 = t2 - t1; /* in ns (10^9) */ + + if (t2 > timeout_limit) { + dev_warn(afe->dev, "mcu_en 0x%x, cus_mcu_en 0x%x, timeout %llu, limit %llu, ret %d\n", + mcu_en, cus_mcu_en, + t2, timeout_limit, ret); + } + +err_irq: + /* clear irq */ + for (i = 0; i < MT8196_IRQ_NUM; ++i) { + /* cus_status_mcu only bit0 is used for TDM */ + if ((status_mcu & (0x1 << i)) || (cus_status_mcu & 0x1)) { + regmap_read(afe->regmap, irq_data[i].irq_clr_reg, &tmp_reg); + regmap_update_bits(afe->regmap, irq_data[i].irq_clr_reg, + AFE_IRQ_CLR_CFG_MASK_SFT | + AFE_IRQ_MISS_FLAG_CLR_CFG_MASK_SFT, + tmp_reg ^ (AFE_IRQ_CLR_CFG_MASK_SFT | + AFE_IRQ_MISS_FLAG_CLR_CFG_MASK_SFT)); + } + } + + return IRQ_HANDLED; +} + +static int mt8196_afe_runtime_suspend(struct device *dev) +{ + struct mtk_base_afe *afe = dev_get_drvdata(dev); + unsigned int value = 0; + unsigned int tmp_reg = 0; + int ret = 0, i; + + if (!afe->regmap) { + dev_err(afe->dev, "skip regmap\n"); + goto skip_regmap; + } + + /* Add to be off for free run*/ + /* disable AFE */ + regmap_update_bits(afe->regmap, AUDIO_ENGEN_CON0, 0x1, 0x0); + + ret = regmap_read_poll_timeout(afe->regmap, + AUDIO_ENGEN_CON0_MON, + value, + (value & AUDIO_ENGEN_MON_SFT) == 0, + 20, + 1 * 1000 * 1000); + dev_dbg(afe->dev, "read_poll ret %d\n", ret); + if (ret) + dev_info(afe->dev, "ret %d\n", ret); + + /* make sure all irq status are cleared */ + for (i = 0; i < MT8196_IRQ_NUM; ++i) { + regmap_read(afe->regmap, irq_data[i].irq_clr_reg, &tmp_reg); + regmap_update_bits(afe->regmap, irq_data[i].irq_clr_reg, + AFE_IRQ_CLR_CFG_MASK_SFT | AFE_IRQ_MISS_FLAG_CLR_CFG_MASK_SFT, + tmp_reg ^ (AFE_IRQ_CLR_CFG_MASK_SFT | + AFE_IRQ_MISS_FLAG_CLR_CFG_MASK_SFT)); + } + + /* reset sgen */ + regmap_write(afe->regmap, AFE_SINEGEN_CON0, 0x0); + regmap_update_bits(afe->regmap, AFE_SINEGEN_CON1, + SINE_DOMAIN_MASK_SFT, + 0x0 << SINE_DOMAIN_SFT); + regmap_update_bits(afe->regmap, AFE_SINEGEN_CON1, + SINE_MODE_MASK_SFT, + 0x0 << SINE_MODE_SFT); + regmap_update_bits(afe->regmap, AFE_SINEGEN_CON1, + INNER_LOOP_BACKI_SEL_MASK_SFT, + 0x0 << INNER_LOOP_BACKI_SEL_SFT); + regmap_update_bits(afe->regmap, AFE_SINEGEN_CON1, + INNER_LOOP_BACK_MODE_MASK_SFT, + 0xff << INNER_LOOP_BACK_MODE_SFT); + + regmap_write(afe->regmap, AUDIO_TOP_CON4, 0x3fff); + + /* reset audio 26M request */ + regmap_update_bits(afe->regmap, + AFE_SPM_CONTROL_REQ, 0x1, 0x0); + + /* cache only */ + regcache_cache_only(afe->regmap, true); + regcache_mark_dirty(afe->regmap); + +skip_regmap: + mt8196_afe_disable_clock(afe); + return 0; +} + +static int mt8196_afe_runtime_resume(struct device *dev) +{ + struct mtk_base_afe *afe = dev_get_drvdata(dev); + int ret = 0; + + ret = mt8196_afe_enable_clock(afe); + if (ret) + return ret; + + if (!afe->regmap) { + dev_warn(afe->dev, "skip regmap\n"); + goto skip_regmap; + } + regcache_cache_only(afe->regmap, false); + regcache_sync(afe->regmap); + + /* set audio 26M request */ + regmap_update_bits(afe->regmap, AFE_SPM_CONTROL_REQ, 0x1, 0x1); + + /* IPM2.0: Clear AUDIO_TOP_CON4 for enabling AP side module clk */ + regmap_write(afe->regmap, AUDIO_TOP_CON4, 0x0); + + /* Add to be on for free run */ + regmap_write(afe->regmap, AUDIO_TOP_CON0, 0x0); + regmap_write(afe->regmap, AUDIO_TOP_CON1, 0x0); + regmap_write(afe->regmap, AUDIO_TOP_CON2, 0x0); + + /* Can't set AUDIO_TOP_CON3 to be 0x0, it will hang in FPGA env */ + regmap_write(afe->regmap, AUDIO_TOP_CON3, 0x0); + + regmap_update_bits(afe->regmap, AFE_CBIP_CFG0, 0x1, 0x1); + + /* force cpu use 8_24 format when writing 32bit data */ + regmap_update_bits(afe->regmap, AFE_MEMIF_CON0, + CPU_HD_ALIGN_MASK_SFT, 0 << CPU_HD_ALIGN_SFT); + + /* enable AFE */ + regmap_update_bits(afe->regmap, AUDIO_ENGEN_CON0, 0x1, 0x1); + +skip_regmap: + return 0; +} + +static int mt8196_afe_component_probe(struct snd_soc_component *component) +{ + if (component) + mtk_afe_add_sub_dai_control(component); + + return 0; +} + +static int mt8196_afe_pcm_open(struct snd_soc_component *component, + struct snd_pcm_substream *substream) +{ + /* set the wait_for_avail to 2 sec*/ + substream->wait_time = msecs_to_jiffies(2 * 1000); + + return 0; +} + +static void mt8196_afe_pcm_free(struct snd_soc_component *component, struct snd_pcm *pcm) +{ + snd_pcm_lib_preallocate_free_for_all(pcm); +} + +static const struct snd_soc_component_driver mt8196_afe_component = { + .name = AFE_PCM_NAME, + .probe = mt8196_afe_component_probe, + .pcm_construct = mtk_afe_pcm_new, + .pcm_destruct = mt8196_afe_pcm_free, + .open = mt8196_afe_pcm_open, + .pointer = mtk_afe_pcm_pointer, +}; + +static int mt8196_dai_memif_register(struct mtk_base_afe *afe) +{ + struct mtk_base_afe_dai *dai; + + dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL); + if (!dai) + return -ENOMEM; + + list_add(&dai->list, &afe->sub_dais); + + dai->dai_drivers = mt8196_memif_dai_driver; + dai->num_dai_drivers = ARRAY_SIZE(mt8196_memif_dai_driver); + + dai->controls = mt8196_pcm_kcontrols; + dai->num_controls = ARRAY_SIZE(mt8196_pcm_kcontrols); + dai->dapm_widgets = mt8196_memif_widgets; + dai->num_dapm_widgets = ARRAY_SIZE(mt8196_memif_widgets); + dai->dapm_routes = mt8196_memif_routes; + dai->num_dapm_routes = ARRAY_SIZE(mt8196_memif_routes); + return 0; +} + +typedef int (*dai_register_cb)(struct mtk_base_afe *); +static const dai_register_cb dai_register_cbs[] = { + mt8196_dai_adda_register, + mt8196_dai_i2s_register, + mt8196_dai_tdm_register, + mt8196_dai_memif_register, +}; + +static int mt8196_afe_pcm_dev_probe(struct platform_device *pdev) +{ + int ret, i; + unsigned int tmp_reg = 0; + int irq_id; + struct mtk_base_afe *afe; + struct mt8196_afe_private *afe_priv; + struct device *dev; + + ret = of_reserved_mem_device_init(&pdev->dev); + if (ret) + dev_dbg(&pdev->dev, "failed to assign memory region: %d\n", ret); + + ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(34)); + if (ret) + return ret; + + afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL); + if (!afe) + return -ENOMEM; + + platform_set_drvdata(pdev, afe); + + afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv), + GFP_KERNEL); + if (!afe->platform_priv) + return -ENOMEM; + + afe_priv = afe->platform_priv; + + afe->dev = &pdev->dev; + dev = afe->dev; + + /* init audio related clock */ + ret = mt8196_init_clock(afe); + if (ret) + return dev_err_probe(dev, ret, "init clock error.\n"); + + pm_runtime_enable(&pdev->dev); + if (!pm_runtime_enabled(&pdev->dev)) + goto err_pm_disable; + + /* Audio device is part of genpd. + * Set audio as syscore device to prevent + * genpd automatically power off audio + * device when suspend + */ + dev_pm_syscore_device(&pdev->dev, true); + + afe->base_addr = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(afe->base_addr)) + return dev_err_probe(dev, PTR_ERR(afe->base_addr), + "AFE base_addr not found\n"); + + /* enable clock for regcache get default value from hw */ + pm_runtime_get_sync(&pdev->dev); + + afe->regmap = devm_regmap_init_mmio(&pdev->dev, afe->base_addr, + &mt8196_afe_regmap_config); + if (IS_ERR(afe->regmap)) + return PTR_ERR(afe->regmap); + + /* IPM2.0 clock flow, need debug */ + regmap_read(afe->regmap, AFE_IRQ_MCU_EN, &tmp_reg); + regmap_write(afe->regmap, AFE_IRQ_MCU_EN, 0xffffffff); + regmap_read(afe->regmap, AFE_IRQ_MCU_EN, &tmp_reg); + /* IPM2.0 clock flow, need debug */ + + pm_runtime_put_sync(&pdev->dev); + + regcache_cache_only(afe->regmap, true); + regcache_mark_dirty(afe->regmap); + + /* init memif */ + /* IPM2.0 no need banding */ + afe->memif_32bit_supported = 1; + afe->memif_size = MT8196_MEMIF_NUM; + afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif), + GFP_KERNEL); + + if (!afe->memif) + return -ENOMEM; + + for (i = 0; i < afe->memif_size; i++) { + afe->memif[i].data = &memif_data[i]; + afe->memif[i].irq_usage = memif_irq_usage[i]; + afe->memif[i].const_irq = 1; + } + + mutex_init(&afe->irq_alloc_lock); + + /* init irq */ + afe->irqs_size = MT8196_IRQ_NUM; + afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs), + GFP_KERNEL); + + if (!afe->irqs) + return -ENOMEM; + + for (i = 0; i < afe->irqs_size; i++) + afe->irqs[i].irq_data = &irq_data[i]; + + /* request irq */ + irq_id = platform_get_irq(pdev, 0); + if (irq_id < 0) + return dev_err_probe(dev, irq_id, "no irq found"); + + ret = devm_request_irq(dev, irq_id, mt8196_afe_irq_handler, + IRQF_TRIGGER_NONE, + "Afe_ISR_Handle", (void *)afe); + if (ret) + return dev_err_probe(dev, ret, "could not request_irq for Afe_ISR_Handle\n"); + + ret = enable_irq_wake(irq_id); + if (ret < 0) + dev_warn(dev, "enable_irq_wake %d ret: %d\n", irq_id, ret); + + /* init sub_dais */ + INIT_LIST_HEAD(&afe->sub_dais); + + for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) { + ret = dai_register_cbs[i](afe); + if (ret) + return dev_err_probe(dev, ret, "dai register i %d fail\n", i); + } + + /* init dai_driver and component_driver */ + ret = mtk_afe_combine_sub_dai(afe); + if (ret) + return dev_err_probe(dev, ret, "mtk_afe_combine_sub_dai fail\n"); + + /* others */ + afe->mtk_afe_hardware = &mt8196_afe_hardware; + afe->memif_fs = mt8196_memif_fs; + afe->irq_fs = mt8196_irq_fs; + afe->get_dai_fs = mt8196_get_dai_fs; + afe->get_memif_pbuf_size = mt8196_get_memif_pbuf_size; + + afe->runtime_resume = mt8196_afe_runtime_resume; + afe->runtime_suspend = mt8196_afe_runtime_suspend; + + afe->request_dram_resource = mt8196_afe_dram_request; + afe->release_dram_resource = mt8196_afe_dram_release; + + /* register component */ + ret = devm_snd_soc_register_component(&pdev->dev, + &mt8196_afe_component, + afe->dai_drivers, + afe->num_dai_drivers); + if (ret) { + dev_warn(dev, "afe component err\n"); + goto err_pm_disable; + } + return 0; + +err_pm_disable: + pm_runtime_disable(&pdev->dev); + return ret; +} + +static void mt8196_afe_pcm_dev_remove(struct platform_device *pdev) +{ + struct mtk_base_afe *afe = platform_get_drvdata(pdev); + + pm_runtime_disable(&pdev->dev); + if (!pm_runtime_status_suspended(&pdev->dev)) + mt8196_afe_runtime_suspend(&pdev->dev); + + /* disable afe clock */ + mt8196_afe_disable_clock(afe); +} + +static const struct of_device_id mt8196_afe_pcm_dt_match[] = { + { .compatible = "mediatek,mt8196-afe-pcm", }, + {}, +}; +MODULE_DEVICE_TABLE(of, mt8196_afe_pcm_dt_match); + +static const struct dev_pm_ops mt8196_afe_pm_ops = { + SET_RUNTIME_PM_OPS(mt8196_afe_runtime_suspend, + mt8196_afe_runtime_resume, NULL) +}; + +static struct platform_driver mt8196_afe_pcm_driver = { + .driver = { + .name = "mt8196-afe-pcm", + .of_match_table = mt8196_afe_pcm_dt_match, +#if IS_ENABLED(CONFIG_PM) + .pm = &mt8196_afe_pm_ops, +#endif + }, + .probe = mt8196_afe_pcm_dev_probe, + .remove = mt8196_afe_pcm_dev_remove, +}; + +module_platform_driver(mt8196_afe_pcm_driver); + +MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver for 8196"); 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648e33d013a911f08eb9c36241bbb6fb-20250407 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1705508885; Mon, 07 Apr 2025 20:11:10 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Mon, 7 Apr 2025 20:11:10 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Mon, 7 Apr 2025 20:11:09 +0800 From: Darren.Ye To: Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Jaroslav Kysela , Takashi Iwai , Linus Walleij , Bartosz Golaszewski CC: , , , , , , Darren Ye Subject: [PATCH v2 09/11] ASoC: dt-bindings: mediatek,mt8196-afe: add audio AFE document Date: Mon, 7 Apr 2025 20:06:33 +0800 Message-ID: <20250407120708.26495-10-darren.ye@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250407120708.26495-1-darren.ye@mediatek.com> References: <20250407120708.26495-1-darren.ye@mediatek.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N From: Darren Ye Add mt8196 audio AFE document. Signed-off-by: Darren Ye --- .../bindings/sound/mediatek,mt8196-afe.yaml | 233 ++++++++++++++++++ 1 file changed, 233 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/mediatek,mt8196-afe.yaml diff --git a/Documentation/devicetree/bindings/sound/mediatek,mt8196-afe.yaml b/Documentation/devicetree/bindings/sound/mediatek,mt8196-afe.yaml new file mode 100644 index 000000000000..44f8847b13a8 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/mediatek,mt8196-afe.yaml @@ -0,0 +1,233 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/mediatek,mt8196-afe.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Audio Front End PCM controller for MT8196 + +maintainers: + - Darren Ye + +properties: + compatible: + const: mediatek,mt8196-afe-pcm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + memory-region: + maxItems: 1 + description: | + Shared memory region for AFE memif. A "shared-dma-pool". + See dtschema reserved-memory/shared-dma-pool.yaml for details. + mediatek,cksys: + $ref: /schemas/types.yaml#/definitions/phandle + description: The phandle of the mediatek clk systemd controller + + mediatek,vlpcksys: + $ref: /schemas/types.yaml#/definitions/phandle + description: The phandle of the mediatek vlpcksys controller + power-domains: + maxItems: 1 + + clocks: + items: + - description: audio hopping clock gate + - description: audio f26m clock gate + - description: audio apll1 clock gate + - description: audio apll2 clock gate + - description: audio apll1 tuner gate + - description: audio apll2 tuner gate + - description: mux for audio vlp int + - description: mux for audio vlp engen1 + - description: mux for audio vlp engen2 + - description: mux for audio h + - description: vlp clock 26m + - description: audio mainpll divide 4 + - description: mux for audio apll1 + - description: audio apll1 + - description: mux for audio apll2 + - description: audio apll2 + - description: audio apll1 divide 4 + - description: audio apll2 divide 4 + - description: mux for i2sin0 mck + - description: mux for i2sin1 mck + - description: mux for fmi2s mck + - description: mux for tdmout mck + - description: auido apll12 divide for i2sin0 + - description: auido apll12 divide for i2sin1 + - description: auido apll12 divide for fmi2s + - description: auido apll12 divide for tdmout mck + - description: auido apll12 divide for tdmout bck + - description: audio adsp clk + - description: 26m clock + + clock-names: + items: + - const: aud_hopping_clk + - const: aud_f26m_clk + - const: aud_apll1_clk + - const: aud_apll2_clk + - const: aud_apll_tuner1_clk + - const: aud_apll_tuner2_clk + - const: vlp_mux_audio_int + - const: vlp_mux_aud_eng1 + - const: vlp_mux_aud_eng2 + - const: vlp_mux_audio_h + - const: vlp_clk26m_clk + - const: ck_mainpll_d4_d4 + - const: ck_mux_aud_1 + - const: ck_apll1_ck + - const: ck_mux_aud_2 + - const: ck_apll2_ck + - const: ck_apll1_d4 + - const: ck_apll2_d4 + - const: ck_i2sin0_m_sel + - const: ck_i2sin1_m_sel + - const: ck_fmi2s_m_sel + - const: ck_tdmout_m_sel + - const: ck_apll12_div_i2sin0 + - const: ck_apll12_div_i2sin1 + - const: ck_apll12_div_fmi2s + - const: ck_apll12_div_tdmout_m + - const: ck_apll12_div_tdmout_b + - const: ck_adsp_sel + - const: ck_clk26m_clk + + mediatek,etdm4-out-ch: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Number of ETDM4 output channels. + minimum: 1 + maximum: 8 + + mediatek,etdm4-in-ch: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Number of ETDM4 input channels. + minimum: 1 + maximum: 8 + + mediatek,etdm4-out-sync: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + ETDM4 output and input enable synchronization. + enum: + - 0 # Enable controlled by itself + - 1 # Enable synchronization with ETDM4 input. + + mediatek,etdm4-in-sync: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + ETDM4 input and outpuot enable synchronization. + enum: + - 0 # Enable controlled by itself + - 1 # Enable synchronization with ETDM4 output. + + + + mediatek,etdm4-ip-mode: + $ref: /schemas/types.yaml#/definitions/uint32 + description: ETDM IP mode. + enum: + - 0 # One ip multi-ch mode + - 1 # Multi-ip 2ch mode + +required: + - compatible + - reg + - interrupts + - mediatek,cksys + - mediatek,vlpcksys + - power-domains + - memory-region + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + afe: mt8196-afe-pcm@1a110000 { + compatible = "mediatek,mt8196-afe-pcm"; + reg = <0 0x1a110000 0 0x9000>; + interrupts = ; + memory-region = <&afe_dma_mem_reserved>; + mediatek,cksys = <&cksys_clk>; + mediatek,vlpcksys = <&vlp_cksys_clk>; + power-domains = <&scpsys 14>; //MT8196_POWER_DOMAIN_AUDIO + mediatek,etdm4-out-ch = <2>; + mediatek,etdm4-in-ch = <2>; + mediatek,etdm4-out-sync = <0>; + mediatek,etdm4-in-sync = <1>; + mediatek,etdm4-ip-mode = <0>; + clocks = <&afe_clk 109>, //CLK_AFE_AUDIO_HOPPING_AFE + <&afe_clk 111>, //CLK_AFE_AUDIO_F26M_AFE + <&afe_clk 113>, //CLK_AFE_APLL1_AFE + <&afe_clk 115>, //CLK_AFE_APLL2_AFE + <&afe_clk 121>, //CLK_AFE_APLL_TUNER1_AFE + <&afe_clk 119>, //CLK_AFE_APLL_TUNER2_AFE + <&vlp_cksys_clk 40>, //CLK_VLP_CK_AUD_INTBUS_SEL + <&vlp_cksys_clk 38>, //CLK_VLP_CK_AUD_ENGEN1_SEL + <&vlp_cksys_clk 39>, //CLK_VLP_CK_AUD_ENGEN2_SEL + <&vlp_cksys_clk 37>, //CLK_VLP_CK_AUDIO_H_SEL + <&vlp_cksys_clk 45>, //CLK_VLP_CK_CLKSQ + <&cksys_clk 98>, //CLK_CK_MAINPLL_D4_D4 + <&cksys_clk 43>, //CLK_CK_AUD_1_SEL + <&cksys_clk 129>, //CLK_CK_APLL1 + <&cksys_clk 44>, //CLK_CK_AUD_2_SEL + <&cksys_clk 132>, //CLK_CK_APLL2 + <&cksys_clk 130>, //CLK_CK_APLL1_D4 + <&cksys_clk 133>, //CLK_CK_APLL2_D4 + <&cksys_clk 66>, //CLK_CK_APLL_I2SIN0_MCK_SEL + <&cksys_clk 67>, //CLK_CK_APLL_I2SIN1_MCK_SEL + <&cksys_clk 78>, //CLK_CK_APLL_FMI2S_MCK_SEL + <&cksys_clk 79>, //CLK_CK_APLL_TDMOUT_MCK_SEL + <&cksys_clk 80>, //CLK_CK_APLL12_CK_DIV_I2SIN0 + <&cksys_clk 81>, //CLK_CK_APLL12_CK_DIV_I2SIN1 + <&cksys_clk 92>, //CLK_CK_APLL12_CK_DIV_FMI2S + <&cksys_clk 93>, //CLK_CK_APLL12_CK_DIV_TDMOUT_M + <&cksys_clk 94>, //CLK_CK_APLL12_CK_DIV_TDMOUT_B + <&cksys_clk 45>, //CLK_CK_ADSP_SEL + <&cksys_clk 140>; //CLK_CK_TCK_26M_MX9 + clock-names = "aud_hopping_clk", + "aud_f26m_clk", + "aud_apll1_clk", + "aud_apll2_clk", + "aud_apll_tuner1_clk", + "aud_apll_tuner2_clk", + "vlp_mux_audio_int", + "vlp_mux_aud_eng1", + "vlp_mux_aud_eng2", + "vlp_mux_audio_h", + "vlp_clk26m_clk", + "ck_mainpll_d4_d4", + "ck_mux_aud_1", + "ck_apll1_ck", + "ck_mux_aud_2", + "ck_apll2_ck", + "ck_apll1_d4", + "ck_apll2_d4", + "ck_i2sin0_m_sel", + "ck_i2sin1_m_sel", + "ck_fmi2s_m_sel", + "ck_tdmout_m_sel", + "ck_apll12_div_i2sin0", + "ck_apll12_div_i2sin1", + "ck_apll12_div_fmi2s", + "ck_apll12_div_tdmout_m", + "ck_apll12_div_tdmout_b", + "ck_adsp_sel", + "ck_clk26m_clk"; + }; + }; From patchwork Mon Apr 7 12:06:34 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Darren.Ye" X-Patchwork-Id: 879153 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 95A3924EA93; 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Mon, 07 Apr 2025 20:11:13 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by MTKMBS09N2.mediatek.inc (172.21.101.94) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Mon, 7 Apr 2025 20:11:12 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Mon, 7 Apr 2025 20:11:11 +0800 From: Darren.Ye To: Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Jaroslav Kysela , Takashi Iwai , Linus Walleij , Bartosz Golaszewski CC: , , , , , , Darren Ye Subject: [PATCH v2 10/11] ASoC: mediatek: mt8196: add machine driver with mt6681 Date: Mon, 7 Apr 2025 20:06:34 +0800 Message-ID: <20250407120708.26495-11-darren.ye@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250407120708.26495-1-darren.ye@mediatek.com> References: <20250407120708.26495-1-darren.ye@mediatek.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N From: Darren Ye Add support for mt8196 board with mt6681. Signed-off-by: Darren Ye --- sound/soc/mediatek/Kconfig | 20 + sound/soc/mediatek/mt8196/Makefile | 2 + sound/soc/mediatek/mt8196/mt8196-mt6681.c | 876 ++++++++++++++++++++++ 3 files changed, 898 insertions(+) create mode 100644 sound/soc/mediatek/mt8196/mt8196-mt6681.c diff --git a/sound/soc/mediatek/Kconfig b/sound/soc/mediatek/Kconfig index 606f221e238c..55f9397fce91 100644 --- a/sound/soc/mediatek/Kconfig +++ b/sound/soc/mediatek/Kconfig @@ -214,6 +214,26 @@ config SND_SOC_MT8196 Select Y if you have such device. If unsure select "N". +config SND_SOC_MT8196_MT6681 + tristate "ASoc Audio driver for MT8196 with I2S codec" + depends on SND_SOC_MT8196 + depends on I2C + select SND_SOC_HDMI_CODEC + select SND_SOC_DMIC + select SND_SOC_NAU8315 + select SND_SOC_NAU8825 + select SND_SOC_RT5645 + select SND_SOC_RT5682_I2C + select SND_SOC_RT5682S + select SND_SOC_TAS2781_COMLIB + select SND_SOC_TAS2781_FMWLIB + select SND_SOC_TAS2781_I2C + help + This adds support for ASoC machine driver for MediaTek MT8196 + boards with the other I2S audio codecs. + Select Y if you have such device. + If unsure select "N". + config SND_SOC_MTK_BTCVSD tristate "ALSA BT SCO CVSD/MSBC Driver" help diff --git a/sound/soc/mediatek/mt8196/Makefile b/sound/soc/mediatek/mt8196/Makefile index 9bcc09a9a94d..4c7dd4c888a7 100644 --- a/sound/soc/mediatek/mt8196/Makefile +++ b/sound/soc/mediatek/mt8196/Makefile @@ -12,3 +12,5 @@ snd-soc-mt8196-afe-objs += \ mt8196-dai-i2s.o \ mt8196-dai-tdm.o +# machine driver +obj-$(CONFIG_SND_SOC_MT8196_MT6681) += mt8196-mt6681.o diff --git a/sound/soc/mediatek/mt8196/mt8196-mt6681.c b/sound/soc/mediatek/mt8196/mt8196-mt6681.c new file mode 100644 index 000000000000..ce09c71e2ba0 --- /dev/null +++ b/sound/soc/mediatek/mt8196/mt8196-mt6681.c @@ -0,0 +1,876 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * mt8196-mt6681.c -- mt8196 mt6681 ALSA SoC machine driver + * + * Copyright (c) 2023 MediaTek Inc. + * Author: Darren Ye + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "mtk-afe-platform-driver.h" +#include "mt8196-afe-common.h" +#include "mtk-afe-platform-driver.h" +#include "mtk-soundcard-driver.h" +#include "mtk-dsp-sof-common.h" +#include "mtk-soc-card.h" + +#include "../../codecs/nau8825.h" +#include "../../codecs/rt5682s.h" + +#define NAU8825_HS_PRESENT BIT(0) +#define RT5682S_HS_PRESENT BIT(1) +#define RT5650_HS_PRESENT BIT(2) + +/* + * Nau88l25 + */ +#define NAU8825_CODEC_DAI "nau8825-hifi" + +/* + * Rt5682s + */ +#define RT5682S_CODEC_DAI "rt5682s-aif1" + +/* + * Rt5650 + */ +#define RT5650_CODEC_DAI "rt5645-aif1" + +#define SOF_DMA_DL1 "SOF_DMA_DL1" +#define SOF_DMA_DL_24CH "SOF_DMA_DL_24CH" +#define SOF_DMA_UL0 "SOF_DMA_UL0" +#define SOF_DMA_UL1 "SOF_DMA_UL1" +#define SOF_DMA_UL2 "SOF_DMA_UL2" + +enum mt8196_jacks { + MT8196_JACK_HEADSET, + MT8196_JACK_DP, + MT8196_JACK_HDMI, + MT8196_JACK_MAX, +}; + +static struct snd_soc_jack_pin mt8196_dp_jack_pins[] = { + { + .pin = "DP", + .mask = SND_JACK_LINEOUT, + }, +}; + +static struct snd_soc_jack_pin mt8196_hdmi_jack_pins[] = { + { + .pin = "HDMI", + .mask = SND_JACK_LINEOUT, + }, +}; + +static struct snd_soc_jack_pin nau8825_jack_pins[] = { + { + .pin = "Headphone Jack", + .mask = SND_JACK_HEADPHONE, + }, + { + .pin = "Headset Mic", + .mask = SND_JACK_MICROPHONE, + }, +}; + +static const struct snd_kcontrol_new mt8196_dumb_spk_controls[] = { + SOC_DAPM_PIN_SWITCH("Ext Spk"), +}; + +static const struct snd_soc_dapm_widget mt8196_dumb_spk_widgets[] = { + SND_SOC_DAPM_SPK("Ext Spk", NULL), +}; + +static const struct snd_soc_dapm_widget mt8196_nau8825_widgets[] = { + SND_SOC_DAPM_HP("Headphone Jack", NULL), + SND_SOC_DAPM_MIC("Headset Mic", NULL), + SND_SOC_DAPM_SINK("DP"), +}; + +static const struct snd_kcontrol_new mt8196_nau8825_controls[] = { + SOC_DAPM_PIN_SWITCH("Headphone Jack"), + SOC_DAPM_PIN_SWITCH("Headset Mic"), +}; + +/* + * if need additional control for the ext spk amp that is connected + * after Lineout Buffer / HP Buffer on the codec, put the control in + * mt8196_mt6681_spk_amp_event() + */ +#define EXT_SPK_AMP_W_NAME "Ext_Speaker_Amp" + +static struct snd_soc_card mt8196_mt6681_soc_card; + +static const struct snd_soc_dapm_widget mt8196_mt6681_widgets[] = { +}; + +static const struct snd_soc_dapm_route mt8196_mt6681_routes[] = { +}; + +static const struct snd_kcontrol_new mt8196_mt6681_controls[] = { + SOC_DAPM_PIN_SWITCH(EXT_SPK_AMP_W_NAME), +}; + +/* + * define mtk_spk_i2s_mck node in dts when need mclk, + * BE i2s need assign snd_soc_ops = mt8196_mt6681_i2s_ops + */ +static int mt8196_mt6681_i2s_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + unsigned int rate = params_rate(params); + unsigned int mclk_fs_ratio = 128; + unsigned int mclk_fs = rate * mclk_fs_ratio; + struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0); + + return snd_soc_dai_set_sysclk(cpu_dai, + 0, mclk_fs, SND_SOC_CLOCK_OUT); +} + +static const struct snd_soc_ops mt8196_mt6681_i2s_ops = { + .hw_params = mt8196_mt6681_i2s_hw_params, +}; + +static int mt8196_dptx_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + unsigned int rate = params_rate(params); + unsigned int mclk_fs_ratio = 256; + unsigned int mclk_fs = rate * mclk_fs_ratio; + struct snd_soc_dai *dai = snd_soc_rtd_to_cpu(rtd, 0); + + return snd_soc_dai_set_sysclk(dai, 0, mclk_fs, SND_SOC_CLOCK_OUT); +} + +static const struct snd_soc_ops mt8196_dptx_ops = { + .hw_params = mt8196_dptx_hw_params, +}; + +static int mt8196_dptx_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + dev_info(rtd->dev, "fix format to 32bit\n"); + + /* fix BE i2s format to 32bit, clean param mask first */ + snd_mask_reset_range(hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT), + 0, (__force unsigned int)SNDRV_PCM_FORMAT_LAST); + + params_set_format(params, SNDRV_PCM_FORMAT_S32_LE); + + return 0; +} + +static int mt8196_i2s_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + dev_info(rtd->dev, "fix format to 32bit\n"); + + /* fix BE i2s format to 32bit, clean param mask first */ + snd_mask_reset_range(hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT), + 0, SNDRV_PCM_FORMAT_LAST); + + params_set_format(params, SNDRV_PCM_FORMAT_S32_LE); + return 0; +} + +static int mt8196_sof_be_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); + struct snd_soc_component *cmpnt_afe = NULL; + struct snd_soc_pcm_runtime *runtime; + + /* find afe component */ + for_each_card_rtds(rtd->card, runtime) { + cmpnt_afe = snd_soc_rtdcom_lookup(runtime, AFE_PCM_NAME); + if (cmpnt_afe) { + dev_info(rtd->dev, "component->name: %s\n", cmpnt_afe->name); + break; + } + } + + if (cmpnt_afe && !pm_runtime_active(cmpnt_afe->dev)) { + dev_err(rtd->dev, "afe pm runtime is not active!!\n"); + return -EINVAL; + } + + return 0; +} + +static const struct snd_soc_ops mt8196_sof_be_ops = { + .hw_params = mt8196_sof_be_hw_params, +}; + +static const struct sof_conn_stream g_sof_conn_streams[] = { + { + .sof_link = "AFE_SOF_DL1", + .sof_dma = SOF_DMA_DL1, + .stream_dir = SNDRV_PCM_STREAM_PLAYBACK + }, + { + .sof_link = "AFE_SOF_DL_24CH", + .sof_dma = SOF_DMA_DL_24CH, + .stream_dir = SNDRV_PCM_STREAM_PLAYBACK + }, + { + .sof_link = "AFE_SOF_UL0", + .sof_dma = SOF_DMA_UL0, + .stream_dir = SNDRV_PCM_STREAM_CAPTURE + }, + { + .sof_link = "AFE_SOF_UL1", + .sof_dma = SOF_DMA_UL1, + .stream_dir = SNDRV_PCM_STREAM_CAPTURE + }, + { + .sof_link = "AFE_SOF_UL2", + .sof_dma = SOF_DMA_UL2, + .stream_dir = SNDRV_PCM_STREAM_CAPTURE + }, +}; + +/* FE */ +SND_SOC_DAILINK_DEFS(playback1, + DAILINK_COMP_ARRAY(COMP_CPU("DL1")), + DAILINK_COMP_ARRAY(COMP_DUMMY()), + DAILINK_COMP_ARRAY(COMP_EMPTY())); +SND_SOC_DAILINK_DEFS(playback_24ch, + DAILINK_COMP_ARRAY(COMP_CPU("DL_24CH")), + DAILINK_COMP_ARRAY(COMP_DUMMY()), + DAILINK_COMP_ARRAY(COMP_EMPTY())); +SND_SOC_DAILINK_DEFS(capture0, + DAILINK_COMP_ARRAY(COMP_CPU("UL0")), + DAILINK_COMP_ARRAY(COMP_DUMMY()), + DAILINK_COMP_ARRAY(COMP_EMPTY())); +SND_SOC_DAILINK_DEFS(capture1, + DAILINK_COMP_ARRAY(COMP_CPU("UL1")), + DAILINK_COMP_ARRAY(COMP_DUMMY()), + DAILINK_COMP_ARRAY(COMP_EMPTY())); +SND_SOC_DAILINK_DEFS(capture2, + DAILINK_COMP_ARRAY(COMP_CPU("UL2")), + DAILINK_COMP_ARRAY(COMP_DUMMY()), + DAILINK_COMP_ARRAY(COMP_EMPTY())); +SND_SOC_DAILINK_DEFS(playback_hdmi, + DAILINK_COMP_ARRAY(COMP_CPU("HDMI")), + DAILINK_COMP_ARRAY(COMP_DUMMY()), + DAILINK_COMP_ARRAY(COMP_EMPTY())); +SND_SOC_DAILINK_DEFS(playback2, + DAILINK_COMP_ARRAY(COMP_CPU("DL2")), + DAILINK_COMP_ARRAY(COMP_DUMMY()), + DAILINK_COMP_ARRAY(COMP_EMPTY())); +SND_SOC_DAILINK_DEFS(capture_cm0, + DAILINK_COMP_ARRAY(COMP_CPU("UL_CM0")), + DAILINK_COMP_ARRAY(COMP_DUMMY()), + DAILINK_COMP_ARRAY(COMP_EMPTY())); +/* BE */ +SND_SOC_DAILINK_DEFS(ap_dmic, + DAILINK_COMP_ARRAY(COMP_CPU("AP_DMIC")), + DAILINK_COMP_ARRAY(COMP_DUMMY()), + DAILINK_COMP_ARRAY(COMP_EMPTY())); +SND_SOC_DAILINK_DEFS(ap_dmic_ch34, + DAILINK_COMP_ARRAY(COMP_CPU("AP_DMIC_CH34")), + DAILINK_COMP_ARRAY(COMP_DUMMY()), + DAILINK_COMP_ARRAY(COMP_EMPTY())); +SND_SOC_DAILINK_DEFS(ap_dmic_multich, + DAILINK_COMP_ARRAY(COMP_CPU("AP_DMIC_MULTICH")), + DAILINK_COMP_ARRAY(COMP_DUMMY()), + DAILINK_COMP_ARRAY(COMP_EMPTY())); +SND_SOC_DAILINK_DEFS(i2sin6, + DAILINK_COMP_ARRAY(COMP_CPU("I2SIN6")), + DAILINK_COMP_ARRAY(COMP_DUMMY()), + DAILINK_COMP_ARRAY(COMP_EMPTY())); +SND_SOC_DAILINK_DEFS(i2sout3, + DAILINK_COMP_ARRAY(COMP_CPU("I2SOUT3")), + DAILINK_COMP_ARRAY(COMP_DUMMY()), + DAILINK_COMP_ARRAY(COMP_EMPTY())); +SND_SOC_DAILINK_DEFS(i2sout4, + DAILINK_COMP_ARRAY(COMP_CPU("I2SOUT4")), + DAILINK_COMP_ARRAY(COMP_DUMMY()), + DAILINK_COMP_ARRAY(COMP_EMPTY())); +SND_SOC_DAILINK_DEFS(i2sout6, + DAILINK_COMP_ARRAY(COMP_CPU("I2SOUT6")), + DAILINK_COMP_ARRAY(COMP_DUMMY()), + DAILINK_COMP_ARRAY(COMP_EMPTY())); +SND_SOC_DAILINK_DEFS(tdm_dptx, + DAILINK_COMP_ARRAY(COMP_CPU("TDM_DPTX")), + DAILINK_COMP_ARRAY(COMP_DUMMY()), + DAILINK_COMP_ARRAY(COMP_EMPTY())); +SND_SOC_DAILINK_DEFS(AFE_SOF_DL_24CH, + DAILINK_COMP_ARRAY(COMP_CPU("SOF_DL_24CH")), + DAILINK_COMP_ARRAY(COMP_DUMMY()), + DAILINK_COMP_ARRAY(COMP_EMPTY())); +SND_SOC_DAILINK_DEFS(AFE_SOF_DL1, + DAILINK_COMP_ARRAY(COMP_CPU("SOF_DL1")), + DAILINK_COMP_ARRAY(COMP_DUMMY()), + DAILINK_COMP_ARRAY(COMP_EMPTY())); +SND_SOC_DAILINK_DEFS(AFE_SOF_UL0, + DAILINK_COMP_ARRAY(COMP_CPU("SOF_UL0")), + DAILINK_COMP_ARRAY(COMP_DUMMY()), + DAILINK_COMP_ARRAY(COMP_EMPTY())); +SND_SOC_DAILINK_DEFS(AFE_SOF_UL1, + DAILINK_COMP_ARRAY(COMP_CPU("SOF_UL1")), + DAILINK_COMP_ARRAY(COMP_DUMMY()), + DAILINK_COMP_ARRAY(COMP_EMPTY())); +SND_SOC_DAILINK_DEFS(AFE_SOF_UL2, + DAILINK_COMP_ARRAY(COMP_CPU("SOF_UL2")), + DAILINK_COMP_ARRAY(COMP_DUMMY()), + DAILINK_COMP_ARRAY(COMP_EMPTY())); + +static struct snd_soc_dai_link mt8196_mt6681_dai_links[] = { + /* + * The SOF topology expects PCM streams 0~4 to be available + * for the SOF PCM streams. Put the SOF BE definitions here + * so that the PCM device numbers are skipped over. + * (BE dailinks do not have PCM devices created.) + */ + { + .name = "AFE_SOF_DL_24CH", + .no_pcm = 1, + .playback_only = 1, + .ops = &mt8196_sof_be_ops, + SND_SOC_DAILINK_REG(AFE_SOF_DL_24CH), + }, + { + .name = "AFE_SOF_DL1", + .no_pcm = 1, + .playback_only = 1, + .ops = &mt8196_sof_be_ops, + SND_SOC_DAILINK_REG(AFE_SOF_DL1), + }, + { + .name = "AFE_SOF_UL0", + .no_pcm = 1, + .capture_only = 1, + .ops = &mt8196_sof_be_ops, + SND_SOC_DAILINK_REG(AFE_SOF_UL0), + }, + { + .name = "AFE_SOF_UL1", + .no_pcm = 1, + .capture_only = 1, + .ops = &mt8196_sof_be_ops, + SND_SOC_DAILINK_REG(AFE_SOF_UL1), + }, + { + .name = "AFE_SOF_UL2", + .no_pcm = 1, + .capture_only = 1, + .ops = &mt8196_sof_be_ops, + SND_SOC_DAILINK_REG(AFE_SOF_UL2), + }, + /* Front End DAI links */ + { + .name = "HDMI_FE", + .stream_name = "HDMI Playback", + .trigger = {SND_SOC_DPCM_TRIGGER_PRE, + SND_SOC_DPCM_TRIGGER_PRE}, + .dynamic = 1, + .playback_only = 1, + SND_SOC_DAILINK_REG(playback_hdmi), + }, + { + .name = "DL2_FE", + .stream_name = "DL2 Playback", + .trigger = {SND_SOC_DPCM_TRIGGER_PRE, + SND_SOC_DPCM_TRIGGER_PRE}, + .dynamic = 1, + .playback_only = 1, + SND_SOC_DAILINK_REG(playback2), + }, + { + .name = "UL_CM0_FE", + .stream_name = "UL_CM0 Capture", + .trigger = {SND_SOC_DPCM_TRIGGER_PRE, + SND_SOC_DPCM_TRIGGER_PRE}, + .dynamic = 1, + .capture_only = 1, + SND_SOC_DAILINK_REG(capture_cm0), + }, + { + .name = "DL_24CH_FE", + .stream_name = "DL_24CH Playback", + .trigger = {SND_SOC_DPCM_TRIGGER_PRE, + SND_SOC_DPCM_TRIGGER_PRE}, + .dynamic = 1, + .playback_only = 1, + SND_SOC_DAILINK_REG(playback_24ch), + }, + { + .name = "DL1_FE", + .stream_name = "DL1 Playback", + .trigger = {SND_SOC_DPCM_TRIGGER_PRE, + SND_SOC_DPCM_TRIGGER_PRE}, + .dynamic = 1, + .playback_only = 1, + SND_SOC_DAILINK_REG(playback1), + }, + { + .name = "UL0_FE", + .stream_name = "UL0 Capture", + .trigger = {SND_SOC_DPCM_TRIGGER_PRE, + SND_SOC_DPCM_TRIGGER_PRE}, + .dynamic = 1, + .capture_only = 1, + SND_SOC_DAILINK_REG(capture0), + }, + { + .name = "UL1_FE", + .stream_name = "UL1 Capture", + .trigger = {SND_SOC_DPCM_TRIGGER_PRE, + SND_SOC_DPCM_TRIGGER_PRE}, + .dynamic = 1, + .capture_only = 1, + SND_SOC_DAILINK_REG(capture1), + }, + { + .name = "UL2_FE", + .stream_name = "UL2 Capture", + .trigger = {SND_SOC_DPCM_TRIGGER_PRE, + SND_SOC_DPCM_TRIGGER_PRE}, + .dynamic = 1, + .capture_only = 1, + SND_SOC_DAILINK_REG(capture2), + }, + /* Back End DAI links */ + { + .name = "I2SIN6_BE", + .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS + | SND_SOC_DAIFMT_GATED, + .ops = &mt8196_mt6681_i2s_ops, + .no_pcm = 1, + .capture_only = 1, + .ignore_suspend = 1, + .be_hw_params_fixup = mt8196_i2s_hw_params_fixup, + SND_SOC_DAILINK_REG(i2sin6), + }, + { + .name = "I2SOUT4_BE", + .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS + | SND_SOC_DAIFMT_GATED, + .ops = &mt8196_mt6681_i2s_ops, + .no_pcm = 1, + .playback_only = 1, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .be_hw_params_fixup = mt8196_i2s_hw_params_fixup, + SND_SOC_DAILINK_REG(i2sout4), + }, + { + .name = "I2SOUT6_BE", + .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS + | SND_SOC_DAIFMT_GATED, + .ops = &mt8196_mt6681_i2s_ops, + .no_pcm = 1, + .playback_only = 1, + .ignore_suspend = 1, + .be_hw_params_fixup = mt8196_i2s_hw_params_fixup, + SND_SOC_DAILINK_REG(i2sout6), + }, + { + .name = "AP_DMIC_BE", + .no_pcm = 1, + .capture_only = 1, + .ignore_suspend = 1, + SND_SOC_DAILINK_REG(ap_dmic), + }, + { + .name = "AP_DMIC_CH34_BE", + .no_pcm = 1, + .capture_only = 1, + .ignore_suspend = 1, + SND_SOC_DAILINK_REG(ap_dmic_ch34), + }, + { + .name = "AP_DMIC_MULTICH_BE", + .no_pcm = 1, + .capture_only = 1, + .ignore_suspend = 1, + SND_SOC_DAILINK_REG(ap_dmic_multich), + }, + { + .name = "TDM_DPTX_BE", + .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS + | SND_SOC_DAIFMT_GATED, + .ops = &mt8196_dptx_ops, + .be_hw_params_fixup = mt8196_dptx_hw_params_fixup, + .no_pcm = 1, + .playback_only = 1, + .ignore_suspend = 1, + SND_SOC_DAILINK_REG(tdm_dptx), + }, + { + .name = "I2SOUT3_BE", + .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS + | SND_SOC_DAIFMT_GATED, + .ops = &mt8196_mt6681_i2s_ops, + .no_pcm = 1, + .playback_only = 1, + .ignore_suspend = 1, + SND_SOC_DAILINK_REG(i2sout3), + }, +}; + +static int mt8196_dumb_amp_init(struct snd_soc_pcm_runtime *rtd) +{ + struct snd_soc_card *card = rtd->card; + int ret = 0; + + ret = snd_soc_dapm_new_controls(&card->dapm, mt8196_dumb_spk_widgets, + ARRAY_SIZE(mt8196_dumb_spk_widgets)); + if (ret) { + dev_err(rtd->dev, "unable to add Dumb Speaker dapm, ret %d\n", ret); + return ret; + } + + ret = snd_soc_add_card_controls(card, mt8196_dumb_spk_controls, + ARRAY_SIZE(mt8196_dumb_spk_controls)); + if (ret) { + dev_err(rtd->dev, "unable to add Dumb card controls, ret %d\n", ret); + return ret; + } + + return 0; +} + +static int mt8196_dptx_codec_init(struct snd_soc_pcm_runtime *rtd) +{ + struct mtk_soc_card_data *soc_card_data = snd_soc_card_get_drvdata(rtd->card); + struct snd_soc_jack *jack = &soc_card_data->card_data->jacks[MT8196_JACK_DP]; + struct snd_soc_component *component = snd_soc_rtd_to_codec(rtd, 0)->component; + int ret = 0; + + ret = snd_soc_card_jack_new_pins(rtd->card, "DP Jack", SND_JACK_LINEOUT, + jack, mt8196_dp_jack_pins, + ARRAY_SIZE(mt8196_dp_jack_pins)); + if (ret) { + dev_err(rtd->dev, "new jack failed: %d\n", ret); + return ret; + } + + ret = snd_soc_component_set_jack(component, jack, NULL); + if (ret) { + dev_err(rtd->dev, "set jack failed on %s (ret=%d)\n", + component->name, ret); + return ret; + } + + return 0; +} + +static int mt8196_hdmi_codec_init(struct snd_soc_pcm_runtime *rtd) +{ + struct mtk_soc_card_data *soc_card_data = snd_soc_card_get_drvdata(rtd->card); + struct snd_soc_jack *jack = &soc_card_data->card_data->jacks[MT8196_JACK_HDMI]; + struct snd_soc_component *component = snd_soc_rtd_to_codec(rtd, 0)->component; + int ret = 0; + + ret = snd_soc_card_jack_new_pins(rtd->card, "HDMI Jack", SND_JACK_LINEOUT, + jack, mt8196_hdmi_jack_pins, + ARRAY_SIZE(mt8196_hdmi_jack_pins)); + if (ret) { + dev_err(rtd->dev, "new jack failed: %d\n", ret); + return ret; + } + + ret = snd_soc_component_set_jack(component, jack, NULL); + if (ret) { + dev_err(rtd->dev, "set jack failed on %s (ret=%d)\n", + component->name, ret); + return ret; + } + + return 0; +} + +static int mt8196_headset_codec_init(struct snd_soc_pcm_runtime *rtd) +{ + struct snd_soc_card *card = rtd->card; + struct mtk_soc_card_data *soc_card_data = snd_soc_card_get_drvdata(card); + struct snd_soc_jack *jack = &soc_card_data->card_data->jacks[MT8196_JACK_HEADSET]; + struct snd_soc_component *component = snd_soc_rtd_to_codec(rtd, 0)->component; + int ret; + int type; + + ret = snd_soc_dapm_new_controls(&card->dapm, mt8196_nau8825_widgets, + ARRAY_SIZE(mt8196_nau8825_widgets)); + if (ret) { + dev_err(rtd->dev, "unable to add nau8825 card widget, ret %d\n", ret); + return ret; + } + + ret = snd_soc_add_card_controls(card, mt8196_nau8825_controls, + ARRAY_SIZE(mt8196_nau8825_controls)); + if (ret) { + dev_err(rtd->dev, "unable to add nau8825 card controls, ret %d\n", ret); + return ret; + } + + ret = snd_soc_card_jack_new_pins(rtd->card, "Headset Jack", + SND_JACK_HEADSET | SND_JACK_BTN_0 | + SND_JACK_BTN_1 | SND_JACK_BTN_2 | + SND_JACK_BTN_3, + jack, + nau8825_jack_pins, + ARRAY_SIZE(nau8825_jack_pins)); + if (ret) { + dev_err(rtd->dev, "Headset Jack creation failed: %d\n", ret); + return ret; + } + + snd_jack_set_key(jack->jack, SND_JACK_BTN_0, KEY_PLAYPAUSE); + snd_jack_set_key(jack->jack, SND_JACK_BTN_1, KEY_VOICECOMMAND); + snd_jack_set_key(jack->jack, SND_JACK_BTN_2, KEY_VOLUMEUP); + snd_jack_set_key(jack->jack, SND_JACK_BTN_3, KEY_VOLUMEDOWN); + + type = SND_JACK_HEADSET | SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2 | SND_JACK_BTN_3; + ret = snd_soc_component_set_jack(component, jack, (void *)&type); + + if (ret) { + dev_err(rtd->dev, "Headset Jack call-back failed: %d\n", ret); + return ret; + } + + return 0; +}; + +static void mt8196_headset_codec_exit(struct snd_soc_pcm_runtime *rtd) +{ + struct snd_soc_component *component = snd_soc_rtd_to_codec(rtd, 0)->component; + + snd_soc_component_set_jack(component, NULL, NULL); +} + +static int mt8196_nau8825_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); + struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0); + unsigned int rate = params_rate(params); + unsigned int bit_width = params_width(params); + int clk_freq, ret; + + clk_freq = rate * 2 * bit_width; + + /* Configure clock for codec */ + ret = snd_soc_dai_set_sysclk(codec_dai, NAU8825_CLK_FLL_BLK, 0, + SND_SOC_CLOCK_IN); + if (ret < 0) { + dev_err(codec_dai->dev, "can't set BCLK clock %d\n", ret); + return ret; + } + + /* Configure pll for codec */ + ret = snd_soc_dai_set_pll(codec_dai, 0, 0, clk_freq, + params_rate(params) * 256); + if (ret < 0) { + dev_err(codec_dai->dev, "can't set BCLK: %d\n", ret); + return ret; + } + + return 0; +} + +static const struct snd_soc_ops mt8196_nau8825_ops = { + .hw_params = mt8196_nau8825_hw_params, +}; + +static int mt8196_rt5682s_i2s_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_card *card = rtd->card; + struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0); + struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0); + unsigned int rate = params_rate(params); + int bitwidth; + int ret; + + bitwidth = snd_pcm_format_width(params_format(params)); + if (bitwidth < 0) { + dev_err(card->dev, "invalid bit width: %d\n", bitwidth); + return bitwidth; + } + + ret = snd_soc_dai_set_tdm_slot(codec_dai, 0x00, 0x0, 0x2, bitwidth); + if (ret) { + dev_err(card->dev, "failed to set tdm slot\n"); + return ret; + } + + ret = snd_soc_dai_set_pll(codec_dai, RT5682S_PLL1, RT5682S_PLL_S_BCLK1, + rate * 32, rate * 512); + if (ret) { + dev_err(card->dev, "failed to set pll\n"); + return ret; + } + + dev_info(card->dev, "%s set mclk rate: %d\n", __func__, rate * 512); + + ret = snd_soc_dai_set_sysclk(codec_dai, RT5682S_SCLK_S_MCLK, + rate * 512, SND_SOC_CLOCK_IN); + if (ret) { + dev_err(card->dev, "failed to set sysclk\n"); + return ret; + } + + return snd_soc_dai_set_sysclk(cpu_dai, 0, rate * 512, + SND_SOC_CLOCK_OUT); +} + +static const struct snd_soc_ops mt8196_rt5682s_i2s_ops = { + .hw_params = mt8196_rt5682s_i2s_hw_params, +}; + +static int mt8196_mt6681_soc_card_probe(struct mtk_soc_card_data *soc_card_data, bool legacy) +{ + struct snd_soc_card *card = soc_card_data->card_data->card; + struct snd_soc_dai_link *dai_link; + bool init_nau8825 = false; + bool init_rt5682s = false; + bool init_rt5650 = false; + bool init_dumb = false; + int i; + + dev_info(card->dev, "legacy: %d\n", legacy); + + for_each_card_prelinks(card, i, dai_link) { + if (strcmp(dai_link->name, "TDM_DPTX_BE") == 0) { + if (dai_link->num_codecs && + strcmp(dai_link->codecs->dai_name, "snd-soc-dummy-dai")) + dai_link->init = mt8196_dptx_codec_init; + } else if (strcmp(dai_link->name, "I2SOUT3_BE") == 0) { + if (dai_link->num_codecs && + strcmp(dai_link->codecs->dai_name, "snd-soc-dummy-dai")) + dai_link->init = mt8196_hdmi_codec_init; + } else if (strcmp(dai_link->name, "I2SOUT6_BE") == 0 || + strcmp(dai_link->name, "I2SIN6_BE") == 0) { + if (!strcmp(dai_link->codecs->dai_name, NAU8825_CODEC_DAI)) { + dai_link->ops = &mt8196_nau8825_ops; + if (!init_nau8825) { + dai_link->init = mt8196_headset_codec_init; + dai_link->exit = mt8196_headset_codec_exit; + init_nau8825 = true; + } + } else if (!strcmp(dai_link->codecs->dai_name, RT5682S_CODEC_DAI)) { + dai_link->ops = &mt8196_rt5682s_i2s_ops; + if (!init_rt5682s) { + dai_link->init = mt8196_headset_codec_init; + dai_link->exit = mt8196_headset_codec_exit; + init_rt5682s = true; + } + } else if (!strcmp(dai_link->codecs->dai_name, RT5650_CODEC_DAI)) { + dai_link->ops = &mt8196_rt5682s_i2s_ops; + if (!init_rt5650) { + dai_link->init = mt8196_headset_codec_init; + dai_link->exit = mt8196_headset_codec_exit; + init_rt5650 = true; + } + } else { + if (strcmp(dai_link->codecs->dai_name, "snd-soc-dummy-dai")) { + if (!init_dumb) { + dai_link->init = mt8196_dumb_amp_init; + init_dumb = true; + } + } + } + } + } + + return 0; +} + +static const struct mtk_sof_priv mt8196_sof_priv = { + .conn_streams = g_sof_conn_streams, + .num_streams = ARRAY_SIZE(g_sof_conn_streams), +}; + +static struct snd_soc_card mt8196_mt6681_soc_card = { + .owner = THIS_MODULE, + .dai_link = mt8196_mt6681_dai_links, + .num_links = ARRAY_SIZE(mt8196_mt6681_dai_links), + .dapm_widgets = mt8196_mt6681_widgets, + .num_dapm_widgets = ARRAY_SIZE(mt8196_mt6681_widgets), + .dapm_routes = mt8196_mt6681_routes, + .num_dapm_routes = ARRAY_SIZE(mt8196_mt6681_routes), + .controls = mt8196_mt6681_controls, + .num_controls = ARRAY_SIZE(mt8196_mt6681_controls), +}; + +static const struct mtk_soundcard_pdata mt8196_evb_card = { + .card_name = "mt8196_mt6681", + .card_data = &(struct mtk_platform_card_data) { + .card = &mt8196_mt6681_soc_card, + .num_jacks = MT8196_JACK_MAX, + }, + .sof_priv = &mt8196_sof_priv, + .soc_probe = mt8196_mt6681_soc_card_probe, +}; + +static const struct mtk_soundcard_pdata mt8196_nau8825_card = { + .card_name = "mt8196_nau8825", + .card_data = &(struct mtk_platform_card_data) { + .card = &mt8196_mt6681_soc_card, + .num_jacks = MT8196_JACK_MAX, + .flags = NAU8825_HS_PRESENT + }, + .sof_priv = &mt8196_sof_priv, + .soc_probe = mt8196_mt6681_soc_card_probe, +}; + +static const struct mtk_soundcard_pdata mt8196_rt5682s_card = { + .card_name = "mt8196_rt5682s", + .card_data = &(struct mtk_platform_card_data) { + .card = &mt8196_mt6681_soc_card, + .num_jacks = MT8196_JACK_MAX, + .flags = RT5682S_HS_PRESENT + }, + .sof_priv = &mt8196_sof_priv, + .soc_probe = mt8196_mt6681_soc_card_probe, +}; + +static const struct mtk_soundcard_pdata mt8196_rt5650_card = { + .card_name = "mt8196_rt5650", + .card_data = &(struct mtk_platform_card_data) { + .card = &mt8196_mt6681_soc_card, + .num_jacks = MT8196_JACK_MAX, + .flags = RT5650_HS_PRESENT + }, + .sof_priv = &mt8196_sof_priv, + .soc_probe = mt8196_mt6681_soc_card_probe, +}; + +static const struct of_device_id mt8196_mt6681_dt_match[] = { + {.compatible = "mediatek,mt8196-mt6681-sound", .data = &mt8196_evb_card,}, + {.compatible = "mediatek,mt8196-nau8825-sound", .data = &mt8196_nau8825_card,}, + {.compatible = "mediatek,mt8196-rt5682s-sound", .data = &mt8196_rt5682s_card,}, + {.compatible = "mediatek,mt8196-rt5650-sound", .data = &mt8196_rt5650_card,}, + {} +}; +MODULE_DEVICE_TABLE(of, mt8196_mt6681_dt_match); + +static struct platform_driver mt8196_mt6681_driver = { + .driver = { + .name = "mt8196-mt6681", + .of_match_table = mt8196_mt6681_dt_match, + .pm = &snd_soc_pm_ops, + }, + .probe = mtk_soundcard_common_probe, +}; +module_platform_driver(mt8196_mt6681_driver); + +/* Module information */ +MODULE_DESCRIPTION("MT8196 mt6681 ALSA SoC machine driver"); +MODULE_AUTHOR("Darren Ye "); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("mt8196 mt6681 soc card"); + From patchwork Mon Apr 7 12:06:35 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Darren.Ye" X-Patchwork-Id: 878789 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 15A4724EF8E; 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Mon, 07 Apr 2025 20:11:16 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Mon, 7 Apr 2025 20:11:14 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Mon, 7 Apr 2025 20:11:14 +0800 From: Darren.Ye To: Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Jaroslav Kysela , Takashi Iwai , Linus Walleij , Bartosz Golaszewski CC: , , , , , , Darren Ye Subject: [PATCH v2 11/11] ASoC: dt-bindings: mediatek,mt8196-mt6681: add mt8196-mt6681 document Date: Mon, 7 Apr 2025 20:06:35 +0800 Message-ID: <20250407120708.26495-12-darren.ye@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250407120708.26495-1-darren.ye@mediatek.com> References: <20250407120708.26495-1-darren.ye@mediatek.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N From: Darren Ye Add document for mt8196 board with mt6681. Signed-off-by: Darren Ye --- .../sound/mediatek,mt8196-mt6681.yaml | 114 ++++++++++++++++++ 1 file changed, 114 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/mediatek,mt8196-mt6681.yaml diff --git a/Documentation/devicetree/bindings/sound/mediatek,mt8196-mt6681.yaml b/Documentation/devicetree/bindings/sound/mediatek,mt8196-mt6681.yaml new file mode 100644 index 000000000000..2c1b0df05c27 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/mediatek,mt8196-mt6681.yaml @@ -0,0 +1,114 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/mediatek,mt8196-mt6681.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT8196 ASoC sound card + +maintainers: + - Darren Ye + +allOf: + - $ref: sound-card-common.yaml# + +properties: + compatible: + oneOf: + - enum: + - mediatek,mt8196-mt6681-sound + - mediatek,mt8196-nau8825-sound + - mediatek,mt8196-rt5682s-sound + - mediatek,mt8196-rt5650-sound + + audio-routing: + description: + Valid names could be the input or output widgets of audio components, + power supplies, MicBias of codec and the software switch. + + mediatek,platform: + $ref: /schemas/types.yaml#/definitions/phandle + description: The phandle of MT8188 ASoC platform. + + mediatek,adsp: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The phandle of the MT8188 ADSP platform, which is the optional Audio DSP + hardware that provides additional audio functionalities if present. + The AFE will link to ADSP when the phandle is provided. + +patternProperties: + "^dai-link-[0-9]+$": + type: object + description: + Container for dai-link level properties and CODEC sub-nodes. + + properties: + link-name: + description: + This property corresponds to the name of the BE dai-link to which + we are going to update parameters in this node. + items: + enum: + - TDM_DPTX_BE + - I2SOUT6_BE + - I2SIN6_BE + - I2SOUT4_BE + - I2SOUT3_BE + + codec: + description: Holds subnode which indicates codec dai. + type: object + additionalProperties: false + properties: + sound-dai: + minItems: 1 + maxItems: 2 + required: + - sound-dai + + dai-format: + description: audio format. + items: + enum: + - i2s + - right_j + - left_j + - dsp_a + - dsp_b + + mediatek,clk-provider: + $ref: /schemas/types.yaml#/definitions/string + description: Indicates dai-link clock master. + items: + enum: + - cpu + - codec + + additionalProperties: false + + required: + - link-name + +unevaluatedProperties: false + +required: + - compatible + - mediatek,platform + +examples: + - | + sound { + compatible = "mediatek,mt8196-mt6681-sound"; + model = "mt8196-mt6681"; + mediatek,platform = <&afe>; + dai-link-0 { + link-name = "I2SOUT6_BE"; + dai-format = "i2s"; + mediatek,clk-provider = "cpu"; + codec { + sound-dai = <&nau8825>; + }; + }; + }; +