From patchwork Wed Apr 9 14:38:19 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 879574 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C1719266B5C for ; Wed, 9 Apr 2025 14:38:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744209507; cv=none; b=AjapbHAaHzpkZ8nEGgSS9OYl3XlyehOGKeeGUVW2VtI4cvbPm29rTC7/fq1eG/BxQwkrGJi3swzyKWmuXW9QD8wF97oGrnJDsAyyiramrIq7pLdAOwmKPvMVNlS9leM6NfRMfScG+ofn+qm1Ly/XSxhkopcd2aQBZcE0HxztJY0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744209507; c=relaxed/simple; bh=ykuyFmkKMHJIXqo4oh3w0kqcgoBIO3smwRfR/rRJkQQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qknA6VEjM0cX1InaWwjXM7BZ66pm1cNY3eeVy9s4UlC7OrxAMC+9xrm1jVdci8ElX5h1RBbTIcS8oW5iUyAHi0cvZrCOaISrBOFNFd5rbU9pVmpLoR6cBrW33bFSJ22FtglEo9qyRTKdcw2BS/QeORji73/LjyA8QPoFIOLh9J0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=nEzRlp4u; arc=none smtp.client-ip=209.85.128.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="nEzRlp4u" Received: by mail-wm1-f54.google.com with SMTP id 5b1f17b1804b1-43d2d952eb1so46364875e9.1 for ; Wed, 09 Apr 2025 07:38:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1744209504; x=1744814304; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=sYQ/bnYqcpDq9DEnr3MypQ+/gd8s486fsMpMYGxMvlw=; b=nEzRlp4uL+dlibbh5aRCl/+0l+86lLLmXD7kDzuy/oAxBgdsBTZssqFa73RZyJiXqQ rb/6tejrcOZkltBhp+UUWOVA8VFEx75elaX8SxcXBTOuTpt2y7hX+U+45imdMeQEGU/q MIfLrY2PJBdARnJh90O21virJcXVJ240uEwDpeutgG0NgF419r+HRxdfuPmpQWOyU7Zg cREnZZVp98jhw8GL+LUBdRcD6uD+BCnOd1qkhRC6LEb3AvFQzIXou4m2mPeYs8qYcB8T jlIP5g2f2zSkfBaQV1mw95Xsgvl0PEY14UnZaOg4caCFNTxygyIoKVc/VltQvXNhvV27 Y0KA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744209504; x=1744814304; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sYQ/bnYqcpDq9DEnr3MypQ+/gd8s486fsMpMYGxMvlw=; b=gfibWOVn4zj2woOUcaPlsoayJoeYNucoTA1wg48+NLNWDJMAcgL+FWObi6N4W01QsT BiAt3zlUn8coz3GukQUE8SXv7ZQV9rBwpubuvUFX4/pfPdSna9NvmnNh20jwXUG1uKEM WpsAIEoWvstui4z/U+ct3oz7nJTZ95Ja1W/ZV9CasxDOqLNRfGebrAXFl27ASmJ0sBhk GkVnRie6U3rxtxb2lFonSc4K/iaUPerkyYyrL9dPxFTALj94ZXlOliq2noKxI6gcO1Ti t0Ahv0Cp5rdrDPCWaNfCsC1SuvMMX122s05e2iLmgp+zGFeDhe/Mev0VRnJu3kyLHCQM uFXA== X-Gm-Message-State: AOJu0YzfFplOMzMXfniAY+SSPAG+3Q0XW0zqPW5l3u+TjGrA/y0ceWzE UbOrorAcQbEZaUTquD9nzWrDl4XH1z754vwSoONcWbf51Uf3t6m0VMwWzzwgwlw= X-Gm-Gg: ASbGncuy+KzjxMaLKvP9kCTZvBSVeHR2HmoOexrN4p9h11f93PkcgN0lgVXFdXR48nO kgjHGAHsAH0VSvVBrCd6DrMYUSJQL6oJlHZGopKHVDApk2s9UkiHPm7/M7KHEUuDzhoGshLoY50 aPz/y3R82LQTV179gFwnAZZGf9stbbgY4U0+525cYhfc0K72KDMA0eIfJcLCMLGGgoyVBq8eLBI rKThu3azLs/FHsyf19UqrG6m8gNcrdbVZD8y/S1JzJg2zOpfSBBqZVMi13XhEP3QBJhj4/4CfIb zvAfWMxB8Xi0YoQWdM3wJ9tnI/BgfNg0WAM9soDi7ft8okHJQjyByWooSWRXlg== X-Google-Smtp-Source: AGHT+IHBnGtNRTilaYkQryGLO6hs4vpGuvJNAjg8RNrmh30sh0SKTKByJcmqQwo4ghfIwNENcwpzGQ== X-Received: by 2002:a05:600c:55ca:b0:43c:ea40:ae4a with SMTP id 5b1f17b1804b1-43f1fde42e8mr25153405e9.31.1744209503989; Wed, 09 Apr 2025 07:38:23 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:3d9:2080:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43f20625ea4sm22222045e9.12.2025.04.09.07.38.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Apr 2025 07:38:23 -0700 (PDT) From: Neil Armstrong Date: Wed, 09 Apr 2025 16:38:19 +0200 Subject: [PATCH v4 1/6] dt-bindings: media: qcom,sm8550-iris: document SM8650 IRIS accelerator Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250409-topic-sm8x50-iris-v10-v4-1-40e411594285@linaro.org> References: <20250409-topic-sm8x50-iris-v10-v4-0-40e411594285@linaro.org> In-Reply-To: <20250409-topic-sm8x50-iris-v10-v4-0-40e411594285@linaro.org> To: Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong , Bryan O'Donoghue X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2152; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=ykuyFmkKMHJIXqo4oh3w0kqcgoBIO3smwRfR/rRJkQQ=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBn9oZbqUk7+4Co9bAwU7Lfb6Svl5ni40t2RvGf8cyp p54a6q6JAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZ/aGWwAKCRB33NvayMhJ0S2vD/ 9WM3g7GrOBIAgQwXCU7ZN2BzAaQmCb/MGgHu8su481EJGYW1UE8VNTMOHRfe5iWBxP29n1LXpOR4lU BtDQ+J2lE+b1bokQMjC8gY2im46/0iPm9pPo6Ag5TBNnUqSMUiqXl3dlg7G/l/Ytl4SX1Us1uv1LKM YvvqZek/7WLayD2hBy8sCR77FUO5JYGAbZMdwWRbQNbm2Sp+0yffvT+3RwWZK3I+SXRIaRmBLUrEsI 6+lCKGRGosKAj1nRQsNuUDaW9gGJuSBc6Sg7s+XHJrTlMrQqmqKGKvfnuEcUThTK75sx0QyZ/TamkO 7nHaohLjKizJVSfkjHscTG6LAHExseJ8FVNe4db45KehCx+0rNrAVjb5m8vDBGkCd+NhMo3ozohjIo MDtaa+iMaRyHUTtGz90dQxoV8C2T2liwFIq2uirv996rPWH/UH0yAZOyoJAwj8e18GgdzW5/V2/gxV vhDGOOZjz9655yRu/E8KKIuMhWn9HNXcGdWfz+ialAdfBv7sYcrUMC9krpuNkAaHBgjf8cjhfoVTv0 QiKUzj9j1W1Lnj01aK8+cZoDvgnBSn7jJjXizWJt2jOX+8MkkplbxQNbKM3OpicPPSKGclgkUdegkz vQItKhK1GMQ0npAGOS0BhRPEgogoB04p7cJE2Jvq2gr6Ea79fFjJQ2ptOhbw== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Document the IRIS video decoder and encoder accelerator found in the SM8650 platform, it requires 2 more reset lines in addition to the properties required for the SM8550 platform. Reviewed-by: Rob Herring (Arm) Reviewed-by: Vikash Garodia Reviewed-by: Bryan O'Donoghue Tested-by: Bryan O'Donoghue # x1e Dell Signed-off-by: Neil Armstrong --- .../bindings/media/qcom,sm8550-iris.yaml | 33 ++++++++++++++++++---- 1 file changed, 28 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml b/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml index e424ea84c211f473a799481fd5463a16580187ed..536cf458dcb08141e5a1ec8c3df964196e599a57 100644 --- a/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml +++ b/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml @@ -14,12 +14,11 @@ description: The iris video processing unit is a video encode and decode accelerator present on Qualcomm platforms. -allOf: - - $ref: qcom,venus-common.yaml# - properties: compatible: - const: qcom,sm8550-iris + enum: + - qcom,sm8550-iris + - qcom,sm8650-iris power-domains: maxItems: 4 @@ -49,11 +48,15 @@ properties: - const: video-mem resets: - maxItems: 1 + minItems: 1 + maxItems: 3 reset-names: + minItems: 1 items: - const: bus + - const: xo + - const: core iommus: maxItems: 2 @@ -75,6 +78,26 @@ required: - iommus - dma-coherent +allOf: + - $ref: qcom,venus-common.yaml# + - if: + properties: + compatible: + enum: + - qcom,sm8650-iris + then: + properties: + resets: + minItems: 3 + reset-names: + minItems: 3 + else: + properties: + resets: + maxItems: 1 + reset-names: + maxItems: 1 + unevaluatedProperties: false examples: From patchwork Wed Apr 9 14:38:20 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 880781 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B29DD266B4C for ; Wed, 9 Apr 2025 14:38:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744209509; cv=none; b=NAanF2hXNprWnt2OwRYeOtJ8aMoECl14qtTbrpI613Z515Va5sBLzGvyZC7t6uA9wS/H8iZy6RNcFAo2ZJCZ1/9htgCUs68sCCzZBY788/akbIjiLwOY2I0f+evRzN/AcBOowmuLIawCXgH03iQ4sisHPr1qU2YzLYj+bDdLnmY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744209509; c=relaxed/simple; bh=ynWcQw0Q/G8mNhYBlkWYNYw4t7oNSEG+zaX/r1AekVc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Z4hHZYghSGnPmXYKmWNSkejI8KJ/Tzc0TOliPqeyCQ+srQmirSVfq/5SlyQH3GKfQMsVqWUOcoC+c5j4Mwp4W+i6oUYAHcOpqoBUetgSCWCcDM+xQ6xBl6TjjHlT/TGUwWcqwhHAb7AuiVtk0DN7A7IpswpJsMpUoBe72U6xUcg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=kuPBdu0a; arc=none smtp.client-ip=209.85.128.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="kuPBdu0a" Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-43ed8d32a95so43338965e9.3 for ; Wed, 09 Apr 2025 07:38:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1744209505; x=1744814305; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=LbEQGTRsZtj+cgrt9s8r7Nmi1WRj8PxAdZ+rmqSr64E=; b=kuPBdu0a8xy1+wDmeJQGoevLk48bPNDTXm/TwOtjYZF3jumIzMx9K2jRE+oSTvVYtz VvN1yGl16gEmP0tgskUURCYXva05GZue5Y5NrW4fQVNqwM9wos/tgGGh1q2Ohpy+ONrT nN6erjOHiLcmq1k7TcSNq0JY996GO8iNFhL9iYf5cGLTpd5eYI4gqZX86oPvnlw9QORb zdjLitgWTMNpxiNT1mOfaj3Grnm51BB+7Ht3+itnFomVutcVgaSgegCtoHJ9uMOEQeqR ykCbsW4lLy3bsDqmWJWOampC9MgxZUClVpC8b2ilYeRvfa8mODB8A8/3IOcuXb3zSlt0 T0XQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744209505; x=1744814305; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LbEQGTRsZtj+cgrt9s8r7Nmi1WRj8PxAdZ+rmqSr64E=; b=R4ZPPsVn4tY5B9MkChA+XTDVNbzEKkKfumd8BPw7kRhN6/tSP5cd4smqbKINQ72z+Y 8832A6u5cUJpXYdrhs4562tJpDVuRq477jvM8I0KvMx8AzkCA/kTLahY/eeGP0YDxk+X 5nOGkeWfmdFkqapA1wDwknuCQO8VUbUk7E6a2eYj6PxCFEa9/+73qmqexqPmt/NMvwSn uB+bLX61hm2tnyLr057kl/hJh2PhOLMvJ5xQrBIyMjt+f5tdmNap1Jpj+35dXl3gibGw AM6RAminJTzqO4CLyi4HVPecVp5uSz56kvqVo1VGBfu+ohm8a3IP11ookqyA3PSXrftO xDZw== X-Gm-Message-State: AOJu0YxYBJMiOy5ArcXVJax5NnLCcCywhzDMSe+ZC2hMf7uH2JS+I4pe 6yzFNMlXC8b2HUO/R3TYo63QMmYLKWmmVkYCp+ZozTi4c0ZQjpF8QQzxpS16nNk= X-Gm-Gg: ASbGncsHGHQTIhu2SnpI56AFsfa1/ojLthTOfXXoBjszQotQzdMdenw+JBTbyRNIiFd D+axwSNYUwoDll1xAaKMhNlKB+YFTmiVkWVUt/6qAkSKA/QychV+gqlV9xThNPZnb8+XvdZleFj RRlzcIunczaJj7dBc2LTnRwdshPd2ZsXDp6GLxIHEtKSSsKNpulRHeUb90zHC7zDou4BmZBb4YL qkbGBe1xpH1fpX4S1LJ/WdBg708BRbNetvp9+664OL3xTALoKqaa9KaYQdUof9j8cN4Wf6p7YtZ 5P5CZ5I4/Q5goaRQr0sfIrAyY4HJgVzr4p9MqRS3bbSWgYPN13lJA77vDyvpEw== X-Google-Smtp-Source: AGHT+IFMDpE0Jb1zFAxpZjczOiEbcPC8E8M1ybhy9jl68Nr4PqP3Z7DKhUV/1ZjX1CVkneA2wf+/5A== X-Received: by 2002:a05:600c:1c28:b0:43b:c95f:fd9 with SMTP id 5b1f17b1804b1-43f1ec7cbfcmr20225845e9.5.1744209504764; Wed, 09 Apr 2025 07:38:24 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:3d9:2080:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43f20625ea4sm22222045e9.12.2025.04.09.07.38.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Apr 2025 07:38:24 -0700 (PDT) From: Neil Armstrong Date: Wed, 09 Apr 2025 16:38:20 +0200 Subject: [PATCH v4 2/6] media: platform: qcom/iris: add power_off_controller to vpu_ops Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250409-topic-sm8x50-iris-v10-v4-2-40e411594285@linaro.org> References: <20250409-topic-sm8x50-iris-v10-v4-0-40e411594285@linaro.org> In-Reply-To: <20250409-topic-sm8x50-iris-v10-v4-0-40e411594285@linaro.org> To: Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong , Bryan O'Donoghue X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3924; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=ynWcQw0Q/G8mNhYBlkWYNYw4t7oNSEG+zaX/r1AekVc=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBn9oZcEew921sqnFFz5PURZPLLPMvPpDrt1epa0lRh MXCUAzmJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZ/aGXAAKCRB33NvayMhJ0c6tD/ 9jkUuxJUKjxIHBgbrrDRsLyAfcIxIz8OsruD1go/P24RWeo+u7xktLSR3LmZAvdZCsbtt5XyKrwYzy 3EGCjiudShuGwNbXm3OuzTyO8lqYI1NtgtghcgEzOaIzJM/0SspL+MG5xiW/EY3Ml25vBCt040X4E2 CCPOY7L/ldi6IoDa1gW8HU9H3kksbdfGxPmQyL1uiLvibJPkK9iUtjxnQH5O6nLrl5mqXHup0jBPYg ojWOwn/RCeHAXgwlNDZaHf8bv5qdzglk9pj6Gwv5WTirXbpkurmFrH8fMhOVlAb8vxeO4RszTS8Sze HNlk4J1eDN4N4DC0VTywWwd++Tr18CEbL5liZTYGT4/qT56WVu3Oju4x+powu5jeo6yNmKvrQGUHdc 0p/4zUHXENuaRboNm7UFYFC/0AUIvLGCPibB88upPTtGgM4GO+PyyHqzhVcDeD9Gq7rPijVl5sqECs lBKZQFOydEA92rrWPYqREOay98Yc2M3yLKJxGVLZh6Li/TUAXgjIwdbL6FjBDq5+x8acv092kY+OeF DOYM9qKj6p+h3B8LVTDkFIj4fKJyxDwHQxSSf7HRKz4sX6tSurmOQi72eb8C3zghl7mE4RRR446+sa DZCSYEVG39aDs49r8VUqjXa28EppoBRQA0H33lR9k0IM0DrpkJB+Anblt9EA== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE In order to support the SM8650 iris33 hardware, we need to provide a specific constoller power off sequences via the vpu_ops callbacks. Add the callback, and use the current helper for currently supported platforms. Reviewed-by: Bryan O'Donoghue Reviewed-by: Dikshita Agarwal Tested-by: Bryan O'Donoghue # x1e Dell Signed-off-by: Neil Armstrong --- drivers/media/platform/qcom/iris/iris_vpu2.c | 1 + drivers/media/platform/qcom/iris/iris_vpu3.c | 1 + drivers/media/platform/qcom/iris/iris_vpu_common.c | 4 ++-- drivers/media/platform/qcom/iris/iris_vpu_common.h | 2 ++ 4 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_vpu2.c b/drivers/media/platform/qcom/iris/iris_vpu2.c index 8f502aed43ce2fa6a272a2ce14ff1ca54d3e63a2..7cf1bfc352d34b897451061b5c14fbe90276433d 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu2.c +++ b/drivers/media/platform/qcom/iris/iris_vpu2.c @@ -34,5 +34,6 @@ static u64 iris_vpu2_calc_freq(struct iris_inst *inst, size_t data_size) const struct vpu_ops iris_vpu2_ops = { .power_off_hw = iris_vpu_power_off_hw, + .power_off_controller = iris_vpu_power_off_controller, .calc_freq = iris_vpu2_calc_freq, }; diff --git a/drivers/media/platform/qcom/iris/iris_vpu3.c b/drivers/media/platform/qcom/iris/iris_vpu3.c index b484638e6105a69319232f667ee7ae95e3853698..13dab61427b8bd0491b69a9bc5f5144d27d17362 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu3.c +++ b/drivers/media/platform/qcom/iris/iris_vpu3.c @@ -118,5 +118,6 @@ static u64 iris_vpu3_calculate_frequency(struct iris_inst *inst, size_t data_siz const struct vpu_ops iris_vpu3_ops = { .power_off_hw = iris_vpu3_power_off_hardware, + .power_off_controller = iris_vpu_power_off_controller, .calc_freq = iris_vpu3_calculate_frequency, }; diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c index fe9896d66848cdcd8c67bd45bbf3b6ce4a01ab10..268e45acaa7c0e3fe237123c62f0133d9dface14 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -211,7 +211,7 @@ int iris_vpu_prepare_pc(struct iris_core *core) return -EAGAIN; } -static int iris_vpu_power_off_controller(struct iris_core *core) +int iris_vpu_power_off_controller(struct iris_core *core) { u32 val = 0; int ret; @@ -264,7 +264,7 @@ void iris_vpu_power_off(struct iris_core *core) { dev_pm_opp_set_rate(core->dev, 0); core->iris_platform_data->vpu_ops->power_off_hw(core); - iris_vpu_power_off_controller(core); + core->iris_platform_data->vpu_ops->power_off_controller(core); iris_unset_icc_bw(core); if (!iris_vpu_watchdog(core, core->intr_status)) diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/media/platform/qcom/iris/iris_vpu_common.h index 63fa1fa5a4989e48aebdb6c7619c140000c0b44c..f8965661c602f990d5a7057565f79df4112d097e 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h @@ -13,6 +13,7 @@ extern const struct vpu_ops iris_vpu3_ops; struct vpu_ops { void (*power_off_hw)(struct iris_core *core); + int (*power_off_controller)(struct iris_core *core); u64 (*calc_freq)(struct iris_inst *inst, size_t data_size); }; @@ -22,6 +23,7 @@ void iris_vpu_clear_interrupt(struct iris_core *core); int iris_vpu_watchdog(struct iris_core *core, u32 intr_status); int iris_vpu_prepare_pc(struct iris_core *core); int iris_vpu_power_on(struct iris_core *core); +int iris_vpu_power_off_controller(struct iris_core *core); void iris_vpu_power_off_hw(struct iris_core *core); void iris_vpu_power_off(struct iris_core *core); From patchwork Wed Apr 9 14:38:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 879573 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9E05E266F1C for ; Wed, 9 Apr 2025 14:38:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744209511; cv=none; b=fFUxP5ksI7NFZU0QzRv04jEth/k+U02ubw7SsKTsJ9j/Bdl/UIpMXmZGXVvgZ1nDDsj0IE6rLAnpQvbRT9hcaAd/uNggvcoYwhyna3/TK13QmKS+qjPs7pZk4S8GY6CNL6hJNc2PzXR9V20fS5A6W7Jo/A2ZasgZzf6+GpWHgrA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744209511; c=relaxed/simple; bh=UkC2xQ49cwtjimQJomEXRVHWedJyZAC8YoJhIXvmiUg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Ml1vlIsHh+MUUwbBI3WLILMeFvqNcJB490+3VxqroIIQOUJTlu71V2VCSjnFE8Zrgc+MiZt9SoIGMn1e2V/fKeHM2QFRR7vvWnHCAYdWtG1OaKrrM2kscGk7wbnzvE8w7aVwnu/etM1osNaRggD724x/FeYjr1Mg3zfcLUunU7A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=WkT/X41n; arc=none smtp.client-ip=209.85.128.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="WkT/X41n" Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-43cfa7e7f54so6099945e9.1 for ; Wed, 09 Apr 2025 07:38:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1744209506; x=1744814306; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Bo4P1zkBy5ZJ7KB9fJf8Jg+rHcpVMabyPlCyrK4lEHg=; b=WkT/X41n9slZelJ0f+IjYW4dktevFl1kI5tUYrvL+tBgdXywaca2arAOIjTTr5OVf4 1wXIwWEQAjzavsv7ATR4yqQAYx6ETzjyEvSi2Z57zOArhF/1cqoBH1j4JpG10ovuyZZu DuN4BLj84QAMWcNJyW1oszIsM3JALKZ1Q9nTmf2CFhfksyhafgW4fMCVCFpcFClrl7W8 u1w+pUOrVeUWugJSyJL6jug3ZOZVD1sZmBRg0iapmtDYowDGsHgavCfERrapOLH+sERA DqprAH+t5dx0AruHB9EFzZXtKB5X58PUyrcbO76BWNYJ0sZDgJWQd/+1bx30458Osprm 26vA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744209506; x=1744814306; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Bo4P1zkBy5ZJ7KB9fJf8Jg+rHcpVMabyPlCyrK4lEHg=; b=VxwvzknqAioRJnFrjsL0tPy0l2CAjVoWgp7wEsvBLxqYTosEMkkC9/J7U995wQTVhZ ip4dvuvlSPuHykKK3B1f7AjrgfcnyQa53MaLpHXsEnOsMPRhZtzl5xqjDb0bhQgwf0rH s3cKvKjhu+iIY2CJQrfIoiP65JGAfMObKQrCyUpmfAPQhay1a7JiCLOLgTcQP+ykl1bB DmktCXddYZ+xb7hewTtnIiREUMmvIH6+jnU/wSmnu3K7u8HXwVQCRMJgHYU3FF1V157G QSTfO3oasdY5U9ueEZwacr+lOlJhJOJQoPZ/54AhjL/gXLiy/H0wecRV7giCNs9zdoHY n2JQ== X-Gm-Message-State: AOJu0YzVXtji3y0EjuOng8tgkEgAYPWCV4zaznsXp8iZKib7/SCT6ke4 vMuXvVxQNcFQy5apJfdUbi4DSwT6Q5TOI6hGa89i2BHhKBPJF1RcqnP3szNYBIU= X-Gm-Gg: ASbGncswMm8w6rVwQ018KFVYpqBQDMDns/eO3NFAMM61WKCdVxylnVz5vOChJXtS1BF 8uD6YcJC/lDz8VkxALbD9mwHdDkJmzGF7FYi0UjWizUBylPrWVo9+HeWgQFJkHpF6GNClCKhlf8 MaeJ+ScDyOtp/yI05muoRKUC3mCKA9cOVvwYUg0k4LHIjzbSb9nrFckQ4906LcwR+oJtgwAAqZ5 5OKOU61PNKQrtmKJ6dKbtj3e1s+rqsFopzxMnIRx36A9sFcYxyJMt7ugaoldjhbRaJ+6hWY829i 8pmv/EQQjJg3IAkUu5igHmMyg/iS+2iWPnjy1c2363TPS+VgohGYCKLmissCqw== X-Google-Smtp-Source: AGHT+IFv7vvZGkXcHBNRCdhKTeLeBp4cYIuYHhGaihx/MrjaTEN7nvEzCapEn3UnIS2n9HKlMs6wyg== X-Received: by 2002:a05:600c:2151:b0:43b:bb72:1dce with SMTP id 5b1f17b1804b1-43f0e55ecc4mr57604475e9.5.1744209505740; Wed, 09 Apr 2025 07:38:25 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:3d9:2080:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43f20625ea4sm22222045e9.12.2025.04.09.07.38.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Apr 2025 07:38:25 -0700 (PDT) From: Neil Armstrong Date: Wed, 09 Apr 2025 16:38:21 +0200 Subject: [PATCH v4 3/6] media: platform: qcom/iris: introduce optional controller_rst_tbl Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250409-topic-sm8x50-iris-v10-v4-3-40e411594285@linaro.org> References: <20250409-topic-sm8x50-iris-v10-v4-0-40e411594285@linaro.org> In-Reply-To: <20250409-topic-sm8x50-iris-v10-v4-0-40e411594285@linaro.org> To: Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong , Bryan O'Donoghue X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4061; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=UkC2xQ49cwtjimQJomEXRVHWedJyZAC8YoJhIXvmiUg=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBn9oZcV7CVwIn1ST/ZBfpW97oqY5UNsIXiraUmG0sV jy96y86JAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZ/aGXAAKCRB33NvayMhJ0d6HD/ wJFG8FstjJU+by0UVFSAK7fztkHtey1OapUAeLcrAeOp/+KCVrUjr37A2sRZskOOqe7ybZFgsBuCwB wsKPhl9YJqR6ej5WIYHfrsP/3/rX5OZWM5P2TnRMPv+Y8XoZXYTRn+feo/f6+PKnTo03dYSmVPkaUS KQcNULUdQc4fsKPKtwIcfT8+H9j9NyxzL3Ws27HNzYTKxLvtolrv2YqurKjxk6b5tNLZducEZcX73k DoDCl3u4DJYHcbrxpao6Exb6g+a6NyC65mwPtyjpcoNKqe6qb3iIPEAFwhkcwV3zr7+Z0QAE0EDvmn V3gknp7ehLJdZh8u9KhMghvuFiQsPc4QKLQwzjF44W1370CrYvYcYzw3+aaQh+Z4CYooSBu31ZeFlO 6tKRgT7Icfl5jWcd7WMSV0OZbEWokPoFMF616TmyOdrBnAt1jER7Z2lEzaqqMNsEzhbd0EMCtoEAbR KT+IOrcPd/ez7rvOUAps0ADpuYl2Af71wUoGaS8TP/hrepqJyy0w++diJVIS0MTS7zym6fxk6xlecG NY56NuUMe8mwVNVgVYW3Abqi1rp7A/8p9ao4RpGejbUNjApUKHlgDS0L1IrL5mkGZIKoVLwq2yz63o SbhUPrvHiUFjLyEny6wFI2ygOXHpNFV0yj5XTcA6ubyvRWwNGrWIPIcf1ehg== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Introduce an optional controller_rst_tbl use to store reset lines used to reset part of the controller. This is necessary for the vpu3 support, when the xo reset line must be asserted separately from the other reset line on power off operation. Factor the iris_init_resets() logic to allow requesting multiple reset tables. Reviewed-by: Bryan O'Donoghue Tested-by: Bryan O'Donoghue # x1e Dell Signed-off-by: Neil Armstrong --- drivers/media/platform/qcom/iris/iris_core.h | 1 + .../platform/qcom/iris/iris_platform_common.h | 2 ++ drivers/media/platform/qcom/iris/iris_probe.c | 39 +++++++++++++++------- 3 files changed, 30 insertions(+), 12 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_core.h b/drivers/media/platform/qcom/iris/iris_core.h index 37fb4919fecc62182784b4dca90fcab47dd38a80..78143855b277cd3ebdc7a1e7f35f6df284aa364c 100644 --- a/drivers/media/platform/qcom/iris/iris_core.h +++ b/drivers/media/platform/qcom/iris/iris_core.h @@ -82,6 +82,7 @@ struct iris_core { struct clk_bulk_data *clock_tbl; u32 clk_count; struct reset_control_bulk_data *resets; + struct reset_control_bulk_data *controller_resets; const struct iris_platform_data *iris_platform_data; enum iris_core_state state; dma_addr_t iface_q_table_daddr; diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index f6b15d2805fb2004699709bb12cd7ce9b052180c..fdd40fd80178c4c66b37e392d07a0a62f492f108 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -156,6 +156,8 @@ struct iris_platform_data { unsigned int clk_tbl_size; const char * const *clk_rst_tbl; unsigned int clk_rst_tbl_size; + const char * const *controller_rst_tbl; + unsigned int controller_rst_tbl_size; u64 dma_mask; const char *fwname; u32 pas_id; diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c index aca442dcc153830e6252d1dca87afb38c0b9eb8f..4f8bce6e2002bffee4c93dcaaf6e52bf4e40992e 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -91,25 +91,40 @@ static int iris_init_clocks(struct iris_core *core) return 0; } -static int iris_init_resets(struct iris_core *core) +static int iris_init_reset_table(struct iris_core *core, + struct reset_control_bulk_data **resets, + const char * const *rst_tbl, u32 rst_tbl_size) { - const char * const *rst_tbl; - u32 rst_tbl_size; u32 i = 0; - rst_tbl = core->iris_platform_data->clk_rst_tbl; - rst_tbl_size = core->iris_platform_data->clk_rst_tbl_size; - - core->resets = devm_kzalloc(core->dev, - sizeof(*core->resets) * rst_tbl_size, - GFP_KERNEL); - if (!core->resets) + *resets = devm_kzalloc(core->dev, + sizeof(struct reset_control_bulk_data) * rst_tbl_size, + GFP_KERNEL); + if (!*resets) return -ENOMEM; for (i = 0; i < rst_tbl_size; i++) - core->resets[i].id = rst_tbl[i]; + (*resets)[i].id = rst_tbl[i]; + + return devm_reset_control_bulk_get_exclusive(core->dev, rst_tbl_size, *resets); +} + +static int iris_init_resets(struct iris_core *core) +{ + int ret; + + ret = iris_init_reset_table(core, &core->resets, + core->iris_platform_data->clk_rst_tbl, + core->iris_platform_data->clk_rst_tbl_size); + if (ret) + return ret; + + if (!core->iris_platform_data->controller_rst_tbl_size) + return 0; - return devm_reset_control_bulk_get_exclusive(core->dev, rst_tbl_size, core->resets); + return iris_init_reset_table(core, &core->controller_resets, + core->iris_platform_data->controller_rst_tbl, + core->iris_platform_data->controller_rst_tbl_size); } static int iris_init_resources(struct iris_core *core) From patchwork Wed Apr 9 14:38:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 880780 Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 86C00266F00 for ; Wed, 9 Apr 2025 14:38:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744209512; cv=none; b=dT/bR6/Ag/+SNbV9ZiX3Lo1abd3JCLUmdlrSNwRq9X36FrhHD+cjCM0gYGRDRITyhIH66lR2mVb4cqwf/TCbKa204YKfzrnoSLW227twwgGQhdNbsOXDClCIzc5j20/UwI7pz5B8AQFEJOQ/4oLS5mvbfA0RfdMX4WHECdz7YRo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744209512; c=relaxed/simple; bh=LFaWlT8O8apwunlmzUQurSx47z7eOOQyQ6z0Cp8+d3k=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MDTVPjolmt81b4ca/A3fkoW+2BfuMj08ZzlEttQ4QPCvZTQJWAn8DkkKdlMWivaGA4wG6Jzat/9yaamKS+Sp/oYEvJY0+pv30wJVQKR4Lc7Gi49Lhs6UlpOroT1nFnVXnwPwPMuzGRr+5a1FPD5Gpmi3n0LBC3ykBGRs3gk28KM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=Mffrfda9; arc=none smtp.client-ip=209.85.221.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="Mffrfda9" Received: by mail-wr1-f41.google.com with SMTP id ffacd0b85a97d-39129fc51f8so5716805f8f.0 for ; Wed, 09 Apr 2025 07:38:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1744209506; x=1744814306; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=B7GE8ttTtM/vr3qrOv34WTHDyd35XgYWdWnFQsZ+vbY=; b=Mffrfda9aWzhCxOfaHpc5/BAV4n45GqI/6v1Gg7IYQpIexuY17y0EX7m55xeQuiEdH WjGbIkj6zK3BW+6gyAu+HFmWH4vi8KEbsOeal2pvMrjwRiIpdNJY59s9VQI0GDB5Ybdg HGTDm5qk9CxuWXdkZg0KYkMsTZo1zeGrQ3tTlkunsQCi8QXd688TIjwvweu2xAqmUi8T OgsvXGc783NoEP2kl6u8wELEuX45PODbKBofgcVcqEk2wmMZOCIloLnnouY19dls7gy9 NRst8HgKpEKB66QE7r/sogzAHVb75XBBSHemgaI8wQLgk2h3qYb2Kz3mbqMWy3IjdI1/ sHxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744209506; x=1744814306; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=B7GE8ttTtM/vr3qrOv34WTHDyd35XgYWdWnFQsZ+vbY=; b=lwSMxAVjxLVhNKnwikaiZLCNVVm2rOa8Dpw5dg8eM3zYGYK//lDYi9a/5B+kdXgusg OwktiTFS2SbT2KfQjHUcYiFH7IInaKWuL9yLpbExIIfGAZqW2nWGjF5ghOfegXcfAZcG 6OVTx0xsLDmQCykq5/DqZOXnJxEjfZSWVX8UqDYrEtuZ+RIGDsELr1pNAFgLhnFvD8mR FtNV4UZ8X5prhCs4NlwFSqPGSncsEtmRs5ZAHpRFSfyyKR6lL3mpZfmKzYUeuaIgDqFE oUnNU281gN9t1tcln1/4VAGztm/DCKK+FZyjw+s8aR6A/suRMBdJ2wETVdonWQ44dxwC 8cyg== X-Gm-Message-State: AOJu0YzbUSCl2qRygC07loFq3KOFB8dvOUZz7WErOvTZ1t9VEZef16M4 H0a5ZvQHhMz/uqqD73AyDOLlsV5qlm80l6dIULIirRFPCAoAHLy7Is8feQX/M9k= X-Gm-Gg: ASbGncsa8Fthq1NsWoYJMehAaPyaR6HgwwBLvWNF0rzOhd//sveQzh5mfgRloMwUEjN QNbIIQGYdfvFqakppYrIzHnNYEQokwfxQT9t4qaAC+9pBSkoXaleoZCFHLJwsUr2deO3YHHgSZK TS9AoRV6/rFevE3OyS4P/rrdCzVB/Z2Ez6qroIqVsY+20VGmNGX6ovEdkBJhct6MFBaZm2yx/bi 4WnL9V1aovcb4fT4bCKu0jfUJlgAPSL1tXME03kREar9nt93kCmH/XWZ0X1PZ4e10M13CTCDwJD WcihYRIt8xUrRMJFlxhTheNiFPMHlW09BwsU/mcTMxoeDQR8BNbyf6pKvpoAtmzwZWnsdJ1T X-Google-Smtp-Source: AGHT+IHBOcnQAUv4WE9+yjJLtCtaUreStK4OYX964pnkEvboEZCla7DUKWRpQdsuIBMFNPLo96W5lQ== X-Received: by 2002:a05:6000:2508:b0:390:ebae:6c18 with SMTP id ffacd0b85a97d-39d87aa57eemr2988297f8f.12.1744209506513; Wed, 09 Apr 2025 07:38:26 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:3d9:2080:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43f20625ea4sm22222045e9.12.2025.04.09.07.38.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Apr 2025 07:38:26 -0700 (PDT) From: Neil Armstrong Date: Wed, 09 Apr 2025 16:38:22 +0200 Subject: [PATCH v4 4/6] media: platform: qcom/iris: rename iris_vpu3 to iris_vpu3x Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250409-topic-sm8x50-iris-v10-v4-4-40e411594285@linaro.org> References: <20250409-topic-sm8x50-iris-v10-v4-0-40e411594285@linaro.org> In-Reply-To: <20250409-topic-sm8x50-iris-v10-v4-0-40e411594285@linaro.org> To: Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong , Bryan O'Donoghue X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1340; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=LFaWlT8O8apwunlmzUQurSx47z7eOOQyQ6z0Cp8+d3k=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBn9oZdrvKI10VRBU2gBQhU5KhrlbnDf2vl/PvYOgG2 RDKqtcyJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZ/aGXQAKCRB33NvayMhJ0UzqD/ 43VnCWC8Zj6mLX4sAkgQr1lCuIfpTLKKrg1Ok+QyZh7elYr/qrF06zdm2n8THAp0DCDOFEKf7OVENX edB3mdsL39N13pHHoETnsIzBhyUWDSHIWI5P+RJD8fSy4p57Qq44+wa5l41acYu/SZzxPmScmhpAbx niOR1vBAEeiqOcedXLfbITZAqqPw/SteuB+2gucNPHqzAiG7UZeB/WtcKU6tXRf05kNC6lCjzDx1IY 7XhgZlcW2DUGftDe8IKSKKEiI7di0r4hnAMqMsyw9HHeEE/iOGk3EWAqslkmXOahiKijybX5QDDckJ SzaN38j17zNiWMOQgGU+EdNTQO3kd15YkKDSU9Bu8R5rjY4r8TqmM8WaxX1MQVVzMMDyaVBUl0b6lc LO/dA7HlEsu+9hwTC4XinTQev8PMNu4hJVd24CfFMMbCB9YwT83coL+z2lMqlvm6r6qJRjrzNHVlwO 25NGiSD4usN/bLW1wlIDhp2cJaHLmMMbw/m+9n2S4czbR+SDpyrs4v9GvsMGrC8YXSPCys+1hzpL5b z21EbKOnY2nVIwUWMCpY6Z3ZLeOuxzrw3qRg4wDlH+Ai3q5hKeonwJLLVseitv/iYqOfjWn4bCWuLr l1ivBNMV2Qzh+BrfbBaQqRHhJzP2HEM3bkuqi+NO1KK0DN4UlcUV2TDd59Wg== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE The vpu33 HW is very close to vpu3, and shares most of the operations, so rename file to vpu3x since we'll handle all vpu3 variants in it. Reviewed-by: Dikshita Agarwal Tested-by: Bryan O'Donoghue # x1e Dell Signed-off-by: Neil Armstrong --- drivers/media/platform/qcom/iris/Makefile | 2 +- drivers/media/platform/qcom/iris/{iris_vpu3.c => iris_vpu3x.c} | 0 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/platform/qcom/iris/Makefile index 35390534534e93f4617c1036a05ca0921567ba1d..473aaf655448180ade917e642289677fc1277f99 100644 --- a/drivers/media/platform/qcom/iris/Makefile +++ b/drivers/media/platform/qcom/iris/Makefile @@ -20,7 +20,7 @@ qcom-iris-objs += \ iris_vb2.o \ iris_vdec.o \ iris_vpu2.o \ - iris_vpu3.o \ + iris_vpu3x.o \ iris_vpu_buffer.o \ iris_vpu_common.o \ diff --git a/drivers/media/platform/qcom/iris/iris_vpu3.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c similarity index 100% rename from drivers/media/platform/qcom/iris/iris_vpu3.c rename to drivers/media/platform/qcom/iris/iris_vpu3x.c From patchwork Wed Apr 9 14:38:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 879572 Received: from mail-wr1-f46.google.com (mail-wr1-f46.google.com [209.85.221.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 623AB2676D9 for ; Wed, 9 Apr 2025 14:38:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744209512; cv=none; b=RMUd6xDPEDMRHaTxFmN8yMikwXdlDfUqESiLQeLn+TPAeswG9trIFAfosgiJy84pf8Xb+EacVfaAQJEP3LkssSZUqcjbTasrxl2eWON/+zXt+RpzW3dYpvO4rTSgbUiEyU/OP7NdRzKhB+JlwpP5PDdNQvHmbwVzGXAwJNCrnkk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744209512; c=relaxed/simple; bh=L29D+dHeTrFH3hV1Wk+oU5i0WH2qeyAcee7cjmaet1w=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=TMaZI4oHXH491yR2K5zVNUuCYDGDkm8LzJgJl0MK1iF3d37AxFWhKLl0s7JMeZhuHxzs5i6v58nWzNln24GdM7iHBYvqNhc+Yxk99y/xFFOL19zG7w4dg4pWA13shCZ9LCjKB6yc185v3fM186u9A1i1ZNof7DDG7tB9m7bJ4xY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=c+tPzEWz; arc=none smtp.client-ip=209.85.221.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="c+tPzEWz" Received: by mail-wr1-f46.google.com with SMTP id ffacd0b85a97d-39c1ee0fd43so5814124f8f.0 for ; Wed, 09 Apr 2025 07:38:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1744209507; x=1744814307; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=s3PkO8wukirLciBy0qd6kGi8KmY6F0eQXfG6DiOuo68=; b=c+tPzEWzaheFlgIMHv/rNJw7P5Er+01EtMuXMM0UclAbIaa8N3Ni3GtM/jwArgyije NomsVuPsZSpkUIiuJwolrLF1L8Oy1h0ArVoWtS8yCqUSs7n0+sYiFtlFMhNID79oitgq o1Wv6NoONtDfH6y1wk9Q8SRp8mZS2qYTPViXPvALLFZIvRuvzksMSBw0YMLuVvGB7/Vq YXsUKuNqaWR865xID2w+UiICIIvQcW5NdN45Dr/vVXRhEe4ovEpofLWVi/mDZ58Nsj0o mbfLGBOjobi7aBDUtTzrzHGgWptggOU9MYFlytGjKISTm/bDe33nKb+LIFZUfihV0naK IJUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744209507; x=1744814307; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=s3PkO8wukirLciBy0qd6kGi8KmY6F0eQXfG6DiOuo68=; b=A87Q/dfNpRuvp6e0LDcOuKVWyMOfrO2+ATFBdrJpZ3E+HDsp9pzTfzQpfP5vmMFAw/ hRie7DdnaR+49dyXDgblhU5rCUiXcm23DWduertzDaAziCHtjkwU7zr/CqMMf7rMDCUF PLHZ0t+7qo9HL7HtKl71ZJyyzFV/Zy65XX0MVTlm+s1MnFQF7xUgTF79v6+/IpL3qiOK gtbNoUWjJYQGxint+b8MKPiGLknrFPUSIWL56fUBdt7XG7hZ3k1pam9NzyfXolR64bsx UQUxzqzexW2hCoAfCBOVortEdgBVfC+frJupEGBQ55grtuy1qfCETFl7cdcOueopxDdk 9T7g== X-Gm-Message-State: AOJu0YwmhP6AzOk+9ck2QtKH2ZW3RRG/ZZ5jJ56MsJjNl6+d8bBcZvVD h7i1gKWs6FLrz/2bJdOoIXuTuuW8521okv77zJ1PTmWmePn1x2aCs5v2vLd4/44= X-Gm-Gg: ASbGnctH0iwsLJ0zEnRIdWtAqDchIoYVRMux7V1FgFC6VZfUM+l8habhLFawHo+Q0qF wvyQDvoPmqYMyP6TmqpDRWv430uPPVgG99dP/+vuw5qn0mVhPG+RBialbyjzSwU7jjgkTmG80O7 uhBwxP35QBQWUyXVAloUT9ZAKNb+t63yWsq1WwL6C7Wh58hjqGG4fks74RAzEy2XtVM00C4kbGO 90cQYKENd78psUs1RIml5s9s4dWtjxUyOeveNo17p0npFxYzNTVF1K/uWM+UBX6QQyhVJd1N6P0 ILBrv0dQU3xoI5CrxrYeGcrqV2kkxi4I8Fq/G9gHH0YCyiMmOST4tR1io71Pfj7qU0NMEE4M X-Google-Smtp-Source: AGHT+IG07vsd8sdXzQ/hg9/E2YQGswo+FG991Y68G+gzXsNkkPm2nAAmtSHhecTGQs/d5NXP6Des0Q== X-Received: by 2002:a5d:64c4:0:b0:391:3915:cffb with SMTP id ffacd0b85a97d-39d885612a7mr2763660f8f.43.1744209507300; Wed, 09 Apr 2025 07:38:27 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:3d9:2080:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43f20625ea4sm22222045e9.12.2025.04.09.07.38.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Apr 2025 07:38:27 -0700 (PDT) From: Neil Armstrong Date: Wed, 09 Apr 2025 16:38:23 +0200 Subject: [PATCH v4 5/6] media: platform: qcom/iris: add support for vpu33 Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250409-topic-sm8x50-iris-v10-v4-5-40e411594285@linaro.org> References: <20250409-topic-sm8x50-iris-v10-v4-0-40e411594285@linaro.org> In-Reply-To: <20250409-topic-sm8x50-iris-v10-v4-0-40e411594285@linaro.org> To: Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong , Bryan O'Donoghue X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=8845; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=L29D+dHeTrFH3hV1Wk+oU5i0WH2qeyAcee7cjmaet1w=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBn9oZdz7dpsVxclXpwHLzrC39buSc/01b3/WjnH3aa NlzSpuCJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZ/aGXQAKCRB33NvayMhJ0Yh5EA CIv12LO6WhCrGMn/BM/UDR5Ki/mNWu2LqDJuUKOFthYPJM0faIdJ14X9Ungt9Ir7BHAyNK6q9h5sJq u+jVLF+JFW0wy6sSpOiTkK6ouUKOODckbi+0e43Fe6v0T+olZHbWDHixGsHMWdueTbo4gX+A8k1Prt xUg7ZSZen4alZAw8iJBtChy2Vr8IZaZbJRc6cCZaD05wdsC/i6p+0IyNKrvI1UgvkHJcQjOvekaO+X GVUne5iz0HXBcNEWGB7bi9jq9bMjxEkdPDEhBsGXau2FQLcU3Dy17insU27JJBwWUQ0d9xmP5sg8gS NtSlkP7SfkNHTcHaF835ODCl90PGbCLBR12xOs8r4gcWE6t5DAUwhsFDKY8MwebOp9RwOcq9WfyVNK qw++8046wTIibVbzptV6oy4/ODgREPZz1sbXAtdjPkfV2TU+yduzsyacGf3/oVm3z+3qYeBQKF8PA2 xYRvgW6rt6Mf1TKIPQQomE8wSNx5hWDrtxrALU+fGq9T2ldQHFAHMGQe0U6ze70TnZUN3eouiNY+zv 4qQMauF7VUx6gWDLqrDfOQUk5OLX4To0B9TDrclUbsCIXtFQP7uDmR1Ls4SaZh9Gm8xcsByBNCKcgo POZUfWlYoWnL1bqaTPKPsg5xDHXPmRHdYZ0rHYzbP1meKkod/N5PVMHewiyw== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE The IRIS acceleration found in the SM8650 platforms uses the vpu33 hardware version, and requires a slighly different reset and power off sequences in order to properly get out of runtime suspend. Tested-by: Bryan O'Donoghue # x1e Dell Signed-off-by: Neil Armstrong --- drivers/media/platform/qcom/iris/iris_vpu3x.c | 160 ++++++++++++++++++++- drivers/media/platform/qcom/iris/iris_vpu_common.h | 1 + 2 files changed, 157 insertions(+), 4 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c index 13dab61427b8bd0491b69a9bc5f5144d27d17362..5d8b437ded2647a71c0c0e6b51a0942919ef6076 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c @@ -4,20 +4,39 @@ */ #include +#include #include "iris_instance.h" #include "iris_vpu_common.h" #include "iris_vpu_register_defines.h" +#define WRAPPER_TZ_BASE_OFFS 0x000C0000 +#define AON_BASE_OFFS 0x000E0000 #define AON_MVP_NOC_RESET 0x0001F000 +#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x54) +#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58) +#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C) +#define REQ_POWER_DOWN_PREP BIT(0) +#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60) #define WRAPPER_CORE_CLOCK_CONFIG (WRAPPER_BASE_OFFS + 0x88) #define CORE_CLK_RUN 0x0 +#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG (WRAPPER_TZ_BASE_OFFS + 0x14) +#define CTL_AXI_CLK_HALT BIT(0) +#define CTL_CLK_HALT BIT(1) + +#define WRAPPER_TZ_QNS4PDXFIFO_RESET (WRAPPER_TZ_BASE_OFFS + 0x18) +#define RESET_HIGH BIT(0) + #define CPU_CS_AHB_BRIDGE_SYNC_RESET (CPU_CS_BASE_OFFS + 0x160) #define CORE_BRIDGE_SW_RESET BIT(0) #define CORE_BRIDGE_HW_RESET_DISABLE BIT(1) +#define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168) +#define MSK_SIGNAL_FROM_TENSILICA BIT(0) +#define MSK_CORE_POWER_ON BIT(1) + #define AON_WRAPPER_MVP_NOC_RESET_REQ (AON_MVP_NOC_RESET + 0x000) #define VIDEO_NOC_RESET_REQ (BIT(0) | BIT(1)) @@ -25,7 +44,16 @@ #define VCODEC_SS_IDLE_STATUSN (VCODEC_BASE_OFFS + 0x70) -static bool iris_vpu3_hw_power_collapsed(struct iris_core *core) +#define AON_WRAPPER_MVP_NOC_LPI_CONTROL (AON_BASE_OFFS) +#define AON_WRAPPER_MVP_NOC_LPI_STATUS (AON_BASE_OFFS + 0x4) + +#define AON_WRAPPER_MVP_NOC_CORE_SW_RESET (AON_BASE_OFFS + 0x18) +#define SW_RESET BIT(0) +#define AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL (AON_BASE_OFFS + 0x20) +#define NOC_HALT BIT(0) +#define AON_WRAPPER_SPARE (AON_BASE_OFFS + 0x28) + +static bool iris_vpu3x_hw_power_collapsed(struct iris_core *core) { u32 value, pwr_status; @@ -40,7 +68,7 @@ static void iris_vpu3_power_off_hardware(struct iris_core *core) u32 reg_val = 0, value, i; int ret; - if (iris_vpu3_hw_power_collapsed(core)) + if (iris_vpu3x_hw_power_collapsed(core)) goto disable_power; dev_err(core->dev, "video hw is power on\n"); @@ -79,7 +107,125 @@ static void iris_vpu3_power_off_hardware(struct iris_core *core) iris_vpu_power_off_hw(core); } -static u64 iris_vpu3_calculate_frequency(struct iris_inst *inst, size_t data_size) +static void iris_vpu33_power_off_hardware(struct iris_core *core) +{ + u32 reg_val = 0, value, i; + int ret; + + if (iris_vpu3x_hw_power_collapsed(core)) + goto disable_power; + + dev_err(core->dev, "video hw is power on\n"); + + value = readl(core->reg_base + WRAPPER_CORE_CLOCK_CONFIG); + if (value) + writel(CORE_CLK_RUN, core->reg_base + WRAPPER_CORE_CLOCK_CONFIG); + + for (i = 0; i < core->iris_platform_data->num_vpp_pipe; i++) { + ret = readl_poll_timeout(core->reg_base + VCODEC_SS_IDLE_STATUSN + 4 * i, + reg_val, reg_val & 0x400000, 2000, 20000); + if (ret) + goto disable_power; + } + + ret = readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATUS, + reg_val, reg_val & BIT(0), 200, 2000); + if (ret) + goto disable_power; + + /* set MNoC to low power, set PD_NOC_QREQ (bit 0) */ + writel(BIT(0), core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); + + writel(CORE_BRIDGE_SW_RESET | CORE_BRIDGE_HW_RESET_DISABLE, + core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); + writel(CORE_BRIDGE_HW_RESET_DISABLE, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); + writel(0x0, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); + +disable_power: + iris_vpu_power_off_hw(core); +} + +static int iris_vpu33_power_off_controller(struct iris_core *core) +{ + u32 xo_rst_tbl_size = core->iris_platform_data->controller_rst_tbl_size; + u32 clk_rst_tbl_size = core->iris_platform_data->clk_rst_tbl_size; + u32 val = 0; + int ret; + + writel(MSK_SIGNAL_FROM_TENSILICA | MSK_CORE_POWER_ON, core->reg_base + CPU_CS_X2RPMH); + + writel(REQ_POWER_DOWN_PREP, core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_CONTROL); + + ret = readl_poll_timeout(core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_STATUS, + val, val & BIT(0), 200, 2000); + if (ret) + goto disable_power; + + writel(0x0, core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_CONTROL); + + ret = readl_poll_timeout(core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_STATUS, + val, val == 0, 200, 2000); + if (ret) + goto disable_power; + + writel(CTL_AXI_CLK_HALT | CTL_CLK_HALT, + core->reg_base + WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG); + writel(RESET_HIGH, core->reg_base + WRAPPER_TZ_QNS4PDXFIFO_RESET); + writel(0x0, core->reg_base + WRAPPER_TZ_QNS4PDXFIFO_RESET); + writel(0x0, core->reg_base + WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG); + + reset_control_bulk_reset(clk_rst_tbl_size, core->resets); + + /* Disable MVP NoC clock */ + val = readl(core->reg_base + AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL); + val |= NOC_HALT; + writel(val, core->reg_base + AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL); + + /* enable MVP NoC reset */ + val = readl(core->reg_base + AON_WRAPPER_MVP_NOC_CORE_SW_RESET); + val |= SW_RESET; + writel(val, core->reg_base + AON_WRAPPER_MVP_NOC_CORE_SW_RESET); + + /* poll AON spare register bit0 to become zero with 50ms timeout */ + ret = readl_poll_timeout(core->reg_base + AON_WRAPPER_SPARE, + val, (val & BIT(0)) == 0, 1000, 50000); + if (ret) + goto disable_power; + + /* enable bit(1) to avoid cvp noc xo reset */ + val = readl(core->reg_base + AON_WRAPPER_SPARE); + val |= BIT(1); + writel(val, core->reg_base + AON_WRAPPER_SPARE); + + reset_control_bulk_assert(xo_rst_tbl_size, core->controller_resets); + + /* De-assert MVP NoC reset */ + val = readl(core->reg_base + AON_WRAPPER_MVP_NOC_CORE_SW_RESET); + val &= ~SW_RESET; + writel(val, core->reg_base + AON_WRAPPER_MVP_NOC_CORE_SW_RESET); + + usleep_range(80, 100); + + reset_control_bulk_deassert(xo_rst_tbl_size, core->controller_resets); + + /* reset AON spare register */ + writel(0, core->reg_base + AON_WRAPPER_SPARE); + + /* Enable MVP NoC clock */ + val = readl(core->reg_base + AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL); + val &= ~NOC_HALT; + writel(val, core->reg_base + AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL); + + iris_disable_unprepare_clock(core, IRIS_CTRL_CLK); + +disable_power: + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); + iris_disable_unprepare_clock(core, IRIS_AXI_CLK); + + return 0; +} + +static u64 iris_vpu3x_calculate_frequency(struct iris_inst *inst, size_t data_size) { struct platform_inst_caps *caps = inst->core->iris_platform_data->inst_caps; struct v4l2_format *inp_f = inst->fmt_src; @@ -119,5 +265,11 @@ static u64 iris_vpu3_calculate_frequency(struct iris_inst *inst, size_t data_siz const struct vpu_ops iris_vpu3_ops = { .power_off_hw = iris_vpu3_power_off_hardware, .power_off_controller = iris_vpu_power_off_controller, - .calc_freq = iris_vpu3_calculate_frequency, + .calc_freq = iris_vpu3x_calculate_frequency, +}; + +const struct vpu_ops iris_vpu33_ops = { + .power_off_hw = iris_vpu33_power_off_hardware, + .power_off_controller = iris_vpu33_power_off_controller, + .calc_freq = iris_vpu3x_calculate_frequency, }; diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/media/platform/qcom/iris/iris_vpu_common.h index f8965661c602f990d5a7057565f79df4112d097e..93b7fa27be3bfa1cf6a3e83cc192cdb89d63575f 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h @@ -10,6 +10,7 @@ struct iris_core; extern const struct vpu_ops iris_vpu2_ops; extern const struct vpu_ops iris_vpu3_ops; +extern const struct vpu_ops iris_vpu33_ops; struct vpu_ops { void (*power_off_hw)(struct iris_core *core); From patchwork Wed Apr 9 14:38:24 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 880779 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1A90D26770C for ; Wed, 9 Apr 2025 14:38:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744209512; cv=none; b=AsR6mfsHKg1o4jLTmfl6FxaviIJEd4K8b7mNSY4e64Z1ycUA0bkvdFMIgVQgjmbUW8rBryCKDLR3PldQIctgLCCImYisCkdrC61gYmjMS7xOLCUO8PxLRk5VxENA0kg5nMgppwvT0weYgcubbabGgY3z8al810Z8b8/8YsCddgQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744209512; c=relaxed/simple; bh=TwpN7WB7TovIb/Aom4JEIlovlaaSBos+8c3GTGn1tRE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qXwMopn4e7gNqldYjWWM/Gsdg1u9+MShOonPMzRaFwJlG2qsO/FZStvJNLTlLFnsBfeJv7+8d3wlmil5k9xgte4kQNiL4g8WR8xNo1+8ZO9S4zapbovZR/Lf9HY1BZUWqm1mWnsciI/14Vilkms8A00+jIJTGCJwP42cfhLQ6Pk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=FCy8/PqM; arc=none smtp.client-ip=209.85.128.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="FCy8/PqM" Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-43ed8d32a95so43339525e9.3 for ; Wed, 09 Apr 2025 07:38:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1744209508; x=1744814308; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=m/NF1ZydIUvd4N7KqoBnhLoGbjaoZN62+JonM5wUK+o=; b=FCy8/PqMbX5ucH/jMP94cZMRQ/WwO+Fo0CV6n6hZ5MHfKfHuR4IS+WjQTVwSWp3aYW gr5YU31k6JNUrv5v35ecwMs5xGDFpoPdzNGveoY24BlSMFjPR2XHQUWj4/Xv4tOkXqo6 G4k7/l3m+3SizudCr4xM/if/u2uzVuYLnjLu/hG5soK1PatVLuBFrRNYg+yHahRj9F4D N8k/VTyiiQygP76RyRWtaXCdeyMSRaHIrURzgRJiAE8lrdOVKjk07bRUaS5teKt2/zje lVnaRzP/AyYQdrUJPykYyq9bdZJJq3DArHz3TVBPVmA9Z8gLDH1dOhhU+lQ7uC7JSgYT Hyow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744209508; x=1744814308; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=m/NF1ZydIUvd4N7KqoBnhLoGbjaoZN62+JonM5wUK+o=; b=Oe0/qFMiyvz062mhUOYnI8U4fRvGnlo5M7jKY71A6xCYIg4t0y/iNoOn/5aphaZTl6 b5wuKXdAwhlBzsvB+VZltN5cZI/RcD3YSdZdZdVLL1vmldv7II70kg7I9tjI1noEyDME VT9+E9vMb8EMH9QY/z4JJReA989kFBMsk5FvUcBOPpdBPeeQqL0LnmxbUtTtdRBjLkqF YYKxZjj6Kf/nGHuNZnfd1E1stH8k0uKS2ziXPGogrKsTGYs5ANQku6FqTYUE9b7D5Oz7 ExNEmyXrJ9JN8a8yS3PMk569aBLjqBJ4ungRO+Bgu0e0Db9CaOpjcLRvfYI5KD+UzbvC n/lg== X-Gm-Message-State: AOJu0YxZ1Ixjo2Xlvb/Ays29DoNnIkZ3p/OwovgCnyxF5FsI0yRHVkhR XEUpFel5XITwCkxU4XAWTmUnniEYuxMHsC4M4uNV/Hh5x0jheSF04Gd9xmOmi4s= X-Gm-Gg: ASbGnctlQp/j4igrtYKkWSyNfVMUBZBvWpBvf2hSe8W2cFIDRuls36I+gy31SxGwsIu B1Y8jMonlHrcXm2r0VLcoSXoJhrKD0LbHkOVzfAvBJMauZ/MHNDKQAUdgdSpNjioyr9m/V8Ey9B ulOU5VayBiRgUwUbbkkJAarjnXqBzAyjYBsVSLA8goUNCID8MwooL5tA+ebnftsBalh8G65VgVg IpEI1Vx3sUoLduq+I0R9KMdrWO9bSKH/Sv+4lrKPiTzM78lckD9yMzXqG3uKLPihFhdTwOyCPBq Ttz136gGBYnzJaX9isbmd5cdQOwCh461iBP6WEZ8WD64xjqumKQgMmeSg4CqWw== X-Google-Smtp-Source: AGHT+IHt3tWE71LTEXVzyHw+QWXDZ9BI265fKqAiFU8xitCNid8MP3TrNBem8f3KAvrsA4uSKRbRSA== X-Received: by 2002:a05:600c:5486:b0:43b:c0fa:f9dd with SMTP id 5b1f17b1804b1-43f1ed4b4a3mr25024705e9.25.1744209508072; Wed, 09 Apr 2025 07:38:28 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:3d9:2080:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43f20625ea4sm22222045e9.12.2025.04.09.07.38.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Apr 2025 07:38:27 -0700 (PDT) From: Neil Armstrong Date: Wed, 09 Apr 2025 16:38:24 +0200 Subject: [PATCH v4 6/6] media: platform: qcom/iris: add sm8650 support Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250409-topic-sm8x50-iris-v10-v4-6-40e411594285@linaro.org> References: <20250409-topic-sm8x50-iris-v10-v4-0-40e411594285@linaro.org> In-Reply-To: <20250409-topic-sm8x50-iris-v10-v4-0-40e411594285@linaro.org> To: Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong , Bryan O'Donoghue X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5286; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=TwpN7WB7TovIb/Aom4JEIlovlaaSBos+8c3GTGn1tRE=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBn9oZe3DEOvpC5qTMwP/UIE7//HGWGN9GM6J2n2dOY VR0lkTeJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZ/aGXgAKCRB33NvayMhJ0R6eD/ 9lB6rU9VZKyLFyyWymyblecXKQW0WaRzZfJOUXMmif3MPclwBLvOBY8Sb/UskWRE7QUDaBMoFeioxx ncGWanh3zYUdMR8wUIff0GmbgACaxujafsGN2tu6GSRayIMyuJit1pITrF69kw8W+5SzNvqtWGlR/s WeH5YDNdWu5th18zSZCbVOOAkmJAZoE9s6NAu7bQqeVBMZgrBJhWDQ0jVuOGgDIpywSyVudzyGT7Ow SksVeyZGIhDYN0zg0XVrRX4FUVehDdAAgwB8qR1AXY9QETkbhhMV/TkzOcY/o9xcLPb0EMPJqUhatR gDfczcmUfjbE0syD6WR+FgsnGAQK4djhoHP/eHXVDwTcIpf0Q92/X59wenrL3884We05N6+6Ab807h UwpyOYSHCipe9iPXK1UMQPAwtZTcSZ2uXtC2qgyoRiFNRhS9jgSWXhjcy41ZBUhuLhBHwOc6/uuZQC s2sr/FhepzlCEmhWrnU80m8cf7RUD6skVCvpN8uKLepAMeUqkb/PcyBi5yNFRdX3mGBX+/dljc+6P1 7HGQI9i0bhMjmzD//8gBTDolkK1+G05JuvstsmdqiXMvmLE+9dEOwDxTuIZIonJ3qfTytDIbmrGhaZ CjVprkEmDWliwWDxFgrUZIOWJ/mXUpabHMNbOygJ2YPGG1F7aumHeOxWU8Uw== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Add support for the SM8650 platform by re-using the SM8550 definitions and using the vpu33 ops. The SM8650/vpu33 requires more reset lines, but the H.264 decoder capabilities are identical. Tested-by: Bryan O'Donoghue # x1e Dell Signed-off-by: Neil Armstrong --- .../platform/qcom/iris/iris_platform_common.h | 1 + .../platform/qcom/iris/iris_platform_sm8550.c | 64 ++++++++++++++++++++++ drivers/media/platform/qcom/iris/iris_probe.c | 4 ++ 3 files changed, 69 insertions(+) diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index fdd40fd80178c4c66b37e392d07a0a62f492f108..6bc3a7975b04d612f6c89206eae95dac678695fc 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -35,6 +35,7 @@ enum pipe_type { extern struct iris_platform_data sm8250_data; extern struct iris_platform_data sm8550_data; +extern struct iris_platform_data sm8650_data; enum platform_clk_type { IRIS_AXI_CLK, diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8550.c b/drivers/media/platform/qcom/iris/iris_platform_sm8550.c index 35d278996c430f2856d0fe59586930061a271c3e..d0f8fa960d53367023e41bc5807ba3f8beae2efc 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_sm8550.c +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8550.c @@ -144,6 +144,10 @@ static const struct icc_info sm8550_icc_table[] = { static const char * const sm8550_clk_reset_table[] = { "bus" }; +static const char * const sm8650_clk_reset_table[] = { "bus", "core" }; + +static const char * const sm8650_controller_reset_table[] = { "xo" }; + static const struct bw_info sm8550_bw_table_dec[] = { { ((4096 * 2160) / 256) * 60, 1608000 }, { ((4096 * 2160) / 256) * 30, 826000 }, @@ -264,3 +268,63 @@ struct iris_platform_data sm8550_data = { .dec_op_int_buf_tbl = sm8550_dec_op_int_buf_tbl, .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_op_int_buf_tbl), }; + +/* + * Shares most of SM8550 data except: + * - vpu_ops to iris_vpu33_ops + * - clk_rst_tbl to sm8650_clk_reset_table + * - controller_rst_tbl to sm8650_controller_reset_table + * - fwname to "qcom/vpu/vpu33_p4.mbn" + */ +struct iris_platform_data sm8650_data = { + .get_instance = iris_hfi_gen2_get_instance, + .init_hfi_command_ops = iris_hfi_gen2_command_ops_init, + .init_hfi_response_ops = iris_hfi_gen2_response_ops_init, + .vpu_ops = &iris_vpu33_ops, + .set_preset_registers = iris_set_sm8550_preset_registers, + .icc_tbl = sm8550_icc_table, + .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table), + .clk_rst_tbl = sm8650_clk_reset_table, + .clk_rst_tbl_size = ARRAY_SIZE(sm8650_clk_reset_table), + .controller_rst_tbl = sm8650_controller_reset_table, + .controller_rst_tbl_size = ARRAY_SIZE(sm8650_controller_reset_table), + .bw_tbl_dec = sm8550_bw_table_dec, + .bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec), + .pmdomain_tbl = sm8550_pmdomain_table, + .pmdomain_tbl_size = ARRAY_SIZE(sm8550_pmdomain_table), + .opp_pd_tbl = sm8550_opp_pd_table, + .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table), + .clk_tbl = sm8550_clk_table, + .clk_tbl_size = ARRAY_SIZE(sm8550_clk_table), + /* Upper bound of DMA address range */ + .dma_mask = 0xe0000000 - 1, + .fwname = "qcom/vpu/vpu33_p4.mbn", + .pas_id = IRIS_PAS_ID, + .inst_caps = &platform_inst_cap_sm8550, + .inst_fw_caps = inst_fw_cap_sm8550, + .inst_fw_caps_size = ARRAY_SIZE(inst_fw_cap_sm8550), + .tz_cp_config_data = &tz_cp_config_sm8550, + .core_arch = VIDEO_ARCH_LX, + .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE, + .ubwc_config = &ubwc_config_sm8550, + .num_vpp_pipe = 4, + .max_session_count = 16, + .max_core_mbpf = ((8192 * 4352) / 256) * 2, + .input_config_params = + sm8550_vdec_input_config_params, + .input_config_params_size = + ARRAY_SIZE(sm8550_vdec_input_config_params), + .output_config_params = + sm8550_vdec_output_config_params, + .output_config_params_size = + ARRAY_SIZE(sm8550_vdec_output_config_params), + .dec_input_prop = sm8550_vdec_subscribe_input_properties, + .dec_input_prop_size = ARRAY_SIZE(sm8550_vdec_subscribe_input_properties), + .dec_output_prop = sm8550_vdec_subscribe_output_properties, + .dec_output_prop_size = ARRAY_SIZE(sm8550_vdec_subscribe_output_properties), + + .dec_ip_int_buf_tbl = sm8550_dec_ip_int_buf_tbl, + .dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl), + .dec_op_int_buf_tbl = sm8550_dec_op_int_buf_tbl, + .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_op_int_buf_tbl), +}; diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c index 4f8bce6e2002bffee4c93dcaaf6e52bf4e40992e..7cd8650fbe9c09598670530103e3d5edf32953e7 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -345,6 +345,10 @@ static const struct of_device_id iris_dt_match[] = { .data = &sm8250_data, }, #endif + { + .compatible = "qcom,sm8650-iris", + .data = &sm8650_data, + }, { }, }; MODULE_DEVICE_TABLE(of, iris_dt_match);