From patchwork Mon Apr 14 21:41:18 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Wanner X-Patchwork-Id: 881169 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B73A71F37C3; Mon, 14 Apr 2025 21:42:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744666925; cv=none; b=r2QUQEYenxBdLBirP608LskyprGYJtl//05+y3vMtqZt6CYEHH2dSHRyuquT0S3Cssio6k9rCHzQdkhMYC9VxwgjtjV713w7yApX5mhS076eYsNWPQv1K+1rQqc59I7M0hQqp4fNUq37+iIq/A1Wgyg+uUGeFHAXHf2UOTxxFnk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744666925; c=relaxed/simple; bh=y6zBcUQgWavANG8NsuRsZDucUUdJh5SHXwtzFjn3t3c=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=MkZrCq1Q0nKMy7aHNPhfP6l3SQhtUaFngDQnGZaBmXIElc1FHNnSVSNl2+FKIUIoJRWfgeyWjSt+9eDwpFLSH/BZuq1oKHukKrNb6tcn+CcWo9kjHj26dWaO+W5qVPcvCxg9V5oYElvhx9po7GFSxka6aw1aNxpZw1oCYBnRNQs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=SS1KNV+l; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="SS1KNV+l" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1744666923; x=1776202923; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=y6zBcUQgWavANG8NsuRsZDucUUdJh5SHXwtzFjn3t3c=; b=SS1KNV+lSIUgzW8prAD46q4jQrewiDHSoJZzrhcbF6QA5pDdyKXZJv3D gGDk5qhnef/DoAUAQDNA0wUXG0VIC1eMYrWftJbzcx5emcm2exleMprVk nyBEaVEd15QstkVCsidiyt+ws1DcfoydVbnTjrffzyv+tjxUqJLhDKZFz Qt2LRFFDdpX0yzi79K6YcdiSQaI9jPGplqtRCur5H1UgiTD0XEsszURz3 zEe+RQ+CajVvJOgCcsC1cCiPviWC1NsbCusFNQHZPXmZdF1JPzU/HuzqE 1dCKEXWV5xZ97jj2INq1OPF9TjlBUow/K04424eR5+Q2xxqn/V/VEvGug w==; X-CSE-ConnectionGUID: jf75aQsXSneWELgtntpGWQ== X-CSE-MsgGUID: oWsgq+VNSYGlvgdS9mCSUQ== X-IronPort-AV: E=Sophos;i="6.15,212,1739862000"; d="scan'208";a="40006667" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 14 Apr 2025 14:41:55 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Mon, 14 Apr 2025 14:41:04 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Mon, 14 Apr 2025 14:41:04 -0700 From: To: , , , , , , , , CC: , , , , , Ryan Wanner Subject: [PATCH v5 01/11] dt-bindings: sram: Add microchip,sama7d65-sram Date: Mon, 14 Apr 2025 14:41:18 -0700 Message-ID: <35015e91dfd7d2240d05160a75cdd6dc4f4e6e79.1744666011.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ryan Wanner Add microchip,sama7d65-sram compatibility to DT binding documentation. Signed-off-by: Ryan Wanner Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/sram/sram.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/sram/sram.yaml b/Documentation/devicetree/bindings/sram/sram.yaml index 7c1337e159f2..3071c5075ee4 100644 --- a/Documentation/devicetree/bindings/sram/sram.yaml +++ b/Documentation/devicetree/bindings/sram/sram.yaml @@ -31,6 +31,7 @@ properties: - amlogic,meson-gxbb-sram - arm,juno-sram-ns - atmel,sama5d2-securam + - microchip,sama7d65-securam - nvidia,tegra186-sysram - nvidia,tegra194-sysram - nvidia,tegra234-sysram From patchwork Mon Apr 14 21:41:19 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Wanner X-Patchwork-Id: 881602 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6EAB71F3BAB; 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X-CSE-ConnectionGUID: jf75aQsXSneWELgtntpGWQ== X-CSE-MsgGUID: kear+yGWQxarTgaYcOwEtg== X-IronPort-AV: E=Sophos;i="6.15,212,1739862000"; d="scan'208";a="40006669" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 14 Apr 2025 14:41:55 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Mon, 14 Apr 2025 14:41:05 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Mon, 14 Apr 2025 14:41:05 -0700 From: To: , , , , , , , , CC: , , , , , Ryan Wanner Subject: [PATCH v5 02/11] dt-bindings: power: reset: atmel, sama5d2-shdwc: Add microchip,sama7d65-shdwc Date: Mon, 14 Apr 2025 14:41:19 -0700 Message-ID: <24666308604d3eb9f2b8c64d4a466c6fd77120e9.1744666011.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ryan Wanner Add SAMA7D65 SHDWC compatible to DT bindings documentation Signed-off-by: Ryan Wanner Acked-by: Rob Herring (Arm) --- .../devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml b/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml index 0735ceb7c103..9c34249b2d6d 100644 --- a/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml +++ b/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml @@ -16,6 +16,11 @@ description: | properties: compatible: oneOf: + - items: + - enum: + - microchip,sama7d65-shdwc + - const: microchip,sama7g5-shdwc + - const: syscon - items: - const: microchip,sama7g5-shdwc - const: syscon From patchwork Mon Apr 14 21:41:20 2025 Content-Type: text/plain; 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Mon, 14 Apr 2025 14:41:05 -0700 From: To: , , , , , , , , CC: , , , , , Ryan Wanner , Krzysztof Kozlowski Subject: [PATCH v5 03/11] dt-bindings: reset: atmel,at91sam9260-reset: add microchip,sama7d65-rstc Date: Mon, 14 Apr 2025 14:41:20 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ryan Wanner Add SAMA7D65 RSTC compatible to DT bindings documentation. The sama7d65-rstc is compatible with the sama7g5-rstc. Signed-off-by: Ryan Wanner Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/reset/atmel,at91sam9260-reset.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml index 98465d26949e..a2ab7f8a11f8 100644 --- a/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml +++ b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml @@ -23,6 +23,9 @@ properties: - atmel,sama5d3-rstc - microchip,sam9x60-rstc - microchip,sama7g5-rstc + - items: + - const: microchip,sama7d65-rstc + - const: microchip,sama7g5-rstc - items: - const: atmel,sama5d3-rstc - const: atmel,at91sam9g45-rstc From patchwork Mon Apr 14 21:41:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Wanner X-Patchwork-Id: 881167 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 32BA31F429C; Mon, 14 Apr 2025 21:42:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744666928; cv=none; b=Jd6N90vESZnX/y8r9RcWmiLfIFDIOQcvmM3rvl4KjtKxbFT66WDWdKPNztla5upr0LhyYUqkMaFLJlmWuGieEtZRPaB63GNDCHQfJ7Jbd95ODBMvSaCamqvSmVijR0k4B5KKOlqOoP/wVzLT1FhpyY15ema4e8p5E5cygaDXWyI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744666928; c=relaxed/simple; bh=lRUUsu68yjl48Dfc+/ph2mpUFrsqqJQ0TwHXN3jGP6Y=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=CpaLiPtEqAvyUPJpFxt0N35KBv1xmZ937/jj6GTf+qpERKWQ5JfytMTN24Y9mQ4Xr70vLYt8c5fXM327mDNyxi+9hFzcv47v25euMK9kUKJXCaL85zc+a3Ti8Ongd/lWISs8sS2wa716ucPq/qDCBSe6KuOxwi5a06XIuioUHrg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=oIDjVUd5; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="oIDjVUd5" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1744666926; x=1776202926; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lRUUsu68yjl48Dfc+/ph2mpUFrsqqJQ0TwHXN3jGP6Y=; b=oIDjVUd5DN2B3QmROM6pAgqm0k4XxRW2B5wYhpLCJlq3xuZyI1J1+ggT qoHeh7iiWjuWHdSdTOy0blYfGanK/SxEuoAsIviLgRf82u3dDm4PbkXto 4H0yx9ykwWjWAU9ltYxSV6VfsjMXCsPY+9WMxL2p6wfvfLXwYRbdGmFMw 5Eb8FMvfDurS4M9u7CCLwpN6Oazjp/QkSfPfozll/9WcqAKRfrPgSR5qp 3dx+tNTbDxSgpQwxnUin99NFlcT2UsE61O1ibzdxcLFS1TYAY+ZWtBANd eAsfYSuBpEf8luDrs2wGQ8uI8B/Jz6JLHiuISWnHpMwdfgt2Ym3SQ1xiA g==; X-CSE-ConnectionGUID: jf75aQsXSneWELgtntpGWQ== X-CSE-MsgGUID: bnp5lq8FSTiv0aGez8zlHw== X-IronPort-AV: E=Sophos;i="6.15,212,1739862000"; d="scan'208";a="40006671" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 14 Apr 2025 14:41:56 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Mon, 14 Apr 2025 14:41:05 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Mon, 14 Apr 2025 14:41:05 -0700 From: To: , , , , , , , , CC: , , , , , Ryan Wanner Subject: [PATCH v5 04/11] dt-bindings: rtc: at91rm9200: add microchip,sama7d65-rtc Date: Mon, 14 Apr 2025 14:41:21 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ryan Wanner Add SAMA7D65 RTC compatible to DT bindings documentation. Signed-off-by: Ryan Wanner Acked-by: Rob Herring (Arm) --- .../devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml index c8bb2eef442d..7c5b13caa40b 100644 --- a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml @@ -23,7 +23,9 @@ properties: - microchip,sam9x60-rtc - microchip,sama7g5-rtc - items: - - const: microchip,sam9x7-rtc + - enum: + - microchip,sam9x7-rtc + - microchip,sama7d65-rtc - const: microchip,sam9x60-rtc reg: From patchwork Mon Apr 14 21:41:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Wanner X-Patchwork-Id: 881601 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3E64C1F4607; Mon, 14 Apr 2025 21:42:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744666928; cv=none; b=HZyDkIyWPnnnJpW7osSL9LXtjPhLsDmuO7aHCo7PIGDksZY1MiojJGG/uQeKAlYloVKHtfhgJVdc4EKahFG4YIXOvIotE4C5sfzcfh+pqoGM3utUPj7cfVPC769QvH791qEpZHAGgspPBTvoJKbh9tJqzIND7+1VkQ7fYQ0erEo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744666928; c=relaxed/simple; bh=P0+FQOoZAZDGBeJjjiJS1++QSiAMr7ZQoLAUMUlSI2E=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=qSiqSz83YYx/ex77rRe2uk1RtU9QdLhQ9FuJd3cBMOWaH/765gasZFvVYdE4oA/Sl4gd9CFp7lhrAQbERQwVzyphAQh7aETVShblU6f5kbCUjQwzm3QTVygU59AsM860b6JOrPMLC6dtLH6HkxMyq6Y2vPgAID+KHQpm1nCedJo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=mZBhuchO; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="mZBhuchO" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1744666926; x=1776202926; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=P0+FQOoZAZDGBeJjjiJS1++QSiAMr7ZQoLAUMUlSI2E=; b=mZBhuchOxlJxh6hGluBiGo7yzecPdjN5NOGW7OITn3aUIJbKTOSKfblq VlbE9wS5CYbd8NqnZdw8ZO/vKr/Eq8Fj+MITRDN+cqn5ae3iwlfTTFBi0 GRnTQe3/LzO8lizj47T9HisuNFUeZU7DotIWaRMfVpAUemX0sy281bzfn PQbxxKBOjNfzfC3TZC/I7KCLlmu0Fc9j1AuaDG/T11p71Phx7W+9aFEAn kpN8jOWFlbUEOEhAYxJqj6II3Hh2jOvWZN3Ye3oNjnN9aDkY5ac5+S/S4 yqK54sKWPC9sq1k5eSqevh7nbGIHOieiwU47dkWDa6gSXZXV33t2Z+KQs w==; X-CSE-ConnectionGUID: jf75aQsXSneWELgtntpGWQ== X-CSE-MsgGUID: oiXX/nZaR0SBoW4EIzQuEg== X-IronPort-AV: E=Sophos;i="6.15,212,1739862000"; d="scan'208";a="40006673" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 14 Apr 2025 14:41:56 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Mon, 14 Apr 2025 14:41:05 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Mon, 14 Apr 2025 14:41:05 -0700 From: To: , , , , , , , , CC: , , , , , Ryan Wanner Subject: [PATCH v5 05/11] dt-bindings: at91rm9260-rtt: add microchip,sama7d65-rtt Date: Mon, 14 Apr 2025 14:41:22 -0700 Message-ID: <183474a65377f4030360166a5f2659af7323e82b.1744666011.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ryan Wanner Add SAMA7D65 RTT compatible to DT bindings documentation. Signed-off-by: Ryan Wanner Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml b/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml index a7f6c1d1a08a..9c9b981fe38b 100644 --- a/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml +++ b/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml @@ -22,6 +22,7 @@ properties: - enum: - microchip,sam9x60-rtt - microchip,sam9x7-rtt + - microchip,sama7d65-rtt - const: atmel,at91sam9260-rtt - items: - const: microchip,sama7g5-rtt From patchwork Mon Apr 14 21:41:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Wanner X-Patchwork-Id: 881600 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 477F61F4C9C; Mon, 14 Apr 2025 21:42:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744666929; cv=none; b=QwevXJf/rHMjGC5V8TwZR6zP9l7a7wncGi8RsQVaet79Iryp+tRtuqQdxZdob/RalmUF+NXqRZPOG9SnahGDVYXiuA00SAhW/uzYFYaPVVIo2cYWTS5NDyeHTC10uaPQCFt322ZYdv7W/XfR1qhupPnhWR9A/9TwviX8g8PEcro= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744666929; c=relaxed/simple; bh=OM1d3llXIfkK0/Fd/B3sNNDqgNroniFjy4Xdxaa5Z5c=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ft/hLuxbJ2UD2zVzdSGX6U04VazCTHS5k4kam5KDvlcwInktXFk5U+J6ZGBT3suNBgNdQs/z0aWAjXB+SpqwCiHt4yq/7/IRaj8AscuNFTrTueJse13+p5ajsENFSSYgDUNcb6e0HPfXKBv8dU8z0epGGj47D856UPHe1EY4Yqg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=WWZou3jl; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="WWZou3jl" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1744666927; x=1776202927; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=OM1d3llXIfkK0/Fd/B3sNNDqgNroniFjy4Xdxaa5Z5c=; b=WWZou3jlLFWxDX4AfxtxYB8SF50orUqVKwVWU4BsX4bc0VRxucD8RQFP 7+itvTepUHO/1FKskOkgpQgEI3V8lkHU6J3ZO+3blPmZ4Z09/k79J7HzW G6O8JxraEpyn7NKYw1k5i/5elcau35w1TvZ1lOzuZrcH+/fNFK+uDyjaR ZGY8+/BsxPT7XAvnmaJClJSmEfjRPt1vlLY349c/rOzfGc+TXLT6bmM0S tuVCMXv60I3LoJOBLYaf3YVb/Eb/kZjU/2f9GT1qYlhZXYlFOxCEmBbkI eFb0gYdQW40CZ7byGYXYu3MRLSH2hCyZ4YwI0Fpv6jzL91jCWLPIITURz g==; X-CSE-ConnectionGUID: jf75aQsXSneWELgtntpGWQ== X-CSE-MsgGUID: fu3b2IBCT8mVUyCt3fIHXQ== X-IronPort-AV: E=Sophos;i="6.15,212,1739862000"; d="scan'208";a="40006674" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 14 Apr 2025 14:41:56 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Mon, 14 Apr 2025 14:41:05 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Mon, 14 Apr 2025 14:41:05 -0700 From: To: , , , , , , , , CC: , , , , , Ryan Wanner , Krzysztof Kozlowski Subject: [PATCH v5 06/11] dt-bindings: mfd: atmel: Add microchip, sama7d65-gpbr Date: Mon, 14 Apr 2025 14:41:23 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ryan Wanner Add SAMA7D65 GPBR compatible to DT bindings documentation. Signed-off-by: Ryan Wanner Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/mfd/atmel,at91sam9260-gpbr.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/atmel,at91sam9260-gpbr.yaml b/Documentation/devicetree/bindings/mfd/atmel,at91sam9260-gpbr.yaml index f805545aa62a..f6f47999c6c1 100644 --- a/Documentation/devicetree/bindings/mfd/atmel,at91sam9260-gpbr.yaml +++ b/Documentation/devicetree/bindings/mfd/atmel,at91sam9260-gpbr.yaml @@ -19,6 +19,7 @@ properties: - items: - enum: - atmel,at91sam9260-gpbr + - microchip,sama7d65-gpbr - const: syscon - items: - enum: From patchwork Mon Apr 14 21:41:24 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Wanner X-Patchwork-Id: 881166 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3E0A31F542E; Mon, 14 Apr 2025 21:42:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744666930; cv=none; b=ADAVqcc02pZlsNgZGR2aT+JSNgaRfWWMLhV6Hs7JMVLnra8q2njbaQKAeV3oiwGf8wdtUhRHZJicsjPXS2/mANqac1GpRzFexRpdJ+nqz3TBeap3p0CPrXVPCCQ9Y6RxntQE/9WXdhoSnWWpjNTc4rVfXsToOJj/p0PD1ut5n+0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744666930; c=relaxed/simple; bh=VCaMKVR89ookuZONPoMM9YW1f2EPtej4NWNimSc/EFo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=SjsnvuEhOs+5RmhLDxFYjJQZyTvjbxG+Nr85B5/Abr3u5zeId0DoK6D8bpDO6gQk0V21Uzz9PoCy2EZv/7p70L8O0ye0PMblY7JNHrzdJt87RlD5izQycCoSCKqyw3m/kU8gSsvbgV6cYBWRJSCwr09GHs2l0H4j5/35yIGwR48= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=Rq7U2VC4; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="Rq7U2VC4" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1744666928; x=1776202928; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VCaMKVR89ookuZONPoMM9YW1f2EPtej4NWNimSc/EFo=; b=Rq7U2VC4EzVpMlzExlzCEogiQOSzPjMgZa0mEocuGyz+mz1X3aG/DZE/ Qa/ifwYvwV7jAnfzbskYNaPZn3iyeRUKi7ziWKzVTXvliFsgAi5Th2RoP tFWm+IZYlkBc8Ev4a35Xzj98pxPXEPmSC0OnsM/qwLh3L6t8rO1v87OKO gBmxMJIBV9Hu3Wf1+KbRnBRWq6cGbYOMN288yK5jVtyQxwguCh/QbhwtL uGGa3VWgBjxNjBcw7W+KyJ/60TdnAlDZnwP5PE1ELkDtUKTpd9qSPuAVy cgvtphgECFzPsscwkqxvV/O5rYPjyr/NXmoD15q+cKtOycyIz4AuQX+Zb g==; X-CSE-ConnectionGUID: jf75aQsXSneWELgtntpGWQ== X-CSE-MsgGUID: D0dtunMcRnuRprEgLd2nHQ== X-IronPort-AV: E=Sophos;i="6.15,212,1739862000"; d="scan'208";a="40006675" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 14 Apr 2025 14:41:57 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Mon, 14 Apr 2025 14:41:05 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Mon, 14 Apr 2025 14:41:05 -0700 From: To: , , , , , , , , CC: , , , , , Ryan Wanner , Krzysztof Kozlowski Subject: [PATCH v5 07/11] dt-bindings: mfd: syscon: atmel,sama5d2-secumod: convert to yaml Date: Mon, 14 Apr 2025 14:41:24 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ryan Wanner Convert Microchip AT91 secumod to YAML format. Signed-off-by: Ryan Wanner Reviewed-by: Krzysztof Kozlowski --- .../bindings/arm/atmel,sama5d2-secumod.yaml | 48 +++++++++++++++++++ .../devicetree/bindings/arm/atmel-sysregs.txt | 25 ---------- 2 files changed, 48 insertions(+), 25 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/atmel,sama5d2-secumod.yaml diff --git a/Documentation/devicetree/bindings/arm/atmel,sama5d2-secumod.yaml b/Documentation/devicetree/bindings/arm/atmel,sama5d2-secumod.yaml new file mode 100644 index 000000000000..b1f766e333d4 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/atmel,sama5d2-secumod.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/atmel,sama5d2-secumod.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip AT91 Security Module (SECUMOD) + +maintainers: + - Nicolas Ferre + +description: + The Security Module also offers the PIOBU pins which can be used as GPIO pins. + Note that they maintain their voltage during Backup/Self-refresh. + +properties: + compatible: + oneOf: + - items: + - const: atmel,sama5d2-secumod + - const: syscon + - items: + - enum: + - microchip,sama7g5-secumod + - const: atmel,sama5d2-secumod + - const: syscon + reg: + maxItems: 1 + + gpio-controller: true + + "#gpio-cells": + const: 2 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + security-module@fc040000 { + compatible = "atmel,sama5d2-secumod", "syscon"; + reg = <0xfc040000 0x100>; + gpio-controller; + #gpio-cells = <2>; + }; diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt index d3821f651e72..5ce54f9befe6 100644 --- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt +++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt @@ -46,28 +46,3 @@ Examples: reg = <0xffffe800 0x200>; }; -Security Module (SECUMOD) - -The Security Module macrocell provides all necessary secure functions to avoid -voltage, temperature, frequency and mechanical attacks on the chip. It also -embeds secure memories that can be scrambled. - -The Security Module also offers the PIOBU pins which can be used as GPIO pins. -Note that they maintain their voltage during Backup/Self-refresh. - -required properties: -- compatible: Should be "atmel,-secumod", "syscon". - can be "sama5d2". -- reg: Should contain registers location and length -- gpio-controller: Marks the port as GPIO controller. -- #gpio-cells: There are 2. The pin number is the - first, the second represents additional - parameters such as GPIO_ACTIVE_HIGH/LOW. - - - secumod@fc040000 { - compatible = "atmel,sama5d2-secumod", "syscon"; - reg = <0xfc040000 0x100>; - gpio-controller; - #gpio-cells = <2>; - }; From patchwork Mon Apr 14 21:41:25 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Wanner X-Patchwork-Id: 881599 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 13CF81F63E4; Mon, 14 Apr 2025 21:42:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744666930; cv=none; b=bFgRP5s9AHSVIwCX50F+aoIZkbYwvevAsd7oROAyXIV8tNwFpHF4U4RV3KZFWgyEeijKCzUvPkkU8DP5xp+0vmuRelhfrASBTpc8q1/J5Knmw97FeLVEXZjm06sbvHkJ22BwnVFryJHmCghE3iNNK62npJNRCjBk55I5MPhWR9g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744666930; c=relaxed/simple; bh=vnVUWi683eLAl6E3rzjUozBpg+T+n1g51iJhW+AjjsE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=FcpL1hQNVUVV7zs00Q0B4XQ/g7CWUruNKr5JXwk8N9md/ehWOjzN11Z38u9o9BNsfywxxK2eZ5zrEdB2dDaNysGV/53FMnmZ/6UKCUSUK+JyqxlR1yAcfNhf/0PH9oL95MHfZiRAklXHvSSaIVXyQ3IHc8auojvYqxVfoz2gNWA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=E9bpsr3h; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="E9bpsr3h" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1744666929; x=1776202929; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=vnVUWi683eLAl6E3rzjUozBpg+T+n1g51iJhW+AjjsE=; b=E9bpsr3hlhOomy9Jtk6Z2UlKJPtdnkg36bzaOWMJQUljNOHufFwMMQ2R lPFkrgEuYj63VK5MOOFONiPGX1SAzNQ8Q/ofmrEnflUnQlCamxBu5cEZO wQXvkImHmYgpQjo+O8N+iXW/znAjSXf8PMhiXEoVd72Qa/zvWv2qg3QaK mji9QSH47zDIkpaPTdkXVLTLyOMvTLsYS1tZof0YRwCPA/EfX6DacJkcS +HosITs5A9c92xCnr5QNSR3SwUEBFQYzM49b7PS8hcWfr9zyXnwx3u9Gb qosEd/j2bvEjz7Mo/4zUIyXCCw94akYi/q5u8x3HMsKnomROnIS/h0rDD w==; X-CSE-ConnectionGUID: jf75aQsXSneWELgtntpGWQ== X-CSE-MsgGUID: P6YyYl5bShyxINJv3ViNTQ== X-IronPort-AV: E=Sophos;i="6.15,212,1739862000"; d="scan'208";a="40006676" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 14 Apr 2025 14:41:57 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Mon, 14 Apr 2025 14:41:06 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Mon, 14 Apr 2025 14:41:06 -0700 From: To: , , , , , , , , CC: , , , , , Ryan Wanner , Krzysztof Kozlowski Subject: [PATCH v5 08/11] dt-bindings: mfd: syscon: add microchip,sama7d65-secumod Date: Mon, 14 Apr 2025 14:41:25 -0700 Message-ID: <2fdd14313d9cf008dbc4a63a91ba0cb5cf372ad6.1744666011.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ryan Wanner Add SAMA7D65 SECUMOD compatible string to DT bindings documentation. Signed-off-by: Ryan Wanner Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/atmel,sama5d2-secumod.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/atmel,sama5d2-secumod.yaml b/Documentation/devicetree/bindings/arm/atmel,sama5d2-secumod.yaml index b1f766e333d4..ad4a98a4ee67 100644 --- a/Documentation/devicetree/bindings/arm/atmel,sama5d2-secumod.yaml +++ b/Documentation/devicetree/bindings/arm/atmel,sama5d2-secumod.yaml @@ -21,6 +21,7 @@ properties: - const: syscon - items: - enum: + - microchip,sama7d65-secumod - microchip,sama7g5-secumod - const: atmel,sama5d2-secumod - const: syscon From patchwork Mon Apr 14 21:41:26 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Wanner X-Patchwork-Id: 881165 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4AD1A1F8731; Mon, 14 Apr 2025 21:42:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744666931; cv=none; b=WcjDS5qziYd6+QNpgoeAHwQjf/lLwgDKjfcpBugRcdkL1gcyRyVGRKe3W9wWoqewJVh9KpS1hiv4GOfaB1eOwPa0HfbUEGzh1D91y1WkPajhFK2gTV60Y/QsQrLRknw2brgLq5hHhQ+PM/ReV3wKR/5ZGIYgaP35TTL+368GImo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744666931; c=relaxed/simple; bh=jUvxnIYUbRoDsGcxWrRs5hQT0rBrN7ve+6frDdnr+zc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=kPLocxjqmMtvbkhMReKiJngIKpOK9FfE/rdALqBZkhVCdqDMysEqH4MAha3bNJrb0Y+SczXgt8C6UTNm6GJmAg8Ko3tSaMXH8HQqD6pA4QwYXSeQoS2qtS0PAweV22ibrAXpAattepz5Fnae4xc7aV9lir8fPxKGJieD9DKkym0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=ha8m4C6s; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="ha8m4C6s" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1744666929; x=1776202929; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jUvxnIYUbRoDsGcxWrRs5hQT0rBrN7ve+6frDdnr+zc=; b=ha8m4C6s5biXrefQBRKl5Nts4CsgH3jENSXRudq2JtNmCy3WX/C3LFL4 4oYJ7nfrOv4og6jVz8nEM/kgCHBaucGEN/dsQD6BPemD2jqGPYt7jtqpP 1l+Fb+I9Azs5uamm9ceDv6aM0bc6pJlLo2HEQv+8G8kLNAVXlwHd8BMjB 1/lkV7VGbe/FekqmYbWP1kpnQipDY/hEP8Og7vpbjy1N/LjOV/xGZN7hr 7wGhn1dUEucNXOU+EbWqvai98exvex51NibjPHiUmKm+tiU4tgVJVSe4o 1R2+S9Af/cRdgZZs3nGSES+DiXf3KRE3Sfyf6MV2SiWOaItsN2ZfbS7/M Q==; X-CSE-ConnectionGUID: jf75aQsXSneWELgtntpGWQ== X-CSE-MsgGUID: H+TRc6fwTnGuExqarZ3BvA== X-IronPort-AV: E=Sophos;i="6.15,212,1739862000"; d="scan'208";a="40006677" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 14 Apr 2025 14:41:57 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Mon, 14 Apr 2025 14:41:06 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Mon, 14 Apr 2025 14:41:06 -0700 From: To: , , , , , , , , CC: , , , , , Ryan Wanner Subject: [PATCH v5 09/11] ARM: dts: microchip: sama7d65: Add SRAM and DRAM components support Date: Mon, 14 Apr 2025 14:41:26 -0700 Message-ID: <354ecd628fdd292d2125570a6b10a93cbecb7706.1744666011.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ryan Wanner Add SRAM, secumod, UDDRC, and DDR3phy to enable support for low power modes. Signed-off-by: Ryan Wanner --- arch/arm/boot/dts/microchip/sama7d65.dtsi | 35 +++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi index b6710ccd4c36..8439c6a9e9f2 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -47,6 +47,14 @@ slow_xtal: clock-slowxtal { }; }; + ns_sram: sram@100000 { + compatible = "mmio-sram"; + reg = <0x100000 0x20000>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + }; + soc { compatible = "simple-bus"; ranges; @@ -58,6 +66,23 @@ sfrbu: sfr@e0008000 { reg = <0xe0008000 0x20>; }; + securam: sram@e0000800 { + compatible = "microchip,sama7d65-securam", "atmel,sama5d2-securam", "mmio-sram"; + reg = <0xe0000800 0x4000>; + ranges = <0 0xe0000800 0x4000>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 17>; + #address-cells = <1>; + #size-cells = <1>; + no-memory-wc; + }; + + secumod: security-module@e0004000 { + compatible = "microchip,sama7d65-secumod", "atmel,sama5d2-secumod", "syscon"; + reg = <0xe0004000 0x4000>; + gpio-controller; + #gpio-cells = <2>; + }; + pioa: pinctrl@e0014000 { compatible = "microchip,sama7d65-pinctrl", "microchip,sama7g5-pinctrl"; reg = <0xe0014000 0x800>; @@ -227,6 +252,16 @@ i2c10: i2c@600 { }; }; + uddrc: uddrc@e3800000 { + compatible = "microchip,sama7d65-uddrc", "microchip,sama7g5-uddrc"; + reg = <0xe3800000 0x4000>; + }; + + ddr3phy: ddr3phy@e3804000 { + compatible = "microchip,sama7d65-ddr3phy", "microchip,sama7g5-ddr3phy"; + reg = <0xe3804000 0x1000>; + }; + gic: interrupt-controller@e8c11000 { compatible = "arm,cortex-a7-gic"; reg = <0xe8c11000 0x1000>, From patchwork Mon Apr 14 21:41:27 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Wanner X-Patchwork-Id: 881598 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C29FD1F3BBB; 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X-CSE-ConnectionGUID: jf75aQsXSneWELgtntpGWQ== X-CSE-MsgGUID: hNKqRSUARQqRIMPx+wlHXw== X-IronPort-AV: E=Sophos;i="6.15,212,1739862000"; d="scan'208";a="40006678" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 14 Apr 2025 14:41:58 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Mon, 14 Apr 2025 14:41:06 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Mon, 14 Apr 2025 14:41:06 -0700 From: To: , , , , , , , , CC: , , , , , Ryan Wanner Subject: [PATCH v5 10/11] ARM: dts: microchip: sama7d65: Add RTT and GPBR Support for sama7d65 SoC Date: Mon, 14 Apr 2025 14:41:27 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ryan Wanner Add RTT support for SAMA7D65 SoC. The GPBR is added so the SoC is able to store the RTT time data. Signed-off-by: Ryan Wanner --- arch/arm/boot/dts/microchip/sama7d65.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi index 8439c6a9e9f2..bec70164a75c 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -132,6 +132,13 @@ shdwc: poweroff@e001d200 { status = "disabled"; }; + rtt: rtc@e001d300 { + compatible = "microchip,sama7d65-rtt", "atmel,at91sam9260-rtt"; + reg = <0xe001d300 0x30>; + interrupts = ; + clocks = <&clk32k 0>; + }; + clk32k: clock-controller@e001d500 { compatible = "microchip,sama7d65-sckc", "microchip,sam9x60-sckc"; reg = <0xe001d500 0x4>; @@ -146,6 +153,11 @@ rtc: rtc@e001d800 { clocks = <&clk32k 1>; }; + gpbr: syscon@e001d700 { + compatible = "microchip,sama7d65-gpbr", "syscon"; + reg = <0xe001d700 0x48>; + }; + chipid@e0020000 { compatible = "microchip,sama7d65-chipid"; reg = <0xe0020000 0x8>; From patchwork Mon Apr 14 21:41:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Wanner X-Patchwork-Id: 881164 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0B83B1FF7A5; Mon, 14 Apr 2025 21:42:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744666932; cv=none; b=YmQR9QY+tTo/1FfZ6CvYRV5n03gV/RXN7CxfTYuoKIH6Lo9LJcAyZFFiAQa4wR6JH5+TeWEuXAPZvejJ3HJAoFYR6qjqpXWnEhyb6jRbxWhNlqb7hCh5qKOVEYUJ4tFreZWayf8myiAAF4yayjLLkHdSUEHL0OqeRwrh7KNlujo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744666932; c=relaxed/simple; bh=cp3KlP5kz8uShLGylSzqchQUQS7t4AEaR6YGK7e5dDw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=InhMw/RbNMGDugwARIx/pNBLSAadWD/4KHApDeVqX+JuFHHqkaSDcB57tE7LGptr18ybY1GD77SKh/ompRE2LWaMQIcVRF0d31o11WxigkzyfDXjEOzQmYaFYX2RLGhlh4W1VigF9Rfxt+SK0cUBIEx6b4xxFhyjp62P39JoY1k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=EQzlmdJf; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="EQzlmdJf" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1744666931; x=1776202931; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cp3KlP5kz8uShLGylSzqchQUQS7t4AEaR6YGK7e5dDw=; b=EQzlmdJfiAVHbP5Yi7XbpBY8pVGmCPOHKsf/SHWA352jSU8eHsjDgkkS caR4NP9Kz8XByyei3GpPw61phruVP2z+3XPzLcM3dIqKJPY/Fns7ugDpj 8g1RYc9MM3MwUux+/lBCIFUBc4rzoI5UpreWm5fRcDUHop9QZMQCHdWqr FsZj30yoiSLhjUdFsb4oCyv9VOZ0OREMqspAi0t4Rr1XLRi+WvlDNlxnU ecwjfNaUu5qckskPz6GHeF5FWL5acZ4cwkhjt42MuUb5trW+i07JvKqUT FXZIQcTqSAWXI6iomEkW0Wsw7yjee0RX35RieKsM26+D7zEXJlYn7N10v A==; X-CSE-ConnectionGUID: jf75aQsXSneWELgtntpGWQ== X-CSE-MsgGUID: MHSMuxp7TpCpQCP646iirw== X-IronPort-AV: E=Sophos;i="6.15,212,1739862000"; d="scan'208";a="40006679" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 14 Apr 2025 14:41:58 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Mon, 14 Apr 2025 14:41:06 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Mon, 14 Apr 2025 14:41:06 -0700 From: To: , , , , , , , , CC: , , , , , Ryan Wanner Subject: [PATCH v5 11/11] ARM: dts: microchip: sama7d65: Add RTT timer to curiosity board Date: Mon, 14 Apr 2025 14:41:28 -0700 Message-ID: <463581224a07bf122c6907d34a0c5c71b1cc73e1.1744666011.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ryan Wanner Add RTT timer with backup register for SAMA7D65_Curiosity board. Signed-off-by: Ryan Wanner --- arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts b/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts index 30fdc4f55a3b..3105fe1766c3 100644 --- a/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts +++ b/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts @@ -141,6 +141,10 @@ pinctrl_uart6_default: uart6-default { }; }; +&rtt { + atmel,rtt-rtc-time-reg = <&gpbr 0x0>; +}; + &sdmmc1 { bus-width = <4>; pinctrl-names = "default";