From patchwork Thu Apr 17 11:27:02 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 882124 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 487CC23D2BD for ; Thu, 17 Apr 2025 11:27:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744889231; cv=none; b=uPKm2A2awuRmEoBfPXvK6bmE4h1u194fRW6FL0rdJLI8DTo5yEmh18lXUq41W59qoY4Ka9AvMH1oUkFDQwdzLy1m68Rxk3rcepjsDH6SpwyTnH/SE5A9IbL59H80Op9hmBcBDgVGMPd9scMDjAIw8couUQ6FAjsk4NWaW36dQp8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744889231; c=relaxed/simple; bh=hDddIwvlTDMzReVuUyCkrtqQUet2IXs5iUQX60KMgaA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fbZY4dtRhs/X5eLQuTVfXbBXPEym79MOTyOn27sTw743lAg/hqOIG63u0KswOUmMUwwW7c5+1aCv9vodl2tHurZLdtDhcCHysyME8bRO7rLFwlAebWzSw3aDi7ZdjRwCg99rvukk51kO4D1OuNcMW167rqkFigML8DpcSDcehbI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=Z9TAXcW0; arc=none smtp.client-ip=209.85.128.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="Z9TAXcW0" Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-43cf05f0c3eso4665245e9.0 for ; Thu, 17 Apr 2025 04:27:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1744889226; x=1745494026; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Jgi1FQ5Hy/QuNveGTgtne5MVjuvQZSqeo7o4egSVbSw=; b=Z9TAXcW04nmtXvI8nRCsOd7I2QIW6PSILHCk2GSJud/vZu41UniREoRfcZgrxRp2JW oFoHV61ojvGYAK2w405TO7LorskBo5q7NbuNcRMxDPJU0x7WNNpUQ7ZDLz5tM3CW0blt 9J4Zc+djEk9UctDU8Wy9sSrj0QjsTziG/IpOsmWhEtDFc6QP7x3BCemH7YX4FsQrJ7em 2oYRlESbPsb+uAl2HR7vOrR3+Ub398FWoclcE2wF7PtXBGq1D7o3P8+gD8xp0cloeNZL QJWbPn3WBevby+lwERiIvY5D04gbG7AwRvoXPatyn+yAzkeWfdfptcYYalWUShCaynO+ nJdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744889226; x=1745494026; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Jgi1FQ5Hy/QuNveGTgtne5MVjuvQZSqeo7o4egSVbSw=; b=l0ZOkWilMctFLKB+zO6HOc/xx0ROLFEzPBm6YE83YZ3raV0QUJPJsuOdsp+gbIM1A7 TmqrCTSPW5gD6fbuMhJlNO3EoMA1ixm4pSM189f+98Qnw54G9kUmIyaLTSNV0c2mdaIj F0LCbNL/Qc3tEAPm2evu/lh7ioSgwgM+fzB8vx2J8IS9+Ib6JP2zdtYbIRG+NMke2L3H Typzoqth8Cfsorp1P4gKFLqg8P1B8vRNJIMriWAEwuvIy8GPqZ5nbyEbm1Hrta3Ks8fd xebE4/3OhT8S6YsoxhMLoA9peBF0bSjyNmowJEBiPP/zyy8xpcwYx8u9NiK/VcxqnZOo kuKA== X-Forwarded-Encrypted: i=1; AJvYcCUTKKe0quiRrRhBE+DaFs3ftIq5BKP9sAahQ8/3PQmmfDC25ud3ckhXmmGXnSHUpfE2PO4xN9lWysZh6A==@vger.kernel.org X-Gm-Message-State: AOJu0YxStzfKIBSgtpqXmfjEKGJ6e7g5YQQ5xyU+mQnTxS7sQwvjf7ea qpi+vvHAITbIn5GfRMU0WcfXmj+NhH+4n4jxwQ8rfZjNyd+AVviiR/dReQ9JT6s= X-Gm-Gg: ASbGncuActPiJCGWd17HBemZLFUfVST+QWWLMw70tSPReOIsPIG9u1XXeefDlhpuLBB TjJiwdVPe+tojWGaYZuJye2u39i/PRasRGECLUW0PVmlR6lr7go9D1TassdU2zkXsOSboFiMby5 ul/vJNPhC3P2RwdlGEVr8zta3Qpe6gXhwcxAO4hD/dtyCbQFdRCn7UprKaKE714D3Zq/bKws9J5 xPGjIhR+ARve9rDRuqnMHUcritZFFP9qPh79P6C/71FHP1nqoloxwEW18QveGXthsPNkumrIgFT bfStY3FqOMuqqDDiGiVJF0ABhWE1XpFYR/fB5uA1zxgqES9vK52i4B9heLRjCcBnn5L4hhk4w/D PN5cmZg== X-Google-Smtp-Source: AGHT+IGN81sMeD9tcxfnFwYfOV4hKuARvvD9rpzZ33eZh0pIDM265CED5xrBR0aBqKfLf+uRTRzidw== X-Received: by 2002:a05:6000:430e:b0:39a:e71d:ef3f with SMTP id ffacd0b85a97d-39ee5b13fe8mr4740139f8f.5.1744889226436; Thu, 17 Apr 2025 04:27:06 -0700 (PDT) Received: from [192.168.0.34] (188-141-3-146.dynamic.upc.ie. [188.141.3.146]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39eae96400dsm20144063f8f.11.2025.04.17.04.27.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Apr 2025 04:27:06 -0700 (PDT) From: Bryan O'Donoghue Date: Thu, 17 Apr 2025 12:27:02 +0100 Subject: [PATCH v7 1/6] arm64: dts: qcom: x1e80100: Add CAMCC block definition Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250417-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v7-1-3fd4124cf35a@linaro.org> References: <20250417-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v7-0-3fd4124cf35a@linaro.org> In-Reply-To: <20250417-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v7-0-3fd4124cf35a@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Robert Foss , Todor Tomov , Mauro Carvalho Chehab , Konrad Dybcio Cc: Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, Bryan O'Donoghue , Vladimir Zapolskiy , Konrad Dybcio X-Mailer: b4 0.14.2 Add the CAMCC block for x1e80100. The x1e80100 CAMCC block is an iteration of previous CAMCC blocks with the exception of having two required power-domains not just one. Reviewed-by: Vladimir Zapolskiy Reviewed-by: Konrad Dybcio Signed-off-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 46b79fce92c90d969e3de48bc88e27915d1592bb..17e044dbb3b6de278d446eaf448561333e407843 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -5116,6 +5117,22 @@ usb_1_ss1_dwc3_ss: endpoint { }; }; + camcc: clock-controller@ade0000 { + compatible = "qcom,x1e80100-camcc"; + reg = <0x0 0x0ade0000 0x0 0x20000>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>; + power-domains = <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + mdss: display-subsystem@ae00000 { compatible = "qcom,x1e80100-mdss"; reg = <0 0x0ae00000 0 0x1000>; From patchwork Thu Apr 17 11:27:03 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 882501 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8306B23E357 for ; Thu, 17 Apr 2025 11:27:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744889233; cv=none; b=pSZ+WxwUq7IGLtkgc5QHEVoBuxdudVy9GEubYzUnU8Irya9sDL6lWhTTOFgoegdloQ2YU5UecmHKc1dInxCfs4rZ+qaNtM15OeISMy7fmgmWITaI/sll3ioMuhvQHK7QlJO8POVFs6A3eZ97X1jvZCSNW5hm1jZgiALKoBDp6w4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744889233; c=relaxed/simple; bh=yHkoD2LLNVtOlp4+3CahP5h/AR17CZ0yLXBiSRySPsQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=e7JcDexkJOY6Qf12NXKwDrP9aDcnRi1xfct83zjau1RWUbq445ddPFQk8oqAPHqTd+hrsQiJ7Mfetrj6Q6MqGGAwMi+0H7ted8DhWnRDA9eU7WPKdyk17FnpHhFRnDqfemfAkrTs6xRjDIjpjG8TiC4obeV5A9wGVKU9B/Cysrk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=cND32fRM; arc=none smtp.client-ip=209.85.128.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="cND32fRM" Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-43cf05f0c3eso4665345e9.0 for ; Thu, 17 Apr 2025 04:27:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1744889228; x=1745494028; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=n+yrwEk3Nrka0pmkGJr3BxDshhuy89tcK7yEvs60tYQ=; b=cND32fRMxkVUt5dt7qt0NJWyFb90BKfkKoTirRj1EsLJJSnyclk/oaUcXVVoXTVkXu o+DANo4P16jrnkpQ+b4j3Q3Zg4qEtlpjoaiucHo8dxyjlSO5kBy16l4kgwrB8qsdRMM1 OWRzH+KTGIkQoVTZcuuU2MzSf6gIH6Hgr05I8TfhEsyOiO8MdftZeINFzkYBPafQA647 a3JJzNYhtLKDRBq6REuV134tyy5caSSfS80uISetF2jPW0/97X+vKUPuEidK/Q70P901 +JpxesLUCjWHQcLkazeOGlwQGj+GLI9bAWGfIbSjYxK0DMMV43MNFeUKOXM92KrG8X+H 0o/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744889228; x=1745494028; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=n+yrwEk3Nrka0pmkGJr3BxDshhuy89tcK7yEvs60tYQ=; b=cFQnxXc/H7uk4l7IKG9n5F66EQB8abuUmyT0jCoHQtlGKLjwQdJa9U83CkWu2zWkHM D7ItJoEGs2PqUERCCIY9KPvgpiscRiGuvVjpuSKKvlYy2RZWch9oBb3z+VhVWwBavGQw X/zsBj4UYPAH5dn2nphg3wRhzYd56Pq8XPUI2N7LPbXDhyS8Rvgw7LtIn5OZXydZmWcF 2QP3ewaQ4pCT10KCafKhyCAs2iht21cL15eQVZ3NmKoJNGWp7iXwhtQGcIHFf9H33zd7 ELnVD7UT2jHL/bkDGxoimYB2yjoxxR2FSjsaAZLN8gAo4wz10j/BUamZo9aFYOaAuAtV EK/g== X-Forwarded-Encrypted: i=1; AJvYcCUeBn45j4VXLHX4ICJ5yWPH3mGuGUgM+o/bV2lutOswGHmR2Gw3nhrgZLQUMtXnBbh3NT6wz3GhzWT9ug==@vger.kernel.org X-Gm-Message-State: AOJu0Yw3/m7Fj+wdkIup/cHZe8dNVFq/Q7sv1o3jZx/s4GtAzk/cOlcS 716BdFFtwlnV2JCmd6lBZ5oXHoLIOdWHMDtSowbBEDR/WsO/Bvu6MxiBKglp7SM= X-Gm-Gg: ASbGnct1rnsMG6KGO12MyI06kl5Z3+7DiJdp7z61rHA8T7vp10jmBRBiYOu7hVD1QQ2 YtCWHGRA4xMqFo5ZWc46Zsp5vdK9U4FKKwxgZGA36s5nlGS2dIN2arz1hkD9StaRY64A4S5+qtk pkdY62Czfwx1nz94WL6cXUTbHP52g9MzRmz/u8GK+VhLnnaaSXOQ7+bVTXp6QVNUbCzHyAuI11Z 3vJ8e5C/HPAvQAg4yUev8K8hQK9zZLlFYrBBj7vtEO/0F+qHgcU/qd19lNHMuDy9rOdjnz2igjm J8/JwFN9EO6X3t53JxKx/yP8bk3ud5YdiKXfbIDURoKJEO08YrOD4CVoFm9YftFd8J/KH91cugK 8hlaASg== X-Google-Smtp-Source: AGHT+IHUQ5BLdAA2VHGA+nSpSqiLYvZyhqSsq+Y/9zmdY8Lr9fjXisyMa0PSuafwlHLT6YWAdJn6Ug== X-Received: by 2002:a05:6000:40da:b0:39e:dbb0:310f with SMTP id ffacd0b85a97d-39ee5b993a4mr5186891f8f.39.1744889227797; Thu, 17 Apr 2025 04:27:07 -0700 (PDT) Received: from [192.168.0.34] (188-141-3-146.dynamic.upc.ie. [188.141.3.146]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39eae96400dsm20144063f8f.11.2025.04.17.04.27.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Apr 2025 04:27:07 -0700 (PDT) From: Bryan O'Donoghue Date: Thu, 17 Apr 2025 12:27:03 +0100 Subject: [PATCH v7 2/6] arm64: dts: qcom: x1e80100: Add CCI definitions Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250417-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v7-2-3fd4124cf35a@linaro.org> References: <20250417-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v7-0-3fd4124cf35a@linaro.org> In-Reply-To: <20250417-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v7-0-3fd4124cf35a@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Robert Foss , Todor Tomov , Mauro Carvalho Chehab , Konrad Dybcio Cc: Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, Bryan O'Donoghue , Konrad Dybcio , Vladimir Zapolskiy X-Mailer: b4 0.14.2 Add in two CCI busses. One bus has two CCI bus master pinouts: cci_i2c_sda0 = gpio101 cci_i2c_scl0 = gpio102 cci_i2c_sda1 = gpio103 cci_i2c_scl1 = gpio104 The second bus has two CCI bus master pinouts: cci_i2c_sda2 = gpio105 cci_i2c_scl2 = gpio106 aon_cci_i2c_sda3 = gpio235 aon_cci_i2c_scl3 = gpio236 Reviewed-by: Konrad Dybcio Reviewed-by: Vladimir Zapolskiy Signed-off-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 150 +++++++++++++++++++++++++++++++++ 1 file changed, 150 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 17e044dbb3b6de278d446eaf448561333e407843..3ef3ebde4b2476c1da1fe11383718fba5ff87f85 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -5117,6 +5117,84 @@ usb_1_ss1_dwc3_ss: endpoint { }; }; + cci0: cci@ac15000 { + compatible = "qcom,x1e80100-cci", "qcom,msm8996-cci"; + reg = <0x0 0x0ac15000 0x0 0x1000>; + + interrupts = ; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_0_CLK>; + clock-names = "camnoc_axi", + "cpas_ahb", + "cci"; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + + pinctrl-0 = <&cci0_default>; + pinctrl-1 = <&cci0_sleep>; + pinctrl-names = "default", "sleep"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci0_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci0_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + cci1: cci@ac16000 { + compatible = "qcom,x1e80100-cci", "qcom,msm8996-cci"; + reg = <0x0 0x0ac16000 0x0 0x1000>; + + interrupts = ; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_1_CLK>; + clock-names = "camnoc_axi", + "cpas_ahb", + "cci"; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + + pinctrl-0 = <&cci1_default>; + pinctrl-1 = <&cci1_sleep>; + pinctrl-names = "default", "sleep"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci1_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci1_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + camcc: clock-controller@ade0000 { compatible = "qcom,x1e80100-camcc"; reg = <0x0 0x0ade0000 0x0 0x20000>; @@ -5741,6 +5819,78 @@ tlmm: pinctrl@f100000 { gpio-ranges = <&tlmm 0 0 239>; wakeup-parent = <&pdc>; + cci0_default: cci0-default-state { + cci0_i2c0_default: cci0-i2c0-default-pins { + /* cci_i2c_sda0, cci_i2c_scl0 */ + pins = "gpio101", "gpio102"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + + cci0_i2c1_default: cci0-i2c1-default-pins { + /* cci_i2c_sda1, cci_i2c_scl1 */ + pins = "gpio103", "gpio104"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + cci0_sleep: cci0-sleep-state { + cci0_i2c0_sleep: cci0-i2c0-sleep-pins { + /* cci_i2c_sda0, cci_i2c_scl0 */ + pins = "gpio101", "gpio102"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci0_i2c1_sleep: cci0-i2c1-sleep-pins { + /* cci_i2c_sda1, cci_i2c_scl1 */ + pins = "gpio103", "gpio104"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cci1_default: cci1-default-state { + cci1_i2c0_default: cci1-i2c0-default-pins { + /* cci_i2c_sda2, cci_i2c_scl2 */ + pins = "gpio105","gpio106"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + + cci1_i2c1_default: cci1-i2c1-default-pins { + /* aon_cci_i2c_sda3, aon_cci_i2c_scl3 */ + pins = "gpio235","gpio236"; + function = "aon_cci"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + cci1_sleep: cci1-sleep-state { + cci1_i2c0_sleep: cci1-i2c0-sleep-pins { + /* cci_i2c_sda2, cci_i2c_scl2 */ + pins = "gpio105","gpio106"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci1_i2c1_sleep: cci1-i2c1-sleep-pins { + /* aon_cci_i2c_sda3, aon_cci_i2c_scl3 */ + pins = "gpio235","gpio236"; + function = "aon_cci"; + drive-strength = <2>; + bias-pull-down; + }; + }; + qup_i2c0_data_clk: qup-i2c0-data-clk-state { /* SDA, SCL */ pins = "gpio0", "gpio1"; From patchwork Thu Apr 17 11:27:04 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 882500 Received: from mail-wr1-f50.google.com (mail-wr1-f50.google.com [209.85.221.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DED2B23ED71 for ; Thu, 17 Apr 2025 11:27:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744889234; cv=none; b=r7hlbKHuUTpjofL9DXwV6dLNLTNmvWC62FWIw0NQ4eUba1sh7NREAdJNgQI82oQ4/gP4NnWJthcDp+kWCo+UR5rrVkPTthN5fR23r8s5bdaKdEDRP0wBz1DnCsqBLBCkGl51zmpncGAr0rrY85HKxzxCamu7rQ8LLAGYTxyjsTA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744889234; c=relaxed/simple; bh=UUY8XNfF4dRzWt4suGlt9o9BBxToYMQT10AYr05Fajg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mi6CwykaDdEIBcepEwX7ZTNIMZpqRzI8v8W0hP3reksYEeffyJO82H/N/4Z3G0qSYVWVLnsFJPA+qhy8piiUyWF1kpEWBSR/y4Ebu15fnOxFMGf96aHmSnpaR0uyO1EWRYqK+97pLvOlRUNfWsjLFc/gS7c7xeIbAvpf/OlV77c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=LGDATElQ; arc=none smtp.client-ip=209.85.221.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="LGDATElQ" Received: by mail-wr1-f50.google.com with SMTP id ffacd0b85a97d-39ac9aea656so873844f8f.3 for ; Thu, 17 Apr 2025 04:27:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1744889229; x=1745494029; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=idQApIo2Y/V8jTW/gFHieZs9cN4yOYyA4VylQhX2Lig=; b=LGDATElQ83H+HNn48LWWrPlRkVpB/ESztY9r6bi8CJNjgIYiYy1hSSMkx0VQJJMRam IAE3Net7W19JtV03Sd4Wbx8oEHJyrYTGbT1JPeGofe9K1PsuCChbOMutQr28QGmL/1zu zQ8gpecjacLG2uajEzSjlj0f95OQ83T7JfNajNX27/KEPNbGMzV89hmTyYOdDixZCxQR i/a9pXZUxmr3/ZpZT5ElMFM6MJkOR4qR5eMkyJkJE+0deebFZR22ZNjQ28dWo0N19YA4 3xsm9MicoIcuWDY5gbRrEWSWxu9MdYKuSU7pqKbaAs8lrIAE9NHxxWJIOTDsjGc3GsLQ fRzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744889229; x=1745494029; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=idQApIo2Y/V8jTW/gFHieZs9cN4yOYyA4VylQhX2Lig=; b=KHl9gZgCLy7eX75f17QCVKlbmPZvJ3rIxP/fmsBGqPCh5sByyGdScJz/xHi2OYS/cJ OKY+K5rfMhh/5HWXVVSoCrVa1hWDbvZO1UsHV+uVZHaq7N9OnYbCJZYn3Nw8iWvncLmK a2Ug5DEvF2qPiuKDHm1AXPRVpwHWbb08pqal6GH9QDL0I3n7hDnhQqQLBincLru2lHGP PSwoxqI8H+9KPl07/nMUlyYiXjR5xdUMCULj+ICUKe0pD6kgtDO2bHx1wttCe8CmBq+7 qe4Y4VXyMGeKy8tAH2uBSsYNupK5F+Wxv2z8ATnSl6tcW718YS2gfgY12R/hpkgnVYDm 4SGA== X-Forwarded-Encrypted: i=1; AJvYcCUJyCCxg5EXOHN7bC+Tq1bunzSs06LIUm8npIhEanWhytMNVrtM0DvlA47bFxdmfBi4f2n3mF8PVqVJ6Q==@vger.kernel.org X-Gm-Message-State: AOJu0YyFAvEqcM5iNm6nm8n4gSWBAqZDXg9WxAf2s3QtiqBmI279t62V 8K9bP/We4u/Pq+G36KwZ6TrYBO1d0A6mhTx+wJciP2r6hxUPv75ZE65q22pcln8= X-Gm-Gg: ASbGncspVGkDaKqZYDxq3kaPkcdkiAbgsSUZ5FYrFThw1PGsPJN5LC7sTVWGJ0hzia4 aapTHDiwY/eEJ6yTEvnZZPk/3xf4WhhZTTt173w/eznI21bU6AdKUW4Gx0yYzYVQoDFY3zPtRDd T7cHDcHsgupNJLTxH2w/Zv5qufUEBScngGU00NIQdGGURkafB/vWTezt0Ip2rZ4AxDsVc28XFIg hUj50wTXyFTgT2SVLJzWUI7LkBjaWZB7pLsAfN3N2i7NIbn4Y7qy5wukLi26VaY8wyGp5Hmhr/S 7tOI6+h94TxHYou5Q87khWNmop/UxGsnZvS+VeqRUShDsaKhXzRvyho430GPr0HT9LXxgT5MZ4N A07V2Kg== X-Google-Smtp-Source: AGHT+IFZTqmDvEfGHPWJHtYU9u0dIPyE8hYBPPfi9argkTx1SKj4F4Bcu7fByR9F5YWTiCJjs2sLQg== X-Received: by 2002:a5d:59a8:0:b0:39c:e28:5f0d with SMTP id ffacd0b85a97d-39ee5b37a82mr4931060f8f.25.1744889229037; Thu, 17 Apr 2025 04:27:09 -0700 (PDT) Received: from [192.168.0.34] (188-141-3-146.dynamic.upc.ie. [188.141.3.146]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39eae96400dsm20144063f8f.11.2025.04.17.04.27.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Apr 2025 04:27:08 -0700 (PDT) From: Bryan O'Donoghue Date: Thu, 17 Apr 2025 12:27:04 +0100 Subject: [PATCH v7 3/6] arm64: dts: qcom: x1e80100: Add CAMSS block definition Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250417-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v7-3-3fd4124cf35a@linaro.org> References: <20250417-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v7-0-3fd4124cf35a@linaro.org> In-Reply-To: <20250417-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v7-0-3fd4124cf35a@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Robert Foss , Todor Tomov , Mauro Carvalho Chehab , Konrad Dybcio Cc: Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, Bryan O'Donoghue , Konrad Dybcio , Vladimir Zapolskiy X-Mailer: b4 0.14.2 Add dtsi to describe the xe180100 CAMSS block 4 x CSIPHY 2 x CSID 2 x CSID Lite 2 x IFE 2 x IFE Lite Reviewed-by: Konrad Dybcio Reviewed-by: Vladimir Zapolskiy Signed-off-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 185 +++++++++++++++++++++++++++++++++ 1 file changed, 185 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 3ef3ebde4b2476c1da1fe11383718fba5ff87f85..01a33005969d7df132b1aca26cb0884828c3c8ea 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -5195,6 +5195,191 @@ cci1_i2c1: i2c-bus@1 { }; }; + camss: isp@acb6000 { + compatible = "qcom,x1e80100-camss"; + + reg = <0x0 0x0acb7000 0x0 0x2000>, + <0x0 0x0acb9000 0x0 0x2000>, + <0x0 0x0acbb000 0x0 0x2000>, + <0x0 0x0acc6000 0x0 0x1000>, + <0x0 0x0acca000 0x0 0x1000>, + <0x0 0x0acb6000 0x0 0x1000>, + <0x0 0x0ace4000 0x0 0x2000>, + <0x0 0x0ace6000 0x0 0x2000>, + <0x0 0x0ace8000 0x0 0x2000>, + <0x0 0x0acec000 0x0 0x2000>, + <0x0 0x0acf6000 0x0 0x1000>, + <0x0 0x0acf7000 0x0 0x1000>, + <0x0 0x0acf8000 0x0 0x1000>, + <0x0 0x0ac62000 0x0 0x4000>, + <0x0 0x0ac71000 0x0 0x4000>, + <0x0 0x0acc7000 0x0 0x2000>, + <0x0 0x0accb000 0x0 0x2000>; + reg-names = "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csid_wrapper", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy4", + "csitpg0", + "csitpg1", + "csitpg2", + "vfe0", + "vfe1", + "vfe_lite0", + "vfe_lite1"; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, + <&camcc CAM_CC_CPAS_IFE_0_CLK>, + <&camcc CAM_CC_CPAS_IFE_1_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>; + clock-names = "camnoc_nrt_axi", + "camnoc_rt_axi", + "core_ahb", + "cpas_ahb", + "cpas_fast_ahb", + "cpas_vfe0", + "cpas_vfe1", + "cpas_vfe_lite", + "cphy_rx_clk_src", + "csid", + "csid_csiphy_rx", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy4", + "csiphy4_timer", + "gcc_axi_hf", + "gcc_axi_sf", + "vfe0", + "vfe0_fast_ahb", + "vfe1", + "vfe1_fast_ahb", + "vfe_lite", + "vfe_lite_ahb", + "vfe_lite_cphy_rx", + "vfe_lite_csid"; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy4", + "vfe0", + "vfe1", + "vfe_lite0", + "vfe_lite1"; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_CAMNOC_ICP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "ahb", + "hf_mnoc", + "sf_mnoc", + "sf_icp_mnoc"; + + iommus = <&apps_smmu 0x800 0x60>, + <&apps_smmu 0x860 0x60>, + <&apps_smmu 0x1800 0x60>, + <&apps_smmu 0x1860 0x60>, + <&apps_smmu 0x18e0 0x00>, + <&apps_smmu 0x1900 0x00>, + <&apps_smmu 0x1980 0x20>, + <&apps_smmu 0x19a0 0x20>; + + power-domains = <&camcc CAM_CC_IFE_0_GDSC>, + <&camcc CAM_CC_IFE_1_GDSC>, + <&camcc CAM_CC_TITAN_TOP_GDSC>; + power-domain-names = "ife0", + "ife1", + "top"; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + port@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + port@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + camcc: clock-controller@ade0000 { compatible = "qcom,x1e80100-camcc"; reg = <0x0 0x0ade0000 0x0 0x20000>; From patchwork Thu Apr 17 11:27:05 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 882123 Received: from mail-wr1-f54.google.com (mail-wr1-f54.google.com [209.85.221.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DEBD823ED6D for ; Thu, 17 Apr 2025 11:27:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744889234; cv=none; b=DDkhhz/QMREZGraqwNtKz/fn8zcRBbehBApXWZ7lHKwSLHjLpOLaUKtpYEyfQueZ/OgbnHjYSt/UKl1XD4CfMvZveI/ZgmFtdH9C+XRaFqg0Ubcu50bx69A+PZMED+UMln0b5a5gbRlpU66Y2vHpwWJolfLDeoRU0GYzF4H6wFY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744889234; c=relaxed/simple; bh=4FrCLQO7j/YGHNafasJjx36+B+nSVYq5seBDTN9ltls=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=FgNmbw/tI8rBHRngPKNPVPY8giiVZ1N51qLnSg8guFDZklA+ZTZXdoFWi9vbdEjr4RBefC+uIT9nkFmCqMq1QIJI0CMLw1p6U1zrSEHruouUIbfZ+Bg6mb8aBbmZSg9B1/7bL6Knq+cpUvF24UMamQcYclAnZbdN19AitJXhE9w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=Z9LLGw1y; arc=none smtp.client-ip=209.85.221.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="Z9LLGw1y" Received: by mail-wr1-f54.google.com with SMTP id ffacd0b85a97d-39c1ee0fd43so560442f8f.0 for ; Thu, 17 Apr 2025 04:27:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1744889230; x=1745494030; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=9kJ8ty7RIGmWcsy+9GDT37Q7U2J3An1slsXu7SJskUQ=; b=Z9LLGw1yqLAc4Gf/F92WjGLf2lZA5Dv+CoLnh0oHD+r6cdB4dZQHTL/wM5UHetcR7l k4GFYqueOA6Nt5NeHVqEz/ycb2A8PWO1axATo0JvemnCD1JobV6n9LqtLl1o6Jg35GPo QG4owukXtMDqWDWqPajvWQsCj+IKwJSWGIs5jpVDYjluZnVhdTkmWHMQ1zklHMEmpy/l oOd7Qz4wcEMZDNCT2R8RukCFVH1K+VNreLX5yDK62tgUh2genSXnoyn0YuxkUOfCRqh7 fnSWCvGiAb3/1SjXH+KwLDxBPW+b6N7hs5/NkYUrX0mwQaNbH+1dAL+v5kwBF2EBzwMB t2Gw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744889230; x=1745494030; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9kJ8ty7RIGmWcsy+9GDT37Q7U2J3An1slsXu7SJskUQ=; b=Ao6EFcdGD/Tl7lNWSlJoNV+vKpSCuilgPSnXogkBUwh36UzmQhPUlIB7yJFNSB2fwS xhEeC6Ptakq3WnA7l+DK8y0ns9qkLMI8KbpRKIgEH66nikekgEfB6eKv75z7P1Yi+MZZ 8dsHlEMwKHIpOxTUu5EYhlp+3tgVAa2p1DxlJBtjK9gZLEegCZKkAE7BHFzqDLzERFQP YT4aaSN8gZFa42spOF0Gk9P2fL2s7kcmsXeZDsH/5bxi+LNwnKCY27vJ9Jq5PEgIO+RS vtkvi/Zx7QfylWemZs1fM9s0Ir2WSbT6Hu6TcCSZeHWwm7LOzhhVCCjibvCBqIFdnqtX KYxw== X-Forwarded-Encrypted: i=1; AJvYcCUXYHw8+IP8VGDxJ4NQZHrhSWztcpFwEKWz3oZFfJTrdtzknY9edy8Cr1JwyrIGZjsHbNCZEoeCETMNwQ==@vger.kernel.org X-Gm-Message-State: AOJu0YwiyZkNW7xCocJhYZuA2C0NDcja1pTQlwWGdPdV+hcOqR1NzxaK 4+6PlYn77J3O9Wn6MZo7qcqJUf8A8C7xXZSUEi/hFRuXiHboqHo6ajqhc16CWOw= X-Gm-Gg: ASbGncvYgwnmCuq6BLzR2hYEWrGOhUpZgGbQQA8p9Dtxg0xoFgMnQefAv1T7zS7Pknf kk4Vh8sONohSAgNqQ8kojvtkCk/vp6BYBbGgb0zuHOTdtOE0MUPgcJmoxPIAxWNEof+jAP4m6Q2 j9HbBB9P+vDb4UNkfq9OuajXiS24DEXTPzrGvpceUH51nq3cdVH8vvp/EB4OHMubZGRrPjBuIT/ P43znufebdCZWL5iP25h9f9GFKRIkJuEeTFD/gd4XLaLht+ABZcrhqh0aStcKtqVu2EVuK2q1mL vDLiCFZ4frHY5XLF9/l31CDQReNmouK1U19x7UtSBTHmSdrhqb8uiqSCVDmr0BUSaw0NJsawb5L TIu2Zg25iBjvgQGBU X-Google-Smtp-Source: AGHT+IGTbJ2TnuYIlie6eiSsOXwcNdw8/al3bp7vr+QQf1mn2X7l3IqvyM9VVHXIyUz8MJKBG/7oBw== X-Received: by 2002:a05:6000:2403:b0:390:e7c1:59c4 with SMTP id ffacd0b85a97d-39ee5b1825emr4559707f8f.13.1744889230313; Thu, 17 Apr 2025 04:27:10 -0700 (PDT) Received: from [192.168.0.34] (188-141-3-146.dynamic.upc.ie. [188.141.3.146]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39eae96400dsm20144063f8f.11.2025.04.17.04.27.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Apr 2025 04:27:09 -0700 (PDT) From: Bryan O'Donoghue Date: Thu, 17 Apr 2025 12:27:05 +0100 Subject: [PATCH v7 4/6] arm64: dts: qcom: x1e80100-crd: Define RGB camera clock and reset pinout Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250417-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v7-4-3fd4124cf35a@linaro.org> References: <20250417-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v7-0-3fd4124cf35a@linaro.org> In-Reply-To: <20250417-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v7-0-3fd4124cf35a@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Robert Foss , Todor Tomov , Mauro Carvalho Chehab , Konrad Dybcio Cc: Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, Bryan O'Donoghue X-Mailer: b4 0.14.2 The RGB camera sensor uses MCLK3/gpio100 as clock with CAM_RESET_N/gpio237 as reset. Signed-off-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/x1-crd.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1-crd.dtsi b/arch/arm64/boot/dts/qcom/x1-crd.dtsi index f73f053a46a08d875acdeeef9ac195a9b857ae3f..e2f6e342db7e2f7cfbda17cbe28199546de5449d 100644 --- a/arch/arm64/boot/dts/qcom/x1-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-crd.dtsi @@ -1460,6 +1460,22 @@ &tlmm { <44 4>, /* SPI (TPM) */ <238 1>; /* UFS Reset */ + cam_rgb_default: cam-rgb-default-state { + mclk-pins { + pins = "gpio100"; + function = "cam_aon"; + drive-strength = <16>; + bias-disable; + }; + + reset-n-pins { + pins = "gpio237"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; + edp_reg_en: edp-reg-en-state { pins = "gpio70"; function = "gpio"; From patchwork Thu Apr 17 11:27:06 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 882122 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F1D623AE7B for ; Thu, 17 Apr 2025 11:27:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744889235; cv=none; b=Swgg9+aSIQZWxRL9u9pDbrmeyLAHAVyEPzyU/Kd/vG/s8s3FNNavqn29P/6LMaaZQVI0yIAG5/Kv65DcGOPtjOcrzujLQwhzJ3XDMg74gbTGHtWPtnz0/BaffpVMZNFuaXi/1jEkD2IeT6xrj7lW80Df9sSGdmU8a3qMhdNmwL0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744889235; c=relaxed/simple; bh=NcriGYMZwRZRM1Qw6vuW4UuCPYe+VfMiyfd9EF14yzA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=NbvPpJm9L0SLLdmxeoF9MMKHHFbjXQekowDlhkYhEpEpcIuhUtVHaCtiutnqOCOjjd142j2fy/zjX7qSM6MHlUzLhDFgsiF0WbbtGPm+YZVeV4WGUWdUYXN57GvjMCBal5HwUIiq0QzxLVat28ExEtsSAkawzXcRJQ9snGDPplc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=zr4dOeTW; arc=none smtp.client-ip=209.85.128.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="zr4dOeTW" Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-43cf257158fso4626905e9.2 for ; Thu, 17 Apr 2025 04:27:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1744889231; x=1745494031; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=VcZh3O74YpUyGxnBpp2yZbicwq/KGRckATMaGfA2GkA=; b=zr4dOeTWbXHGv/WSI1kV148Pl/EjZ2k65+XUgNp/h8XxtTjG1WN9VA2uhR+zahX5+z qNUGpNw/4+BOb4Zi9NmnblJT9wfklKrxokcCnTabKPxuBrnjQkXz6qPnBLKvihEvYLZR Ae6OefkkDV1V2OhJQDxLIxph30sOCs8LCtrwiUfYUpaxzfUznquKRv1wrIvxnM5UepcO m9z01WGZ1WUDWA190Hh+3kjYTXR/dOoqBOTgyotXYHt7/ZHfFtIcGu1d1nxnYHC0DKQr IMatADvBVsCUGNyz6s+lIwLdK/AwlXIpwW36E+9JGZXURozkt4J9l7qa5I/g+iH7WSUH 7vXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744889231; x=1745494031; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VcZh3O74YpUyGxnBpp2yZbicwq/KGRckATMaGfA2GkA=; b=Phpl9nTmUbLeyPB3m1/nw4tOCgv8hAPGYOVC+2wfbT8uA+CjMNmfzocL3cWLmnCDed AmaC35iMdlATrWsxmeumXSv6BbyfyXdXDbgJyVMmWQ8o2LjLAwMyvepd05goHFCeoUcP Q+eAydQV3dBP18yK3WJAIFQ5jez7mMWzBDryz1988eYkgvkDfQODOVNem12Kwsg4a0bU urM9gpfD24Z3uDFKjWZs6mf3htPMfZ1Y5A206rdxkamtPCe/5XkEz2xAsjd31MOKziOp 30qMihsv35Vxi/qVZG7yX09XJ5CjsbYSsG7ENF7j2ez/fd4McUpIVMXhnELn7wCL+T+X mctA== X-Forwarded-Encrypted: i=1; AJvYcCU2dLyJyfkPcvGvUaacXq9ZwVDJQHk6TNu4CbihhY+lAeHBx8I5msoTW8M93BVQEHoNgUy+4DRuS8rAAg==@vger.kernel.org X-Gm-Message-State: AOJu0YyXd6qvKO+klPttHqpPDm6u4B+0L2CrDMusX0hhCJZVNYgMQe6v ecvpS0V+p73iR/pZEVODss0I7xjeRqzi2Zx7uKRO2zE3kEpGM4+XHPZDFnWdt2Y= X-Gm-Gg: ASbGnctkoYGT9NOCaTAaV3QBXUYwh7z2+RSW+VJCt3KPmFTnUfZGdbSLHTw/ybjztoT Ij6dAXVFGirC3/6XpWakrOGji+rXdPZzRVrNMngkvEHlmcas2FHsbki/FmqCX0+sWcqpnlo8j4R rrqsIE2S5yq4AabmtLCWAJ7fzA+AmgmZ1Z8D56z8oF33ist7NgjpS19ktNQiemC6gBQuVpO/eXv UCzbfhEJ7dVteH9OqHaN90JM6vhq7ptoYEdFxhPgvCUnyWjnMr4+FsiGnhTRY3BTnseEo3mBbrn QKQHzWCc9gALVEEgdUA2gOZGu5avOyajJAPKasaJ7KdRMvaNUTWCkAgoO5EyhOtrB8Ah54GJcuK z0S4ncA== X-Google-Smtp-Source: AGHT+IHYDrL+8g1EtW3z+xAlBB/JWa/n5mlaOnthkSWN9ndNXgNcV4bD3PEl2KB/vdDssbFxhpK52w== X-Received: by 2002:a05:600c:1c22:b0:43c:f85d:1245 with SMTP id 5b1f17b1804b1-4405d62a53fmr55768145e9.17.1744889231465; Thu, 17 Apr 2025 04:27:11 -0700 (PDT) Received: from [192.168.0.34] (188-141-3-146.dynamic.upc.ie. [188.141.3.146]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39eae96400dsm20144063f8f.11.2025.04.17.04.27.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Apr 2025 04:27:11 -0700 (PDT) From: Bryan O'Donoghue Date: Thu, 17 Apr 2025 12:27:06 +0100 Subject: [PATCH v7 5/6] arm64: dts: qcom: x1e80100-crd: Add pm8010 CRD pmic,id=m regulators Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250417-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v7-5-3fd4124cf35a@linaro.org> References: <20250417-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v7-0-3fd4124cf35a@linaro.org> In-Reply-To: <20250417-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v7-0-3fd4124cf35a@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Robert Foss , Todor Tomov , Mauro Carvalho Chehab , Konrad Dybcio Cc: Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, Bryan O'Donoghue X-Mailer: b4 0.14.2 Add pmic,id = m rpmh to regulator definitions. This regulator set provides vreg_l3m_1p8 the regulator for the ov08x40 RGB sensor on the CRD. Signed-off-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/x1-crd.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1-crd.dtsi b/arch/arm64/boot/dts/qcom/x1-crd.dtsi index e2f6e342db7e2f7cfbda17cbe28199546de5449d..74bf2f48d93522d3f5b7ca990c06519ca664d905 100644 --- a/arch/arm64/boot/dts/qcom/x1-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-crd.dtsi @@ -858,6 +858,36 @@ vreg_l3j_0p8: ldo3 { regulator-initial-mode = ; }; }; + + regulators-8 { + compatible = "qcom,pm8010-rpmh-regulators"; + qcom,pmic-id = "m"; + + vdd-l1-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-l4-supply = <&vreg_s4c_1p8>; + vdd-l7-supply = <&vreg_bob1>; + + vreg_l3m_1p8: ldo3 { + regulator-name = "vreg_l3m_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1808000>; + regulator-initial-mode = ; + }; + + vrer_l4m_1p8: ldo4 { + regulator-name = "vrer_l4m_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1808000>; + regulator-initial-mode = ; + }; + + vreg_l7m_2p9: ldo7 { + regulator-name = "vreg_l7m_2p9"; + regulator-min-microvolt = <2912000>; + regulator-max-microvolt = <2912000>; + regulator-initial-mode = ; + }; + }; }; &gpu { From patchwork Thu Apr 17 11:27:07 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 882499 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C0F22417F0 for ; Thu, 17 Apr 2025 11:27:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744889238; cv=none; b=DcQ5q59kq2NhJg+X/6zbh5v0/mzM/A89/7cTPgBWnmlfepZXZG8TriOod2fRCbNOPn8P9TAXieePbPiosUvY5kbcTtPqP44Sia7ZDYKOlv/b1aYAWAFTSzahIB4OWuPBVz2PuvbsJm/VTJ5WyTmNTPpC1ULTMmS2pSitnaI6uWc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744889238; c=relaxed/simple; bh=2nnKPnNKSenGk7oH+W/zKyt+Vs9nyo2TyOcvxnYkJUo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=pMVo6Ce5ZOLlx0TO1ClFOI8cuDNtPyuujA2/RBxiqc1xVknXwliII1a0Q6czpV+umkqTw73F5ymb2/6vW+I6gyuaPTdGR8JD3r2raWapQlPCY9CWKsEPqoqI27AEg7DMNWHQkWEn8ftDlcDfG5pZpjH1ZuE2M/cdV7hMbYnmm+8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=qce22+Mm; arc=none smtp.client-ip=209.85.128.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="qce22+Mm" Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-43cf257158fso4627055e9.2 for ; Thu, 17 Apr 2025 04:27:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1744889233; x=1745494033; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Mn6UYVV7ZzZexDC3IKQgx7MkJK5bKEbv3iNQ8BNX+8I=; b=qce22+MmVOpq8gspYBBebktf0hkeW/6Dw0KtR75F68pVR7+Hl6BcvJoOFpwKp/TZwe kmvzaPWy/5TlOKoDwRZRF42Jny/EKAI6ws6Ps3KNqJ9dpEXabrScj30unZ2AEftMUkBh Mn5laNRNtXwnCTQb1YUPk20l29xDFUTX6HQygtp+ulkjCcemC8C20WUGlZXxH2zFgTyO o/DhMVogOebZG6vU7u5jNkhoelx64jEVrTPoVtHB2jHIJTIsufBu47wO84N2rQOvLSxu iwzJbqSTYS84i0IhJK3T2A7lGneE53g6D+SFrb2eCAoE78ceJ9KBJja4sIQlSVkhjf+T ZaHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744889233; x=1745494033; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Mn6UYVV7ZzZexDC3IKQgx7MkJK5bKEbv3iNQ8BNX+8I=; b=RuyO2FZ2gutUaGnGQ2H5QlUD1p+9wTBmxsTclKWD8h2JgLsTRASiJPOUZQm0rG1AeH UM3XS+G/7AtPbOv7v5nYMLa49i2U9IOGVqVP/ahrZX3+Pnf5ZLoONSop3rYW3lzBxWbi YOtuBCNSNTWQJ4muXeBweCg2u3mYNNor1vDRHnZ/OnTZpHO98KsMbB32vtxf1tApiYfe ym+UPi4uTt7LKZO2lPIZgHiyzpV9n0GcXudQQx50WJO5KJ7JGZ6XVGvtixq+0btp3We1 knLfMkloV7MsKQXhJQsTJe/kiwUCk2ZiFPv5Echx/Kf9ZuTtRlSY/Ac6BHcxLYvODroE QfEQ== X-Forwarded-Encrypted: i=1; AJvYcCXyKDdBkV+TV9ID45SOFAI8yiin5brEZE/T2vArvo592tpXAo3zIu84BjYIg5zY1MXsQJSI4g48ml1/Mw==@vger.kernel.org X-Gm-Message-State: AOJu0YyZXhIwc1uPJIOwF7g8Dmnjbc+nxMARYWAN3u3ZSUQoQUbYdWqp YDmprEBwBmvPk6QaJQNklKrjVHSX54Pl/r8X0fbvd+zjvK96vA8Wl0KzARKL0MQ= X-Gm-Gg: ASbGncug37/O2NPIn039oQyv9NTgUS3hMErzbhb773cuNy5rb+9flsJqE+5h2Lbe07V E2tSt0A0ZKp/sCpfBgpruSLGjB8cwoJnIDHMguZkXDlelAeYDLeHSzXKZ5URWMiUtHF0u6Ll6vu 65F0SbPmaH4M/sF0zA6+3x28KA67S/u5KdCUfIhUYnuaW7SwKn5SErkPh0DzOxlmlTQVBkWKlfI 9IEsTGhA0dmMYA6cdCWPr6uGH76SN0lvTsFDwX9rZOXIRQXHSQTS9LF5hIPnZnQ6zzcJtMjY/ra r/YDc+MI2zWPYaxsYS01S2OFJ/bCjzJdTJxsQloikCs04YK/jLdAUQ74CVKn2zfnvhisKlBDRB2 awgBZLQ== X-Google-Smtp-Source: AGHT+IEUqScCO1azSIC6mQA8vGrm3CDpp/x7AVftuXoA1RfRc/gtPvrF3kjcLdpXweKxDtGUu+/VdA== X-Received: by 2002:a05:600c:c0b:b0:43d:934:ea97 with SMTP id 5b1f17b1804b1-4405d6df1fcmr54165755e9.27.1744889232626; Thu, 17 Apr 2025 04:27:12 -0700 (PDT) Received: from [192.168.0.34] (188-141-3-146.dynamic.upc.ie. [188.141.3.146]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39eae96400dsm20144063f8f.11.2025.04.17.04.27.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Apr 2025 04:27:12 -0700 (PDT) From: Bryan O'Donoghue Date: Thu, 17 Apr 2025 12:27:07 +0100 Subject: [PATCH v7 6/6] arm64: dts: qcom: x1e80100-crd: Define RGB sensor for cci1_i2c1 Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250417-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v7-6-3fd4124cf35a@linaro.org> References: <20250417-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v7-0-3fd4124cf35a@linaro.org> In-Reply-To: <20250417-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v7-0-3fd4124cf35a@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Robert Foss , Todor Tomov , Mauro Carvalho Chehab , Konrad Dybcio Cc: Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, Bryan O'Donoghue X-Mailer: b4 0.14.2 Define ov08x40 on cci1_i2c1. The RGB sensor appears on the AON CCI pins connected to CSIPHY4 in four lane mode. Signed-off-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/x1-crd.dtsi | 60 ++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1-crd.dtsi b/arch/arm64/boot/dts/qcom/x1-crd.dtsi index 74bf2f48d93522d3f5b7ca990c06519ca664d905..048e49aa805c7239e1a22b59bd784683d1d0da08 100644 --- a/arch/arm64/boot/dts/qcom/x1-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-crd.dtsi @@ -894,6 +894,66 @@ &gpu { status = "okay"; }; +&camcc { + status = "okay"; +}; + +&camss { + vdd-csiphy-0p8-supply = <&vreg_l2c_0p8>; + vdd-csiphy-1p2-supply = <&vreg_l1c_1p2>; + + status = "okay"; + + ports { + /* + * port0 => csiphy0 + * port1 => csiphy1 + * port2 => csiphy2 + * port3 => csiphy4 + */ + port@3 { + csiphy4_ep: endpoint@4 { + reg = <4>; + clock-lanes = <7>; + data-lanes = <0 1 2 3>; + remote-endpoint = <&ov08x40_ep>; + }; + }; + }; +}; + +&cci1 { + status = "okay"; +}; + +&cci1_i2c1 { + camera@36 { + compatible = "ovti,ov08x40"; + reg = <0x36>; + + reset-gpios = <&tlmm 237 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_rgb_default>; + + clocks = <&camcc CAM_CC_MCLK4_CLK>; + assigned-clocks = <&camcc CAM_CC_MCLK4_CLK>; + assigned-clock-rates = <19200000>; + + orientation = <0>; /* front facing */ + + avdd-supply = <&vreg_l7b_2p8>; + dovdd-supply = <&vreg_l3m_1p8>; + + port { + ov08x40_ep: endpoint { + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <400000000>; + remote-endpoint = <&csiphy4_ep>; + }; + }; + }; +}; + &i2c0 { clock-frequency = <400000>;