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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73dbf8e4932sm9448160b3a.55.2025.04.22.14.11.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 14:11:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, Pierrick Bouvier Subject: [PULL 1/9] target/avr: Improve decode of LDS, STS Date: Tue, 22 Apr 2025 14:11:16 -0700 Message-ID: <20250422211124.305724-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422211124.305724-1-richard.henderson@linaro.org> References: <20250422211124.305724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The comment about not being able to define a field with zero bits is out of date since 94597b6146f3 ("decodetree: Allow !function with no input bits"). This fixes the missing load of imm in the disassembler. Cc: qemu-stable@nongnu.org Fixes: 9d8caa67a24 ("target/avr: Add support for disassembling via option '-d in_asm'") Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/avr/translate.c | 2 -- target/avr/insn.decode | 7 ++----- 2 files changed, 2 insertions(+), 7 deletions(-) diff --git a/target/avr/translate.c b/target/avr/translate.c index 4ab71d8138..e7f8ced9b3 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -1578,7 +1578,6 @@ static bool trans_LDS(DisasContext *ctx, arg_LDS *a) TCGv Rd = cpu_r[a->rd]; TCGv addr = tcg_temp_new_i32(); TCGv H = cpu_rampD; - a->imm = next_word(ctx); tcg_gen_mov_tl(addr, H); /* addr = H:M:L */ tcg_gen_shli_tl(addr, addr, 16); @@ -1783,7 +1782,6 @@ static bool trans_STS(DisasContext *ctx, arg_STS *a) TCGv Rd = cpu_r[a->rd]; TCGv addr = tcg_temp_new_i32(); TCGv H = cpu_rampD; - a->imm = next_word(ctx); tcg_gen_mov_tl(addr, H); /* addr = H:M:L */ tcg_gen_shli_tl(addr, addr, 16); diff --git a/target/avr/insn.decode b/target/avr/insn.decode index 482c23ad0c..cc302249db 100644 --- a/target/avr/insn.decode +++ b/target/avr/insn.decode @@ -118,11 +118,8 @@ BRBC 1111 01 ....... ... @op_bit_imm @io_rd_imm .... . .. ..... .... &rd_imm rd=%rd imm=%io_imm @ldst_d .. . . .. . rd:5 . ... &rd_imm imm=%ldst_d_imm -# The 16-bit immediate is completely in the next word. -# Fields cannot be defined with no bits, so we cannot play -# the same trick and append to a zero-bit value. -# Defer reading the immediate until trans_{LDS,STS}. -@ldst_s .... ... rd:5 .... imm=0 +%ldst_imm !function=next_word +@ldst_s .... ... rd:5 .... imm=%ldst_imm MOV 0010 11 . ..... .... @op_rd_rr MOVW 0000 0001 .... .... &rd_rr rd=%rd_d rr=%rr_d From patchwork Tue Apr 22 21:11:17 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 883153 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp2623140wrs; Tue, 22 Apr 2025 14:11:51 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVIl35rv3p2rLZMxaV0gpQiWTzJdbQw2wmEtdf6+77WyLVgckWVSp5dyL7SdWAhixcYJvarvg==@linaro.org X-Google-Smtp-Source: AGHT+IGu3mTvg8ipuAPtfYfXcVsohdTwJz0rnflrBmwvXcs21KdJ6kknt2QMQE9Q9QILDmV7k9LK X-Received: by 2002:a05:620a:4544:b0:7c5:e2a0:4e64 with SMTP id af79cd13be357-7c9280494fdmr2861198585a.51.1745356311158; Tue, 22 Apr 2025 14:11:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1745356311; cv=none; d=google.com; s=arc-20240605; b=PfJmE8MBrN6/qZCwaVACmZulplNxMbh5mjkaP7zgjespIc3TWicT6Mb3qZMzotXzDx B+ZsgLRvDdq3W+NNJk5hyBGIDITSXxQjqrlpospEAPoFywD2zTZgNDJ1p0bPQuT63ZEG UxsADBWGxfK0cFACJR19Lj8uqXieDhHVJIMmByqY3Rcx1q4tJDTh6vZe7V5C+/Oqfa7s KdqSqzymf0Oeoqzp4APaDTrk5/ilfq6RqrmideuIktqUEJF6x+knddkiT1o1baBD8XdM mZMF2y9kCXz+ovlrf+eFSiCx5LfnWHB+E9aCogbR+GMwIVXhcT8xHj3i1DG7qH56oZVU uYDQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=whE4tOIG14eY8JQ2gptqlrplDWnqt4RDL3Ybv6G0d7s=; fh=i/pWNGcx7KiR3ewgypxpPkuORYlkCnVXLqKVm9/UgNc=; b=CqsrNdMOgisKccP0VmYYCOAbrCHUsMPstu3KYb7TRVPZzGOBFM/lOAe3I7qPeUKZYr 3oJHb/vAc0dRnsUCekfURMr9bQQFV/LE2f5YvLXuZeWDolHkLv5tMymSbd1Z740UaN4G FzhslxQjTBh24i63ufz/g5C1o7xrj5W8mP1MswC5rLfD+9lS+/gzUY9d7Lt10gDZOrf9 KBAsvhOMGJYQ7949Z1xOKqhsnlBc3ITpgYg6jmPUGbI03FfIdh871SxWcP8xq2mBo6C8 YqnvFSbYtOr8GCQPbyrPpVBlNmu0O5JgxCwvV/dACGnAfePt/MqN9OKSFiiZkN0sBxUM MCMQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oykMgZ7s; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73dbf8e4932sm9448160b3a.55.2025.04.22.14.11.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 14:11:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PULL 2/9] target/avr: Remove OFFSET_CPU_REGISTERS Date: Tue, 22 Apr 2025 14:11:17 -0700 Message-ID: <20250422211124.305724-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422211124.305724-1-richard.henderson@linaro.org> References: <20250422211124.305724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This define isn't really used. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/avr/cpu.h | 2 -- target/avr/helper.c | 3 +-- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/target/avr/cpu.h b/target/avr/cpu.h index 06f5ae4d1b..84a8f5cc8c 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -60,8 +60,6 @@ #define OFFSET_CODE 0x00000000 /* CPU registers, IO registers, and SRAM */ #define OFFSET_DATA 0x00800000 -/* CPU registers specifically, these are mapped at the start of data */ -#define OFFSET_CPU_REGISTERS OFFSET_DATA /* * IO registers, including status register, stack pointer, and memory * mapped peripherals, mapped just after CPU registers diff --git a/target/avr/helper.c b/target/avr/helper.c index 3412312ad5..e5bf16c6b7 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -340,8 +340,7 @@ void helper_fullwr(CPUAVRState *env, uint32_t data, uint32_t addr) env->fullacc = false; /* Following logic assumes this: */ - assert(OFFSET_CPU_REGISTERS == OFFSET_DATA); - assert(OFFSET_IO_REGISTERS == OFFSET_CPU_REGISTERS + + assert(OFFSET_IO_REGISTERS == OFFSET_DATA + NUMBER_OF_CPU_REGISTERS); if (addr < NUMBER_OF_CPU_REGISTERS) { From patchwork Tue Apr 22 21:11:18 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 883156 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp2623256wrs; Tue, 22 Apr 2025 14:12:09 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWh+iSA/Au9C7UJxP0B+giGeO+I8rlpOvJo7RGD4ceHIHFvF8Pj4tHRNwTMRSUt1QNkF2OWmQ==@linaro.org X-Google-Smtp-Source: AGHT+IHLabzymQO45JdlZVIdwdXXvreTxaslPLF22JuRyLeWNZi6IVmWVIuFeeI05dHHp75MEtQx X-Received: by 2002:ac8:5954:0:b0:47a:e63b:ec60 with SMTP id d75a77b69052e-47aec3cb62bmr274087071cf.27.1745356328979; Tue, 22 Apr 2025 14:12:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1745356328; cv=none; d=google.com; s=arc-20240605; b=Dj9zIC7Bke1LTmYj10wyCngmna6iLPUxnWO9wLVKfGBC4eblW8ZQY/SAmwsEVp/YxZ NjPD8MiuuKw5SuOuJu4W9fO7nGZB3ULprYBSUSuQ9QckvBrG4tb+P9P0lyD3h5H5VgIA JRwOtGbySApKn7uVauMe/IKsmye2Zw8TvnG2Yr7B9y1VBEUULVXiHD5jo7HzYOMwbA5q 7afBjEOCnO+EDYcEZa4AcgQtiELBY4Q4uV6dt3zMNvOyspFO1WIsfkfKIXKa+do8InwT dQ9mh9MQTByDeIbSicYaineC+Arka1UQK2eQicxomDPywC+bQ/FxQtCvqgQXNL7eYnCS 5vlA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=X7HP2zbvSkDBMLOLYhU6UsrfPqpzWt02XJu5z93nvtA=; fh=i/pWNGcx7KiR3ewgypxpPkuORYlkCnVXLqKVm9/UgNc=; b=G2SIZ4tbc0esi/ucV6UDm2ckT1sg4tqhIDE4AWU40McEEKNH5IBFs9bUuRnYuSQWN9 ajgj+qg5do4N7WUGDVaFAZn5fdNoHiywTuT74SGoWhZckjcipJCTSBTi8Awu+ngtuOiL hgeOdc0eNO4OcCwO09ASFJdseckxEczMJZnWTXMyJrN9aDZsY3UM4mh078+CfUrCwY5J HtJjuXIEMe8Yt09Eb5rRdppZmPR+ag57zoJaxT4uZfBPXrGaFZyu9ZIGKXkMuSrcVFkn pwwQqIMnlLpIky4MuvINM9GI9qW8o9Adb5RMfcSArMCnmM/1tJUohQGHRKoh748qWcyZ 6IPA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Yiptxcol; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73dbf8e4932sm9448160b3a.55.2025.04.22.14.11.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 14:11:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PULL 3/9] target/avr: Add defines for i/o port registers Date: Tue, 22 Apr 2025 14:11:18 -0700 Message-ID: <20250422211124.305724-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422211124.305724-1-richard.henderson@linaro.org> References: <20250422211124.305724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/avr/cpu.h | 10 ++++++++++ target/avr/helper.c | 36 ++++++++++++++++++------------------ 2 files changed, 28 insertions(+), 18 deletions(-) diff --git a/target/avr/cpu.h b/target/avr/cpu.h index 84a8f5cc8c..1a5a5b8e3e 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -47,6 +47,16 @@ /* Number of IO registers accessible by ld/st/in/out */ #define NUMBER_OF_IO_REGISTERS 64 +/* CPU registers mapped into i/o ports 0x38-0x3f. */ +#define REG_38_RAMPD 0 +#define REG_38_RAMPX 1 +#define REG_38_RAMPY 2 +#define REG_38_RAMPZ 3 +#define REG_38_EIDN 4 +#define REG_38_SPL 5 +#define REG_38_SPH 6 +#define REG_38_SREG 7 + /* * Offsets of AVR memory regions in host memory space. * diff --git a/target/avr/helper.c b/target/avr/helper.c index e5bf16c6b7..f8ada8b106 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -216,29 +216,29 @@ target_ulong helper_inb(CPUAVRState *env, uint32_t port) { target_ulong data = 0; - switch (port) { - case 0x38: /* RAMPD */ + switch (port - 0x38) { + case REG_38_RAMPD: data = 0xff & (env->rampD >> 16); break; - case 0x39: /* RAMPX */ + case REG_38_RAMPX: data = 0xff & (env->rampX >> 16); break; - case 0x3a: /* RAMPY */ + case REG_38_RAMPY: data = 0xff & (env->rampY >> 16); break; - case 0x3b: /* RAMPZ */ + case REG_38_RAMPZ: data = 0xff & (env->rampZ >> 16); break; - case 0x3c: /* EIND */ + case REG_38_EIDN: data = 0xff & (env->eind >> 16); break; - case 0x3d: /* SPL */ + case REG_38_SPL: data = env->sp & 0x00ff; break; - case 0x3e: /* SPH */ + case REG_38_SPH: data = env->sp >> 8; break; - case 0x3f: /* SREG */ + case REG_38_SREG: data = cpu_get_sreg(env); break; default: @@ -265,39 +265,39 @@ void helper_outb(CPUAVRState *env, uint32_t port, uint32_t data) { data &= 0x000000ff; - switch (port) { - case 0x38: /* RAMPD */ + switch (port - 0x38) { + case REG_38_RAMPD: if (avr_feature(env, AVR_FEATURE_RAMPD)) { env->rampD = (data & 0xff) << 16; } break; - case 0x39: /* RAMPX */ + case REG_38_RAMPX: if (avr_feature(env, AVR_FEATURE_RAMPX)) { env->rampX = (data & 0xff) << 16; } break; - case 0x3a: /* RAMPY */ + case REG_38_RAMPY: if (avr_feature(env, AVR_FEATURE_RAMPY)) { env->rampY = (data & 0xff) << 16; } break; - case 0x3b: /* RAMPZ */ + case REG_38_RAMPZ: if (avr_feature(env, AVR_FEATURE_RAMPZ)) { env->rampZ = (data & 0xff) << 16; } break; - case 0x3c: /* EIDN */ + case REG_38_EIDN: env->eind = (data & 0xff) << 16; break; - case 0x3d: /* SPL */ + case REG_38_SPL: env->sp = (env->sp & 0xff00) | (data); break; - case 0x3e: /* SPH */ + case REG_38_SPH: if (avr_feature(env, AVR_FEATURE_2_BYTE_SP)) { env->sp = (env->sp & 0x00ff) | (data << 8); } break; - case 0x3f: /* SREG */ + case REG_38_SREG: cpu_set_sreg(env, data); break; default: From patchwork Tue Apr 22 21:11:19 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 883162 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp2623723wrs; Tue, 22 Apr 2025 14:13:21 -0700 (PDT) X-Forwarded-Encrypted: i=2; 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73dbf8e4932sm9448160b3a.55.2025.04.22.14.11.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 14:11:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PULL 4/9] target/avr: Move cpu register accesses into system memory Date: Tue, 22 Apr 2025 14:11:19 -0700 Message-ID: <20250422211124.305724-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422211124.305724-1-richard.henderson@linaro.org> References: <20250422211124.305724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Integrate the i/o 0x00-0x1f and 0x38-0x3f loopbacks into the cpu registers with normal address space accesses. We no longer need to trap accesses to the first page within avr_cpu_tlb_fill but can wait until a write occurs. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/avr/cpu.h | 7 ++ target/avr/helper.h | 3 - target/avr/cpu.c | 16 +++ target/avr/helper.c | 223 +++++++++++++++++------------------------ target/avr/translate.c | 42 ++++---- 5 files changed, 138 insertions(+), 153 deletions(-) diff --git a/target/avr/cpu.h b/target/avr/cpu.h index 1a5a5b8e3e..6f68060ab0 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -23,6 +23,7 @@ #include "cpu-qom.h" #include "exec/cpu-defs.h" +#include "exec/memory.h" #ifdef CONFIG_USER_ONLY #error "AVR 8-bit does not support user mode" @@ -152,6 +153,9 @@ struct ArchCPU { CPUAVRState env; + MemoryRegion cpu_reg1; + MemoryRegion cpu_reg2; + /* Initial value of stack pointer */ uint32_t init_sp; }; @@ -252,6 +256,9 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +extern const MemoryRegionOps avr_cpu_reg1; +extern const MemoryRegionOps avr_cpu_reg2; + #include "exec/cpu-all.h" #endif /* QEMU_AVR_CPU_H */ diff --git a/target/avr/helper.h b/target/avr/helper.h index 4d02e648fa..e8d13e925f 100644 --- a/target/avr/helper.h +++ b/target/avr/helper.h @@ -23,7 +23,4 @@ DEF_HELPER_1(debug, noreturn, env) DEF_HELPER_1(break, noreturn, env) DEF_HELPER_1(sleep, noreturn, env) DEF_HELPER_1(unsupported, noreturn, env) -DEF_HELPER_3(outb, void, env, i32, i32) -DEF_HELPER_2(inb, tl, env, i32) DEF_HELPER_3(fullwr, void, env, i32, i32) -DEF_HELPER_2(fullrd, tl, env, i32) diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 834c7082aa..0b14b36c17 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -23,6 +23,7 @@ #include "qemu/qemu-print.h" #include "exec/exec-all.h" #include "exec/translation-block.h" +#include "exec/address-spaces.h" #include "cpu.h" #include "disas/dis-asm.h" #include "tcg/debug-assert.h" @@ -110,6 +111,8 @@ static void avr_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) static void avr_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs = CPU(dev); + CPUAVRState *env = cpu_env(cs); + AVRCPU *cpu = env_archcpu(env); AVRCPUClass *mcc = AVR_CPU_GET_CLASS(dev); Error *local_err = NULL; @@ -122,6 +125,19 @@ static void avr_cpu_realizefn(DeviceState *dev, Error **errp) cpu_reset(cs); mcc->parent_realize(dev, errp); + + /* + * Two blocks in the low data space loop back into cpu registers. + */ + memory_region_init_io(&cpu->cpu_reg1, OBJECT(cpu), &avr_cpu_reg1, env, + "avr-cpu-reg1", 32); + memory_region_add_subregion(get_system_memory(), + OFFSET_DATA, &cpu->cpu_reg1); + + memory_region_init_io(&cpu->cpu_reg2, OBJECT(cpu), &avr_cpu_reg2, env, + "avr-cpu-reg2", 8); + memory_region_add_subregion(get_system_memory(), + OFFSET_DATA + 0x58, &cpu->cpu_reg2); } static void avr_cpu_set_int(void *opaque, int irq, int level) diff --git a/target/avr/helper.c b/target/avr/helper.c index f8ada8b106..d0e86f5614 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -108,7 +108,7 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { - int prot, page_size = TARGET_PAGE_SIZE; + int prot; uint32_t paddr; address &= TARGET_PAGE_MASK; @@ -133,23 +133,9 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size, /* Access to memory. */ paddr = OFFSET_DATA + address; prot = PAGE_READ | PAGE_WRITE; - if (address < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) { - /* - * Access to CPU registers, exit and rebuilt this TB to use - * full access in case it touches specially handled registers - * like SREG or SP. For probing, set page_size = 1, in order - * to force tlb_fill to be called for the next access. - */ - if (probe) { - page_size = 1; - } else { - cpu_env(cs)->fullacc = 1; - cpu_loop_exit_restore(cs, retaddr); - } - } } - tlb_set_page(cs, address, paddr, prot, mmu_idx, page_size); + tlb_set_page(cs, address, paddr, prot, mmu_idx, TARGET_PAGE_SIZE); return true; } @@ -203,134 +189,78 @@ void helper_wdr(CPUAVRState *env) } /* - * This function implements IN instruction - * - * It does the following - * a. if an IO register belongs to CPU, its value is read and returned - * b. otherwise io address is translated to mem address and physical memory - * is read. - * c. it caches the value for sake of SBI, SBIC, SBIS & CBI implementation - * + * The first 32 bytes of the data space are mapped to the cpu regs. + * We cannot write these from normal store operations because TCG + * does not expect global temps to be modified -- a global may be + * live in a host cpu register across the store. We can however + * read these, as TCG does make sure the global temps are saved + * in case the load operation traps. */ -target_ulong helper_inb(CPUAVRState *env, uint32_t port) + +static uint64_t avr_cpu_reg1_read(void *opaque, hwaddr addr, unsigned size) { - target_ulong data = 0; + CPUAVRState *env = opaque; - switch (port - 0x38) { - case REG_38_RAMPD: - data = 0xff & (env->rampD >> 16); - break; - case REG_38_RAMPX: - data = 0xff & (env->rampX >> 16); - break; - case REG_38_RAMPY: - data = 0xff & (env->rampY >> 16); - break; - case REG_38_RAMPZ: - data = 0xff & (env->rampZ >> 16); - break; - case REG_38_EIDN: - data = 0xff & (env->eind >> 16); - break; - case REG_38_SPL: - data = env->sp & 0x00ff; - break; - case REG_38_SPH: - data = env->sp >> 8; - break; - case REG_38_SREG: - data = cpu_get_sreg(env); - break; - default: - /* not a special register, pass to normal memory access */ - data = address_space_ldub(&address_space_memory, - OFFSET_IO_REGISTERS + port, - MEMTXATTRS_UNSPECIFIED, NULL); - } - - return data; + assert(addr < 32); + return env->r[addr]; } /* - * This function implements OUT instruction - * - * It does the following - * a. if an IO register belongs to CPU, its value is written into the register - * b. otherwise io address is translated to mem address and physical memory - * is written. - * c. it caches the value for sake of SBI, SBIC, SBIS & CBI implementation - * + * The range 0x38-0x3f of the i/o space is mapped to cpu regs. + * As above, we cannot write these from normal store operations. */ -void helper_outb(CPUAVRState *env, uint32_t port, uint32_t data) -{ - data &= 0x000000ff; - switch (port - 0x38) { +static uint64_t avr_cpu_reg2_read(void *opaque, hwaddr addr, unsigned size) +{ + CPUAVRState *env = opaque; + + switch (addr) { case REG_38_RAMPD: - if (avr_feature(env, AVR_FEATURE_RAMPD)) { - env->rampD = (data & 0xff) << 16; - } - break; + return 0xff & (env->rampD >> 16); case REG_38_RAMPX: - if (avr_feature(env, AVR_FEATURE_RAMPX)) { - env->rampX = (data & 0xff) << 16; - } - break; + return 0xff & (env->rampX >> 16); case REG_38_RAMPY: - if (avr_feature(env, AVR_FEATURE_RAMPY)) { - env->rampY = (data & 0xff) << 16; - } - break; + return 0xff & (env->rampY >> 16); case REG_38_RAMPZ: - if (avr_feature(env, AVR_FEATURE_RAMPZ)) { - env->rampZ = (data & 0xff) << 16; - } - break; + return 0xff & (env->rampZ >> 16); case REG_38_EIDN: - env->eind = (data & 0xff) << 16; - break; + return 0xff & (env->eind >> 16); case REG_38_SPL: - env->sp = (env->sp & 0xff00) | (data); - break; + return env->sp & 0x00ff; case REG_38_SPH: - if (avr_feature(env, AVR_FEATURE_2_BYTE_SP)) { - env->sp = (env->sp & 0x00ff) | (data << 8); - } - break; + return 0xff & (env->sp >> 8); case REG_38_SREG: - cpu_set_sreg(env, data); - break; - default: - /* not a special register, pass to normal memory access */ - address_space_stb(&address_space_memory, OFFSET_IO_REGISTERS + port, - data, MEMTXATTRS_UNSPECIFIED, NULL); + return cpu_get_sreg(env); } + g_assert_not_reached(); } -/* - * this function implements LD instruction when there is a possibility to read - * from a CPU register - */ -target_ulong helper_fullrd(CPUAVRState *env, uint32_t addr) +static void avr_cpu_trap_write(void *opaque, hwaddr addr, + uint64_t data64, unsigned size) { - uint8_t data; + CPUAVRState *env = opaque; + CPUState *cs = env_cpu(env); - env->fullacc = false; - - if (addr < NUMBER_OF_CPU_REGISTERS) { - /* CPU registers */ - data = env->r[addr]; - } else if (addr < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) { - /* IO registers */ - data = helper_inb(env, addr - NUMBER_OF_CPU_REGISTERS); - } else { - /* memory */ - data = address_space_ldub(&address_space_memory, OFFSET_DATA + addr, - MEMTXATTRS_UNSPECIFIED, NULL); - } - return data; + env->fullacc = true; + cpu_loop_exit_restore(cs, cs->mem_io_pc); } +const MemoryRegionOps avr_cpu_reg1 = { + .read = avr_cpu_reg1_read, + .write = avr_cpu_trap_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid.min_access_size = 1, + .valid.max_access_size = 1, +}; + +const MemoryRegionOps avr_cpu_reg2 = { + .read = avr_cpu_reg2_read, + .write = avr_cpu_trap_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid.min_access_size = 1, + .valid.max_access_size = 1, +}; + /* * this function implements ST instruction when there is a possibility to write * into a CPU register @@ -339,19 +269,50 @@ void helper_fullwr(CPUAVRState *env, uint32_t data, uint32_t addr) { env->fullacc = false; - /* Following logic assumes this: */ - assert(OFFSET_IO_REGISTERS == OFFSET_DATA + - NUMBER_OF_CPU_REGISTERS); - - if (addr < NUMBER_OF_CPU_REGISTERS) { + switch (addr) { + case 0 ... 31: /* CPU registers */ env->r[addr] = data; - } else if (addr < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) { - /* IO registers */ - helper_outb(env, addr - NUMBER_OF_CPU_REGISTERS, data); - } else { - /* memory */ + break; + + case REG_38_RAMPD + 0x38 + NUMBER_OF_CPU_REGISTERS: + if (avr_feature(env, AVR_FEATURE_RAMPD)) { + env->rampD = data << 16; + } + break; + case REG_38_RAMPX + 0x38 + NUMBER_OF_CPU_REGISTERS: + if (avr_feature(env, AVR_FEATURE_RAMPX)) { + env->rampX = data << 16; + } + break; + case REG_38_RAMPY + 0x38 + NUMBER_OF_CPU_REGISTERS: + if (avr_feature(env, AVR_FEATURE_RAMPY)) { + env->rampY = data << 16; + } + break; + case REG_38_RAMPZ + 0x38 + NUMBER_OF_CPU_REGISTERS: + if (avr_feature(env, AVR_FEATURE_RAMPZ)) { + env->rampZ = data << 16; + } + break; + case REG_38_EIDN + 0x38 + NUMBER_OF_CPU_REGISTERS: + env->eind = data << 16; + break; + case REG_38_SPL + 0x38 + NUMBER_OF_CPU_REGISTERS: + env->sp = (env->sp & 0xff00) | data; + break; + case REG_38_SPH + 0x38 + NUMBER_OF_CPU_REGISTERS: + if (avr_feature(env, AVR_FEATURE_2_BYTE_SP)) { + env->sp = (env->sp & 0x00ff) | (data << 8); + } + break; + case REG_38_SREG + 0x38 + NUMBER_OF_CPU_REGISTERS: + cpu_set_sreg(env, data); + break; + + default: address_space_stb(&address_space_memory, OFFSET_DATA + addr, data, MEMTXATTRS_UNSPECIFIED, NULL); + break; } } diff --git a/target/avr/translate.c b/target/avr/translate.c index e7f8ced9b3..0490936cd5 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -194,6 +194,9 @@ static bool avr_have_feature(DisasContext *ctx, int feature) static bool decode_insn(DisasContext *ctx, uint16_t insn); #include "decode-insn.c.inc" +static void gen_inb(DisasContext *ctx, TCGv data, int port); +static void gen_outb(DisasContext *ctx, TCGv data, int port); + /* * Arithmetic Instructions */ @@ -1293,9 +1296,8 @@ static bool trans_SBRS(DisasContext *ctx, arg_SBRS *a) static bool trans_SBIC(DisasContext *ctx, arg_SBIC *a) { TCGv data = tcg_temp_new_i32(); - TCGv port = tcg_constant_i32(a->reg); - gen_helper_inb(data, tcg_env, port); + gen_inb(ctx, data, a->reg); tcg_gen_andi_tl(data, data, 1 << a->bit); ctx->skip_cond = TCG_COND_EQ; ctx->skip_var0 = data; @@ -1311,9 +1313,8 @@ static bool trans_SBIC(DisasContext *ctx, arg_SBIC *a) static bool trans_SBIS(DisasContext *ctx, arg_SBIS *a) { TCGv data = tcg_temp_new_i32(); - TCGv port = tcg_constant_i32(a->reg); - gen_helper_inb(data, tcg_env, port); + gen_inb(ctx, data, a->reg); tcg_gen_andi_tl(data, data, 1 << a->bit); ctx->skip_cond = TCG_COND_NE; ctx->skip_var0 = data; @@ -1502,11 +1503,18 @@ static void gen_data_store(DisasContext *ctx, TCGv data, TCGv addr) static void gen_data_load(DisasContext *ctx, TCGv data, TCGv addr) { - if (ctx->base.tb->flags & TB_FLAGS_FULL_ACCESS) { - gen_helper_fullrd(data, tcg_env, addr); - } else { - tcg_gen_qemu_ld_tl(data, addr, MMU_DATA_IDX, MO_UB); - } + tcg_gen_qemu_ld_tl(data, addr, MMU_DATA_IDX, MO_UB); +} + +static void gen_inb(DisasContext *ctx, TCGv data, int port) +{ + gen_data_load(ctx, data, tcg_constant_i32(port + NUMBER_OF_CPU_REGISTERS)); +} + +static void gen_outb(DisasContext *ctx, TCGv data, int port) +{ + gen_helper_fullwr(tcg_env, data, + tcg_constant_i32(port + NUMBER_OF_CPU_REGISTERS)); } /* @@ -2126,9 +2134,8 @@ static bool trans_SPMX(DisasContext *ctx, arg_SPMX *a) static bool trans_IN(DisasContext *ctx, arg_IN *a) { TCGv Rd = cpu_r[a->rd]; - TCGv port = tcg_constant_i32(a->imm); - gen_helper_inb(Rd, tcg_env, port); + gen_inb(ctx, Rd, a->imm); return true; } @@ -2139,9 +2146,8 @@ static bool trans_IN(DisasContext *ctx, arg_IN *a) static bool trans_OUT(DisasContext *ctx, arg_OUT *a) { TCGv Rd = cpu_r[a->rd]; - TCGv port = tcg_constant_i32(a->imm); - gen_helper_outb(tcg_env, port, Rd); + gen_outb(ctx, Rd, a->imm); return true; } @@ -2407,11 +2413,10 @@ static bool trans_SWAP(DisasContext *ctx, arg_SWAP *a) static bool trans_SBI(DisasContext *ctx, arg_SBI *a) { TCGv data = tcg_temp_new_i32(); - TCGv port = tcg_constant_i32(a->reg); - gen_helper_inb(data, tcg_env, port); + gen_inb(ctx, data, a->reg); tcg_gen_ori_tl(data, data, 1 << a->bit); - gen_helper_outb(tcg_env, port, data); + gen_outb(ctx, data, a->reg); return true; } @@ -2422,11 +2427,10 @@ static bool trans_SBI(DisasContext *ctx, arg_SBI *a) static bool trans_CBI(DisasContext *ctx, arg_CBI *a) { TCGv data = tcg_temp_new_i32(); - TCGv port = tcg_constant_i32(a->reg); - gen_helper_inb(data, tcg_env, port); + gen_inb(ctx, data, a->reg); tcg_gen_andi_tl(data, data, ~(1 << a->bit)); - gen_helper_outb(tcg_env, port, data); + gen_outb(ctx, data, a->reg); return true; } From patchwork Tue Apr 22 21:11:20 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 883155 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp2623168wrs; Tue, 22 Apr 2025 14:11:57 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUFPyL6xQnA/MamDHcOO0HAQt+CNbpvoAVetK169mEYOYuBU/lGSVQq4qr+Qe2/CheeUo8thw==@linaro.org X-Google-Smtp-Source: AGHT+IFCdLW+IrK1k0X9J5+T8K46iDLqB51eq4HX84Ra/RfytlRKy69lNsV/42sRoSnyle7tu0SG X-Received: by 2002:a05:6214:250c:b0:6e8:fbe2:2db0 with SMTP id 6a1803df08f44-6f2c463f955mr231826226d6.30.1745356316762; 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Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/avr/cpu.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/avr/cpu.h b/target/avr/cpu.h index 6f68060ab0..9862705c6a 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -45,8 +45,6 @@ /* Number of CPU registers */ #define NUMBER_OF_CPU_REGISTERS 32 -/* Number of IO registers accessible by ld/st/in/out */ -#define NUMBER_OF_IO_REGISTERS 64 /* CPU registers mapped into i/o ports 0x38-0x3f. */ #define REG_38_RAMPD 0 From patchwork Tue Apr 22 21:11:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 883161 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp2623700wrs; Tue, 22 Apr 2025 14:13:16 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVxZMHpkHe0lXA2VCgIgQou4SfE4vjbWsjHVwsEZ1nunVub/EGfTj6LY6srLBwQnM/taniWmA==@linaro.org X-Google-Smtp-Source: AGHT+IET/YhXFQrjmvBgFYmKk8FyXkqhyJlikvJzJIsmciEp3Ase1Hav/i5+e/I4mjgNdblnxRWu X-Received: by 2002:a05:6214:21ef:b0:6e6:684f:7f78 with SMTP id 6a1803df08f44-6f2c450c0d2mr278746806d6.3.1745356396016; Tue, 22 Apr 2025 14:13:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1745356396; cv=none; d=google.com; s=arc-20240605; b=LS0PzVjfBs3x0tSEk841Vy+HDnUeQosrxEyMmbZDTQZpXpF+N+4UW/cZHtSgGKqkx7 ROAcvSv88xK5s34P9KVwrmolcy1QhSup77pCie59PPotXO7dQbjP5tMPiUaMFpX2BK7j ie7UIXnRYtiUWoQGzj0BhoNRz9IuoguSVjuY4bKPyfhsHitxirABr8/UA7PjqXQCm7pS P7Pmu8T3jC5+45uGX/ErjyhL0m5owMBhxqBG8WxzOQ0Dn7GkNX/EukIMuiUIKwVKesos Ox0o1M9tsvVjQOULehfpscFrGaMl6r9HJjb9wSYiAMLoaVxvHFFuLVX4TYBgn1/Fj4GD yC5g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=p5VV71JY8goeor4xQCwdYnut93y9ysd8cImiGLe4Oic=; fh=vm85eyWrvOAHduw3sqEA+cYBqvHB7M0MHFcRJg7VWOo=; b=FimGYWnED2eMtELTsD+UFK4Bxw903fnHnDSy5hIe0qxn7vNpu02cUGuowmot4C3C4i UccCoNV2LchknuV7Wj3ZITU/IWQVsbJb7fHBBbVzUchF0aF6VeqcFzftuEzPVoPkXkOQ KA0hvG5BRiMyNVC4loNiBalfDlTKNnqIlgMi2NIrTy3wHB8P/UvTiwkWDVVetjF6e9yf B71x/RdEdfDVR50kATlMAk8x4+wdllnP7tYBV6FpSB2oWJU13ABfwQwJfiK19bTFOPmj CcJB/kYUYtzV2L0jzOWbNPZ1iJLbeqxHEQG/bh/1aUomy+TJTtGTiUcxyxfJ92urFg8i zMSw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cdIMRHb0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73dbf8e4932sm9448160b3a.55.2025.04.22.14.11.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 14:11:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PULL 6/9] target/avr: Use cpu_stb_mmuidx_ra in helper_fullwr Date: Tue, 22 Apr 2025 14:11:21 -0700 Message-ID: <20250422211124.305724-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422211124.305724-1-richard.henderson@linaro.org> References: <20250422211124.305724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Avoid direct use of address_space_memory. Make use of the softmmu cache of the i/o page. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/avr/helper.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/target/avr/helper.c b/target/avr/helper.c index d0e86f5614..7d6954ec26 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -23,10 +23,10 @@ #include "qemu/error-report.h" #include "cpu.h" #include "accel/tcg/cpu-ops.h" +#include "accel/tcg/getpc.h" #include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/cpu_ldst.h" -#include "exec/address-spaces.h" #include "exec/helper-proto.h" bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request) @@ -67,6 +67,11 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request) return false; } +static void do_stb(CPUAVRState *env, uint32_t addr, uint8_t data, uintptr_t ra) +{ + cpu_stb_mmuidx_ra(env, addr, data, MMU_DATA_IDX, ra); +} + void avr_cpu_do_interrupt(CPUState *cs) { CPUAVRState *env = cpu_env(cs); @@ -311,8 +316,7 @@ void helper_fullwr(CPUAVRState *env, uint32_t data, uint32_t addr) break; default: - address_space_stb(&address_space_memory, OFFSET_DATA + addr, data, - MEMTXATTRS_UNSPECIFIED, NULL); + do_stb(env, addr, data, GETPC()); break; } } From patchwork Tue Apr 22 21:11:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 883158 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp2623452wrs; Tue, 22 Apr 2025 14:12:38 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCU8kBbCaQGoEG4eCkXakmOSjRh4LhSOBLGBQM7ac8+0gl9kUbsOJ9GKWI0LfYBfK8uKJYYvKg==@linaro.org X-Google-Smtp-Source: AGHT+IEQdjfFTMOgXOZ41Odbdt6uQnAOUt9C0t7PgxVnn8NU52+ztvnlqHzwanot+hH1BCjE1AO1 X-Received: by 2002:a05:6214:e6c:b0:6e8:f470:2b11 with SMTP id 6a1803df08f44-6f2c4577c1emr323093206d6.23.1745356358200; Tue, 22 Apr 2025 14:12:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1745356358; cv=none; d=google.com; s=arc-20240605; b=RLAU4SApfLtZ1hRaxfA2KTZU9sZ+NmUaQyo+HwL9JPMr6uagF/pQvqGC2i4aY7e85D FtFUFNTKf7M19Whbcfg8wUE87Owa5DJ4uF1JAFsSIMeTQyjo5Ce0JIdHn08AEQpCzNAQ CP6KFIzIk+WLRzZ2GS5G8UQnA0VALuuoZJCJ1WMJnaHG3f5lrwZAddR8BsZ02PdHY8h1 3+KLa4bp0zsyMJzvMe16vthcnLlmNjsNBgvOQFiNij5wmbi2L4RlBPrBHm+QkvIXohgm SKKQbUnA/IDt50hPfnqMC/BQgUs69JcSCenC5wIrR/OO1ZSoMN8Duggo8kNiON0cu0v4 qM5Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=DUF+4Y4/PqO50T2IhlnvWA6B/DIxYokH9Y5du5vjVAo=; fh=i/pWNGcx7KiR3ewgypxpPkuORYlkCnVXLqKVm9/UgNc=; b=GpuOvga7moHqTF6/SSX7hAaCsIf2Zv6Rxl4y8OnFoxZS0GOpbA/bg1Q2sUuRyR5K4h RJ2ybw0l4bbQWI54tP2yD39ALQvsCclh4KnNW1JGyxNw+KQWp68ZA+NGbV+9c0lhTKgr VLXOUzDibFLOReRC4EBqcptgJgX70hMCsGxt+dFOMaCwmVu72tMgTO7gzR9RRWREAhaN o9owLn1pFtCC6xfi+nA51diRIXaPubTkvmeneMyJhwy8VT9BQq595c9rjO/gdGF4Q6kK lxkkPfNTSlKii5dRZRBhjXwG5LQyznePStOwnVUhhBcChSTVTbM202QVR09+TSSZjVL/ a7mw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Kg19Xh/D"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73dbf8e4932sm9448160b3a.55.2025.04.22.14.11.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 14:11:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PULL 7/9] target/avr: Use do_stb in avr_cpu_do_interrupt Date: Tue, 22 Apr 2025 14:11:22 -0700 Message-ID: <20250422211124.305724-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422211124.305724-1-richard.henderson@linaro.org> References: <20250422211124.305724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/avr/helper.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/avr/helper.c b/target/avr/helper.c index 7d6954ec26..f23fa3e8ba 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -88,14 +88,14 @@ void avr_cpu_do_interrupt(CPUState *cs) } if (avr_feature(env, AVR_FEATURE_3_BYTE_PC)) { - cpu_stb_data(env, env->sp--, (ret & 0x0000ff)); - cpu_stb_data(env, env->sp--, (ret & 0x00ff00) >> 8); - cpu_stb_data(env, env->sp--, (ret & 0xff0000) >> 16); + do_stb(env, env->sp--, ret, 0); + do_stb(env, env->sp--, ret >> 8, 0); + do_stb(env, env->sp--, ret >> 16, 0); } else if (avr_feature(env, AVR_FEATURE_2_BYTE_PC)) { - cpu_stb_data(env, env->sp--, (ret & 0x0000ff)); - cpu_stb_data(env, env->sp--, (ret & 0x00ff00) >> 8); + do_stb(env, env->sp--, ret, 0); + do_stb(env, env->sp--, ret >> 8, 0); } else { - cpu_stb_data(env, env->sp--, (ret & 0x0000ff)); + do_stb(env, env->sp--, ret, 0); } env->pc_w = base + vector * size; From patchwork Tue Apr 22 21:11:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 883160 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp2623645wrs; Tue, 22 Apr 2025 14:13:07 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXWqeB7C5Nw29AFBY8hHT4MZah02crf4L+VSw7p5fH8rfSc/3cabYhgjL1qWhsqfwDpXH8s9Q==@linaro.org X-Google-Smtp-Source: AGHT+IHZkW5UHVTClLhuCgBbRgLbl/XUsSzne3v1YonTLZBJY4F63Qpu+OaLs31X/ylPKe0eeYZH X-Received: by 2002:ac8:5dcb:0:b0:476:a03b:96e1 with SMTP id d75a77b69052e-47aec4c681bmr305342341cf.52.1745356387445; Tue, 22 Apr 2025 14:13:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1745356387; cv=none; d=google.com; s=arc-20240605; b=NP+5EiEDN8P4A9X8XXqI2OkR3od6BjAeg9OSKQ5Vec9LlQKS3MnGv+2Le+B+FdVZQp yV7pc/yNI1LdRp2Uku9sziP4DAlukrhvZrWSxlb6rCnGu2HWfVXsFwoqwfKJTOtAcGwj M61kWNDAgSDs8mzg5UbfoVSatIUCJxnjZXNjdKF5fThEjJeh7ACoUzC9uFXVaUdyKi+N k/jjULZOSYLCaMSty3wpk7MRExFzpQwF2v8Zq8mlXy3UFo/4Jo47Dbs4U/Vxb+MV3ThV VtA1nYMur1y/qcSDq5QVkTM3NlEZiUrVa+vcoDiFOloEKMI6C4JaUyWCCLd40adq4BGg z/uA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=HNdVjawedf7L7sOM+y7tXhWt3e7lZuKafuAKLevf0NY=; fh=vm85eyWrvOAHduw3sqEA+cYBqvHB7M0MHFcRJg7VWOo=; b=hk5pvjk3rOsnBbVTfwB9BBvAnmAM74KQgvVUqQAPgfVNC8IOu/7v7xihvaO2JeX+kF naxZNWSeBPhdRjdoemx67bvEcaTaLfTcEnyDPfDYfUt4ZcIB4NmMDnEWAI0nLU2OjnZe axpHy0cca+og3ZXyoNhKTb2jeAuvkjUp3dcNb6FDDDu38pTZnbrNp2fqdijwp96xnHR7 o/9tKpbw2Ec7YZhjCvJGaV3ET6dDcqkmhGMFAobKn1bjNF6mb7bOjF50sHzcls8KngcN 18Tq/pqDzzuTgxX6SCVtGHA975OhFW/KyuCO5yKSg8cnCoPhHjo1ChFkcbSYUBmqv6Cu ZmMg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tVbcbr8i; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73dbf8e4932sm9448160b3a.55.2025.04.22.14.11.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 14:11:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PULL 8/9] hw/avr: Prepare for TARGET_PAGE_SIZE > 256 Date: Tue, 22 Apr 2025 14:11:23 -0700 Message-ID: <20250422211124.305724-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422211124.305724-1-richard.henderson@linaro.org> References: <20250422211124.305724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org If i/o does not cover the entire first page, allocate a portion of ram as an i/o device, so that the entire first page is i/o. While memory_region_init_ram_device_ptr is happy to allocate the RAMBlock, it does not register the ram for migration. Do this by hand. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- hw/avr/atmega.h | 1 + hw/avr/atmega.c | 39 ++++++++++++++++++++++++++++++++------- 2 files changed, 33 insertions(+), 7 deletions(-) diff --git a/hw/avr/atmega.h b/hw/avr/atmega.h index a99ee15c7e..9ac4678231 100644 --- a/hw/avr/atmega.h +++ b/hw/avr/atmega.h @@ -41,6 +41,7 @@ struct AtmegaMcuState { MemoryRegion flash; MemoryRegion eeprom; MemoryRegion sram; + MemoryRegion sram_io; DeviceState *io; AVRMaskState pwr[POWER_MAX]; AVRUsartState usart[USART_MAX]; diff --git a/hw/avr/atmega.c b/hw/avr/atmega.c index f6844bf118..11fab184de 100644 --- a/hw/avr/atmega.c +++ b/hw/avr/atmega.c @@ -19,6 +19,7 @@ #include "hw/sysbus.h" #include "qom/object.h" #include "hw/misc/unimp.h" +#include "migration/vmstate.h" #include "atmega.h" enum AtmegaPeripheral { @@ -224,8 +225,6 @@ static void atmega_realize(DeviceState *dev, Error **errp) char *devname; size_t i; - assert(mc->io_size <= 0x200); - if (!s->xtal_freq_hz) { error_setg(errp, "\"xtal-frequency-hz\" property must be provided."); return; @@ -240,11 +239,37 @@ static void atmega_realize(DeviceState *dev, Error **errp) qdev_realize(DEVICE(&s->cpu), NULL, &error_abort); cpudev = DEVICE(&s->cpu); - /* SRAM */ - memory_region_init_ram(&s->sram, OBJECT(dev), "sram", mc->sram_size, - &error_abort); - memory_region_add_subregion(get_system_memory(), - OFFSET_DATA + mc->io_size, &s->sram); + /* + * SRAM + * + * Softmmu is not able mix i/o and ram on the same page. + * Therefore in all cases, the first page exclusively contains i/o. + * + * If the MCU's i/o region matches the page size, then we can simply + * allocate all ram starting at the second page. Otherwise, we must + * allocate some ram as i/o to complete the first page. + */ + assert(mc->io_size == 0x100 || mc->io_size == 0x200); + if (mc->io_size >= TARGET_PAGE_SIZE) { + memory_region_init_ram(&s->sram, OBJECT(dev), "sram", mc->sram_size, + &error_abort); + memory_region_add_subregion(get_system_memory(), + OFFSET_DATA + mc->io_size, &s->sram); + } else { + int sram_io_size = TARGET_PAGE_SIZE - mc->io_size; + void *sram_io_mem = g_malloc0(sram_io_size); + + memory_region_init_ram_device_ptr(&s->sram_io, OBJECT(dev), "sram-as-io", + sram_io_size, sram_io_mem); + memory_region_add_subregion(get_system_memory(), + OFFSET_DATA + mc->io_size, &s->sram_io); + vmstate_register_ram(&s->sram_io, dev); + + memory_region_init_ram(&s->sram, OBJECT(dev), "sram", + mc->sram_size - sram_io_size, &error_abort); + memory_region_add_subregion(get_system_memory(), + OFFSET_DATA + TARGET_PAGE_SIZE, &s->sram); + } /* Flash */ memory_region_init_rom(&s->flash, OBJECT(dev), From patchwork Tue Apr 22 21:11:24 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 883154 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp2623152wrs; Tue, 22 Apr 2025 14:11:53 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWtrVNG0ch0N3h3Id7+MG7SN8mDZn9cliMbjz4EHtKSz9wJDXSt+TWlREBOcprnse8mSuFUZQ==@linaro.org X-Google-Smtp-Source: AGHT+IFpkkjE+6fpxJW9a1ZiXICINZYtW+4awL9w3Vg7+lK+w5LEDkFSvXnhPF0Z+mINb2JNTRfR X-Received: by 2002:a05:620a:4711:b0:7c5:49e8:993b with SMTP id af79cd13be357-7c92804d386mr3000275785a.56.1745356313620; Tue, 22 Apr 2025 14:11:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1745356313; cv=none; d=google.com; s=arc-20240605; b=G9XuKTUFCptYe23O/OVhxk+7+5wic8AwNJtvxcfu2YdqzH4spjoU3SqgKUd3K45R4W 5zlD8+/u86+u/eDRDSvUbfwjaIKs8vahx2sHeeEW3VVVQXLwMulUKbjTK6sZS1aynHFc 9zH4DyuBLWgdsfBu0pilL/G1heWefPwdMGJRsyC0/ic9CCVNDkOq2MC3C8umnez6KLZQ goC1vyinEekrlj/Bugcd9KyTyYZWh9Aut1+fslZqHp7x06ZOhWlWBSNMOka0QdTkn4G4 Zv0+bPSMvhBhAE7FxDezdAt/MXAZDS6KNNawWsR3zfzwFVnGbGTZgZHzkTcvB6Z4XJWq qD2Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=E4x0j7WHmS5PoiJFKXF/CXQYHRcuf16x9CbNw0mWO8Y=; fh=vm85eyWrvOAHduw3sqEA+cYBqvHB7M0MHFcRJg7VWOo=; b=UiMJXmqZzNRjH/JHobsrzfqE9bstyrxBz1M92J3VMoaJ/T4yv2sdsq/WxQr05P6drP vrN1oUxxMEgYD30LYvPQfSI+C/HZbwJEcemIkEcYJDu3Vcu6CQUp1zPWa4uO3/03u1cP kSs2En/i9fCqMAlkMaJcgObrQ0uEyAtNSS5iC+mP8jDMwBIjfsVJC6jqrMNDqkvdHgvk xeEiTDWCdqgbO0d9c85fRbRfWUM0MEg7A+Xk0iZkGCsSCqKKhdgOPUr0wHU1Il4T/Mo6 hKUFUR6oNqteMpxIp6WgdZiibZStZ28ijUe9IRLpC4Fezrredc5c3Qv1NT2j9nTzG6l0 j9XA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gfBJvrFJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73dbf8e4932sm9448160b3a.55.2025.04.22.14.11.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 14:11:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PULL 9/9] target/avr: Increase TARGET_PAGE_BITS to 10 Date: Tue, 22 Apr 2025 14:11:24 -0700 Message-ID: <20250422211124.305724-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422211124.305724-1-richard.henderson@linaro.org> References: <20250422211124.305724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Now that we can handle the MCU allocating only a portion of the first page to i/o, increase the page size. Choose 10 as larger than the i/o on every MCU, just so that this path is tested. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/avr/cpu-param.h | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h index 81f3f49ee1..f5248ce9e7 100644 --- a/target/avr/cpu-param.h +++ b/target/avr/cpu-param.h @@ -21,13 +21,7 @@ #ifndef AVR_CPU_PARAM_H #define AVR_CPU_PARAM_H -/* - * TARGET_PAGE_BITS cannot be more than 8 bits because - * 1. all IO registers occupy [0x0000 .. 0x00ff] address range, and they - * should be implemented as a device and not memory - * 2. SRAM starts at the address 0x0100 - */ -#define TARGET_PAGE_BITS 8 +#define TARGET_PAGE_BITS 10 #define TARGET_PHYS_ADDR_SPACE_BITS 24 #define TARGET_VIRT_ADDR_SPACE_BITS 24