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/* MSM8998 */ static const struct dpu_lm_sub_blks msm8998_lm_sblk = { - .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .maxblendstages = 7, /* excluding base layer */ .blendstage_base = { /* offsets relative to mixer base */ 0x20, 0x50, 0x80, 0xb0, 0x230, @@ -390,7 +389,6 @@ static const struct dpu_lm_sub_blks msm8998_lm_sblk = { /* SDM845 */ static const struct dpu_lm_sub_blks sdm845_lm_sblk = { - .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .maxblendstages = 11, /* excluding base layer */ .blendstage_base = { /* offsets relative to mixer base */ 0x20, 0x38, 0x50, 0x68, 0x80, 0x98, @@ -401,7 +399,6 @@ static const struct dpu_lm_sub_blks sdm845_lm_sblk = { /* SC7180 */ static const struct dpu_lm_sub_blks sc7180_lm_sblk = { - .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .maxblendstages = 7, /* excluding base layer */ .blendstage_base = { /* offsets relative to mixer base */ 0x20, 0x38, 0x50, 0x68, 0x80, 0x98, 0xb0 @@ -411,7 +408,6 @@ static const struct dpu_lm_sub_blks sc7180_lm_sblk = { /* QCM2290 */ static const struct dpu_lm_sub_blks qcm2290_lm_sblk = { - .maxwidth = DEFAULT_DPU_LINE_WIDTH, .maxblendstages = 4, /* excluding base layer */ .blendstage_base = { /* offsets relative to mixer base */ 0x20, 0x38, 0x50, 0x68 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 4cea19e1a203..5f1f3eae0f6f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -390,7 +390,6 @@ struct dpu_sspp_sub_blks { * @blendstage_base: Blend-stage register base offset */ struct dpu_lm_sub_blks { - u32 maxwidth; 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[199.106.103.254]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22fc8271aebsm104468735ad.107.2025.05.14.16.52.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 May 2025 16:52:43 -0700 (PDT) From: Jessica Zhang Date: Wed, 14 May 2025 16:52:30 -0700 Subject: [PATCH 2/5] drm/msm/dpu: Add max pingpong and dsc width to HW catalog Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250514-max-mixer-width-v1-2-c8ba0d9bb858@oss.qualcomm.com> References: <20250514-max-mixer-width-v1-0-c8ba0d9bb858@oss.qualcomm.com> In-Reply-To: <20250514-max-mixer-width-v1-0-c8ba0d9bb858@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Abhinav Kumar Cc: Abhinav Kumar , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jessica Zhang X-Mailer: b4 0.15-dev-64971 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747266760; l=49595; i=jessica.zhang@oss.qualcomm.com; s=20230329; h=from:subject:message-id; bh=nCSq6OlfZwTps329MQg7IWBHTHk/iD+YRAV1hNfF7T0=; b=r67/tiNCtWdcSsgEoIpDTfV8oLr8hNLocI6SMTLtSVwiLHOGmxrt4/8cb9YuiLfmI05ewMdMF 3ZuQ9wWGuSyAaqfjH/6A7/YrJRAE6AwOZ/tMvMogGhmrLx2aFHVNBTl X-Developer-Key: i=jessica.zhang@oss.qualcomm.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-Proofpoint-ORIG-GUID: K0_oHhZiiYZf5YaRFO14RK2kkoUWAn6Y X-Authority-Analysis: v=2.4 cv=D8dHKuRj c=1 sm=1 tr=0 ts=68252cce cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=EUspDBNiAAAA:8 a=iw1z9ScEdSCrm4yMxkEA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE0MDIyMiBTYWx0ZWRfX4cAkwAppIp3B 2gUt8Lu5iBS/d9TVNLQB3YSaht9hr5kx3ghTUIjMHk7oQG+USVFzSOCb6VMn4F3ASNuelbLKwea maYQyprVRBIy3C2IvMXnLbqnPo5YGw594tosPXiqHS5f98k7q37hAsGCJq83YRVP8u7+dl/Tdhs va/YONHFclaJvp2hfHowkXw5cxAre2CoHdeqDhn39/Mf1P0UExi3zegTF41BIucDsvuvg6dp/WX 6pD3kZ0aTizCKo+WI0Gu97LLeAul1L72w6stdB+s0X4Zs1qyFA3JzDACWFNtsHndg1/TjxKKSHW RUE8UAU6djnyEmyxoV8GC2REdH2ZXEjLejZgohnNo2cBNMQ1sXRdy2ctNRSs00MzwiE++EeBKY1 mYsguoKDsSaAl6cbs8c5kYrC/EI8IpNXn5U7CZjnRIlAmky9lB1nlShrRSlT14CXOkcc6oPx X-Proofpoint-GUID: K0_oHhZiiYZf5YaRFO14RK2kkoUWAn6Y X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-14_04,2025-05-14_03,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 spamscore=0 impostorscore=0 bulkscore=0 priorityscore=1501 suspectscore=0 malwarescore=0 mlxscore=0 adultscore=0 phishscore=0 clxscore=1015 lowpriorityscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505140222 Add max_dsc_encoder_width to dpu_caps struct and max_linewidth to dpu_pingpong_cfg for all chipsets within the HW catalog. Note: The max supported PINGPONG width was 4096 but increased to 5120 after DPU 6.x. In addition, DPU 8.x+ increases the max supported width of PINGPONG_0 specifically to 8960. Signed-off-by: Jessica Zhang --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 11 +++++++++++ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h | 2 ++ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h | 1 + drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h | 2 ++ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h | 4 ++++ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 4 ++++ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h | 4 ++++ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h | 2 ++ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 4 ++++ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 6 ++++++ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 6 ++++++ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h | 4 ++++ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 3 +++ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 2 ++ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 6 ++++++ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 2 ++ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 1 + drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 2 ++ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 1 + drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 1 + drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 7 +++++++ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 5 +++++ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 7 +++++++ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 9 +++++++++ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 9 +++++++++ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 9 +++++++++ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 9 +++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 10 ++++++++++ 28 files changed, 133 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h index 6ac97c378056..9db31591e27e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h @@ -9,6 +9,7 @@ static const struct dpu_caps sm8650_dpu_caps = { .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_dsc_encoder_width = DEFAULT_DSC_ENCODER_MAX_WIDTH, .max_mixer_blendstages = 0xb, .has_src_split = true, .has_dim_layer = true, @@ -214,6 +215,7 @@ static const struct dpu_pingpong_cfg sm8650_pp[] = { { .name = "pingpong_0", .id = PINGPONG_0, .base = 0x69000, .len = 0, + .max_linewidth = DPU_8_x_MAX_PINGPONG_0_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_0, @@ -221,6 +223,7 @@ static const struct dpu_pingpong_cfg sm8650_pp[] = { }, { .name = "pingpong_1", .id = PINGPONG_1, .base = 0x6a000, .len = 0, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_0, @@ -228,6 +231,7 @@ static const struct dpu_pingpong_cfg sm8650_pp[] = { }, { .name = "pingpong_2", .id = PINGPONG_2, .base = 0x6b000, .len = 0, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_1, @@ -235,6 +239,7 @@ static const struct dpu_pingpong_cfg sm8650_pp[] = { }, { .name = "pingpong_3", .id = PINGPONG_3, .base = 0x6c000, .len = 0, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_1, @@ -242,6 +247,7 @@ static const struct dpu_pingpong_cfg sm8650_pp[] = { }, { .name = "pingpong_4", .id = PINGPONG_4, .base = 0x6d000, .len = 0, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_2, @@ -249,6 +255,7 @@ static const struct dpu_pingpong_cfg sm8650_pp[] = { }, { .name = "pingpong_5", .id = PINGPONG_5, .base = 0x6e000, .len = 0, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_2, @@ -256,24 +263,28 @@ static const struct dpu_pingpong_cfg sm8650_pp[] = { }, { .name = "pingpong_cwb_0", .id = PINGPONG_CWB_0, .base = 0x66000, .len = 0, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_3, }, { .name = "pingpong_cwb_1", .id = PINGPONG_CWB_1, .base = 0x66400, .len = 0, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_3, }, { .name = "pingpong_cwb_2", .id = PINGPONG_CWB_2, .base = 0x7e000, .len = 0, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_4, }, { .name = "pingpong_cwb_3", .id = PINGPONG_CWB_3, .base = 0x7e400, .len = 0, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_4, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h index 1f32807bb5e5..4ac89cadf328 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h @@ -101,6 +101,7 @@ static const struct dpu_pingpong_cfg msm8937_pp[] = { .name = "pingpong_0", .id = PINGPONG_0, .base = 0x70000, .len = 0xd4, .features = PINGPONG_MSM8996_MASK, + .max_linewidth = DPU_1_x_MAX_PINGPONG_WIDTH, .sblk = &msm8996_pp_sblk, .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), @@ -108,6 +109,7 @@ static const struct dpu_pingpong_cfg msm8937_pp[] = { .name = "pingpong_1", .id = PINGPONG_1, .base = 0x70800, .len = 0xd4, .features = PINGPONG_MSM8996_MASK, + .max_linewidth = DPU_1_x_MAX_PINGPONG_WIDTH, .sblk = &msm8996_pp_sblk, .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h index 42131959ff22..dbd4129439a8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h @@ -94,6 +94,7 @@ static const struct dpu_pingpong_cfg msm8917_pp[] = { .name = "pingpong_0", .id = PINGPONG_0, .base = 0x70000, .len = 0xd4, .features = PINGPONG_MSM8996_MASK, + .max_linewidth = DPU_1_x_MAX_PINGPONG_WIDTH, .sblk = &msm8996_pp_sblk, .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h index 2b4723a5c676..a93976f6167c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h @@ -101,6 +101,7 @@ static const struct dpu_pingpong_cfg msm8953_pp[] = { .name = "pingpong_0", .id = PINGPONG_0, .base = 0x70000, .len = 0xd4, .features = PINGPONG_MSM8996_MASK, + .max_linewidth = DPU_1_x_MAX_PINGPONG_WIDTH, .sblk = &msm8996_pp_sblk, .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), @@ -108,6 +109,7 @@ static const struct dpu_pingpong_cfg msm8953_pp[] = { .name = "pingpong_1", .id = PINGPONG_1, .base = 0x70800, .len = 0xd4, .features = PINGPONG_MSM8996_MASK, + .max_linewidth = DPU_1_x_MAX_PINGPONG_WIDTH, .sblk = &msm8996_pp_sblk, .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h index 5cf19de71f06..e2e99504c715 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h @@ -181,6 +181,7 @@ static const struct dpu_pingpong_cfg msm8996_pp[] = { { .name = "pingpong_0", .id = PINGPONG_0, .base = 0x70000, .len = 0xd4, + .max_linewidth = DPU_1_x_MAX_PINGPONG_WIDTH, .features = PINGPONG_MSM8996_TE2_MASK, .sblk = &msm8996_pp_sblk_te, .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), @@ -188,6 +189,7 @@ static const struct dpu_pingpong_cfg msm8996_pp[] = { }, { .name = "pingpong_1", .id = PINGPONG_1, .base = 0x70800, .len = 0xd4, + .max_linewidth = DPU_1_x_MAX_PINGPONG_WIDTH, .features = PINGPONG_MSM8996_TE2_MASK, .sblk = &msm8996_pp_sblk_te, .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), @@ -195,6 +197,7 @@ static const struct dpu_pingpong_cfg msm8996_pp[] = { }, { .name = "pingpong_2", .id = PINGPONG_2, .base = 0x71000, .len = 0xd4, + .max_linewidth = DPU_1_x_MAX_PINGPONG_WIDTH, .features = PINGPONG_MSM8996_MASK, .sblk = &msm8996_pp_sblk, .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), @@ -202,6 +205,7 @@ static const struct dpu_pingpong_cfg msm8996_pp[] = { }, { .name = "pingpong_3", .id = PINGPONG_3, .base = 0x71800, .len = 0xd4, + .max_linewidth = DPU_1_x_MAX_PINGPONG_WIDTH, .features = PINGPONG_MSM8996_MASK, .sblk = &msm8996_pp_sblk, .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h index 746474679ef5..1bdffe168fb1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h @@ -170,6 +170,7 @@ static const struct dpu_pingpong_cfg msm8998_pp[] = { { .name = "pingpong_0", .id = PINGPONG_0, .base = 0x70000, .len = 0xd4, + .max_linewidth = DPU_1_x_MAX_PINGPONG_WIDTH, .features = PINGPONG_SDM845_TE2_MASK, .sblk = &sdm845_pp_sblk_te, .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), @@ -177,6 +178,7 @@ static const struct dpu_pingpong_cfg msm8998_pp[] = { }, { .name = "pingpong_1", .id = PINGPONG_1, .base = 0x70800, .len = 0xd4, + .max_linewidth = DPU_1_x_MAX_PINGPONG_WIDTH, .features = PINGPONG_SDM845_TE2_MASK, .sblk = &sdm845_pp_sblk_te, .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), @@ -184,6 +186,7 @@ static const struct dpu_pingpong_cfg msm8998_pp[] = { }, { .name = "pingpong_2", .id = PINGPONG_2, .base = 0x71000, .len = 0xd4, + .max_linewidth = DPU_1_x_MAX_PINGPONG_WIDTH, .features = PINGPONG_SDM845_MASK, .sblk = &sdm845_pp_sblk, .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), @@ -191,6 +194,7 @@ static const struct dpu_pingpong_cfg msm8998_pp[] = { }, { .name = "pingpong_3", .id = PINGPONG_3, .base = 0x71800, .len = 0xd4, + .max_linewidth = DPU_1_x_MAX_PINGPONG_WIDTH, .features = PINGPONG_SDM845_MASK, .sblk = &sdm845_pp_sblk, .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h index 4f2f68b07f20..03f46a652449 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h @@ -141,6 +141,7 @@ static const struct dpu_pingpong_cfg sdm660_pp[] = { { .name = "pingpong_0", .id = PINGPONG_0, .base = 0x70000, .len = 0xd4, + .max_linewidth = DPU_1_x_MAX_PINGPONG_WIDTH, .features = PINGPONG_SDM845_TE2_MASK, .sblk = &sdm845_pp_sblk_te, .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), @@ -148,6 +149,7 @@ static const struct dpu_pingpong_cfg sdm660_pp[] = { }, { .name = "pingpong_1", .id = PINGPONG_1, .base = 0x70800, .len = 0xd4, + .max_linewidth = DPU_1_x_MAX_PINGPONG_WIDTH, .features = PINGPONG_SDM845_TE2_MASK, .sblk = &sdm845_pp_sblk_te, .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), @@ -155,6 +157,7 @@ static const struct dpu_pingpong_cfg sdm660_pp[] = { }, { .name = "pingpong_2", .id = PINGPONG_2, .base = 0x71000, .len = 0xd4, + .max_linewidth = DPU_1_x_MAX_PINGPONG_WIDTH, .features = PINGPONG_SDM845_MASK, .sblk = &sdm845_pp_sblk, .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), @@ -162,6 +165,7 @@ static const struct dpu_pingpong_cfg sdm660_pp[] = { }, { .name = "pingpong_3", .id = PINGPONG_3, .base = 0x71800, .len = 0xd4, + .max_linewidth = DPU_1_x_MAX_PINGPONG_WIDTH, .features = PINGPONG_SDM845_MASK, .sblk = &sdm845_pp_sblk, .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h index c70bef025ac4..011e98e6e7db 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h @@ -115,6 +115,7 @@ static const struct dpu_pingpong_cfg sdm630_pp[] = { { .name = "pingpong_0", .id = PINGPONG_0, .base = 0x70000, .len = 0xd4, + .max_linewidth = DPU_1_x_MAX_PINGPONG_WIDTH, .features = PINGPONG_SDM845_TE2_MASK, .sblk = &sdm845_pp_sblk_te, .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), @@ -122,6 +123,7 @@ static const struct dpu_pingpong_cfg sdm630_pp[] = { }, { .name = "pingpong_2", .id = PINGPONG_2, .base = 0x71000, .len = 0xd4, + .max_linewidth = DPU_1_x_MAX_PINGPONG_WIDTH, .features = PINGPONG_SDM845_MASK, .sblk = &sdm845_pp_sblk, .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h index ab7b4822ca63..152fa5ea12dd 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h @@ -194,6 +194,7 @@ static const struct dpu_pingpong_cfg sdm845_pp[] = { { .name = "pingpong_0", .id = PINGPONG_0, .base = 0x70000, .len = 0xd4, + .max_linewidth = DPU_1_x_MAX_PINGPONG_WIDTH, .features = PINGPONG_SDM845_TE2_MASK, .sblk = &sdm845_pp_sblk_te, .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), @@ -201,6 +202,7 @@ static const struct dpu_pingpong_cfg sdm845_pp[] = { }, { .name = "pingpong_1", .id = PINGPONG_1, .base = 0x70800, .len = 0xd4, + .max_linewidth = DPU_1_x_MAX_PINGPONG_WIDTH, .features = PINGPONG_SDM845_TE2_MASK, .sblk = &sdm845_pp_sblk_te, .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), @@ -208,6 +210,7 @@ static const struct dpu_pingpong_cfg sdm845_pp[] = { }, { .name = "pingpong_2", .id = PINGPONG_2, .base = 0x71000, .len = 0xd4, + .max_linewidth = DPU_1_x_MAX_PINGPONG_WIDTH, .features = PINGPONG_SDM845_MASK, .sblk = &sdm845_pp_sblk, .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), @@ -215,6 +218,7 @@ static const struct dpu_pingpong_cfg sdm845_pp[] = { }, { .name = "pingpong_3", .id = PINGPONG_3, .base = 0x71800, .len = 0xd4, + .max_linewidth = DPU_1_x_MAX_PINGPONG_WIDTH, .features = PINGPONG_SDM845_MASK, .sblk = &sdm845_pp_sblk, .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h index 979527d98fbc..7f0754e47c2e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h @@ -218,6 +218,7 @@ static const struct dpu_pingpong_cfg sm8150_pp[] = { { .name = "pingpong_0", .id = PINGPONG_0, .base = 0x70000, .len = 0xd4, + .max_linewidth = DPU_1_x_MAX_PINGPONG_WIDTH, .features = PINGPONG_SM8150_MASK, .sblk = &sdm845_pp_sblk, .merge_3d = MERGE_3D_0, @@ -225,6 +226,7 @@ static const struct dpu_pingpong_cfg sm8150_pp[] = { }, { .name = "pingpong_1", .id = PINGPONG_1, .base = 0x70800, .len = 0xd4, + .max_linewidth = DPU_1_x_MAX_PINGPONG_WIDTH, .features = PINGPONG_SM8150_MASK, .sblk = &sdm845_pp_sblk, .merge_3d = MERGE_3D_0, @@ -232,6 +234,7 @@ static const struct dpu_pingpong_cfg sm8150_pp[] = { }, { .name = "pingpong_2", .id = PINGPONG_2, .base = 0x71000, .len = 0xd4, + .max_linewidth = DPU_1_x_MAX_PINGPONG_WIDTH, .features = PINGPONG_SM8150_MASK, .sblk = &sdm845_pp_sblk, .merge_3d = MERGE_3D_1, @@ -239,6 +242,7 @@ static const struct dpu_pingpong_cfg sm8150_pp[] = { }, { .name = "pingpong_3", .id = PINGPONG_3, .base = 0x71800, .len = 0xd4, + .max_linewidth = DPU_1_x_MAX_PINGPONG_WIDTH, .features = PINGPONG_SM8150_MASK, .sblk = &sdm845_pp_sblk, .merge_3d = MERGE_3D_1, @@ -246,6 +250,7 @@ static const struct dpu_pingpong_cfg sm8150_pp[] = { }, { .name = "pingpong_4", .id = PINGPONG_4, .base = 0x72000, .len = 0xd4, + .max_linewidth = DPU_1_x_MAX_PINGPONG_WIDTH, .features = PINGPONG_SM8150_MASK, .sblk = &sdm845_pp_sblk, .merge_3d = MERGE_3D_2, @@ -253,6 +258,7 @@ static const struct dpu_pingpong_cfg sm8150_pp[] = { }, { .name = "pingpong_5", .id = PINGPONG_5, .base = 0x72800, .len = 0xd4, + .max_linewidth = DPU_1_x_MAX_PINGPONG_WIDTH, .features = PINGPONG_SM8150_MASK, .sblk = &sdm845_pp_sblk, .merge_3d = MERGE_3D_2, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h index d76b8992a6c1..1a904b68950a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h @@ -217,6 +217,7 @@ static const struct dpu_pingpong_cfg sc8180x_pp[] = { { .name = "pingpong_0", .id = PINGPONG_0, .base = 0x70000, .len = 0xd4, + .max_linewidth = DPU_1_x_MAX_PINGPONG_WIDTH, .features = PINGPONG_SM8150_MASK, .sblk = &sdm845_pp_sblk, .merge_3d = MERGE_3D_0, @@ -224,6 +225,7 @@ static const struct dpu_pingpong_cfg sc8180x_pp[] = { }, { .name = "pingpong_1", .id = PINGPONG_1, .base = 0x70800, .len = 0xd4, + .max_linewidth = DPU_1_x_MAX_PINGPONG_WIDTH, .features = PINGPONG_SM8150_MASK, .sblk = &sdm845_pp_sblk, .merge_3d = MERGE_3D_0, @@ -231,6 +233,7 @@ static const struct dpu_pingpong_cfg sc8180x_pp[] = { }, { .name = "pingpong_2", .id = PINGPONG_2, .base = 0x71000, .len = 0xd4, + .max_linewidth = DPU_1_x_MAX_PINGPONG_WIDTH, .features = PINGPONG_SM8150_MASK, .sblk = &sdm845_pp_sblk, .merge_3d = MERGE_3D_1, @@ -238,6 +241,7 @@ static const struct dpu_pingpong_cfg sc8180x_pp[] = { }, { .name = "pingpong_3", .id = PINGPONG_3, .base = 0x71800, .len = 0xd4, + .max_linewidth = DPU_1_x_MAX_PINGPONG_WIDTH, .features = PINGPONG_SM8150_MASK, .sblk = &sdm845_pp_sblk, .merge_3d = MERGE_3D_1, @@ -245,6 +249,7 @@ static const struct dpu_pingpong_cfg sc8180x_pp[] = { }, { .name = "pingpong_4", .id = PINGPONG_4, .base = 0x72000, .len = 0xd4, + .max_linewidth = DPU_1_x_MAX_PINGPONG_WIDTH, .features = PINGPONG_SM8150_MASK, .sblk = &sdm845_pp_sblk, .merge_3d = MERGE_3D_2, @@ -252,6 +257,7 @@ static const struct dpu_pingpong_cfg sc8180x_pp[] = { }, { .name = "pingpong_5", .id = PINGPONG_5, .base = 0x72800, .len = 0xd4, + .max_linewidth = DPU_1_x_MAX_PINGPONG_WIDTH, .features = PINGPONG_SM8150_MASK, .sblk = &sdm845_pp_sblk, .merge_3d = MERGE_3D_2, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h index 83db11339b29..7c65f77a2c43 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h @@ -164,6 +164,7 @@ static const struct dpu_pingpong_cfg sm7150_pp[] = { { .name = "pingpong_0", .id = PINGPONG_0, .base = 0x70000, .len = 0xd4, + .max_linewidth = DPU_1_x_MAX_PINGPONG_WIDTH, .features = PINGPONG_SM8150_MASK, .sblk = &sdm845_pp_sblk, .merge_3d = MERGE_3D_0, @@ -171,6 +172,7 @@ static const struct dpu_pingpong_cfg sm7150_pp[] = { }, { .name = "pingpong_1", .id = PINGPONG_1, .base = 0x70800, .len = 0xd4, + .max_linewidth = DPU_1_x_MAX_PINGPONG_WIDTH, .features = PINGPONG_SM8150_MASK, .sblk = &sdm845_pp_sblk, .merge_3d = MERGE_3D_0, @@ -178,6 +180,7 @@ static const struct dpu_pingpong_cfg sm7150_pp[] = { }, { .name = "pingpong_2", .id = PINGPONG_2, .base = 0x71000, .len = 0xd4, + .max_linewidth = DPU_1_x_MAX_PINGPONG_WIDTH, .features = PINGPONG_SM8150_MASK, .sblk = &sdm845_pp_sblk, .merge_3d = MERGE_3D_1, @@ -185,6 +188,7 @@ static const struct dpu_pingpong_cfg sm7150_pp[] = { }, { .name = "pingpong_3", .id = PINGPONG_3, .base = 0x71800, .len = 0xd4, + .max_linewidth = DPU_1_x_MAX_PINGPONG_WIDTH, .features = PINGPONG_SM8150_MASK, .sblk = &sdm845_pp_sblk, .merge_3d = MERGE_3D_1, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h index da11830d4407..f0539dd11dc8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h @@ -145,18 +145,21 @@ static const struct dpu_pingpong_cfg sm6150_pp[] = { { .name = "pingpong_0", .id = PINGPONG_0, .base = 0x70000, .len = 0xd4, + .max_linewidth = DPU_1_x_MAX_PINGPONG_WIDTH, .features = PINGPONG_SM8150_MASK, .sblk = &sdm845_pp_sblk, .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), }, { .name = "pingpong_1", .id = PINGPONG_1, .base = 0x70800, .len = 0xd4, + .max_linewidth = DPU_1_x_MAX_PINGPONG_WIDTH, .features = PINGPONG_SM8150_MASK, .sblk = &sdm845_pp_sblk, .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), }, { .name = "pingpong_2", .id = PINGPONG_2, .base = 0x71000, .len = 0xd4, + .max_linewidth = DPU_1_x_MAX_PINGPONG_WIDTH, .features = PINGPONG_SM8150_MASK, .sblk = &sdm845_pp_sblk, .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h index d3d3a34d0b45..a357567ad597 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h @@ -126,6 +126,7 @@ static const struct dpu_pingpong_cfg sm6125_pp[] = { { .name = "pingpong_0", .id = PINGPONG_0, .base = 0x70000, .len = 0xd4, + .max_linewidth = DPU_1_x_MAX_PINGPONG_WIDTH, .features = PINGPONG_SM8150_MASK, .merge_3d = 0, .sblk = &sdm845_pp_sblk, @@ -133,6 +134,7 @@ static const struct dpu_pingpong_cfg sm6125_pp[] = { }, { .name = "pingpong_1", .id = PINGPONG_1, .base = 0x70800, .len = 0xd4, + .max_linewidth = DPU_1_x_MAX_PINGPONG_WIDTH, .features = PINGPONG_SM8150_MASK, .merge_3d = 0, .sblk = &sdm845_pp_sblk, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h index 47e01c3c242f..c0bf1eba1eab 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h @@ -216,6 +216,7 @@ static const struct dpu_pingpong_cfg sm8250_pp[] = { { .name = "pingpong_0", .id = PINGPONG_0, .base = 0x70000, .len = 0xd4, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = PINGPONG_SM8150_MASK, .sblk = &sdm845_pp_sblk, .merge_3d = MERGE_3D_0, @@ -223,6 +224,7 @@ static const struct dpu_pingpong_cfg sm8250_pp[] = { }, { .name = "pingpong_1", .id = PINGPONG_1, .base = 0x70800, .len = 0xd4, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = PINGPONG_SM8150_MASK, .sblk = &sdm845_pp_sblk, .merge_3d = MERGE_3D_0, @@ -230,6 +232,7 @@ static const struct dpu_pingpong_cfg sm8250_pp[] = { }, { .name = "pingpong_2", .id = PINGPONG_2, .base = 0x71000, .len = 0xd4, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = PINGPONG_SM8150_MASK, .sblk = &sdm845_pp_sblk, .merge_3d = MERGE_3D_1, @@ -237,6 +240,7 @@ static const struct dpu_pingpong_cfg sm8250_pp[] = { }, { .name = "pingpong_3", .id = PINGPONG_3, .base = 0x71800, .len = 0xd4, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = PINGPONG_SM8150_MASK, .sblk = &sdm845_pp_sblk, .merge_3d = MERGE_3D_1, @@ -244,6 +248,7 @@ static const struct dpu_pingpong_cfg sm8250_pp[] = { }, { .name = "pingpong_4", .id = PINGPONG_4, .base = 0x72000, .len = 0xd4, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = PINGPONG_SM8150_MASK, .sblk = &sdm845_pp_sblk, .merge_3d = MERGE_3D_2, @@ -251,6 +256,7 @@ static const struct dpu_pingpong_cfg sm8250_pp[] = { }, { .name = "pingpong_5", .id = PINGPONG_5, .base = 0x72800, .len = 0xd4, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = PINGPONG_SM8150_MASK, .sblk = &sdm845_pp_sblk, .merge_3d = MERGE_3D_2, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h index 040c94c0bb66..d004e7ee71fb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h @@ -115,6 +115,7 @@ static const struct dpu_pingpong_cfg sc7180_pp[] = { { .name = "pingpong_0", .id = PINGPONG_0, .base = 0x70000, .len = 0xd4, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = PINGPONG_SM8150_MASK, .sblk = &sdm845_pp_sblk, .merge_3d = 0, @@ -122,6 +123,7 @@ static const struct dpu_pingpong_cfg sc7180_pp[] = { }, { .name = "pingpong_1", .id = PINGPONG_1, .base = 0x70800, .len = 0xd4, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = PINGPONG_SM8150_MASK, .sblk = &sdm845_pp_sblk, .merge_3d = 0, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h index 43f64a005f5a..b0659b55542f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h @@ -78,6 +78,7 @@ static const struct dpu_pingpong_cfg sm6115_pp[] = { { .name = "pingpong_0", .id = PINGPONG_0, .base = 0x70000, .len = 0xd4, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = PINGPONG_SM8150_MASK, .sblk = &sdm845_pp_sblk, .merge_3d = 0, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h index 397278ba999b..ae0196372f35 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h @@ -124,6 +124,7 @@ static struct dpu_pingpong_cfg sm6350_pp[] = { { .name = "pingpong_0", .id = PINGPONG_0, .base = 0x70000, .len = 0xd4, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = PINGPONG_SM8150_MASK, .sblk = &sdm845_pp_sblk, .merge_3d = 0, @@ -131,6 +132,7 @@ static struct dpu_pingpong_cfg sm6350_pp[] = { }, { .name = "pingpong_1", .id = PINGPONG_1, .base = 0x70800, .len = 0xd4, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = PINGPONG_SM8150_MASK, .sblk = &sdm845_pp_sblk, .merge_3d = 0, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h index 3cbb2fe8aba2..d9bb18f11a49 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h @@ -78,6 +78,7 @@ static const struct dpu_pingpong_cfg qcm2290_pp[] = { { .name = "pingpong_0", .id = PINGPONG_0, .base = 0x70000, .len = 0xd4, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = PINGPONG_SM8150_MASK, .sblk = &sdm845_pp_sblk, .merge_3d = 0, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h index a06c8634d2d7..8893b39e2ca3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h @@ -80,6 +80,7 @@ static const struct dpu_pingpong_cfg sm6375_pp[] = { { .name = "pingpong_0", .id = PINGPONG_0, .base = 0x70000, .len = 0xd4, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = PINGPONG_SM8150_MASK, .sblk = &sdm845_pp_sblk, .merge_3d = 0, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h index 0c860e804cab..6ded8b0309d9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h @@ -9,6 +9,7 @@ static const struct dpu_caps sm8350_dpu_caps = { .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_dsc_encoder_width = DEFAULT_DSC_ENCODER_MAX_WIDTH, .max_mixer_blendstages = 0xb, .has_src_split = true, .has_dim_layer = true, @@ -216,6 +217,7 @@ static const struct dpu_pingpong_cfg sm8350_pp[] = { { .name = "pingpong_0", .id = PINGPONG_0, .base = 0x69000, .len = 0, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_0, @@ -223,6 +225,7 @@ static const struct dpu_pingpong_cfg sm8350_pp[] = { }, { .name = "pingpong_1", .id = PINGPONG_1, .base = 0x6a000, .len = 0, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_0, @@ -230,6 +233,7 @@ static const struct dpu_pingpong_cfg sm8350_pp[] = { }, { .name = "pingpong_2", .id = PINGPONG_2, .base = 0x6b000, .len = 0, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_1, @@ -237,6 +241,7 @@ static const struct dpu_pingpong_cfg sm8350_pp[] = { }, { .name = "pingpong_3", .id = PINGPONG_3, .base = 0x6c000, .len = 0, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_1, @@ -244,6 +249,7 @@ static const struct dpu_pingpong_cfg sm8350_pp[] = { }, { .name = "pingpong_4", .id = PINGPONG_4, .base = 0x6d000, .len = 0, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_2, @@ -251,6 +257,7 @@ static const struct dpu_pingpong_cfg sm8350_pp[] = { }, { .name = "pingpong_5", .id = PINGPONG_5, .base = 0x6e000, .len = 0, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_2, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h index e9625c48c567..e1512ff5945c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h @@ -9,6 +9,7 @@ static const struct dpu_caps sc7280_dpu_caps = { .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_dsc_encoder_width = DEFAULT_DSC_ENCODER_MAX_WIDTH, .max_mixer_blendstages = 0x7, .has_dim_layer = true, .has_idle_pc = true, @@ -126,6 +127,7 @@ static const struct dpu_pingpong_cfg sc7280_pp[] = { { .name = "pingpong_0", .id = PINGPONG_0, .base = 0x69000, .len = 0, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = 0, @@ -133,6 +135,7 @@ static const struct dpu_pingpong_cfg sc7280_pp[] = { }, { .name = "pingpong_1", .id = PINGPONG_1, .base = 0x6a000, .len = 0, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = 0, @@ -140,6 +143,7 @@ static const struct dpu_pingpong_cfg sc7280_pp[] = { }, { .name = "pingpong_2", .id = PINGPONG_2, .base = 0x6b000, .len = 0, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = 0, @@ -147,6 +151,7 @@ static const struct dpu_pingpong_cfg sc7280_pp[] = { }, { .name = "pingpong_3", .id = PINGPONG_3, .base = 0x6c000, .len = 0, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = 0, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h index fcee1c3665f8..2a084ee071b9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -9,6 +9,7 @@ static const struct dpu_caps sc8280xp_dpu_caps = { .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_dsc_encoder_width = DEFAULT_DSC_ENCODER_MAX_WIDTH, .max_mixer_blendstages = 11, .has_src_split = true, .has_dim_layer = true, @@ -216,6 +217,7 @@ static const struct dpu_pingpong_cfg sc8280xp_pp[] = { { .name = "pingpong_0", .id = PINGPONG_0, .base = 0x69000, .len = 0, + .max_linewidth = DPU_8_x_MAX_PINGPONG_0_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_0, @@ -223,6 +225,7 @@ static const struct dpu_pingpong_cfg sc8280xp_pp[] = { }, { .name = "pingpong_1", .id = PINGPONG_1, .base = 0x6a000, .len = 0, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_0, @@ -230,6 +233,7 @@ static const struct dpu_pingpong_cfg sc8280xp_pp[] = { }, { .name = "pingpong_2", .id = PINGPONG_2, .base = 0x6b000, .len = 0, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_1, @@ -237,6 +241,7 @@ static const struct dpu_pingpong_cfg sc8280xp_pp[] = { }, { .name = "pingpong_3", .id = PINGPONG_3, .base = 0x6c000, .len = 0, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_1, @@ -244,6 +249,7 @@ static const struct dpu_pingpong_cfg sc8280xp_pp[] = { }, { .name = "pingpong_4", .id = PINGPONG_4, .base = 0x6d000, .len = 0, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_2, @@ -251,6 +257,7 @@ static const struct dpu_pingpong_cfg sc8280xp_pp[] = { }, { .name = "pingpong_5", .id = PINGPONG_5, .base = 0x6e000, .len = 0, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_2, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h index 19b2ee8bbd5f..2cb3966ee51f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -9,6 +9,7 @@ static const struct dpu_caps sm8450_dpu_caps = { .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_dsc_encoder_width = DEFAULT_DSC_ENCODER_MAX_WIDTH, .max_mixer_blendstages = 0xb, .has_src_split = true, .has_dim_layer = true, @@ -217,6 +218,7 @@ static const struct dpu_pingpong_cfg sm8450_pp[] = { { .name = "pingpong_0", .id = PINGPONG_0, .base = 0x69000, .len = 0, + .max_linewidth = DPU_8_x_MAX_PINGPONG_0_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_0, @@ -224,6 +226,7 @@ static const struct dpu_pingpong_cfg sm8450_pp[] = { }, { .name = "pingpong_1", .id = PINGPONG_1, .base = 0x6a000, .len = 0, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_0, @@ -231,6 +234,7 @@ static const struct dpu_pingpong_cfg sm8450_pp[] = { }, { .name = "pingpong_2", .id = PINGPONG_2, .base = 0x6b000, .len = 0, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_1, @@ -238,6 +242,7 @@ static const struct dpu_pingpong_cfg sm8450_pp[] = { }, { .name = "pingpong_3", .id = PINGPONG_3, .base = 0x6c000, .len = 0, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_1, @@ -245,6 +250,7 @@ static const struct dpu_pingpong_cfg sm8450_pp[] = { }, { .name = "pingpong_4", .id = PINGPONG_4, .base = 0x6d000, .len = 0, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_2, @@ -252,6 +258,7 @@ static const struct dpu_pingpong_cfg sm8450_pp[] = { }, { .name = "pingpong_5", .id = PINGPONG_5, .base = 0x6e000, .len = 0, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_2, @@ -259,12 +266,14 @@ static const struct dpu_pingpong_cfg sm8450_pp[] = { }, { .name = "pingpong_cwb_0", .id = PINGPONG_CWB_0, .base = 0x65800, .len = 0, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_3, }, { .name = "pingpong_cwb_1", .id = PINGPONG_CWB_1, .base = 0x65c00, .len = 0, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_3, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h index 4d96ce71746f..1135918e0a86 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h @@ -8,6 +8,7 @@ static const struct dpu_caps sa8775p_dpu_caps = { .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_dsc_encoder_width = DEFAULT_DSC_ENCODER_MAX_WIDTH, .max_mixer_blendstages = 0xb, .has_src_split = true, .has_dim_layer = true, @@ -216,6 +217,7 @@ static const struct dpu_pingpong_cfg sa8775p_pp[] = { { .name = "pingpong_0", .id = PINGPONG_0, .base = 0x69000, .len = 0, + .max_linewidth = DPU_8_x_MAX_PINGPONG_0_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_0, @@ -223,6 +225,7 @@ static const struct dpu_pingpong_cfg sa8775p_pp[] = { }, { .name = "pingpong_1", .id = PINGPONG_1, .base = 0x6a000, .len = 0, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_0, @@ -230,6 +233,7 @@ static const struct dpu_pingpong_cfg sa8775p_pp[] = { }, { .name = "pingpong_2", .id = PINGPONG_2, .base = 0x6b000, .len = 0, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_1, @@ -237,6 +241,7 @@ static const struct dpu_pingpong_cfg sa8775p_pp[] = { }, { .name = "pingpong_3", .id = PINGPONG_3, .base = 0x6c000, .len = 0, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_1, @@ -244,6 +249,7 @@ static const struct dpu_pingpong_cfg sa8775p_pp[] = { }, { .name = "pingpong_4", .id = PINGPONG_4, .base = 0x6d000, .len = 0, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_2, @@ -251,6 +257,7 @@ static const struct dpu_pingpong_cfg sa8775p_pp[] = { }, { .name = "pingpong_5", .id = PINGPONG_5, .base = 0x6e000, .len = 0, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_2, @@ -258,12 +265,14 @@ static const struct dpu_pingpong_cfg sa8775p_pp[] = { }, { .name = "pingpong_6", .id = PINGPONG_CWB_0, .base = 0x65800, .len = 0, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_3, }, { .name = "pingpong_7", .id = PINGPONG_CWB_1, .base = 0x65c00, .len = 0, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_3, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index 24f988465bf6..0516e75a3a16 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -9,6 +9,7 @@ static const struct dpu_caps sm8550_dpu_caps = { .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_dsc_encoder_width = DEFAULT_DSC_ENCODER_MAX_WIDTH, .max_mixer_blendstages = 0xb, .has_src_split = true, .has_dim_layer = true, @@ -213,6 +214,7 @@ static const struct dpu_pingpong_cfg sm8550_pp[] = { { .name = "pingpong_0", .id = PINGPONG_0, .base = 0x69000, .len = 0, + .max_linewidth = DPU_8_x_MAX_PINGPONG_0_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_0, @@ -220,6 +222,7 @@ static const struct dpu_pingpong_cfg sm8550_pp[] = { }, { .name = "pingpong_1", .id = PINGPONG_1, .base = 0x6a000, .len = 0, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_0, @@ -227,6 +230,7 @@ static const struct dpu_pingpong_cfg sm8550_pp[] = { }, { .name = "pingpong_2", .id = PINGPONG_2, .base = 0x6b000, .len = 0, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_1, @@ -234,6 +238,7 @@ static const struct dpu_pingpong_cfg sm8550_pp[] = { }, { .name = "pingpong_3", .id = PINGPONG_3, .base = 0x6c000, .len = 0, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_1, @@ -241,6 +246,7 @@ static const struct dpu_pingpong_cfg sm8550_pp[] = { }, { .name = "pingpong_4", .id = PINGPONG_4, .base = 0x6d000, .len = 0, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_2, @@ -248,6 +254,7 @@ static const struct dpu_pingpong_cfg sm8550_pp[] = { }, { .name = "pingpong_5", .id = PINGPONG_5, .base = 0x6e000, .len = 0, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_2, @@ -255,12 +262,14 @@ static const struct dpu_pingpong_cfg sm8550_pp[] = { }, { .name = "pingpong_cwb_0", .id = PINGPONG_CWB_0, .base = 0x66000, .len = 0, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_3, }, { .name = "pingpong_cwb_1", .id = PINGPONG_CWB_1, .base = 0x66400, .len = 0, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_3, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h index 6417baa84f82..23d044e10c75 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h @@ -8,6 +8,7 @@ static const struct dpu_caps x1e80100_dpu_caps = { .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_dsc_encoder_width = DEFAULT_DSC_ENCODER_MAX_WIDTH, .max_mixer_blendstages = 0xb, .has_src_split = true, .has_dim_layer = true, @@ -213,6 +214,7 @@ static const struct dpu_pingpong_cfg x1e80100_pp[] = { { .name = "pingpong_0", .id = PINGPONG_0, .base = 0x69000, .len = 0, + .max_linewidth = DPU_8_x_MAX_PINGPONG_0_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_0, @@ -220,6 +222,7 @@ static const struct dpu_pingpong_cfg x1e80100_pp[] = { }, { .name = "pingpong_1", .id = PINGPONG_1, .base = 0x6a000, .len = 0, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_0, @@ -227,6 +230,7 @@ static const struct dpu_pingpong_cfg x1e80100_pp[] = { }, { .name = "pingpong_2", .id = PINGPONG_2, .base = 0x6b000, .len = 0, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_1, @@ -234,6 +238,7 @@ static const struct dpu_pingpong_cfg x1e80100_pp[] = { }, { .name = "pingpong_3", .id = PINGPONG_3, .base = 0x6c000, .len = 0, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_1, @@ -241,6 +246,7 @@ static const struct dpu_pingpong_cfg x1e80100_pp[] = { }, { .name = "pingpong_4", .id = PINGPONG_4, .base = 0x6d000, .len = 0, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_2, @@ -248,6 +254,7 @@ static const struct dpu_pingpong_cfg x1e80100_pp[] = { }, { .name = "pingpong_5", .id = PINGPONG_5, .base = 0x6e000, .len = 0, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_2, @@ -255,12 +262,14 @@ static const struct dpu_pingpong_cfg x1e80100_pp[] = { }, { .name = "pingpong_cwb_0", .id = PINGPONG_CWB_0, .base = 0x66000, .len = 0, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_3, }, { .name = "pingpong_cwb_1", .id = PINGPONG_CWB_1, .base = 0x66400, .len = 0, + .max_linewidth = DPU_6_x_MAX_PINGPONG_WIDTH, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_3, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 5f1f3eae0f6f..194780905d29 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -24,6 +24,12 @@ #define DPU_MAX_IMG_WIDTH 0x3fff #define DPU_MAX_IMG_HEIGHT 0x3fff +#define DPU_1_x_MAX_PINGPONG_WIDTH 4096 +#define DPU_6_x_MAX_PINGPONG_WIDTH 5120 +#define DPU_8_x_MAX_PINGPONG_0_WIDTH 8960 + +#define DEFAULT_DSC_ENCODER_MAX_WIDTH 2560 + #define CRTC_DUAL_MIXERS 2 #define MAX_XIN_COUNT 16 @@ -336,6 +342,7 @@ struct dpu_rotation_cfg { /** * struct dpu_caps - define DPU capabilities * @max_mixer_width max layer mixer line width support. + * @max_dsc_encoder_width max dsc encoder line width support * @max_mixer_blendstages max layer mixer blend stages or * supported z order * @has_src_split source split feature status @@ -349,6 +356,7 @@ struct dpu_rotation_cfg { */ struct dpu_caps { u32 max_mixer_width; + u32 max_dsc_encoder_width; u32 max_mixer_blendstages; bool has_src_split; bool has_dim_layer; @@ -530,6 +538,7 @@ struct dpu_dspp_cfg { * @id enum identifying this block * @base register offset of this block * @features bit mask identifying sub-blocks/features + * @max_linewidth max linewidth for PINGPONG * @intr_done: index for PINGPONG done interrupt * @intr_rdptr: index for PINGPONG readpointer done interrupt * @sblk sub-blocks information @@ -537,6 +546,7 @@ struct dpu_dspp_cfg { struct dpu_pingpong_cfg { DPU_HW_BLK_INFO; u32 merge_3d; + u32 max_linewidth; unsigned int intr_done; unsigned int intr_rdptr; const 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In addition, drop MAX_HDISPLAY_SPLIT and base LM reservation off of PINGPONG or DSC encoder max width As noted in the patch, while DPU 8.x+ supports a max linewidth of 8960 for PINGPONG_0, there is some additional logic that needs to be added to the resource manager to specifically try and reserve PINGPONG_0 for modes that are greater than 5k. Since this is out of the scope of this series, add a helper that will get the overall minimum PINGPONG max linewidth for a given chipset. Signed-off-by: Jessica Zhang --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 46 +++++++++++++++++++++++++++----- 1 file changed, 39 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 0714936d8835..6131d071b051 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -723,6 +723,31 @@ void dpu_crtc_complete_commit(struct drm_crtc *crtc) _dpu_crtc_complete_flip(crtc); } +static int msm_display_get_max_pingpong_width(struct dpu_kms *dpu_kms) +{ + const struct dpu_pingpong_cfg *pingpong; + u32 max_pingpong_width = dpu_kms->catalog->pingpong[0].max_linewidth; + + /* + * Find the smallest overall PINGPONG max_linewidth in the catalog since + * max_linewidth can differ between PINGPONGs even within the same + * chipset. + * + * Note: While, for DPU 8.x+, PINGPONG_0 can technically support up to + * 8k resolutions, this requires reworking the RM to try to reserve + * PINGPONG_0 for modes greater than 5k. + * + * Once this additional logic is implemented, we can drop this helper + * and use the reserved PINGPONG's max_linewidth + */ + for (int i = 1; i < dpu_kms->catalog->pingpong_count; i++) { + pingpong = &dpu_kms->catalog->pingpong[i]; + max_pingpong_width = min(max_pingpong_width, pingpong->max_linewidth); + } + + return max_pingpong_width; +} + static int _dpu_crtc_check_and_setup_lm_bounds(struct drm_crtc *crtc, struct drm_crtc_state *state) { @@ -730,13 +755,14 @@ static int _dpu_crtc_check_and_setup_lm_bounds(struct drm_crtc *crtc, struct drm_display_mode *adj_mode = &state->adjusted_mode; u32 crtc_split_width = adj_mode->hdisplay / cstate->num_mixers; struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc); + int max_pingpong_width = msm_display_get_max_pingpong_width(dpu_kms); int i; /* if we cannot merge 2 LMs (no 3d mux) better to fail earlier * before even checking the width after the split */ if (!dpu_kms->catalog->caps->has_3d_merge && - adj_mode->hdisplay > dpu_kms->catalog->caps->max_mixer_width) + adj_mode->hdisplay > max_pingpong_width) return -E2BIG; for (i = 0; i < cstate->num_mixers; i++) { @@ -748,7 +774,7 @@ static int _dpu_crtc_check_and_setup_lm_bounds(struct drm_crtc *crtc, trace_dpu_crtc_setup_lm_bounds(DRMID(crtc), i, r); - if (drm_rect_width(r) > dpu_kms->catalog->caps->max_mixer_width) + if (drm_rect_width(r) > max_pingpong_width) return -E2BIG; } @@ -1279,7 +1305,6 @@ static int dpu_crtc_reassign_planes(struct drm_crtc *crtc, struct drm_crtc_state } #define MAX_CHANNELS_PER_CRTC 2 -#define MAX_HDISPLAY_SPLIT 1080 static struct msm_display_topology dpu_crtc_get_topology( struct drm_crtc *crtc, @@ -1289,12 +1314,18 @@ static struct msm_display_topology dpu_crtc_get_topology( struct drm_display_mode *mode = &crtc_state->adjusted_mode; struct msm_display_topology topology = {0}; struct drm_encoder *drm_enc; + const struct dpu_caps *caps = dpu_kms->catalog->caps; + u32 max_hdisplay_split; drm_for_each_encoder_mask(drm_enc, crtc->dev, crtc_state->encoder_mask) dpu_encoder_update_topology(drm_enc, &topology, crtc_state->state, &crtc_state->adjusted_mode); topology.cwb_enabled = drm_crtc_in_clone_mode(crtc_state); + max_hdisplay_split = msm_display_get_max_pingpong_width(dpu_kms); + + if (topology.num_dsc > 0 && caps->max_dsc_encoder_width > 0) + max_hdisplay_split = min(max_hdisplay_split, caps->max_dsc_encoder_width); /* * Datapath topology selection @@ -1315,7 +1346,7 @@ static struct msm_display_topology dpu_crtc_get_topology( * count both the WB and real-time phys encoders. * * For non-DSC CWB usecases, have the num_lm be decided by the - * (mode->hdisplay > MAX_HDISPLAY_SPLIT) check. + * (mode->hdisplay > max_hdisplay_split) check. */ if (topology.num_intf == 2 && !topology.cwb_enabled) @@ -1323,7 +1354,7 @@ static struct msm_display_topology dpu_crtc_get_topology( else if (topology.num_dsc == 2) topology.num_lm = 2; else if (dpu_kms->catalog->caps->has_3d_merge) - topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1; + topology.num_lm = (mode->hdisplay > max_hdisplay_split) ? 2 : 1; else topology.num_lm = 1; @@ -1501,18 +1532,19 @@ static enum drm_mode_status dpu_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode) { struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc); + int max_pingpong_width = msm_display_get_max_pingpong_width(dpu_kms); /* if there is no 3d_mux block we cannot merge LMs so we cannot * split the large layer into 2 LMs, filter out such modes */ if (!dpu_kms->catalog->caps->has_3d_merge && - mode->hdisplay > dpu_kms->catalog->caps->max_mixer_width) + mode->hdisplay > max_pingpong_width) return MODE_BAD_HVALUE; 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Signed-off-by: Jessica Zhang --- drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c index 8ff496082902..0a198896f656 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c @@ -14,14 +14,7 @@ static int dpu_wb_conn_get_modes(struct drm_connector *connector) struct msm_drm_private *priv = dev->dev_private; struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms); - /* - * We should ideally be limiting the modes only to the maxlinewidth but - * on some chipsets this will allow even 4k modes to be added which will - * fail the per SSPP bandwidth checks. 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[199.106.103.254]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22fc8271aebsm104468735ad.107.2025.05.14.16.52.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 May 2025 16:52:47 -0700 (PDT) From: Jessica Zhang Date: Wed, 14 May 2025 16:52:33 -0700 Subject: [PATCH 5/5] drm/msm/dpu: Remove max_mixer_width from catalog Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250514-max-mixer-width-v1-5-c8ba0d9bb858@oss.qualcomm.com> References: <20250514-max-mixer-width-v1-0-c8ba0d9bb858@oss.qualcomm.com> In-Reply-To: <20250514-max-mixer-width-v1-0-c8ba0d9bb858@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Abhinav Kumar Cc: Abhinav Kumar , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jessica Zhang X-Mailer: b4 0.15-dev-64971 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747266760; l=17506; i=jessica.zhang@oss.qualcomm.com; s=20230329; h=from:subject:message-id; bh=FR/UnX260/Vn2NQFCzJ2cky51dUA4u7bl7zZ9YB/KsI=; b=5wBSmSpRMWf2bCUYh0At2gpXO5rSk2pn8aZ9HFmsRshcMHbb9pV86YFbWjc7TsjwjYfCOBUlF B1LK4QtlSTKCY1zxvqmWKGnchvGIzdxzxqTTJ85YcZrS/7RxledDoxV X-Developer-Key: i=jessica.zhang@oss.qualcomm.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE0MDIyMiBTYWx0ZWRfX2JUVbyd0SwBp L5epeEoFlvihH0srQdxZQMeLICA9WtEqOUf3eE6poKI2UJJMPBmZkVg13sZuzK/NctGbq1o7obu TOwtRvtG2A670AaCY0TsupDwqbAsEsfJ0TQCJheyp7EkS5CvFUiQLxxhD4ed1B4fVSLhoGidy0i 03nl8trpD+H7V9cso0H4njNhMqjjObSwEcbSLfxQaWt9tn4RTqj34GKELUa9KgSg124Rr2XQ/SK 8fwsuGPuwXlmcS2R3LDZtK6vnykPZXbdlWi9p904I31i+skdqKQIpR53P+/Ctbp78RAvJdeSCaF 9aLlU10S3Ov4O68z6vCO8ACjX9sij9DE+FbtpFJu++Z92rrba8rKkI1cu2NBzEGlWCIQyo6BQr3 icvKn+WBFg4P9qXPqiU9vD3QR3rBYNYm7hMNCKQHyGCVJxlJVz4JiXzd71ouSnxuHmuwZ4Lg X-Authority-Analysis: v=2.4 cv=G5scE8k5 c=1 sm=1 tr=0 ts=68252cd1 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=EUspDBNiAAAA:8 a=nedybW00AaWt5EjSzA4A:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-GUID: YguBrtt5vGMh7CM3dX2btPOUURYjmX1d X-Proofpoint-ORIG-GUID: YguBrtt5vGMh7CM3dX2btPOUURYjmX1d X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-14_04,2025-05-14_03,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxlogscore=999 clxscore=1015 phishscore=0 bulkscore=0 suspectscore=0 spamscore=0 impostorscore=0 lowpriorityscore=0 mlxscore=0 malwarescore=0 adultscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505140222 Remove the now-unused max_mixer_width field from the HW catalog Signed-off-by: Jessica Zhang Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 -- 28 files changed, 29 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h index 9db31591e27e..2f0f4cf07338 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h @@ -8,7 +8,6 @@ #define _DPU_10_0_SM8650_H static const struct dpu_caps sm8650_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_dsc_encoder_width = DEFAULT_DSC_ENCODER_MAX_WIDTH, .max_mixer_blendstages = 0xb, .has_src_split = true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h index 4ac89cadf328..6c1bfd6b6ac9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h @@ -7,7 +7,6 @@ #define _DPU_1_14_MSM8937_H static const struct dpu_caps msm8937_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_LINE_WIDTH, .max_mixer_blendstages = 0x4, .max_linewidth = DEFAULT_DPU_LINE_WIDTH, .pixel_ram_size = 40 * 1024, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h index dbd4129439a8..c00d45b8fb6f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h @@ -7,7 +7,6 @@ #define _DPU_1_14_MSM8917_H static const struct dpu_caps msm8917_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_LINE_WIDTH, .max_mixer_blendstages = 0x4, .max_linewidth = DEFAULT_DPU_LINE_WIDTH, .pixel_ram_size = 16 * 1024, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h index a93976f6167c..5c1383b31691 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h @@ -7,7 +7,6 @@ #define _DPU_1_16_MSM8953_H static const struct dpu_caps msm8953_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_LINE_WIDTH, .max_mixer_blendstages = 0x4, .max_linewidth = DEFAULT_DPU_LINE_WIDTH, .pixel_ram_size = 40 * 1024, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h index e2e99504c715..5dcd1f81a4c5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h @@ -9,7 +9,6 @@ #define _DPU_1_7_MSM8996_H static const struct dpu_caps msm8996_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0x7, .has_src_split = true, .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h index 1bdffe168fb1..a283b4107f8a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h @@ -8,7 +8,6 @@ #define _DPU_3_0_MSM8998_H static const struct dpu_caps msm8998_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0x7, .has_src_split = true, .has_dim_layer = true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h index 03f46a652449..0c8362befe62 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h @@ -7,7 +7,6 @@ #define _DPU_3_2_SDM660_H static const struct dpu_caps sdm660_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0x7, .has_src_split = true, .has_dim_layer = true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h index 011e98e6e7db..49b9bd52bf41 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h @@ -7,7 +7,6 @@ #define _DPU_3_3_SDM630_H static const struct dpu_caps sdm630_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_LINE_WIDTH, .max_mixer_blendstages = 0x7, .has_src_split = true, .has_dim_layer = true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h index 152fa5ea12dd..e35fbe0eb1db 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h @@ -8,7 +8,6 @@ #define _DPU_4_0_SDM845_H static const struct dpu_caps sdm845_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0xb, .has_src_split = true, .has_dim_layer = true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h index 7f0754e47c2e..b55cc140aa88 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h @@ -8,7 +8,6 @@ #define _DPU_5_0_SM8150_H static const struct dpu_caps sm8150_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0xb, .has_src_split = true, .has_dim_layer = true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h index 1a904b68950a..22bfd755d214 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h @@ -8,7 +8,6 @@ #define _DPU_5_1_SC8180X_H static const struct dpu_caps sc8180x_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0xb, .has_src_split = true, .has_dim_layer = true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h index 7c65f77a2c43..6ca54f2401d6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h @@ -8,7 +8,6 @@ #define _DPU_5_2_SM7150_H static const struct dpu_caps sm7150_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0xb, .has_src_split = true, .has_dim_layer = true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h index f0539dd11dc8..2f21b01393b6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h @@ -7,7 +7,6 @@ #define _DPU_5_3_SM6150_H static const struct dpu_caps sm6150_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0x9, .has_dim_layer = true, .has_idle_pc = true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h index a357567ad597..e5c5945a0385 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h @@ -9,7 +9,6 @@ #define _DPU_5_4_SM6125_H static const struct dpu_caps sm6125_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0x6, .has_dim_layer = true, .has_idle_pc = true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h index c0bf1eba1eab..ba2b5dda1054 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h @@ -8,7 +8,6 @@ #define _DPU_6_0_SM8250_H static const struct dpu_caps sm8250_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0xb, .has_src_split = true, .has_dim_layer = true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h index d004e7ee71fb..43c7f6794cb5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h @@ -8,7 +8,6 @@ #define _DPU_6_2_SC7180_H static const struct dpu_caps sc7180_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0x9, .has_dim_layer = true, .has_idle_pc = true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h index b0659b55542f..7c2be386fc73 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h @@ -8,7 +8,6 @@ #define _DPU_6_3_SM6115_H static const struct dpu_caps sm6115_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_LINE_WIDTH, .max_mixer_blendstages = 0x4, .has_dim_layer = true, .has_idle_pc = true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h index ae0196372f35..6c4531be116f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h @@ -9,7 +9,6 @@ #define _DPU_6_4_SM6350_H static const struct dpu_caps sm6350_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0x7, .has_src_split = true, .has_dim_layer = true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h index d9bb18f11a49..b5f78064f761 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h @@ -8,7 +8,6 @@ #define _DPU_6_5_QCM2290_H static const struct dpu_caps qcm2290_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_LINE_WIDTH, .max_mixer_blendstages = 0x4, .has_dim_layer = true, .has_idle_pc = true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h index 8893b39e2ca3..0564f108db22 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h @@ -9,7 +9,6 @@ #define _DPU_6_9_SM6375_H static const struct dpu_caps sm6375_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_LINE_WIDTH, .max_mixer_blendstages = 0x4, .has_dim_layer = true, .has_idle_pc = true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h index 6ded8b0309d9..31517c894a13 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h @@ -8,7 +8,6 @@ #define _DPU_7_0_SM8350_H static const struct dpu_caps sm8350_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_dsc_encoder_width = DEFAULT_DSC_ENCODER_MAX_WIDTH, .max_mixer_blendstages = 0xb, .has_src_split = true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h index e1512ff5945c..9c5bc570b754 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h @@ -8,7 +8,6 @@ #define _DPU_7_2_SC7280_H static const struct dpu_caps sc7280_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_dsc_encoder_width = DEFAULT_DSC_ENCODER_MAX_WIDTH, .max_mixer_blendstages = 0x7, .has_dim_layer = true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h index 2a084ee071b9..f2fbff348d16 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -8,7 +8,6 @@ #define _DPU_8_0_SC8280XP_H static const struct dpu_caps sc8280xp_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_dsc_encoder_width = DEFAULT_DSC_ENCODER_MAX_WIDTH, .max_mixer_blendstages = 11, .has_src_split = true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h index 2cb3966ee51f..5e9cb02602ae 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -8,7 +8,6 @@ #define _DPU_8_1_SM8450_H static const struct dpu_caps sm8450_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_dsc_encoder_width = DEFAULT_DSC_ENCODER_MAX_WIDTH, .max_mixer_blendstages = 0xb, .has_src_split = true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h index 1135918e0a86..e3b332c313b3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h @@ -7,7 +7,6 @@ #define _DPU_8_4_SA8775P_H static const struct dpu_caps sa8775p_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_dsc_encoder_width = DEFAULT_DSC_ENCODER_MAX_WIDTH, .max_mixer_blendstages = 0xb, .has_src_split = true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index 0516e75a3a16..a27a50da28d9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -8,7 +8,6 @@ #define _DPU_9_0_SM8550_H static const struct dpu_caps sm8550_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_dsc_encoder_width = DEFAULT_DSC_ENCODER_MAX_WIDTH, .max_mixer_blendstages = 0xb, .has_src_split = true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h index 23d044e10c75..7d5b94408e69 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h @@ -7,7 +7,6 @@ #define _DPU_9_2_X1E80100_H static const struct dpu_caps x1e80100_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_dsc_encoder_width = DEFAULT_DSC_ENCODER_MAX_WIDTH, .max_mixer_blendstages = 0xb, .has_src_split = true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 194780905d29..f0534c0cd905 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -341,7 +341,6 @@ struct dpu_rotation_cfg { /** * struct dpu_caps - define DPU capabilities - * @max_mixer_width max layer mixer line width support. * @max_dsc_encoder_width max dsc encoder line width support * @max_mixer_blendstages max layer mixer blend stages or * supported z order @@ -355,7 +354,6 @@ struct dpu_rotation_cfg { * @max_vdeci_exp max vertical decimation supported (max is 2^value) */ struct dpu_caps { - u32 max_mixer_width; u32 max_dsc_encoder_width; u32 max_mixer_blendstages; bool has_src_split;