From patchwork Wed May 14 09:22:57 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 890474 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 51BED227BA1; Wed, 14 May 2025 09:23:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747214591; cv=none; b=g3m8uTCYB8DYlYgl4k3p8CnI1z0Sm+Cv9e/S2UBhR25H95Jbbw0SQvJG2ZX/2B2gkyDexUN1kUInAebNeQlKCTXiDl5Sx+8U1uqWndtB+qX+f3JV4HKUvKq2O/OzbdFvY7YLjjItiy993zzTtKZELd0jTNNdgVpaN7gGEVqiNVU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747214591; c=relaxed/simple; bh=+1pbbQr6IhaWYuDDxWS5O5XFpl8IElD/YxVqY/H8a60=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=dpcGRHrpyA8pp4cb4Hw0PG/wmDgGvW4Wpxnb5ZYVB7uposX6v2EXfPfCz7Prdh8m3lFXmAPioSjOefED1FMABcY0kQKlRpcM2iTFZMnTI5z5b1FODufRJjvqdLfi/fKCEIkLIro0D4NqNIv7w3OM2jLFmDmkqIV4X3TfvPgf4dc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=Wh4sc9Qa; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="Wh4sc9Qa" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1747214587; bh=+1pbbQr6IhaWYuDDxWS5O5XFpl8IElD/YxVqY/H8a60=; h=From:To:Cc:Subject:Date:From; b=Wh4sc9Qa05xj4yd8MmneyFPg0FeSVWh+s//2l7EzCfr2FlhjG6lYhSXwNQ6xDkdgq mQN/iujkehU5CGmkaIFjS3COdJDeqDdSPGOjwbDoRYSSfHkEAcprTHep4lk68ODHlE ZWExgB1bdfoyMTfKW38EP+egdGFv9wJQnOJ0sCcldJCp/ZaH7UTUA+qq45S2oKlQqU cPmXRma/D8g8kHkyskyvC0cftGa2qj0zi7i+NxODCKXxexOOlwyNa59H2/P3L7WhDq e93+p/pdbx2EL2Q9avwLFq/70Ag5V/7V3wKFdEqh7a2sChQKNDRMW2PK9XLJvPVvhA 4K+LqYTed8WXQ== Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id AAD5217E04C0; Wed, 14 May 2025 11:23:06 +0200 (CEST) From: AngeloGioacchino Del Regno To: robh@kernel.org Cc: linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, AngeloGioacchino Del Regno , Nicolas Dufresne , Chun-Kuang Hu , Conor Dooley Subject: [PATCH v2 1/3] dt-bindings: display: mediatek: Add compatibles for MT8188 MDP3 Date: Wed, 14 May 2025 11:22:57 +0200 Message-ID: <20250514092259.47035-1-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.49.0 Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add compatible strings for the AAL, COLOR, MERGE and PADDING hardware components found in MediaTek's MT8188 SoC. This hardware is compatible with MT8195. Acked-by: Nicolas Dufresne Acked-by: Chun-Kuang Hu Acked-by: Conor Dooley Signed-off-by: AngeloGioacchino Del Regno --- .../bindings/display/mediatek/mediatek,aal.yaml | 4 ++++ .../bindings/display/mediatek/mediatek,color.yaml | 4 ++++ .../bindings/display/mediatek/mediatek,merge.yaml | 4 ++++ .../bindings/display/mediatek/mediatek,padding.yaml | 10 +++++++--- 4 files changed, 19 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml index 5d2089dc596e..daf90ebb39bf 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml @@ -25,6 +25,10 @@ properties: - mediatek,mt8173-disp-aal - mediatek,mt8183-disp-aal - mediatek,mt8195-mdp3-aal + - items: + - enum: + - mediatek,mt8188-mdp3-aal + - const: mediatek,mt8195-mdp3-aal - items: - enum: - mediatek,mt2712-disp-aal diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml index 6160439ce4d7..5564f4063317 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml @@ -27,6 +27,10 @@ properties: - mediatek,mt8167-disp-color - mediatek,mt8173-disp-color - mediatek,mt8195-mdp3-color + - items: + - enum: + - mediatek,mt8188-mdp3-color + - const: mediatek,mt8195-mdp3-color - items: - enum: - mediatek,mt7623-disp-color diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml index 0de9f64f3f84..3798a25402d3 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml @@ -25,6 +25,10 @@ properties: - mediatek,mt8173-disp-merge - mediatek,mt8195-disp-merge - mediatek,mt8195-mdp3-merge + - items: + - enum: + - mediatek,mt8188-mdp3-merge + - const: mediatek,mt8195-mdp3-merge - items: - const: mediatek,mt6795-disp-merge - const: mediatek,mt8173-disp-merge diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml index be07bbdc54e3..86787866ced0 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml @@ -20,9 +20,13 @@ description: properties: compatible: - enum: - - mediatek,mt8188-disp-padding - - mediatek,mt8195-mdp3-padding + oneOf: + - enum: + - mediatek,mt8188-disp-padding + - mediatek,mt8195-mdp3-padding + - items: + - const: mediatek,mt8188-mdp3-padding + - const: mediatek,mt8195-mdp3-padding reg: maxItems: 1 From patchwork Wed May 14 09:22:58 2025 Content-Type: text/plain; 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Wed, 14 May 2025 11:23:07 +0200 (CEST) From: AngeloGioacchino Del Regno To: robh@kernel.org Cc: linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, AngeloGioacchino Del Regno , Nicolas Dufresne , Chun-Kuang Hu , Conor Dooley Subject: [PATCH v2 2/3] dt-bindings: media: mediatek: mdp3: Add compatibles for MT8188 MDP3 Date: Wed, 14 May 2025 11:22:58 +0200 Message-ID: <20250514092259.47035-2-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250514092259.47035-1-angelogioacchino.delregno@collabora.com> References: <20250514092259.47035-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add compatible strings for the FG, HDR, RSZ, STITCH, TCC, TDSHP and WROT hardware components found in MediaTek's MT8188 SoC. This hardware is compatible with MT8195. Acked-by: Nicolas Dufresne Acked-by: Conor Dooley Signed-off-by: AngeloGioacchino Del Regno --- .../devicetree/bindings/media/mediatek,mdp3-fg.yaml | 8 ++++++-- .../devicetree/bindings/media/mediatek,mdp3-hdr.yaml | 8 ++++++-- .../devicetree/bindings/media/mediatek,mdp3-rsz.yaml | 1 + .../devicetree/bindings/media/mediatek,mdp3-stitch.yaml | 8 ++++++-- .../devicetree/bindings/media/mediatek,mdp3-tcc.yaml | 8 ++++++-- .../devicetree/bindings/media/mediatek,mdp3-tdshp.yaml | 8 ++++++-- .../devicetree/bindings/media/mediatek,mdp3-wrot.yaml | 1 + 7 files changed, 32 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml index 03f31b009085..40fda59fa8a8 100644 --- a/Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml @@ -16,8 +16,12 @@ description: properties: compatible: - enum: - - mediatek,mt8195-mdp3-fg + oneOf: + - enum: + - mediatek,mt8195-mdp3-fg + - items: + - const: mediatek,mt8188-mdp3-fg + - const: mediatek,mt8195-mdp3-fg reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml index d4609bba6578..d9f926c20220 100644 --- a/Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml @@ -16,8 +16,12 @@ description: properties: compatible: - enum: - - mediatek,mt8195-mdp3-hdr + oneOf: + - enum: + - mediatek,mt8195-mdp3-hdr + - items: + - const: mediatek,mt8188-mdp3-hdr + - const: mediatek,mt8195-mdp3-hdr reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml index f5676bec4326..8124c39d73e9 100644 --- a/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml @@ -20,6 +20,7 @@ properties: - mediatek,mt8183-mdp3-rsz - items: - enum: + - mediatek,mt8188-mdp3-rsz - mediatek,mt8195-mdp3-rsz - const: mediatek,mt8183-mdp3-rsz diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml index d815bea29154..1d8e7e202c42 100644 --- a/Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml @@ -16,8 +16,12 @@ description: properties: compatible: - enum: - - mediatek,mt8195-mdp3-stitch + oneOf: + - enum: + - mediatek,mt8195-mdp3-stitch + - items: + - const: mediatek,mt8188-mdp3-stitch + - const: mediatek,mt8195-mdp3-stitch reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml index 14ea556d4f82..6cff7c073ce4 100644 --- a/Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml @@ -17,8 +17,12 @@ description: properties: compatible: - enum: - - mediatek,mt8195-mdp3-tcc + oneOf: + - enum: + - mediatek,mt8195-mdp3-tcc + - items: + - const: mediatek,mt8188-mdp3-tcc + - const: mediatek,mt8195-mdp3-tcc reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml index 8ab7f2d8e148..cdfa27324738 100644 --- a/Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml @@ -16,8 +16,12 @@ description: properties: compatible: - enum: - - mediatek,mt8195-mdp3-tdshp + oneOf: + - enum: + - mediatek,mt8195-mdp3-tdshp + - items: + - const: mediatek,mt8188-mdp3-tdshp + - const: mediatek,mt8195-mdp3-tdshp reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml index 53a679338402..b6269f4f9fd6 100644 --- a/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml @@ -20,6 +20,7 @@ properties: - mediatek,mt8183-mdp3-wrot - items: - enum: + - mediatek,mt8188-mdp3-wrot - mediatek,mt8195-mdp3-wrot - const: mediatek,mt8183-mdp3-wrot From patchwork Wed May 14 09:22:59 2025 Content-Type: text/plain; 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Wed, 14 May 2025 11:23:08 +0200 (CEST) From: AngeloGioacchino Del Regno To: robh@kernel.org Cc: linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, AngeloGioacchino Del Regno , Nicolas Dufresne , Chun-Kuang Hu , Conor Dooley Subject: [PATCH v2 3/3] arm64: dts: mediatek: mt8188: Add all Multimedia Data Path 3 nodes Date: Wed, 14 May 2025 11:22:59 +0200 Message-ID: <20250514092259.47035-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250514092259.47035-1-angelogioacchino.delregno@collabora.com> References: <20250514092259.47035-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add all of the Multimedia Data Path 3 (MDP3) related nodes including its Mutex instances, one for each VPPSYS block, and all of its DMA controllers, Film Grain (FG), HDR, Adaptive Ambient Light (AAL), Frame Resizer (RSZ), Tone Curve Conversion (TCC), Two-Dimensional Sharpness (TDSHP), and others, enabling the entire MDP3 macro-block. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 299 +++++++++++++++++++++++ 1 file changed, 299 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi index 29d35ca94597..55260357ac66 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -2224,6 +2224,118 @@ vppsys0: syscon@14000000 { #clock-cells = <1>; }; + dma-controller@14001000 { + compatible = "mediatek,mt8188-mdp3-rdma"; + reg = <0 0x14001000 0 0x1000>; + #dma-cells = <1>; + clocks = <&vppsys0 CLK_VPP0_MDP_RDMA>; + mboxes = <&gce0 13 CMDQ_THR_PRIO_1>, + <&gce0 14 CMDQ_THR_PRIO_1>, + <&gce0 16 CMDQ_THR_PRIO_1>, + <&gce0 21 CMDQ_THR_PRIO_1>, + <&gce0 22 CMDQ_THR_PRIO_1>; + iommus = <&vpp_iommu M4U_PORT_L4_MDP_RDMA>; + power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>; + mediatek,gce-events = , + ; + mediatek,scp = <&scp>; + }; + + display@14002000 { + compatible = "mediatek,mt8188-mdp3-fg", "mediatek,mt8195-mdp3-fg"; + reg = <0 0x14002000 0 0x1000>; + clocks = <&vppsys0 CLK_VPP0_MDP_FG>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>; + }; + + display@14004000 { + compatible = "mediatek,mt8188-mdp3-hdr", "mediatek,mt8195-mdp3-hdr"; + reg = <0 0x14004000 0 0x1000>; + clocks = <&vppsys0 CLK_VPP0_MDP_HDR>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>; + }; + + display@14005000 { + compatible = "mediatek,mt8188-mdp3-aal", "mediatek,mt8195-mdp3-aal"; + reg = <0 0x14005000 0 0x1000>; + interrupts = ; + clocks = <&vppsys0 CLK_VPP0_MDP_AAL>; + power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x5000 0x1000>; + }; + + display@14006000 { + compatible = "mediatek,mt8188-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; + reg = <0 0x14006000 0 0x1000>; + clocks = <&vppsys0 CLK_VPP0_MDP_RSZ>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x6000 0x1000>; + mediatek,gce-events = , + ; + }; + + display@14007000 { + compatible = "mediatek,mt8188-mdp3-tdshp", "mediatek,mt8195-mdp3-tdshp"; + reg = <0 0x14007000 0 0x1000>; + clocks = <&vppsys0 CLK_VPP0_MDP_TDSHP>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x7000 0x1000>; + }; + + display@14008000 { + compatible = "mediatek,mt8188-mdp3-color", "mediatek,mt8195-mdp3-color"; + reg = <0 0x14008000 0 0x1000>; + interrupts = ; + clocks = <&vppsys0 CLK_VPP0_MDP_COLOR>; + power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x8000 0x1000>; + }; + + display@14009000 { + compatible = "mediatek,mt8188-mdp3-ovl", "mediatek,mt8195-mdp3-ovl"; + reg = <0 0x14009000 0 0x1000>; + interrupts = ; + clocks = <&vppsys0 CLK_VPP0_MDP_OVL>; + power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x9000 0x1000>; + iommus = <&vpp_iommu M4U_PORT_L4_MDP_OVL>; + }; + + display@1400a000 { + compatible = "mediatek,mt8188-mdp3-padding", "mediatek,mt8195-mdp3-padding"; + reg = <0 0x1400a000 0 0x1000>; + clocks = <&vppsys0 CLK_VPP0_PADDING>; + power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xa000 0x1000>; + }; + + display@1400b000 { + compatible = "mediatek,mt8188-mdp3-tcc", "mediatek,mt8195-mdp3-tcc"; + reg = <0 0x1400b000 0 0x1000>; + clocks = <&vppsys0 CLK_VPP0_MDP_TCC>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>; + }; + + display@1400c000 { + compatible = "mediatek,mt8188-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; + reg = <0 0x1400c000 0 0x1000>; + #dma-cells = <1>; + clocks = <&vppsys0 CLK_VPP0_MDP_WROT>; + iommus = <&vpp_iommu M4U_PORT_L4_MDP_WROT>; + power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xc000 0x1000>; + mediatek,gce-events = , + ; + }; + + mutex@1400f000 { + compatible = "mediatek,mt8188-vpp-mutex"; + reg = <0 0x1400f000 0 0x1000>; + interrupts = ; + clocks = <&vppsys0 CLK_VPP0_MUTEX>; + power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xf000 0x1000>; + }; + vpp_smi_common: smi@14012000 { compatible = "mediatek,mt8188-smi-common-vpp"; reg = <0 0x14012000 0 0x1000>; @@ -2255,6 +2367,184 @@ vpp_iommu: iommu@14018000 { mediatek,larbs = <&larb1 &larb3 &larb4 &larb6 &larb7 &larb23>; }; + dma-controller@14f09000 { + compatible = "mediatek,mt8188-mdp3-rdma"; + reg = <0 0x14f09000 0 0x1000>; + #dma-cells = <1>; + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RDMA>; + iommus = <&vdo_iommu M4U_PORT_L5_SVPP2_MDP_RDMA>; + power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x9000 0x1000>; + mediatek,gce-events = , + ; + }; + + dma-controller@14f0a000 { + compatible = "mediatek,mt8188-mdp3-rdma"; + reg = <0 0x14f0a000 0 0x1000>; + #dma-cells = <1>; + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RDMA>; + iommus = <&vpp_iommu M4U_PORT_L6_SVPP3_MDP_RDMA>; + power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xa000 0x1000>; + mediatek,gce-events = , + ; + }; + + display@14f0c000 { + compatible = "mediatek,mt8188-mdp3-fg", "mediatek,mt8195-mdp3-fg"; + reg = <0 0x14f0c000 0 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_FG>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xc000 0x1000>; + }; + + display@14f0d000 { + compatible = "mediatek,mt8188-mdp3-fg", "mediatek,mt8195-mdp3-fg"; + reg = <0 0x14f0d000 0 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_FG>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xd000 0x1000>; + }; + + display@14f0f000 { + compatible = "mediatek,mt8188-mdp3-hdr", "mediatek,mt8195-mdp3-hdr"; + reg = <0 0x14f0f000 0 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_HDR>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xf000 0x1000>; + }; + + display@14f10000 { + compatible = "mediatek,mt8188-mdp3-hdr", "mediatek,mt8195-mdp3-hdr"; + reg = <0 0x14f10000 0 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_HDR>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0 0x1000>; + }; + + display@14f12000 { + compatible = "mediatek,mt8188-mdp3-aal", "mediatek,mt8195-mdp3-aal"; + reg = <0 0x14f12000 0 0x1000>; + interrupts = ; + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_AAL>; + power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x2000 0x1000>; + }; + + display@14f13000 { + compatible = "mediatek,mt8188-mdp3-aal", "mediatek,mt8195-mdp3-aal"; + reg = <0 0x14f13000 0 0x1000>; + interrupts = ; + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_AAL>; + power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x3000 0x1000>; + }; + + display@14f15000 { + compatible = "mediatek,mt8188-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; + reg = <0 0x14f15000 0 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RSZ>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x5000 0x1000>; + mediatek,gce-events = , + ; + }; + + display@14f16000 { + compatible = "mediatek,mt8188-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; + reg = <0 0x14f16000 0 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RSZ>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x6000 0x1000>; + mediatek,gce-events = , + ; + }; + + display@14f18000 { + compatible = "mediatek,mt8188-mdp3-tdshp", "mediatek,mt8195-mdp3-tdshp"; + reg = <0 0x14f18000 0 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_TDSHP>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x8000 0x1000>; + }; + + display@14f19000 { + compatible = "mediatek,mt8188-mdp3-tdshp", "mediatek,mt8195-mdp3-tdshp"; + reg = <0 0x14f19000 0 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_TDSHP>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x9000 0x1000>; + }; + + display@14f1a000 { + compatible = "mediatek,mt8188-mdp3-merge", "mediatek,mt8195-mdp3-merge"; + reg = <0 0x14f1a000 0 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_MERGE>; + power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xa000 0x1000>; + }; + + display@14f1b000 { + compatible = "mediatek,mt8188-mdp3-merge", "mediatek,mt8195-mdp3-merge"; + reg = <0 0x14f1b000 0 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_MERGE>; + power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xb000 0x1000>; + }; + + display@14f1d000 { + compatible = "mediatek,mt8188-mdp3-color", "mediatek,mt8195-mdp3-color"; + reg = <0 0x14f1d000 0 0x1000>; + interrupts = ; + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_COLOR>; + power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xd000 0x1000>; + }; + + display@14f1e000 { + compatible = "mediatek,mt8188-mdp3-color", "mediatek,mt8195-mdp3-color"; + reg = <0 0x14f1e000 0 0x1000>; + interrupts = ; + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_COLOR>; + power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xe000 0x1000>; + }; + + display@14f21000 { + compatible = "mediatek,mt8188-mdp3-padding", + "mediatek,mt8195-mdp3-padding"; + reg = <0 0x14f21000 0 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_PAD>; + power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x1000 0x1000>; + }; + + display@14f22000 { + compatible = "mediatek,mt8188-mdp3-padding", + "mediatek,mt8195-mdp3-padding"; + reg = <0 0x14f22000 0 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_PAD>; + power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x2000 0x1000>; + }; + + display@14f24000 { + compatible = "mediatek,mt8188-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; + reg = <0 0x14f24000 0 0x1000>; + #dma-cells = <1>; + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_WROT>; + iommus = <&vdo_iommu M4U_PORT_L5_SVPP2_MDP_WROT>; + power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x4000 0x1000>; + mediatek,gce-events = , + ; + }; + + display@14f25000 { + compatible = "mediatek,mt8188-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; + reg = <0 0x14f25000 0 0x1000>; + #dma-cells = <1>; + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_WROT>; + iommus = <&vpp_iommu M4U_PORT_L6_SVPP3_MDP_WROT>; + power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x5000 0x1000>; + mediatek,gce-events = , + ; + }; + wpesys: clock-controller@14e00000 { compatible = "mediatek,mt8188-wpesys"; reg = <0 0x14e00000 0 0x1000>; @@ -2284,6 +2574,15 @@ vppsys1: syscon@14f00000 { #clock-cells = <1>; }; + mutex@14f01000 { + compatible = "mediatek,mt8188-vpp-mutex"; + reg = <0 0x14f01000 0 0x1000>; + interrupts = ; + clocks = <&vppsys1 CLK_VPP1_DISP_MUTEX>; + power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x1000 0x1000>; + }; + larb5: smi@14f02000 { compatible = "mediatek,mt8188-smi-larb"; reg = <0 0x14f02000 0 0x1000>;