From patchwork Sun May 25 17:56:04 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: George Moussalem via B4 Relay X-Patchwork-Id: 892475 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AB11624A058; Sun, 25 May 2025 17:56:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748195768; cv=none; b=CWRQiyi7Fknk/TJ81gSDQSLJGZPGLdwxvyomAamCaMINAPo9eQhTWB9sayh5dkgTbSj1rdiliOwLquoDAiI12yzGPBubh5ezb7JBqAlEiTpABHeV77vW/Zdh4zp8ywMccWhq68aVI3Pxh2I1vO007g+XphIEjjxrPfDe7uK86Ik= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748195768; c=relaxed/simple; bh=PgQd1WmItZOq2615uJLVmRncCuiX7cIc+Tm0tdKHp2A=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=bDMw2efctdJ2X8kM97hQFw+5RB1NcW1I9jhGnHOIWM+QDIZwQpTGaqS5l7CISGxPqfDQJuLc4sySXUy8UdCNwdpa6HIeysbBfWotwMFE14/My/6uHNR9f1HvWqXE5eSxbfertI6fCJUCE1E+uqGOMWqO6bKy5HjnhQlrJmSeK9M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=lgX9reo1; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="lgX9reo1" Received: by smtp.kernel.org (Postfix) with ESMTPS id 1CAE4C4CEEF; Sun, 25 May 2025 17:56:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1748195768; bh=PgQd1WmItZOq2615uJLVmRncCuiX7cIc+Tm0tdKHp2A=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=lgX9reo1HYSJFPN/qSxBu13wKB1wrVcpcqec2FRHKvZ3wn915OrwjGLGav6EgwEqV 0BfDT0avqordh2DcrfG9yAAwjiICipUuqvleXe6OaNxWyocLZLP1iTAlSppQzZeoyW f6PJe9d9D9b7YVGzdrS5amAzRYzz4C+6m9ybccnUtLs+CHYaeassk40ahzzTjHJ6Df DHXpjQNPVktIFNK029SrV72hrM++4B/r8Ztx74q2mOOvz4dDmdFzGF99X24p4136+R a3EqmgyYYfEx5PCTd6utMOiV/EcLlEVAujAqRshAFTmsKwdlxSlCRtA7Fa2TU02gCB cegayybgv2Fmg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0BC8BC54FB3; Sun, 25 May 2025 17:56:08 +0000 (UTC) From: George Moussalem via B4 Relay Date: Sun, 25 May 2025 21:56:04 +0400 Subject: [PATCH 1/5] dt-bindings: net: qca,ar803x: Add IPQ5018 Internal GE PHY support Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250525-ipq5018-ge-phy-v1-1-ddab8854e253@outlook.com> References: <20250525-ipq5018-ge-phy-v1-0-ddab8854e253@outlook.com> In-Reply-To: <20250525-ipq5018-ge-phy-v1-0-ddab8854e253@outlook.com> To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, George Moussalem X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748195765; l=2331; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=ayUL3wYd9rvR/ur2nGKYm+iV8WIysnk8OxJFKcrz/ig=; b=Aekb7yvWZ5o9Vu+/YejmG2dcGjSGGiy0sUVTXRtXoAARJBX9e0Yh53Df5khsfiuiuTzfUWXMp 7UerUABr5A2AgqMJGulb8w/DKe1Rhx1gyp/R1pqYNddLikeBxoT0d9b X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem Document the IPQ5018 Internal Gigabit Ethernet PHY found in the IPQ5018 SoC. Its output pins provide an MDI interface to either an external switch in a PHY to PHY link scenario or is directly attached to an RJ45 connector. In a phy to phy architecture, DAC values need to be set to accommodate for the short cable length. As such, add an optional property to do so. In addition, the LDO controller found in the IPQ5018 SoC needs to be enabled to driver low voltages to the CMN Ethernet Block (CMN BLK) which the GE PHY depends on. The LDO must be enabled in TCSR by writing to a specific register. So, adding a property that takes a phandle to the TCSR node and the register offset. Signed-off-by: George Moussalem --- .../devicetree/bindings/net/qca,ar803x.yaml | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/Documentation/devicetree/bindings/net/qca,ar803x.yaml b/Documentation/devicetree/bindings/net/qca,ar803x.yaml index 3acd09f0da863137f8a05e435a1fd28a536c2acd..a9e94666ff0af107db4f358b144bf8644c6597e8 100644 --- a/Documentation/devicetree/bindings/net/qca,ar803x.yaml +++ b/Documentation/devicetree/bindings/net/qca,ar803x.yaml @@ -60,6 +60,29 @@ properties: minimum: 1 maximum: 255 + qca,dac: + description: + Values for MDAC and EDAC to adjust amplitude, bias current settings, + and error detection and correction algorithm. Only set in a PHY to PHY + link architecture to accommodate for short cable length. + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - items: + - description: value for MDAC. Expected 0x10, if set + - description: value for EDAC. Expected 0x10, if set + - maxItems: 1 + + qca,eth-ldo-enable: + description: + Register in TCSR to enable the LDO controller to supply + low voltages to the common ethernet block (CMN BLK). + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle of TCSR syscon + - description: offset of TCSR register to enable the LDO controller + - maxItems: 1 + vddio-supply: description: | RGMII I/O voltage regulator (see regulator/regulator.yaml). From patchwork Sun May 25 17:56:05 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: George Moussalem via B4 Relay X-Patchwork-Id: 892811 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC62C259CBE; Sun, 25 May 2025 17:56:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748195768; cv=none; b=jMYl6mfmyZ0zhreuW7F71GbsbiLtiaUH4pAZ+Lf1oIlBCY/o0BbaFyDfBt2BW2gXnNbuTBveF4rK1uHWOuA3SMlPZBs2TVdZezG+P5hDeuht0j/lpK5GUcyZAv7Z+Cm19fc54XSVar5Z0pjoxssflvFvYV6OETMFSww7rY06tmk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748195768; c=relaxed/simple; bh=PEvKO/wryGgjZziPiEVFS4XnMJm6SAdt0loKuMnLA9A=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=RSl2nlBV31PLa/NUUPOp2530IxGkcPR1ANCzrF4uyurxddW3FD8ARmK6F8iIAJdMS0w0IzuYVpUN3Q19YCvcE6jdX3jCNQC7fdNDQsklyHUZBpYq4vbOZ7hA4DOAgl4PglxMUEKt9qV80G7+Lww27unf7X7lP7twLXFhC78cmT4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=oiW7+iro; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="oiW7+iro" Received: by smtp.kernel.org (Postfix) with ESMTPS id 29996C4AF09; Sun, 25 May 2025 17:56:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1748195768; bh=PEvKO/wryGgjZziPiEVFS4XnMJm6SAdt0loKuMnLA9A=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=oiW7+iroJjpTyWIjPq4AmdRXqkEnu5YcTzsXcYjzZnHw5EYGieoPGs7snQghgSYg2 dr0l2qPeJoT1HAT3hQs/DJrwCK/PEYufqcUGMJRYsL7befgZPTVtnh7qG/8ytiZ3nF 6VY4KWNw9/kGYFRo4cpLNgjRUpNBB1NWbzhPB5APwd1A/eoxCn1rQwH9EBc5pts0G3 MNE2PUWH44UyMpeCRikBwz/u5T4QlR35MgK7+JAjv+5205+76MoOdtl2eV8TYSvNzm GLVi2h5SEbZdWjC/fV8UNGuETazrweY9LuiSzhnZzFbQUTU/cEBhAlc80BbvtZTmOc nqyUURDIrkLhQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1BBFBC5B541; Sun, 25 May 2025 17:56:08 +0000 (UTC) From: George Moussalem via B4 Relay Date: Sun, 25 May 2025 21:56:05 +0400 Subject: [PATCH 2/5] clk: qcom: gcc-ipq5018: fix GE PHY reset Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250525-ipq5018-ge-phy-v1-2-ddab8854e253@outlook.com> References: <20250525-ipq5018-ge-phy-v1-0-ddab8854e253@outlook.com> In-Reply-To: <20250525-ipq5018-ge-phy-v1-0-ddab8854e253@outlook.com> To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, George Moussalem X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748195765; l=1149; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=oIkUIGsEO4IxSACM3i9ZzN1oSf3eDEKLwbaKL+SIoYs=; b=02XFO8KJUlDf/GQd0oZSxvLXGTZYrGzhEljPdbdnmF3LQkWU+O1zbHOfU5UYGN6hY3jyv7wMk IdbCEfGcfhPBaDz4Y5AKdRWodS3NgeHf5YGFoZkJgwCqcH0fCYGK81c X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem The MISC reset is supposed to trigger a resets across the MDC, DSP, and RX & TX clocks of the IPQ5018 internal GE PHY. So let's set the bitmask of the reset definition accordingly in the GCC as per the downstream driver. Link: https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/commit/00743c3e82fa87cba4460e7a2ba32f473a9ce932 Signed-off-by: George Moussalem --- drivers/clk/qcom/gcc-ipq5018.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/qcom/gcc-ipq5018.c b/drivers/clk/qcom/gcc-ipq5018.c index 70f5dcb96700f55da1fb19fc893d22350a7e63bf..02d6f08f389f24eccc961b9a4271288c6b635bbc 100644 --- a/drivers/clk/qcom/gcc-ipq5018.c +++ b/drivers/clk/qcom/gcc-ipq5018.c @@ -3660,7 +3660,7 @@ static const struct qcom_reset_map gcc_ipq5018_resets[] = { [GCC_WCSS_AXI_S_ARES] = { 0x59008, 6 }, [GCC_WCSS_Q6_BCR] = { 0x18004, 0 }, [GCC_WCSSAON_RESET] = { 0x59010, 0}, - [GCC_GEPHY_MISC_ARES] = { 0x56004, 0 }, + [GCC_GEPHY_MISC_ARES] = { 0x56004, .bitmask = 0xf }, }; static const struct of_device_id gcc_ipq5018_match_table[] = { From patchwork Sun May 25 17:56:06 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: George Moussalem via B4 Relay X-Patchwork-Id: 892474 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B2D6A25A2DA; Sun, 25 May 2025 17:56:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748195768; cv=none; b=CETwPJIBL908b0xSoL+4cQuU1oEi0Ua1BQkpgM7n++fEHfpjDAv8lzGsCG/L+7jqkxTGZvv8wvLEAH9z2/6mWL9MTY8iG7shhyoFogwuDN+5bglYhpDhn2kit9+THmOZ2wCRSAGrt5T+InDUhjPsN2Z+9/GOCoYddUv1pT/C/BE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748195768; c=relaxed/simple; bh=AKJIKHwqfg6frSKU+vRiCmR7f/Zj8aVNbWSz09oX9do=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=SeeIZJcgffhMSQGv8PmAuylwgrxvWI3DsIFl3mBIPTxsqXnOgu1MxgYLzG6d9X+4n1CVJAfVtCXV6EplqUmh4kZkCUxMlhJxzGAS+kzbTIAtnsZL2soXl59TQAqgq/28fUD1fFOBUwTQsXSGI7PFljSs1olZBROP2KD3kyjQvOs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=PhFrxy/B; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="PhFrxy/B" Received: by smtp.kernel.org (Postfix) with ESMTPS id 3C5B8C4CEF5; Sun, 25 May 2025 17:56:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1748195768; bh=AKJIKHwqfg6frSKU+vRiCmR7f/Zj8aVNbWSz09oX9do=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=PhFrxy/BGXdBznmC2FEPLnhJCSLEHjtlTwV3ktwF6Z5c796SJmcmFj5hUNkoBY1sx P1nzZfgdQfHrJH2vKQPYQQQvG9HYJlpToRNaiW1b6Ga6IegFa8TnCBzejwW96s6MYe zLPivNcmzm9jHrr6WQjc80YYKpZqlE1u784mvtWuW/hfOr0KbdfQDq6u590ONgCruk CyzTptlUE6XXuZDCtEnCWWkElta37jVD0QzvkH5d+ygRdJsa0LQCZLXq3mtXiqPxCt 5Y6zVTDty+d9QcdLezWYPc91sQ31Djud3uKNay8kmcdfvAbBrD1UPuTVo2Wxm3uiUm tYuCkLn8c8hrA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2BFE7C5AE59; Sun, 25 May 2025 17:56:08 +0000 (UTC) From: George Moussalem via B4 Relay Date: Sun, 25 May 2025 21:56:06 +0400 Subject: [PATCH 3/5] net: phy: qcom: at803x: Add Qualcomm IPQ5018 Internal PHY support Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250525-ipq5018-ge-phy-v1-3-ddab8854e253@outlook.com> References: <20250525-ipq5018-ge-phy-v1-0-ddab8854e253@outlook.com> In-Reply-To: <20250525-ipq5018-ge-phy-v1-0-ddab8854e253@outlook.com> To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, George Moussalem X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748195765; l=11080; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=wRbrnAUbRsi2zrpJq8AScaHZAsdMnDBTOHmfUPma2Lg=; b=4hx6HRG5ILfGlbXja0Vlly/aGVN4irzQlMfisrrBdDyyZDux5VXggXFo8tH2sGcZn3LY87DHS liBV/7/YBRiAiWu4ag0a8/oGFwyJHMNEHmVTg4sVzrXbsBFGds7yB+x X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem The IPQ5018 SoC contains a single internal Gigabit Ethernet PHY which provides an MDI interface directly to an RJ45 connector or an external switch over a PHY to PHY link. The internal LDO in the SoC itself needs to be enabled in TCSR to supply low voltages powering the common ethernet block found in the SoC which is required by the PHY. Let's add support for this PHY found in the at803x driver as it falls within the Qualcomm Atheros OUI. Signed-off-by: George Moussalem --- drivers/net/phy/qcom/Kconfig | 2 +- drivers/net/phy/qcom/at803x.c | 221 ++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 214 insertions(+), 9 deletions(-) diff --git a/drivers/net/phy/qcom/Kconfig b/drivers/net/phy/qcom/Kconfig index 570626cc8e14d3e6615f74a6377f0f7c9f723e89..84239e08a8dfa466b0a7b2a5ec724a168b692cd2 100644 --- a/drivers/net/phy/qcom/Kconfig +++ b/drivers/net/phy/qcom/Kconfig @@ -7,7 +7,7 @@ config AT803X_PHY select QCOM_NET_PHYLIB depends on REGULATOR help - Currently supports the AR8030, AR8031, AR8033, AR8035 model + Currently supports the AR8030, AR8031, AR8033, AR8035, IPQ5018 model config QCA83XX_PHY tristate "Qualcomm Atheros QCA833x PHYs" diff --git a/drivers/net/phy/qcom/at803x.c b/drivers/net/phy/qcom/at803x.c index 26350b962890b0321153d74758b13d817407d094..1e30ccbee74e6463be8db9a7819e5f2e7031ebab 100644 --- a/drivers/net/phy/qcom/at803x.c +++ b/drivers/net/phy/qcom/at803x.c @@ -7,19 +7,24 @@ * Author: Matus Ujhelyi */ -#include -#include -#include -#include +#include +#include +#include #include #include -#include -#include -#include -#include +#include +#include +#include #include +#include #include +#include +#include +#include +#include +#include #include +#include #include #include "qcom.h" @@ -96,6 +101,8 @@ #define ATH8035_PHY_ID 0x004dd072 #define AT8030_PHY_ID_MASK 0xffffffef +#define IPQ5018_PHY_ID 0x004dd0c0 + #define QCA9561_PHY_ID 0x004dd042 #define AT803X_PAGE_FIBER 0 @@ -108,6 +115,46 @@ /* disable hibernation mode */ #define AT803X_DISABLE_HIBERNATION_MODE BIT(2) +#define IPQ5018_PHY_FIFO_CONTROL 0x19 +#define IPQ5018_PHY_FIFO_RESET GENMASK(1, 0) + +#define IPQ5018_PHY_DEBUG_EDAC 0x4380 +#define IPQ5018_PHY_MMD1_MDAC 0x8100 +#define IPQ5018_PHY_DAC_MASK GENMASK(15, 8) + +#define IPQ5018_PHY_MMD1_MSE_THRESH1 0x1000 +#define IPQ5018_PHY_MMD1_MSE_THRESH2 0x1001 +#define IPQ5018_PHY_MMD3_AZ_CTRL1 0x8008 +#define IPQ5018_PHY_MMD3_AZ_CTRL2 0x8009 +#define IPQ5018_PHY_MMD3_CDT_THRESH_CTRL3 0x8074 +#define IPQ5018_PHY_MMD3_CDT_THRESH_CTRL4 0x8075 +#define IPQ5018_PHY_MMD3_CDT_THRESH_CTRL5 0x8076 +#define IPQ5018_PHY_MMD3_CDT_THRESH_CTRL6 0x8077 +#define IPQ5018_PHY_MMD3_CDT_THRESH_CTRL7 0x8078 +#define IPQ5018_PHY_MMD3_CDT_THRESH_CTRL9 0x807a +#define IPQ5018_PHY_MMD3_CDT_THRESH_CTRL13 0x807e +#define IPQ5018_PHY_MMD3_CDT_THRESH_CTRL14 0x807f + +#define IPQ5018_PHY_MMD1_MSE_THRESH1_VAL 0xf1 +#define IPQ5018_PHY_MMD1_MSE_THRESH2_VAL 0x1f6 +#define IPQ5018_PHY_MMD3_AZ_CTRL1_VAL 0x7880 +#define IPQ5018_PHY_MMD3_AZ_CTRL2_VAL 0xc8 +#define IPQ5018_PHY_MMD3_CDT_THRESH_CTRL3_VAL 0xc040 +#define IPQ5018_PHY_MMD3_CDT_THRESH_CTRL4_VAL 0xa060 +#define IPQ5018_PHY_MMD3_CDT_THRESH_CTRL5_VAL 0xc040 +#define IPQ5018_PHY_MMD3_CDT_THRESH_CTRL6_VAL 0xa060 +#define IPQ5018_PHY_MMD3_CDT_THRESH_CTRL7_VAL 0xc24c +#define IPQ5018_PHY_MMD3_CDT_THRESH_CTRL9_VAL 0xc060 +#define IPQ5018_PHY_MMD3_CDT_THRESH_CTRL13_VAL 0xb060 +#define IPQ5018_PHY_MMD3_NEAR_ECHO_THRESH_VAL 0x90b0 + +#define IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE 0x1 +#define IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_MASK GENMASK(7, 4) +#define IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_DEFAULT 0x50 +#define IPQ5018_PHY_DEBUG_ANA_DAC_FILTER 0xa080 + +#define IPQ5018_TCSR_ETH_LDO_READY BIT(0) + MODULE_DESCRIPTION("Qualcomm Atheros AR803x PHY driver"); MODULE_AUTHOR("Matus Ujhelyi"); MODULE_LICENSE("GPL"); @@ -133,6 +180,14 @@ struct at803x_context { u16 led_control; }; +struct ipq5018_priv { + int num_clks; + struct clk_bulk_data *clks; + struct reset_control *rst; + u32 mdac; + u32 edac; +}; + static int at803x_write_page(struct phy_device *phydev, int page) { int mask; @@ -987,6 +1042,142 @@ static int at8035_probe(struct phy_device *phydev) return at8035_parse_dt(phydev); } +static inline int ipq5018_cmnblk_enable(struct device *dev) +{ + unsigned int offset; + struct regmap *tcsr; + + tcsr = syscon_regmap_lookup_by_phandle_args(dev->of_node, "qca,eth-ldo-ready", + 1, &offset); + if (IS_ERR(tcsr)) + return PTR_ERR(tcsr); + + return regmap_set_bits(tcsr, offset, IPQ5018_TCSR_ETH_LDO_READY); +} + +static int ipq5018_cable_test_start(struct phy_device *phydev) +{ + phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_MMD3_CDT_THRESH_CTRL3, + IPQ5018_PHY_MMD3_CDT_THRESH_CTRL3_VAL); + phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_MMD3_CDT_THRESH_CTRL4, + IPQ5018_PHY_MMD3_CDT_THRESH_CTRL4_VAL); + phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_MMD3_CDT_THRESH_CTRL5, + IPQ5018_PHY_MMD3_CDT_THRESH_CTRL5_VAL); + phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_MMD3_CDT_THRESH_CTRL6, + IPQ5018_PHY_MMD3_CDT_THRESH_CTRL6_VAL); + phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_MMD3_CDT_THRESH_CTRL7, + IPQ5018_PHY_MMD3_CDT_THRESH_CTRL7_VAL); + phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_MMD3_CDT_THRESH_CTRL9, + IPQ5018_PHY_MMD3_CDT_THRESH_CTRL9_VAL); + phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_MMD3_CDT_THRESH_CTRL13, + IPQ5018_PHY_MMD3_CDT_THRESH_CTRL13_VAL); + phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_MMD3_CDT_THRESH_CTRL3, + IPQ5018_PHY_MMD3_NEAR_ECHO_THRESH_VAL); + + /* we do all the (time consuming) work later */ + return 0; +} + +static int ipq5018_config_init(struct phy_device *phydev) +{ + struct ipq5018_priv *priv = phydev->priv; + u16 val = 0; + + /* + * set LDO efuse: first temporarily store ANA_DAC_FILTER value from + * debug register as it will be reset once the ANA_LDO_EFUSE register + * is written to + */ + val = at803x_debug_reg_read(phydev, IPQ5018_PHY_DEBUG_ANA_DAC_FILTER); + at803x_debug_reg_mask(phydev, IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE, + IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_MASK, + IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_DEFAULT); + at803x_debug_reg_write(phydev, IPQ5018_PHY_DEBUG_ANA_DAC_FILTER, val); + + /* set 8023AZ CTRL values */ + phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_MMD3_AZ_CTRL1, + IPQ5018_PHY_MMD3_AZ_CTRL1_VAL); + phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_MMD3_AZ_CTRL2, + IPQ5018_PHY_MMD3_AZ_CTRL2_VAL); + + /* set MSE threshold values */ + phy_write_mmd(phydev, MDIO_MMD_PMAPMD, IPQ5018_PHY_MMD1_MSE_THRESH1, + IPQ5018_PHY_MMD1_MSE_THRESH1_VAL); + phy_write_mmd(phydev, MDIO_MMD_PMAPMD, IPQ5018_PHY_MMD1_MSE_THRESH2, + IPQ5018_PHY_MMD1_MSE_THRESH2_VAL); + + if (priv->mdac && priv->edac) { + /* setting MDAC (Multi-level Digital-to-Analog Converter) in MMD1 */ + phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, IPQ5018_PHY_MMD1_MDAC, + IPQ5018_PHY_DAC_MASK, priv->mdac); + + /* setting EDAC (Error-detection and Correction) in debug register */ + at803x_debug_reg_mask(phydev, IPQ5018_PHY_DEBUG_EDAC, + IPQ5018_PHY_DAC_MASK, priv->edac); + } + + return 0; +} + +static void ipq5018_link_change_notify(struct phy_device *phydev) +{ + mdiobus_modify_changed(phydev->mdio.bus, phydev->mdio.addr, + IPQ5018_PHY_FIFO_CONTROL, IPQ5018_PHY_FIFO_RESET, + phydev->link ? IPQ5018_PHY_FIFO_RESET : 0); +} + +static int ipq5018_probe(struct phy_device *phydev) +{ + struct device *dev = &phydev->mdio.dev; + struct ipq5018_priv *priv; + u32 mdac, edac = 0; + int ret, cnt; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + /* PHY DAC values are optional and only set in a PHY to PHY link architecture */ + cnt = of_property_count_u32_elems(dev->of_node, "qca,dac"); + if (cnt == 2) { + ret = of_property_read_u32_index(dev->of_node, "qca,dac", 0, &mdac); + if (!ret) + priv->mdac = mdac; + + ret = of_property_read_u32_index(dev->of_node, "qca,dac", 1, &edac); + if (!ret) + priv->edac = edac; + } + + ret = ipq5018_cmnblk_enable(dev); + if (ret) + return dev_err_probe(dev, ret, + "Failed to enable LDO controller to CMN BLK"); + + priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks); + if (priv->num_clks < 0) + return dev_err_probe(dev, priv->num_clks, + "failed to acquire clocks\n"); + + ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks); + if (ret) + return dev_err_probe(dev, ret, + "failed to enable clocks\n"); + + priv->rst = devm_reset_control_array_get_exclusive(dev); + if (IS_ERR_OR_NULL(priv->rst)) + return dev_err_probe(dev, PTR_ERR(priv->rst), + "failed to acquire reset\n"); + + ret = reset_control_reset(priv->rst); + if (ret) + return dev_err_probe(dev, ret, "failed to reset\n"); + + phydev->priv = priv; + + return 0; +} + static struct phy_driver at803x_driver[] = { { /* Qualcomm Atheros AR8035 */ @@ -1078,6 +1269,19 @@ static struct phy_driver at803x_driver[] = { .read_status = at803x_read_status, .soft_reset = genphy_soft_reset, .config_aneg = at803x_config_aneg, +}, { + PHY_ID_MATCH_EXACT(IPQ5018_PHY_ID), + .name = "Qualcomm Atheros IPQ5018 internal PHY", + .flags = PHY_IS_INTERNAL | PHY_POLL_CABLE_TEST, + .probe = ipq5018_probe, + .config_init = ipq5018_config_init, + .link_change_notify = ipq5018_link_change_notify, + .read_status = at803x_read_status, + .config_intr = at803x_config_intr, + .handle_interrupt = at803x_handle_interrupt, + .cable_test_start = ipq5018_cable_test_start, + .cable_test_get_status = qca808x_cable_test_get_status, + .soft_reset = genphy_soft_reset, }, { /* Qualcomm Atheros QCA9561 */ PHY_ID_MATCH_EXACT(QCA9561_PHY_ID), @@ -1104,6 +1308,7 @@ static const struct mdio_device_id __maybe_unused atheros_tbl[] = { { PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) }, { PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) }, { PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) }, + { PHY_ID_MATCH_EXACT(IPQ5018_PHY_ID) }, { PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) }, { } }; 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Sun, 25 May 2025 17:56:08 +0000 (UTC) From: George Moussalem via B4 Relay Date: Sun, 25 May 2025 21:56:07 +0400 Subject: [PATCH 4/5] arm64: dts: qcom: ipq5018: add MDIO buses Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250525-ipq5018-ge-phy-v1-4-ddab8854e253@outlook.com> References: <20250525-ipq5018-ge-phy-v1-0-ddab8854e253@outlook.com> In-Reply-To: <20250525-ipq5018-ge-phy-v1-0-ddab8854e253@outlook.com> To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, George Moussalem X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748195765; l=1458; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=4Z6dvq+B+YexBDa/RxyvWcr+v3oZkqxqlrrl5K8MHDY=; b=gI1hk2iJGzZU8JpoiAL9oggKCV52OlHnYhuWvf+AX1/w5yZ+9vaGGcB8nwoYlz+ItajE/XkkA CBxrn0CycT7CGWGhbsxGTsG3hi+PdMujBU3PEpGGyqpAdfZEVlb0iUp X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem IPQ5018 contains two mdio buses of which one bus is used to control the SoC's internal GE PHY, while the other bus is connected to external PHYs or switches. There's already support for IPQ5018 in the mdio-ipq4019 driver, so let's simply add the mdio nodes for them. Signed-off-by: George Moussalem --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi index 130360014c5e14c778e348d37e601f60325b0b14..03ebc3e305b267c98a034c41ce47a39269afce75 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -182,6 +182,30 @@ pcie0_phy: phy@86000 { status = "disabled"; }; + mdio0: mdio@88000 { + compatible = "qcom,ipq5018-mdio"; + reg = <0x00088000 0x64>; + #address-cells = <1>; + #size-cells = <0>; + + clocks = <&gcc GCC_MDIO0_AHB_CLK>; + clock-names = "gcc_mdio_ahb_clk"; + + status = "disabled"; + }; + + mdio1: mdio@90000 { + compatible = "qcom,ipq5018-mdio"; + reg = <0x00090000 0x64>; + #address-cells = <1>; + #size-cells = <0>; + + clocks = <&gcc GCC_MDIO1_AHB_CLK>; + clock-names = "gcc_mdio_ahb_clk"; + + status = "disabled"; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,ipq5018-tlmm"; reg = <0x01000000 0x300000>; From patchwork Sun May 25 17:56:08 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: George Moussalem via B4 Relay X-Patchwork-Id: 892810 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DF93425C70D; Sun, 25 May 2025 17:56:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748195769; cv=none; b=H8kkMOJQZK1X287AaLWzoXhr4cyr8RQ4topbUlucnN458f8WXwHi8jjn9WyQZiZ6AH/Y5lkdsUG7wTlBOCkhIQ+b+bL+g4DNvw71bxLyN5siikEcsfeye27ffKEr/Nl9tu3xFwNy1yDoF+Nu7KzPNLGc5amA1IIiJw6WeAA46ZA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748195769; c=relaxed/simple; bh=9A/6O9r2IqeLYzOFaVCEJKjY9Ul0YdWsU/rVzaX6qCc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=k54rlP0itJhXV5gFHrKflsdZbAe/mhnr+yHov9HbhR+nRhAvGyZijiMI1xZYiUD26XNrvPKepuBAOcfDG7hyL899zlBipMeJPvgfB2zqHxbQkWRT9NHKnfYje3IsdN91ISrngEqy7d2Y4OCzKPuqceFNzUZFblMYEu9p8z0JOoQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=BSfbwS1+; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="BSfbwS1+" Received: by smtp.kernel.org (Postfix) with ESMTPS id 570D3C4CEFA; Sun, 25 May 2025 17:56:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1748195768; bh=9A/6O9r2IqeLYzOFaVCEJKjY9Ul0YdWsU/rVzaX6qCc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=BSfbwS1+Z6WZKLQFpUmLvoXUwMsG9ZiYzfdy1Galm+2fkh0Zv97THsbe0HFw60iib GKS7NneNIYYOKPnNczhhCOQS9IfZHaIRiF8tavW1aPmGLQEicBxN7IS04jZF4NKUdP P8Rpip7Oz5rPiUSlJqxa02aRI/mmfzYNWKMhI0/R+La+3PB6vRAfV4uka3rl0WSn5x RBCRm0+BDQevps0HTt5xNBI6JJcdZRiGZ//uF7u31ddtiNU5hQHMPPk04ZcCBFgaR5 PVcuJQqeUZFhh1rCd8R4zdimojkVMp4TdDlpPlSTpAdNa+GP3+6icVcgtREvdW9Nhq ZgwdSCgMMqNiw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4D18FC54FB3; Sun, 25 May 2025 17:56:08 +0000 (UTC) From: George Moussalem via B4 Relay Date: Sun, 25 May 2025 21:56:08 +0400 Subject: [PATCH 5/5] arm64: dts: qcom: ipq5018: Add GE PHY to internal mdio bus Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250525-ipq5018-ge-phy-v1-5-ddab8854e253@outlook.com> References: <20250525-ipq5018-ge-phy-v1-0-ddab8854e253@outlook.com> In-Reply-To: <20250525-ipq5018-ge-phy-v1-0-ddab8854e253@outlook.com> To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, George Moussalem X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748195765; l=1843; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=RbZYI9mHUjINGh38wXyVEQGgEtjNvQeZPMy+hpynOhA=; b=VYUp3FjEr6voXpngVWA+ruIyKayYUaXPmgTAd4U/eODjiXYYjWK3ETaw/TxwWWlHt2kUfaiox 8HhdPvf0hFaCND7OBVCC0uXcmYJy+ASmjLbH4aV7OY1jhuVkTc4GNSZ X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem The IPQ5018 SoC contains an internal GE PHY, always at phy address 7. As such, let's add the GE PHY node to the SoC dtsi. In addition, the GE PHY outputs both the RX and TX clocks to the GCC which gate controls them and routes them back to the PHY itself. So let's create two DT fixed clocks and register them in the GCC node. Signed-off-by: George Moussalem --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 27 +++++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi index 03ebc3e305b267c98a034c41ce47a39269afce75..ff2de44f9b85993fb2d426f85676f7d54c5cf637 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -16,6 +16,18 @@ / { #size-cells = <2>; clocks { + gephy_rx_clk: gephy-rx-clk { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + #clock-cells = <0>; + }; + + gephy_tx_clk: gephy-tx-clk { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + #clock-cells = <0>; + }; + sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -192,6 +204,17 @@ mdio0: mdio@88000 { clock-names = "gcc_mdio_ahb_clk"; status = "disabled"; + + ge_phy: ethernet-phy@7 { + reg = <7>; + + clocks = <&gcc GCC_GEPHY_RX_CLK>, + <&gcc GCC_GEPHY_TX_CLK>; + + resets = <&gcc GCC_GEPHY_MISC_ARES>; + + qca,eth-ldo-ready = <&tcsr 0x105c4>; + }; }; mdio1: mdio@90000 { @@ -232,8 +255,8 @@ gcc: clock-controller@1800000 { <&pcie0_phy>, <&pcie1_phy>, <0>, - <0>, - <0>, + <&gephy_rx_clk>, + <&gephy_tx_clk>, <0>, <0>; #clock-cells = <1>;