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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a4cfbf2644sm7294056f8f.59.2025.05.26.11.06.04 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 26 May 2025 11:06:04 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: John Snow , Gerd Hoffmann , Jiaxun Yang , Laurent Vivier , qemu-block@nongnu.org, Fabiano Rosas , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [RFC PATCH 1/2] hw/ide/ahci: Introduce ahci_reset_delayed() and ahci_reset_complete() Date: Mon, 26 May 2025 20:05:57 +0200 Message-ID: <20250526180558.65613-2-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250526180558.65613-1-philmd@linaro.org> References: <20250526180558.65613-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org AHCI reset is not instantaneous in physical world, and software might poll the reset bits of port and host control registers to detect completion (see chapter 14 of AHCI spec). In preparation of adding a timed reset, split ahci_reset() as ahci_reset_delayed() which keeps the reset bits and ahci_reset_complete() which resets them. No logical changes so far. Signed-off-by: Philippe Mathieu-Daudé --- hw/ide/ahci.c | 31 ++++++++++++++++++++++++++++--- hw/ide/trace-events | 1 + 2 files changed, 29 insertions(+), 3 deletions(-) diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c index 1303c21cb70..7e586c7a0a4 100644 --- a/hw/ide/ahci.c +++ b/hw/ide/ahci.c @@ -46,6 +46,7 @@ static bool ahci_map_clb_address(AHCIDevice *ad); static bool ahci_map_fis_address(AHCIDevice *ad); static void ahci_unmap_clb_address(AHCIDevice *ad); static void ahci_unmap_fis_address(AHCIDevice *ad); +static void ahci_reset_delayed(AHCIState *s, bool immediate); static const char *AHCIHostReg_lookup[AHCI_HOST_REG__COUNT] = { [AHCI_HOST_REG_CAP] = "CAP", @@ -1623,7 +1624,22 @@ void ahci_uninit(AHCIState *s) g_free(s->dev); } -void ahci_reset(AHCIState *s) +static void ahci_reset_complete(void *opaque) +{ + AHCIState *s = opaque; + + trace_ahci_reset_done(s); + + for (unsigned i = 0; i < s->ports; i++) { + AHCIPortRegs *pr; + + pr = &s->dev[i].port_regs; + pr->cmd &= ~PORT_CMD_LIST_ON; + } + s->control_regs.ghc &= ~HOST_CTL_RESET; +} + +static void ahci_reset_delayed(AHCIState *s, bool immediate) { AHCIPortRegs *pr; int i; @@ -1639,16 +1655,25 @@ void ahci_reset(AHCIState *s) * * We set HOST_CAP_AHCI so we must enable AHCI at reset. */ - s->control_regs.ghc = HOST_CTL_AHCI_EN; + s->control_regs.ghc = HOST_CTL_RESET | HOST_CTL_AHCI_EN; for (i = 0; i < s->ports; i++) { pr = &s->dev[i].port_regs; pr->irq_stat = 0; pr->irq_mask = 0; pr->scr_ctl = 0; - pr->cmd = PORT_CMD_SPIN_UP | PORT_CMD_POWER_ON; + pr->cmd = PORT_CMD_SPIN_UP | PORT_CMD_POWER_ON | PORT_CMD_LIST_ON; ahci_reset_port(s, i); } + + if (immediate) { + ahci_reset_complete(s); + } +} + +void ahci_reset(AHCIState *s) +{ + ahci_reset_delayed(s, false); } static const VMStateDescription vmstate_ncq_tfs = { diff --git a/hw/ide/trace-events b/hw/ide/trace-events index 57042cafddc..979145c58b8 100644 --- a/hw/ide/trace-events +++ b/hw/ide/trace-events @@ -82,6 +82,7 @@ ahci_mem_write_host(void *s, unsigned size, const char *reg, uint64_t addr, uint ahci_mem_write_unimpl(void *s, unsigned size, uint64_t addr, uint64_t val) "ahci(%p): write%u to unknown register 0x%"PRIx64": 0x%016"PRIx64 ahci_set_signature(void *s, int port, uint8_t nsector, uint8_t sector, uint8_t lcyl, uint8_t hcyl, uint32_t sig) "ahci(%p)[%d]: set signature sector:0x%02x nsector:0x%02x lcyl:0x%02x hcyl:0x%02x (cumulatively: 0x%08x)" ahci_reset_port(void *s, int port) "ahci(%p)[%d]: reset port" +ahci_reset_done(void *s) "ahci(%p): reset done" ahci_unmap_fis_address_null(void *s, int port) "ahci(%p)[%d]: Attempt to unmap NULL FIS address" ahci_unmap_clb_address_null(void *s, int port) "ahci(%p)[%d]: Attempt to unmap NULL CLB address" ahci_populate_sglist(void *s, int port) "ahci(%p)[%d]" From patchwork Mon May 26 18:05:58 2025 Content-Type: text/plain; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a4dc1172ecsm2684499f8f.48.2025.05.26.11.06.08 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 26 May 2025 11:06:09 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: John Snow , Gerd Hoffmann , Jiaxun Yang , Laurent Vivier , qemu-block@nongnu.org, Fabiano Rosas , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [RFC PATCH 2/2] hw/ide/ahci: Delay a bit before completing reset Date: Mon, 26 May 2025 20:05:58 +0200 Message-ID: <20250526180558.65613-3-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250526180558.65613-1-philmd@linaro.org> References: <20250526180558.65613-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Give few milliseconds to (emulated) hardware to complete its reset sequence. The intent is to have this model better match hardware, reducing firmware bugs "works in QEMU but not in real world" such https://github.com/FlyGoat/csmwrap/issues/14. Reported-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daudé --- include/hw/ide/ahci.h | 1 + hw/ide/ahci.c | 39 +++++++++++++++++++++++++++++++++++++-- tests/qtest/ahci-test.c | 4 ++++ 3 files changed, 42 insertions(+), 2 deletions(-) diff --git a/include/hw/ide/ahci.h b/include/hw/ide/ahci.h index cd07b87811b..82617835195 100644 --- a/include/hw/ide/ahci.h +++ b/include/hw/ide/ahci.h @@ -46,6 +46,7 @@ typedef struct AHCIState { uint32_t ports; qemu_irq irq; AddressSpace *as; + QEMUTimer *reset_timer; } AHCIState; diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c index 7e586c7a0a4..cf1c5d3f3db 100644 --- a/hw/ide/ahci.c +++ b/hw/ide/ahci.c @@ -28,6 +28,7 @@ #include "qemu/error-report.h" #include "qemu/log.h" #include "qemu/main-loop.h" +#include "qemu/timer.h" #include "system/block-backend.h" #include "system/dma.h" #include "ahci-internal.h" @@ -47,6 +48,7 @@ static bool ahci_map_fis_address(AHCIDevice *ad); static void ahci_unmap_clb_address(AHCIDevice *ad); static void ahci_unmap_fis_address(AHCIDevice *ad); static void ahci_reset_delayed(AHCIState *s, bool immediate); +static void ahci_reset_complete(void *opaque); static const char *AHCIHostReg_lookup[AHCI_HOST_REG__COUNT] = { [AHCI_HOST_REG_CAP] = "CAP", @@ -459,7 +461,7 @@ static void ahci_mem_write(void *opaque, hwaddr addr, break; case AHCI_HOST_REG_CTL: /* R/W */ if (val & HOST_CTL_RESET) { - ahci_reset(s); + ahci_reset_delayed(s, true); } else { s->control_regs.ghc = (val & 0x3) | HOST_CTL_AHCI_EN; ahci_check_irq(s); @@ -1591,6 +1593,7 @@ void ahci_realize(AHCIState *s, DeviceState *qdev, AddressSpace *as) s->as = as; assert(s->ports > 0); s->dev = g_new0(AHCIDevice, s->ports); + s->reset_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, ahci_reset_complete, s); ahci_reg_init(s); irqs = qemu_allocate_irqs(ahci_irq_set, s, s->ports); for (i = 0; i < s->ports; i++) { @@ -1622,8 +1625,12 @@ void ahci_uninit(AHCIState *s) } g_free(s->dev); + + timer_free(s->reset_timer); } +#define AHCI_RESET_DELAY_MS 69 /* Arbitrary value less than 500 ms */ + static void ahci_reset_complete(void *opaque) { AHCIState *s = opaque; @@ -1667,7 +1674,11 @@ static void ahci_reset_delayed(AHCIState *s, bool immediate) } if (immediate) { + timer_del(s->reset_timer); ahci_reset_complete(s); + } else if (!timer_pending(s->reset_timer)) { + timer_mod(s->reset_timer, + qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + AHCI_RESET_DELAY_MS); } } @@ -1676,6 +1687,24 @@ void ahci_reset(AHCIState *s) ahci_reset_delayed(s, false); } +static bool ahci_timer_needed(void *opaque) +{ + AHCIState *s = opaque; + + return timer_pending(s->reset_timer); +} + +static const VMStateDescription vmstate_ahci_timer = { + .name = "ahci/reset_timer", + .version_id = 1, + .minimum_version_id = 1, + .needed = ahci_timer_needed, + .fields = (const VMStateField[]) { + VMSTATE_TIMER_PTR(reset_timer, AHCIState), + VMSTATE_END_OF_LIST() + } +}; + static const VMStateDescription vmstate_ncq_tfs = { .name = "ncq state", .version_id = 1, @@ -1734,7 +1763,9 @@ static int ahci_state_post_load(void *opaque, int version_id) ad = &s->dev[i]; pr = &ad->port_regs; - if (!(pr->cmd & PORT_CMD_START) && (pr->cmd & PORT_CMD_LIST_ON)) { + if (timer_pending(s->reset_timer)) { + /* Reset in progress */ + } else if (!(pr->cmd & PORT_CMD_START) && (pr->cmd & PORT_CMD_LIST_ON)) { error_report("AHCI: DMA engine should be off, but status bit " "indicates it is still running."); return -1; @@ -1823,6 +1854,10 @@ const VMStateDescription vmstate_ahci = { VMSTATE_UINT32_EQUAL(ports, AHCIState, NULL), VMSTATE_END_OF_LIST() }, + .subsections = (const VMStateDescription * const []) { + &vmstate_ahci_timer, + NULL + } }; void ahci_ide_create_devs(AHCIState *ahci, DriveInfo **hd) diff --git a/tests/qtest/ahci-test.c b/tests/qtest/ahci-test.c index e8aabfc13f5..4389aaa7f70 100644 --- a/tests/qtest/ahci-test.c +++ b/tests/qtest/ahci-test.c @@ -40,6 +40,8 @@ #define TEST_IMAGE_SIZE_MB_LARGE (200 * 1024) #define TEST_IMAGE_SIZE_MB_SMALL 64 +#define AHCI_RESET_TIMEOUT_NS (500 * 1000 * 1000) + /*** Globals ***/ static char *tmp_path; static char *debug_path; @@ -483,6 +485,8 @@ static void ahci_test_hba_spec(AHCIQState *ahci) g_assert(ahci != NULL); + qtest_clock_step(ahci->parent->qts, AHCI_RESET_TIMEOUT_NS); + /* * Note that the AHCI spec does expect the BIOS to set up a few things: * CAP.SSS - Support for staggered spin-up (t/f)