From patchwork Mon May 26 14:40:17 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ze Huang X-Patchwork-Id: 892910 Received: from mail-m155101.qiye.163.com (mail-m155101.qiye.163.com [101.71.155.101]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6BBFC211479; Mon, 26 May 2025 14:40:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=101.71.155.101 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748270442; cv=none; b=cgTAtNZB/9yVEyWHTrXOiow/chQl4yU1DXwoUL1F6L3FEk5XJnCapbY8T0p/iIQN74QpfW2MeN5EMtDjDhFbjWeu18D2mMiVxLxohqNoV0NiZfAxfLrtoEozzWpO7Yd9NuldsNqdxvzFj0Up3WZISff05HcODfcyNb07I3NdZps= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748270442; c=relaxed/simple; bh=bwc4ehrUUb5yMr61UXhl319IcCCrFAV6pb82Pcs8dqI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=W7ziH6k8oH0kDczRtw4viknqFKZHSwaGOaAdj/cvytdhCQYiGvtwvFamMPNfjVNVVo8/v2pkgFprz6pccC8JMJPpgxBIIAHiIQYb0m0Y2s6H8v8uA+iPC05a8C7mNXrF/pJwWZwIoqoTPOgd0Q013PF0dWBVorHhR4zq3xSOWxk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=whut.edu.cn; spf=pass smtp.mailfrom=whut.edu.cn; arc=none smtp.client-ip=101.71.155.101 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=whut.edu.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=whut.edu.cn Received: from [127.0.0.1] (gy-adaptive-ssl-proxy-3-entmail-virt135.gy.ntes [27.18.99.37]) by smtp.qiye.163.com (Hmail) with ESMTP id 16709a323; Mon, 26 May 2025 22:40:30 +0800 (GMT+08:00) From: Ze Huang Date: Mon, 26 May 2025 22:40:17 +0800 Subject: [PATCH v4 1/4] dt-bindings: usb: dwc3: add support for SpacemiT K1 Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250526-b4-k1-dwc3-v3-v4-1-63e4e525e5cb@whut.edu.cn> References: <20250526-b4-k1-dwc3-v3-v4-0-63e4e525e5cb@whut.edu.cn> In-Reply-To: <20250526-b4-k1-dwc3-v3-v4-0-63e4e525e5cb@whut.edu.cn> To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Thinh Nguyen , Philipp Zabel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, Ze Huang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748270423; l=3650; i=huangze@whut.edu.cn; s=20250325; h=from:subject:message-id; bh=bwc4ehrUUb5yMr61UXhl319IcCCrFAV6pb82Pcs8dqI=; b=4WUvEDLz9hoMoYvR0A1q4dM0FNou2Q5lu6Ek6vmgD1+ATlDBk7yfp6NCgACDGnB60kk7VvTRG eaVF9rrPeW1Cq09qfQ6iamBFp4Q5HTDKSZKZ8w7Xk2le1X3N/dTs4ZM X-Developer-Key: i=huangze@whut.edu.cn; a=ed25519; pk=C3zfn/kH6oMJickaXBa8dxTZO68EBiD93F+tAenboRA= X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVkZH0gaVktCTUlPGR0eQkJLTVYeHw5VEwETFhoSFy QUDg9ZV1kYEgtZQVlJTFVKQ1VCQlVITFlXWRYaDxIVHRRZQVlPS0hVSktJQk1KSlVKS0tVS1kG X-HM-Tid: 0a970d09b8fc03a1kunm5f56ec4c12e05 X-HM-MType: 10 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6MTI6GDo4TzE3PgwWGisYFDk2 PzgwChZVSlVKTE9DSUxLT0hNQ0tLVTMWGhIXVRMOGhUcAR47DBMOD1UeHw5VGBVFWVdZEgtZQVlJ TFVKQ1VCQlVITFlXWQgBWUFOSkxPNwY+ Add support for the USB 3.0 Dual-Role Device (DRD) controller embedded in the SpacemiT K1 SoC. The controller is based on the Synopsys DesignWare Core USB 3 (DWC3) IP, supporting USB3.0 host mode and USB 2.0 DRD mode. Signed-off-by: Ze Huang Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/usb/spacemit,k1-dwc3.yaml | 116 +++++++++++++++++++++ 1 file changed, 116 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml new file mode 100644 index 0000000000000000000000000000000000000000..bba3fc1c020500383b1256a97648be3f626c7602 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml @@ -0,0 +1,116 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/spacemit,k1-dwc3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SpacemiT K1 SuperSpeed DWC3 USB SoC Controller + +maintainers: + - Ze Huang + +description: | + The SpacemiT K1 embeds a DWC3 USB IP Core which supports Host functions + for USB 3.0 and DRD for USB 2.0. + + Key features: + - USB3.0 SuperSpeed and USB2.0 High/Full/Low-Speed support + - Supports low-power modes (USB2.0 suspend, USB3.0 U1/U2/U3) + - Internal DMA controller and flexible endpoint FIFO sizing + + Communication Interface: + - Use of PIPE3 (125MHz) interface for USB3.0 PHY + - Use of UTMI+ (30/60MHz) interface for USB2.0 PHY + +allOf: + - $ref: snps,dwc3-common.yaml# + +properties: + compatible: + const: spacemit,k1-dwc3 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: usbdrd30 + + interconnects: + maxItems: 1 + description: + On SpacemiT K1, USB performs DMA through bus other than parent DT node. + The 'interconnects' property explicitly describes this path, ensuring + correct address translation. + + interconnect-names: + const: dma-mem + + interrupts: + maxItems: 1 + + phys: + items: + - description: phandle to USB2/HS PHY + - description: phandle to USB3/SS PHY + + phy-names: + items: + - const: usb2-phy + - const: usb3-phy + + resets: + maxItems: 1 + + vbus-supply: + description: A phandle to the regulator supplying the VBUS voltage. + +required: + - compatible + - reg + - clocks + - clock-names + - interconnects + - interconnect-names + - interrupts + - phys + - phy-names + - resets + +unevaluatedProperties: false + +examples: + - | + usb@c0a00000 { + compatible = "spacemit,k1-dwc3"; + reg = <0xc0a00000 0x10000>; + clocks = <&syscon_apmu 16>; + clock-names = "usbdrd30"; + interconnects = <&mbus0>; + interconnect-names = "dma-mem"; + interrupts = <125>; + phys = <&usb2phy>, <&usb3phy>; + phy-names = "usb2-phy", "usb3-phy"; + resets = <&syscon_apmu 8>; + vbus-supply = <&usb3_vbus>; + #address-cells = <1>; + #size-cells = <0>; + + hub_2_0: hub@1 { + compatible = "usb2109,2817"; + reg = <1>; + vdd-supply = <&usb3_vhub>; + peer-hub = <&hub_3_0>; + reset-gpios = <&gpio 3 28 1>; + }; + + hub_3_0: hub@2 { + compatible = "usb2109,817"; + reg = <2>; + vdd-supply = <&usb3_vhub>; + peer-hub = <&hub_2_0>; + reset-gpios = <&gpio 3 28 1>; + }; + }; From patchwork Mon May 26 14:40:18 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ze Huang X-Patchwork-Id: 892713 Received: from mail-m49197.qiye.163.com (mail-m49197.qiye.163.com [45.254.49.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CF606213236; 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dmarc=pass (p=none dis=none) header.from=whut.edu.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=whut.edu.cn Received: from [127.0.0.1] (gy-adaptive-ssl-proxy-3-entmail-virt135.gy.ntes [27.18.99.37]) by smtp.qiye.163.com (Hmail) with ESMTP id 16709a332; Mon, 26 May 2025 22:40:37 +0800 (GMT+08:00) From: Ze Huang Date: Mon, 26 May 2025 22:40:18 +0800 Subject: [PATCH v4 2/4] dt-bindings: soc: spacemit: Add K1 MBUS controller Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250526-b4-k1-dwc3-v3-v4-2-63e4e525e5cb@whut.edu.cn> References: <20250526-b4-k1-dwc3-v3-v4-0-63e4e525e5cb@whut.edu.cn> In-Reply-To: <20250526-b4-k1-dwc3-v3-v4-0-63e4e525e5cb@whut.edu.cn> To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Thinh Nguyen , Philipp Zabel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, Ze Huang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748270423; l=2263; i=huangze@whut.edu.cn; s=20250325; h=from:subject:message-id; bh=BH+M8S+LdjO6vILGDAHjXkmrs1lq+W5Vv7MqYlwP/g0=; b=mXuYbUjZP4VNczBinGSiUwmr+XM0tW9D6UVDvHbEPTMKTZBGwhdUEo3ZZ/ONnqaX0EurDsGm1 wL44DC+/un2BQ90TeHQNgj2x3DP1Zf6cDPfd/hyKI4H9ZyJFd1Zp/vl X-Developer-Key: i=huangze@whut.edu.cn; a=ed25519; pk=C3zfn/kH6oMJickaXBa8dxTZO68EBiD93F+tAenboRA= X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVlDGk9OVhlJSk4fGB9LTU9ITlYeHw5VEwETFhoSFy QUDg9ZV1kYEgtZQVlJTFVKQ1VCQlVITFlXWRYaDxIVHRRZQVlPS0hVSktJSEJLQ1VKS0tVSkJZBg ++ X-HM-Tid: 0a970d09d31703a1kunm5f56ec4c12e60 X-HM-MType: 10 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6PDY6OQw*CTErLgwNTzVJFDhR ME8aFAJVSlVKTE9DSUxLT09ISENLVTMWGhIXVRMOGhUcAR47DBMOD1UeHw5VGBVFWVdZEgtZQVlJ TFVKQ1VCQlVITFlXWQgBWUFITENNNwY+ Some devices on the SpacemiT K1 SoC perform DMA through a memory bus (MBUS) that is not their immediate parent in the device tree. This bus uses a different address mapping than the CPU. To express this topology properly, devices are expected to use the interconnects with name "dma-mem" to reference the MBUS controller. Signed-off-by: Ze Huang --- .../bindings/soc/spacemit/spacemit,k1-mbus.yaml | 55 ++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-mbus.yaml b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-mbus.yaml new file mode 100644 index 0000000000000000000000000000000000000000..533cf99dff689cf55a159118c32a676054294ffa --- /dev/null +++ b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-mbus.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/spacemit/spacemit,k1-mbus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SpacemiT Memory Bus controller + +maintainers: + - Ze Huang + +description: | + On the SpacemiT K1 SoC, some devices do not perform DMA through their + immediate parent node in the device tree. Instead, they access memory + through a separate memory bus (MBUS) that uses a different address + mapping from the CPU. + + To correctly describe the DMA path, such devices must reference the MBUS + controller through an interconnect with the reserved name "dma-mem". + +properties: + compatible: + const: spacemit,k1-mbus + + reg: + maxItems: 1 + + dma-ranges: + maxItems: 1 + + "#address-cells": true + + "#size-cells": true + + "#interconnect-cells": + const: 0 + +required: + - compatible + - reg + - dma-ranges + - "#interconnect-cells" + +additionalProperties: false + +examples: + - | + dram-controller@0 { + compatible = "spacemit,k1-mbus"; + reg = <0x00000000 0x80000000>; + dma-ranges = <0x00000000 0x00000000 0x80000000>; + #address-cells = <1>; + #size-cells = <1>; + #interconnect-cells = <0>; + }; From patchwork Mon May 26 14:40:19 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ze Huang X-Patchwork-Id: 892909 Received: from mail-m49198.qiye.163.com (mail-m49198.qiye.163.com [45.254.49.198]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7B7A42101BD; Mon, 26 May 2025 14:40:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.254.49.198 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748270455; cv=none; b=t9dhsyUXvjg0PfzKGxBrkYw/Gk7wbOYEoWWxsgeUv0x/w2pvGY4RINK5vKaQD2lD6z/N2ETnr30O4X6DoOq3odr0KQLYQot9gb/PYcA/MrYoyFPzty2pBHHeNwsiCMrJuk609mLK+HzEejxqR1tQ6XlpJZ2Z9t45p4R4TYevfZo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748270455; c=relaxed/simple; bh=Z5+l2LS4FLiuHcGP6xncYtlXScMGvhd7SS6ZusY5OmI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=a2puORKoDEC9yhY9G+T+VbZVGOgRRjdp/IaRm7NUMBYgFm+iFrtgB1z53DG3uOQ7pVHKfl93GeAk9IWKJdPhziuRBVJm4sEThSfSv9JTm7BuAdkY/hngUa20+mYVDjjmzAqQ+mLmw0M0QBYf5ZEdWmPUaK2e9Onil8pAnulI+Mc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=whut.edu.cn; spf=pass smtp.mailfrom=whut.edu.cn; arc=none smtp.client-ip=45.254.49.198 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=whut.edu.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=whut.edu.cn Received: from [127.0.0.1] (gy-adaptive-ssl-proxy-3-entmail-virt135.gy.ntes [27.18.99.37]) by smtp.qiye.163.com (Hmail) with ESMTP id 16709a338; Mon, 26 May 2025 22:40:43 +0800 (GMT+08:00) From: Ze Huang Date: Mon, 26 May 2025 22:40:19 +0800 Subject: [PATCH v4 3/4] usb: dwc3: add generic driver to support flattened DT Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250526-b4-k1-dwc3-v3-v4-3-63e4e525e5cb@whut.edu.cn> References: <20250526-b4-k1-dwc3-v3-v4-0-63e4e525e5cb@whut.edu.cn> In-Reply-To: <20250526-b4-k1-dwc3-v3-v4-0-63e4e525e5cb@whut.edu.cn> To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Thinh Nguyen , Philipp Zabel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, Ze Huang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748270423; l=6956; i=huangze@whut.edu.cn; s=20250325; h=from:subject:message-id; bh=Z5+l2LS4FLiuHcGP6xncYtlXScMGvhd7SS6ZusY5OmI=; b=8HN+deS9nwPP6UlNOEjqQZgejc+uNCtsoQU9+B/TWhqMOZSF4hhXe5IqzxA89JzLxFBcZKuQv KkjWqwuCfs6BJb2x1fPghnU9aWZkTK4SdNBSXK7ebxdyPRBw0Rw5D8M X-Developer-Key: i=huangze@whut.edu.cn; a=ed25519; pk=C3zfn/kH6oMJickaXBa8dxTZO68EBiD93F+tAenboRA= X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVlDQ0lIVk5DSE1IHh1NSU9IS1YeHw5VEwETFhoSFy QUDg9ZV1kYEgtZQVlJTFVKQ1VCQlVITFlXWRYaDxIVHRRZQVlPS0hVSktJQk1KSlVKS0tVS1kG X-HM-Tid: 0a970d09ec2803a1kunm5f56ec4c12ea5 X-HM-MType: 10 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6Mk06PRw*LDE2TQxNMDQuFDEq LxkKFCpVSlVKTE9DSUxLT05LSkJNVTMWGhIXVRMOGhUcAR47DBMOD1UeHw5VGBVFWVdZEgtZQVlJ TFVKQ1VCQlVITFlXWQgBWUFDT0NPNwY+ To support flattened dwc3 dt model and drop the glue layer, introduce the `dwc3-generic` driver. This enables direct binding of the DWC3 core driver and offers an alternative to the existing glue driver `dwc3-of-simple`. Signed-off-by: Ze Huang --- drivers/usb/dwc3/Kconfig | 9 ++ drivers/usb/dwc3/Makefile | 1 + drivers/usb/dwc3/dwc3-generic-plat.c | 189 +++++++++++++++++++++++++++++++++++ 3 files changed, 199 insertions(+) diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig index 310d182e10b50b253d7e5a51674806e6ec442a2a..082627f39c9726ee4e0c5f966c5bc454f5541c9a 100644 --- a/drivers/usb/dwc3/Kconfig +++ b/drivers/usb/dwc3/Kconfig @@ -118,6 +118,15 @@ config USB_DWC3_OF_SIMPLE Currently supports Xilinx and Qualcomm DWC USB3 IP. Say 'Y' or 'M' if you have one such device. +config USB_DWC3_GENERIC_PLAT + tristate "DWC3 Generic Platform Driver" + depends on OF && COMMON_CLK + default USB_DWC3 + help + Support USB3 functionality in simple SoC integrations. + Currently supports SpacemiT DWC USB3 IP. + Say 'Y' or 'M' if you have one such device. + config USB_DWC3_ST tristate "STMicroelectronics Platforms" depends on (ARCH_STI || COMPILE_TEST) && OF diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile index 830e6c9e5fe073c1f662ce34b6a4a2da34c407a2..96469e48ff9d189cc8d0b65e65424eae2158bcfe 100644 --- a/drivers/usb/dwc3/Makefile +++ b/drivers/usb/dwc3/Makefile @@ -57,3 +57,4 @@ obj-$(CONFIG_USB_DWC3_IMX8MP) += dwc3-imx8mp.o obj-$(CONFIG_USB_DWC3_XILINX) += dwc3-xilinx.o obj-$(CONFIG_USB_DWC3_OCTEON) += dwc3-octeon.o obj-$(CONFIG_USB_DWC3_RTK) += dwc3-rtk.o +obj-$(CONFIG_USB_DWC3_GENERIC_PLAT) += dwc3-generic-plat.o diff --git a/drivers/usb/dwc3/dwc3-generic-plat.c b/drivers/usb/dwc3/dwc3-generic-plat.c new file mode 100644 index 0000000000000000000000000000000000000000..8ff4626d324c40ecb52e115832c803fed7d38354 --- /dev/null +++ b/drivers/usb/dwc3/dwc3-generic-plat.c @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * dwc3-generic-plat.c - DesignWare USB3 generic platform driver + * + * Copyright (C) 2025 Ze Huang + * + * Inspired by dwc3-qcom.c and dwc3-of-simple.c + */ + +#include +#include +#include +#include +#include +#include +#include "glue.h" + +struct dwc3_generic { + struct device *dev; + struct dwc3 dwc; + struct clk_bulk_data *clks; + int num_clocks; + struct reset_control *resets; +}; + +static int dwc3_generic_probe(struct platform_device *pdev) +{ + struct dwc3_probe_data probe_data = {}; + struct device *dev = &pdev->dev; + struct dwc3_generic *dwc3; + struct resource *res; + int ret; + + dwc3 = devm_kzalloc(dev, sizeof(*dwc3), GFP_KERNEL); + if (!dwc3) + return -ENOMEM; + + dwc3->dev = dev; + + platform_set_drvdata(pdev, dwc3); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "missing memory resource\n"); + return -ENODEV; + } + + dwc3->resets = of_reset_control_array_get_optional_exclusive(dev->of_node); + if (IS_ERR(dwc3->resets)) + return dev_err_probe(dev, PTR_ERR(dwc3->resets), "failed to get reset\n"); + + ret = reset_control_assert(dwc3->resets); + if (ret) + return dev_err_probe(dev, ret, "failed to assert reset\n"); + + usleep_range(10, 1000); + + ret = reset_control_deassert(dwc3->resets); + if (ret) { + dev_err(dev, "failed to deassert reset\n"); + goto reset_assert; + } + + ret = clk_bulk_get_all(dwc3->dev, &dwc3->clks); + if (ret < 0) { + dev_err(dev, "failed to get clocks\n"); + goto reset_assert; + } + + dwc3->num_clocks = ret; + + ret = clk_bulk_prepare_enable(dwc3->num_clocks, dwc3->clks); + if (ret) { + dev_err(dev, "failed to enable clocks\n"); + goto reset_assert; + } + + dwc3->dwc.dev = dev; + probe_data.dwc = &dwc3->dwc; + probe_data.res = res; + probe_data.ignore_clocks_and_resets = true; + ret = dwc3_core_probe(&probe_data); + if (ret) { + dev_err(dev, "failed to register DWC3 Core\n"); + goto clk_disable; + } + + return 0; + +clk_disable: + clk_bulk_disable_unprepare(dwc3->num_clocks, dwc3->clks); + clk_bulk_put_all(dwc3->num_clocks, dwc3->clks); + +reset_assert: + reset_control_assert(dwc3->resets); + + return ret; +} + +static void dwc3_generic_remove(struct platform_device *pdev) +{ + struct dwc3_generic *dwc3 = platform_get_drvdata(pdev); + + dwc3_core_remove(&dwc3->dwc); + + clk_bulk_disable_unprepare(dwc3->num_clocks, dwc3->clks); + clk_bulk_put_all(dwc3->num_clocks, dwc3->clks); + + reset_control_assert(dwc3->resets); +} + +static int __maybe_unused dwc3_generic_suspend(struct device *dev) +{ + struct dwc3_generic *dwc3 = dev_get_drvdata(dev); + int ret; + + ret = dwc3_pm_suspend(&dwc3->dwc); + if (ret) + return ret; + + clk_bulk_disable_unprepare(dwc3->num_clocks, dwc3->clks); + + return 0; +} + +static int __maybe_unused dwc3_generic_resume(struct device *dev) +{ + struct dwc3_generic *dwc3 = dev_get_drvdata(dev); + int ret; + + ret = clk_bulk_prepare_enable(dwc3->num_clocks, dwc3->clks); + if (ret) + return ret; + + ret = dwc3_pm_resume(&dwc3->dwc); + if (ret) + return ret; + + return 0; +} + +static int __maybe_unused dwc3_generic_runtime_suspend(struct device *dev) +{ + struct dwc3_generic *dwc3 = dev_get_drvdata(dev); + + return dwc3_runtime_suspend(&dwc3->dwc); +} + +static int __maybe_unused dwc3_generic_runtime_resume(struct device *dev) +{ + struct dwc3_generic *dwc3 = dev_get_drvdata(dev); + + return dwc3_runtime_resume(&dwc3->dwc); +} + +static int __maybe_unused dwc3_generic_runtime_idle(struct device *dev) +{ + struct dwc3_generic *dwc3 = dev_get_drvdata(dev); + + return dwc3_runtime_idle(&dwc3->dwc); +} + +static const struct dev_pm_ops dwc3_generic_dev_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(dwc3_generic_suspend, dwc3_generic_resume) + SET_RUNTIME_PM_OPS(dwc3_generic_runtime_suspend, dwc3_generic_runtime_resume, + dwc3_generic_runtime_idle) +}; + +static const struct of_device_id dwc3_generic_of_match[] = { + { .compatible = "spacemit,k1-dwc3", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, dwc3_generic_of_match); + +static struct platform_driver dwc3_generic_driver = { + .probe = dwc3_generic_probe, + .remove = dwc3_generic_remove, + .driver = { + .name = "dwc3-generic-plat", + .of_match_table = dwc3_generic_of_match, +#ifdef CONFIG_PM_SLEEP + .pm = &dwc3_generic_dev_pm_ops, +#endif /* CONFIG_PM_SLEEP */ + }, +}; +module_platform_driver(dwc3_generic_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("DesignWare USB3 generic platform driver"); From patchwork Mon May 26 14:40:20 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ze Huang X-Patchwork-Id: 892712 Received: from mail-m49197.qiye.163.com (mail-m49197.qiye.163.com [45.254.49.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 69B2A212FB0; Mon, 26 May 2025 14:40:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.254.49.197 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748270463; cv=none; b=fNEdMaJTx1f8tPxFyT/rUeFHFXg4FpoML8ohbfQgB7MPQjgCd67pKViGJ0j3YQve14ZShQWu8Of10cwqkYub0lik1NHhlaxV+K0ifdT3Vsd0wj1xCyicgzI1AohL2ZM1Dyfef2+CxoBudhUcv6wBoTFIvHO5BncrH2hw6VrZIVA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748270463; c=relaxed/simple; bh=cGVbOqpUYlVjPJ9sdnL9JMn3K7BgmO8hSIFFZcC21rQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Fn2M1uhhvRKSQIaFGwtpd63L4vd4/t4fCgdh9ISDdOdoc+Gm0Qcqna3UhsQnARjvXBY88AcBrl0pqxdePJhj3iDFabdXphBkMkWYQw2Vc1pI+XfKydf+0al4n+fSy2Aq87uuSnVxLC0/oujhDoWtantaoPcXRSAOVdgFZ7RUyjA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=whut.edu.cn; spf=pass smtp.mailfrom=whut.edu.cn; arc=none smtp.client-ip=45.254.49.197 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=whut.edu.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=whut.edu.cn Received: from [127.0.0.1] (gy-adaptive-ssl-proxy-3-entmail-virt135.gy.ntes [27.18.99.37]) by smtp.qiye.163.com (Hmail) with ESMTP id 16709a33f; Mon, 26 May 2025 22:40:50 +0800 (GMT+08:00) From: Ze Huang Date: Mon, 26 May 2025 22:40:20 +0800 Subject: [PATCH v4 4/4] riscv: dts: spacemit: add usb3.0 support for K1 Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250526-b4-k1-dwc3-v3-v4-4-63e4e525e5cb@whut.edu.cn> References: <20250526-b4-k1-dwc3-v3-v4-0-63e4e525e5cb@whut.edu.cn> In-Reply-To: <20250526-b4-k1-dwc3-v3-v4-0-63e4e525e5cb@whut.edu.cn> To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Thinh Nguyen , Philipp Zabel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, Ze Huang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748270423; l=5426; i=huangze@whut.edu.cn; s=20250325; h=from:subject:message-id; bh=cGVbOqpUYlVjPJ9sdnL9JMn3K7BgmO8hSIFFZcC21rQ=; b=dvUL5idzS2fqYMvI0gmi9yeE8UN14gsHQUVnnAR5LvJGp5WR/4J8RqMrM/PWSx01FX6z+kN2K qehbIV1k72sAULbGHhGZM40nRnWqpDmugEUNRdZDvuBNm1VZGoKSshL X-Developer-Key: i=huangze@whut.edu.cn; a=ed25519; pk=C3zfn/kH6oMJickaXBa8dxTZO68EBiD93F+tAenboRA= X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVlDSBhIVkNPS00YSEMeGB9NGlYeHw5VEwETFhoSFy QUDg9ZV1kYEgtZQVlJTFVKQ1VCQlVITFlXWRYaDxIVHRRZQVlPS0hVSktJQk1KSlVKS0tVS1kG X-HM-Tid: 0a970d0a072803a1kunm5f56ec4c12f04 X-HM-MType: 10 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6Pz46FAw6QjEyOgw4CjYBFDcy EgMaCQ1VSlVKTE9DSUxLT05MTElPVTMWGhIXVRMOGhUcAR47DBMOD1UeHw5VGBVFWVdZEgtZQVlJ TFVKQ1VCQlVITFlXWQgBWUFNQk9NNwY+ Add USB 3.0 support for the SpacemiT K1 SoC, including the following components: - USB 2.0 PHY nodes - USB 3.0 combo PHY node - USB 3.0 host controller - USB 3.0 hub and vbus regulator (usb3_vhub, usb3_vbus) - DRAM interconnect node for USB DMA ("dma-mem") The `usb3_vbus` and `usb3_vhub` regulator node provides a fixed 5V supply to power the onboard USB 3.0 hub and usb vbus. On K1, some DMA transfers from devices to memory use separate buses with different DMA address translation rules from the parent node. We express this relationship through the interconnects node "dma-mem", similar to [1]. Link: https://lore.kernel.org/all/09e5e29a4c54ec7337e4e62e5d6001b69d92b103.1554108995.git-series.maxime.ripard@bootlin.com [1] Signed-off-by: Ze Huang --- arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 51 +++++++++++++++++++ arch/riscv/boot/dts/spacemit/k1.dtsi | 67 +++++++++++++++++++++++++ 2 files changed, 118 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts index 816ef1bc358ec490aff184d5915d680dbd9f00cb..1f4585fe30b64a63ee643ed9596a3a97db8c0f0d 100644 --- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts @@ -28,6 +28,25 @@ led1 { default-state = "on"; }; }; + + usb3_vhub: regulator-vhub-5v { + compatible = "regulator-fixed"; + regulator-name = "USB30_VHUB"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio K1_GPIO(123) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usb3_vbus: regulator-vbus-5v { + compatible = "regulator-fixed"; + regulator-name = "USB30_VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + gpio = <&gpio K1_GPIO(97) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; }; &uart0 { @@ -35,3 +54,35 @@ &uart0 { pinctrl-0 = <&uart0_2_cfg>; status = "okay"; }; + +&usbphy2 { + status = "okay"; +}; + +&combphy { + status = "okay"; +}; + +&usb_dwc3 { + dr_mode = "host"; + vbus-supply = <&usb3_vbus>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + hub_2_0: hub@1 { + compatible = "usb2109,2817"; + reg = <0x1>; + vdd-supply = <&usb3_vhub>; + peer-hub = <&hub_3_0>; + reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>; + }; + + hub_3_0: hub@2 { + compatible = "usb2109,817"; + reg = <0x2>; + vdd-supply = <&usb3_vhub>; + peer-hub = <&hub_2_0>; + reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>; + }; +}; diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi index 61f5ca250ded0da7b91cd4bbd55a5574a89c6ab0..e57b39bba877f90d52227349c983ce638559e601 100644 --- a/arch/riscv/boot/dts/spacemit/k1.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi @@ -4,6 +4,8 @@ */ #include +#include +#include /dts-v1/; / { @@ -346,6 +348,15 @@ soc { dma-noncoherent; ranges; + mbus0: dram-controller@0 { + compatible = "spacemit,k1-mbus"; + reg = <0x0 0x00000000 0x0 0x80000000>; + dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>; + #address-cells = <2>; + #size-cells = <2>; + #interconnect-cells = <0>; + }; + syscon_rcpu: system-controller@c0880000 { compatible = "spacemit,k1-syscon-rcpu"; reg = <0x0 0xc0880000 0x0 0x2048>; @@ -358,6 +369,62 @@ syscon_rcpu2: system-controller@c0888000 { #reset-cells = <1>; }; + usb_dwc3: usb@c0a00000 { + compatible = "spacemit,k1-dwc3"; + reg = <0x0 0xc0a00000 0x0 0x10000>; + clocks = <&syscon_apmu CLK_USB30>; + clock-names = "usbdrd30"; + interconnects = <&mbus0>; + interconnect-names = "dma-mem"; + interrupts = <125>; + phys = <&usbphy2>, <&combphy PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi"; + resets = <&syscon_apmu RESET_USB3_0>; + snps,hsphy_interface = "utmi"; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,dis_rxdet_inp3_quirk; + status = "disabled"; + }; + + usbphy0: phy@c0940000 { + compatible = "spacemit,k1-usb2-phy"; + reg = <0x0 0xc0940000 0x0 0x200>; + clocks = <&syscon_apmu CLK_USB_AXI>; + #phy-cells = <0>; + status = "disabled"; + }; + + usbphy1: phy@c09c0000 { + compatible = "spacemit,k1-usb2-phy"; + reg = <0x0 0xc09c0000 0x0 0x200>; + clocks = <&syscon_apmu CLK_USB_P1>; + #phy-cells = <0>; + status = "disabled"; + }; + + usbphy2: phy@c0a30000 { + compatible = "spacemit,k1-usb2-phy"; + reg = <0x0 0xc0a30000 0x0 0x200>; + clocks = <&syscon_apmu CLK_USB30>; + #phy-cells = <0>; + status = "disabled"; + }; + + combphy: phy@c0b10000 { + compatible = "spacemit,k1-combphy"; + reg = <0x0 0xc0b10000 0x0 0x800>, + <0x0 0xd4282910 0x0 0x400>; + reg-names = "ctrl", "sel"; + resets = <&syscon_apmu RESET_PCIE0>; + #phy-cells = <1>; + status = "disabled"; + }; + syscon_apbc: system-control@d4015000 { compatible = "spacemit,k1-syscon-apbc"; reg = <0x0 0xd4015000 0x0 0x1000>;