From patchwork Wed May 28 10:52:51 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Umer Uddin X-Patchwork-Id: 893089 Received: from sendmail.purelymail.com (sendmail.purelymail.com [34.202.193.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 38C4424469C for ; Wed, 28 May 2025 10:54:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=34.202.193.197 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748429650; cv=none; b=Xak/v+9hLwbgQuJartHMN1puElKdV6hkcl2Up+POCnUIw/V+lhQ4J1Btw4D/NvA2wXmK7uzTLAu8ImsTe5cfSyknIAsphSk04zLyO+4NfGbjU1mpaUvhRm+VOxKa7pD73ypvaMOjlhk2kpineZXdDkf7rjDD/czR5++W/26ShtM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748429650; c=relaxed/simple; bh=JgCYTvLWUK/mh8lOqOaJ8RLcYi0tSYTu+9p0SfSb+sI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=c8icWG4b5bYA8wOimpagUOyKZqgmKdU5VGv6VKT7cUv9Pqw1XiYRLWFUGAy1qtW7+py61Vzfo3MSV2MTIUO9wsuiizNWjYF1yScRIS6G/ivOi6zpCKHg3ViT5Vpqr6o0qjOSVYm5ILWC63MDd9y8nBrHlwHdZIPYZGW+t3PdLh4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=mentallysanemainliners.org; spf=pass smtp.mailfrom=mentallysanemainliners.org; dkim=pass (2048-bit key) header.d=purelymail.com header.i=@purelymail.com header.b=jTiJGQds; arc=none smtp.client-ip=34.202.193.197 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=mentallysanemainliners.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mentallysanemainliners.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=purelymail.com header.i=@purelymail.com header.b="jTiJGQds" Authentication-Results: purelymail.com; auth=pass DKIM-Signature: a=rsa-sha256; b=jTiJGQdsCmZMEXP3gFgOQDOSjH0QEjZ8GGVwwvgcwHzLqI0p5osRERcq/pfByCUMf1TNS5fRePgSJDzD9AXWhAa3FGqWBOFZpozxG+M2p40ZCxSn8BhCEp50LrrxwMf/9fSBQc7t0kavcKTXhSe25HJR32dPFyPwoTDUKhdGbuxXPIJmDg+RAO9Y+PqX9Bp0S76oRAeNcm4nVebItWQhth7ujro99NQA6pbi2fwVn8XfNXj1iMlF4fy/FVDJqvXfNa8GvsHOi6XH40jmuCHe290ElWsKm6GDOC7tmqPu10f/Xhi4vUAof03dW/w45jI3T5uwFVP4K5NLQHP6Jtc6Lw==; s=purelymail3; d=purelymail.com; v=1; bh=JgCYTvLWUK/mh8lOqOaJ8RLcYi0tSYTu+9p0SfSb+sI=; h=Feedback-ID:Received:From:To:Subject:Date; Feedback-ID: 68229:10037:null:purelymail X-Pm-Original-To: linux-samsung-soc@vger.kernel.org Received: by smtp.purelymail.com (Purelymail SMTP) with ESMTPSA id -1157235224; (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384); Wed, 28 May 2025 10:53:47 +0000 (UTC) From: Umer Uddin To: Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley , Igor Belwon Cc: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 1/2] dt-bindings: clock: exynos990: Add CMU_HSI1 bindings Date: Wed, 28 May 2025 11:52:51 +0100 Message-ID: <20250528105252.157533-2-umer.uddin@mentallysanemainliners.org> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250528105252.157533-1-umer.uddin@mentallysanemainliners.org> References: <20250528105252.157533-1-umer.uddin@mentallysanemainliners.org> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MIME-Autoconverted: from 8bit to quoted-printable by Purelymail Add dt-schema documentation for the Exynos990 CMU_HSI1 block. This clock management unit provides clocks for the DesignWare MMC controller, PCIE subsystem and UFS subsystem. Signed-off-by: Umer Uddin --- .../clock/samsung,exynos990-clock.yaml | 27 +++++++++++++++++++ include/dt-bindings/clock/samsung,exynos990.h | 7 +++++ 2 files changed, 34 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos990-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos990-clock.yaml index c15cc1752..ce3b845ce 100644 --- a/Documentation/devicetree/bindings/clock/samsung,exynos990-clock.yaml +++ b/Documentation/devicetree/bindings/clock/samsung,exynos990-clock.yaml @@ -31,6 +31,7 @@ properties: compatible: enum: - samsung,exynos990-cmu-hsi0 + - samsung,exynos990-cmu-hsi1 - samsung,exynos990-cmu-peris - samsung,exynos990-cmu-top @@ -80,6 +81,32 @@ allOf: - const: usbdp_debug - const: dpgtc + - if: + properties: + compatible: + contains: + const: samsung,exynos990-cmu-hsi1 + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_HSI1 BUS clock (from CMU_TOP) + - description: CMU_HSI1 MMC_CARD clock (from CMU_TOP) + - description: CMU_HSI1 PCIE clock (from CMU_TOP) + - description: CMU_HSI1 UFS_CARD clock (from CMU_TOP) + - description: CMU_HSI1 UFS_EMBD clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: bus + - const: mmc_card + - const: pcie + - const: ufs_card + - const: ufs_embd + - if: properties: compatible: diff --git a/include/dt-bindings/clock/samsung,exynos990.h b/include/dt-bindings/clock/samsung,exynos990.h index 6b9df09d2..3164cca44 100644 --- a/include/dt-bindings/clock/samsung,exynos990.h +++ b/include/dt-bindings/clock/samsung,exynos990.h @@ -254,4 +254,11 @@ #define CLK_GOUT_PERIS_OTP_CON_BIRA_OSCCLK 18 #define CLK_GOUT_PERIS_OTP_CON_TOP_OSCCLK 19 +/* CMU_HSI1 */ +#define CLK_MOUT_HSI1_BUS_USER 1 +#define CLK_MOUT_HSI1_MMC_CARD_USER 2 +#define CLK_MOUT_HSI1_PCIE_USER 3 +#define CLK_MOUT_HSI1_UFS_CARD_USER 4 +#define CLK_MOUT_HSI1_UFS_EMBD_USER 5 + #endif From patchwork Wed May 28 10:52:52 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Umer Uddin X-Patchwork-Id: 893294 Received: from sendmail.purelymail.com (sendmail.purelymail.com [34.202.193.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3C97F217F23 for ; Wed, 28 May 2025 10:54:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=34.202.193.197 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748429654; cv=none; b=FyEzQp/4oD01qXLEnRyhGMxY/0ANW/UOAgcOTxyl3anq0BM00TKFiAXdLXgNjliVj0PJKcoJbDgmRqpapzS01AZRBnwftbhNEtHdbVtlRTmS4A/CdFhMynvEPZARkl25tFo/6JBdmmRbJ0BsASaeSG09HOe/4sqOSPXdsjBZIV4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748429654; c=relaxed/simple; bh=0pPylfzDfxShLC+1NXvmbMDM0mKUGGgu8xx79UZwJpw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; 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s=purelymail3; d=purelymail.com; v=1; bh=0pPylfzDfxShLC+1NXvmbMDM0mKUGGgu8xx79UZwJpw=; h=Feedback-ID:Received:From:To:Subject:Date; Feedback-ID: 68229:10037:null:purelymail X-Pm-Original-To: linux-samsung-soc@vger.kernel.org Received: by smtp.purelymail.com (Purelymail SMTP) with ESMTPSA id -1157235224; (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384); Wed, 28 May 2025 10:53:49 +0000 (UTC) From: Umer Uddin To: Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley , Igor Belwon Cc: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 2/2] clk: samsung: exynos990: Add CMU_HSI1 block Date: Wed, 28 May 2025 11:52:52 +0100 Message-ID: <20250528105252.157533-3-umer.uddin@mentallysanemainliners.org> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250528105252.157533-1-umer.uddin@mentallysanemainliners.org> References: <20250528105252.157533-1-umer.uddin@mentallysanemainliners.org> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MIME-Autoconverted: from 8bit to quoted-printable by Purelymail The CMU_HSI1 block is used for providing clocks for the DesignWare MMC Controller, PCIE Subsystem and UFS subsystem, and has six dependency clocks from CMU_TOP. Signed-off-by: Umer Uddin --- drivers/clk/samsung/clk-exynos990.c | 221 ++++++++++++++++++++++++++++ 1 file changed, 221 insertions(+) diff --git a/drivers/clk/samsung/clk-exynos990.c b/drivers/clk/samsung/clk-exynos990.c index 8d3f193d2..91ecbafcf 100644 --- a/drivers/clk/samsung/clk-exynos990.c +++ b/drivers/clk/samsung/clk-exynos990.c @@ -20,6 +20,7 @@ #define CLKS_NR_TOP (CLK_GOUT_CMU_VRA_BUS + 1) #define CLKS_NR_HSI0 (CLK_GOUT_HSI0_XIU_D_HSI0_ACLK + 1) #define CLKS_NR_PERIS (CLK_GOUT_PERIS_OTP_CON_TOP_OSCCLK + 1) +#define CLKS_NR_HSI1 (CLK_MOUT_HSI1_UFS_EMBD_USER + 1) /* ---- CMU_TOP ------------------------------------------------------------- */ @@ -1483,6 +1484,222 @@ static void __init exynos990_cmu_peris_init(struct device_node *np) CLK_OF_DECLARE(exynos990_cmu_peris, "samsung,exynos990-cmu-peris", exynos990_cmu_peris_init); +/* ---- CMU_HSI1 ------------------------------------------------------------ */ + +/* Register Offset definitions for CMU_HSI1 (0x13000000) */ +#define PLL_CON0_MUX_CLKCMU_HSI1_BUS_USER 0x0600 +#define PLL_CON1_MUX_CLKCMU_HSI1_BUS_USER 0x0604 +#define PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER 0x0610 +#define PLL_CON1_MUX_CLKCMU_HSI1_MMC_CARD_USER 0x0614 +#define PLL_CON0_MUX_CLKCMU_HSI1_PCIE_USER 0x0620 +#define PLL_CON1_MUX_CLKCMU_HSI1_PCIE_USER 0x0624 +#define PLL_CON0_MUX_CLKCMU_HSI1_UFS_CARD_USER 0x0630 +#define PLL_CON1_MUX_CLKCMU_HSI1_UFS_CARD_USER 0x0634 +#define PLL_CON0_MUX_CLKCMU_HSI1_UFS_EMBD_USER 0x0640 +#define PLL_CON1_MUX_CLKCMU_HSI1_UFS_EMBD_USER 0x0644 +#define HSI1_CMU_HSI1_CONTROLLER_OPTION 0x0800 +#define CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PHY_REFCLK_IN 0x2000 +#define CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_001_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN 0x2004 +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK 0x2008 +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK 0x200c +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK 0x2010 +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_LHM_AXI_P_HSI1_IPCLKPORT_I_CLK 0x2014 +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_LHS_ACEL_D_HSI1_IPCLKPORT_I_CLK 0x2018 +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_MMC_CARD_IPCLKPORT_I_ACLK 0x201c +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_MMC_CARD_IPCLKPORT_SDCLKIN 0x2020 +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_DBI_ACLK 0x2024 +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIEG2_PHY_X1_INST_0_I_SCL_APB_PCLK 0x2028 +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_MSTR_ACLK 0x202c +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK 0x2030 +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PIPE2_DIGITAL_X1_WRAP_INST_0_I_APB_PCLK_SCL 0x2034 +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_SLV_ACLK 0x2038 +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_001_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG 0x203c +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_001_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG 0x2040 +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_001_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG 0x2044 +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_001_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK 0x2048 +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK 0x204c +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY000X2_LN07LPP_QCH_TM_WRAPPER_INST_0_I_APB_PCLK 0x2050 +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN2_IPCLKPORT_I_CLK 0x2054 +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN4_0_IPCLKPORT_I_CLK 0x2058 +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK 0x205c +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK 0x2060 +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_BUS_IPCLKPORT_CLK 0x2064 +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_OSCCLK_IPCLKPORT_CLK 0x2068 +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2 0x206c +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK 0x2070 +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_CARD_IPCLKPORT_I_ACLK 0x2074 +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_CARD_IPCLKPORT_I_CLK_UNIPRO 0x2078 +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_CARD_IPCLKPORT_I_FMP_CLK 0x207c +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_ACLK 0x2080 +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO 0x2084 +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK 0x2088 +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_VGEN_LITE_HSI1_IPCLKPORT_CLK 0x208c +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK 0x2090 +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK 0x2094 +#define DMYQCH_CON_PCIE_GEN2_QCH_REF 0x3000 +#define DMYQCH_CON_PCIE_GEN4_0_QCH_REF 0x3004 +#define QCH_CON_D_TZPC_HSI1_QCH 0x3024 +#define QCH_CON_GPIO_HSI1_QCH 0x3028 +#define QCH_CON_HSI1_CMU_HSI1_QCH 0x302c +#define QCH_CON_LHM_AXI_P_HSI1_QCH 0x3030 +#define QCH_CON_LHS_ACEL_D_HSI1_QCH 0x3034 +#define QCH_CON_MMC_CARD_QCH 0x3038 +#define QCH_CON_PCIE_GEN2_QCH_APB 0x303c +#define QCH_CON_PCIE_GEN2_QCH_DBI 0x3040 +#define QCH_CON_PCIE_GEN2_QCH_MSTR 0x3044 +#define QCH_CON_PCIE_GEN2_QCH_PCS 0x3048 +#define QCH_CON_PCIE_GEN2_QCH_PHY 0x304c +#define QCH_CON_PCIE_GEN4_0_QCH_APB 0x3050 +#define QCH_CON_PCIE_GEN4_0_QCH_AXI 0x3054 +#define QCH_CON_PCIE_GEN4_0_QCH_DBI 0x3058 +#define QCH_CON_PCIE_GEN4_0_QCH_PCS_APB 0x305c +#define QCH_CON_PCIE_GEN4_0_QCH_PMA_APB 0x3060 +#define QCH_CON_PCIE_IA_GEN2_QCH 0x3064 +#define QCH_CON_PCIE_IA_GEN4_0_QCH 0x3068 +#define QCH_CON_PPMU_HSI1_QCH 0x306c +#define QCH_CON_SYSMMU_HSI1_QCH 0x3070 +#define QCH_CON_SYSREG_HSI1_QCH 0x3074 +#define QCH_CON_UFS_CARD_QCH 0x3078 +#define QCH_CON_UFS_CARD_QCH_FMP 0x307c +#define QCH_CON_UFS_EMBD_QCH 0x3080 +#define QCH_CON_UFS_EMBD_QCH_FMP 0x3084 +#define QCH_CON_VGEN_LITE_HSI1_QCH 0x3088 + +static const unsigned long hsi1_clk_regs[] __initconst = { + PLL_CON0_MUX_CLKCMU_HSI1_BUS_USER, + PLL_CON1_MUX_CLKCMU_HSI1_BUS_USER, + PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER, + PLL_CON1_MUX_CLKCMU_HSI1_MMC_CARD_USER, + PLL_CON0_MUX_CLKCMU_HSI1_PCIE_USER, + PLL_CON1_MUX_CLKCMU_HSI1_PCIE_USER, + PLL_CON0_MUX_CLKCMU_HSI1_UFS_CARD_USER, + PLL_CON1_MUX_CLKCMU_HSI1_UFS_CARD_USER, + PLL_CON0_MUX_CLKCMU_HSI1_UFS_EMBD_USER, + PLL_CON1_MUX_CLKCMU_HSI1_UFS_EMBD_USER, + HSI1_CMU_HSI1_CONTROLLER_OPTION, + CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PHY_REFCLK_IN, + CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_001_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_LHM_AXI_P_HSI1_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_LHS_ACEL_D_HSI1_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_MMC_CARD_IPCLKPORT_I_ACLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_MMC_CARD_IPCLKPORT_SDCLKIN, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_DBI_ACLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIEG2_PHY_X1_INST_0_I_SCL_APB_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_MSTR_ACLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PIPE2_DIGITAL_X1_WRAP_INST_0_I_APB_PCLK_SCL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_SLV_ACLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_001_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_001_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_001_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_001_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY000X2_LN07LPP_QCH_TM_WRAPPER_INST_0_I_APB_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN2_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN4_0_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_BUS_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_OSCCLK_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_CARD_IPCLKPORT_I_ACLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_CARD_IPCLKPORT_I_CLK_UNIPRO, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_CARD_IPCLKPORT_I_FMP_CLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_ACLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_VGEN_LITE_HSI1_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK, + DMYQCH_CON_PCIE_GEN2_QCH_REF, + DMYQCH_CON_PCIE_GEN4_0_QCH_REF, + QCH_CON_D_TZPC_HSI1_QCH, + QCH_CON_GPIO_HSI1_QCH, + QCH_CON_HSI1_CMU_HSI1_QCH, + QCH_CON_LHM_AXI_P_HSI1_QCH, + QCH_CON_LHS_ACEL_D_HSI1_QCH, + QCH_CON_MMC_CARD_QCH, + QCH_CON_PCIE_GEN2_QCH_APB, + QCH_CON_PCIE_GEN2_QCH_DBI, + QCH_CON_PCIE_GEN2_QCH_MSTR, + QCH_CON_PCIE_GEN2_QCH_PCS, + QCH_CON_PCIE_GEN2_QCH_PHY, + QCH_CON_PCIE_GEN4_0_QCH_APB, + QCH_CON_PCIE_GEN4_0_QCH_AXI, + QCH_CON_PCIE_GEN4_0_QCH_DBI, + QCH_CON_PCIE_GEN4_0_QCH_PCS_APB, + QCH_CON_PCIE_GEN4_0_QCH_PMA_APB, + QCH_CON_PCIE_IA_GEN2_QCH, + QCH_CON_PCIE_IA_GEN4_0_QCH, + QCH_CON_PPMU_HSI1_QCH, + QCH_CON_SYSMMU_HSI1_QCH, + QCH_CON_SYSREG_HSI1_QCH, + QCH_CON_UFS_CARD_QCH, + QCH_CON_UFS_CARD_QCH_FMP, + QCH_CON_UFS_EMBD_QCH, + QCH_CON_UFS_EMBD_QCH_FMP, + QCH_CON_VGEN_LITE_HSI1_QCH, +}; + +/* Parent clock list for CMU_HSI1 muxes */ +PNAME(mout_hsi1_ufs_embd_p) = { "oscclk", + "dout_cmu_shared0_div4", + "dout_cmu_shared2_div2", + "oscclk" }; +PNAME(mout_hsi1_ufs_card_p) = { "oscclk", + "dout_cmu_shared0_div4", + "dout_cmu_shared2_div2", + "oscclk" }; +PNAME(mout_hsi1_pcie_p) = { "oscclk", "fout_shared2_pll" }; +PNAME(mout_hsi1_bus_p) = { "dout_cmu_shared0_div3", + "dout_cmu_shared0_div4", + "dout_cmu_shared1_div4", + "dout_cmu_shared4_div3", + "dout_cmu_shared2_div2", + "fout_mmc_pll", + "oscclk", + "oscclk" }; +PNAME(mout_hsi1_mmc_card_p) = { "oscclk", + "fout_shared2_pll", + "fout_mmc_pll", + "dout_cmu_shared0_div4" }; +PNAME(mout_hsi1_bus_user_p) = { "oscclk", "dout_cmu_hsi1_bus" }; +PNAME(mout_hsi1_mmc_card_user_p) = { "oscclk", "dout_cmu_hsi1_mmc_card" }; +PNAME(mout_hsi1_pcie_user_p) = { "oscclk", "dout_cmu_hsi1_pcie" }; +PNAME(mout_hsi1_ufs_card_user_p) = { "oscclk", "dout_cmu_hsi1_ufs_card" }; +PNAME(mout_hsi1_ufs_embd_user_p) = { "oscclk", "dout_cmu_hsi1_ufs_embd" }; + +static const struct samsung_mux_clock hsi1_mux_clks[] __initconst = { + MUX(CLK_MOUT_HSI1_BUS_USER, "mout_hsi1_bus_user", + mout_hsi1_bus_user_p, PLL_CON0_MUX_CLKCMU_HSI1_BUS_USER, + 4, 1), + MUX(CLK_MOUT_HSI1_MMC_CARD_USER, "mout_hsi1_mmc_card_user", + mout_hsi1_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER, + 4, 1), + MUX(CLK_MOUT_HSI1_PCIE_USER, "mout_hsi1_pcie_user", + mout_hsi1_pcie_user_p, PLL_CON0_MUX_CLKCMU_HSI1_PCIE_USER, + 4, 1), + MUX(CLK_MOUT_HSI1_UFS_CARD_USER, "mout_hsi1_ufs_card_user", + mout_hsi1_ufs_card_user_p, PLL_CON0_MUX_CLKCMU_HSI1_UFS_CARD_USER, + 4, 1), + MUX(CLK_MOUT_HSI1_UFS_EMBD_USER, "mout_hsi1_ufs_embd_user", + mout_hsi1_ufs_embd_user_p, PLL_CON0_MUX_CLKCMU_HSI1_UFS_EMBD_USER, + 4, 1), +}; + +static const struct samsung_cmu_info hsi1_cmu_info __initconst = { + .mux_clks = hsi1_mux_clks, + .nr_mux_clks = ARRAY_SIZE(hsi1_mux_clks), + .nr_clk_ids = CLKS_NR_HSI1, + .clk_regs = hsi1_clk_regs, + .nr_clk_regs = ARRAY_SIZE(hsi1_clk_regs), + .clk_name = "bus", +}; + /* ----- platform_driver ----- */ static int __init exynos990_cmu_probe(struct platform_device *pdev) @@ -1501,6 +1718,10 @@ static const struct of_device_id exynos990_cmu_of_match[] = { .compatible = "samsung,exynos990-cmu-hsi0", .data = &hsi0_cmu_info, }, + { + .compatible = "samsung,exynos990-cmu-hsi1", + .data = &hsi1_cmu_info, + }, { }, };