From patchwork Thu May 29 22:23:48 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wilczynski X-Patchwork-Id: 893515 Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BA20521D5A9 for ; Thu, 29 May 2025 22:24:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.118.77.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748557455; cv=none; b=TcnDbhavkXp0DPNye+431e3LiA9HSpjtOyDOG+jLg0DJVPtysyaq4iFkxWfU6CEx4EfpmcARuFlmX6yxB+b7KYTn173OOJN79PPP6r5rSJwcqfcArhRj9U5QeHP+BEtvVs8lcO4JO+LfNqBtF0jAoi6irjCNHPBRadFJfoAfZ3E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748557455; c=relaxed/simple; bh=LKLrrWq8thhk1EMk6yfw2Nl2anZxcSL9JmtArSpirfg=; h=From:Date:Subject:MIME-Version:Message-Id:In-Reply-To:To:Cc: Content-Type:References; b=aDOIYviCIK4Y7uaAJU3vmaJZBgq9yAI/mLxqq/cLe9Qu34bWKjwbvwNxTE7tLgAS6Q4SDMVs/7riWuzvz+Ej9POHLoPG1E1+bRh44DraiVLTbFQTDYO+qWKCV85NGsLXS/ysEbzoaELNv2vQKQbDx3wdB/gOqcvojt55c7aL91k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=PdlwNPOP; arc=none smtp.client-ip=210.118.77.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="PdlwNPOP" Received: from eucas1p1.samsung.com (unknown [182.198.249.206]) by mailout2.w1.samsung.com (KnoxPortal) with ESMTP id 20250529222405euoutp020a3dece1e8a1113aea41cc1b8762e088~EH7uHzi_k2213722137euoutp02u for ; Thu, 29 May 2025 22:24:05 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout2.w1.samsung.com 20250529222405euoutp020a3dece1e8a1113aea41cc1b8762e088~EH7uHzi_k2213722137euoutp02u DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1748557445; bh=YWgZEAPcMH46NIGH2/oSKhwnvWs2dOgmME8UVmfVxfk=; h=From:Date:Subject:In-Reply-To:To:Cc:References:From; b=PdlwNPOP7Bq6mAnKXwUUKOtMzeH42uNn7zWl+n5xLfLi4AmEtVSivsrBSDR/3kAhM wPFrUy503C1TVlyEuXqJo/BRIgCHm1/2YKxlRUOQZCbGwPP0QsecSm0y7i1Yh2DE0p JJuXDfCPTdFS49H/jNLU1o7vwoAnJHKiRfzaaqA8= Received: from eusmtip2.samsung.com (unknown [203.254.199.222]) by eucas1p1.samsung.com (KnoxPortal) with ESMTPA id 20250529222403eucas1p1923fe09240be34e3bbadf16822574d75~EH7sXLUlv2958729587eucas1p1j; Thu, 29 May 2025 22:24:03 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250529222402eusmtip2d7d50774a6c6e15081addf3fce030b9c~EH7reGp5Y3031530315eusmtip2K; Thu, 29 May 2025 22:24:02 +0000 (GMT) From: Michal Wilczynski Date: Fri, 30 May 2025 00:23:48 +0200 Subject: [PATCH v3 1/8] dt-bindings: power: Add T-HEAD TH1520 GPU power sequencer Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250530-apr_14_for_sending-v3-1-83d5744d997c@samsung.com> In-Reply-To: <20250530-apr_14_for_sending-v3-0-83d5744d997c@samsung.com> To: Drew Fustini , Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michal Wilczynski , Bartosz Golaszewski , Philipp Zabel , Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Ulf Hansson , Marek Szyprowski Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dri-devel@lists.freedesktop.org X-Mailer: b4 0.15-dev X-CMS-MailID: 20250529222403eucas1p1923fe09240be34e3bbadf16822574d75 X-Msg-Generator: CA X-RootMTR: 20250529222403eucas1p1923fe09240be34e3bbadf16822574d75 X-EPHeader: CA X-CMS-RootMailID: 20250529222403eucas1p1923fe09240be34e3bbadf16822574d75 References: <20250530-apr_14_for_sending-v3-0-83d5744d997c@samsung.com> Introduce device tree bindings for a new power sequencer provider dedicated to the T-HEAD TH1520 SoC's GPU. The thead,th1520-gpu-pwrseq compatible designates a node that will manage the complex power-up and power-down sequence for the GPU. This sequencer requires a handle to the GPU's clock generator reset line (gpu-clkgen), which is specified in its device tree node. This binding will be used by a new pwrseq driver to abstract the SoC specific power management details from the generic GPU driver. Signed-off-by: Michal Wilczynski --- .../bindings/power/thead,th1520-pwrseq.yaml | 42 ++++++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 43 insertions(+) diff --git a/Documentation/devicetree/bindings/power/thead,th1520-pwrseq.yaml b/Documentation/devicetree/bindings/power/thead,th1520-pwrseq.yaml new file mode 100644 index 0000000000000000000000000000000000000000..4c302abfb76fb9e243946f4eefa333c6b02e59d3 --- /dev/null +++ b/Documentation/devicetree/bindings/power/thead,th1520-pwrseq.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/thead,th1520-pwrseq.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: T-HEAD TH1520 GPU Power Sequencer + +maintainers: + - Michal Wilczynski + +description: | + This binding describes the power sequencer for the T-HEAD TH1520 GPU. + This sequencer handles the specific power-up and power-down sequences + required by the GPU, including managing clocks and resets from both the + sequencer and the GPU device itself. + +properties: + compatible: + const: thead,th1520-gpu-pwrseq + + resets: + description: A phandle to the GPU clock generator reset. + maxItems: 1 + + reset-names: + const: gpu-clkgen + +required: + - compatible + - resets + - reset-names + +additionalProperties: false + +examples: + - | + gpu_pwrseq: pwrseq { + compatible = "thead,th1520-gpu-pwrseq"; + resets = <&rst 0>; + reset-names = "gpu-clkgen"; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 0d59a5910e632350a4d72a761c6c5ce1d3a1bc34..78e3067df1152929de638244b03264733d08556e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21355,6 +21355,7 @@ F: Documentation/devicetree/bindings/firmware/thead,th1520-aon.yaml F: Documentation/devicetree/bindings/mailbox/thead,th1520-mbox.yaml F: Documentation/devicetree/bindings/net/thead,th1520-gmac.yaml F: Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml +F: Documentation/devicetree/bindings/power/thead,th1520-pwrseq.yaml F: Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml F: arch/riscv/boot/dts/thead/ F: drivers/clk/thead/clk-th1520-ap.c From patchwork Thu May 29 22:23:49 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wilczynski X-Patchwork-Id: 893514 Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com [210.118.77.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C9BA921D011 for ; Thu, 29 May 2025 22:24:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.118.77.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748557457; cv=none; b=kx5uKubvfuML+4J4HZhhhazgfKZIhjeHh5984oVmfWe5v8RBFcAIjfUduePcBt4JHH9CU06TxhTxib3hV2utJM4HSpAPS9nFNWqSKrhBIs3050jE2ZKs63G5BOp3KqhFc4PK69Viv6jkM/EwfZX+IDIn/KpHjqVP3loiKVORVB0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748557457; c=relaxed/simple; bh=XYPnSniSl5TQ1Kilk0vMYbPbVUZoTWkdcRno4GekXmw=; h=From:Date:Subject:MIME-Version:Message-Id:In-Reply-To:To:Cc: Content-Type:References; b=Dzw5IBqbxFoLZwv1RDh2a6CC+9aw72SHdqXyR3qNT10diOupK00M25OCHUfcqEBAeGeqrZeCRWG6WCnAXSrxccIRCosBW/0qxowc0zTARNW9eXlSj0zOWbpXwMivoXvHZCrUqiK3EhU4qUPxRMYsezgrPzo2fn29N1arQIkYJ3c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=B+3UP7tZ; arc=none smtp.client-ip=210.118.77.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="B+3UP7tZ" Received: from eucas1p2.samsung.com (unknown [182.198.249.207]) by mailout1.w1.samsung.com (KnoxPortal) with ESMTP id 20250529222406euoutp01d2aeb11f171f880fb851a9c95026c4db~EH7u2A-Iq2316423164euoutp01w for ; Thu, 29 May 2025 22:24:06 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout1.w1.samsung.com 20250529222406euoutp01d2aeb11f171f880fb851a9c95026c4db~EH7u2A-Iq2316423164euoutp01w DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1748557446; bh=UObq1t0kD6KfUVwCQSJxpDszWtGDpqoeR5CqwEksnG0=; h=From:Date:Subject:In-Reply-To:To:Cc:References:From; b=B+3UP7tZxIyAyROXbo/GXzWdx73wYbI+jMPYPNrJYNb4XZ6gy7Hzk0Y1IUW/F1j5G LnxUoJiiYCxDWuE9Ur6+TAipeJoV+M+gItouO7dPd6o41kpWospJE2XjNf54LQY3K/ GdiRoN+J1Nc0iE0WkUE/SlisoCSKYDDJzJFyNovk= Received: from eusmtip2.samsung.com (unknown [203.254.199.222]) by eucas1p2.samsung.com (KnoxPortal) with ESMTPA id 20250529222404eucas1p2856b44ad410171edfc2190127dafee0c~EH7tVu98u0077600776eucas1p27; Thu, 29 May 2025 22:24:04 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250529222403eusmtip20eae166d9772e97e6f93490f4880dff2~EH7sasbSi2867928679eusmtip2T; Thu, 29 May 2025 22:24:03 +0000 (GMT) From: Michal Wilczynski Date: Fri, 30 May 2025 00:23:49 +0200 Subject: [PATCH v3 2/8] power: sequencing: Add T-HEAD TH1520 GPU power sequencer driver Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250530-apr_14_for_sending-v3-2-83d5744d997c@samsung.com> In-Reply-To: <20250530-apr_14_for_sending-v3-0-83d5744d997c@samsung.com> To: Drew Fustini , Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michal Wilczynski , Bartosz Golaszewski , Philipp Zabel , Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Ulf Hansson , Marek Szyprowski Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dri-devel@lists.freedesktop.org X-Mailer: b4 0.15-dev X-CMS-MailID: 20250529222404eucas1p2856b44ad410171edfc2190127dafee0c X-Msg-Generator: CA X-RootMTR: 20250529222404eucas1p2856b44ad410171edfc2190127dafee0c X-EPHeader: CA X-CMS-RootMailID: 20250529222404eucas1p2856b44ad410171edfc2190127dafee0c References: <20250530-apr_14_for_sending-v3-0-83d5744d997c@samsung.com> Introduce the pwrseq-thead-gpu driver, a power sequencer provider for the Imagination BXM-4-64 GPU on the T-HEAD TH1520 SoC. The TH1520 GPU requires a specific sequence to correctly initialize and power down its resources: - Enable GPU clocks (core and sys). - De-assert the GPU clock generator reset (clkgen_reset). - Introduce a short hardware-required delay. - De-assert the GPU core reset. The power-down sequence performs these steps in reverse. Implement this sequence via the pwrseq_power_on and pwrseq_power_off callbacks. It binds to the "thead,th1520-gpu-pwrseq" device tree node, from which it acquires the clkgen_reset. Crucially, the driver's match function is called when a consumer (the Imagination GPU driver) requests the "gpu-power" target. During this match, the sequencer uses devm_clk_bulk_get() and devm_reset_control_get_exclusive() on the consumer's device to obtain handles to the GPU's "core" and "sys" clocks, and the GPU core reset. These, along with its own clkgen_reset, allow it to perform the complete sequence. Signed-off-by: Michal Wilczynski --- MAINTAINERS | 1 + drivers/power/sequencing/Kconfig | 8 ++ drivers/power/sequencing/Makefile | 1 + drivers/power/sequencing/pwrseq-thead-gpu.c | 183 ++++++++++++++++++++++++++++ 4 files changed, 193 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 78e3067df1152929de638244b03264733d08556e..237b37a3f6296a72323657419789dc6fdad1b5d0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21364,6 +21364,7 @@ F: drivers/mailbox/mailbox-th1520.c F: drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c F: drivers/pinctrl/pinctrl-th1520.c F: drivers/pmdomain/thead/ +F: drivers/power/sequencing/pwrseq-thead-gpu.c F: drivers/reset/reset-th1520.c F: include/dt-bindings/clock/thead,th1520-clk-ap.h F: include/dt-bindings/power/thead,th1520-power.h diff --git a/drivers/power/sequencing/Kconfig b/drivers/power/sequencing/Kconfig index ddcc42a984921c55667c46ac586d259625e1f1a7..935428ce8cf44794b7eb943f722ace5021237af2 100644 --- a/drivers/power/sequencing/Kconfig +++ b/drivers/power/sequencing/Kconfig @@ -27,4 +27,12 @@ config POWER_SEQUENCING_QCOM_WCN this driver is needed for correct power control or else we'd risk not respecting the required delays between enabling Bluetooth and WLAN. +config POWER_SEQUENCING_THEAD_GPU + tristate "T-HEAD TH1520 GPU power sequencing driver" + depends on ARCH_THEAD + help + Say Y here to enable the power sequencing driver for the TH1520 SoC + GPU. This driver handles the complex clock and reset sequence + required to power on the Imagination BXM GPU on this platform. + endif diff --git a/drivers/power/sequencing/Makefile b/drivers/power/sequencing/Makefile index 2eec2df7912d11827f9ba914177dd2c882e44bce..647f81f4013ab825630f069d2e0f6d22159f1f56 100644 --- a/drivers/power/sequencing/Makefile +++ b/drivers/power/sequencing/Makefile @@ -4,3 +4,4 @@ obj-$(CONFIG_POWER_SEQUENCING) += pwrseq-core.o pwrseq-core-y := core.o obj-$(CONFIG_POWER_SEQUENCING_QCOM_WCN) += pwrseq-qcom-wcn.o +obj-$(CONFIG_POWER_SEQUENCING_THEAD_GPU) += pwrseq-thead-gpu.o diff --git a/drivers/power/sequencing/pwrseq-thead-gpu.c b/drivers/power/sequencing/pwrseq-thead-gpu.c new file mode 100644 index 0000000000000000000000000000000000000000..e4c15c3d62eee0c088710c4d134ac2c4b16e2b06 --- /dev/null +++ b/drivers/power/sequencing/pwrseq-thead-gpu.c @@ -0,0 +1,183 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * T-HEAD TH1520 GPU Power Sequencer Driver + * + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * Author: Michal Wilczynski + * + * This driver implements the power sequence for the Imagination BXM GPU + * on the T-HEAD TH1520 SoC. The sequence requires coordinating resources + * from both the sequencer's device node (clkgen_reset) and the GPU's + * device node (clocks and core reset). + * + * The `match` function is used to acquire the GPU's resources when the + * GPU driver requests the "gpu-power" sequence target. + */ + +#include +#include +#include +#include +#include +#include +#include + +struct pwrseq_thead_gpu_ctx { + struct pwrseq_device *pwrseq; + struct reset_control *clkgen_reset; + + /* Consumer resources */ + struct clk_bulk_data *clks; + int num_clks; + struct reset_control *gpu_reset; +}; + +static int pwrseq_thead_gpu_power_on(struct pwrseq_device *pwrseq) +{ + struct pwrseq_thead_gpu_ctx *ctx = pwrseq_device_get_drvdata(pwrseq); + int ret; + + if (!ctx->clks || !ctx->gpu_reset) + return -ENODEV; + + ret = clk_bulk_prepare_enable(ctx->num_clks, ctx->clks); + if (ret) + return ret; + + ret = reset_control_deassert(ctx->clkgen_reset); + if (ret) + goto err_disable_clks; + + /* + * According to the hardware manual, a delay of at least 32 clock + * cycles is required between de-asserting the clkgen reset and + * de-asserting the GPU reset. Assuming a worst-case scenario with + * a very high GPU clock frequency, a delay of 1 microsecond is + * sufficient to ensure this requirement is met across all + * feasible GPU clock speeds. + */ + udelay(1); + + ret = reset_control_deassert(ctx->gpu_reset); + if (ret) + goto err_assert_clkgen; + + return 0; + +err_assert_clkgen: + reset_control_assert(ctx->clkgen_reset); +err_disable_clks: + clk_bulk_disable_unprepare(ctx->num_clks, ctx->clks); + return ret; +} + +static int pwrseq_thead_gpu_power_off(struct pwrseq_device *pwrseq) +{ + struct pwrseq_thead_gpu_ctx *ctx = pwrseq_device_get_drvdata(pwrseq); + + if (!ctx->clks || !ctx->gpu_reset) + return -ENODEV; + + reset_control_assert(ctx->gpu_reset); + reset_control_assert(ctx->clkgen_reset); + clk_bulk_disable_unprepare(ctx->num_clks, ctx->clks); + + return 0; +} + +static const struct pwrseq_unit_data pwrseq_thead_gpu_unit = { + .name = "gpu-power-sequence", + .enable = pwrseq_thead_gpu_power_on, + .disable = pwrseq_thead_gpu_power_off, +}; + +static const struct pwrseq_target_data pwrseq_thead_gpu_target = { + .name = "gpu-power", + .unit = &pwrseq_thead_gpu_unit, +}; + +static const struct pwrseq_target_data *pwrseq_thead_gpu_targets[] = { + &pwrseq_thead_gpu_target, + NULL +}; + +static int pwrseq_thead_gpu_match(struct pwrseq_device *pwrseq, struct device *dev) +{ + struct pwrseq_thead_gpu_ctx *ctx = pwrseq_device_get_drvdata(pwrseq); + static const char *const clk_names[] = { "core", "sys" }; + int i, ret; + + /* We only match the specific T-HEAD TH1520 GPU compatible */ + if (!of_device_is_compatible(dev->of_node, "thead,th1520-gpu")) + return 0; + + /* Prevent multiple consumers from attaching */ + if (ctx->gpu_reset || ctx->clks) + return -EBUSY; + + ctx->num_clks = ARRAY_SIZE(clk_names); + ctx->clks = devm_kcalloc(dev, ctx->num_clks, sizeof(*ctx->clks), GFP_KERNEL); + if (!ctx->clks) + return -ENOMEM; + + for (i = 0; i < ctx->num_clks; i++) + ctx->clks[i].id = clk_names[i]; + + ret = devm_clk_bulk_get(dev, ctx->num_clks, ctx->clks); + if (ret) + return dev_err_probe(dev, ret, "Failed to get GPU clocks\n"); + + ctx->gpu_reset = devm_reset_control_get_exclusive(dev, NULL); + if (IS_ERR(ctx->gpu_reset)) + return dev_err_probe(dev, PTR_ERR(ctx->gpu_reset), "Failed to get GPU reset\n"); + + return 1; +} + +static int pwrseq_thead_gpu_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct pwrseq_thead_gpu_ctx *ctx; + struct pwrseq_config config = {}; + + ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + + ctx->clkgen_reset = devm_reset_control_get_exclusive(dev, "gpu-clkgen"); + if (IS_ERR(ctx->clkgen_reset)) + return dev_err_probe(dev, PTR_ERR(ctx->clkgen_reset), + "Failed to get GPU clkgen reset\n"); + + config.parent = dev; + config.owner = THIS_MODULE; + config.drvdata = ctx; + config.match = pwrseq_thead_gpu_match; + config.targets = pwrseq_thead_gpu_targets; + + ctx->pwrseq = devm_pwrseq_device_register(dev, &config); + if (IS_ERR(ctx->pwrseq)) + return dev_err_probe(dev, PTR_ERR(ctx->pwrseq), + "Failed to register power sequencer\n"); + + return 0; +} + +static const struct of_device_id pwrseq_thead_gpu_of_match[] = { + { .compatible = "thead,th1520-gpu-pwrseq" }, + { } +}; +MODULE_DEVICE_TABLE(of, pwrseq_thead_gpu_of_match); + +static struct platform_driver pwrseq_thead_gpu_driver = { + .driver = { + .name = "pwrseq-thead-gpu", + .of_match_table = pwrseq_thead_gpu_of_match, + }, + .probe = pwrseq_thead_gpu_probe, +}; +module_platform_driver(pwrseq_thead_gpu_driver); + +MODULE_AUTHOR("Michal Wilczynski "); +MODULE_DESCRIPTION("T-HEAD TH1520 GPU power sequencer driver"); +MODULE_LICENSE("GPL"); From patchwork Thu May 29 22:23:50 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wilczynski X-Patchwork-Id: 893288 Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E843821E094 for ; Thu, 29 May 2025 22:24:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.118.77.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748557456; cv=none; b=s9zd6dnBKKZTKkjq4WZdFTsqQlEmypp+nNI4hStD7MjYKCXzC5wGZiS802qyOz3Wd5mFeH9VwuhQ7yZeB0q5W/3//VhR4tWHeK0t4TKFH5CeuDFnqQ1s3lMQFIprZyVfoxXU0F1Y0aW8cxVMoQsGGdq6cp5jryzcdGeYmfrLF6k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748557456; c=relaxed/simple; bh=g3HrJI+i/qPWzFTH4SgOBu/2lO60y1spJ4g/6Mp0yD8=; h=From:Date:Subject:MIME-Version:Message-Id:In-Reply-To:To:Cc: Content-Type:References; b=pAsNgJkEQ8GgHu20MQ1n3Lk+uRpHtGQHRtpqeg61uLSTjeGSCkqI5xM9V1D9k2x2f9uNWKSvW0zWsLSck/gxOGng4ppt4G5xkJlUd8xu7PlJ66eDq9H6ndgv4zOt78I/Fyx9sRXelmXqH5xD2Bmb/Rc58pJiWB+/UBErV61ElRs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=llvfwWOv; arc=none smtp.client-ip=210.118.77.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="llvfwWOv" Received: from eucas1p2.samsung.com (unknown [182.198.249.207]) by mailout2.w1.samsung.com (KnoxPortal) with ESMTP id 20250529222406euoutp02df6cbdb7cd378fbdb8844f293e1dd770~EH7vV2nCZ2213722137euoutp02z for ; Thu, 29 May 2025 22:24:06 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout2.w1.samsung.com 20250529222406euoutp02df6cbdb7cd378fbdb8844f293e1dd770~EH7vV2nCZ2213722137euoutp02z DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1748557446; bh=l0+urxkDydJaXZt0i4z0eElhXfnETxRC93PMjjsxpdg=; h=From:Date:Subject:In-Reply-To:To:Cc:References:From; b=llvfwWOv0sO8NtmufNjuIBWK2vet2yjTAqstOr3zZg4XsoKpfav2awGlw7/jyJyXg 1UvbgDFg3uGtQI6nDAcTzb4a3akd2UIWHqCGMixCO5oHeGWWQ2me/ecSYRnVkLFYxH RAy24GPFwLObzua/bmTej4qJg1+wIdvA3VuaPewM= Received: from eusmtip2.samsung.com (unknown [203.254.199.222]) by eucas1p1.samsung.com (KnoxPortal) with ESMTPA id 20250529222405eucas1p18ed1254bf1b2d78468734656fec537e1~EH7uSIjI11302113021eucas1p1A; Thu, 29 May 2025 22:24:05 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250529222404eusmtip2ba5a345a3bd699d30ca989a3242df931~EH7tZQdKj3031530315eusmtip2L; Thu, 29 May 2025 22:24:04 +0000 (GMT) From: Michal Wilczynski Date: Fri, 30 May 2025 00:23:50 +0200 Subject: [PATCH v3 3/8] drm/imagination: Use pwrseq for TH1520 GPU power management Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250530-apr_14_for_sending-v3-3-83d5744d997c@samsung.com> In-Reply-To: <20250530-apr_14_for_sending-v3-0-83d5744d997c@samsung.com> To: Drew Fustini , Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michal Wilczynski , Bartosz Golaszewski , Philipp Zabel , Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Ulf Hansson , Marek Szyprowski Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dri-devel@lists.freedesktop.org X-Mailer: b4 0.15-dev X-CMS-MailID: 20250529222405eucas1p18ed1254bf1b2d78468734656fec537e1 X-Msg-Generator: CA X-RootMTR: 20250529222405eucas1p18ed1254bf1b2d78468734656fec537e1 X-EPHeader: CA X-CMS-RootMailID: 20250529222405eucas1p18ed1254bf1b2d78468734656fec537e1 References: <20250530-apr_14_for_sending-v3-0-83d5744d997c@samsung.com> Update the Imagination PVR DRM driver to leverage the pwrseq framework for managing the power sequence of the GPU on the T-HEAD TH1520 SoC. In pvr_device_init(), the driver now attempts to get a handle to the "gpu-power" sequencer target using devm_pwrseq_get(). If successful, the responsibility for powering on and off the GPU's core clocks and resets is delegated to the power sequencer. Consequently, the GPU driver conditionally skips acquiring the GPU reset line if the pwrseq handle is obtained, as the sequencer's match function will acquire it. Clock handles are still acquired by the GPU driver for other purposes like devfreq. The runtime PM callbacks, pvr_power_device_resume() and pvr_power_device_suspend(), are modified to call pwrseq_power_on() and pwrseq_power_off() respectively when the sequencer is present. If no sequencer is found, the driver falls back to its existing manual clock and reset management. A helper function, pvr_power_off_sequence_manual(), is introduced to encapsulate the manual power-down logic. Signed-off-by: Michal Wilczynski --- drivers/gpu/drm/imagination/Kconfig | 1 + drivers/gpu/drm/imagination/pvr_device.c | 33 +++++++++++-- drivers/gpu/drm/imagination/pvr_device.h | 6 +++ drivers/gpu/drm/imagination/pvr_power.c | 82 +++++++++++++++++++++----------- 4 files changed, 89 insertions(+), 33 deletions(-) diff --git a/drivers/gpu/drm/imagination/Kconfig b/drivers/gpu/drm/imagination/Kconfig index 3bfa2ac212dccb73c53bdc2bc259bcba636e7cfc..737ace77c4f1247c687cc1fde2f139fc2e118c50 100644 --- a/drivers/gpu/drm/imagination/Kconfig +++ b/drivers/gpu/drm/imagination/Kconfig @@ -11,6 +11,7 @@ config DRM_POWERVR select DRM_SCHED select DRM_GPUVM select FW_LOADER + select POWER_SEQUENCING help Choose this option if you have a system that has an Imagination Technologies PowerVR (Series 6 or later) or IMG GPU. diff --git a/drivers/gpu/drm/imagination/pvr_device.c b/drivers/gpu/drm/imagination/pvr_device.c index 8b9ba4983c4cb5bc40342fcafc4259078bc70547..19d48bbc828cf2b8dbead602e90ff88780152124 100644 --- a/drivers/gpu/drm/imagination/pvr_device.c +++ b/drivers/gpu/drm/imagination/pvr_device.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -631,10 +632,34 @@ pvr_device_init(struct pvr_device *pvr_dev) if (err) return err; - /* Get the reset line for the GPU */ - err = pvr_device_reset_init(pvr_dev); - if (err) - return err; + /* + * Try to get a power sequencer. If successful, it will handle clocks + * and resets. Otherwise, we fall back to managing them ourselves. + */ + pvr_dev->pwrseq = devm_pwrseq_get(dev, "gpu-power"); + if (IS_ERR(pvr_dev->pwrseq)) { + int pwrseq_err = PTR_ERR(pvr_dev->pwrseq); + + /* + * If the error is -EPROBE_DEFER, it's because the + * optional sequencer provider is not present + * and it's safe to fall back on manual power-up. + */ + if (pwrseq_err == -EPROBE_DEFER) + pvr_dev->pwrseq = NULL; + else + return dev_err_probe(dev, pwrseq_err, + "Failed to get power sequencer\n"); + } + + /* Get the reset line for the GPU, but since it's exclusive only + * get it if the pwerseq is NULL. + */ + if (!pvr_dev->pwrseq) { + err = pvr_device_reset_init(pvr_dev); + if (err) + return err; + } /* Explicitly power the GPU so we can access control registers before the FW is booted. */ err = pm_runtime_resume_and_get(dev); diff --git a/drivers/gpu/drm/imagination/pvr_device.h b/drivers/gpu/drm/imagination/pvr_device.h index 7cb01c38d2a9c3fc71effe789d4dfe54eddd93ee..0b6d53994d25abe32a2f1b133a4efa574e150da9 100644 --- a/drivers/gpu/drm/imagination/pvr_device.h +++ b/drivers/gpu/drm/imagination/pvr_device.h @@ -37,6 +37,9 @@ struct clk; /* Forward declaration from . */ struct firmware; +/* Forward declaration from #include #include +#include #include #define POWER_SYNC_TIMEOUT_US (1000000) /* 1s */ @@ -234,6 +235,19 @@ pvr_watchdog_init(struct pvr_device *pvr_dev) return 0; } +static int pvr_power_off_sequence_manual(struct pvr_device *pvr_dev) +{ + int err; + + err = reset_control_assert(pvr_dev->reset); + + clk_disable_unprepare(pvr_dev->mem_clk); + clk_disable_unprepare(pvr_dev->sys_clk); + clk_disable_unprepare(pvr_dev->core_clk); + + return err; +} + int pvr_power_device_suspend(struct device *dev) { @@ -252,11 +266,10 @@ pvr_power_device_suspend(struct device *dev) goto err_drm_dev_exit; } - clk_disable_unprepare(pvr_dev->mem_clk); - clk_disable_unprepare(pvr_dev->sys_clk); - clk_disable_unprepare(pvr_dev->core_clk); - - err = reset_control_assert(pvr_dev->reset); + if (pvr_dev->pwrseq) + err = pwrseq_power_off(pvr_dev->pwrseq); + else + err = pvr_power_off_sequence_manual(pvr_dev); err_drm_dev_exit: drm_dev_exit(idx); @@ -276,44 +289,55 @@ pvr_power_device_resume(struct device *dev) if (!drm_dev_enter(drm_dev, &idx)) return -EIO; - err = clk_prepare_enable(pvr_dev->core_clk); - if (err) - goto err_drm_dev_exit; + if (pvr_dev->pwrseq) { + err = pwrseq_power_on(pvr_dev->pwrseq); + if (err) + goto err_drm_dev_exit; + } else { + err = clk_prepare_enable(pvr_dev->core_clk); + if (err) + goto err_drm_dev_exit; - err = clk_prepare_enable(pvr_dev->sys_clk); - if (err) - goto err_core_clk_disable; + err = clk_prepare_enable(pvr_dev->sys_clk); + if (err) + goto err_core_clk_disable; - err = clk_prepare_enable(pvr_dev->mem_clk); - if (err) - goto err_sys_clk_disable; + err = clk_prepare_enable(pvr_dev->mem_clk); + if (err) + goto err_sys_clk_disable; - /* - * According to the hardware manual, a delay of at least 32 clock - * cycles is required between de-asserting the clkgen reset and - * de-asserting the GPU reset. Assuming a worst-case scenario with - * a very high GPU clock frequency, a delay of 1 microsecond is - * sufficient to ensure this requirement is met across all - * feasible GPU clock speeds. - */ - udelay(1); + /* + * According to the hardware manual, a delay of at least 32 clock + * cycles is required between de-asserting the clkgen reset and + * de-asserting the GPU reset. Assuming a worst-case scenario with + * a very high GPU clock frequency, a delay of 1 microsecond is + * sufficient to ensure this requirement is met across all + * feasible GPU clock speeds. + */ + udelay(1); - err = reset_control_deassert(pvr_dev->reset); - if (err) - goto err_mem_clk_disable; + err = reset_control_deassert(pvr_dev->reset); + if (err) + goto err_mem_clk_disable; + } if (pvr_dev->fw_dev.booted) { err = pvr_power_fw_enable(pvr_dev); if (err) - goto err_reset_assert; + goto err_power_off; } drm_dev_exit(idx); return 0; -err_reset_assert: - reset_control_assert(pvr_dev->reset); +err_power_off: + if (pvr_dev->pwrseq) + pwrseq_power_off(pvr_dev->pwrseq); + else + pvr_power_off_sequence_manual(pvr_dev); + + goto err_drm_dev_exit; err_mem_clk_disable: clk_disable_unprepare(pvr_dev->mem_clk); From patchwork Thu May 29 22:23:51 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wilczynski X-Patchwork-Id: 893287 Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6157021FF49 for ; Thu, 29 May 2025 22:24:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.118.77.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748557458; cv=none; b=e/AdBkKqT04Elztq1vuYojayN+tvCqA55F6j4FFmR6ZgIzNn7gI/yUVFgsKsGICS0EBk/7bUXanhR3iq6DlGgOxrcro8Tqra9RDrOzTuWfiLHRNRY8l0CRVNJ8IIX52BrDWB3njB+wBdrG/aldnpcCyrrqKpblTpfaLGDK7q8RE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748557458; c=relaxed/simple; bh=hoW1ePKj+9Kt2vDJuZuku3nkno6cEQvJM0OL3LmjDt4=; h=From:Date:Subject:MIME-Version:Message-Id:In-Reply-To:To:Cc: Content-Type:References; b=Eu2nCZVjOSi888ezWfWRxE880tUhZHY4rLURgVZZQDtVqEbRL72W6Sknbb73mi2VvhYh/Lbrb6y23z6JyDT3306nYNBEoleeJQy3N3Q/vvUpTbBeMoEXxN6Fydwj1WZmvN0+k45G33XhKnWeufu+AHRfjpUt2ohP6xPd2I/XAqo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=Br6LqUE7; arc=none smtp.client-ip=210.118.77.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="Br6LqUE7" Received: from eucas1p1.samsung.com (unknown [182.198.249.206]) by mailout2.w1.samsung.com (KnoxPortal) with ESMTP id 20250529222408euoutp02ffa78e0a8a5df6e1efe21b9bc1ae0b3f~EH7wip13h0242202422euoutp02K for ; Thu, 29 May 2025 22:24:08 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout2.w1.samsung.com 20250529222408euoutp02ffa78e0a8a5df6e1efe21b9bc1ae0b3f~EH7wip13h0242202422euoutp02K DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1748557448; bh=N+9Ly84haaDNbayhjJ5K7mS9nQgacJUjkY7dLk4JuAo=; h=From:Date:Subject:In-Reply-To:To:Cc:References:From; b=Br6LqUE70WYogOLypvJQ71L+3ybXj/0elULdf8i6w9h8W5fYRmnNnOc10/J5LDZIT haJjVpIINhbSXhQHeNxxYJCHKtBA7YOmwe+wgaaSjKB2RzhmQgzPyVQ/VAz7maNGIm IMqar0BvUK9GADMJQWVsXYxPxYVPy4+NWWkDPYRw= Received: from eusmtip2.samsung.com (unknown [203.254.199.222]) by eucas1p1.samsung.com (KnoxPortal) with ESMTPA id 20250529222406eucas1p117082ce4f06921f71bbc442c47e58574~EH7vRuKw80315603156eucas1p11; Thu, 29 May 2025 22:24:06 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250529222405eusmtip225dbe36b13806921f0a6fd4e8c8f3ad1~EH7uV3wY02867928679eusmtip2U; Thu, 29 May 2025 22:24:05 +0000 (GMT) From: Michal Wilczynski Date: Fri, 30 May 2025 00:23:51 +0200 Subject: [PATCH v3 4/8] dt-bindings: gpu: Add TH1520 GPU compatible to Imagination bindings Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250530-apr_14_for_sending-v3-4-83d5744d997c@samsung.com> In-Reply-To: <20250530-apr_14_for_sending-v3-0-83d5744d997c@samsung.com> To: Drew Fustini , Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michal Wilczynski , Bartosz Golaszewski , Philipp Zabel , Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Ulf Hansson , Marek Szyprowski Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dri-devel@lists.freedesktop.org X-Mailer: b4 0.15-dev X-CMS-MailID: 20250529222406eucas1p117082ce4f06921f71bbc442c47e58574 X-Msg-Generator: CA X-RootMTR: 20250529222406eucas1p117082ce4f06921f71bbc442c47e58574 X-EPHeader: CA X-CMS-RootMailID: 20250529222406eucas1p117082ce4f06921f71bbc442c47e58574 References: <20250530-apr_14_for_sending-v3-0-83d5744d997c@samsung.com> Update the img,powervr-rogue.yaml device tree bindings to include the T-HEAD TH1520 SoC's specific GPU compatible string. The thead,th1520-gpu compatible, along with its full chain img,img-bxm-4-64, and img,img-rogue, is added to the list of recognized GPU types. This allows the Imagination DRM driver to correctly bind to the GPU node defined in the TH1520 device tree. The power-domains property requirement for img,img-bxm-4-64 is also ensured by adding it to the relevant allOf condition. Signed-off-by: Michal Wilczynski --- Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml index 4450e2e73b3ccf74d29f0e31e2e6687d7cbe5d65..c12837a0d39b8c3043b9133d444cc33a59135c33 100644 --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml @@ -26,6 +26,11 @@ properties: - ti,j721s2-gpu - const: img,img-bxs-4-64 - const: img,img-rogue + - items: + - enum: + - thead,th1520-gpu + - const: img,img-bxm-4-64 + - const: img,img-rogue # This legacy combination of compatible strings was introduced early on # before the more specific GPU identifiers were used. @@ -93,7 +98,9 @@ allOf: properties: compatible: contains: - const: img,img-axe-1-16m + enum: + - img,img-axe-1-16m + - img,img-bxm-4-64 then: properties: power-domains: From patchwork Thu May 29 22:23:52 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wilczynski X-Patchwork-Id: 893513 Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 615CF21FF4E for ; Thu, 29 May 2025 22:24:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.118.77.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748557458; cv=none; b=T7FEaXluReO05nG7FWM1NIbgabX2SoY3wpjlo3fh2AbN7AKsLvEaedG5Wm9r5MYh4SgjoMxpeG2I89iSkYds99dz7GEqZBtNEnMbgohObOKPpd9n2zc5zsmKt0Aqn+jBkCoF+aNLpQ2VW7q5VbhT2R6K9vbqg6NNSh4wo7ob0mo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748557458; c=relaxed/simple; bh=8ehvIhyMSQqVR119BSQV9qbRojv4D1Uow/adRa6T4EY=; h=From:Date:Subject:MIME-Version:Message-Id:In-Reply-To:To:Cc: Content-Type:References; b=lWNmekA7NoDt//6iqV+en3gxgTQDFgXmE5pW3VSQw//sOuHHVc6hPR48qw6xuAMppmJ0cNvgG8GvJNM7LTCm/bT+k1XQgZlPjQt5ziXJgZ9Ne18/AkRSDuZXr3wu+MTHzy1iJtUk6lcsflPps62oSgf/WHmD6dKwfflPDyzHjls= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=Bo1cbFTC; arc=none smtp.client-ip=210.118.77.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="Bo1cbFTC" Received: from eucas1p1.samsung.com (unknown [182.198.249.206]) by mailout2.w1.samsung.com (KnoxPortal) with ESMTP id 20250529222409euoutp02a25725bbedbe44a054ee3b768a080f30~EH7xxUeY50243002430euoutp02L for ; Thu, 29 May 2025 22:24:09 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout2.w1.samsung.com 20250529222409euoutp02a25725bbedbe44a054ee3b768a080f30~EH7xxUeY50243002430euoutp02L DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1748557449; bh=UtMJUuq6/j+HHS1BRexsXIMJEKVh/fKMbHv0hDIc9WQ=; h=From:Date:Subject:In-Reply-To:To:Cc:References:From; b=Bo1cbFTC/L2jtBQzgLE4qcGuhQaPqUydLGvl1eR5kYcegBYAbznwVpewNQjOM+yLp ChI8ODy+AELbT5s2uhpaO5+kogdPSCMAnn0n7Xlp2TAfEuLBdDDyMcftnrkQffezDa ToCcohPrYIOFrDPqBDdbftHrF4VTUawqSTw8bmBE= Received: from eusmtip2.samsung.com (unknown [203.254.199.222]) by eucas1p2.samsung.com (KnoxPortal) with ESMTPA id 20250529222407eucas1p233be883d7e84e5a000e4d44b37cf7265~EH7wSHjOI1565715657eucas1p2_; Thu, 29 May 2025 22:24:07 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250529222406eusmtip29a64f97e4cb0480e499cfbe8b47ef396~EH7vU3Abr3031530315eusmtip2M; Thu, 29 May 2025 22:24:06 +0000 (GMT) From: Michal Wilczynski Date: Fri, 30 May 2025 00:23:52 +0200 Subject: [PATCH v3 5/8] riscv: dts: thead: th1520: Add missing reset controller header include Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250530-apr_14_for_sending-v3-5-83d5744d997c@samsung.com> In-Reply-To: <20250530-apr_14_for_sending-v3-0-83d5744d997c@samsung.com> To: Drew Fustini , Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michal Wilczynski , Bartosz Golaszewski , Philipp Zabel , Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Ulf Hansson , Marek Szyprowski Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dri-devel@lists.freedesktop.org X-Mailer: b4 0.15-dev X-CMS-MailID: 20250529222407eucas1p233be883d7e84e5a000e4d44b37cf7265 X-Msg-Generator: CA X-RootMTR: 20250529222407eucas1p233be883d7e84e5a000e4d44b37cf7265 X-EPHeader: CA X-CMS-RootMailID: 20250529222407eucas1p233be883d7e84e5a000e4d44b37cf7265 References: <20250530-apr_14_for_sending-v3-0-83d5744d997c@samsung.com> TH1520_RESET_ID_GPU_CLKGEN and TH1520_RESET_ID_GPU are required for GPU power sequencing to work. To make these symbols available, add the necessary include for the T-HEAD TH1520 reset controller bindings. This change was dropped during conflict resolution [1]. [1] - https://lore.kernel.org/all/aAvfn2mq0Ksi8DF2@x1/ Signed-off-by: Michal Wilczynski --- arch/riscv/boot/dts/thead/th1520.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index 1db0054c4e093400e9dbebcee5fcfa5b5cae6e32..bdbb1b985b0b76cf669a9bf40c6ec37258329056 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include / { compatible = "thead,th1520"; From patchwork Thu May 29 22:23:53 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wilczynski X-Patchwork-Id: 893286 Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com [210.118.77.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 32F7D221557 for ; Thu, 29 May 2025 22:24:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.118.77.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748557459; cv=none; b=aMYVgIgIjrqQm9tsUB7pT7GQQyhhwk6D6vl+ACgC/LlyYuJoZgt3wKvZf1fup083ToDoAnOIEaak0hvJOEJ3uWPN4mj2YhHxYZIORIAT0V0ZNWQ0CNmadNxUNA852qSX7Yr9cM7+FhcR6e/Mziyk3SDgOKkDGVPtZDshE8ioCn0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748557459; c=relaxed/simple; bh=gzz08eHWwUxuY3CeJ2uiRThhY0/iCcyEUXquAUPnEIM=; h=From:Date:Subject:MIME-Version:Message-Id:In-Reply-To:To:Cc: Content-Type:References; b=IVnbvoEVwP3IOIIkjbicSfAlvlEOfvi5RdHW1yUsV/OsTs8DQh5rZDRDf4SfJqNrZ+CdPDMsI3Onl61Q3NH+CPRSA3IInCEkQJDPe3qtWFavskuchuItWJUjKG00TZPipu7gdbUzfBENqF1wYFsLFRoxYKx+CpuL0XZffNtDsIc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=dCo4LnRW; arc=none smtp.client-ip=210.118.77.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="dCo4LnRW" Received: from eucas1p2.samsung.com (unknown [182.198.249.207]) by mailout1.w1.samsung.com (KnoxPortal) with ESMTP id 20250529222410euoutp01c6e5eb0971f84d3a18d84bdd2ff67d11~EH7yc7t7V2316223162euoutp014 for ; Thu, 29 May 2025 22:24:10 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout1.w1.samsung.com 20250529222410euoutp01c6e5eb0971f84d3a18d84bdd2ff67d11~EH7yc7t7V2316223162euoutp014 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1748557450; bh=iDKUS4/W4anCMc9efhu9LJv9bqq+RveQHjm6X16x1K4=; h=From:Date:Subject:In-Reply-To:To:Cc:References:From; b=dCo4LnRWzbECCNOWoukauv0ANlBhHJGWGXYMXYvikk5a8fbpA1qqD2GfAAXzBWOys rsr1Zpl2JWu8UR1d44jOInxEDiWWpMxh+NJogCbgflXUJkfHDhKcGj7luBt/iHCwvY VfsgcaTRGxvXbIj4WJKpF2+BzBGZc854MbzVF70Q= Received: from eusmtip2.samsung.com (unknown [203.254.199.222]) by eucas1p2.samsung.com (KnoxPortal) with ESMTPA id 20250529222408eucas1p20f62cea4c9c64bb5dda6db1fd38fb333~EH7xQ4-m70456404564eucas1p2V; Thu, 29 May 2025 22:24:08 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250529222408eusmtip20e45fce43476667b7407ee8364f8de8a~EH7wV181P2867928679eusmtip2V; Thu, 29 May 2025 22:24:07 +0000 (GMT) From: Michal Wilczynski Date: Fri, 30 May 2025 00:23:53 +0200 Subject: [PATCH v3 6/8] riscv: dts: thead: Add GPU power sequencer node Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250530-apr_14_for_sending-v3-6-83d5744d997c@samsung.com> In-Reply-To: <20250530-apr_14_for_sending-v3-0-83d5744d997c@samsung.com> To: Drew Fustini , Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michal Wilczynski , Bartosz Golaszewski , Philipp Zabel , Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Ulf Hansson , Marek Szyprowski Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dri-devel@lists.freedesktop.org X-Mailer: b4 0.15-dev X-CMS-MailID: 20250529222408eucas1p20f62cea4c9c64bb5dda6db1fd38fb333 X-Msg-Generator: CA X-RootMTR: 20250529222408eucas1p20f62cea4c9c64bb5dda6db1fd38fb333 X-EPHeader: CA X-CMS-RootMailID: 20250529222408eucas1p20f62cea4c9c64bb5dda6db1fd38fb333 References: <20250530-apr_14_for_sending-v3-0-83d5744d997c@samsung.com> Add the device tree node for the T-HEAD TH1520 GPU power sequencer (gpu_pwrseq) to the th1520.dtsi file. This node instantiates the thead,th1520-gpu-pwrseq driver, which is responsible for managing the GPU's power-on/off sequence. The node specifies the gpu-clkgen reset, which is one of the resources controlled by this sequencer. Signed-off-by: Michal Wilczynski --- arch/riscv/boot/dts/thead/th1520.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index bdbb1b985b0b76cf669a9bf40c6ec37258329056..6170eec79e919b606a2046ac8f52db07e47ef441 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -238,6 +238,12 @@ aon: aon { #power-domain-cells = <1>; }; + gpu_pwrseq: pwrseq { + compatible = "thead,th1520-gpu-pwrseq"; + resets = <&rst TH1520_RESET_ID_GPU_CLKGEN>; + reset-names = "gpu-clkgen"; + }; + soc { compatible = "simple-bus"; interrupt-parent = <&plic>; From patchwork Thu May 29 22:23:54 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wilczynski X-Patchwork-Id: 893512 Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B627024EA9D for ; Thu, 29 May 2025 22:24:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.118.77.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748557460; cv=none; b=CQkc3l+30aJqdKILxvKG31IegCRewoH6oJzsQp645sx9jYxr7+BqNg3s2ixKhKAJYwszSSa13IyIMgC6jI/pfTHOEzPEHHz3k0SKJ+yRrrLTbXevJyCzjqvFHbPW5PKLUaYK+CY4V93MBrnDHpjEmHC7XeUWNmbq3mOV6KfOhJA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748557460; c=relaxed/simple; bh=d6wIdElBOLG6xQuvZ2bU9mvzEoZIWeAG2YgNqMUnmXw=; h=From:Date:Subject:MIME-Version:Message-Id:In-Reply-To:To:Cc: Content-Type:References; b=jMkjjRoRPpfW5i2qnCAnaRMsyT70QNHxWNvDKtlNcSRb9HiK8zEIBAnRXGnZmK86sQ0wJPaaJhAVaMsIw5J/QO02jS0plHk1mj0qS3hHyEDhiidosQJjAfGX2v70Yg4YfvRQJwzJ6Z6T4pCIRvLhJC0Oh/fNbU8jX+EGY99RtEU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=INdOF+Rf; arc=none smtp.client-ip=210.118.77.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="INdOF+Rf" Received: from eucas1p2.samsung.com (unknown [182.198.249.207]) by mailout2.w1.samsung.com (KnoxPortal) with ESMTP id 20250529222411euoutp02c912c34f2c625b206f41e0d978d5fe81~EH7zefHWn0242202422euoutp02S for ; Thu, 29 May 2025 22:24:11 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout2.w1.samsung.com 20250529222411euoutp02c912c34f2c625b206f41e0d978d5fe81~EH7zefHWn0242202422euoutp02S DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1748557451; bh=1ZbpOJ5cqo6u8v/Cxt565zQQp/mhmNI7EweztDD0hgk=; h=From:Date:Subject:In-Reply-To:To:Cc:References:From; b=INdOF+RfEFSSDdxXgb03n5NwmRKgpVTgTK1/EZwCkw21jLWXJeTO6RjCvGPAByNJz QDRrPbGT3nTCdAd/wdI1p1xCKYSg5s4bErbmLPLvbH9yVjlTkRxfpw8yeLNV9fa7r1 QDwBcalGIRk1fXDlz5/TWi7pQnFsSNJyYQBtRlHk= Received: from eusmtip2.samsung.com (unknown [203.254.199.222]) by eucas1p2.samsung.com (KnoxPortal) with ESMTPA id 20250529222410eucas1p2e1d41a2fc717caef1aed51367a7db944~EH7yOiEY10077600776eucas1p28; Thu, 29 May 2025 22:24:10 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250529222409eusmtip208fc59df153696657f5efe1ccf7cdbaa~EH7xUl_h23031530315eusmtip2N; Thu, 29 May 2025 22:24:09 +0000 (GMT) From: Michal Wilczynski Date: Fri, 30 May 2025 00:23:54 +0200 Subject: [PATCH v3 7/8] riscv: dts: thead: th1520: Add IMG BXM-4-64 GPU node Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250530-apr_14_for_sending-v3-7-83d5744d997c@samsung.com> In-Reply-To: <20250530-apr_14_for_sending-v3-0-83d5744d997c@samsung.com> To: Drew Fustini , Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michal Wilczynski , Bartosz Golaszewski , Philipp Zabel , Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Ulf Hansson , Marek Szyprowski Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dri-devel@lists.freedesktop.org X-Mailer: b4 0.15-dev X-CMS-MailID: 20250529222410eucas1p2e1d41a2fc717caef1aed51367a7db944 X-Msg-Generator: CA X-RootMTR: 20250529222410eucas1p2e1d41a2fc717caef1aed51367a7db944 X-EPHeader: CA X-CMS-RootMailID: 20250529222410eucas1p2e1d41a2fc717caef1aed51367a7db944 References: <20250530-apr_14_for_sending-v3-0-83d5744d997c@samsung.com> Add a device tree node for the IMG BXM-4-64 GPU present in the T-HEAD TH1520 SoC used by the Lichee Pi 4A board. This node enables support for the GPU using the drm/imagination driver. By adding this node, the kernel can recognize and initialize the GPU, providing graphics acceleration capabilities on the Lichee Pi 4A and other boards based on the TH1520 SoC. Add fixed clock gpu_mem_clk, as the MEM clock on the T-HEAD SoC can't be controlled programatically. Signed-off-by: Michal Wilczynski --- arch/riscv/boot/dts/thead/th1520.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index 6170eec79e919b606a2046ac8f52db07e47ef441..ee937bbdb7c08439a70306f035b1cc82ddb4bae2 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -225,6 +225,13 @@ aonsys_clk: clock-73728000 { #clock-cells = <0>; }; + gpu_mem_clk: mem-clk { + compatible = "fixed-clock"; + clock-frequency = <0>; + clock-output-names = "gpu_mem_clk"; + #clock-cells = <0>; + }; + stmmac_axi_config: stmmac-axi-config { snps,wr_osr_lmt = <15>; snps,rd_osr_lmt = <15>; @@ -504,6 +511,21 @@ clk: clock-controller@ffef010000 { #clock-cells = <1>; }; + gpu: gpu@ffef400000 { + compatible = "thead,th1520-gpu", "img,img-bxm-4-64", + "img,img-rogue"; + reg = <0xff 0xef400000 0x0 0x100000>; + interrupt-parent = <&plic>; + interrupts = <102 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_vo CLK_GPU_CORE>, + <&gpu_mem_clk>, + <&clk_vo CLK_GPU_CFG_ACLK>; + clock-names = "core", "mem", "sys"; + power-domains = <&aon TH1520_GPU_PD>; + power-domain-names = "a"; + resets = <&rst TH1520_RESET_ID_GPU>; + }; + rst: reset-controller@ffef528000 { compatible = "thead,th1520-reset"; reg = <0xff 0xef528000 0x0 0x4f>; From patchwork Thu May 29 22:23:55 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wilczynski X-Patchwork-Id: 893285 Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 75005220F4D for ; Thu, 29 May 2025 22:24:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.118.77.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748557461; cv=none; b=KawnB6WGdRxmCnO/yjuZnJKH5wlnK4RmFFoIZkYcGI3H93sXxYkAR1RZsa4+sWU3lvCdzYZeFSOqOEKw2yMT1ZNP4QvmR6O+ihl/bkOU+pj0WFWOSNZkPLnJ42vMUj5+AErZDq0HozoNEwPEySGkm4mCp3bxGCNeT2sUDHh076Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748557461; c=relaxed/simple; bh=1FOB/tgbWbr2J9qY9wwVwJjFsVMUQQmh0+XPdLjMp74=; h=From:Date:Subject:MIME-Version:Message-Id:In-Reply-To:To:Cc: Content-Type:References; b=FPpypbHBLsoswpWCE+oTRkeu7r7SZ57pjWrcWY3N8SUcAOEGDdcNRvMiRp4oeNQz7ldoyEe9oiQ7lKOzaSPbsq4gEje/NeMMLTf4DbG1RknE9dEqSvCqYC6P+BxZdtk63j9Rxh6jNqm990FTqNdxroyV74VikWsaqsWOblEb360= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=R1dO6qIx; arc=none smtp.client-ip=210.118.77.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="R1dO6qIx" Received: from eucas1p1.samsung.com (unknown [182.198.249.206]) by mailout2.w1.samsung.com (KnoxPortal) with ESMTP id 20250529222411euoutp022cd94fb4797ed3b6134736fbe926e52c~EH7z8hpGC2216022160euoutp024 for ; Thu, 29 May 2025 22:24:11 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout2.w1.samsung.com 20250529222411euoutp022cd94fb4797ed3b6134736fbe926e52c~EH7z8hpGC2216022160euoutp024 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1748557451; bh=5egH5KWzs9ZC7lOWXRNh1it6vTUa7BxSAQZBLKObvZA=; h=From:Date:Subject:In-Reply-To:To:Cc:References:From; b=R1dO6qIxkW3CQsa3OH9T1WJ45bAArBU4Lvvl6sEs95fbeHIspElrYf5YTB3AFTBQA nMPk73pelIdwVOusfMHmVC1V5r/mhYtwbUQ/EsNdfpiCXMHVGZ4rKWt5gW4QN7vLE+ triOhRZmPZ3e+G+IFMeNVjYHwlwYvKVyD7LLhMDo= Received: from eusmtip2.samsung.com (unknown [203.254.199.222]) by eucas1p2.samsung.com (KnoxPortal) with ESMTPA id 20250529222411eucas1p27e4b662d6f120c4e83d808cb03e4bb1e~EH7zNTci01565915659eucas1p2w; Thu, 29 May 2025 22:24:11 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250529222410eusmtip2679dfbe0e8921c3283af235ded40b4f8~EH7ySR5a32867928679eusmtip2W; Thu, 29 May 2025 22:24:10 +0000 (GMT) From: Michal Wilczynski Date: Fri, 30 May 2025 00:23:55 +0200 Subject: [PATCH v3 8/8] drm/imagination: Enable PowerVR driver for RISC-V Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250530-apr_14_for_sending-v3-8-83d5744d997c@samsung.com> In-Reply-To: <20250530-apr_14_for_sending-v3-0-83d5744d997c@samsung.com> To: Drew Fustini , Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michal Wilczynski , Bartosz Golaszewski , Philipp Zabel , Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Ulf Hansson , Marek Szyprowski Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dri-devel@lists.freedesktop.org X-Mailer: b4 0.15-dev X-CMS-MailID: 20250529222411eucas1p27e4b662d6f120c4e83d808cb03e4bb1e X-Msg-Generator: CA X-RootMTR: 20250529222411eucas1p27e4b662d6f120c4e83d808cb03e4bb1e X-EPHeader: CA X-CMS-RootMailID: 20250529222411eucas1p27e4b662d6f120c4e83d808cb03e4bb1e References: <20250530-apr_14_for_sending-v3-0-83d5744d997c@samsung.com> Several RISC-V boards feature Imagination GPUs that are compatible with the PowerVR driver. An example is the IMG BXM-4-64 GPU on the Lichee Pi 4A board. This commit adjusts the driver's Kconfig dependencies to allow the PowerVR driver to be compiled on the RISC-V architecture. By enabling compilation on RISC-V, we expand support for these GPUs, providing graphics acceleration capabilities and enhancing hardware compatibility on RISC-V platforms. Signed-off-by: Michal Wilczynski --- drivers/gpu/drm/imagination/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/imagination/Kconfig b/drivers/gpu/drm/imagination/Kconfig index 737ace77c4f1247c687cc1fde2f139fc2e118c50..3b773879d781b17549455fac252cec8adfd3a9c8 100644 --- a/drivers/gpu/drm/imagination/Kconfig +++ b/drivers/gpu/drm/imagination/Kconfig @@ -3,7 +3,7 @@ config DRM_POWERVR tristate "Imagination Technologies PowerVR (Series 6 and later) & IMG Graphics" - depends on ARM64 + depends on (ARM64 || RISCV) depends on DRM depends on PM select DRM_EXEC