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Tue, 3 Jun 2025 08:30:39 -0700 From: Akhil R To: , , , , , , , , , , , , CC: Akhil R Subject: [PATCH v4 1/3] dt-bindings: i2c: nvidia,tegra20-i2c: Specify the required properties Date: Tue, 3 Jun 2025 21:00:20 +0530 Message-ID: <20250603153022.39434-1-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.49.0 Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD7F:EE_|DS4PR12MB9681:EE_ X-MS-Office365-Filtering-Correlation-Id: d69b17c1-d7e4-4736-6d52-08dda2b3a572 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|376014|7416014|36860700013|82310400026|921020; X-Microsoft-Antispam-Message-Info: =?utf-8?q?gSdzp3FS92Z5tY0vvILWyTL2e6rrIJ7?= =?utf-8?q?3fj06OZnax04IE2KjzUxxTRFIw/t7003k5xIxoe5BAfetSKt6vbooE+Hb+g9vc3ER?= =?utf-8?q?OhPv+jVrAJg2d8fYDVHzjVS2iyhC/KItiOeEkN3goFi7HcBETgs9uGoDDnXPx4f2I?= =?utf-8?q?zUN02yvSF0N4BizHZ7X9PQLh7VGMtAbndmvgH+k0Lq8pB8bMhZQ8+/cpMzChytecM?= =?utf-8?q?sn9AhbKUxuTnjH1J2gNut/kwWjGEKek/yTypGGMj8tr3fUxkkNUitz7EK6Bz2PVAu?= =?utf-8?q?xN6MqwZsuyfd6XAA0+tlJakTy4Dfsw6gjhWBiLZDUkiDT+YgI+10cF7PN1lB1AD5H?= =?utf-8?q?A87/yJNMFskzwgYNKWRieDqnIP0j4APm5jHOJMg7MrSO7DCm97FmbTB0NG5NIYyfe?= =?utf-8?q?Jap1ohcZkoa7V6fleYDPJQK3bREAO1P7JmJYHP/qlhqb+/eIS8kQBJpOCv3sTDlEh?= =?utf-8?q?YxiVs/HozmyiioOP+YWPuIejDXfl6gZKdBBlwHfO9b0Baaa5CSvynJ3O06M1FLlPc?= =?utf-8?q?0P7wTDOQqQbcMCUlFo4ZY3SEVMJQ/GKoB8KH8i8cTORaHleyPVOJsMRXgSQGD/GAq?= =?utf-8?q?Vx1LIWsDYy8/f2UI3fq72gKhR3Ago/Etr5VZ6EXGnHKwEDrl7Jea4CcdvhKfAeVP1?= =?utf-8?q?AiAS0oY5DL3X67syBZY/qaujt8YP6TIrmeDHBcoEjbgNKrXIT8kZNXVRbTc3Jj4cL?= =?utf-8?q?0NxCrtypVdL41cDG502MF/wV1SJH6KLpkev417HbkpOR83ez3cZCq9XQfJwnHSvGC?= =?utf-8?q?7y5sDi8uaYumPZZn0dg8Ed1r2dJfZcRAaznHFM2C2WjKGoioKp++5s21qpZSK1ghZ?= =?utf-8?q?EQrl8Zgkcg/c68j8G2/qNf0rWIoiS0ezquP97Ies5j/UWiLGPP2b4gAyikUhMH1m+?= =?utf-8?q?qgmX3+l7R/7F9uKlnO4J/7pNrArknq/Md11VeLt1KNfivryjbE2+KT0Z+WOImqqFZ?= =?utf-8?q?ejEKMOyD8ovxPVUdwZNH+z0xtbrhCP0hTGoZHAgDI3iqz4eTMASQ5jwHvCWL2hNdS?= =?utf-8?q?4vj9yN5kE/JUUFDZ+Rp1/ozf3kUMXvDFUgmGL9JFFtEhjj76Ij3W/c9zfGe4rJ6v4?= =?utf-8?q?/IRKB1wKy0CXs3y+bOoMMDx9DOuMPD98Ak/fymO1cmNSz9m+9A5aJU/A98CjR9hgM?= =?utf-8?q?Gp47ZApK2SGTEjKam8teFteaUJ4b5jAHoGbax9nr7hcSnpudJFjmDKhy1BhwrQ+Lw?= =?utf-8?q?BwAaV8zNu+zqrJ735dhqJbqVYz8POB7BtAATyXnSSxZb37wZ77lRno7vRhb1GLZT4?= =?utf-8?q?jMNiQ0lp1WnDvNWTlvUs/gS7toIgvc3sYlAfj0YbiIOTot2NEZMr++OsOSZ+seKg8?= =?utf-8?q?HVSkqG+r2iGYhL45PxqShW9/RQzaONztkDSDqwWa6MIO6zn7NkSmVTyh1qy85husC?= =?utf-8?q?GJbmmnLGF9nwVRxSLkZFGoob1vWDq0Q8t3ErnUpBFXHVDfOZ0y71f1rjipJJ5x3mO?= =?utf-8?q?oRg5QZp2e0cF/UtJkbBVJk+jSIpvf6Aw=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.233; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge2.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(376014)(7416014)(36860700013)(82310400026)(921020); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Jun 2025 15:31:01.3665 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d69b17c1-d7e4-4736-6d52-08dda2b3a572 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.233]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7F.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS4PR12MB9681 Specify the properties which are essential and which are not for the Tegra I2C driver to function correctly. This was not added correctly when the TXT binding was converted to yaml. All the existing DT nodes have these properties already and hence this does not break the ABI. dmas and dma-names which were specified as a must in the TXT binding is now made optional since the driver can work in PIO mode if dmas are missing. Fixes: f10a9b722f80 ("dt-bindings: i2c: tegra: Convert to json-schema”) Signed-off-by: Akhil R Reviewed-by: Krzysztof Kozlowski --- v3->v4: * Updated commit message, and "description" section. v2->v3: * Updated commit description on the details and fixed indentation issue. v1->v2: * Added all required properties .../bindings/i2c/nvidia,tegra20-i2c.yaml | 24 ++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml index b57ae6963e62..10f30d6a1fad 100644 --- a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml @@ -97,7 +97,10 @@ properties: resets: items: - - description: module reset + - description: + Module reset. This property is optional for controllers in Tegra194, + Tegra234 etc where an internal software reset is available as an + alternative. reset-names: items: @@ -116,6 +119,13 @@ properties: - const: rx - const: tx +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + allOf: - $ref: /schemas/i2c/i2c-controller.yaml - if: @@ -169,6 +179,18 @@ allOf: properties: power-domains: false + - if: + not: + properties: + compatible: + contains: + enum: + - nvidia,tegra194-i2c + then: + required: + - resets + - reset-names + unevaluatedProperties: false examples: From patchwork Tue Jun 3 15:30:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil R X-Patchwork-Id: 893908 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2087.outbound.protection.outlook.com [40.107.243.87]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B8B4123BD0F; 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This is useful in systems that choose to restrict reset control from Linux. Signed-off-by: Akhil R --- v3->v4: No change v2->v3: No change v1->v2: * Call devm_reset_control_get_optional_exclusive() unconditionally. * Add more delay based on HW recommendation. drivers/i2c/busses/i2c-tegra.c | 33 +++++++++++++++++++++++++++++++-- 1 file changed, 31 insertions(+), 2 deletions(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 87976e99e6d0..22ddbae9d847 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -134,6 +134,8 @@ #define I2C_MST_FIFO_STATUS_TX GENMASK(23, 16) #define I2C_MST_FIFO_STATUS_RX GENMASK(7, 0) +#define I2C_MASTER_RESET_CNTRL 0x0a8 + /* configuration load timeout in microseconds */ #define I2C_CONFIG_LOAD_TIMEOUT 1000000 @@ -184,6 +186,9 @@ enum msg_end_type { * @has_mst_fifo: The I2C controller contains the new MST FIFO interface that * provides additional features and allows for longer messages to * be transferred in one go. + * @has_mst_reset: The I2C controller contains MASTER_RESET_CTRL register which + * provides an alternative to controller reset when configured as + * I2C master * @quirks: I2C adapter quirks for limiting write/read transfer size and not * allowing 0 length transfers. * @supports_bus_clear: Bus Clear support to recover from bus hang during @@ -213,6 +218,7 @@ struct tegra_i2c_hw_feature { bool has_multi_master_mode; bool has_slcg_override_reg; bool has_mst_fifo; + bool has_mst_reset; const struct i2c_adapter_quirks *quirks; bool supports_bus_clear; bool has_apb_dma; @@ -604,6 +610,20 @@ static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev *i2c_dev) return 0; } +static int tegra_i2c_master_reset(struct tegra_i2c_dev *i2c_dev) +{ + if (!i2c_dev->hw->has_mst_reset) + return -EOPNOTSUPP; + + i2c_writel(i2c_dev, 0x1, I2C_MASTER_RESET_CNTRL); + udelay(2); + + i2c_writel(i2c_dev, 0x0, I2C_MASTER_RESET_CNTRL); + udelay(2); + + return 0; +} + static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) { u32 val, clk_divisor, clk_multiplier, tsu_thd, tlow, thigh, non_hs_mode; @@ -621,8 +641,10 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) */ if (handle) err = acpi_evaluate_object(handle, "_RST", NULL, NULL); - else + else if (i2c_dev->rst) err = reset_control_reset(i2c_dev->rst); + else + err = tegra_i2c_master_reset(i2c_dev); WARN_ON_ONCE(err); @@ -1467,6 +1489,7 @@ static const struct tegra_i2c_hw_feature tegra20_i2c_hw = { .has_multi_master_mode = false, .has_slcg_override_reg = false, .has_mst_fifo = false, + .has_mst_reset = false, .quirks = &tegra_i2c_quirks, .supports_bus_clear = false, .has_apb_dma = true, @@ -1491,6 +1514,7 @@ static const struct tegra_i2c_hw_feature tegra30_i2c_hw = { .has_multi_master_mode = false, .has_slcg_override_reg = false, .has_mst_fifo = false, + .has_mst_reset = false, .quirks = &tegra_i2c_quirks, .supports_bus_clear = false, .has_apb_dma = true, @@ -1515,6 +1539,7 @@ static const struct tegra_i2c_hw_feature tegra114_i2c_hw = { .has_multi_master_mode = false, .has_slcg_override_reg = false, .has_mst_fifo = false, + .has_mst_reset = false, .quirks = &tegra_i2c_quirks, .supports_bus_clear = true, .has_apb_dma = true, @@ -1539,6 +1564,7 @@ static const struct tegra_i2c_hw_feature tegra124_i2c_hw = { .has_multi_master_mode = false, .has_slcg_override_reg = true, .has_mst_fifo = false, + .has_mst_reset = false, .quirks = &tegra_i2c_quirks, .supports_bus_clear = true, .has_apb_dma = true, @@ -1563,6 +1589,7 @@ static const struct tegra_i2c_hw_feature tegra210_i2c_hw = { .has_multi_master_mode = false, .has_slcg_override_reg = true, .has_mst_fifo = false, + .has_mst_reset = false, .quirks = &tegra_i2c_quirks, .supports_bus_clear = true, .has_apb_dma = true, @@ -1587,6 +1614,7 @@ static const struct tegra_i2c_hw_feature tegra186_i2c_hw = { .has_multi_master_mode = false, .has_slcg_override_reg = true, .has_mst_fifo = false, + .has_mst_reset = false, .quirks = &tegra_i2c_quirks, .supports_bus_clear = true, .has_apb_dma = false, @@ -1611,6 +1639,7 @@ static const struct tegra_i2c_hw_feature tegra194_i2c_hw = { .has_multi_master_mode = true, .has_slcg_override_reg = true, .has_mst_fifo = true, + .has_mst_reset = true, .quirks = &tegra194_i2c_quirks, .supports_bus_clear = true, .has_apb_dma = false, @@ -1666,7 +1695,7 @@ static int tegra_i2c_init_reset(struct tegra_i2c_dev *i2c_dev) if (ACPI_HANDLE(i2c_dev->dev)) return 0; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge2.nvidia.com; CAT:NONE; SFS:(13230040)(7416014)(376014)(36860700013)(82310400026)(1800799024)(921020); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Jun 2025 15:31:16.0456 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3db87b90-510c-41a1-4248-08dda2b3ae33 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.233]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7D.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7764 Calling dma_sync_*() on a buffer from dma_alloc_coherent() is pointless. The driver should not be doing its own bounce-buffering if the buffer is allocated through dma_alloc_coherent() Suggested-by: Robin Murphy Signed-off-by: Akhil R --- v3->v4: No change v2->v3: No change v1->v2: No change drivers/i2c/busses/i2c-tegra.c | 20 +------------------- 1 file changed, 1 insertion(+), 19 deletions(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 22ddbae9d847..b10a4bc9cb34 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -1292,17 +1292,9 @@ static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev, if (i2c_dev->dma_mode) { if (i2c_dev->msg_read) { - dma_sync_single_for_device(i2c_dev->dma_dev, - i2c_dev->dma_phys, - xfer_size, DMA_FROM_DEVICE); - err = tegra_i2c_dma_submit(i2c_dev, xfer_size); if (err) return err; - } else { - dma_sync_single_for_cpu(i2c_dev->dma_dev, - i2c_dev->dma_phys, - xfer_size, DMA_TO_DEVICE); } } @@ -1312,11 +1304,6 @@ static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev, if (i2c_dev->dma_mode) { memcpy(i2c_dev->dma_buf + I2C_PACKET_HEADER_SIZE, msg->buf, i2c_dev->msg_len); - - dma_sync_single_for_device(i2c_dev->dma_dev, - i2c_dev->dma_phys, - xfer_size, DMA_TO_DEVICE); - err = tegra_i2c_dma_submit(i2c_dev, xfer_size); if (err) return err; @@ -1357,13 +1344,8 @@ static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev, return -ETIMEDOUT; } - if (i2c_dev->msg_read && i2c_dev->msg_err == I2C_ERR_NONE) { - dma_sync_single_for_cpu(i2c_dev->dma_dev, - i2c_dev->dma_phys, - xfer_size, DMA_FROM_DEVICE); - + if (i2c_dev->msg_read && i2c_dev->msg_err == I2C_ERR_NONE) memcpy(i2c_dev->msg_buf, i2c_dev->dma_buf, i2c_dev->msg_len); - } } time_left = tegra_i2c_wait_completion(i2c_dev, &i2c_dev->msg_complete,