From patchwork Wed Jun 4 00:15:13 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 894026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 54E842C3251; Wed, 4 Jun 2025 00:18:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748996284; cv=none; b=C+M0H+dVTqzDNOJAwUamUQ+LHs7F/q6nf9A8Kn9RswU3uXro5zQGGBh10cZLqFImGGcL6lRggx8eOuZS42jQKqQbz+SW6xUTMc5spXuJr1r44XTWSz2W9iBss4P7Y3/VbGm9Ja4WiqkNclOAaO6EV6fdoT+4nrqqsFqugqtbGgM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748996284; c=relaxed/simple; bh=WlIPLmc/FFq62iCagksYCp6qUw2SVgS1XlRC8UQ86RY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=sKyuxoiVc1gPnhbA8BF8hsxsawgHMc4wfZ6/G+bv6GkG9XpyiCAMj/SLpnqzZkkiiT5Y627bcaNqhof24piPDVWPsLgaDxLVEOsxyqVq6pa6f8eWgfFJ4M0o0gENgubwvY+6Cj7nK+e9vgPuyOlQoiuifuuwGB9FLfJ+gy0qlmg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=OjQ+g6WJ; arc=none smtp.client-ip=198.175.65.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="OjQ+g6WJ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1748996283; x=1780532283; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=WlIPLmc/FFq62iCagksYCp6qUw2SVgS1XlRC8UQ86RY=; b=OjQ+g6WJBQCa9ERHE2/SiWMwYo2BG1zBVjbmzVCp0b+BMe++NJxY4mlv smFnycGz/oGGX2Fvnz8CeCStZ2zPIiagZEVeR93dNNChm/up74ns85Vi8 5Aqqw/dhWh3tRokmUj/2Wgc11PeHarBjf9I6abl37EIlGth1x4xR3yjX2 f/S8H3mfJybjjjNZt2AG10qrxvIQQ+OgtCxvbn8BTc0ZNVkA0/dcTg4kU u76Dro0JYD2AQj9TFf3T8a/opJnxFf6oluXM2y5v7U0v/jGMxCdkhO0cz p0h1uce0rQBeNE8GLhPGi3xkMMG8IPH1MOUnY57Ua+Jsnz0aBx5ko67lq A==; X-CSE-ConnectionGUID: plUX8MMAQ4a6KsMt258sew== X-CSE-MsgGUID: E6Q0aKIMRa2EgP7VvPWeqw== X-IronPort-AV: E=McAfee;i="6700,10204,11453"; a="62112927" X-IronPort-AV: E=Sophos;i="6.16,207,1744095600"; d="scan'208";a="62112927" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2025 17:18:01 -0700 X-CSE-ConnectionGUID: Zq9LiRrKR3O6C1R9Li/Tcw== X-CSE-MsgGUID: bFGiFZfiSz6RUM6oQ5bwdA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,207,1744095600"; d="scan'208";a="149904451" Received: from unknown (HELO [172.25.112.21]) ([172.25.112.21]) by fmviesa005.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2025 17:18:00 -0700 From: Ricardo Neri Date: Tue, 03 Jun 2025 17:15:13 -0700 Subject: [PATCH v4 01/10] x86/acpi: Add a helper functions to setup and access the wakeup mailbox Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250603-rneri-wakeup-mailbox-v4-1-d533272b7232@linux.intel.com> References: <20250603-rneri-wakeup-mailbox-v4-0-d533272b7232@linux.intel.com> In-Reply-To: <20250603-rneri-wakeup-mailbox-v4-0-d533272b7232@linux.intel.com> To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley , "Rafael J. Wysocki" Cc: Saurabh Sengar , Chris Oo , "Kirill A. Shutemov" , linux-hyperv@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, "Ravi V. Shankar" , Ricardo Neri , Ricardo Neri X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748996287; l=3940; i=ricardo.neri-calderon@linux.intel.com; s=20250602; h=from:subject:message-id; bh=WlIPLmc/FFq62iCagksYCp6qUw2SVgS1XlRC8UQ86RY=; b=OSOBVCV+0Em4QTXbhjXb/J+EoNF3QP2p8VNGT+Z1LJIjU5aqld4VELjoZBgn0IIhZe3X1dnhU RLgOMPg89OeB0PxRnPZNQq4Rn4RhHYRc1rNAB9P0ffvz9luLB5rKlNx X-Developer-Key: i=ricardo.neri-calderon@linux.intel.com; a=ed25519; pk=NfZw5SyQ2lxVfmNMaMR6KUj3+0OhcwDPyRzFDH9gY2w= In preparation to move the functionality to wake secondary CPUs up out of the ACPI code, add two helper functions. The function acpi_setup_mp_wakeup_mailbox() stores the physical address of the mailbox and updates the wakeup_secondary_cpu_64() APIC callback. There is a slight change in behavior: now the APIC callback is updated before configuring CPU hotplug offline behavior. This is fine as the APIC callback continues to be updated unconditionally, regardless of the restriction on CPU offlining. The function acpi_madt_multiproc_wakeup_mailbox() returns a pointer to the mailbox. Use this helper function only in the portions of the code for which the variable acpi_mp_wake_mailbox will be out of scope once it is relocated out of the ACPI directory. The wakeup mailbox is only supported for CONFIG_X86_64 and needed only with CONFIG_SMP=y. Signed-off-by: Ricardo Neri --- Changes since v3: - Squashed the two first patches of the series into one, both introduce helper functions. (Rafael) - Renamed setup_mp_wakeup_mailbox() as acpi_setup_mp_wakeup_mailbox(). (Rafael) - Dropped the function prototype for !CONFIG_X86_64. (Rafael) Changes since v2: - Introduced this patch. Changes since v1: - N/A --- arch/x86/include/asm/smp.h | 3 +++ arch/x86/kernel/acpi/madt_wakeup.c | 20 +++++++++++++++----- 2 files changed, 18 insertions(+), 5 deletions(-) diff --git a/arch/x86/include/asm/smp.h b/arch/x86/include/asm/smp.h index 0c1c68039d6f..77dce560a70a 100644 --- a/arch/x86/include/asm/smp.h +++ b/arch/x86/include/asm/smp.h @@ -146,6 +146,9 @@ static inline struct cpumask *cpu_l2c_shared_mask(int cpu) return per_cpu(cpu_l2c_shared_map, cpu); } +void acpi_setup_mp_wakeup_mailbox(u64 addr); +struct acpi_madt_multiproc_wakeup_mailbox *acpi_get_mp_wakeup_mailbox(void); + #else /* !CONFIG_SMP */ #define wbinvd_on_cpu(cpu) wbinvd() static inline int wbinvd_on_all_cpus(void) diff --git a/arch/x86/kernel/acpi/madt_wakeup.c b/arch/x86/kernel/acpi/madt_wakeup.c index f36f28405dcc..4033c804307a 100644 --- a/arch/x86/kernel/acpi/madt_wakeup.c +++ b/arch/x86/kernel/acpi/madt_wakeup.c @@ -37,6 +37,7 @@ static void acpi_mp_play_dead(void) static void acpi_mp_cpu_die(unsigned int cpu) { + struct acpi_madt_multiproc_wakeup_mailbox *mailbox = acpi_get_mp_wakeup_mailbox(); u32 apicid = per_cpu(x86_cpu_to_apicid, cpu); unsigned long timeout; @@ -46,13 +47,13 @@ static void acpi_mp_cpu_die(unsigned int cpu) * * BIOS has to clear 'command' field of the mailbox. */ - acpi_mp_wake_mailbox->apic_id = apicid; - smp_store_release(&acpi_mp_wake_mailbox->command, + mailbox->apic_id = apicid; + smp_store_release(&mailbox->command, ACPI_MP_WAKE_COMMAND_TEST); /* Don't wait longer than a second. */ timeout = USEC_PER_SEC; - while (READ_ONCE(acpi_mp_wake_mailbox->command) && --timeout) + while (READ_ONCE(mailbox->command) && --timeout) udelay(1); if (!timeout) @@ -227,7 +228,7 @@ int __init acpi_parse_mp_wake(union acpi_subtable_headers *header, acpi_table_print_madt_entry(&header->common); - acpi_mp_wake_mailbox_paddr = mp_wake->mailbox_address; + acpi_setup_mp_wakeup_mailbox(mp_wake->mailbox_address); if (mp_wake->version >= ACPI_MADT_MP_WAKEUP_VERSION_V1 && mp_wake->header.length >= ACPI_MADT_MP_WAKEUP_SIZE_V1) { @@ -243,7 +244,16 @@ int __init acpi_parse_mp_wake(union acpi_subtable_headers *header, acpi_mp_disable_offlining(mp_wake); } + return 0; +} + +void __init acpi_setup_mp_wakeup_mailbox(u64 mailbox_paddr) +{ + acpi_mp_wake_mailbox_paddr = mailbox_paddr; apic_update_callback(wakeup_secondary_cpu_64, acpi_wakeup_cpu); +} - return 0; +struct acpi_madt_multiproc_wakeup_mailbox *acpi_get_mp_wakeup_mailbox(void) +{ + return acpi_mp_wake_mailbox; } From patchwork Wed Jun 4 00:15:15 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 894025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D23F379F5; Wed, 4 Jun 2025 00:18:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748996285; cv=none; b=JIpVniCEmn15C9vJzfNB4bB1a5842VvIk9E5hdAas7pks+l1TGCcRIW0NJbj2p+1a1wLcZlVLHfC2c4z4UY+AtuL3Xue2s5lMMkbe38iya2Gid0V/FkZl7VniKgmrdyRxXZA9wft0PzFfgALTKWnoBoJpl6DprglMxZpkapvpb0= ARC-Message-Signature: i=1; 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d="scan'208";a="149904458" Received: from unknown (HELO [172.25.112.21]) ([172.25.112.21]) by fmviesa005.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2025 17:18:00 -0700 From: Ricardo Neri Date: Tue, 03 Jun 2025 17:15:15 -0700 Subject: [PATCH v4 03/10] dt-bindings: reserved-memory: Wakeup Mailbox for Intel processors Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250603-rneri-wakeup-mailbox-v4-3-d533272b7232@linux.intel.com> References: <20250603-rneri-wakeup-mailbox-v4-0-d533272b7232@linux.intel.com> In-Reply-To: <20250603-rneri-wakeup-mailbox-v4-0-d533272b7232@linux.intel.com> To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley , "Rafael J. Wysocki" Cc: Saurabh Sengar , Chris Oo , "Kirill A. Shutemov" , linux-hyperv@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, "Ravi V. Shankar" , Ricardo Neri , Yunhong Jiang , Ricardo Neri X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748996287; l=4376; i=ricardo.neri-calderon@linux.intel.com; s=20250602; h=from:subject:message-id; bh=vvzYz3uQ9MMaozEQnAeRM+GHHaJn/qRlXLRb/AZhEXU=; b=siYJEvDiKe+DCn4lcO2uPx6gRKyuWl+gMC+a9Alta4m8j0lQm1lqxadUmd+iFDNL+2Pi3JOgi PB/otJXRApoAc0Yp3dp/Gi29aWYTS+cdw7lqh56cjTOK7N9X7qBvGjl X-Developer-Key: i=ricardo.neri-calderon@linux.intel.com; a=ed25519; pk=NfZw5SyQ2lxVfmNMaMR6KUj3+0OhcwDPyRzFDH9gY2w= Add DeviceTree bindings to enumerate the wakeup mailbox used in platform firmware for Intel processors. x86 platforms commonly boot secondary CPUs using an INIT assert, de-assert followed by Start-Up IPI messages. The wakeup mailbox can be used when this mechanism is unavailable. The wakeup mailbox offers more control to the operating system to boot secondary CPUs than a spin-table. It allows the reuse of same wakeup vector for all CPUs while maintaining control over which CPUs to boot and when. While it is possible to achieve the same level of control using a spin- table, it would require to specify a separate `cpu-release-addr` for each secondary CPU. The operation and structure of the mailbox is described in the Multiprocessor Wakeup Structure defined in the ACPI specification. Note that this structure does not specify how to publish the mailbox to the operating system (ACPI-based platform firmware uses a separate table). No ACPI table is needed in DeviceTree-based firmware to enumerate the mailbox. Add a `compatible` property that the operating system can use to discover the mailbox. Nodes wanting to refer to the reserved memory usually define a `memory-region` property. /cpus/cpu* nodes would want to refer to the mailbox, but they do not have such property defined in the DeviceTree specification. Moreover, it would imply that there is a memory region per CPU. Co-developed-by: Yunhong Jiang Signed-off-by: Yunhong Jiang Signed-off-by: Ricardo Neri --- Changes since v3: - Removed redefinitions of the mailbox and instead referred to ACPI specification as per discussion on LKML. - Clarified that DeviceTree-based firmware do not require the use of ACPI tables to enumerate the mailbox. (Rob) - Described the need of using a `compatible` property. - Dropped the `alignment` property. (Krzysztof, Rafael) - Used a real address for the mailbox node. (Krzysztof) Changes since v2: - Implemented the mailbox as a reserved-memory node. Add to it a `compatible` property. (Krzysztof) - Explained the relationship between the mailbox and the `enable-mehod` property of the CPU nodes. - Expanded the documentation of the binding. Changes since v1: - Added more details to the description of the binding. - Added requirement a new requirement for cpu@N nodes to add an `enable-method`. --- .../reserved-memory/intel,wakeup-mailbox.yaml | 48 ++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/Documentation/devicetree/bindings/reserved-memory/intel,wakeup-mailbox.yaml b/Documentation/devicetree/bindings/reserved-memory/intel,wakeup-mailbox.yaml new file mode 100644 index 000000000000..f18643805866 --- /dev/null +++ b/Documentation/devicetree/bindings/reserved-memory/intel,wakeup-mailbox.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reserved-memory/intel,wakeup-mailbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Wakeup Mailbox for Intel processors + +description: | + The Wakeup Mailbox provides a mechanism for the operating system to wake up + secondary CPUs on Intel processors. It is an alternative to the INIT-!INIT- + SIPI sequence used on most x86 systems. + + The structure and operation of the mailbox is described in the Multiprocessor + Wakeup Structure of the ACPI specification. + + The implementation of the mailbox in platform firmware is described in the + Intel TDX Virtual Firmware Design Guide section 4.3.5. + + See https://www.intel.com/content/www/us/en/content-details/733585/intel-tdx-virtual-firmware-design-guide.html + +maintainers: + - Ricardo Neri + +allOf: + - $ref: reserved-memory.yaml + +properties: + compatible: + const: intel,wakeup-mailbox + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + reserved-memory { + #address-cells = <2>; + #size-cells = <1>; + + wakeup-mailbox@ffff0000 { + compatible = "intel,wakeup-mailbox"; + reg = <0x0 0xffff0000 0x1000>; + }; + }; From patchwork Wed Jun 4 00:15:17 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 894024 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 78B341BC5C; Wed, 4 Jun 2025 00:18:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748996287; cv=none; b=kYljDw/LNa+l5h9nAs7+qqEG4C+J8ckStA37KYlOmw/6iO+epIZoNLD566qOsEKrdO5OniaN8/7fB+yFTrb9iiObcF5Wme5qV43nTxXeiIzMXNw1X+IIjow4NyoEoCAwVfzIMC185UtDF97LD9q0d9pO5huQLjNbvslD/vESN7E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748996287; c=relaxed/simple; bh=NWTFVdsTu15JID3vMZXamOvuYlBjkvLIfQE8cTt7NKg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=iW41UwodfQn+FcQTnzwFBHcQXhxsM5icu4xCCjgcf2E+PgZ0GxrdsQn9S/ppmyOIJASM/0lGdqphROvmF2yw95HWU2zajySwVs26p3xrZrKPNYzW16Ge4QTuquJG+TDWXmc6zEsGRzsn99T9rene8jQEi7kkF0UH/EnZF1S5fE0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=nBp4DTF8; arc=none smtp.client-ip=198.175.65.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="nBp4DTF8" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1748996286; x=1780532286; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=NWTFVdsTu15JID3vMZXamOvuYlBjkvLIfQE8cTt7NKg=; b=nBp4DTF8zvNwzJiP+1/a7ecP/O/bAxoMaF6VX3Z2VBuuAIaXWgaKgE1p wfEb3Fz97p+fmavB7asGrgbV59/WLWLNTu2849hAlWcqegIur9/b1Kjj2 WW2GOfc57FI3bAQsYbyC7EuEztgbxyZEKU6XTioFUGAzvyoRShHDPg+iD 7MSfDg2BQhuPANhgw4DiQY236nANwxF7F0m6pfShjqzKrsr6zOHkwyOOv GdFk9YzF/5raGsch19/NY2v88a/TlTyhYNZusnvZWVLCia0vy77i2rErB G5R4EpBlBiWvfaCifY6kJDIV0IW0ghRzv0049MH3vVbZa6haZszcJi5Dv g==; X-CSE-ConnectionGUID: XTn8HViyQ2uEtSFW6gZFHg== X-CSE-MsgGUID: i3wW5Ai0Q32zmb/7s3MXJw== X-IronPort-AV: E=McAfee;i="6700,10204,11453"; a="62112953" X-IronPort-AV: E=Sophos;i="6.16,207,1744095600"; d="scan'208";a="62112953" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2025 17:18:02 -0700 X-CSE-ConnectionGUID: FytyVrbJSn6EQTC47ZrZ3A== X-CSE-MsgGUID: 3aQpAMD1TWSq/JeozQXYyw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,207,1744095600"; d="scan'208";a="149904467" Received: from unknown (HELO [172.25.112.21]) ([172.25.112.21]) by fmviesa005.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2025 17:18:01 -0700 From: Ricardo Neri Date: Tue, 03 Jun 2025 17:15:17 -0700 Subject: [PATCH v4 05/10] x86/hyperv/vtl: Set real_mode_header in hv_vtl_init_platform() Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250603-rneri-wakeup-mailbox-v4-5-d533272b7232@linux.intel.com> References: <20250603-rneri-wakeup-mailbox-v4-0-d533272b7232@linux.intel.com> In-Reply-To: <20250603-rneri-wakeup-mailbox-v4-0-d533272b7232@linux.intel.com> To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley , "Rafael J. Wysocki" Cc: Saurabh Sengar , Chris Oo , "Kirill A. Shutemov" , linux-hyperv@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, "Ravi V. Shankar" , Ricardo Neri , Yunhong Jiang , Thomas Gleixner , Ricardo Neri X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748996287; l=1988; i=ricardo.neri-calderon@linux.intel.com; s=20250602; h=from:subject:message-id; bh=NksHFVn/eI0Fawofj7b00BEZiD32GqG4d/7RPbAEdi8=; b=MN+Qd6iKIzbJOTMiDJkH7medS+yCAXXXI1B2TzD3+vzND9xt24W4AWRTAtiLpb3eCFprENtUf 4lqo5BemmKJB3tL5Egmg24JdKGJDMEGcPaiHzQcQcuj3VN/cpby/Ab8 X-Developer-Key: i=ricardo.neri-calderon@linux.intel.com; a=ed25519; pk=NfZw5SyQ2lxVfmNMaMR6KUj3+0OhcwDPyRzFDH9gY2w= From: Yunhong Jiang Hyper-V VTL clears x86_platform.realmode_{init(), reserve()} in hv_vtl_platform_init() whereas it sets real_mode_header later in hv_vtl_early_init(). There is no need to deal with the real mode memory in two places: x86_platform.realmode_init() is invoked much later via an early_initcall. Set real_mode_header in hv_vtl_init_platform() to keep all code dealing with memory for the real mode trampoline in one place. Besides making the code more readable, it prepares it for a subsequent changeset in which the behavior needs to change to support Hyper-V VTL guests in TDX environment. Reviewed-by: Michael Kelley Suggested-by: Thomas Gleixner Signed-off-by: Yunhong Jiang Signed-off-by: Ricardo Neri --- Changes since v3: - Added Reviewed-by tag from Michael. Thanks! Changes since v2: - Edited the commit message for clarity. Changes since v1: - Introduced this patch. --- arch/x86/hyperv/hv_vtl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/hyperv/hv_vtl.c b/arch/x86/hyperv/hv_vtl.c index 4580936dcb03..6bd183ee484f 100644 --- a/arch/x86/hyperv/hv_vtl.c +++ b/arch/x86/hyperv/hv_vtl.c @@ -60,6 +60,7 @@ void __init hv_vtl_init_platform(void) x86_platform.realmode_reserve = x86_init_noop; x86_platform.realmode_init = x86_init_noop; + real_mode_header = &hv_vtl_real_mode_header; x86_init.irqs.pre_vector_init = x86_init_noop; x86_init.timers.timer_init = x86_init_noop; x86_init.resources.probe_roms = x86_init_noop; @@ -279,7 +280,6 @@ int __init hv_vtl_early_init(void) panic("XSAVE has to be disabled as it is not supported by this module.\n" "Please add 'noxsave' to the kernel command line.\n"); - real_mode_header = &hv_vtl_real_mode_header; apic_update_callback(wakeup_secondary_cpu_64, hv_vtl_wakeup_secondary_cpu); return 0; From patchwork Wed Jun 4 00:15:19 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 894023 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EA8963595A; Wed, 4 Jun 2025 00:18:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748996287; cv=none; b=FIUWqdbXCTkwceqnsUIBtASsO+rW926ycFYsV8yrrIJV2Rs8iO97xESMixvuoNNDNL8v+3wb7jh8at0gcu5KWt2NWCQLlWBgaEAKn1IbC7lIljAzM/fg0csmjqgra2iZWi3Du8tUBYSC1jTSjCoM0k8s+hNy9RtOtYBNAXIegoI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748996287; c=relaxed/simple; bh=KV3C22xeOFoKXBk/U+nLRQtAIIYTiSgcSALyUOXxLKU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ji0U10D4myCAVQz0PNt/2U+yTTCg0IMlZWIlLusLjw2e+fj4CM8HgP1K/J8F/MnrmLOOuJOPNins6QcDrO34VItsS0HPrjEzFy2LWQQp7hwMsu4GSMEjfKkXf0kNU4GXURgWne97Zgdp19XY8uirAtntO7eSt4Kb3ppP+saLD+4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=I7D8XiPy; arc=none smtp.client-ip=198.175.65.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="I7D8XiPy" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1748996286; x=1780532286; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=KV3C22xeOFoKXBk/U+nLRQtAIIYTiSgcSALyUOXxLKU=; b=I7D8XiPyb8e38Akfwqk3anTDmcDpBo2mJ6/QXiaa6vnyTzQbX+mmDk2k d4NPxscX5ftciO1zYqF8DEoxQfcTMzRORjSMYb6TU2R3UWUgpN+yoFcAm Bd3BrZjrKtUi36z1QocdLf1jclgAP2dD1E12fGATZ8AARVW+bz86glAGI pdzA9oodcGjLWV9KgDP3dWK3QzBuPmaZ7lTpUIx0kBl4eRjIAFjW/HsZu mHiL6awKc4X5VFCELjNpd5kOX1bWEQTSf2fXWY038WQ1EZeThT2OCTe56 CACOYQVQg4M6aX5BveIQPPnHBFZALt5gZvyLdhFbG5akgu5M5bYEljHRy A==; X-CSE-ConnectionGUID: dz7r1JGgTUOchLNDkLXeCg== X-CSE-MsgGUID: edjBSBV9Sp6MwDlnrZedFQ== X-IronPort-AV: E=McAfee;i="6700,10204,11453"; a="62112963" X-IronPort-AV: E=Sophos;i="6.16,207,1744095600"; d="scan'208";a="62112963" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2025 17:18:02 -0700 X-CSE-ConnectionGUID: zTf4k3h6TjGu+vnS7EEd9Q== X-CSE-MsgGUID: /63SA10USl2JM0T6K3F+qg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,207,1744095600"; d="scan'208";a="149904476" Received: from unknown (HELO [172.25.112.21]) ([172.25.112.21]) by fmviesa005.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2025 17:18:01 -0700 From: Ricardo Neri Date: Tue, 03 Jun 2025 17:15:19 -0700 Subject: [PATCH v4 07/10] x86/hyperv/vtl: Setup the 64-bit trampoline for TDX guests Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250603-rneri-wakeup-mailbox-v4-7-d533272b7232@linux.intel.com> References: <20250603-rneri-wakeup-mailbox-v4-0-d533272b7232@linux.intel.com> In-Reply-To: <20250603-rneri-wakeup-mailbox-v4-0-d533272b7232@linux.intel.com> To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley , "Rafael J. Wysocki" Cc: Saurabh Sengar , Chris Oo , "Kirill A. Shutemov" , linux-hyperv@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, "Ravi V. Shankar" , Ricardo Neri , Yunhong Jiang , Ricardo Neri X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748996287; l=2512; i=ricardo.neri-calderon@linux.intel.com; s=20250602; h=from:subject:message-id; bh=cwjzbQJMuckUfYrMyGEivmvlDqF1G7Qp0Q7oqGDvum0=; b=iOiCh0sBp1vME5V7EgWP7K/SYZ9V0T2RvZgXULmi9oV7K8jmbntaWo8lLvDgOrtCv3sOa+yWr nsbZSp7iGfsBGOw+pVcZaxYYEU9YnmTOvTqfQptW1b2p2y4fLhUb57i X-Developer-Key: i=ricardo.neri-calderon@linux.intel.com; a=ed25519; pk=NfZw5SyQ2lxVfmNMaMR6KUj3+0OhcwDPyRzFDH9gY2w= From: Yunhong Jiang The hypervisor is an untrusted entity for TDX guests. It cannot be used to boot secondary CPUs - neither via hypercalls not the INIT assert, de-assert plus Start-Up IPI messages. Instead, the platform virtual firmware boots the secondary CPUs and puts them in a state to transfer control to the kernel. This mechanism uses the wakeup mailbox described in the Multiprocessor Wakeup Structure of the ACPI specification. The entry point to the kernel is trampoline_start64. Allocate and setup the trampoline using the default x86_platform callbacks. The platform firmware configures the secondary CPUs in long mode. It is no longer necessary to locate the trampoline under 1MB memory. After handoff from firmware, the trampoline code switches briefly to 32-bit addressing mode, which has an addressing limit of 4GB. Set the upper bound of the trampoline memory accordingly. Reviewed-by: Michael Kelley Signed-off-by: Yunhong Jiang Signed-off-by: Ricardo Neri --- Changes since v3: - Added Reviewed-by tag from Michael. Thanks! Changes since v2: - Added a note regarding there is no need to check for a present paravisor. - Edited commit message for clarity. Changes since v1: - Dropped the function hv_reserve_real_mode(). Instead, used the new members realmode_limit and reserve_bios members of x86_init to set the upper bound of the trampoline memory. (Thomas) --- arch/x86/hyperv/hv_vtl.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/x86/hyperv/hv_vtl.c b/arch/x86/hyperv/hv_vtl.c index 6bd183ee484f..8b497c8292d3 100644 --- a/arch/x86/hyperv/hv_vtl.c +++ b/arch/x86/hyperv/hv_vtl.c @@ -58,9 +58,14 @@ void __init hv_vtl_init_platform(void) { pr_info("Linux runs in Hyper-V Virtual Trust Level\n"); - x86_platform.realmode_reserve = x86_init_noop; - x86_platform.realmode_init = x86_init_noop; - real_mode_header = &hv_vtl_real_mode_header; + /* There is no paravisor present if we are here. */ + if (hv_isolation_type_tdx()) { + x86_init.resources.realmode_limit = SZ_4G; + } else { + x86_platform.realmode_reserve = x86_init_noop; + x86_platform.realmode_init = x86_init_noop; + real_mode_header = &hv_vtl_real_mode_header; + } x86_init.irqs.pre_vector_init = x86_init_noop; x86_init.timers.timer_init = x86_init_noop; x86_init.resources.probe_roms = x86_init_noop; From patchwork Wed Jun 4 00:15:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 894022 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8032D78F5E; Wed, 4 Jun 2025 00:18:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748996289; cv=none; b=TBYFuLNbLnUdkGNL/edLgfE4QRf4i41+T+vAy/3QLCuriKHub9FU4l3b87KsC8gRPCZs4GrrVCRtBr8frzk7/oMaLK3Tmm5TMGA9zE7W9dUu7bv8Hz+rdPe9CPz5T4dXqIupeIyOWXHoFb79GQK4Qxq2rQdQ4UJhXcPCT1VSCrI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748996289; c=relaxed/simple; bh=ahMl9gGZluKayAijS2KHGKWb3QX1PeyP1wqA7nZwVBg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=eHiEMGBqf3OHhQ7d2yg7mPqQpgTRj9CIP0u8rtgW5z4MKL33PFhKtOnN/GYNxAz8vYMBB6i9sexx5uUtSXl4ZJOYziynlxVQENVzrMIHZWGONtdkFlR2Acb6rBCPmG8+Raq86Zf0eJgTiVTBSXevh+kTqGhzaAZBlG4r+TSzGQc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=K99x7mJt; arc=none smtp.client-ip=198.175.65.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="K99x7mJt" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1748996288; x=1780532288; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=ahMl9gGZluKayAijS2KHGKWb3QX1PeyP1wqA7nZwVBg=; b=K99x7mJt8/2wUpgWOUP6SQTQSa15em2y9fMXS12F9+NZXvqRNjJ8OgUm z+Ovx8WY0qD+kY0iTMuqlHPvcJ/O8meZHStjjZ0//LcmnN8StAnSkoZ39 FPJq1pV05dHkm+qbSplBHcbwYNnFrOpwwLNfiOZlmY2dp+OXyUlp/+eWh eA9EZqtNyiDt3m1g4nB8/xSetHL1FiAnGLmwiXANyGKF/TbQaBXZJ7MFS 13NGegkZCqvrxow6z03x+OrvvxLrlL3zPJoZybaDvnNCScU4YlslbOwOy gGC7zrL3biD0/U8cWH+PxSWSqgDUdR5tjDVZkyHTrE36+T3xwDfnoHtso g==; X-CSE-ConnectionGUID: w41gQkwnRm+XiZxxYSm8xQ== X-CSE-MsgGUID: ssOr0ge8T1+I3a5zrviMEA== X-IronPort-AV: E=McAfee;i="6700,10204,11453"; a="62112972" X-IronPort-AV: E=Sophos;i="6.16,207,1744095600"; d="scan'208";a="62112972" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2025 17:18:02 -0700 X-CSE-ConnectionGUID: o7KteomWTiqC13zvEWT8Wg== X-CSE-MsgGUID: mvkNHSwNQEeigQfJHs5PAw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,207,1744095600"; d="scan'208";a="149904483" Received: from unknown (HELO [172.25.112.21]) ([172.25.112.21]) by fmviesa005.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2025 17:18:01 -0700 From: Ricardo Neri Date: Tue, 03 Jun 2025 17:15:21 -0700 Subject: [PATCH v4 09/10] x86/hyperv/vtl: Mark the wakeup mailbox page as private Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250603-rneri-wakeup-mailbox-v4-9-d533272b7232@linux.intel.com> References: <20250603-rneri-wakeup-mailbox-v4-0-d533272b7232@linux.intel.com> In-Reply-To: <20250603-rneri-wakeup-mailbox-v4-0-d533272b7232@linux.intel.com> To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley , "Rafael J. Wysocki" Cc: Saurabh Sengar , Chris Oo , "Kirill A. Shutemov" , linux-hyperv@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, "Ravi V. Shankar" , Ricardo Neri , Yunhong Jiang , Ricardo Neri X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748996287; l=2300; i=ricardo.neri-calderon@linux.intel.com; s=20250602; h=from:subject:message-id; bh=bKxLwQiFT1mEsXYGzQ6fKI1YFK6+0GKv4TRntu2AgMw=; b=1/Up4bCIx6mjNMhO3/oBdQNhSi1JTQh0eBL63IT62HJsLKEIAIhu05Pw+DbatnHJ9Z2zHctxn /Bu7utPgztACFr6NPwggXF+tRgD5FLgG6C4BhnOuuf8o2Z+maIsN9T0 X-Developer-Key: i=ricardo.neri-calderon@linux.intel.com; a=ed25519; pk=NfZw5SyQ2lxVfmNMaMR6KUj3+0OhcwDPyRzFDH9gY2w= From: Yunhong Jiang The current code maps MMIO devices as shared (decrypted) by default in a confidential computing VM. In a TDX environment, secondary CPUs are booted using the Multiprocessor Wakeup Structure defined in the ACPI specification. The virtual firmware and the operating system function in the guest context, without intervention from the VMM. Map the physical memory of the mailbox as private. Use the is_private_mmio() callback. Reviewed-by: Michael Kelley Signed-off-by: Yunhong Jiang Signed-off-by: Ricardo Neri --- Changes since v3: - Updated to use the renamed function acpi_get_mp_wakeup_mailbox_paddr(). - Added Reviewed-by tag from Michael. Thanks! Changes since v2: - Use the new helper function get_mp_wakeup_mailbox_paddr(). - Edited the commit message for clarity. Changes since v1: - Added the helper function within_page() to improve readability - Override the is_private_mmio() callback when detecting a TDX environment. The address of the mailbox is checked in hv_is_private_mmio_tdx(). --- arch/x86/hyperv/hv_vtl.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/x86/hyperv/hv_vtl.c b/arch/x86/hyperv/hv_vtl.c index 8b497c8292d3..995d1de7a9be 100644 --- a/arch/x86/hyperv/hv_vtl.c +++ b/arch/x86/hyperv/hv_vtl.c @@ -54,6 +54,18 @@ static void __noreturn hv_vtl_restart(char __maybe_unused *cmd) hv_vtl_emergency_restart(); } +static inline bool within_page(u64 addr, u64 start) +{ + return addr >= start && addr < (start + PAGE_SIZE); +} + +static bool hv_vtl_is_private_mmio_tdx(u64 addr) +{ + u64 mb_addr = acpi_get_mp_wakeup_mailbox_paddr(); + + return mb_addr && within_page(addr, mb_addr); +} + void __init hv_vtl_init_platform(void) { pr_info("Linux runs in Hyper-V Virtual Trust Level\n"); @@ -61,6 +73,8 @@ void __init hv_vtl_init_platform(void) /* There is no paravisor present if we are here. */ if (hv_isolation_type_tdx()) { x86_init.resources.realmode_limit = SZ_4G; + x86_platform.hyper.is_private_mmio = hv_vtl_is_private_mmio_tdx; + } else { x86_platform.realmode_reserve = x86_init_noop; x86_platform.realmode_init = x86_init_noop;