From patchwork Thu Jun 5 13:28:01 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Ernberg X-Patchwork-Id: 894543 Received: from mail.actia.se (mail.actia.se [212.181.117.226]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 820EC233156; Thu, 5 Jun 2025 13:28:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=212.181.117.226 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749130094; cv=none; b=OgIMqZH2Al60fhWlLDqNV0wZ6MroEXkXuh1zofZ3o6f7vHztFtU7vExaVq5k6+3/KvYOfN+6/XIgzZsYrL2Bb/ERMr/aTiCBPN7fQtsRasdbC7Hye/lZ+ACq/pe04rLcHCbqfMBNnDUimpQhx75gkdYYR2o6C4VOVzF1p4hXuqM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749130094; c=relaxed/simple; bh=/ieZ0vxH4omc1mUqVzRc72rlNUiEFsdEdZ7K/9g2NXA=; h=From:To:CC:Subject:Date:Message-ID:References:In-Reply-To: Content-Type:MIME-Version; b=Cz40QCMo0uSkbT5C6OToNWtkbjayW90oLcIqXDgYEKpGGUTNdfljFGS86y4JlwcqaklG8w8majmLW75NKVPHqrj8eWhs/glQ28MPWu3xwlaOVSDwzPncgehZ5wzX3Ue4cnfrx3Z8yoIWwcMbxRtdnQJzaGS0TSSzl2NbK+FHdbQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=actia.se; spf=pass smtp.mailfrom=actia.se; arc=none smtp.client-ip=212.181.117.226 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=actia.se Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=actia.se Received: from S036ANL.actianordic.se (10.12.31.117) by S035ANL.actianordic.se (10.12.31.116) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 5 Jun 2025 15:28:02 +0200 Received: from S036ANL.actianordic.se ([fe80::e13e:1feb:4ea6:ec69]) by S036ANL.actianordic.se ([fe80::e13e:1feb:4ea6:ec69%3]) with mapi id 15.01.2507.039; Thu, 5 Jun 2025 15:28:02 +0200 From: John Ernberg To: =?iso-8859-2?q?Horia_Geant=E3?= , Pankaj Gupta , Gaurav Jain , Herbert Xu , "David S . Miller" , "Rob Herring" , Krzysztof Kozlowski , "Conor Dooley" , Shawn Guo , Sascha Hauer CC: Frank Li , Pengutronix Kernel Team , Fabio Estevam , "linux-crypto@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "imx@lists.linux.dev" , "linux-arm-kernel@lists.infradead.org" , John Ernberg , "stable@kernel.org" Subject: [PATCH v4 1/4] crypto: caam - Prevent crash on suspend with iMX8QM / iMX8ULP Thread-Topic: [PATCH v4 1/4] crypto: caam - Prevent crash on suspend with iMX8QM / iMX8ULP Thread-Index: AQHb1h2plHQMa1AvZEqS7N0zrhQB1A== Date: Thu, 5 Jun 2025 13:28:01 +0000 Message-ID: <20250605132754.1771368-2-john.ernberg@actia.se> References: <20250605132754.1771368-1-john.ernberg@actia.se> In-Reply-To: <20250605132754.1771368-1-john.ernberg@actia.se> Accept-Language: en-US, sv-SE Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.49.0 x-esetresult: clean, is OK x-esetid: 37303A2956B1445363726A Precedence: bulk X-Mailing-List: linux-crypto@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Since the CAAM on these SoCs is managed by another ARM core, called the SECO (Security Controller) on iMX8QM and Secure Enclave on iMX8ULP, which also reserves access to register page 0 suspend operations cannot touch this page. This is similar to when running OPTEE, where OPTEE will reserve page 0. Track this situation using a new state variable no_page0, reflecting if page 0 is reserved elsewhere, either by other management cores in SoC or by OPTEE. Replace the optee_en check in suspend/resume with the new check. optee_en cannot go away as it's needed elsewhere to gate OPTEE specific situations. Fixes the following splat at suspend: Internal error: synchronous external abort: 0000000096000010 [#1] SMP Hardware name: Freescale i.MX8QXP ACU6C (DT) pstate: 60400005 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--) pc : readl+0x0/0x18 lr : rd_reg32+0x18/0x3c sp : ffffffc08192ba20 x29: ffffffc08192ba20 x28: ffffff8025190000 x27: 0000000000000000 x26: ffffffc0808ae808 x25: ffffffc080922338 x24: ffffff8020e89090 x23: 0000000000000000 x22: ffffffc080922000 x21: ffffff8020e89010 x20: ffffffc080387ef8 x19: ffffff8020e89010 x18: 000000005d8000d5 x17: 0000000030f35963 x16: 000000008f785f3f x15: 000000003b8ef57c x14: 00000000c418aef8 x13: 00000000f5fea526 x12: 0000000000000001 x11: 0000000000000002 x10: 0000000000000001 x9 : 0000000000000000 x8 : ffffff8025190870 x7 : ffffff8021726880 x6 : 0000000000000002 x5 : ffffff80217268f0 x4 : ffffff8021726880 x3 : ffffffc081200000 x2 : 0000000000000001 x1 : ffffff8020e89010 x0 : ffffffc081200004 Call trace: readl+0x0/0x18 caam_ctrl_suspend+0x30/0xdc dpm_run_callback.constprop.0+0x24/0x5c device_suspend+0x170/0x2e8 dpm_suspend+0xa0/0x104 dpm_suspend_start+0x48/0x50 suspend_devices_and_enter+0x7c/0x45c pm_suspend+0x148/0x160 state_store+0xb4/0xf8 kobj_attr_store+0x14/0x24 sysfs_kf_write+0x38/0x48 kernfs_fop_write_iter+0xb4/0x178 vfs_write+0x118/0x178 ksys_write+0x6c/0xd0 __arm64_sys_write+0x14/0x1c invoke_syscall.constprop.0+0x64/0xb0 do_el0_svc+0x90/0xb0 el0_svc+0x18/0x44 el0t_64_sync_handler+0x88/0x124 el0t_64_sync+0x150/0x154 Code: 88dffc21 88dffc21 5ac00800 d65f03c0 (b9400000) Fixes: d2835701d93c ("crypto: caam - i.MX8ULP donot have CAAM page0 access") Cc: stable@kernel.org # v6.10+ Signed-off-by: John Ernberg --- I noticed this when enabling the iMX8QXP support (next patch), hence the iMX8QXP backtrace, but the iMX8QM CAAM integration works exactly the same and according to the NXP tree [1] the iMX8ULP suffers the same issue. [1]: https://github.com/nxp-imx/linux-imx/commit/653712ffe52dd59f407af1b781ce318f3d9e17bb --- v4: - Drop 2nd Fixes tag (Frank Li) v3: - no changes v2: - Adjust commit message to make it clearer what is happening around no_page0 (Frank Li) --- drivers/crypto/caam/ctrl.c | 5 +++-- drivers/crypto/caam/intern.h | 1 + 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c index 38ff931059b4..766c447c9cfb 100644 --- a/drivers/crypto/caam/ctrl.c +++ b/drivers/crypto/caam/ctrl.c @@ -831,7 +831,7 @@ static int caam_ctrl_suspend(struct device *dev) { const struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev); - if (ctrlpriv->caam_off_during_pm && !ctrlpriv->optee_en) + if (ctrlpriv->caam_off_during_pm && !ctrlpriv->no_page0) caam_state_save(dev); return 0; @@ -842,7 +842,7 @@ static int caam_ctrl_resume(struct device *dev) struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev); int ret = 0; - if (ctrlpriv->caam_off_during_pm && !ctrlpriv->optee_en) { + if (ctrlpriv->caam_off_during_pm && !ctrlpriv->no_page0) { caam_state_restore(dev); /* HW and rng will be reset so deinstantiation can be removed */ @@ -908,6 +908,7 @@ static int caam_probe(struct platform_device *pdev) imx_soc_data = imx_soc_match->data; reg_access = reg_access && imx_soc_data->page0_access; + ctrlpriv->no_page0 = !reg_access; /* * CAAM clocks cannot be controlled from kernel. */ diff --git a/drivers/crypto/caam/intern.h b/drivers/crypto/caam/intern.h index e51320150872..51c90d17a40d 100644 --- a/drivers/crypto/caam/intern.h +++ b/drivers/crypto/caam/intern.h @@ -115,6 +115,7 @@ struct caam_drv_private { u8 blob_present; /* Nonzero if BLOB support present in device */ u8 mc_en; /* Nonzero if MC f/w is active */ u8 optee_en; /* Nonzero if OP-TEE f/w is active */ + u8 no_page0; /* Nonzero if register page 0 is not controlled by Linux */ bool pr_support; /* RNG prediction resistance available */ int secvio_irq; /* Security violation interrupt number */ int virt_en; /* Virtualization enabled in CAAM */ From patchwork Thu Jun 5 13:28:02 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Ernberg X-Patchwork-Id: 894302 Received: from mail.actia.se (mail.actia.se [212.181.117.226]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0C4A523F439; Thu, 5 Jun 2025 13:28:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=212.181.117.226 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749130097; cv=none; b=SQhqEcUJWYSlacLhlYoUE663UGFMJ8bu34z1UuFnxD/6oAh4Yldh3xQPzdDLfy97Bqrnb6fd/vHv7D1Qt/QH1n8TB2JsgStmfjB9D+4NgfZNcbhDlCCjEfJdpg0e+dQkxpfbyMS4Q0ZleYtZQOjw9XXyfJmtCp/wCLLM7peHiUU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749130097; c=relaxed/simple; bh=0VaaYgemooqHftsLY5hq5p91XL19Z/Eis8kNzUp04wg=; h=From:To:CC:Subject:Date:Message-ID:References:In-Reply-To: Content-Type:MIME-Version; b=m2t0+w1hXTlEUpuoGI0FzN5xgkvPF0OrfJHL0vch9bMppDLCzNvlCa5Z4mIGxXQZxqeDA2TaGtK3Me7/daV0SGgxIPjiW+ETC9sTzQZ60KY9/EA9Ij8Q/DyTqKnWe+Z5jdyTsMVa+A7+x9fl3UiftHT8zQ0GzOXdrY1+hitmfwg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=actia.se; spf=pass smtp.mailfrom=actia.se; arc=none smtp.client-ip=212.181.117.226 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=actia.se Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=actia.se Received: from S036ANL.actianordic.se (10.12.31.117) by S035ANL.actianordic.se (10.12.31.116) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 5 Jun 2025 15:28:02 +0200 Received: from S036ANL.actianordic.se ([fe80::e13e:1feb:4ea6:ec69]) by S036ANL.actianordic.se ([fe80::e13e:1feb:4ea6:ec69%3]) with mapi id 15.01.2507.039; Thu, 5 Jun 2025 15:28:02 +0200 From: John Ernberg To: =?iso-8859-2?q?Horia_Geant=E3?= , Pankaj Gupta , Gaurav Jain , Herbert Xu , "David S . Miller" , "Rob Herring" , Krzysztof Kozlowski , "Conor Dooley" , Shawn Guo , Sascha Hauer CC: Frank Li , Pengutronix Kernel Team , Fabio Estevam , "linux-crypto@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "imx@lists.linux.dev" , "linux-arm-kernel@lists.infradead.org" , John Ernberg , Frank Li Subject: [PATCH v4 2/4] crypto: caam - Support iMX8QXP and variants thereof Thread-Topic: [PATCH v4 2/4] crypto: caam - Support iMX8QXP and variants thereof Thread-Index: AQHb1h2pah806/NWaU+ZkYPXGVG3qQ== Date: Thu, 5 Jun 2025 13:28:02 +0000 Message-ID: <20250605132754.1771368-3-john.ernberg@actia.se> References: <20250605132754.1771368-1-john.ernberg@actia.se> In-Reply-To: <20250605132754.1771368-1-john.ernberg@actia.se> Accept-Language: en-US, sv-SE Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.49.0 x-esetresult: clean, is OK x-esetid: 37303A2956B1445363726A Precedence: bulk X-Mailing-List: linux-crypto@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The iMX8QXP (and variants such as the QX, DX, DXP) all identify as iMX8QXP. They have the exact same restrictions as the supported iMX8QM introduced at commit 61bb8db6f682 ("crypto: caam - Add support for i.MX8QM") Loosen the check a little bit with a wildcard to also match the iMX8QXP and its variants. Signed-off-by: John Ernberg Reviewed-by: Frank Li --- v4: - no changes v3: - no changes v2: - Collect review tag --- drivers/crypto/caam/ctrl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c index 766c447c9cfb..ce7b99019537 100644 --- a/drivers/crypto/caam/ctrl.c +++ b/drivers/crypto/caam/ctrl.c @@ -573,7 +573,7 @@ static const struct soc_device_attribute caam_imx_soc_table[] = { { .soc_id = "i.MX7*", .data = &caam_imx7_data }, { .soc_id = "i.MX8M*", .data = &caam_imx7_data }, { .soc_id = "i.MX8ULP", .data = &caam_imx8ulp_data }, - { .soc_id = "i.MX8QM", .data = &caam_imx8ulp_data }, + { .soc_id = "i.MX8Q*", .data = &caam_imx8ulp_data }, { .soc_id = "VF*", .data = &caam_vf610_data }, { .family = "Freescale i.MX" }, { /* sentinel */ } From patchwork Thu Jun 5 13:28:02 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Ernberg X-Patchwork-Id: 894542 Received: from mail.actia.se (mail.actia.se [212.181.117.226]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A504724503C; Thu, 5 Jun 2025 13:28:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=212.181.117.226 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749130099; cv=none; b=Y8W/QyFHdN9jHvTR4m4z3/Ym0QrDi2FWCGNqXjk/ZCVMQU3v6tyNPr+BUcvbLkjUf01I1rNA9HoqzL6kfa56eH7T9C/aAeiIRuJnhRHMzCq8yDtl+2oeT2ZzVL8tUDeW+B+otbyLuiLAKHtFEqDYQyx9sj3qIXqCy9T1IdO+RZ8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749130099; c=relaxed/simple; bh=cMf4IvswtrJysRpI222aZBga78g0ROKP/Nd036IwvDE=; h=From:To:CC:Subject:Date:Message-ID:References:In-Reply-To: Content-Type:MIME-Version; b=CvRGEfIy39uqem9BTExlCArflHrjdAypxxUHyxpqnYBeDIcVKjcMEXFb7y8a17fT8FQh1buepJdiaMEJ0HyDdAdkfxLJPKdMD3DYvxqOv1d4TzA6tqP2XIEe9FZ1zFHHAzMjs1hV2JOCk16K2WsLgZX7eidyThkDMePBlMK0Thc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=actia.se; spf=pass smtp.mailfrom=actia.se; arc=none smtp.client-ip=212.181.117.226 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=actia.se Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=actia.se Received: from S036ANL.actianordic.se (10.12.31.117) by S035ANL.actianordic.se (10.12.31.116) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 5 Jun 2025 15:28:02 +0200 Received: from S036ANL.actianordic.se ([fe80::e13e:1feb:4ea6:ec69]) by S036ANL.actianordic.se ([fe80::e13e:1feb:4ea6:ec69%3]) with mapi id 15.01.2507.039; Thu, 5 Jun 2025 15:28:02 +0200 From: John Ernberg To: =?iso-8859-2?q?Horia_Geant=E3?= , Pankaj Gupta , Gaurav Jain , Herbert Xu , "David S . Miller" , "Rob Herring" , Krzysztof Kozlowski , "Conor Dooley" , Shawn Guo , Sascha Hauer CC: Frank Li , Pengutronix Kernel Team , Fabio Estevam , "linux-crypto@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "imx@lists.linux.dev" , "linux-arm-kernel@lists.infradead.org" , John Ernberg Subject: [PATCH v4 3/4] dt-bindings: crypto: fsl,sec-v4.0: Add power domains for iMX8QM and iMX8QXP Thread-Topic: [PATCH v4 3/4] dt-bindings: crypto: fsl,sec-v4.0: Add power domains for iMX8QM and iMX8QXP Thread-Index: AQHb1h2p186darlQmUK22qpyzH8BCg== Date: Thu, 5 Jun 2025 13:28:02 +0000 Message-ID: <20250605132754.1771368-4-john.ernberg@actia.se> References: <20250605132754.1771368-1-john.ernberg@actia.se> In-Reply-To: <20250605132754.1771368-1-john.ernberg@actia.se> Accept-Language: en-US, sv-SE Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.49.0 x-esetresult: clean, is OK x-esetid: 37303A2956B1445363726A Precedence: bulk X-Mailing-List: linux-crypto@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 NXP SoCs like the iMX8QM, iMX8QXP or iMX8DXP use power domains for resource management. Add compatible strings for these SoCs (QXP and DXP gets to share as their only difference is a core-count, Q=Quad core and D=Dual core), and allow power-domains for them only. Keep the old restriction for others. Signed-off-by: John Ernberg --- v4: - Reword commit message (Frank Li) - Add explicit imx8qxp compatible (Frank Li) - Move the job-ring constraints back to the job-ring section under an 'allOf:' to avoid the warning from v2 (Rob Herring) v3: - Fix warnings discovered by Rob Herring's bot - Declare the compatibles correctly (Krzysztof Kozlowski) v2: - Adjust commit message (Frank Li) - Only allow power-domains when compatible with imx8qm (Frank Li) --- .../bindings/crypto/fsl,sec-v4.0.yaml | 41 ++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/crypto/fsl,sec-v4.0.yaml b/Documentation/devicetree/bindings/crypto/fsl,sec-v4.0.yaml index 75afa441e019..eab43e7a354c 100644 --- a/Documentation/devicetree/bindings/crypto/fsl,sec-v4.0.yaml +++ b/Documentation/devicetree/bindings/crypto/fsl,sec-v4.0.yaml @@ -46,6 +46,8 @@ properties: - items: - enum: - fsl,imx6ul-caam + - fsl,imx8qm-caam + - fsl,imx8qxp-caam - fsl,sec-v5.0 - const: fsl,sec-v4.0 - const: fsl,sec-v4.0 @@ -77,6 +79,9 @@ properties: interrupts: maxItems: 1 + power-domains: + maxItems: 1 + fsl,sec-era: description: Defines the 'ERA' of the SEC device. $ref: /schemas/types.yaml#/definitions/uint32 @@ -106,7 +111,10 @@ patternProperties: - const: fsl,sec-v5.0-job-ring - const: fsl,sec-v4.0-job-ring - items: - - const: fsl,sec-v5.0-job-ring + - enum: + - fsl,imx8qm-job-ring + - fsl,imx8qxp-job-ring + - fsl,sec-v5.0-job-ring - const: fsl,sec-v4.0-job-ring - const: fsl,sec-v4.0-job-ring @@ -116,6 +124,9 @@ patternProperties: interrupts: maxItems: 1 + power-domains: + maxItems: 1 + fsl,liodn: description: Specifies the LIODN to be used in conjunction with the ppid-to-liodn @@ -125,6 +136,20 @@ patternProperties: $ref: /schemas/types.yaml#/definitions/uint32-array items: - maximum: 0xfff + allOf: + - if: + properties: + compatible: + contains: + enum: + - fsl,imx8qm-job-ring + - fsl,imx8qxp-job-ring + then: + required: + - power-domains + else: + properties: + power-domains: false '^rtic@[0-9a-f]+$': type: object @@ -212,6 +237,20 @@ required: - reg - ranges +if: + properties: + compatible: + contains: + enum: + - fsl,imx8qm-caam + - fsl,imx8qxp-caam +then: + required: + - power-domains +else: + properties: + power-domains: false + additionalProperties: false examples: From patchwork Thu Jun 5 13:28:02 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: John Ernberg X-Patchwork-Id: 894301 Received: from mail.actia.se (mail.actia.se [212.181.117.226]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F17D4246775; Thu, 5 Jun 2025 13:28:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=212.181.117.226 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749130101; cv=none; b=rzGdcFXYDpaI7yw1pDqrMDTpFN6g1GHutTTRrbyM6Wv4fx88ORBN77lRE3cCGA48RWrXwhNlNgpIK1tY2aJ+MftlU7TqcrfOy04De9rQAVTYO9SYl5X70jO101MuBSEvkgEa46LfNQRCm7ZjctxcMXPUC+SdpiRpYEZZnJe8/EU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749130101; c=relaxed/simple; bh=Y/PkaHnmDJIFCq7JUHOIoqq0JufPEvzABwQKtTywsGs=; h=From:To:CC:Subject:Date:Message-ID:References:In-Reply-To: Content-Type:MIME-Version; b=qybFOEW9+36CLWM0ABfutKBDz1DppWbohA/GDqsQCSGDi5vHJ1Yj81NQc00UbKx+8ZhOB0hUaFOQzmE42/rSphVQlJDja6PQFOCqaKjbFCGIDpzy0DtQexBeKNGJ2es+Z6NU1Kb08NhIh9bBHalrRtDopN/8T8dY1q/IylawIzY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=actia.se; spf=pass smtp.mailfrom=actia.se; arc=none smtp.client-ip=212.181.117.226 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=actia.se Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=actia.se Received: from S036ANL.actianordic.se (10.12.31.117) by S035ANL.actianordic.se (10.12.31.116) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 5 Jun 2025 15:28:02 +0200 Received: from S036ANL.actianordic.se ([fe80::e13e:1feb:4ea6:ec69]) by S036ANL.actianordic.se ([fe80::e13e:1feb:4ea6:ec69%3]) with mapi id 15.01.2507.039; Thu, 5 Jun 2025 15:28:02 +0200 From: John Ernberg To: =?utf-8?q?Horia_Geant=C4=83?= , Pankaj Gupta , Gaurav Jain , Herbert Xu , "David S . Miller" , "Rob Herring" , Krzysztof Kozlowski , "Conor Dooley" , Shawn Guo , Sascha Hauer CC: Frank Li , Pengutronix Kernel Team , Fabio Estevam , "linux-crypto@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "imx@lists.linux.dev" , "linux-arm-kernel@lists.infradead.org" , John Ernberg Subject: [PATCH v4 4/4] arm64: dts: freescale: imx8qxp/imx8qm: Add CAAM support Thread-Topic: [PATCH v4 4/4] arm64: dts: freescale: imx8qxp/imx8qm: Add CAAM support Thread-Index: AQHb1h2ph2TtuHQV/UyvhoDM1n6IyQ== Date: Thu, 5 Jun 2025 13:28:02 +0000 Message-ID: <20250605132754.1771368-5-john.ernberg@actia.se> References: <20250605132754.1771368-1-john.ernberg@actia.se> In-Reply-To: <20250605132754.1771368-1-john.ernberg@actia.se> Accept-Language: en-US, sv-SE Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.49.0 x-esetresult: clean, is OK x-esetid: 37303A2956B1445363726A Content-ID: <256320B80A75A6469D813BA76D6A1239@actia.se> Precedence: bulk X-Mailing-List: linux-crypto@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Horia Geantă The iMX8QXP and iMX8QM have a CAAM (Cryptographic Acceleration and Assurance Module) like many other iMXs. Add the definitions for it. Job Rings 0 and 1 are bound to the SECO (Security Controller) ARM core and are not exposed outside it. There's no point to define them in the bindings as they cannot be used outside the SECO. Signed-off-by: Horia Geantă Signed-off-by: John Ernberg --- Imported from NXP tree, trimmed down and fixed the dtbs_check warnings. Constrained the ranges to the needed ones. Changed the commit message. Original here: https://github.com/nxp-imx/linux-imx/commit/699e54b386cb9b53def401798d0a4e646105583d --- v4: - Drop [ ] rework detailing from commit log. (Frank Li) - Add an override dtsi to change the compatibles on QXP due to changes in 3/4. (Frank Li) v3: - no changes v2: - Use new compatibles introduced in 3/4 (Frank Li) --- .../boot/dts/freescale/imx8-ss-security.dtsi | 38 +++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8qm.dtsi | 1 + .../dts/freescale/imx8qxp-ss-security.dtsi | 16 ++++++++ arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 2 + 4 files changed, 57 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-security.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-ss-security.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-security.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-security.dtsi new file mode 100644 index 000000000000..9ecabb2d03e9 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-security.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include + +security_subsys: bus@31400000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x31400000 0x0 0x31400000 0x90000>; + + crypto: crypto@31400000 { + compatible = "fsl,imx8qm-caam", "fsl,sec-v4.0"; + reg = <0x31400000 0x90000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x31400000 0x90000>; + fsl,sec-era = <9>; + power-domains = <&pd IMX_SC_R_CAAM_JR2>; + + sec_jr2: jr@30000 { + compatible = "fsl,imx8qm-job-ring", "fsl,sec-v4.0-job-ring"; + reg = <0x30000 0x10000>; + interrupts = ; + power-domains = <&pd IMX_SC_R_CAAM_JR2>; + }; + + sec_jr3: jr@40000 { + compatible = "fsl,imx8qm-job-ring", "fsl,sec-v4.0-job-ring"; + reg = <0x40000 0x10000>; + interrupts = ; + power-domains = <&pd IMX_SC_R_CAAM_JR3>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi index 6fa31bc9ece8..6df018643f20 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi @@ -612,6 +612,7 @@ vpu_dsp: dsp@556e8000 { }; /* sorted in register address */ + #include "imx8-ss-security.dtsi" #include "imx8-ss-cm41.dtsi" #include "imx8-ss-audio.dtsi" #include "imx8-ss-vpu.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-security.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-security.dtsi new file mode 100644 index 000000000000..15f1239dab24 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-security.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 Actia Nordic AB + */ + +&crypto { + compatible = "fsl,imx8qxp-caam", "fsl,sec-v4.0"; +}; + +&sec_jr2 { + compatible = "fsl,imx8qxp-job-ring", "fsl,sec-v4.0-job-ring"; +}; + +&sec_jr3 { + compatible = "fsl,imx8qxp-job-ring", "fsl,sec-v4.0-job-ring"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index 05138326f0a5..e2e799cc294c 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -321,6 +321,7 @@ map0 { /* sorted in register address */ #include "imx8-ss-img.dtsi" #include "imx8-ss-vpu.dtsi" + #include "imx8-ss-security.dtsi" #include "imx8-ss-cm40.dtsi" #include "imx8-ss-gpu0.dtsi" #include "imx8-ss-adma.dtsi" @@ -332,6 +333,7 @@ map0 { #include "imx8qxp-ss-img.dtsi" #include "imx8qxp-ss-vpu.dtsi" +#include "imx8qxp-ss-security.dtsi" #include "imx8qxp-ss-adma.dtsi" #include "imx8qxp-ss-conn.dtsi" #include "imx8qxp-ss-lsio.dtsi"