From patchwork Fri Jun 6 12:34:42 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 894452 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:ecd:b0:3a4:ee3f:8f15 with SMTP id ea13csp483637wrb; Fri, 6 Jun 2025 05:42:52 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWbg2e5In8oMtYJO++JsB2REBm++0HIIXLRbFokD/Z2KJlWoo/VwXkyznpyQiN8GyFQ/yA6bA==@linaro.org X-Google-Smtp-Source: AGHT+IExEYY+U4DLsi5DlJvXT+NwtM3UMmvXmLc1CbNQEak2Sk8tRUqxZqiybgffl9rQWVwtI+wf X-Received: by 2002:a05:6214:d6b:b0:6fa:c168:8de4 with SMTP id 6a1803df08f44-6fb08f8d36emr54741766d6.33.1749213772235; Fri, 06 Jun 2025 05:42:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1749213772; cv=none; d=google.com; s=arc-20240605; b=X7A1gLyxI3fUT8rqjRHkyiodRHucz7VSZtF8c4fafeMBVebIF5Aw1cfrGMOB7gyKxt he5bTXi/GKKhz8vHqM8tNicTH91cVb2kQ8tcgMimqc5u6i6f8dXttgC+2IhVpwS4m+JK UboppdMPsdi1oefbzrdVBwP2kAgBc3WlHKq6Op1k8/e7L3kSM3b2w7lUKuZbqiOl+jOg lSa02Uy6c1e8A92DE4+IuxWoQ4ZXxtP5WZWgDqv3nstiKHZJXMFfb2MFBTk7WnFlM3bQ 3wSFDH7xCyc2zqnkXg3Faksb0b3wKgyVdKD3uRH69wmpV4eXqNXPzOopes0aSKcQJ1qN /U0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=lyIpbhdOi8uKuobeqFQ0SyC2g54IbnY9g+PvajejF10=; fh=LCBicqeu5OWASEl1rLR9HJKJ77k8ScftFktlzJMVrFY=; b=MzWoRuqukHpkyiW45guWhAmColTSVnPtR5xsZ5X/vd5PDRRj0H0Y7srzbvMxQw+O93 NqtjdLXple72DIL9pSopaLCPNNK0pqIo2IHp9C3RV4u/H8yGjuwJ0gIWXeQwlraIUqYN zoisCGdJUa0imjjV60EOaF/zfBVbaWY9FJURSReZE6xbcmnHzkre8Np7mdBDEWYGMb4X phR5nguY0hAWo7at+ZqL4l2OnFyr3OHnekk8059Zwygsp5EUHNF/NVyH4FejVTGtFM7s OXoRxa6By0MwHu2cS4Ku2OErUiVx7CTmA3u2NKhqr88aaz0gol6i8kKvX/LyYfHx9f49 J98w==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=N2HElMrV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 6a1803df08f44-6fb09ab056fsi16915266d6.88.2025.06.06.05.42.52 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 06 Jun 2025 05:42:52 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=N2HElMrV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=redhat.com Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uNWLH-0005M8-R4; Fri, 06 Jun 2025 08:38:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uNWJF-0003jx-Ax for qemu-devel@nongnu.org; Fri, 06 Jun 2025 08:36:39 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uNWJC-00060h-Ev for qemu-devel@nongnu.org; Fri, 06 Jun 2025 08:36:32 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1749213388; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=lyIpbhdOi8uKuobeqFQ0SyC2g54IbnY9g+PvajejF10=; b=N2HElMrVS5ieGU1kCd3Pc4CRAAHPcWzqvXk4IWVFc+KsL5FxyfJ5cdJ92rsoW+1nfK/5LE fUBde688UODXvDVD5jySnkfG8TbYs+CkqIMHOQAJ/fK513tGe9KzcDstF2kRayP8llE4/c QVHtj/DaT5IEdDSiTW4yC4CT5fWH/uQ= Received: from mail-wr1-f72.google.com (mail-wr1-f72.google.com [209.85.221.72]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-695-nLeCYytqNBi-mSEcZKGdGA-1; Fri, 06 Jun 2025 08:36:27 -0400 X-MC-Unique: nLeCYytqNBi-mSEcZKGdGA-1 X-Mimecast-MFC-AGG-ID: nLeCYytqNBi-mSEcZKGdGA_1749213386 Received: by mail-wr1-f72.google.com with SMTP id ffacd0b85a97d-3a3696a0d3aso857882f8f.2 for ; Fri, 06 Jun 2025 05:36:27 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749213386; x=1749818186; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lyIpbhdOi8uKuobeqFQ0SyC2g54IbnY9g+PvajejF10=; b=IRZSHb1Il/dNhAu97qYJ5A5/h1iI4sCqE77KCObQvQVDA8nmfZSUY+EMryu/UMIep1 XfnAc1OtZ/A68UR2dgY7JsYfX/fAaemuWJ/Q5JmevRBPJNv4ncaQfjS6C6Jt5jpWKOT0 O3KyXbdzIA/FXMsorcoLOnwjj8Wl6shvLEwJB7lQDtRIqBfcAlMBHSrekr81xSES0fZr aEAQVZGwiXN454/q53oFP5SUsYSSSKxResXLJxurvpgsrho4VZzVesZaOXqIzOQ9eJuh MFC8kiSY8NTZOwXH65+ICM1WHbssdGinXgOor33V6LqkvZGs1F32HT7NAnB2BJaPXTkk t4pQ== X-Gm-Message-State: AOJu0Yyd1jPhoUr+e3lb51IkEJ/axFTI+2gHSxrYIJo47/Rjh1yrrj57 XoK8mwEjejjjbUDb/3jyIbyr1D735IBRSNtwkNeoUxLIH96sdXc9/Mm3kmipcs4ZYzfIUeHX6i8 5DCUdxA3caSmJ1Ishcn9S7dG3FA4D4Q0AQo9692Fy6diYMOJ6oudFcXuMRCD22kb46Pe+SucyvO LzvmhP2J+bQu8XOf4BuPmCOA5fsdK1f38x/miw3L5t X-Gm-Gg: ASbGncsoVSVKMJiVvj7Lc1X6GfgBJHFPjhilcu2xXsvIH7jfVutseUKkgUphmI3Oeb8 N6szmlyAA5wZ1JMcU1EoDJXRDuO1d1Q2YOsNaiNO2EEEjdXCxKz+vhZcWBXgyTiZwC0lLkyN+5L gfI0jth3dW4bsLqpn6JfkJqjbOxl8v4VIStDD70rHzRe+6oyFwP98oCTQ3nx7b0D/ZO3KJpvZc3 8JkDxGeYxV4ukjw1i9iOQCZCrvtYj0hm0/nkyIWpVSxplWADj2t0OOy8aRLFz1LGIbMl47+AE4G oOLoid1PLTzqgQ== X-Received: by 2002:a05:6000:24c7:b0:3a4:eb80:762d with SMTP id ffacd0b85a97d-3a531ced4d6mr2688897f8f.56.1749213385680; Fri, 06 Jun 2025 05:36:25 -0700 (PDT) X-Received: by 2002:a05:6000:24c7:b0:3a4:eb80:762d with SMTP id ffacd0b85a97d-3a531ced4d6mr2688876f8f.56.1749213385201; Fri, 06 Jun 2025 05:36:25 -0700 (PDT) Received: from [192.168.10.48] ([151.49.64.79]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4526e05636dsm20342895e9.4.2025.06.06.05.36.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Jun 2025 05:36:22 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Peter Maydell , Richard Henderson , Zhao Liu Subject: [PULL 28/31] target/i386: Detect flush-to-zero after rounding Date: Fri, 6 Jun 2025 14:34:42 +0200 Message-ID: <20250606123447.538131-29-pbonzini@redhat.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250606123447.538131-1-pbonzini@redhat.com> References: <20250606123447.538131-1-pbonzini@redhat.com> MIME-Version: 1.0 Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.104, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Peter Maydell The Intel SDM section 10.2.3.3 on the MXCSR.FTZ bit says that we flush outputs to zero when we detect underflow, which is after rounding. Set the detect_ftz flag accordingly. This allows us to enable the test in fma.c which checks this behaviour. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Zhao Liu Link: https://lore.kernel.org/r/20250519145114.2786534-2-peter.maydell@linaro.org Signed-off-by: Paolo Bonzini --- target/i386/tcg/fpu_helper.c | 8 ++++---- tests/tcg/x86_64/fma.c | 5 ----- 2 files changed, 4 insertions(+), 9 deletions(-) diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index 1cbadb14533..9ea67ea76c8 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -189,13 +189,13 @@ void cpu_init_fp_statuses(CPUX86State *env) set_float_default_nan_pattern(0b11000000, &env->mmx_status); set_float_default_nan_pattern(0b11000000, &env->sse_status); /* - * TODO: x86 does flush-to-zero detection after rounding (the SDM + * x86 does flush-to-zero detection after rounding (the SDM * section 10.2.3.3 on the FTZ bit of MXCSR says that we flush * when we detect underflow, which x86 does after rounding). */ - set_float_ftz_detection(float_ftz_before_rounding, &env->fp_status); - set_float_ftz_detection(float_ftz_before_rounding, &env->mmx_status); - set_float_ftz_detection(float_ftz_before_rounding, &env->sse_status); + set_float_ftz_detection(float_ftz_after_rounding, &env->fp_status); + set_float_ftz_detection(float_ftz_after_rounding, &env->mmx_status); + set_float_ftz_detection(float_ftz_after_rounding, &env->sse_status); } static inline uint8_t save_exception_flags(CPUX86State *env) diff --git a/tests/tcg/x86_64/fma.c b/tests/tcg/x86_64/fma.c index 09c622ebc00..46f863005ed 100644 --- a/tests/tcg/x86_64/fma.c +++ b/tests/tcg/x86_64/fma.c @@ -79,14 +79,9 @@ static testdata tests[] = { /* * Flushing of denormal outputs to zero should also happen after * rounding, so setting FTZ should not affect the result or the flags. - * QEMU currently does not emulate this correctly because we do the - * flush-to-zero check before rounding, so we incorrectly produce a - * zero result and set Underflow as well as Precision. */ -#ifdef ENABLE_FAILING_TESTS { 0x3fdfffffffffffff, 0x001fffffffffffff, 0x801fffffffffffff, true, 0x8010000000000000, 0x20 }, /* Enabling FTZ shouldn't change flags */ -#endif }; int main(void) From patchwork Fri Jun 6 12:34:43 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 894451 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:ecd:b0:3a4:ee3f:8f15 with SMTP id ea13csp482324wrb; Fri, 6 Jun 2025 05:39:42 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCU1uWtRD0rumVM04HaEre/q/Eu5Vx46uw2uc7BVAA2EqgUZHm9mqvE4KnUKrgl1TbGLAB/lFQ==@linaro.org X-Google-Smtp-Source: AGHT+IFos51ymnjcsPdm2RBWqrKqOykoIiGq6mwYe3NwC126Veik+yh3dyjjcHw8wiH2EFMaBCGo X-Received: by 2002:a05:6214:4015:b0:6f8:b4aa:2a4d with SMTP id 6a1803df08f44-6fb08fbbc5cmr56095916d6.31.1749213582706; Fri, 06 Jun 2025 05:39:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1749213582; cv=none; d=google.com; s=arc-20240605; b=CX0tNDGyOInqGjibSAI2BVIAfXIVQSKfoFb9vpflB4Q3NqJaIR5ECVvFt56NLOdYd0 mqiRXxAktE0D9XpMBzq9XBgJ0jtZwwSbJsaz4ftm2nAQWluxYbimp9NtE5zJ6LfRg4zt mnQDtvIkgYPs+cCdfkVyDP63C9H+Q1AKklHjv9zW/WDLsh/M11bSXksserqsiUdGydx/ zAWNF6dK9gjquxDJaWYTeOsdBx0BMWKHVHAZaMpahL+h5GGXsfb2gp7BhAKH2NGdahbD GAa3FjkRnnRGNX6dzHHd7oAdTR20JpIj7fe4iQcsSZ+oGW7yAgDNRcO+axWecPXH9afR skQA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=7kj1AeO1EtewcC7z+Hv0M7dwyRuL1nrrx38TVQWmK0Y=; fh=gtwAdQr+I6kV6HK7JmciaCp0z5aJn8839iUk/6Vxp/I=; b=gezl9Hj3CZ8sdT/JyaQehRSMLWkzNOOcM7jl3gVTKJBOMEN3kds3v5T3dXStyD+m7w DPvljZJODvMOsK0BWIXGwvE8dGX3jxnPqczdQ850AKYvU0JeOkG7HfVGy1/dV2bEfaQp GR4kmhmMjnGIxEOLagl57Goe0qC+u3AZ1rldkgkk0NMGNVdrZz6kvsuA0jRZJqj+pOwH dQJICbULAiO+odnFYz2GakFgIoVOMuC46UM0uYmhVJ83wR8crZAdhxTHfbO5Uut4kjPc 8loesrIHbHibx/ir9VhWM5exdPBwYxmxg4qsjzpebWMHZUIKsH8gNyeO7514Qb+bebPK qEZw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=E02VwYOp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id af79cd13be357-7d25e60f2a5si160350685a.525.2025.06.06.05.39.42 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 06 Jun 2025 05:39:42 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=E02VwYOp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=redhat.com Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uNWLS-0005QS-BM; Fri, 06 Jun 2025 08:38:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uNWJO-0003qB-8a for qemu-devel@nongnu.org; Fri, 06 Jun 2025 08:36:42 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uNWJG-000611-Sy for qemu-devel@nongnu.org; Fri, 06 Jun 2025 08:36:41 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1749213392; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=7kj1AeO1EtewcC7z+Hv0M7dwyRuL1nrrx38TVQWmK0Y=; b=E02VwYOpkqFbIcY+3Fu0n8yYk/midmOC2TZCZhzRADi1kp3nWqJVjBqE9hentYCbzJVTz2 sWsrFl+HdaJm5xir95Omy9ijEkIC5AtaF0RKN+1vZmhOWBzC45F4mDNHnyGAVjIRyDULO2 SGYLLZcS88EPAZI4SYCTm98tCp7u0/s= Received: from mail-wr1-f69.google.com (mail-wr1-f69.google.com [209.85.221.69]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-558-fyBKxjDOO9miX942yNALeQ-1; Fri, 06 Jun 2025 08:36:31 -0400 X-MC-Unique: fyBKxjDOO9miX942yNALeQ-1 X-Mimecast-MFC-AGG-ID: fyBKxjDOO9miX942yNALeQ_1749213390 Received: by mail-wr1-f69.google.com with SMTP id ffacd0b85a97d-3a4eec544c6so1061681f8f.0 for ; Fri, 06 Jun 2025 05:36:31 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749213389; x=1749818189; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7kj1AeO1EtewcC7z+Hv0M7dwyRuL1nrrx38TVQWmK0Y=; b=KG1HDRLQocOt0cef+piJ+vtkZEZvoAqRDcHa9GXUMjInvhlXvv8fPRQZc5nvGXrWVt xOdu9gbZibyCPx8layvqZPDtaE6zE5l4ma8yHwnkWBGh7Hb0habYl2tLBEgDubDv4tYX coKzJz5KGSn+fvgIZwHglaQ881eM049L4OkPQB3MEasi2r3WZR2XwqYFfpTZhchcBcEm ngg9dvVon8G4cG/yOEASzzGz6qJxVaDYMPRFIqTBgkMDMYoeP10v3fWYH9/7wlfJJ1FO z0tbPYochDjAaEvg/XBRKS23HNa1PDVFEoP+iQIJF9CqvgrweBjLIEJfl6UgpWoDr/VV R99g== X-Gm-Message-State: AOJu0YyhTcmlYwPZ0wuqcUTpYZtRURRlqsA6eHaNoG6QLt2HZiLt7dpN oyLc3/A/D8m/koUj2rW5C9JT7IyO+m+n9A/L4kFfyI3v7RA8tFHoS8H83SVn+eo+nMm9EmbuvGY 3qhFpXFPnP0GODGk9ItTekf8oIxqEckuM2E7vQAY8lzmYewOQi9wr5AvmBBR4MIG3K8hj9JI82A ABAWAdkJgP0D0Eonj4/PVVsDoEHDHSvEFV1GfaTzoA X-Gm-Gg: ASbGnct1G9fd2OvDfy4qD+/Tj3e8uI1dlJ9QLWv1RNFH0VvQ8UReFan3SI+xQ/hS7PS SsK7BZjXOt1nD3f4wBsmhoi+VfL0xVVaYB8LJGiBGFEx05Si3TQKan5U6mZ6viF8YN2nkP/forQ 2xFGBUGx44+SzemmrE41QhiXJsvn7Q8oeRO79xvMkzVpLEn7BOHcmYET6ncNMeUvFGRe9WjIye9 5+PbH2K6p8dZyVXKiZK6HHb9Xd3TMdhWsDydXQ1M0AabX1rsIaNSEYqZuX8Hr23cyM2IQ5F8QMq Q5gpsrCkdb4KUA== X-Received: by 2002:a05:6000:4212:b0:3a4:e844:745d with SMTP id ffacd0b85a97d-3a531cf5420mr2780145f8f.56.1749213389253; Fri, 06 Jun 2025 05:36:29 -0700 (PDT) X-Received: by 2002:a05:6000:4212:b0:3a4:e844:745d with SMTP id ffacd0b85a97d-3a531cf5420mr2780113f8f.56.1749213388716; Fri, 06 Jun 2025 05:36:28 -0700 (PDT) Received: from [192.168.10.48] ([151.49.64.79]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4521375bca3sm22683665e9.39.2025.06.06.05.36.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Jun 2025 05:36:26 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Peter Maydell , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Zhao Liu Subject: [PULL 29/31] target/i386: Use correct type for get_float_exception_flags() values Date: Fri, 6 Jun 2025 14:34:43 +0200 Message-ID: <20250606123447.538131-30-pbonzini@redhat.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250606123447.538131-1-pbonzini@redhat.com> References: <20250606123447.538131-1-pbonzini@redhat.com> MIME-Version: 1.0 Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.104, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Peter Maydell The softfloat get_float_exception_flags() function returns 'int', but in various places in target/i386 we incorrectly store the returned value into a uint8_t. This currently has no ill effects because i386 doesn't care about any of the float_flag enum values above 0x40. However, we want to start using float_flag_input_denormal_used, which is 0x4000. Switch to using 'int' so that we can handle all the possible valid float_flag_* values. This includes changing the return type of save_exception_flags() and the argument to merge_exception_flags(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Zhao Liu Link: https://lore.kernel.org/r/20250519145114.2786534-3-peter.maydell@linaro.org Signed-off-by: Paolo Bonzini --- target/i386/ops_sse.h | 16 +++---- target/i386/tcg/fpu_helper.c | 82 ++++++++++++++++++------------------ 2 files changed, 49 insertions(+), 49 deletions(-) diff --git a/target/i386/ops_sse.h b/target/i386/ops_sse.h index f0aa1894aa2..a2e4d480399 100644 --- a/target/i386/ops_sse.h +++ b/target/i386/ops_sse.h @@ -842,7 +842,7 @@ int64_t helper_cvttsd2sq(CPUX86State *env, ZMMReg *s) void glue(helper_rsqrtps, SUFFIX)(CPUX86State *env, ZMMReg *d, ZMMReg *s) { - uint8_t old_flags = get_float_exception_flags(&env->sse_status); + int old_flags = get_float_exception_flags(&env->sse_status); int i; for (i = 0; i < 2 << SHIFT; i++) { d->ZMM_S(i) = float32_div(float32_one, @@ -855,7 +855,7 @@ void glue(helper_rsqrtps, SUFFIX)(CPUX86State *env, ZMMReg *d, ZMMReg *s) #if SHIFT == 1 void helper_rsqrtss(CPUX86State *env, ZMMReg *d, ZMMReg *v, ZMMReg *s) { - uint8_t old_flags = get_float_exception_flags(&env->sse_status); + int old_flags = get_float_exception_flags(&env->sse_status); int i; d->ZMM_S(0) = float32_div(float32_one, float32_sqrt(s->ZMM_S(0), &env->sse_status), @@ -869,7 +869,7 @@ void helper_rsqrtss(CPUX86State *env, ZMMReg *d, ZMMReg *v, ZMMReg *s) void glue(helper_rcpps, SUFFIX)(CPUX86State *env, ZMMReg *d, ZMMReg *s) { - uint8_t old_flags = get_float_exception_flags(&env->sse_status); + int old_flags = get_float_exception_flags(&env->sse_status); int i; for (i = 0; i < 2 << SHIFT; i++) { d->ZMM_S(i) = float32_div(float32_one, s->ZMM_S(i), &env->sse_status); @@ -880,7 +880,7 @@ void glue(helper_rcpps, SUFFIX)(CPUX86State *env, ZMMReg *d, ZMMReg *s) #if SHIFT == 1 void helper_rcpss(CPUX86State *env, ZMMReg *d, ZMMReg *v, ZMMReg *s) { - uint8_t old_flags = get_float_exception_flags(&env->sse_status); + int old_flags = get_float_exception_flags(&env->sse_status); int i; d->ZMM_S(0) = float32_div(float32_one, s->ZMM_S(0), &env->sse_status); for (i = 1; i < 2 << SHIFT; i++) { @@ -1714,7 +1714,7 @@ void glue(helper_phminposuw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) void glue(helper_roundps, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, uint32_t mode) { - uint8_t old_flags = get_float_exception_flags(&env->sse_status); + int old_flags = get_float_exception_flags(&env->sse_status); signed char prev_rounding_mode; int i; @@ -1738,7 +1738,7 @@ void glue(helper_roundps, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, void glue(helper_roundpd, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, uint32_t mode) { - uint8_t old_flags = get_float_exception_flags(&env->sse_status); + int old_flags = get_float_exception_flags(&env->sse_status); signed char prev_rounding_mode; int i; @@ -1763,7 +1763,7 @@ void glue(helper_roundpd, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, void glue(helper_roundss, SUFFIX)(CPUX86State *env, Reg *d, Reg *v, Reg *s, uint32_t mode) { - uint8_t old_flags = get_float_exception_flags(&env->sse_status); + int old_flags = get_float_exception_flags(&env->sse_status); signed char prev_rounding_mode; int i; @@ -1788,7 +1788,7 @@ void glue(helper_roundss, SUFFIX)(CPUX86State *env, Reg *d, Reg *v, Reg *s, void glue(helper_roundsd, SUFFIX)(CPUX86State *env, Reg *d, Reg *v, Reg *s, uint32_t mode) { - uint8_t old_flags = get_float_exception_flags(&env->sse_status); + int old_flags = get_float_exception_flags(&env->sse_status); signed char prev_rounding_mode; int i; diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index 9ea67ea76c8..4732b718129 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -198,16 +198,16 @@ void cpu_init_fp_statuses(CPUX86State *env) set_float_ftz_detection(float_ftz_after_rounding, &env->sse_status); } -static inline uint8_t save_exception_flags(CPUX86State *env) +static inline int save_exception_flags(CPUX86State *env) { - uint8_t old_flags = get_float_exception_flags(&env->fp_status); + int old_flags = get_float_exception_flags(&env->fp_status); set_float_exception_flags(0, &env->fp_status); return old_flags; } -static void merge_exception_flags(CPUX86State *env, uint8_t old_flags) +static void merge_exception_flags(CPUX86State *env, int old_flags) { - uint8_t new_flags = get_float_exception_flags(&env->fp_status); + int new_flags = get_float_exception_flags(&env->fp_status); float_raise(old_flags, &env->fp_status); fpu_set_exception(env, ((new_flags & float_flag_invalid ? FPUS_IE : 0) | @@ -220,7 +220,7 @@ static void merge_exception_flags(CPUX86State *env, uint8_t old_flags) static inline floatx80 helper_fdiv(CPUX86State *env, floatx80 a, floatx80 b) { - uint8_t old_flags = save_exception_flags(env); + int old_flags = save_exception_flags(env); floatx80 ret = floatx80_div(a, b, &env->fp_status); merge_exception_flags(env, old_flags); return ret; @@ -240,7 +240,7 @@ static void fpu_raise_exception(CPUX86State *env, uintptr_t retaddr) void helper_flds_FT0(CPUX86State *env, uint32_t val) { - uint8_t old_flags = save_exception_flags(env); + int old_flags = save_exception_flags(env); union { float32 f; uint32_t i; @@ -253,7 +253,7 @@ void helper_flds_FT0(CPUX86State *env, uint32_t val) void helper_fldl_FT0(CPUX86State *env, uint64_t val) { - uint8_t old_flags = save_exception_flags(env); + int old_flags = save_exception_flags(env); union { float64 f; uint64_t i; @@ -271,7 +271,7 @@ void helper_fildl_FT0(CPUX86State *env, int32_t val) void helper_flds_ST0(CPUX86State *env, uint32_t val) { - uint8_t old_flags = save_exception_flags(env); + int old_flags = save_exception_flags(env); int new_fpstt; union { float32 f; @@ -288,7 +288,7 @@ void helper_flds_ST0(CPUX86State *env, uint32_t val) void helper_fldl_ST0(CPUX86State *env, uint64_t val) { - uint8_t old_flags = save_exception_flags(env); + int old_flags = save_exception_flags(env); int new_fpstt; union { float64 f; @@ -338,7 +338,7 @@ void helper_fildll_ST0(CPUX86State *env, int64_t val) uint32_t helper_fsts_ST0(CPUX86State *env) { - uint8_t old_flags = save_exception_flags(env); + int old_flags = save_exception_flags(env); union { float32 f; uint32_t i; @@ -351,7 +351,7 @@ uint32_t helper_fsts_ST0(CPUX86State *env) uint64_t helper_fstl_ST0(CPUX86State *env) { - uint8_t old_flags = save_exception_flags(env); + int old_flags = save_exception_flags(env); union { float64 f; uint64_t i; @@ -364,7 +364,7 @@ uint64_t helper_fstl_ST0(CPUX86State *env) int32_t helper_fist_ST0(CPUX86State *env) { - uint8_t old_flags = save_exception_flags(env); + int old_flags = save_exception_flags(env); int32_t val; val = floatx80_to_int32(ST0, &env->fp_status); @@ -378,7 +378,7 @@ int32_t helper_fist_ST0(CPUX86State *env) int32_t helper_fistl_ST0(CPUX86State *env) { - uint8_t old_flags = save_exception_flags(env); + int old_flags = save_exception_flags(env); int32_t val; val = floatx80_to_int32(ST0, &env->fp_status); @@ -391,7 +391,7 @@ int32_t helper_fistl_ST0(CPUX86State *env) int64_t helper_fistll_ST0(CPUX86State *env) { - uint8_t old_flags = save_exception_flags(env); + int old_flags = save_exception_flags(env); int64_t val; val = floatx80_to_int64(ST0, &env->fp_status); @@ -404,7 +404,7 @@ int64_t helper_fistll_ST0(CPUX86State *env) int32_t helper_fistt_ST0(CPUX86State *env) { - uint8_t old_flags = save_exception_flags(env); + int old_flags = save_exception_flags(env); int32_t val; val = floatx80_to_int32_round_to_zero(ST0, &env->fp_status); @@ -418,7 +418,7 @@ int32_t helper_fistt_ST0(CPUX86State *env) int32_t helper_fisttl_ST0(CPUX86State *env) { - uint8_t old_flags = save_exception_flags(env); + int old_flags = save_exception_flags(env); int32_t val; val = floatx80_to_int32_round_to_zero(ST0, &env->fp_status); @@ -431,7 +431,7 @@ int32_t helper_fisttl_ST0(CPUX86State *env) int64_t helper_fisttll_ST0(CPUX86State *env) { - uint8_t old_flags = save_exception_flags(env); + int old_flags = save_exception_flags(env); int64_t val; val = floatx80_to_int64_round_to_zero(ST0, &env->fp_status); @@ -527,7 +527,7 @@ static const int fcom_ccval[4] = {0x0100, 0x4000, 0x0000, 0x4500}; void helper_fcom_ST0_FT0(CPUX86State *env) { - uint8_t old_flags = save_exception_flags(env); + int old_flags = save_exception_flags(env); FloatRelation ret; ret = floatx80_compare(ST0, FT0, &env->fp_status); @@ -537,7 +537,7 @@ void helper_fcom_ST0_FT0(CPUX86State *env) void helper_fucom_ST0_FT0(CPUX86State *env) { - uint8_t old_flags = save_exception_flags(env); + int old_flags = save_exception_flags(env); FloatRelation ret; ret = floatx80_compare_quiet(ST0, FT0, &env->fp_status); @@ -549,7 +549,7 @@ static const int fcomi_ccval[4] = {CC_C, CC_Z, 0, CC_Z | CC_P | CC_C}; void helper_fcomi_ST0_FT0(CPUX86State *env) { - uint8_t old_flags = save_exception_flags(env); + int old_flags = save_exception_flags(env); int eflags; FloatRelation ret; @@ -562,7 +562,7 @@ void helper_fcomi_ST0_FT0(CPUX86State *env) void helper_fucomi_ST0_FT0(CPUX86State *env) { - uint8_t old_flags = save_exception_flags(env); + int old_flags = save_exception_flags(env); int eflags; FloatRelation ret; @@ -575,28 +575,28 @@ void helper_fucomi_ST0_FT0(CPUX86State *env) void helper_fadd_ST0_FT0(CPUX86State *env) { - uint8_t old_flags = save_exception_flags(env); + int old_flags = save_exception_flags(env); ST0 = floatx80_add(ST0, FT0, &env->fp_status); merge_exception_flags(env, old_flags); } void helper_fmul_ST0_FT0(CPUX86State *env) { - uint8_t old_flags = save_exception_flags(env); + int old_flags = save_exception_flags(env); ST0 = floatx80_mul(ST0, FT0, &env->fp_status); merge_exception_flags(env, old_flags); } void helper_fsub_ST0_FT0(CPUX86State *env) { - uint8_t old_flags = save_exception_flags(env); + int old_flags = save_exception_flags(env); ST0 = floatx80_sub(ST0, FT0, &env->fp_status); merge_exception_flags(env, old_flags); } void helper_fsubr_ST0_FT0(CPUX86State *env) { - uint8_t old_flags = save_exception_flags(env); + int old_flags = save_exception_flags(env); ST0 = floatx80_sub(FT0, ST0, &env->fp_status); merge_exception_flags(env, old_flags); } @@ -615,28 +615,28 @@ void helper_fdivr_ST0_FT0(CPUX86State *env) void helper_fadd_STN_ST0(CPUX86State *env, int st_index) { - uint8_t old_flags = save_exception_flags(env); + int old_flags = save_exception_flags(env); ST(st_index) = floatx80_add(ST(st_index), ST0, &env->fp_status); merge_exception_flags(env, old_flags); } void helper_fmul_STN_ST0(CPUX86State *env, int st_index) { - uint8_t old_flags = save_exception_flags(env); + int old_flags = save_exception_flags(env); ST(st_index) = floatx80_mul(ST(st_index), ST0, &env->fp_status); merge_exception_flags(env, old_flags); } void helper_fsub_STN_ST0(CPUX86State *env, int st_index) { - uint8_t old_flags = save_exception_flags(env); + int old_flags = save_exception_flags(env); ST(st_index) = floatx80_sub(ST(st_index), ST0, &env->fp_status); merge_exception_flags(env, old_flags); } void helper_fsubr_STN_ST0(CPUX86State *env, int st_index) { - uint8_t old_flags = save_exception_flags(env); + int old_flags = save_exception_flags(env); ST(st_index) = floatx80_sub(ST0, ST(st_index), &env->fp_status); merge_exception_flags(env, old_flags); } @@ -861,7 +861,7 @@ void helper_fbld_ST0(CPUX86State *env, target_ulong ptr) void helper_fbst_ST0(CPUX86State *env, target_ulong ptr) { - uint8_t old_flags = save_exception_flags(env); + int old_flags = save_exception_flags(env); int v; target_ulong mem_ref, mem_end; int64_t val; @@ -1136,7 +1136,7 @@ static const struct f2xm1_data f2xm1_table[65] = { void helper_f2xm1(CPUX86State *env) { - uint8_t old_flags = save_exception_flags(env); + int old_flags = save_exception_flags(env); uint64_t sig = extractFloatx80Frac(ST0); int32_t exp = extractFloatx80Exp(ST0); bool sign = extractFloatx80Sign(ST0); @@ -1369,7 +1369,7 @@ static const struct fpatan_data fpatan_table[9] = { void helper_fpatan(CPUX86State *env) { - uint8_t old_flags = save_exception_flags(env); + int old_flags = save_exception_flags(env); uint64_t arg0_sig = extractFloatx80Frac(ST0); int32_t arg0_exp = extractFloatx80Exp(ST0); bool arg0_sign = extractFloatx80Sign(ST0); @@ -1808,7 +1808,7 @@ void helper_fpatan(CPUX86State *env) void helper_fxtract(CPUX86State *env) { - uint8_t old_flags = save_exception_flags(env); + int old_flags = save_exception_flags(env); CPU_LDoubleU temp; temp.d = ST0; @@ -1857,7 +1857,7 @@ void helper_fxtract(CPUX86State *env) static void helper_fprem_common(CPUX86State *env, bool mod) { - uint8_t old_flags = save_exception_flags(env); + int old_flags = save_exception_flags(env); uint64_t quotient; CPU_LDoubleU temp0, temp1; int exp0, exp1, expdiff; @@ -2053,7 +2053,7 @@ static void helper_fyl2x_common(CPUX86State *env, floatx80 arg, int32_t *exp, void helper_fyl2xp1(CPUX86State *env) { - uint8_t old_flags = save_exception_flags(env); + int old_flags = save_exception_flags(env); uint64_t arg0_sig = extractFloatx80Frac(ST0); int32_t arg0_exp = extractFloatx80Exp(ST0); bool arg0_sign = extractFloatx80Sign(ST0); @@ -2151,7 +2151,7 @@ void helper_fyl2xp1(CPUX86State *env) void helper_fyl2x(CPUX86State *env) { - uint8_t old_flags = save_exception_flags(env); + int old_flags = save_exception_flags(env); uint64_t arg0_sig = extractFloatx80Frac(ST0); int32_t arg0_exp = extractFloatx80Exp(ST0); bool arg0_sign = extractFloatx80Sign(ST0); @@ -2298,7 +2298,7 @@ void helper_fyl2x(CPUX86State *env) void helper_fsqrt(CPUX86State *env) { - uint8_t old_flags = save_exception_flags(env); + int old_flags = save_exception_flags(env); if (floatx80_is_neg(ST0)) { env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */ env->fpus |= 0x400; @@ -2324,14 +2324,14 @@ void helper_fsincos(CPUX86State *env) void helper_frndint(CPUX86State *env) { - uint8_t old_flags = save_exception_flags(env); + int old_flags = save_exception_flags(env); ST0 = floatx80_round_to_int(ST0, &env->fp_status); merge_exception_flags(env, old_flags); } void helper_fscale(CPUX86State *env) { - uint8_t old_flags = save_exception_flags(env); + int old_flags = save_exception_flags(env); if (floatx80_invalid_encoding(ST1, &env->fp_status) || floatx80_invalid_encoding(ST0, &env->fp_status)) { float_raise(float_flag_invalid, &env->fp_status); @@ -2369,7 +2369,7 @@ void helper_fscale(CPUX86State *env) } else { int n; FloatX80RoundPrec save = env->fp_status.floatx80_rounding_precision; - uint8_t save_flags = get_float_exception_flags(&env->fp_status); + int save_flags = get_float_exception_flags(&env->fp_status); set_float_exception_flags(0, &env->fp_status); n = floatx80_to_int32_round_to_zero(ST1, &env->fp_status); set_float_exception_flags(save_flags, &env->fp_status); @@ -3269,7 +3269,7 @@ void update_mxcsr_status(CPUX86State *env) void update_mxcsr_from_sse_status(CPUX86State *env) { - uint8_t flags = get_float_exception_flags(&env->sse_status); + int flags = get_float_exception_flags(&env->sse_status); /* * The MXCSR denormal flag has opposite semantics to * float_flag_input_denormal_flushed (the softfloat code sets that flag From patchwork Fri Jun 6 12:34:44 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 894454 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:ecd:b0:3a4:ee3f:8f15 with SMTP id ea13csp484243wrb; Fri, 6 Jun 2025 05:44:20 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVC0tFzf3WML8xpVl3WJ+eJMmNGwJB2V/c0/ID/t2lyF8kzNG1QB2d6WKabfof/bH3nDkmO6w==@linaro.org X-Google-Smtp-Source: AGHT+IHy3reeTCOmk+MEf+0LUC9PUzQFbsWtZHdqAw+Fglg+pmLhO+qPFiUIKYvAJigKT3feroUE X-Received: by 2002:a05:620a:28c3:b0:7ca:bdbe:c5af with SMTP id af79cd13be357-7d2298968f2mr410221985a.10.1749213859864; Fri, 06 Jun 2025 05:44:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1749213859; cv=none; d=google.com; s=arc-20240605; b=WZ21XNsKPahyi+BHNaDBhGxGbwraT6OYdrmhHYf1E+pb6LJ3ibiTWqiLR1ZQoIaHAS hTqGlyz9BeoGIkW9tSbHjIsxqE5BL9KxawajHSr4zpDuXT/f3hSpZ+kI6IMBIlW9bBXB TIGXZi3b57H2568Pg+07neplXjLehcesr80tzP1xcgHL7nRZorUPaMjAWkYketf5ieVB ooByf94kIRiD3Di4Kr04LaYljGSF/FDBsxstELNOr8oAmwfBhhVaNJOc0+rLE+2Seo4R /OtSnX7bCytXaXEciczn0WRU4pYK731Mg2ThK2iNVsBo8imc559X1kSM4u7F+45xEumL Y3fA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=GrcwJxyFvjJ8kIq5UYIgWeREzkk5jO+by21HvIVwTtM=; fh=mAkTJkmys9sHI/rBpbMW0gFFmA1+Q6Xmaym6a9hMRlo=; b=id8jIQIYqehIZYoUTPZar3dyjt2Vhg+bXRj93M58dZTBn3QEWGvqYiU1y/ctpH+xSY DMpzprQ+PCij+w1YBFpWyMxHjXbxQQF8Oaf3cOi5+nLgawIdJ7Xo9eV0KeOJGrwC41Af o/VEXAPk04J/tQE41K7X0ZUX/gq2iuo5wWgcc8v7Ftezszs/G3xqcucpRwhnWbZm5rht WirUZaZF4YHa7yHeI8dKK9f0q1iShIm4oTVJvSVCpHx1zHnpJFA8mU3wRGiX/kTjfxj8 g3EvgXMClS7cZJQdyvJa/k/NTgt8Me6YJwdMLVo2UHFZqdUHhzmFxdUEN/bvR+jIGvRH 5MHg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=hdE5GyQB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 6a1803df08f44-6fb09ab0768si17196756d6.81.2025.06.06.05.44.19 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 06 Jun 2025 05:44:19 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=hdE5GyQB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=redhat.com Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uNWM8-00063I-2l; Fri, 06 Jun 2025 08:39:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uNWJO-0003qT-ND for qemu-devel@nongnu.org; Fri, 06 Jun 2025 08:36:44 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uNWJL-00061U-2i for qemu-devel@nongnu.org; Fri, 06 Jun 2025 08:36:42 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1749213396; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=GrcwJxyFvjJ8kIq5UYIgWeREzkk5jO+by21HvIVwTtM=; b=hdE5GyQB3U66rAEYXse0da4YkoYSeiQbl4gn9oTJ1QPHSO3SnLmfATanXz40603fbjwGL+ n5zAIuTNL/Odno+gZLd4o+OyDDTtxwcXV+KuZnTV9dw+xC2I8mmqJm1Q8+rGmxgYqmN+US 53NFFB9AvtiS2l3VdV/sD0VEf5mK+20= Received: from mail-wm1-f70.google.com (mail-wm1-f70.google.com [209.85.128.70]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-680-gRytHlH6ND-WcFN1RucwlQ-1; Fri, 06 Jun 2025 08:36:35 -0400 X-MC-Unique: gRytHlH6ND-WcFN1RucwlQ-1 X-Mimecast-MFC-AGG-ID: gRytHlH6ND-WcFN1RucwlQ_1749213393 Received: by mail-wm1-f70.google.com with SMTP id 5b1f17b1804b1-451d3f03b74so12344825e9.3 for ; Fri, 06 Jun 2025 05:36:34 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749213392; x=1749818192; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GrcwJxyFvjJ8kIq5UYIgWeREzkk5jO+by21HvIVwTtM=; b=e1yxD19P2ePCqBLpJfZVvlbs06UnvpP1fynQwCsZvHHYPvYXO5XmYz8KtKepSEISp/ JYuxl4KC0wdkqQeUP9rj6Ss7uLa2NFH+tO+M4Sd4tRx1blUqK6OcdAtFWKu02a0YiYGX fwci/wnjd5y6c/jHCf/7hnB9B4T8Sl7ZO63x7e7DzFjw07h7PN4xrPg6B8J6OF0zoZH3 +r0DyHPU3b8MJbEaR1ktcRr2QmDNkMQ9AkJdB29UU6EaPCKrsowj7gWPQSBXAdmY36J+ yUs5xgx3/+gwFXMI64dUX+9emWOlXkAbi9uAowxnlp5NWt2iU+Ntwg5orTp7dYv5qqEp ROEg== X-Gm-Message-State: AOJu0YywIjd2P8Aszi5uHvl6nBM1WoBnKw+8/Hxj9SLDIeookCoUQV7J pVyiMhDviBGu7KgsgL/z6kEcPQaQt0+FNBMmZ0b+quJpff8hIl1WAr/oQGriPaCS4CxL3THX1U0 WMp/P1ONMm3ZrnlNoK68s+6nGA3PZVOy45+glPkb+hRGhU8IvKRnIvrpgLv783ur9HMbR4v4kG/ 5U/3gLUjBX07NW6Ez97H28lEljhYA46CJN+1OsPt8v X-Gm-Gg: ASbGncsk+HOVQnHmAwsiPUgs3z0S8q284vRsjbN9QMTNiLfeUQ/2J64vaytqOroTXhU 7NDDAoEYsWP8dE10690FxJlPWkftwzvqic+x3pk5A+6/9XAT16tZB0GPM3x2zjpKUUG7aX6yPd7 zJRLhW+plLN6zfa5T95pBPe5Oh2cw+sQRhwHQM54Jt1uVE90NvM2dK6b+AlbrR5OPHjZmvJNuAN u2rPGXXWxGf7JVtRfoYjPNCJEP/kM7ElK9ZhT04hfQVviPereHcKDnBbi3kkaiqrH1+I1mj76VF a9J/7EX+DLICK0KvuS6J56vL X-Received: by 2002:a05:600c:3b10:b0:450:cd25:e69c with SMTP id 5b1f17b1804b1-452013d1f6bmr31345665e9.21.1749213392101; Fri, 06 Jun 2025 05:36:32 -0700 (PDT) X-Received: by 2002:a05:600c:3b10:b0:450:cd25:e69c with SMTP id 5b1f17b1804b1-452013d1f6bmr31345405e9.21.1749213391615; Fri, 06 Jun 2025 05:36:31 -0700 (PDT) Received: from [192.168.10.48] ([151.49.64.79]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4521370936esm22684215e9.20.2025.06.06.05.36.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Jun 2025 05:36:29 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Peter Maydell , Richard Henderson Subject: [PULL 30/31] target/i386: Wire up MXCSR.DE and FPUS.DE correctly Date: Fri, 6 Jun 2025 14:34:44 +0200 Message-ID: <20250606123447.538131-31-pbonzini@redhat.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250606123447.538131-1-pbonzini@redhat.com> References: <20250606123447.538131-1-pbonzini@redhat.com> MIME-Version: 1.0 Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.104, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Peter Maydell The x86 DE bit in the FPU and MXCSR status is supposed to be set when an input denormal is consumed. We didn't previously report this from softfloat, so the x86 code either simply didn't set the DE bit or else incorrectly wired it up to denormal_flushed, depending on which register you looked at. Now we have input_denormal_used we can wire up these DE bits with the semantics they are supposed to have. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Link: https://lore.kernel.org/r/20250519145114.2786534-4-peter.maydell@linaro.org Signed-off-by: Paolo Bonzini --- target/i386/tcg/fpu_helper.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index 4732b718129..b3b23823fda 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -215,7 +215,7 @@ static void merge_exception_flags(CPUX86State *env, int old_flags) (new_flags & float_flag_overflow ? FPUS_OE : 0) | (new_flags & float_flag_underflow ? FPUS_UE : 0) | (new_flags & float_flag_inexact ? FPUS_PE : 0) | - (new_flags & float_flag_input_denormal_flushed ? FPUS_DE : 0))); + (new_flags & float_flag_input_denormal_used ? FPUS_DE : 0))); } static inline floatx80 helper_fdiv(CPUX86State *env, floatx80 a, floatx80 b) @@ -3254,6 +3254,7 @@ void update_mxcsr_status(CPUX86State *env) /* Set exception flags. */ set_float_exception_flags((mxcsr & FPUS_IE ? float_flag_invalid : 0) | + (mxcsr & FPUS_DE ? float_flag_input_denormal_used : 0) | (mxcsr & FPUS_ZE ? float_flag_divbyzero : 0) | (mxcsr & FPUS_OE ? float_flag_overflow : 0) | (mxcsr & FPUS_UE ? float_flag_underflow : 0) | @@ -3270,14 +3271,8 @@ void update_mxcsr_status(CPUX86State *env) void update_mxcsr_from_sse_status(CPUX86State *env) { int flags = get_float_exception_flags(&env->sse_status); - /* - * The MXCSR denormal flag has opposite semantics to - * float_flag_input_denormal_flushed (the softfloat code sets that flag - * only when flushing input denormals to zero, but SSE sets it - * only when not flushing them to zero), so is not converted - * here. - */ env->mxcsr |= ((flags & float_flag_invalid ? FPUS_IE : 0) | + (flags & float_flag_input_denormal_used ? FPUS_DE : 0) | (flags & float_flag_divbyzero ? FPUS_ZE : 0) | (flags & float_flag_overflow ? FPUS_OE : 0) | (flags & float_flag_underflow ? FPUS_UE : 0) | From patchwork Fri Jun 6 12:34:45 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 894453 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:ecd:b0:3a4:ee3f:8f15 with SMTP id ea13csp483877wrb; Fri, 6 Jun 2025 05:43:28 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUOG5fsx6W5iQ5P97/P5evLu78jxirJ3Q5MjgwEtJZgc44SIry6yjB0G7OcDCRsGpHfwXz3tQ==@linaro.org X-Google-Smtp-Source: AGHT+IHi2riKSzZMDdfdYqAv7CY1oXSRkxRS55IaEtKm2QUFf5jjX78IUmHmyUPWAySf42yLkKQ2 X-Received: by 2002:a05:622a:5809:b0:48d:8053:d8ee with SMTP id d75a77b69052e-4a5b9ec2e35mr55917071cf.36.1749213807833; Fri, 06 Jun 2025 05:43:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1749213807; cv=none; d=google.com; s=arc-20240605; b=iqZ8hNKJ/R5dhIlBC4mifgniJPQfvK/Q5ov0sEkrBjwp9BKM5LmpCCCH0QWvcT0a3C 4cJsaqnUJ21usT9EREN/xMDlQaZkH1ZWLf7jiEBiXgateL43bV7Fh/4+0tIvhx1cUlIt u/BhqqHwjFSIfkha4cuN73sXt7WRUl1n1K82kRzsxGrsPcrJNutx7kdQDiX0a5WocJW6 2uDCf1b4+08O+2hnBd3SpohoPlZRHOrqGbBIjLR5dTItFW0ELP0NYV7pYD6zjkrF/hSW QWk520tFcWwkXoxLTtl/q1V2eljLoUmp8XNz3o7MqwhinhhA4rvqGmPXlHPZBWsnD8GQ yqEQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=rqC/toGRqED1KkT0crHa1j83NZQruIG+EZBTua+GSwo=; fh=LCBicqeu5OWASEl1rLR9HJKJ77k8ScftFktlzJMVrFY=; b=MlIDmhk+fZffZQAxijOjasp3Abv0mnmSB6UUcRrXooFjjtzBPRS0dn7oQkqLBS/HQE VYhJ+2ryj3wbEjSbLRRPmNPZBgcNnHUQ6s6noLIPDZmE3mAAzSHGeoxcCq+gTccUFIkz xHVFbZvMF5MWCICJLEZgCYfzDU4PQckv7FmozT11WSiAc7H1wXnboS/y0lnPe9QxIxnl /vxDP96c3yAnqg2X6HV+f8ge7bpb5a+1ded5yfmq9Zmq8UYsZfc8JUCHuLQw9j9wNDZi WUpzjcRsGnxxF+4/KMu5szK7h3LnfX+tSSUm9L5zV0Iok81jbuLwuhJQVUUQtQjcnnF5 U3YQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=M8JMUQKH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d75a77b69052e-4a6198cea3asi15811281cf.661.2025.06.06.05.43.27 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 06 Jun 2025 05:43:27 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=M8JMUQKH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=redhat.com Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uNWMG-0006g3-Cb; Fri, 06 Jun 2025 08:39:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uNWJP-0003qV-0Z for qemu-devel@nongnu.org; Fri, 06 Jun 2025 08:36:44 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uNWJL-00061d-Qg for qemu-devel@nongnu.org; Fri, 06 Jun 2025 08:36:42 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1749213398; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=rqC/toGRqED1KkT0crHa1j83NZQruIG+EZBTua+GSwo=; b=M8JMUQKHqrJ71c/9wUfOeY60peAFd3v+7kk3OPd93WHbsuuTDkUpI+ZYDVeN5tnN1yEckb vtgtcwl1Co6siBlFG48tL6LioLReqZad5JvwEydh02q9TJa1/A6+9jRcfG+/vFipO/Ru68 wBk8lX4BoXRMcpNVm8+myzKO/c4puEo= Received: from mail-wm1-f72.google.com (mail-wm1-f72.google.com [209.85.128.72]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-477-4XWQn4KfNSGW0ho14ioqHQ-1; Fri, 06 Jun 2025 08:36:37 -0400 X-MC-Unique: 4XWQn4KfNSGW0ho14ioqHQ-1 X-Mimecast-MFC-AGG-ID: 4XWQn4KfNSGW0ho14ioqHQ_1749213396 Received: by mail-wm1-f72.google.com with SMTP id 5b1f17b1804b1-441c122fa56so10413105e9.2 for ; Fri, 06 Jun 2025 05:36:37 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749213395; x=1749818195; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rqC/toGRqED1KkT0crHa1j83NZQruIG+EZBTua+GSwo=; b=T0XYoCItzUfRrmpzKNea7WCSmuqsQJ4n33JxRDdbgzIJpuRiW7YV8PvQ5LBNlqSeZ7 e+LGmfps6nQvFUccYW8ambl9pufPIpvEIPrzsAOjZTbce6ef5yzxJBAHeeDSxImHDn03 5sMaRSqqsvgx+ICVzJaQtopebwx9MK80RggY4es8LgRWS0v3mckzdKxG+GQsDK2DtYAz TvMvnF/wArZIhwnDyz0asyYbixk0fj2YPHdDG48d4FpbZgRrR8Z6lPpODvc47YFuMAGE UPh/Ovi7JLPr0lzv1ae7ozGxGVQgZJPESyJrFXMX8SUsvkHsCGzvxJRHB3V0EQ1OPK4a AB0Q== X-Gm-Message-State: AOJu0YyOMuyHPYgPPLvb4OjpIo9oT7I8e1c2c7b2pHLEE6nW69yiXGw8 6cnZkfLznaVFcDpZZxC79iutTyV5aL8ZzynzFudZIgWgTflOcejSDxVnfj9UZ9CWcN8Y2fM036t xu/eCMDeIDYJlLdWowrgdYfXHYfYiIdPUYuzdpiHUiOqYiz6H9uSLKJlbFznWT3Fwt5Od9WRr7S sfuLQWVmKYjj25bHnUooS3KuoANaixxKhlh7GWN8N7 X-Gm-Gg: ASbGncvacimostrIJaCaStHpumBJFL7Nkb6XE+qyhrGRdES+MvVpuDidf6LJm/k3RWG hZhmpVdAN/4gf6AGDDhg3eaUxwSyvd7L+/dD8tK87VR0Tx4M202ymlfhMDzxvZY0WhEUMpZ+YVs tpIzpaLdy0a8pP1hhm/uj/b3j4LyTnf8GWXYP7cdFNykoyIz3vvwSSpX6+d9+gRKk7tL/hsi6aQ TflZvwG75gQ72kGNI+1OoqZNfLcvP38fTncGM8B9VOTpYhqK24rlqkR0d3Fp14Rig9JvSoYK6r9 bZN00lahrrH0PUFvsOBhA6Pq X-Received: by 2002:a05:600c:1c8b:b0:43c:e7ae:4bcf with SMTP id 5b1f17b1804b1-4520128d3e8mr38077575e9.0.1749213395567; Fri, 06 Jun 2025 05:36:35 -0700 (PDT) X-Received: by 2002:a05:600c:1c8b:b0:43c:e7ae:4bcf with SMTP id 5b1f17b1804b1-4520128d3e8mr38077235e9.0.1749213395047; Fri, 06 Jun 2025 05:36:35 -0700 (PDT) Received: from [192.168.10.48] ([151.49.64.79]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4526e163447sm19828035e9.17.2025.06.06.05.36.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Jun 2025 05:36:32 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Peter Maydell , Richard Henderson , Zhao Liu Subject: [PULL 31/31] tests/tcg/x86_64/fma: add test for exact-denormal output Date: Fri, 6 Jun 2025 14:34:45 +0200 Message-ID: <20250606123447.538131-32-pbonzini@redhat.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250606123447.538131-1-pbonzini@redhat.com> References: <20250606123447.538131-1-pbonzini@redhat.com> MIME-Version: 1.0 Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.104, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Peter Maydell Add some fma test cases that check for correct handling of FTZ and for the flag that indicates that the input denormal was consumed. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Zhao Liu Link: https://lore.kernel.org/r/20250519145114.2786534-5-peter.maydell@linaro.org Signed-off-by: Paolo Bonzini --- tests/tcg/x86_64/fma.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/tests/tcg/x86_64/fma.c b/tests/tcg/x86_64/fma.c index 46f863005ed..34219614c0a 100644 --- a/tests/tcg/x86_64/fma.c +++ b/tests/tcg/x86_64/fma.c @@ -82,6 +82,18 @@ static testdata tests[] = { */ { 0x3fdfffffffffffff, 0x001fffffffffffff, 0x801fffffffffffff, true, 0x8010000000000000, 0x20 }, /* Enabling FTZ shouldn't change flags */ + /* + * normal * 0 + a denormal. With FTZ disabled this gives an exact + * result (equal to the input denormal) that has consumed the denormal. + */ + { 0x3cc8000000000000, 0x0000000000000000, 0x8008000000000000, false, + 0x8008000000000000, 0x2 }, /* Denormal */ + /* + * With FTZ enabled, this consumes the denormal, returns zero (because + * flushed) and indicates also Underflow and Precision. + */ + { 0x3cc8000000000000, 0x0000000000000000, 0x8008000000000000, true, + 0x8000000000000000, 0x32 }, /* Precision, Underflow, Denormal */ }; int main(void)