From patchwork Mon Jun 9 20:05:06 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 895067 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B4967221265; Mon, 9 Jun 2025 20:05:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749499528; cv=none; b=NCoumrfjqG6fvRPhm7AKejnPS5FxsAYhB5CYLaFxGLpp+TH8MAJF95U16D+78ECY5eMPDWsFWqS5R8DLVII+6Kz9aa9I99iVyz7k+FsJgtzDDzUd99O1/6y1Js0YXR0fkp0GpB1D6cmf7p25Q3B2Qa/6jbO9YqJo0vNQyi9GLVI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749499528; c=relaxed/simple; bh=AVsyPkcu32VxzENcZiPE+1VWR7BX3rSOwxiwk/J8OKM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jFQ02pkHcRGMtS4p4Z0Mb/VOzvHO3Tifn2WZeJ8r8q669jh4Nzr935Idg/Hjb+tohCKhlj7J3roTZliMTsZPCq+98mHSUeMPiGcdCZSZBi/8IQ0fEMwDz8UexI8q1g798Hx7g2Sqj6J9vg35kD9VswG5N2/W/KYpnXnSek0kMBY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=FfInTSw8; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="FfInTSw8" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C266CC4CEF4; Mon, 9 Jun 2025 20:05:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749499528; bh=AVsyPkcu32VxzENcZiPE+1VWR7BX3rSOwxiwk/J8OKM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FfInTSw8PwshAt/BodyU1GLEjlOPFGZObGuIi44TDu+sJ+02Bx+jCWQ+E4FcYWbJH WcGkyuRldg/FjGSj3+HsUZFICu+QhoC+LhUl7xhuRgWTDwIBlS2JejdpPRT2DSXq0x 6gd6tixNxfBXJeoASKhBdOfbdwc/X+3f9M5SSJKXQ0wnffWyhXGURFiFdLhHyvIJNx 4GQAhipdEfcu/UeiBI16RIpQamMc95ShcbYZBpmbIOk+/XUPxfB2IhVgnJgPuZaqnl +eVSocCCAQPiJvAzW8ZklBf1Dzj4hD6HWmbn1mn00QVvX0owp4W8WMfI7MY7/4ImMb wXWSl2nnkNurw== From: Mario Limonciello To: =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: Mario Limonciello , Perry Yuan , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), "H . Peter Anvin" , Jonathan Corbet , Huang Rui , "Gautham R . Shenoy" , "Rafael J . Wysocki" , Viresh Kumar , platform-driver-x86@vger.kernel.org (open list:AMD HETERO CORE HARDWARE FEEDBACK DRIVER), linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-pm@vger.kernel.org (open list:AMD PSTATE DRIVER), Perry Yuan , Bagas Sanjaya Subject: [PATCH v11 01/13] Documentation: x86: Add AMD Hardware Feedback Interface documentation Date: Mon, 9 Jun 2025 15:05:06 -0500 Message-ID: <20250609200518.3616080-2-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250609200518.3616080-1-superm1@kernel.org> References: <20250609200518.3616080-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Perry Yuan Introduce a new documentation file, `amd_hfi.rst`, which delves into the implementation details of the AMD Hardware Feedback Interface and its associated driver, `amd_hfi`. This documentation describes how the driver provides hint to the OS scheduling which depends on the capability of core performance and efficiency ranking data. This documentation describes * The design of the driver * How the driver provides hints to the OS scheduling * How the driver interfaces with the kernel for efficiency ranking data. Reviewed-by: Bagas Sanjaya Signed-off-by: Perry Yuan Reviewed-by: Mario Limonciello Signed-off-by: Mario Limonciello --- v11: * Incorporate some feedback from Randy Dunlap v9: * Reflow to ~80 characters * Move higher in the index * 2024->2025 --- Documentation/arch/x86/amd-hfi.rst | 133 +++++++++++++++++++++++++++++ Documentation/arch/x86/index.rst | 1 + 2 files changed, 134 insertions(+) create mode 100644 Documentation/arch/x86/amd-hfi.rst diff --git a/Documentation/arch/x86/amd-hfi.rst b/Documentation/arch/x86/amd-hfi.rst new file mode 100644 index 0000000000000..bf3d3a1985a2d --- /dev/null +++ b/Documentation/arch/x86/amd-hfi.rst @@ -0,0 +1,133 @@ +.. SPDX-License-Identifier: GPL-2.0 + +====================================================================== +Hardware Feedback Interface For Hetero Core Scheduling On AMD Platform +====================================================================== + +:Copyright: 2025 Advanced Micro Devices, Inc. All Rights Reserved. + +:Author: Perry Yuan +:Author: Mario Limonciello + +Overview +-------- + +AMD Heterogeneous Core implementations are comprised of more than one +architectural class and CPUs are comprised of cores of various efficiency and +power capabilities: performance-oriented *classic cores* and power-efficient +*dense cores*. As such, power management strategies must be designed to +accommodate the complexities introduced by incorporating different core types. +Heterogeneous systems can also extend to more than two architectural classes +as well. The purpose of the scheduling feedback mechanism is to provide +information to the operating system scheduler in real time such that the +scheduler can direct threads to the optimal core. + +The goal of AMD's heterogeneous architecture is to attain power benefit by +sending background threads to the dense cores while sending high priority +threads to the classic cores. From a performance perspective, sending +background threads to dense cores can free up power headroom and allow the +classic cores to optimally service demanding threads. Furthermore, the area +optimized nature of the dense cores allows for an increasing number of +physical cores. This improved core density will have positive multithreaded +performance impact. + +AMD Heterogeneous Core Driver +----------------------------- + +The ``amd_hfi`` driver delivers the operating system a performance and energy +efficiency capability data for each CPU in the system. The scheduler can use +the ranking data from the HFI driver to make task placement decisions. + +Thread Classification and Ranking Table Interaction +---------------------------------------------------- + +The thread classification is used to select into a ranking table that +describes an efficiency and performance ranking for each classification. + +Threads are classified during runtime into enumerated classes. The classes +represent thread performance/power characteristics that may benefit from +special scheduling behaviors. The below table depicts an example of thread +classification and a preference where a given thread should be scheduled +based on its thread class. The real time thread classification is consumed +by the operating system and is used to inform the scheduler of where the +thread should be placed. + +Thread Classification Example Table +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ++----------+----------------+-------------------------------+---------------------+---------+ +| class ID | Classification | Preferred scheduling behavior | Preemption priority | Counter | ++----------+----------------+-------------------------------+---------------------+---------+ +| 0 | Default | Performant | Highest | | ++----------+----------------+-------------------------------+---------------------+---------+ +| 1 | Non-scalable | Efficient | Lowest | PMCx1A1 | ++----------+----------------+-------------------------------+---------------------+---------+ +| 2 | I/O bound | Efficient | Lowest | PMCx044 | ++----------+----------------+-------------------------------+---------------------+---------+ + +Thread classification is performed by the hardware each time that the thread is switched out. +Threads that don't meet any hardware specified criteria are classified as "default". + +AMD Hardware Feedback Interface +-------------------------------- + +The Hardware Feedback Interface provides to the operating system information +about the performance and energy efficiency of each CPU in the system. Each +capability is given as a unit-less quantity in the range [0-255]. A higher +performance value indicates higher performance capability, and a higher +efficiency value indicates more efficiency. Energy efficiency and performance +are reported in separate capabilities in the shared memory based ranking table. + +These capabilities may change at runtime as a result of changes in the +operating conditions of the system or the action of external factors. +Power Management firmware is responsible for detecting events that require +a reordering of the performance and efficiency ranking. Table updates happen +relatively infrequently and occur on the time scale of seconds or more. + +The following events trigger a table update: + * Thermal Stress Events + * Silent Compute + * Extreme Low Battery Scenarios + +The kernel or a userspace policy daemon can use these capabilities to modify +task placement decisions. For instance, if either the performance or energy +capabilities of a given logical processor becomes zero, it is an indication +that the hardware recommends to the operating system to not schedule any tasks +on that processor for performance or energy efficiency reasons, respectively. + +Implementation details for Linux +-------------------------------- + +The implementation of threads scheduling consists of the following steps: + +1. A thread is spawned and scheduled to the ideal core using the default + heterogeneous scheduling policy. +2. The processor profiles thread execution and assigns an enumerated + classification ID. + This classification is communicated to the OS via logical processor + scope MSR. +3. During the thread context switch out the operating system consumes the + workload (WL) classification which resides in a logical processor scope MSR. +4. The OS triggers the hardware to clear its history by writing to an MSR, + after consuming the WL classification and before switching in the new thread. +5. If due to the classification, ranking table, and processor availability, + the thread is not on its ideal processor, the OS will then consider + scheduling the thread on its ideal processor (if available). + +Ranking Table +------------- +The ranking table is a shared memory region that is used to communicate the +performance and energy efficiency capabilities of each CPU in the system. + +The ranking table design includes rankings for each APIC ID in the system and +rankings both for performance and efficiency for each workload classification. + +.. kernel-doc:: drivers/platform/x86/amd/hfi/hfi.c + :doc: amd_shmem_info + +Ranking Table update +--------------------------- +The power management firmware issues an platform interrupt after updating the +ranking table and is ready for the operating system to consume it. CPUs receive +such interrupt and read new ranking table from shared memory which PCCT table +has provided, then ``amd_hfi`` driver parses the new table to provide new +consume data for scheduling decisions. diff --git a/Documentation/arch/x86/index.rst b/Documentation/arch/x86/index.rst index 8ea762494bccf..f88bcfceb7f2a 100644 --- a/Documentation/arch/x86/index.rst +++ b/Documentation/arch/x86/index.rst @@ -28,6 +28,7 @@ x86-specific Documentation amd-debugging amd-memory-encryption amd_hsmp + amd-hfi tdx pti mds From patchwork Mon Jun 9 20:05:07 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 895484 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D1FFB221561; Mon, 9 Jun 2025 20:05:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749499530; cv=none; b=FaNiHoTqxS9cJK7zdsrk1QXS9qdqN9FgmN4VX7tBcTlPlY1IIsu3oCSwxj2hK6iVw73IC20RtgY95zKFKXDlrLiaOCgNVZDmNGt5u0rjeqUv3aDF8L4IyjMqgsuI3xHLvTHg06Jt0FV5U0qYQUeHNCiJEsDOYs3qreLJxOyKx24= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749499530; c=relaxed/simple; bh=xd0ANTCIAhb5Zjtakv/7sLtRH2DzucNIAXwrLWGgIz4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=PpCmHN+75twoCINswU8DmN4FtAP2lY8xBOdhHrTlxVOwGIFRizwc1S+46OqoDD3vDoF+fmTTxIsJAMfDZJDcvc6fPXM4xW4yJukducAvCo5pKVARt44Lf+xVem1l3JrDbj+mWEq/0xT3rHUYX3rKlSRqJrCLm73Gyxf3YB6GipI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=TnGdVmER; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="TnGdVmER" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CFFBCC4CEEB; Mon, 9 Jun 2025 20:05:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749499530; bh=xd0ANTCIAhb5Zjtakv/7sLtRH2DzucNIAXwrLWGgIz4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TnGdVmERsc8x5mmlV5akc6NtGvdrQGnXb8o+Vev8SjLffnbAdyTgnhvxJmK9/fJEq 1+NABlWeI5H+jE1gN8F2BlZdXoAUB8AsWloFmKfiiAztXTXHed3NJ11C7pEfiw75Mu UpMYmRLjNcTiAyB9WLeTQtuQjk8TIHXIKZqFsgux28poO/FylSJ+txSLH8fUpKrRXd HI4uIM4jKWF8Mat2+mpfxJf0ZI46PjYCz+BgRLPm413ZoZ9tmxihkIYNK2xApz0oR7 SN5bQ1rvCDwkmOvIGslqu2UZ71dF9FUx6kMax4U4iE3PC4+50rG8g9CWK3fF1EDfNL SmwPtr0Z8tlAg== From: Mario Limonciello To: =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: Mario Limonciello , Perry Yuan , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), "H . Peter Anvin" , Jonathan Corbet , Huang Rui , "Gautham R . Shenoy" , "Rafael J . Wysocki" , Viresh Kumar , platform-driver-x86@vger.kernel.org (open list:AMD HETERO CORE HARDWARE FEEDBACK DRIVER), linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-pm@vger.kernel.org (open list:AMD PSTATE DRIVER) Subject: [PATCH v11 02/13] MAINTAINERS: Add maintainer entry for AMD Hardware Feedback Driver Date: Mon, 9 Jun 2025 15:05:07 -0500 Message-ID: <20250609200518.3616080-3-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250609200518.3616080-1-superm1@kernel.org> References: <20250609200518.3616080-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mario Limonciello Introduce the `amd_hfi` driver into the MAINTAINERS file. The driver will support AMD Heterogeneous Core design which provides hardware feedback to the OS scheduler. Moving forward, Mario will be responsible for the maintenance and Perry will assist on review of patches related to this driver. Signed-off-by: Mario Limonciello --- MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index a8da72b0338da..748889bf7af96 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1112,6 +1112,15 @@ F: arch/x86/include/asm/amd/hsmp.h F: arch/x86/include/uapi/asm/amd_hsmp.h F: drivers/platform/x86/amd/hsmp/ +AMD HETERO CORE HARDWARE FEEDBACK DRIVER +M: Mario Limonciello +R: Perry Yuan +L: platform-driver-x86@vger.kernel.org +S: Supported +B: https://gitlab.freedesktop.org/drm/amd/-/issues +F: Documentation/arch/x86/amd-hfi.rst +F: drivers/platform/x86/amd/hfi/ + AMD IOMMU (AMD-VI) M: Joerg Roedel R: Suravee Suthikulpanit From patchwork Mon Jun 9 20:05:08 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 895066 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C9210221DAD; Mon, 9 Jun 2025 20:05:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749499532; cv=none; b=mUzpzg5mqcDkD95tO9pyYvogwPUlKUfaO/FyhIK9aRmCy/y/MyDv8sd/Pg0aGrl71q2gHBx+51ESwGIhhgS2KQMB0/F0ZPZGWOcmAduRFkI4ai5yda4Ee3t4zNNxPZ18Ny5fhuBmvwgBgiQaN1HrqKrYTgm+jBJPxSAsIrF6Sg0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749499532; c=relaxed/simple; bh=kkos//V5t0x/UeYtEykftE5VkPNQHr/VJTi0wRGvZFw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=JDxdEVANwLW+0OWUOu6fWo9J0LuV9BS/QUeA+PejPJfx1H+unPYI0DNIroItqs34hoF0t0P04ecgrY8UwIO2nge0bdm3VFi5c3bPSCUYdx8MAp+SqSj3oAa3902l1RFBSzqjgwbi9DcIp2/2JK/01NoeIujgGhhm5viJHWRebNg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=C1SKUd0c; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="C1SKUd0c" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B4600C4CEF5; Mon, 9 Jun 2025 20:05:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749499532; bh=kkos//V5t0x/UeYtEykftE5VkPNQHr/VJTi0wRGvZFw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=C1SKUd0c/ka5+i2L/ydwfilabOs63+nyhRdVTEGYJgnB68ivuelSGHY/om2faTWMU 8rT7p7cobfFu6Net5OQ8Yl81rdpO77zADqOhzc+ocHFsrly53FbWWrw767F5/Rm4I2 pS0VUMguohvZf1MuXZ8VA14xnjg+SUgHaCBKRpE36amNySvFhnTMUVzY2ztF1/koCX BKUBuQ/6gFyGSYqmFt06lOH5F3sbvi0l0Dm5dgbESGr2KyvTOnOlNX7o2/v4n5eKv5 LcPzRrx0CNoRhfPZps/tCeNGz+VyElHDT3D3L+m60HEnzwKIeu+1Ju4oDXcrYfrHw1 fb2EgGZpXzD9g== From: Mario Limonciello To: =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: Mario Limonciello , Perry Yuan , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), "H . Peter Anvin" , Jonathan Corbet , Huang Rui , "Gautham R . Shenoy" , "Rafael J . Wysocki" , Viresh Kumar , platform-driver-x86@vger.kernel.org (open list:AMD HETERO CORE HARDWARE FEEDBACK DRIVER), linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-pm@vger.kernel.org (open list:AMD PSTATE DRIVER) Subject: [PATCH v11 03/13] x86/msr-index: define AMD heterogeneous CPU related MSR Date: Mon, 9 Jun 2025 15:05:08 -0500 Message-ID: <20250609200518.3616080-4-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250609200518.3616080-1-superm1@kernel.org> References: <20250609200518.3616080-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Perry Yuan Introduces new MSR registers for AMD hardware feedback support. These registers enable the system to provide workload classification and configuration capabilities. Reviewed-by: Gautham R. Shenoy Signed-off-by: Perry Yuan Signed-off-by: Mario Limonciello --- v11: * Prefix new MSRs with MSR_AMD --- arch/x86/include/asm/msr-index.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index b7dded3c81132..4dbf6dbf4c1da 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -732,6 +732,11 @@ #define MSR_AMD64_PERF_CNTR_GLOBAL_CTL 0xc0000301 #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR 0xc0000302 +/* AMD Hardware Feedback Support MSRs */ +#define MSR_AMD_WORKLOAD_CLASS_CONFIG 0xc0000500 +#define MSR_AMD_WORKLOAD_CLASS_ID 0xc0000501 +#define MSR_AMD_WORKLOAD_HRST 0xc0000502 + /* AMD Last Branch Record MSRs */ #define MSR_AMD64_LBR_SELECT 0xc000010e From patchwork Mon Jun 9 20:05:09 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 895483 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B3490221FBA; Mon, 9 Jun 2025 20:05:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749499534; cv=none; b=kQPzBh0pSzZ7P2PM91pMOpc7uMcl6ZQ1KB8wKG3qqRJpDaic6IcVDHW+ZPJ7DPgBRtL98bLGe7tQtGlfUkhqZturyjbaG0xFJnJK0GBGuPP4IxYklDfqZY7BNqBnjQvMC8W/uvmlJS69VMx4I6Y4sB0iFon+eJzNL/jsqP4COrU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749499534; c=relaxed/simple; bh=lSaLanyn+kHdSqSgLQKmnHdRc7dGBuqWLjuUQUyNAwg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=I8tgxE8jOJ2PzqRMom4yjGjo1lwDqcFxGzAUAxWvhMU6vLefWzNxuda20aYyc3oliOg3rrPgtEL+3XlUfGDwqjd9+9qvlvV+azngEn3V/uD2Kyc7bGSEdG6qVb4k4/cBBiPTvntdIw3EKGuQnjgGACStNUq+RDSNFzuxUl2mafM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=qVeKutTc; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="qVeKutTc" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 94AF9C4CEFB; Mon, 9 Jun 2025 20:05:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749499534; bh=lSaLanyn+kHdSqSgLQKmnHdRc7dGBuqWLjuUQUyNAwg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=qVeKutTc/7rtY8nzOrQKBtdq1tjDUEDuoR+L552BrIm5dU57oQAwfbhBl5uCSr1rR xIpn4ZwE6TPRt3VgGlBMKgYgfILDBb+zl4S7yhNDLnnEpHwbmTDnGulvSH1kdBO9Zz nkGkLhJd+t3cjEBidI/H0NFBCA6oSUHNCP/Itax4IB9G1qQh8ZiFhxrR9rde8vG/vV 0KJzIMTmUXMyb7AlBBSz9VhEIOLaOAs7034XLYVZ35u7qI3PNL2796oDbjRM4aXTKt OTWBpQTq71DsHmO228+TsU2XxMD2LZyHcJ47FzIA5ztPF0f3ezYr+TwEAKns2ajDUQ VYEtvl6EJXz5g== From: Mario Limonciello To: =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: Mario Limonciello , Perry Yuan , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), "H . Peter Anvin" , Jonathan Corbet , Huang Rui , "Gautham R . Shenoy" , "Rafael J . Wysocki" , Viresh Kumar , platform-driver-x86@vger.kernel.org (open list:AMD HETERO CORE HARDWARE FEEDBACK DRIVER), linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-pm@vger.kernel.org (open list:AMD PSTATE DRIVER), Perry Yuan , Shyam Sundar S K Subject: [PATCH v11 04/13] platform/x86: hfi: Introduce AMD Hardware Feedback Interface Driver Date: Mon, 9 Jun 2025 15:05:09 -0500 Message-ID: <20250609200518.3616080-5-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250609200518.3616080-1-superm1@kernel.org> References: <20250609200518.3616080-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Perry Yuan The AMD Heterogeneous core design and Hardware Feedback Interface (HFI) provide behavioral classification and a dynamically updated ranking table for the scheduler to use when choosing cores for tasks. There are two CPU core types defined: `Classic Core` and `Dense Core`. "Classic" cores are the standard performance cores, while "Dense" cores are optimized for area and efficiency. Heterogeneous compute refers to CPU implementations that are comprised of more than one architectural class, each with two capabilities. This means each CPU reports two separate capabilities: "perf" and "eff". Each capability lists all core ranking numbers between 0 and 255, where a higher number represents a higher capability. Heterogeneous systems can also extend to more than two architectural classes. The purpose of the scheduling feedback mechanism is to provide information to the operating system scheduler in real time, allowing the scheduler to direct threads to the optimal core during task scheduling. All core ranking data are provided by the PMFW via a shared memory ranking table, which the driver reads and uses to update core capabilities to the scheduler. When the hardware updates the table, it generates a platform interrupt to notify the OS to read the new ranking table. Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 Reviewed-by: Gautham R. Shenoy Reviewed-by: Shyam Sundar S K Signed-off-by: Perry Yuan Co-developed-by: Mario Limonciello Signed-off-by: Mario Limonciello --- v11: * Rebase on v6.16-rc1 (Adjust for X86_FEATURE_AMD_HTR_CORES) * Use one tab + two spaces for help text (Randy) v9: * Drop Kconfig mentions of $FUTURE features * 2024 -> 2025 * change nr_class_id to unsigned * change classes number error to be clearer * symmetry for probe/cleanup * drop extra mutex v8: * s,devm_kzalloc,devm_kcalloc, * fold newlines from patch 5 into this patch * Drop ->cpu member, push to later patch * s,for_each_present_cpu,for_each_possible_cpu, v7: * Adjust Kconfig to 80 characters --- drivers/platform/x86/amd/Kconfig | 1 + drivers/platform/x86/amd/Makefile | 1 + drivers/platform/x86/amd/hfi/Kconfig | 17 +++ drivers/platform/x86/amd/hfi/Makefile | 7 ++ drivers/platform/x86/amd/hfi/hfi.c | 158 ++++++++++++++++++++++++++ 5 files changed, 184 insertions(+) create mode 100644 drivers/platform/x86/amd/hfi/Kconfig create mode 100644 drivers/platform/x86/amd/hfi/Makefile create mode 100644 drivers/platform/x86/amd/hfi/hfi.c diff --git a/drivers/platform/x86/amd/Kconfig b/drivers/platform/x86/amd/Kconfig index 63e4bd985699c..b813f92653686 100644 --- a/drivers/platform/x86/amd/Kconfig +++ b/drivers/platform/x86/amd/Kconfig @@ -6,6 +6,7 @@ source "drivers/platform/x86/amd/hsmp/Kconfig" source "drivers/platform/x86/amd/pmf/Kconfig" source "drivers/platform/x86/amd/pmc/Kconfig" +source "drivers/platform/x86/amd/hfi/Kconfig" config AMD_3D_VCACHE tristate "AMD 3D V-Cache Performance Optimizer Driver" diff --git a/drivers/platform/x86/amd/Makefile b/drivers/platform/x86/amd/Makefile index b0e284b5d4979..f6ff0c837f345 100644 --- a/drivers/platform/x86/amd/Makefile +++ b/drivers/platform/x86/amd/Makefile @@ -11,3 +11,4 @@ obj-$(CONFIG_AMD_HSMP) += hsmp/ obj-$(CONFIG_AMD_PMF) += pmf/ obj-$(CONFIG_AMD_WBRF) += wbrf.o obj-$(CONFIG_AMD_ISP_PLATFORM) += amd_isp4.o +obj-$(CONFIG_AMD_HFI) += hfi/ diff --git a/drivers/platform/x86/amd/hfi/Kconfig b/drivers/platform/x86/amd/hfi/Kconfig new file mode 100644 index 0000000000000..019638047e629 --- /dev/null +++ b/drivers/platform/x86/amd/hfi/Kconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# AMD Hardware Feedback Interface Driver +# + +config AMD_HFI + bool "AMD Hetero Core Hardware Feedback Driver" + depends on ACPI + depends on CPU_SUP_AMD + help + Select this option to enable the AMD Heterogeneous Core Hardware + Feedback Interface. If selected, hardware provides runtime thread + classification guidance to the operating system on the performance and + energy efficiency capabilities of each heterogeneous CPU core. These + capabilities may vary due to the inherent differences in the core types + and can also change as a result of variations in the operating + conditions of the system such as power and thermal limits. diff --git a/drivers/platform/x86/amd/hfi/Makefile b/drivers/platform/x86/amd/hfi/Makefile new file mode 100644 index 0000000000000..672c6ac106e95 --- /dev/null +++ b/drivers/platform/x86/amd/hfi/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# AMD Hardware Feedback Interface Driver +# + +obj-$(CONFIG_AMD_HFI) += amd_hfi.o +amd_hfi-objs := hfi.o diff --git a/drivers/platform/x86/amd/hfi/hfi.c b/drivers/platform/x86/amd/hfi/hfi.c new file mode 100644 index 0000000000000..e613bdf027b26 --- /dev/null +++ b/drivers/platform/x86/amd/hfi/hfi.c @@ -0,0 +1,158 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * AMD Hardware Feedback Interface Driver + * + * Copyright (C) 2025 Advanced Micro Devices, Inc. All Rights Reserved. + * + * Authors: Perry Yuan + * Mario Limonciello + */ + +#define pr_fmt(fmt) "amd-hfi: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define AMD_HFI_DRIVER "amd_hfi" + +#define AMD_HETERO_CPUID_27 0x80000027 + +static struct platform_device *device; + +struct amd_hfi_data { + const char *name; + struct device *dev; +}; + +struct amd_hfi_classes { + u32 perf; + u32 eff; +}; + +/** + * struct amd_hfi_cpuinfo - HFI workload class info per CPU + * @cpu: cpu index + * @class_index: workload class ID index + * @nr_class: max number of workload class supported + * @amd_hfi_classes: current cpu workload class ranking data + * + * Parameters of a logical processor linked with hardware feedback class. + */ +struct amd_hfi_cpuinfo { + int cpu; + s16 class_index; + u8 nr_class; + struct amd_hfi_classes *amd_hfi_classes; +}; + +static DEFINE_PER_CPU(struct amd_hfi_cpuinfo, amd_hfi_cpuinfo) = {.class_index = -1}; + +static int amd_hfi_alloc_class_data(struct platform_device *pdev) +{ + struct amd_hfi_cpuinfo *hfi_cpuinfo; + struct device *dev = &pdev->dev; + u32 nr_class_id; + int idx; + + nr_class_id = cpuid_eax(AMD_HETERO_CPUID_27); + if (nr_class_id > 255) { + dev_err(dev, "number of supported classes too large: %d\n", + nr_class_id); + return -EINVAL; + } + + for_each_possible_cpu(idx) { + struct amd_hfi_classes *classes; + + classes = devm_kcalloc(dev, + nr_class_id, + sizeof(struct amd_hfi_classes), + GFP_KERNEL); + if (!classes) + return -ENOMEM; + hfi_cpuinfo = per_cpu_ptr(&amd_hfi_cpuinfo, idx); + hfi_cpuinfo->amd_hfi_classes = classes; + hfi_cpuinfo->nr_class = nr_class_id; + } + + return 0; +} + +static const struct acpi_device_id amd_hfi_platform_match[] = { + {"AMDI0104", 0}, + { } +}; +MODULE_DEVICE_TABLE(acpi, amd_hfi_platform_match); + +static int amd_hfi_probe(struct platform_device *pdev) +{ + struct amd_hfi_data *amd_hfi_data; + int ret; + + if (!acpi_match_device(amd_hfi_platform_match, &pdev->dev)) + return -ENODEV; + + amd_hfi_data = devm_kzalloc(&pdev->dev, sizeof(*amd_hfi_data), GFP_KERNEL); + if (!amd_hfi_data) + return -ENOMEM; + + amd_hfi_data->dev = &pdev->dev; + platform_set_drvdata(pdev, amd_hfi_data); + + ret = amd_hfi_alloc_class_data(pdev); + if (ret) + return ret; + + return 0; +} + +static struct platform_driver amd_hfi_driver = { + .driver = { + .name = AMD_HFI_DRIVER, + .owner = THIS_MODULE, + .acpi_match_table = ACPI_PTR(amd_hfi_platform_match), + }, + .probe = amd_hfi_probe, +}; + +static int __init amd_hfi_init(void) +{ + int ret; + + if (acpi_disabled || + !cpu_feature_enabled(X86_FEATURE_AMD_HTR_CORES) || + !cpu_feature_enabled(X86_FEATURE_AMD_WORKLOAD_CLASS)) + return -ENODEV; + + device = platform_device_register_simple(AMD_HFI_DRIVER, -1, NULL, 0); + if (IS_ERR(device)) { + pr_err("unable to register HFI platform device\n"); + return PTR_ERR(device); + } + + ret = platform_driver_register(&amd_hfi_driver); + if (ret) + pr_err("failed to register HFI driver\n"); + + return ret; +} + +static __exit void amd_hfi_exit(void) +{ + platform_driver_unregister(&amd_hfi_driver); + platform_device_unregister(device); +} +module_init(amd_hfi_init); +module_exit(amd_hfi_exit); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("AMD Hardware Feedback Interface Driver"); From patchwork Mon Jun 9 20:05:10 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 895065 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD4AB2222D9; Mon, 9 Jun 2025 20:05:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749499536; cv=none; b=e0uLnqQOb9DhkixTfo4D0OGi5t+r4DjeDI1aM3TL7uQxxxi3ugiG9JHHeoDtsSnC4gvS4tl0bFMSoE5s0CgWnvQ9pS2ECGPfZeRUzJRvg1B7oiPyl6xt5596EHBKFF2oGzyiA45jvvVR2h/4nDOHkMBMyodxF8h34LDWDGwqSaE= ARC-Message-Signature: i=1; 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b=KKzTNkZYWGqzZarzDCIIckAXvxGhNrYEj8mlyyipRZZqQXjw008/9Puy/YoRZ/wvy kz2TwbGc8cRbj6CQnJFVZRL1YgeR3QP3aP25tbpFWp0BG7jZuYlrnhJ3D4E3NXgSpA apPvSX6I1uqkhGqXtu7dme0kd01mJ1Arc6zSk7da6P8tcDtMdhG/INS3f94cCsh3pe EfHSDgXlniX9PlYolg1+DFXWxR5WoSa3SDn1eVT9yTb9X9qTWagNRKt/TcCiIk09Op k1/GEssRu7V2zcAAjA0bcI/xZV6Dati+PIPybQvH9YYRdHpBPVod+ql9+UKmc1mBa+ P771auNkW+zmw== From: Mario Limonciello To: =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: Mario Limonciello , Perry Yuan , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), "H . Peter Anvin" , Jonathan Corbet , Huang Rui , "Gautham R . Shenoy" , "Rafael J . Wysocki" , Viresh Kumar , platform-driver-x86@vger.kernel.org (open list:AMD HETERO CORE HARDWARE FEEDBACK DRIVER), linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-pm@vger.kernel.org (open list:AMD PSTATE DRIVER), Perry Yuan Subject: [PATCH v11 05/13] platform/x86: hfi: parse CPU core ranking data from shared memory Date: Mon, 9 Jun 2025 15:05:10 -0500 Message-ID: <20250609200518.3616080-6-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250609200518.3616080-1-superm1@kernel.org> References: <20250609200518.3616080-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Perry Yuan When `amd_hfi` driver is loaded, it will use PCCT subspace type 4 table to retrieve the shared memory address which contains the CPU core ranking table. This table includes a header that specifies the number of ranking data entries to be parsed and rank each CPU core with the Performance and Energy Efficiency capability as implemented by the CPU power management firmware. Once the table has been parsed, each CPU is assigned a ranking score within its class. Subsequently, when the scheduler selects cores, it chooses from the ranking list based on the assigned scores in each class, thereby ensuring the optimal selection of CPU cores according to their predefined classifications and priorities. Reviewed-by: Ilpo Järvinen Signed-off-by: Perry Yuan Co-developed-by: Mario Limonciello Signed-off-by: Mario Limonciello --- v11: * shorter line for an error v9 * Fix an indexing logic error in amd_hfi_fill_metadata() leading to wrong APIC IDs being used. * Add a missing space * use dev_err/dev_warn * pcct->PCCT * signed->unsigned v3: * Reverse xmas tree order in amd_hfi_fill_metadata() * s,for_each_present_cpu,for_each_possible_cpu, v2: * Drop __packed --- drivers/platform/x86/amd/hfi/hfi.c | 198 +++++++++++++++++++++++++++++ 1 file changed, 198 insertions(+) diff --git a/drivers/platform/x86/amd/hfi/hfi.c b/drivers/platform/x86/amd/hfi/hfi.c index e613bdf027b26..4e991ef1ffb0b 100644 --- a/drivers/platform/x86/amd/hfi/hfi.c +++ b/drivers/platform/x86/amd/hfi/hfi.c @@ -18,21 +18,71 @@ #include #include #include +#include #include +#include #include #include +#include +#include + +#include + +#include +#include #define AMD_HFI_DRIVER "amd_hfi" +#define AMD_HFI_MAILBOX_COUNT 1 +#define AMD_HETERO_RANKING_TABLE_VER 2 #define AMD_HETERO_CPUID_27 0x80000027 static struct platform_device *device; +/** + * struct amd_shmem_info - Shared memory table for AMD HFI + * + * @header: The PCCT table header including signature, length flags and command. + * @version_number: Version number of the table + * @n_logical_processors: Number of logical processors + * @n_capabilities: Number of ranking dimensions (performance, efficiency, etc) + * @table_update_context: Command being sent over the subspace + * @n_bitmaps: Number of 32-bit bitmaps to enumerate all the APIC IDs + * This is based on the maximum APIC ID enumerated in the system + * @reserved: 24 bit spare + * @table_data: Bit Map(s) of enabled logical processors + * Followed by the ranking data for each logical processor + */ +struct amd_shmem_info { + struct acpi_pcct_ext_pcc_shared_memory header; + u32 version_number :8, + n_logical_processors :8, + n_capabilities :8, + table_update_context :8; + u32 n_bitmaps :8, + reserved :24; + u32 table_data[]; +}; + struct amd_hfi_data { const char *name; struct device *dev; + + /* PCCT table related */ + struct pcc_mbox_chan *pcc_chan; + void __iomem *pcc_comm_addr; + struct acpi_subtable_header *pcct_entry; + struct amd_shmem_info *shmem; }; +/** + * struct amd_hfi_classes - HFI class capabilities per CPU + * @perf: Performance capability + * @eff: Power efficiency capability + * + * Capabilities of a logical processor in the ranking table. These capabilities + * are unitless and specific to each HFI class. + */ struct amd_hfi_classes { u32 perf; u32 eff; @@ -41,21 +91,107 @@ struct amd_hfi_classes { /** * struct amd_hfi_cpuinfo - HFI workload class info per CPU * @cpu: cpu index + * @apic_id: apic id of the current cpu * @class_index: workload class ID index * @nr_class: max number of workload class supported + * @ipcc_scores: ipcc scores for each class * @amd_hfi_classes: current cpu workload class ranking data * * Parameters of a logical processor linked with hardware feedback class. */ struct amd_hfi_cpuinfo { int cpu; + u32 apic_id; s16 class_index; u8 nr_class; + int *ipcc_scores; struct amd_hfi_classes *amd_hfi_classes; }; static DEFINE_PER_CPU(struct amd_hfi_cpuinfo, amd_hfi_cpuinfo) = {.class_index = -1}; +static int find_cpu_index_by_apicid(unsigned int target_apicid) +{ + int cpu_index; + + for_each_possible_cpu(cpu_index) { + struct cpuinfo_x86 *info = &cpu_data(cpu_index); + + if (info->topo.apicid == target_apicid) { + pr_debug("match APIC id %u for CPU index: %d\n", + info->topo.apicid, cpu_index); + return cpu_index; + } + } + + return -ENODEV; +} + +static int amd_hfi_fill_metadata(struct amd_hfi_data *amd_hfi_data) +{ + struct acpi_pcct_ext_pcc_slave *pcct_ext = + (struct acpi_pcct_ext_pcc_slave *)amd_hfi_data->pcct_entry; + void __iomem *pcc_comm_addr; + u32 apic_start = 0; + + pcc_comm_addr = acpi_os_ioremap(amd_hfi_data->pcc_chan->shmem_base_addr, + amd_hfi_data->pcc_chan->shmem_size); + if (!pcc_comm_addr) { + dev_err(amd_hfi_data->dev, "failed to ioremap PCC common region mem\n"); + return -ENOMEM; + } + + memcpy_fromio(amd_hfi_data->shmem, pcc_comm_addr, pcct_ext->length); + iounmap(pcc_comm_addr); + + if (amd_hfi_data->shmem->header.signature != PCC_SIGNATURE) { + dev_err(amd_hfi_data->dev, "invalid signature in shared memory\n"); + return -EINVAL; + } + if (amd_hfi_data->shmem->version_number != AMD_HETERO_RANKING_TABLE_VER) { + dev_err(amd_hfi_data->dev, "invalid version %d\n", + amd_hfi_data->shmem->version_number); + return -EINVAL; + } + + for (unsigned int i = 0; i < amd_hfi_data->shmem->n_bitmaps; i++) { + u32 bitmap = amd_hfi_data->shmem->table_data[i]; + + for (unsigned int j = 0; j < BITS_PER_TYPE(u32); j++) { + u32 apic_id = i * BITS_PER_TYPE(u32) + j; + struct amd_hfi_cpuinfo *info; + int cpu_index, apic_index; + + if (!(bitmap & BIT(j))) + continue; + + cpu_index = find_cpu_index_by_apicid(apic_id); + if (cpu_index < 0) { + dev_warn(amd_hfi_data->dev, "APIC ID %u not found\n", apic_id); + continue; + } + + info = per_cpu_ptr(&amd_hfi_cpuinfo, cpu_index); + info->apic_id = apic_id; + + /* Fill the ranking data for each logical processor */ + info = per_cpu_ptr(&amd_hfi_cpuinfo, cpu_index); + apic_index = apic_start * info->nr_class * 2; + for (unsigned int k = 0; k < info->nr_class; k++) { + u32 *table = amd_hfi_data->shmem->table_data + + amd_hfi_data->shmem->n_bitmaps + + i * info->nr_class; + + info->amd_hfi_classes[k].eff = table[apic_index + 2 * k]; + info->amd_hfi_classes[k].perf = table[apic_index + 2 * k + 1]; + } + apic_start++; + } + } + + return 0; +} + static int amd_hfi_alloc_class_data(struct platform_device *pdev) { struct amd_hfi_cpuinfo *hfi_cpuinfo; @@ -72,6 +208,7 @@ static int amd_hfi_alloc_class_data(struct platform_device *pdev) for_each_possible_cpu(idx) { struct amd_hfi_classes *classes; + int *ipcc_scores; classes = devm_kcalloc(dev, nr_class_id, @@ -79,14 +216,71 @@ static int amd_hfi_alloc_class_data(struct platform_device *pdev) GFP_KERNEL); if (!classes) return -ENOMEM; + ipcc_scores = devm_kcalloc(dev, nr_class_id, sizeof(int), GFP_KERNEL); + if (!ipcc_scores) + return -ENOMEM; hfi_cpuinfo = per_cpu_ptr(&amd_hfi_cpuinfo, idx); hfi_cpuinfo->amd_hfi_classes = classes; + hfi_cpuinfo->ipcc_scores = ipcc_scores; hfi_cpuinfo->nr_class = nr_class_id; } return 0; } +static int amd_hfi_metadata_parser(struct platform_device *pdev, + struct amd_hfi_data *amd_hfi_data) +{ + struct acpi_pcct_ext_pcc_slave *pcct_ext; + struct acpi_subtable_header *pcct_entry; + struct mbox_chan *pcc_mbox_channels; + struct acpi_table_header *pcct_tbl; + struct pcc_mbox_chan *pcc_chan; + acpi_status status; + int ret; + + pcc_mbox_channels = devm_kcalloc(&pdev->dev, AMD_HFI_MAILBOX_COUNT, + sizeof(*pcc_mbox_channels), GFP_KERNEL); + if (!pcc_mbox_channels) + return -ENOMEM; + + pcc_chan = devm_kcalloc(&pdev->dev, AMD_HFI_MAILBOX_COUNT, + sizeof(*pcc_chan), GFP_KERNEL); + if (!pcc_chan) + return -ENOMEM; + + status = acpi_get_table(ACPI_SIG_PCCT, 0, &pcct_tbl); + if (ACPI_FAILURE(status) || !pcct_tbl) + return -ENODEV; + + /* get pointer to the first PCC subspace entry */ + pcct_entry = (struct acpi_subtable_header *) ( + (unsigned long)pcct_tbl + sizeof(struct acpi_table_pcct)); + + pcc_chan->mchan = &pcc_mbox_channels[0]; + + amd_hfi_data->pcc_chan = pcc_chan; + amd_hfi_data->pcct_entry = pcct_entry; + pcct_ext = (struct acpi_pcct_ext_pcc_slave *)pcct_entry; + + if (pcct_ext->length <= 0) + return -EINVAL; + + amd_hfi_data->shmem = devm_kzalloc(amd_hfi_data->dev, pcct_ext->length, GFP_KERNEL); + if (!amd_hfi_data->shmem) + return -ENOMEM; + + pcc_chan->shmem_base_addr = pcct_ext->base_address; + pcc_chan->shmem_size = pcct_ext->length; + + /* parse the shared memory info from the PCCT table */ + ret = amd_hfi_fill_metadata(amd_hfi_data); + + acpi_put_table(pcct_tbl); + + return ret; +} + static const struct acpi_device_id amd_hfi_platform_match[] = { {"AMDI0104", 0}, { } @@ -112,6 +306,10 @@ static int amd_hfi_probe(struct platform_device *pdev) if (ret) return ret; + ret = amd_hfi_metadata_parser(pdev, amd_hfi_data); + if (ret) + return ret; + return 0; } From patchwork Mon Jun 9 20:05:11 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 895482 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BA5452236E1; Mon, 9 Jun 2025 20:05:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Mon, 9 Jun 2025 20:05:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749499538; bh=IeL2jb17nVQNxtQ3Im8moxSVPX9fuLF1EUdc6AVisTM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KXXGrW+z3QZCjoo7VECEa8hcMZGHdWw9gQS5rd/bfjY44KP6xyo+xdhD9JpN9ney8 jorr4Vpn80V9n4trGYV07gmc4JdiYShlKlR75u53qTbaH2Dy8CsRLHwiaFIPzFfujA nzze8sYuMlIxIyoAE+HGD27mP9WthLsvqapvgj5VKBGQDBdfMKCBN+RZ367ryvJJLh ZPP1O546wm1Frwg0PevUibWvz331gDoA1lwcl8ukxKf2rLUdHw21VSagBnI1pF5m1d aMJW/yT+QduPM2G1eB8lRJXcCvtql9DtIo/qI/9lrjFDzEcuIGTHBGsyw+GDS67NYC iLahk8OQpUZUQ== From: Mario Limonciello To: =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: Mario Limonciello , Perry Yuan , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), "H . Peter Anvin" , Jonathan Corbet , Huang Rui , "Gautham R . Shenoy" , "Rafael J . Wysocki" , Viresh Kumar , platform-driver-x86@vger.kernel.org (open list:AMD HETERO CORE HARDWARE FEEDBACK DRIVER), linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-pm@vger.kernel.org (open list:AMD PSTATE DRIVER), Perry Yuan Subject: [PATCH v11 06/13] platform/x86: hfi: init per-cpu scores for each class Date: Mon, 9 Jun 2025 15:05:11 -0500 Message-ID: <20250609200518.3616080-7-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250609200518.3616080-1-superm1@kernel.org> References: <20250609200518.3616080-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Perry Yuan Initialize per cpu score `amd_hfi_ipcc_scores` which store energy score and performance score data for each class. `Classic core` and `Dense core` are ranked according to those values as energy efficiency capability or performance capability. OS scheduler will pick cores from the ranking list on each class ID for the thread which provide the class id got from hardware feedback interface. Reviewed-by: Gautham R. Shenoy Signed-off-by: Perry Yuan Co-developed-by: Mario Limonciello Signed-off-by: Mario Limonciello --- v8: * s,for_each_present_cpu,for_each_possible_cpu, v7: * Drop mutex, move to proper patch --- drivers/platform/x86/amd/hfi/hfi.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/platform/x86/amd/hfi/hfi.c b/drivers/platform/x86/amd/hfi/hfi.c index 4e991ef1ffb0b..234698696ac0b 100644 --- a/drivers/platform/x86/amd/hfi/hfi.c +++ b/drivers/platform/x86/amd/hfi/hfi.c @@ -228,6 +228,31 @@ static int amd_hfi_alloc_class_data(struct platform_device *pdev) return 0; } +static int amd_set_hfi_ipcc_score(struct amd_hfi_cpuinfo *hfi_cpuinfo, int cpu) +{ + for (int i = 0; i < hfi_cpuinfo->nr_class; i++) + WRITE_ONCE(hfi_cpuinfo->ipcc_scores[i], + hfi_cpuinfo->amd_hfi_classes[i].perf); + + return 0; +} + +static int update_hfi_ipcc_scores(void) +{ + int cpu; + int ret; + + for_each_possible_cpu(cpu) { + struct amd_hfi_cpuinfo *hfi_cpuinfo = per_cpu_ptr(&amd_hfi_cpuinfo, cpu); + + ret = amd_set_hfi_ipcc_score(hfi_cpuinfo, cpu); + if (ret) + return ret; + } + + return 0; +} + static int amd_hfi_metadata_parser(struct platform_device *pdev, struct amd_hfi_data *amd_hfi_data) { @@ -310,6 +335,10 @@ static int amd_hfi_probe(struct platform_device *pdev) if (ret) return ret; + ret = update_hfi_ipcc_scores(); + if (ret) + return ret; + return 0; } From patchwork Mon Jun 9 20:05:12 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 895064 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD33B22423A; Mon, 9 Jun 2025 20:05:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749499540; cv=none; b=EIaB6rZPN0kkwa1slvYfAbkr7I65MtqSF23QfjbDBdChXe3nuucZeq+egqkF2U9sw3huxTfZhohoPLMtAZNZtJmS0Ch0jVL/N7DOpr0mxNbSKgfZGTDX2i5f7/LIId6SVai6lcnTzkTX2a8YfJqdoOgTZqsbNpjRGmnnrAug0y4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749499540; c=relaxed/simple; bh=XPdm06fgKnGy2vaqeWKlv63m/AdHInspn/EDdleDghc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ZI/T75ugdqEk0F5UecvskQxHAp2WtFTyWdIZLMpxnj1qH5cbe+8/Ina60Gj6dl926KZ0R6+LSEqHX63wS/frj3CnkDYuT1w+ICBDJVRqiJdmnkUEhav1zqZDI3pX4xwqBphswfAlQBbnfqneP1Dj8UtnIygJM2HYpM7ZKWvm3FQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ML2yD8O4; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ML2yD8O4" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8C075C4CEEB; Mon, 9 Jun 2025 20:05:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749499540; bh=XPdm06fgKnGy2vaqeWKlv63m/AdHInspn/EDdleDghc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ML2yD8O4jWdjXBhfHo6JnX0zVhtBFoFQ8bvDlxf82t1VKWJKUO/W0swJ4bVwgFg4e F0aFD8nutOVLEynRotACol7GuX92S/D6NbQHN29X+UUqFYiOagiQw63u+zpzO5ddUn vqaTeM79YZ9SIHT9eheYzXKQKUHQ9Q8n+rMYc315IdzpMCNwNRPSssUsjDudJVltHA qftFxVsiG7UCHcBgNBaq6QD4ezAwBPlYx3KpcjMZMtC8xvjeVIfsZfsWNCgboh5OOW bRErXgynwA19ScwAcSmreSMsVYk+taqMskkOOSMKdsnuciGhUqvBvhwNdsZTJcoCVO /PAVL4MAIsHxg== From: Mario Limonciello To: =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: Mario Limonciello , Perry Yuan , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), "H . Peter Anvin" , Jonathan Corbet , Huang Rui , "Gautham R . Shenoy" , "Rafael J . Wysocki" , Viresh Kumar , platform-driver-x86@vger.kernel.org (open list:AMD HETERO CORE HARDWARE FEEDBACK DRIVER), linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-pm@vger.kernel.org (open list:AMD PSTATE DRIVER), Perry Yuan Subject: [PATCH v11 07/13] platform/x86: hfi: add online and offline callback support Date: Mon, 9 Jun 2025 15:05:12 -0500 Message-ID: <20250609200518.3616080-8-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250609200518.3616080-1-superm1@kernel.org> References: <20250609200518.3616080-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Perry Yuan There are some firmware parameters that need to be configured when a CPU core is brought online or offline. when CPU is online, it will initialize the workload classification parameters to CPU firmware which will trigger the workload class ID updating function. Once the CPU is going to offline, it will need to disable the workload classification function and clear the history. Reviewed-by: Gautham R. Shenoy Signed-off-by: Perry Yuan Co-developed-by: Mario Limonciello Signed-off-by: Mario Limonciello --- v11: * rebase on v6.16-rc1 (wrmsrl_on_cpu->wrmsrq_on_cpu) v9: * explicit conversion for bool * fix signed/unsigned for some prints v8: * Move cpus member to this patch * Add comment about online v7: * move mutex to this patch --- drivers/platform/x86/amd/hfi/hfi.c | 88 ++++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/drivers/platform/x86/amd/hfi/hfi.c b/drivers/platform/x86/amd/hfi/hfi.c index 234698696ac0b..681767d169c26 100644 --- a/drivers/platform/x86/amd/hfi/hfi.c +++ b/drivers/platform/x86/amd/hfi/hfi.c @@ -92,6 +92,7 @@ struct amd_hfi_classes { * struct amd_hfi_cpuinfo - HFI workload class info per CPU * @cpu: cpu index * @apic_id: apic id of the current cpu + * @cpus: mask of cpus associated with amd_hfi_cpuinfo * @class_index: workload class ID index * @nr_class: max number of workload class supported * @ipcc_scores: ipcc scores for each class @@ -102,6 +103,7 @@ struct amd_hfi_classes { struct amd_hfi_cpuinfo { int cpu; u32 apic_id; + cpumask_var_t cpus; s16 class_index; u8 nr_class; int *ipcc_scores; @@ -110,6 +112,8 @@ struct amd_hfi_cpuinfo { static DEFINE_PER_CPU(struct amd_hfi_cpuinfo, amd_hfi_cpuinfo) = {.class_index = -1}; +static DEFINE_MUTEX(hfi_cpuinfo_lock); + static int find_cpu_index_by_apicid(unsigned int target_apicid) { int cpu_index; @@ -237,6 +241,81 @@ static int amd_set_hfi_ipcc_score(struct amd_hfi_cpuinfo *hfi_cpuinfo, int cpu) return 0; } +static int amd_hfi_set_state(unsigned int cpu, bool state) +{ + int ret; + + ret = wrmsrq_on_cpu(cpu, MSR_AMD_WORKLOAD_CLASS_CONFIG, state ? 1 : 0); + if (ret) + return ret; + + return wrmsrq_on_cpu(cpu, MSR_AMD_WORKLOAD_HRST, 0x1); +} + +/** + * amd_hfi_online() - Enable workload classification on @cpu + * @cpu: CPU in which the workload classification will be enabled + * + * Return: 0 on success, negative error code on failure. + */ +static int amd_hfi_online(unsigned int cpu) +{ + struct amd_hfi_cpuinfo *hfi_info = per_cpu_ptr(&amd_hfi_cpuinfo, cpu); + struct amd_hfi_classes *hfi_classes; + int ret; + + if (WARN_ON_ONCE(!hfi_info)) + return -EINVAL; + + /* + * Check if @cpu as an associated, initialized and ranking data must + * be filled. + */ + hfi_classes = hfi_info->amd_hfi_classes; + if (!hfi_classes) + return -EINVAL; + + guard(mutex)(&hfi_cpuinfo_lock); + + if (!zalloc_cpumask_var(&hfi_info->cpus, GFP_KERNEL)) + return -ENOMEM; + + cpumask_set_cpu(cpu, hfi_info->cpus); + + ret = amd_hfi_set_state(cpu, true); + if (ret) + pr_err("WCT enable failed for CPU %u\n", cpu); + + return ret; +} + +/** + * amd_hfi_offline() - Disable workload classification on @cpu + * @cpu: CPU in which the workload classification will be disabled + * + * Remove @cpu from those covered by its HFI instance. + * + * Return: 0 on success, negative error code on failure + */ +static int amd_hfi_offline(unsigned int cpu) +{ + struct amd_hfi_cpuinfo *hfi_info = &per_cpu(amd_hfi_cpuinfo, cpu); + int ret; + + if (WARN_ON_ONCE(!hfi_info)) + return -EINVAL; + + guard(mutex)(&hfi_cpuinfo_lock); + + ret = amd_hfi_set_state(cpu, false); + if (ret) + pr_err("WCT disable failed for CPU %u\n", cpu); + + free_cpumask_var(hfi_info->cpus); + + return ret; +} + static int update_hfi_ipcc_scores(void) { int cpu; @@ -339,6 +418,15 @@ static int amd_hfi_probe(struct platform_device *pdev) if (ret) return ret; + /* + * Tasks will already be running at the time this happens. This is + * OK because rankings will be adjusted by the callbacks. + */ + ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/amd_hfi:online", + amd_hfi_online, amd_hfi_offline); + if (ret < 0) + return ret; + return 0; } From patchwork Mon Jun 9 20:05:13 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 895481 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6745D224AE8; Mon, 9 Jun 2025 20:05:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749499542; cv=none; b=S31YV1FjM16Yo6dio1AjMRcyfFqZrFActyAGEQgOJwd80HQ8Rl/s71Xw5zscQwRJ+yA2kAFy308hfMhkbmRHfKPT6ge3dhMf48Bm7eWiY5z0nbjcZqjQhBzUW8bMS4Xbi0lMFd4H4BqrPSv1dxF4ajZha4OlhJT03g/83fdCmLU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749499542; c=relaxed/simple; bh=A0PimShuH3lA4xwk1tp0mt3DYevGbEQvlECDRve1+7U=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=DirOuAHLT+fdzi67NafByK6jbG7HlteK5AflJLHxDxva4ekFIGTuCYK5MTqEK1RZ4YtAt06BvQkiL2H+ptQnvI9/NEMhIXfJOMB2UI4mJMDUQD6aHbo2Wf37mEUOcgRycJ4SYo6k6UvppYjROrU1Tu6w4ytjeF9B5S07waOb8/g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=pdQEyUPB; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="pdQEyUPB" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 893F7C4CEF2; Mon, 9 Jun 2025 20:05:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749499542; bh=A0PimShuH3lA4xwk1tp0mt3DYevGbEQvlECDRve1+7U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=pdQEyUPBjA9sfxRU11xE0csgHTF7mv/6v6JroqFi8mFELLfhIKejyV5TBGcPVlPIX 59mj7JVhkj44qD9wdZLpZ5i0xK2VbORHxSuKSSESUTtQpF2GPToDqEJ9WVtAWDNNtq JS8gac4lCOP2d5XMJIUJ/mhILaX5gz4QuKrwiUwSoGnjfLbAMs5HHK9FH2LqdgerAu ru6jrPo+jxv7IczCCIfWiadmDDc79F/OIUvaPKKJuwOdYJMnespAWuh+VltEG1LuNB ++ZEiBues6HX9o595JxPJQ5VAlVzmBTA0xhHdrTM++DkQRo4/5Bl7Ymh0ZspVt77Kl oNY2u2wQXU4Fw== From: Mario Limonciello To: =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: Mario Limonciello , Perry Yuan , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), "H . Peter Anvin" , Jonathan Corbet , Huang Rui , "Gautham R . Shenoy" , "Rafael J . Wysocki" , Viresh Kumar , platform-driver-x86@vger.kernel.org (open list:AMD HETERO CORE HARDWARE FEEDBACK DRIVER), linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-pm@vger.kernel.org (open list:AMD PSTATE DRIVER), Perry Yuan Subject: [PATCH v11 08/13] platform/x86: hfi: add power management callback Date: Mon, 9 Jun 2025 15:05:13 -0500 Message-ID: <20250609200518.3616080-9-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250609200518.3616080-1-superm1@kernel.org> References: <20250609200518.3616080-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Perry Yuan Introduces power management callbacks for the `amd_hfi` driver. Specifically, the `suspend` and `resume` callbacks have been added to handle the necessary operations during system low power states and wake-up. Reviewed-by: Gautham R. Shenoy Signed-off-by: Perry Yuan Co-developed-by: Mario Limonciello Signed-off-by: Mario Limonciello --- drivers/platform/x86/amd/hfi/hfi.c | 33 ++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/platform/x86/amd/hfi/hfi.c b/drivers/platform/x86/amd/hfi/hfi.c index 681767d169c26..2c6832a3020ec 100644 --- a/drivers/platform/x86/amd/hfi/hfi.c +++ b/drivers/platform/x86/amd/hfi/hfi.c @@ -385,6 +385,38 @@ static int amd_hfi_metadata_parser(struct platform_device *pdev, return ret; } +static int amd_hfi_pm_resume(struct device *dev) +{ + int ret, cpu; + + for_each_online_cpu(cpu) { + ret = amd_hfi_set_state(cpu, true); + if (ret < 0) { + dev_err(dev, "failed to enable workload class config: %d\n", ret); + return ret; + } + } + + return 0; +} + +static int amd_hfi_pm_suspend(struct device *dev) +{ + int ret, cpu; + + for_each_online_cpu(cpu) { + ret = amd_hfi_set_state(cpu, false); + if (ret < 0) { + dev_err(dev, "failed to disable workload class config: %d\n", ret); + return ret; + } + } + + return 0; +} + +static DEFINE_SIMPLE_DEV_PM_OPS(amd_hfi_pm_ops, amd_hfi_pm_suspend, amd_hfi_pm_resume); + static const struct acpi_device_id amd_hfi_platform_match[] = { {"AMDI0104", 0}, { } @@ -434,6 +466,7 @@ static struct platform_driver amd_hfi_driver = { .driver = { .name = AMD_HFI_DRIVER, .owner = THIS_MODULE, + .pm = &amd_hfi_pm_ops, .acpi_match_table = ACPI_PTR(amd_hfi_platform_match), }, .probe = amd_hfi_probe, From patchwork Mon Jun 9 20:05:14 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 895063 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 516BA22423A; Mon, 9 Jun 2025 20:05:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749499544; cv=none; b=lL4ebOZtv6ANpYpb+UwFBEIutzQgPnOdwqyEOEYQUx1G4wFoVVWvldyMtIzGzrUZqghBQEQg2o7V8LHScvnxm3b5h1RqAOcbFymRUlLQ/dpuZLywBSqPvV3He+9eZw/wDtZM881TLMj9VmJfDte/eBFAPjpyT0uwAnDlZ6DWIDw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749499544; c=relaxed/simple; bh=CC3ONKTbRtD9u8FsFEBcRqpmUcqJA7JDfWnuy7ME05E=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=sLOQKkDF+E+rcRVJ4Vfe475yy4gyi+zs1VrHcagtPLAJX/Y7i/8rqKDDWYg3yZhAgbqhCrPsQl9WzByVu7piE+3xNKh119sdS61uO/w8H75cIf9NJ1RktXvckvSTjCbxRD+eT12jSbKCf3R1CLi+cmsvWCTj+bj0XX1A0/+KZLw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=I6XeH2mx; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="I6XeH2mx" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 836B6C4CEF0; Mon, 9 Jun 2025 20:05:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749499544; bh=CC3ONKTbRtD9u8FsFEBcRqpmUcqJA7JDfWnuy7ME05E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=I6XeH2mx97jgo/6o57NQQrj2A+Xl8cJCzQQbu1BkSsyct/nF7eL9b5Z6btlF7pNMo wlip4mu5w7psSaicD76pGWh3m0PNGNinDmpaKCyGE1hfgwpHA66/xQKxwihBsibH3+ 2vFxQtlP0DdOuky1nPfaaH4kzXOluCmR2pj+e/EKIclO8ZGsXrX5/KVOQ6zCS/ZOhg pBVAVpZeLKrqmCf9pUVWf33Ujv87Gj/zqc0/iKfFUqNQtdKOwCz2GY6CKCIoc36Fr3 cWZc0542WXy3AtRW+qiNuMO79opi7w9jxrlTTW3Uf0q7Yw9MIEB3DtMT1W/hsAAYbC RdZn8SOqii4aQ== From: Mario Limonciello To: =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: Mario Limonciello , Perry Yuan , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), "H . Peter Anvin" , Jonathan Corbet , Huang Rui , "Gautham R . Shenoy" , "Rafael J . Wysocki" , Viresh Kumar , platform-driver-x86@vger.kernel.org (open list:AMD HETERO CORE HARDWARE FEEDBACK DRIVER), linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-pm@vger.kernel.org (open list:AMD PSTATE DRIVER) Subject: [PATCH v11 09/13] x86/process: Clear hardware feedback history for AMD processors Date: Mon, 9 Jun 2025 15:05:14 -0500 Message-ID: <20250609200518.3616080-10-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250609200518.3616080-1-superm1@kernel.org> References: <20250609200518.3616080-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Perry Yuan Incorporate a mechanism within the context switching code to reset the hardware history for AMD processors. Specifically, when a task is switched in, the class ID was read and reset the hardware workload classification history of CPU firmware and then it start to trigger workload classification for the next running thread. Signed-off-by: Perry Yuan Co-developed-by: Mario Limonciello Signed-off-by: Mario Limonciello --- v8: * Only for 64 bit --- arch/x86/kernel/process_64.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c index 8d6cf25127aab..f386928c472db 100644 --- a/arch/x86/kernel/process_64.c +++ b/arch/x86/kernel/process_64.c @@ -707,6 +707,10 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p) /* Load the Intel cache allocation PQR MSR. */ resctrl_arch_sched_in(next_p); + /* Reset hw history on AMD CPUs */ + if (cpu_feature_enabled(X86_FEATURE_AMD_WORKLOAD_CLASS)) + wrmsrl(MSR_AMD_WORKLOAD_HRST, 0x1); + return prev_p; } From patchwork Mon Jun 9 20:05:15 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 895480 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7B3E222579B; Mon, 9 Jun 2025 20:05:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749499546; cv=none; b=f64ipbEFbo61Eac5BSXOSvl82SWmIXU2YZULp24pwmkE2It6uCNIVBNePROpSLgRifyyTehu+y+Y/JQxhBUxno4IdNS5euGe/TI7W4FeLrQ3impk2cFonrSgAROjcD9Wq/bzK/2IYuv/UttIBmu1EWpKN2oDpvOnWd77Qhucdtg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749499546; c=relaxed/simple; bh=4bssHTqSWbzsmJNwqd3WJzHulDgwe+FA6qh8+k0oGo0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=u0253sauPvWK/ItwUjlxoTYJ2uUnRMjkFHrEmzqTLdYc+czUmwtPuly7MwAZsaaktU4+xZ43XOybBYhpSelI6s7r8hp2miJU8k5nWWItVgDsCNVd6daB/U6UV4VjV8DPvYqGywnWuuLaD+qEnvotxxlAenVBiDbb/sZmaPcURMU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=FjV2qzMR; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="FjV2qzMR" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6A4A4C4CEF2; Mon, 9 Jun 2025 20:05:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749499546; bh=4bssHTqSWbzsmJNwqd3WJzHulDgwe+FA6qh8+k0oGo0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FjV2qzMRxYPtazheh66pTCb+v2t/POJnFw8TOndgrLP41qptXchDZNGsVr3BCpl90 Hm7ovUSbyGNO6Z6TavPmkG1WZHSFKgWVJZs8egiClUHITkUnGH9sNYXsSSrmc6j5Po VKY2aWQu8Cwk5yOgR6z6xxgUVIvqbaJLmdrlXbwGfrx0jIOiIi13WywTH1BvK50Eji KQWmGKg7FDh6OZLSkY3c8t3BKncAdZruHUmgOkE6USOQ18eHoDKMEPKMFqfz5ykpZS qgdzfy9cm9pjdlZ11SVKUMKteTPwiAgynldi2Q8dJvuilmDv9gU0MQg2DI2AGyalg9 bOvC98yeoJRwA== From: Mario Limonciello To: =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: Mario Limonciello , Perry Yuan , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), "H . Peter Anvin" , Jonathan Corbet , Huang Rui , "Gautham R . Shenoy" , "Rafael J . Wysocki" , Viresh Kumar , platform-driver-x86@vger.kernel.org (open list:AMD HETERO CORE HARDWARE FEEDBACK DRIVER), linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-pm@vger.kernel.org (open list:AMD PSTATE DRIVER) Subject: [PATCH v11 10/13] cpufreq/amd-pstate: Disable preferred cores on designs with workload classification Date: Mon, 9 Jun 2025 15:05:15 -0500 Message-ID: <20250609200518.3616080-11-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250609200518.3616080-1-superm1@kernel.org> References: <20250609200518.3616080-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mario Limonciello On designs that have workload classification, it's preferred that the amd-hfi driver is used to provide hints to the scheduler of which cores to use instead of the amd-pstate driver. Reviewed-by: Gautham R. Shenoy Reviewed-by: Perry Yuan Signed-off-by: Mario Limonciello --- drivers/cpufreq/amd-pstate.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 6ba0e4478877e..f48b65980ed18 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -834,6 +834,12 @@ static void amd_pstate_init_prefcore(struct amd_cpudata *cpudata) /* user disabled or not detected */ if (!amd_pstate_prefcore) return; + /* should use amd-hfi instead */ + if (cpu_feature_enabled(X86_FEATURE_AMD_WORKLOAD_CLASS) && + IS_ENABLED(CONFIG_AMD_HFI)) { + amd_pstate_prefcore = false; + return; + } cpudata->hw_prefcore = true; From patchwork Mon Jun 9 20:05:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 895062 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 13A5F226545; Mon, 9 Jun 2025 20:05:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749499548; cv=none; b=k6tmALklJJnK2K9i21XCzb6NhWlo8gH4FmpczlWPwwCPVo/zCasSduma8Uonvh/g6PtFxZKqg8mZSBpveE+y9/VIVAFq1X9K75WWhjlZ9OvdJJTXWbXPup5hX4mgXb9gcYp0YLeiKnlmtlapoo9aZYuYdaTMz74UhfuF2eC7pBY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749499548; c=relaxed/simple; bh=RfYSMBAHzzthlwu3koY6cePj5ENJllMqmK+GS+Iydb4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CWJtBC3G+BJh/0z9g/izvtSEGs6o6FmnhvE5YH8ZwlHvBWXnl5PEx25gjH13C/MsQFtlP6Kq9DEELEjGerC4xF8iS3bY21h1ubM7mF31kU92ON0fZROouO+Tf0Sh51tLVyFXER7C2xoSP9fy2fgHQvDv2UtYy75nAJgwmsooZnE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=lM3a3Z7e; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="lM3a3Z7e" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4BC37C4CEEB; Mon, 9 Jun 2025 20:05:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749499547; bh=RfYSMBAHzzthlwu3koY6cePj5ENJllMqmK+GS+Iydb4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lM3a3Z7eNvpRoggFW9Ha3sbovVNPovPMMyVZeTGMNZC7vHKw83aiZAndrA1x1U/SE BLwvAue2BCHgkM622mjO/MfUHx//u7+gZP81kt26ijuu6hYWfI5U1bnJ58O8I7gpgX V/emS1k/FO6kb/HlQBsZeJQ5Q5vlWXHBMqE+zLoPe5DRkJDYUnhxb4NpD4fSqn17EB cW0Rf8qSSvEwkuzrdukkn7OHqnoWKvkRMKSKQXHhS5cJrp02vFfHAfgLekgMwotNng hrhwHJkExcdQCgjuU/gDuReYKpxhCGzH0ve8g7LKBwTBa7n8otqWXTi/7DlskIyk6y JitrHE2xJcROg== From: Mario Limonciello To: =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: Mario Limonciello , Perry Yuan , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), "H . Peter Anvin" , Jonathan Corbet , Huang Rui , "Gautham R . Shenoy" , "Rafael J . Wysocki" , Viresh Kumar , platform-driver-x86@vger.kernel.org (open list:AMD HETERO CORE HARDWARE FEEDBACK DRIVER), linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-pm@vger.kernel.org (open list:AMD PSTATE DRIVER) Subject: [PATCH v11 11/13] platform/x86/amd: hfi: Set ITMT priority from ranking data Date: Mon, 9 Jun 2025 15:05:16 -0500 Message-ID: <20250609200518.3616080-12-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250609200518.3616080-1-superm1@kernel.org> References: <20250609200518.3616080-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mario Limonciello The static ranking data that is read at module load should be used to set up the priorities for the cores relative to the performance values. Reviewed-by: Gautham R. Shenoy Signed-off-by: Mario Limonciello --- drivers/platform/x86/amd/hfi/Kconfig | 1 + drivers/platform/x86/amd/hfi/hfi.c | 10 ++++++++++ 2 files changed, 11 insertions(+) diff --git a/drivers/platform/x86/amd/hfi/Kconfig b/drivers/platform/x86/amd/hfi/Kconfig index 019638047e629..fecef68480234 100644 --- a/drivers/platform/x86/amd/hfi/Kconfig +++ b/drivers/platform/x86/amd/hfi/Kconfig @@ -7,6 +7,7 @@ config AMD_HFI bool "AMD Hetero Core Hardware Feedback Driver" depends on ACPI depends on CPU_SUP_AMD + depends on SCHED_MC_PRIO help Select this option to enable the AMD Heterogeneous Core Hardware Feedback Interface. If selected, hardware provides runtime thread diff --git a/drivers/platform/x86/amd/hfi/hfi.c b/drivers/platform/x86/amd/hfi/hfi.c index 2c6832a3020ec..ef38bc367eecc 100644 --- a/drivers/platform/x86/amd/hfi/hfi.c +++ b/drivers/platform/x86/amd/hfi/hfi.c @@ -114,6 +114,12 @@ static DEFINE_PER_CPU(struct amd_hfi_cpuinfo, amd_hfi_cpuinfo) = {.class_index = static DEFINE_MUTEX(hfi_cpuinfo_lock); +static void amd_hfi_sched_itmt_work(struct work_struct *work) +{ + sched_set_itmt_support(); +} +static DECLARE_WORK(sched_amd_hfi_itmt_work, amd_hfi_sched_itmt_work); + static int find_cpu_index_by_apicid(unsigned int target_apicid) { int cpu_index; @@ -238,6 +244,8 @@ static int amd_set_hfi_ipcc_score(struct amd_hfi_cpuinfo *hfi_cpuinfo, int cpu) WRITE_ONCE(hfi_cpuinfo->ipcc_scores[i], hfi_cpuinfo->amd_hfi_classes[i].perf); + sched_set_itmt_core_prio(hfi_cpuinfo->ipcc_scores[0], cpu); + return 0; } @@ -459,6 +467,8 @@ static int amd_hfi_probe(struct platform_device *pdev) if (ret < 0) return ret; + schedule_work(&sched_amd_hfi_itmt_work); + return 0; } From patchwork Mon Jun 9 20:05:17 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 895479 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D7C3522128C; Mon, 9 Jun 2025 20:05:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749499549; cv=none; b=I6YxxHJb9mPGpKgicy/DFU8xbFFmjwI02qQYizpEXOm8aHbVHMqjb7U/YGXLT/N5TVSeiZnHy0C5BvqVRbN9ynPw2RIjMoxEdfCfr6S8+PZEwAxZEVHmUBhcqrqlM4xX0OtsvKscWuCkFMWb0wdhsUPCjvVcRL7+4kuouvfJwHY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749499549; c=relaxed/simple; bh=98IFVg/2xavMwcAK1kftPNwdCjBQz1GB//A4WKY7EPU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=JDTXAQyx3udE1sb3MJ2WpsjViAOIBo8yBr8jrH3taQVAYM30pQopEovxw1RWXbaIdmqOxWNyYFyz/ZOkVq+h98wGLOzKIKNArSlmRxfjh2W4pQszUCccEom04YtxrPsbbahwbIDl+/zL807uZnScxxOCnVn7MzYkdFRFUaAoySM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=hNoOtvB3; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="hNoOtvB3" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 295CCC4CEF0; Mon, 9 Jun 2025 20:05:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749499549; bh=98IFVg/2xavMwcAK1kftPNwdCjBQz1GB//A4WKY7EPU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hNoOtvB3EVe330aRisayDJKGm2M8xd5X0cMlaHa/rodUM4+BNSA8pPlWc48YUrQZf yjwB89qJdg8ML4xmCNR9aLpgxAJuz02HwKG0CyfpV6DLgLo830SuySHg/mUoNHjtnk 1E5tf5vMV2ZzOCUZTTsJwXc7/L1J/EczhkWagDbnwS8krX/NvGD/r1b+zvAohlXnAu pGEw8AC6lUA2mQAa8b9oxfsNpnezklUlr6TWMtiGToTTUMv8KtkKttjW2Mg08govoj EmE1/ihZJY9tvy1127h0/URRhOSrQMVee/TkfV5SCplOSApVUw9EFro/IqBP59JmNo LvoquiBuUtxPA== From: Mario Limonciello To: =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: Mario Limonciello , Perry Yuan , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), "H . Peter Anvin" , Jonathan Corbet , Huang Rui , "Gautham R . Shenoy" , "Rafael J . Wysocki" , Viresh Kumar , platform-driver-x86@vger.kernel.org (open list:AMD HETERO CORE HARDWARE FEEDBACK DRIVER), linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-pm@vger.kernel.org (open list:AMD PSTATE DRIVER) Subject: [PATCH v11 12/13] platform/x86/amd: hfi: Add debugfs support Date: Mon, 9 Jun 2025 15:05:17 -0500 Message-ID: <20250609200518.3616080-13-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250609200518.3616080-1-superm1@kernel.org> References: <20250609200518.3616080-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mario Limonciello Add a dump of the class and capabilities table to debugfs to assist with debugging scheduler issues. Reviewed-by: Gautham R. Shenoy Signed-off-by: Mario Limonciello --- v9: * signed->unsigned v8: * s,for_each_present_cpu,for_each_possible_cpu, v3: * Move idx to earlier line --- drivers/platform/x86/amd/hfi/hfi.c | 35 ++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/platform/x86/amd/hfi/hfi.c b/drivers/platform/x86/amd/hfi/hfi.c index ef38bc367eecc..17df96d47de88 100644 --- a/drivers/platform/x86/amd/hfi/hfi.c +++ b/drivers/platform/x86/amd/hfi/hfi.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -73,6 +74,8 @@ struct amd_hfi_data { void __iomem *pcc_comm_addr; struct acpi_subtable_header *pcct_entry; struct amd_shmem_info *shmem; + + struct dentry *dbgfs_dir; }; /** @@ -238,6 +241,13 @@ static int amd_hfi_alloc_class_data(struct platform_device *pdev) return 0; } +static void amd_hfi_remove(struct platform_device *pdev) +{ + struct amd_hfi_data *dev = platform_get_drvdata(pdev); + + debugfs_remove_recursive(dev->dbgfs_dir); +} + static int amd_set_hfi_ipcc_score(struct amd_hfi_cpuinfo *hfi_cpuinfo, int cpu) { for (int i = 0; i < hfi_cpuinfo->nr_class; i++) @@ -393,6 +403,26 @@ static int amd_hfi_metadata_parser(struct platform_device *pdev, return ret; } +static int class_capabilities_show(struct seq_file *s, void *unused) +{ + u32 cpu, idx; + + seq_puts(s, "CPU #\tWLC\tPerf\tEff\n"); + for_each_possible_cpu(cpu) { + struct amd_hfi_cpuinfo *hfi_cpuinfo = per_cpu_ptr(&amd_hfi_cpuinfo, cpu); + + seq_printf(s, "%d", cpu); + for (idx = 0; idx < hfi_cpuinfo->nr_class; idx++) { + seq_printf(s, "\t%u\t%u\t%u\n", idx, + hfi_cpuinfo->amd_hfi_classes[idx].perf, + hfi_cpuinfo->amd_hfi_classes[idx].eff); + } + } + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(class_capabilities); + static int amd_hfi_pm_resume(struct device *dev) { int ret, cpu; @@ -469,6 +499,10 @@ static int amd_hfi_probe(struct platform_device *pdev) schedule_work(&sched_amd_hfi_itmt_work); + amd_hfi_data->dbgfs_dir = debugfs_create_dir("amd_hfi", arch_debugfs_dir); + debugfs_create_file("class_capabilities", 0644, amd_hfi_data->dbgfs_dir, pdev, + &class_capabilities_fops); + return 0; } @@ -480,6 +514,7 @@ static struct platform_driver amd_hfi_driver = { .acpi_match_table = ACPI_PTR(amd_hfi_platform_match), }, .probe = amd_hfi_probe, + .remove = amd_hfi_remove, }; static int __init amd_hfi_init(void) From patchwork Mon Jun 9 20:05:18 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 895061 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1AC89228C9D; Mon, 9 Jun 2025 20:05:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749499552; cv=none; b=hWXJfJjs6uHl+YWC78TcmEYSRR+0X9VnQGu5giJs1n3RytmakPUV0l/A1Uo9p4NIdOomWZazbRX2Enbp1pJxyXB8xD1BHaKCE+4CwvPh3BsahWs9ShIFURpbFX8QYQCUNk1d8nJfjT/bfIZUOydetXnWhA/1j9oacH03F4m38P4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749499552; c=relaxed/simple; bh=ccxi92/CdYcFz5SRXc75fcFWq7DUZRAtA96LadU0vMs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=QUwo/2osB/xjPO/BdEczGFn5pEo0s6tT0SvbWrjWi/9h1obKmkrwqDuyYgdtBg80o06Je++8Tx0OpXOEkjcyfx5rKep4fuq1b8gEqZns8jt10FjsTVzu8TYoopW186FmibKC9UUhI0ailtk75svBojiuJIplqHCY8CODWmZ/KIs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=RU1diagR; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="RU1diagR" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 01DDFC4CEF2; Mon, 9 Jun 2025 20:05:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749499551; bh=ccxi92/CdYcFz5SRXc75fcFWq7DUZRAtA96LadU0vMs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RU1diagRRM9N/rrqnuVcJid6v3sYjjs4ARVPWzRA4HNyGSA9Cgdp/u0DOd7zH1Z/j OBxrQfu01B0JycCekT+t4nPn90DvP01hr50A8cE4vYZG0ISAsoF77m7eWVJAYMEswg k6G/RfXhZ5L87Ok9E0E4WuVeVdsDy0u8IyF31pQv7hZqLbHe6HiQPHsb/CprKmPhKe ycsNk0UMmEUKz1V4GMpKr2Q05mIOjrGNbHSkBHVZ8sKb11hhR5Omq74yz9tR/+IUqn v6pRyoRiewXti7ki3Hfx1xSpCPIhX0Hx4zD05kynXs5lXwg4pTrv+KG5cuy/TCCcEy Zye38+GBreYng== From: Mario Limonciello To: =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: Mario Limonciello , Perry Yuan , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), "H . Peter Anvin" , Jonathan Corbet , Huang Rui , "Gautham R . Shenoy" , "Rafael J . Wysocki" , Viresh Kumar , platform-driver-x86@vger.kernel.org (open list:AMD HETERO CORE HARDWARE FEEDBACK DRIVER), linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-pm@vger.kernel.org (open list:AMD PSTATE DRIVER) Subject: [PATCH v11 13/13] x86/itmt: Add debugfs file to show core priorities Date: Mon, 9 Jun 2025 15:05:18 -0500 Message-ID: <20250609200518.3616080-14-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250609200518.3616080-1-superm1@kernel.org> References: <20250609200518.3616080-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mario Limonciello Multiple drivers can report priorities to ITMT. To aid in debugging any issues with the values reported by drivers introduce a debugfs file to read out the values. Signed-off-by: Mario Limonciello --- arch/x86/kernel/itmt.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/x86/kernel/itmt.c b/arch/x86/kernel/itmt.c index 9cea1fc36c18f..243a769fdd97b 100644 --- a/arch/x86/kernel/itmt.c +++ b/arch/x86/kernel/itmt.c @@ -59,6 +59,18 @@ static ssize_t sched_itmt_enabled_write(struct file *filp, return result; } +static int sched_core_priority_show(struct seq_file *s, void *unused) +{ + int cpu; + + seq_puts(s, "CPU #\tPriority\n"); + for_each_possible_cpu(cpu) + seq_printf(s, "%d\t%d\n", cpu, arch_asym_cpu_priority(cpu)); + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(sched_core_priority); + static const struct file_operations dfs_sched_itmt_fops = { .read = debugfs_read_file_bool, .write = sched_itmt_enabled_write, @@ -67,6 +79,7 @@ static const struct file_operations dfs_sched_itmt_fops = { }; static struct dentry *dfs_sched_itmt; +static struct dentry *dfs_sched_core_prio; /** * sched_set_itmt_support() - Indicate platform supports ITMT @@ -102,6 +115,14 @@ int sched_set_itmt_support(void) return -ENOMEM; } + dfs_sched_core_prio = debugfs_create_file("sched_core_priority", 0644, + arch_debugfs_dir, NULL, + &sched_core_priority_fops); + if (IS_ERR_OR_NULL(dfs_sched_core_prio)) { + dfs_sched_core_prio = NULL; + return -ENOMEM; + } + sched_itmt_capable = true; sysctl_sched_itmt_enabled = 1; @@ -133,6 +154,8 @@ void sched_clear_itmt_support(void) debugfs_remove(dfs_sched_itmt); dfs_sched_itmt = NULL; + debugfs_remove(dfs_sched_core_prio); + dfs_sched_core_prio = NULL; if (sysctl_sched_itmt_enabled) { /* disable sched_itmt if we are no longer ITMT capable */