From patchwork Tue Jun 10 08:37:55 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: George Moussalem via B4 Relay X-Patchwork-Id: 895304 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F06441DD9D3; Tue, 10 Jun 2025 08:38:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749544687; cv=none; b=oaELl71hjfVUVFhrorR5904o0qUx9sosO5iyG9IR8zv9RWKp7u2fZrEstSK5QILH9/ev4ONxJNiiaCwln5J8aDxlgHVr4hHtrfnCDVTcROBi+Y9cT25udmgS556/LqA8oJLP0RKiEhbffMDLE8BTHHrZbeEs229bPb889w4isE8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749544687; c=relaxed/simple; bh=8Y2htiPy5meWxzHXQzhyzo1AQtbeIgcyev3Yn6FKh6Q=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=dei5MTZijvsmFLI9sD0tcviSBgVcy/dLI91tVID0l0B5A3CvTxFaan0f1S0K9uemjjuEmO9es8TMq5XFFRL5yphHvNwJQz8LMNyTWtID5w+mODNhDPX6frqxglpB0ekJVMLn/pc8a+uthQYWpOfXM+K8snswMZEe2qBLcpmIJfo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ePZhZU14; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ePZhZU14" Received: by smtp.kernel.org (Postfix) with ESMTPS id 9364BC4CEF2; Tue, 10 Jun 2025 08:38:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749544686; bh=8Y2htiPy5meWxzHXQzhyzo1AQtbeIgcyev3Yn6FKh6Q=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=ePZhZU14Sp+y0japK5Gby46W1qZDL32cvhjiA3hAfq8/KujcPEP0TMMoIAyrFhLWT SmBq5zKXA1Wn0+J4iaAULcA3HXfHHxOApGeRMVOAkRRke4EkbZyrdoS1/CsZRzqhA2 pKnhNvzjpjIQ45PQqy8Bb48AEJruxmrhbFq1RDrVCA6IQv7fiwqCLJdeV7DW8jRmBg ELiLu9llNyTCMxJYAvxqvZ9vqWISpUXpZI9X1XmOmQ3qTWc0IETy/0y0omPQGkde20 nY2X96+2qrfpqC1paMt9cC0QqtbaAOPeiaCtRUeGdcRs6a918XRnZGSq/kEBXk0k2u TjQZysrRUcO8w== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 82A05C61DB2; Tue, 10 Jun 2025 08:38:06 +0000 (UTC) From: George Moussalem via B4 Relay Date: Tue, 10 Jun 2025 12:37:55 +0400 Subject: [PATCH v5 1/5] clk: qcom: gcc-ipq5018: fix GE PHY reset Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250610-ipq5018-ge-phy-v5-1-daa9694bdbd1@outlook.com> References: <20250610-ipq5018-ge-phy-v5-0-daa9694bdbd1@outlook.com> In-Reply-To: <20250610-ipq5018-ge-phy-v5-0-daa9694bdbd1@outlook.com> To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, George Moussalem , Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1749544683; l=1220; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=y65n0Od6u+x9wP3HKotpTyPdgu84le/dyFb7G8W0t/E=; b=FwKHoMxaPysoeaqp1bvm0yyBuOQ2kyrcMP02yVlcHy+ILSyZMWinN2ckZoTJsWATaat4x5sMI /NV40gSj9rjC18x8QfHsmFINGdbBCekMd4Kg7r6tE8J0veib/BBLsda X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem The MISC reset is supposed to trigger a resets across the MDC, DSP, and RX & TX clocks of the IPQ5018 internal GE PHY. So let's set the bitmask of the reset definition accordingly in the GCC as per the downstream driver. Link: https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/commit/00743c3e82fa87cba4460e7a2ba32f473a9ce932 Reviewed-by: Konrad Dybcio Signed-off-by: George Moussalem --- drivers/clk/qcom/gcc-ipq5018.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/qcom/gcc-ipq5018.c b/drivers/clk/qcom/gcc-ipq5018.c index 70f5dcb96700f55da1fb19fc893d22350a7e63bf..6eb86c034fda18c38dcd9726f0903841252381da 100644 --- a/drivers/clk/qcom/gcc-ipq5018.c +++ b/drivers/clk/qcom/gcc-ipq5018.c @@ -3660,7 +3660,7 @@ static const struct qcom_reset_map gcc_ipq5018_resets[] = { [GCC_WCSS_AXI_S_ARES] = { 0x59008, 6 }, [GCC_WCSS_Q6_BCR] = { 0x18004, 0 }, [GCC_WCSSAON_RESET] = { 0x59010, 0}, - [GCC_GEPHY_MISC_ARES] = { 0x56004, 0 }, + [GCC_GEPHY_MISC_ARES] = { 0x56004, .bitmask = GENMASK(3, 0) }, }; static const struct of_device_id gcc_ipq5018_match_table[] = { From patchwork Tue Jun 10 08:37:56 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: George Moussalem via B4 Relay X-Patchwork-Id: 895302 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3AD6527FB35; Tue, 10 Jun 2025 08:38:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749544687; cv=none; b=XvdsrHBtBSkpV0I7GtICxUSCw+UNWZHWHYgxQzflH/s5E0L6BQfAeOeq5Yaqzc2PuqCnaOskmXKsJG80f8/BuEMv7cHIpar9wJcsmUoIvvs2bj7MstN4HUuXtYZp5fs+f7FDzx0lzKlN06a72gorIeZsLC89ZxhiuY9fnjk+mnw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749544687; c=relaxed/simple; bh=w9+uhG8mukFv3LUxt/Camybk60EdgO3KKFcvGpshaz8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=FHv5AsYqM0zl+SYBGWohRhyypwGtDhuosMw7jnRte/JSgb8Bhjn1cmDP3mDmRPy27jsFxLdiuYcCFE+MWX5fngfGX9NeH6Jzp31BOKebiDWiJzj2GI9YtTEJfVs5YeL6qmVemoM5WfYF745u4PzyO4BImNql0EV4KQQo18bBXqk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Q6XOO5JL; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Q6XOO5JL" Received: by smtp.kernel.org (Postfix) with ESMTPS id A21C0C4CEF0; Tue, 10 Jun 2025 08:38:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749544686; bh=w9+uhG8mukFv3LUxt/Camybk60EdgO3KKFcvGpshaz8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Q6XOO5JLgAc5J7fGCjxS636vtasYi3TaxN6Z1oXeWMjw32pEirFdljFUVHY9BjD9J XU2GtiCFIiVuAH8H6BSWYo2IonyRLETqd8aUj9i8yKkeSlh8Mzg8w+EPxA09sEEH3S E9uQ5ufyB76wvMBlNB+8biWEi2XZjRxVb923sOS4bpI5oC5CkvYCbkb60HATvSmLP1 epy2eyf2TXxEm3CF8b0odB2KhzXHN/pLZhLdc97iFKaW18JtlAvXLLPUhpYgalltWz L9/W1beybLTEsc2ih+8HyHhtlDqOW5YZQSiCYtTaKmkBDBhyYkxn20HCXkB7Z2/LaC krlMOvdNZ1Ymg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9249AC5B543; Tue, 10 Jun 2025 08:38:06 +0000 (UTC) From: George Moussalem via B4 Relay Date: Tue, 10 Jun 2025 12:37:56 +0400 Subject: [PATCH v5 2/5] dt-bindings: net: qca,ar803x: Add IPQ5018 Internal GE PHY support Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250610-ipq5018-ge-phy-v5-2-daa9694bdbd1@outlook.com> References: <20250610-ipq5018-ge-phy-v5-0-daa9694bdbd1@outlook.com> In-Reply-To: <20250610-ipq5018-ge-phy-v5-0-daa9694bdbd1@outlook.com> To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, George Moussalem X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1749544683; l=2960; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=MSreklj9uhNRgsWlk9VY//Ue1TwD7d3ZsG5R6DaH9lo=; b=9IY8hBnqBK66IfR9ksjn9U/xrjA039Q0Su+/dBpWDHfG6NYfIGjc6/C+NfvBtBumkrpq7/rBm GofmxHJ+vHsDXR51n31vDlKGIGWv7KzOwUx+UvR9osDICyLpngYcYvk X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem Document the IPQ5018 Internal Gigabit Ethernet PHY found in the IPQ5018 SoC. Its output pins provide an MDI interface to either an external switch in a PHY to PHY link scenario or is directly attached to an RJ45 connector. The PHY supports 10/100/1000 mbps link modes, CDT, auto-negotiation and 802.3az EEE. For operation, the LDO controller found in the IPQ5018 SoC for which there is provision in the mdio-4019 driver. Two common archictures across IPQ5018 boards are: 1. IPQ5018 PHY --> MDI --> RJ45 connector 2. IPQ5018 PHY --> MDI --> External PHY In a phy to phy architecture, the DAC needs to be configured to accommodate for the short cable length. As such, add an optional boolean property so the driver sets preset DAC register values accordingly. Signed-off-by: George Moussalem --- .../devicetree/bindings/net/qca,ar803x.yaml | 43 ++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/Documentation/devicetree/bindings/net/qca,ar803x.yaml b/Documentation/devicetree/bindings/net/qca,ar803x.yaml index 3acd09f0da863137f8a05e435a1fd28a536c2acd..7ae5110e7aa2cc97498a0ec46b67d8ed8440f3f2 100644 --- a/Documentation/devicetree/bindings/net/qca,ar803x.yaml +++ b/Documentation/devicetree/bindings/net/qca,ar803x.yaml @@ -16,8 +16,37 @@ description: | allOf: - $ref: ethernet-phy.yaml# + - if: + properties: + compatible: + contains: + enum: + - ethernet-phy-id004d.d0c0 + + then: + properties: + reg: + const: 7 # This PHY is always at MDIO address 7 in the IPQ5018 SoC + + resets: + items: + - description: + GE PHY MISC reset which triggers a reset across MDC, DSP, RX, and TX lines. + + qcom,dac-preset-short-cable: + description: + Set if this phy is connected to another phy to adjust the values for + MDAC and EDAC to adjust amplitude, bias current settings, and error + detection and correction algorithm to accommodate for short cable length. + If not set, DAC values are not modified and it is assumed the MDI output pins + of this PHY are directly connected to an RJ45 connector. + type: boolean properties: + compatible: + enum: + - ethernet-phy-id004d.d0c0 + qca,clk-out-frequency: description: Clock output frequency in Hertz. $ref: /schemas/types.yaml#/definitions/uint32 @@ -132,3 +161,17 @@ examples: }; }; }; + - | + #include + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ge_phy: ethernet-phy@7 { + compatible = "ethernet-phy-id004d.d0c0"; + reg = <7>; + + resets = <&gcc GCC_GEPHY_MISC_ARES>; + }; + }; From patchwork Tue Jun 10 08:37:57 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: George Moussalem via B4 Relay X-Patchwork-Id: 896778 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 397FB27FB27; Tue, 10 Jun 2025 08:38:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749544687; cv=none; b=MYhGcwswZsP7fHNce9aJ7JGaSOrQ85n6I/zwX4H5mdY/CzTqWykPDT8UiZTJUimMNmIgYguRdC1fMgFJl3zNOBasI+9dMPegQIaxvdCDdEj+sa/SBlKDrHxBL46D7zwG60GreRKSLLp/EtRMqWfwV8FJHSz0XQ4/x/Vpd9rrB8g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749544687; c=relaxed/simple; bh=ofG/4sPfTw7Uz3dJ8b8M+etDIlM9GkNHvfZnVO1fUMo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=aSc+WGGFo45/KIKRkMbY++Ofh7wqSLMPPewRbwiCZA5SMyF/KNjUJAsObwkIQWCSWpk7/gT5ZOCeskv/N04t/5yd2I3RN+n4JYXjA9L3dvTrcf4THgRaoRpPZLFo4b2T9WccQEuV8TRkmZRYa4COOe70tsPa3ABYf1hytG3rSyY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=HjFXSAq0; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="HjFXSAq0" Received: by smtp.kernel.org (Postfix) with ESMTPS id B12C4C4CEF3; Tue, 10 Jun 2025 08:38:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749544686; bh=ofG/4sPfTw7Uz3dJ8b8M+etDIlM9GkNHvfZnVO1fUMo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=HjFXSAq0ba50gT/ZPB6vk5SuJ/ITi/fP6LIpHWoD5ziN7hBlVmPkL2FNvFlg074bG JQTb+PciacUfyO5lVG1nok2x0NcpKLXsY6p9PqFwKXL6EGGx/GL4bXOe0KEIvnFPeW 2HT6CUNg8pez7vYs6F1Oin5mJcJwz1/7FvGh1d65U2AmH5ZM6BpzasKVPYFR7MjG3R U1i8mrWbSJZeeg9JomTk3QdR3lYxDtuXnLrR7VGZ5TYIDxgbxnrQqeyNm8AaEXpaLe uZLsxVOF+qLanS8qv6mXZANCzL+DlYe0ItiKXPHDAsAxJvIlaMTY2qOnH//hy5cCj+ 53SCEpfFuXR6w== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id A22C4C677C4; Tue, 10 Jun 2025 08:38:06 +0000 (UTC) From: George Moussalem via B4 Relay Date: Tue, 10 Jun 2025 12:37:57 +0400 Subject: [PATCH v5 3/5] net: phy: qcom: at803x: Add Qualcomm IPQ5018 Internal PHY support Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250610-ipq5018-ge-phy-v5-3-daa9694bdbd1@outlook.com> References: <20250610-ipq5018-ge-phy-v5-0-daa9694bdbd1@outlook.com> In-Reply-To: <20250610-ipq5018-ge-phy-v5-0-daa9694bdbd1@outlook.com> To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, George Moussalem X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1749544683; l=9449; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=LLaUOkML98/X7EbLgdB3L5q7J3Kc0PDmLb1AVTCEvYw=; b=qnIUHjd0MbgejXmL9weiPJruJu6qEvhMQGIWwNd9CIuPcHrk2gqQi6epnbbn7HWOj5bbeS51j WwtEfH8CX9jA/wGKIGLLshmpP/ECruH3vIuHpNBUetej1IB0tVapEEp X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem The IPQ5018 SoC contains a single internal Gigabit Ethernet PHY which provides an MDI interface directly to an RJ45 connector or an external switch over a PHY to PHY link. The PHY supports 10BASE-T/100BASE-TX/1000BASE-T link modes in SGMII interface mode, CDT, auto-negotiation and 802.3az EEE. Let's add support for this PHY in the at803x driver as it falls within the Qualcomm Atheros OUI. Signed-off-by: George Moussalem --- drivers/net/phy/qcom/Kconfig | 2 +- drivers/net/phy/qcom/at803x.c | 167 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 168 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/qcom/Kconfig b/drivers/net/phy/qcom/Kconfig index 570626cc8e14d3e6615f74a6377f0f7c9f723e89..84239e08a8dfa466b0a7b2a5ec724a168b692cd2 100644 --- a/drivers/net/phy/qcom/Kconfig +++ b/drivers/net/phy/qcom/Kconfig @@ -7,7 +7,7 @@ config AT803X_PHY select QCOM_NET_PHYLIB depends on REGULATOR help - Currently supports the AR8030, AR8031, AR8033, AR8035 model + Currently supports the AR8030, AR8031, AR8033, AR8035, IPQ5018 model config QCA83XX_PHY tristate "Qualcomm Atheros QCA833x PHYs" diff --git a/drivers/net/phy/qcom/at803x.c b/drivers/net/phy/qcom/at803x.c index 26350b962890b0321153d74758b13d817407d094..43e604171828ce35d5950e02b1d08ee3e4523fdc 100644 --- a/drivers/net/phy/qcom/at803x.c +++ b/drivers/net/phy/qcom/at803x.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include @@ -96,6 +97,8 @@ #define ATH8035_PHY_ID 0x004dd072 #define AT8030_PHY_ID_MASK 0xffffffef +#define IPQ5018_PHY_ID 0x004dd0c0 + #define QCA9561_PHY_ID 0x004dd042 #define AT803X_PAGE_FIBER 0 @@ -108,6 +111,48 @@ /* disable hibernation mode */ #define AT803X_DISABLE_HIBERNATION_MODE BIT(2) +#define IPQ5018_PHY_FIFO_CONTROL 0x19 +#define IPQ5018_PHY_FIFO_RESET GENMASK(1, 0) + +#define IPQ5018_PHY_DEBUG_EDAC 0x4380 +#define IPQ5018_PHY_MMD1_MDAC 0x8100 +#define IPQ5018_PHY_DAC_MASK GENMASK(15, 8) + +/* MDAC and EDAC values for short cable length */ +#define IPQ5018_PHY_DEBUG_EDAC_VAL 0x10 +#define IPQ5018_PHY_MMD1_MDAC_VAL 0x10 + +#define IPQ5018_PHY_MMD1_MSE_THRESH1 0x1000 +#define IPQ5018_PHY_MMD1_MSE_THRESH2 0x1001 +#define IPQ5018_PHY_PCS_EEE_TX_TIMER 0x8008 +#define IPQ5018_PHY_PCS_EEE_RX_TIMER 0x8009 +#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL3 0x8074 +#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL4 0x8075 +#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL5 0x8076 +#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL6 0x8077 +#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL7 0x8078 +#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL9 0x807a +#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL13 0x807e +#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL14 0x807f + +#define IPQ5018_PHY_MMD1_MSE_THRESH1_VAL 0xf1 +#define IPQ5018_PHY_MMD1_MSE_THRESH2_VAL 0x1f6 +#define IPQ5018_PHY_PCS_EEE_TX_TIMER_VAL 0x7880 +#define IPQ5018_PHY_PCS_EEE_RX_TIMER_VAL 0xc8 +#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL3_VAL 0xc040 +#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL4_VAL 0xa060 +#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL5_VAL 0xc040 +#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL6_VAL 0xa060 +#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL7_VAL 0xc24c +#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL9_VAL 0xc060 +#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL13_VAL 0xb060 +#define IPQ5018_PHY_PCS_NEAR_ECHO_THRESH_VAL 0x90b0 + +#define IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE 0x1 +#define IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_MASK GENMASK(7, 4) +#define IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_DEFAULT 0x50 +#define IPQ5018_PHY_DEBUG_ANA_DAC_FILTER 0xa080 + MODULE_DESCRIPTION("Qualcomm Atheros AR803x PHY driver"); MODULE_AUTHOR("Matus Ujhelyi"); MODULE_LICENSE("GPL"); @@ -133,6 +178,11 @@ struct at803x_context { u16 led_control; }; +struct ipq5018_priv { + struct reset_control *rst; + bool set_short_cable_dac; +}; + static int at803x_write_page(struct phy_device *phydev, int page) { int mask; @@ -987,6 +1037,109 @@ static int at8035_probe(struct phy_device *phydev) return at8035_parse_dt(phydev); } +static int ipq5018_cable_test_start(struct phy_device *phydev) +{ + phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL3, + IPQ5018_PHY_PCS_CDT_THRESH_CTRL3_VAL); + phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL4, + IPQ5018_PHY_PCS_CDT_THRESH_CTRL4_VAL); + phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL5, + IPQ5018_PHY_PCS_CDT_THRESH_CTRL5_VAL); + phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL6, + IPQ5018_PHY_PCS_CDT_THRESH_CTRL6_VAL); + phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL7, + IPQ5018_PHY_PCS_CDT_THRESH_CTRL7_VAL); + phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL9, + IPQ5018_PHY_PCS_CDT_THRESH_CTRL9_VAL); + phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL13, + IPQ5018_PHY_PCS_CDT_THRESH_CTRL13_VAL); + phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL3, + IPQ5018_PHY_PCS_NEAR_ECHO_THRESH_VAL); + + /* we do all the (time consuming) work later */ + return 0; +} + +static int ipq5018_config_init(struct phy_device *phydev) +{ + struct ipq5018_priv *priv = phydev->priv; + u16 val; + + /* + * set LDO efuse: first temporarily store ANA_DAC_FILTER value from + * debug register as it will be reset once the ANA_LDO_EFUSE register + * is written to + */ + val = at803x_debug_reg_read(phydev, IPQ5018_PHY_DEBUG_ANA_DAC_FILTER); + at803x_debug_reg_mask(phydev, IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE, + IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_MASK, + IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_DEFAULT); + at803x_debug_reg_write(phydev, IPQ5018_PHY_DEBUG_ANA_DAC_FILTER, val); + + /* set 8023AZ EEE TX and RX timer values */ + phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_EEE_TX_TIMER, + IPQ5018_PHY_PCS_EEE_TX_TIMER_VAL); + phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_EEE_RX_TIMER, + IPQ5018_PHY_PCS_EEE_RX_TIMER_VAL); + + /* set MSE threshold values */ + phy_write_mmd(phydev, MDIO_MMD_PMAPMD, IPQ5018_PHY_MMD1_MSE_THRESH1, + IPQ5018_PHY_MMD1_MSE_THRESH1_VAL); + phy_write_mmd(phydev, MDIO_MMD_PMAPMD, IPQ5018_PHY_MMD1_MSE_THRESH2, + IPQ5018_PHY_MMD1_MSE_THRESH2_VAL); + + /* PHY DAC values are optional and only set in a PHY to PHY link architecture */ + if (priv->set_short_cable_dac) { + /* setting MDAC (Multi-level Digital-to-Analog Converter) in MMD1 */ + phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, IPQ5018_PHY_MMD1_MDAC, + IPQ5018_PHY_DAC_MASK, IPQ5018_PHY_MMD1_MDAC_VAL); + + /* setting EDAC (Error-detection and Correction) in debug register */ + at803x_debug_reg_mask(phydev, IPQ5018_PHY_DEBUG_EDAC, + IPQ5018_PHY_DAC_MASK, IPQ5018_PHY_DEBUG_EDAC_VAL); + } + + return 0; +} + +static void ipq5018_link_change_notify(struct phy_device *phydev) +{ + /* + * Reset the FIFO buffer upon link disconnects to clear any residual data + * which may cause issues with the FIFO which it cannot recover from. + */ + mdiobus_modify_changed(phydev->mdio.bus, phydev->mdio.addr, + IPQ5018_PHY_FIFO_CONTROL, IPQ5018_PHY_FIFO_RESET, + phydev->link ? IPQ5018_PHY_FIFO_RESET : 0); +} + +static int ipq5018_probe(struct phy_device *phydev) +{ + struct device *dev = &phydev->mdio.dev; + struct ipq5018_priv *priv; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->set_short_cable_dac = of_property_read_bool(dev->of_node, + "qcom,dac-preset-short-cable"); + + priv->rst = devm_reset_control_array_get_exclusive(dev); + if (IS_ERR(priv->rst)) + return dev_err_probe(dev, PTR_ERR(priv->rst), + "failed to acquire reset\n"); + + ret = reset_control_reset(priv->rst); + if (ret) + return dev_err_probe(dev, ret, "failed to reset\n"); + + phydev->priv = priv; + + return 0; +} + static struct phy_driver at803x_driver[] = { { /* Qualcomm Atheros AR8035 */ @@ -1078,6 +1231,19 @@ static struct phy_driver at803x_driver[] = { .read_status = at803x_read_status, .soft_reset = genphy_soft_reset, .config_aneg = at803x_config_aneg, +}, { + PHY_ID_MATCH_EXACT(IPQ5018_PHY_ID), + .name = "Qualcomm Atheros IPQ5018 internal PHY", + .flags = PHY_IS_INTERNAL | PHY_POLL_CABLE_TEST, + .probe = ipq5018_probe, + .config_init = ipq5018_config_init, + .link_change_notify = ipq5018_link_change_notify, + .read_status = at803x_read_status, + .config_intr = at803x_config_intr, + .handle_interrupt = at803x_handle_interrupt, + .cable_test_start = ipq5018_cable_test_start, + .cable_test_get_status = qca808x_cable_test_get_status, + .soft_reset = genphy_soft_reset, }, { /* Qualcomm Atheros QCA9561 */ PHY_ID_MATCH_EXACT(QCA9561_PHY_ID), @@ -1104,6 +1270,7 @@ static const struct mdio_device_id __maybe_unused atheros_tbl[] = { { PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) }, { PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) }, { PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) }, + { PHY_ID_MATCH_EXACT(IPQ5018_PHY_ID) }, { PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) }, { } }; From patchwork Tue Jun 10 08:37:58 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: George Moussalem via B4 Relay X-Patchwork-Id: 895303 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3827C27F161; Tue, 10 Jun 2025 08:38:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749544687; cv=none; b=N5F3YGEX/kcIWlYetetFyooO9Q2QXGDsPSaxs1TFT6pk4VEyLlD7+fr3egSSeZK5fcBOBS3VAhdtS6imRcXa0fkXAUqE3kW+O5pFvF5GvgdN1ygxagOOMrx2weK31Z5DGr5VT9KrmklzMQebvQToaY3cUIjnc2kaw+QdNKSvPOQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749544687; c=relaxed/simple; bh=WzM5y2OoQkwywYk7ze1eYenAU+huZ1+9rx3teZ27zKM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=AeM2x6naDnHA4/iitIwJH9MaqFlqG9N9JHMaOZP2bWFupGSlARqhhLmD59dSHqm4sK2d9zutnMuKGAmRn0brIqkgGklYkpj2F/U65cVaYeEpqi7YfjHIyz4XwCbVKkbqEBDqjTjThRAUkMQvI5AVkwlDn6kuFVcD46CTWW/T4Xo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=XjoAbiSm; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="XjoAbiSm" Received: by smtp.kernel.org (Postfix) with ESMTPS id B975CC4CEF8; Tue, 10 Jun 2025 08:38:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749544686; bh=WzM5y2OoQkwywYk7ze1eYenAU+huZ1+9rx3teZ27zKM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=XjoAbiSmg1Po7tpwTGAmWWtYTbiZ0LXLYE1v/BL3GqwqJmZ9KsjXUOmRb79WY7Byc QJv6vjNMQBGzp6R3FCyrZkQIjjTigQ5kf5W/FmAoY8w4a2oNuZtetTE7kt0ZmJdNvJ 8eVwqhfil2j3gklSOVDJj7+Di3LwkGEEaFBsv12rUL76LDhF35tZsiO7C5m6K8Dmjr SlSWrmMZ5uHdZhUJdku7U9qol75pL5nFncpfRItKd4NUehTEZKalH3NhCGWG3ht6iZ KsQVsCCGWpqLhUu87P5wnDqSRz7LcyJeJdkHnnlt2rLmIJHvIsr62gzWI7VJoc3qsL veOzGQtctxOfA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1350C5B552; Tue, 10 Jun 2025 08:38:06 +0000 (UTC) From: George Moussalem via B4 Relay Date: Tue, 10 Jun 2025 12:37:58 +0400 Subject: [PATCH v5 4/5] arm64: dts: qcom: ipq5018: Add MDIO buses Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250610-ipq5018-ge-phy-v5-4-daa9694bdbd1@outlook.com> References: <20250610-ipq5018-ge-phy-v5-0-daa9694bdbd1@outlook.com> In-Reply-To: <20250610-ipq5018-ge-phy-v5-0-daa9694bdbd1@outlook.com> To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, George Moussalem , Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1749544683; l=1519; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=jA4BQsaw0tlEf36IZrwvZtR6C1am2pcwyAdrevsj4Hk=; b=hSdTUjtHpj86cr4Uswl07p/eGEBxIRuMBAke+RvCCCJbKkJroLYukxiZGqC+81GFvdhl/6/cy QmPPrAlvwkPCk1J1YNDgekzSGJVfB+izSE0U42LnirA4BF3JajsjhEj X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem IPQ5018 contains two mdio buses of which one bus is used to control the SoC's internal GE PHY, while the other bus is connected to external PHYs or switches. There's already support for IPQ5018 in the mdio-ipq4019 driver, so let's simply add the mdio nodes for them. Reviewed-by: Konrad Dybcio Signed-off-by: George Moussalem --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi index 130360014c5e14c778e348d37e601f60325b0b14..03ebc3e305b267c98a034c41ce47a39269afce75 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -182,6 +182,30 @@ pcie0_phy: phy@86000 { status = "disabled"; }; + mdio0: mdio@88000 { + compatible = "qcom,ipq5018-mdio"; + reg = <0x00088000 0x64>; + #address-cells = <1>; + #size-cells = <0>; + + clocks = <&gcc GCC_MDIO0_AHB_CLK>; + clock-names = "gcc_mdio_ahb_clk"; + + status = "disabled"; + }; + + mdio1: mdio@90000 { + compatible = "qcom,ipq5018-mdio"; + reg = <0x00090000 0x64>; + #address-cells = <1>; + #size-cells = <0>; + + clocks = <&gcc GCC_MDIO1_AHB_CLK>; + clock-names = "gcc_mdio_ahb_clk"; + + status = "disabled"; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,ipq5018-tlmm"; reg = <0x01000000 0x300000>; From patchwork Tue Jun 10 08:37:59 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: George Moussalem via B4 Relay X-Patchwork-Id: 896777 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7D3A328134E; Tue, 10 Jun 2025 08:38:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749544687; cv=none; b=k8SiALqhRWRdQsvPOpk6TTeEq6J6pj/9TlMZvxBbDZXUB2G10BT/FQsSmPBG2yVTPLYswcUXxs3AlrrIv0GuYvp+CHeOIHQ7T8k2TG0yl0s+ybqmyQAwwkW8dNSuxOisVBC+0Vnl5adA2JcDIzT32wzollH1KyHwiCNDtQu2FIc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749544687; c=relaxed/simple; bh=YW0aYGk44OBGXMXwnXBPhhKQgB+lh/nINEBWmVaTupA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Y4GXQHOSGznNYnrZdTuEfZq9xiVngpzfA+W8aPXq33d6YXgI6KgPspie3qyh7q5emhjXoPczzBjzvLti7QjQUs3z3YsjxTvugkSIATj9/U1Opb3DLs/3liGsiJGn95llhD4ijDhXEna/6UGQISgtnQ9+ECw8s4N2pZw59OtcwKY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=SFIXccSH; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="SFIXccSH" Received: by smtp.kernel.org (Postfix) with ESMTPS id CC05AC4CEF5; Tue, 10 Jun 2025 08:38:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749544686; bh=YW0aYGk44OBGXMXwnXBPhhKQgB+lh/nINEBWmVaTupA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=SFIXccSH7RpfZmy9fQXhsOmQBdyuLthpHn6jExJY9Y1yEoAH2urzKGdKmfBJYuCWD tu9u9xA13wbutNtOZeMkLEuQGnv4tJV/66W/xrh4kKsf83hpdJHkeyvh7GHj3Mr1Zx JbnOwOvrQIUxiZ+CCmsXG6u+YC7WvhPiZngCOU3sbJ5bfxHyguGksgRdSlXEIsmvxs otnW4wl5s6x8TgIAx8IS2FIdrs5ozlBAqRbMPgfKeg/Ajy02Z7iiH8OxsPwdEomaoQ /FujURbqWrgMOgAbi+92jay6DbWEuFuwaVtsUN9LY5YrTWBf1YouiOKkQGi63ZZY+H /b19VGlmAX2+w== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0CDEC71132; Tue, 10 Jun 2025 08:38:06 +0000 (UTC) From: George Moussalem via B4 Relay Date: Tue, 10 Jun 2025 12:37:59 +0400 Subject: [PATCH v5 5/5] arm64: dts: qcom: ipq5018: Add GE PHY to internal mdio bus Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250610-ipq5018-ge-phy-v5-5-daa9694bdbd1@outlook.com> References: <20250610-ipq5018-ge-phy-v5-0-daa9694bdbd1@outlook.com> In-Reply-To: <20250610-ipq5018-ge-phy-v5-0-daa9694bdbd1@outlook.com> To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, George Moussalem , Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1749544683; l=2285; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=hFpy0osU/0n+A52muRC0D3Drst6JCZAX5hmtJZDrLks=; b=un9tciC84pDmPnVnCf6Uie9NGEQ6Hd5vibaYUdIvTGuG8+/rnLmHQVbnV/UwXhl3YMHXPCqml K7G9SC7SM27BTOaRCX1l9VJrPxs4PqCQ1UOA5HOIdXpOK582Tm1ZjcU X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem The IPQ5018 SoC contains an internal GE PHY, always at phy address 7. As such, let's add the GE PHY node to the SoC dtsi. The LDO controller found in the SoC must be enabled to provide constant low voltages to the PHY. The mdio-ipq4019 driver already has support for this, so adding the appropriate TCSR register offset. In addition, the GE PHY outputs both the RX and TX clocks to the GCC which gate controls them and routes them back to the PHY itself. So let's create two DT fixed clocks and register them in the GCC node. Reviewed-by: Konrad Dybcio Signed-off-by: George Moussalem --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 26 +++++++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi index 03ebc3e305b267c98a034c41ce47a39269afce75..d47ad62b01991fafa51e7082bd1fcf6670d9b0bc 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -16,6 +16,18 @@ / { #size-cells = <2>; clocks { + gephy_rx_clk: gephy-rx-clk { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + #clock-cells = <0>; + }; + + gephy_tx_clk: gephy-tx-clk { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + #clock-cells = <0>; + }; + sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -184,7 +196,8 @@ pcie0_phy: phy@86000 { mdio0: mdio@88000 { compatible = "qcom,ipq5018-mdio"; - reg = <0x00088000 0x64>; + reg = <0x00088000 0x64>, + <0x019475c4 0x4>; #address-cells = <1>; #size-cells = <0>; @@ -192,6 +205,13 @@ mdio0: mdio@88000 { clock-names = "gcc_mdio_ahb_clk"; status = "disabled"; + + ge_phy: ethernet-phy@7 { + compatible = "ethernet-phy-id004d.d0c0"; + reg = <7>; + + resets = <&gcc GCC_GEPHY_MISC_ARES>; + }; }; mdio1: mdio@90000 { @@ -232,8 +252,8 @@ gcc: clock-controller@1800000 { <&pcie0_phy>, <&pcie1_phy>, <0>, - <0>, - <0>, + <&gephy_rx_clk>, + <&gephy_tx_clk>, <0>, <0>; #clock-cells = <1>;