From patchwork Wed Jun 11 16:15:33 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Nuno_S=C3=A1_via_B4_Relay?= X-Patchwork-Id: 895741 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 13C4D15A8; Wed, 11 Jun 2025 16:15:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749658528; cv=none; b=RvaRBdnwxc1wGy+/RCBNxxCoCH6nejJoHJLiFh6lE4Notl5X7kmVyOV1WwaP5fzyzS8FiqLKC4TROd0zUOv21NC0Gnk6wSyk0FOwvGFVzBz3y+TK5JdH5bOMW9HAQTdV0duDAsJke604zYIlzChfolCP1S0Y8uN00OQce1J9Axs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749658528; c=relaxed/simple; bh=l8GHgN4bthv1D4rTi1VIlfnTVIkCL8BlPGbaZoVw+8Y=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=tpCzkNBiNKmixGA3fCGClSc58p1Hwyk/ahs3Ry6p+YZ7wEpwCYrHvGQXFnBVfyZTAni2nb+n1B8DnrCGKlnX7fR9wQP7ueHxxqLjBKktuXd6vEOJ03olpEQKVkTjVQIHgTrZ/B1mQjnaErWHjyRbkszQ6W3LCZ4MIjBrxdbBOZQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Kq9RwuKj; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Kq9RwuKj" Received: by smtp.kernel.org (Postfix) with ESMTPS id B304DC4CEF4; Wed, 11 Jun 2025 16:15:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749658527; bh=l8GHgN4bthv1D4rTi1VIlfnTVIkCL8BlPGbaZoVw+8Y=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Kq9RwuKjdYYEuDWIhN/AdP8+WZCcHeG+mXLGypzgVfsOPH7869YhUikdVuaA6phms h5Zyc5PAH0VzYc9OzDUQfzdREUFeTeU9Pb8UAgFTlptsxMX5Fh5ZfrweNFxOKZ7wl+ k3mECkA+V7rk3e8HhczdmZXoLo7Rt8OjqYnbdgJiErtYm6kpC4NkWsx/HiGg9yebZV 1ww1UqbO2PEnuXKRYdY/+Duf6AE9HW3JauF3LJ69tlMjeSUgn4XM/g8o+co3C1e5Ij CNcRQfwkv6RHJ8kCkWEgUMrydFxvXhF+wucdDzKbA3CGPx1EveFOFESA+TxlpoDP40 dBH2W8zZf3mLQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 866C3C71136; Wed, 11 Jun 2025 16:15:27 +0000 (UTC) From: =?utf-8?q?Nuno_S=C3=A1_via_B4_Relay?= Date: Wed, 11 Jun 2025 17:15:33 +0100 Subject: [PATCH v7 1/7] clk: clk-axi-clkgen: fix fpfd_max frequency for zynq Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250611-dev-axi-clkgen-limits-v7-1-3e7ff89dc366@analog.com> References: <20250611-dev-axi-clkgen-limits-v7-0-3e7ff89dc366@analog.com> In-Reply-To: <20250611-dev-axi-clkgen-limits-v7-0-3e7ff89dc366@analog.com> To: linux-clk@vger.kernel.org, linux-fpga@vger.kernel.org, dmaengine@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-iio@vger.kernel.org, linux-pwm@vger.kernel.org, linux-spi@vger.kernel.org Cc: Stephen Boyd , Michael Turquette , Moritz Fischer , Wu Hao , Xu Yilun , Tom Rix , Vinod Koul , Jean Delvare , Guenter Roeck , Michael Hennerich , Jonathan Cameron , Trevor Gamblin , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , David Lechner , Mark Brown , Mike Turquette X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1749658534; l=1051; i=nuno.sa@analog.com; s=20231116; h=from:subject:message-id; bh=JzRJBVV4hmqfyR9B0h2hyDBM9zs6OBzwS0DPME3ZrAA=; b=YtNqWyeeeafIzxivB6S+327Shfi2k5Dif3dTAEaaJapROPgYxtF7XMkAO3kEThUsewEuaz4BT e9ECWREFZHCD5YdYuvQ2BTbrj/hUdN0QwEFyQQw/8QlA3v1Tnxq3AB0 X-Developer-Key: i=nuno.sa@analog.com; a=ed25519; pk=3NQwYA013OUYZsmDFBf8rmyyr5iQlxV/9H4/Df83o1E= X-Endpoint-Received: by B4 Relay for nuno.sa@analog.com/20231116 with auth_id=100 X-Original-From: =?utf-8?q?Nuno_S=C3=A1?= Reply-To: nuno.sa@analog.com From: Nuno Sá The fpfd_max frequency should be set to 450 MHz instead of 300 MHz. Well, it actually depends on the platform speed grade but we are being conservative for ultrascale so let's be consistent. In a following change we will set these limits at runtime. Fixes: 0e646c52cf0e ("clk: Add axi-clkgen driver") Reviewed-by: David Lechner Signed-off-by: Nuno Sá --- drivers/clk/clk-axi-clkgen.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/clk-axi-clkgen.c b/drivers/clk/clk-axi-clkgen.c index 934e53a96dddac8ed61dd109cfc188f3a2a0539a..00bf799964c61a3efc042b0f3a9ec3bc8625c9da 100644 --- a/drivers/clk/clk-axi-clkgen.c +++ b/drivers/clk/clk-axi-clkgen.c @@ -118,7 +118,7 @@ static const struct axi_clkgen_limits axi_clkgen_zynqmp_default_limits = { static const struct axi_clkgen_limits axi_clkgen_zynq_default_limits = { .fpfd_min = 10000, - .fpfd_max = 300000, + .fpfd_max = 450000, .fvco_min = 600000, .fvco_max = 1200000, }; From patchwork Wed Jun 11 16:15:34 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Nuno_S=C3=A1_via_B4_Relay?= X-Patchwork-Id: 895740 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 49C5F1F8756; Wed, 11 Jun 2025 16:15:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749658528; cv=none; b=Zh8g5oxqzoqOddp9W39p7eXcMaJH5XxzrouMrse2nqyclNUYISBf3xobjVcS3dNo8pQzRy2aw4K+YqfOnYlm4xYspSc2nWuuj91X3dOyHLEXAju4YL4+DKvGnYEhbUp/XdAnJjKQD4xG5wewD1EPQ2GHtDJhfSgc9mdsZYllSzw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749658528; c=relaxed/simple; bh=tYiLJujWc+iv8z7OkMU3wg41iVItPHvcvfpeKX54doE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Fbs9NjV/50nTkl+xSBfab/7YHIH/9+YDxijpYivKSHKZD2/SSQr2exNbpHPe0yC+q71wjyXxLAOdIOCYYHYil5DGA8ZKLLggLmbUEnU28sUzr+YpB/whUk69m6S43Qg6Uv9W5WApiFWnm3tBMKfKcoMI6lKEv/pYmmpyMaNJkrA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=GVp/72ZE; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="GVp/72ZE" Received: by smtp.kernel.org (Postfix) with ESMTPS id D1DF1C4CEF5; Wed, 11 Jun 2025 16:15:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749658527; bh=tYiLJujWc+iv8z7OkMU3wg41iVItPHvcvfpeKX54doE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=GVp/72ZEEWfkipDnLCVY/9XsEp8ydGn0S4Ae1wjCQ9kzFn0+2GNI1y79oXp5Oibic XREuN4fNwvVgeAl1hRrx1oXwKBMrQgR5WvdfWRULmHs8kVDhvKZF0iUlwmcW1j8XE0 nYwWfKlUKbyABeLa7ebF4/XqMlMQF95PtGLSNgTomXWpRrz11aUX4ehvrvtvT1DJEs 057iFBlf5xvwDn1Swg5LErCRIxN/rbRvKDUfGxlVVgEuq+V3br2A0ol/vZMUHhpn5P cb4+ccBsh59K+KChe6ZJ5axKJ++YDTKsFZ9o1uqS8jRAzDYVeKgRa+4A+2cBq05OEh 0lEmPFwgXQpUw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id C2359C71137; Wed, 11 Jun 2025 16:15:27 +0000 (UTC) From: =?utf-8?q?Nuno_S=C3=A1_via_B4_Relay?= Date: Wed, 11 Jun 2025 17:15:34 +0100 Subject: [PATCH v7 2/7] clk: clk-axi-clkgen: make sure to include mod_devicetable.h Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250611-dev-axi-clkgen-limits-v7-2-3e7ff89dc366@analog.com> References: <20250611-dev-axi-clkgen-limits-v7-0-3e7ff89dc366@analog.com> In-Reply-To: <20250611-dev-axi-clkgen-limits-v7-0-3e7ff89dc366@analog.com> To: linux-clk@vger.kernel.org, linux-fpga@vger.kernel.org, dmaengine@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-iio@vger.kernel.org, linux-pwm@vger.kernel.org, linux-spi@vger.kernel.org Cc: Stephen Boyd , Michael Turquette , Moritz Fischer , Wu Hao , Xu Yilun , Tom Rix , Vinod Koul , Jean Delvare , Guenter Roeck , Michael Hennerich , Jonathan Cameron , Trevor Gamblin , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , David Lechner , Mark Brown , Mike Turquette X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1749658534; l=711; i=nuno.sa@analog.com; s=20231116; h=from:subject:message-id; bh=MyQa116l4E9wDyCm1ZTrQoq6qju7oKOtUMHCY6i0bL8=; b=lpqn2NFACO8BVxIFWzKavxSdCK09vkm+m/iz7arjiDzWCELzB5HWvCWN3dummH4EkjOmRCr7K cHIZjqT/3uLC5GSh9o/+TcTkXZvBEFLumXjz7yG6/Mv/TI3pJC+WcRn X-Developer-Key: i=nuno.sa@analog.com; a=ed25519; pk=3NQwYA013OUYZsmDFBf8rmyyr5iQlxV/9H4/Df83o1E= X-Endpoint-Received: by B4 Relay for nuno.sa@analog.com/20231116 with auth_id=100 X-Original-From: =?utf-8?q?Nuno_S=C3=A1?= Reply-To: nuno.sa@analog.com From: Nuno Sá The mod_devicetable header is the one to be used for struct of_device_id. Reviewed-by: David Lechner Signed-off-by: Nuno Sá --- drivers/clk/clk-axi-clkgen.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/clk-axi-clkgen.c b/drivers/clk/clk-axi-clkgen.c index 00bf799964c61a3efc042b0f3a9ec3bc8625c9da..2a95f9b220234a1245024a821c50e1eb9c104ac9 100644 --- a/drivers/clk/clk-axi-clkgen.c +++ b/drivers/clk/clk-axi-clkgen.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #define AXI_CLKGEN_V2_REG_RESET 0x40 From patchwork Wed Jun 11 16:15:35 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Nuno_S=C3=A1_via_B4_Relay?= X-Patchwork-Id: 896617 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 49CC11FBEA6; Wed, 11 Jun 2025 16:15:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749658528; cv=none; b=LXVkX4wLgRc6CnMKMWD72sGNLUkr36GmoApwQIiAewhSX9Gr5BL1so6ys8pNkHVQt0i5UvCcm0SpqeCBgJJYxVGPfBLVKB+cNpPngO3MFXDCFurQWYmp+HyzmLtZq0roBjRm/rpBYpnmb3pJZ1a3oa534tIDO+nk8a3zUJkLW6Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749658528; c=relaxed/simple; bh=QIiuXtrBlH8VQb4Kh0Au+xvFFn8KUJ1zYPChv1e6lKw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=BjfiqshN7kh+GFBDtpxS/C5W/IsOl7r644yXrbuKNUBhmT6xgQKFYZ45V5CrEz3y8ivB3/D9vOU0/x52q3ZpK9FsAcaavSblan5bwq8MhDg8Vg074Y+nV3d1TaiXhX6uhtQEijfHvzGIueACNi7Q+iKwk9k4Lo3elx7jwJ6ELm4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=NNWh0R1r; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="NNWh0R1r" Received: by smtp.kernel.org (Postfix) with ESMTPS id E905CC4CEF8; Wed, 11 Jun 2025 16:15:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749658528; bh=QIiuXtrBlH8VQb4Kh0Au+xvFFn8KUJ1zYPChv1e6lKw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=NNWh0R1r1WSPNDqPKXPszjVTQtF+rSve0S9d7uIReAgKk3EKccci9DLAxAiFz3c25 Z2NN4vq1/ucHyXfRwB+tKSYg/tk9t6M148YodvpLSefrpcblFHy8AyKaMDB4jQe+oQ gDYbkN4m46hd5jKn6XLvek+NAFrlvg3BgN766uPM8W6JVc2/0bSPnVeeQ9kX/LVXBt yrNTOpgWt0USJ7M44K8Pba/++F4Fap0g7+VjVG5X4UNdrgtR78G1FnbBnwbgXob1Zm Pmz03hUZG+0tG5Oqx1icc3e2D/t0pMXWL2TMxzFZppIgPAhreHs9meNzlm1XWqRaLx z5RhOfqiiWlYQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD9B4C71131; Wed, 11 Jun 2025 16:15:27 +0000 (UTC) From: =?utf-8?q?Nuno_S=C3=A1_via_B4_Relay?= Date: Wed, 11 Jun 2025 17:15:35 +0100 Subject: [PATCH v7 3/7] include: linux: move adi-axi-common.h out of fpga Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250611-dev-axi-clkgen-limits-v7-3-3e7ff89dc366@analog.com> References: <20250611-dev-axi-clkgen-limits-v7-0-3e7ff89dc366@analog.com> In-Reply-To: <20250611-dev-axi-clkgen-limits-v7-0-3e7ff89dc366@analog.com> To: linux-clk@vger.kernel.org, linux-fpga@vger.kernel.org, dmaengine@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-iio@vger.kernel.org, linux-pwm@vger.kernel.org, linux-spi@vger.kernel.org Cc: Stephen Boyd , Michael Turquette , Moritz Fischer , Wu Hao , Xu Yilun , Tom Rix , Vinod Koul , Jean Delvare , Guenter Roeck , Michael Hennerich , Jonathan Cameron , Trevor Gamblin , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , David Lechner , Mark Brown , Mike Turquette , Xu Yilun , Jonathan Cameron X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1749658534; l=4922; i=nuno.sa@analog.com; s=20231116; h=from:subject:message-id; bh=yfuzhyQ99zS15NVAtmX0gWwBIRxX8p3l95YLPlSA540=; b=WInx09vU1MgBG2cGBYDAw1KDxrhyNPAMCIrpYPTKIsj84AFvbnHslVCVT44aGR3YSuZti2cqX UNKS/+BRh1SD6/5mX5mxw8OVJZrc/AsCx3p8+fsNyi8ZFpLrb3EzXml X-Developer-Key: i=nuno.sa@analog.com; a=ed25519; pk=3NQwYA013OUYZsmDFBf8rmyyr5iQlxV/9H4/Df83o1E= X-Endpoint-Received: by B4 Relay for nuno.sa@analog.com/20231116 with auth_id=100 X-Original-From: =?utf-8?q?Nuno_S=C3=A1?= Reply-To: nuno.sa@analog.com From: Nuno Sá The adi-axi-common.h header has some common defines used in various ADI IPs. However they are not specific for any fpga manager so it's questionable for the header to live under include/linux/fpga. Hence let's just move one directory up and update all users. Suggested-by: Xu Yilun Acked-by: Xu Yilun Acked-by: Jonathan Cameron # for IIO Acked-by: Uwe Kleine-König Acked-by: Mark Brown Reviewed-by: David Lechner Signed-off-by: Nuno Sá --- drivers/dma/dma-axi-dmac.c | 2 +- drivers/hwmon/axi-fan-control.c | 2 +- drivers/iio/adc/adi-axi-adc.c | 3 +-- drivers/iio/dac/adi-axi-dac.c | 2 +- drivers/pwm/pwm-axi-pwmgen.c | 2 +- drivers/spi/spi-axi-spi-engine.c | 2 +- include/linux/{fpga => }/adi-axi-common.h | 0 7 files changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/dma/dma-axi-dmac.c b/drivers/dma/dma-axi-dmac.c index 36943b0c6d603cbe38606b0d7bde02535f529a9a..5b06b0dc67ee12017c165bf815fb7c0e1bf5abd8 100644 --- a/drivers/dma/dma-axi-dmac.c +++ b/drivers/dma/dma-axi-dmac.c @@ -6,6 +6,7 @@ * Author: Lars-Peter Clausen */ +#include #include #include #include @@ -22,7 +23,6 @@ #include #include #include -#include #include diff --git a/drivers/hwmon/axi-fan-control.c b/drivers/hwmon/axi-fan-control.c index 35c862eb158b0909dac64c2e9f51f0f9f0e8bf72..b7bb325c3ad966ed2a93be4dfbf4e20661568509 100644 --- a/drivers/hwmon/axi-fan-control.c +++ b/drivers/hwmon/axi-fan-control.c @@ -4,9 +4,9 @@ * * Copyright 2019 Analog Devices Inc. */ +#include #include #include -#include #include #include #include diff --git a/drivers/iio/adc/adi-axi-adc.c b/drivers/iio/adc/adi-axi-adc.c index c7357601f0f869e57636f00bb1e26c059c3ab15c..87fa18f1ec96782556bdfad08bedb5e7549fb93d 100644 --- a/drivers/iio/adc/adi-axi-adc.c +++ b/drivers/iio/adc/adi-axi-adc.c @@ -6,6 +6,7 @@ * Copyright 2012-2020 Analog Devices Inc. */ +#include #include #include #include @@ -20,8 +21,6 @@ #include #include -#include - #include #include #include diff --git a/drivers/iio/dac/adi-axi-dac.c b/drivers/iio/dac/adi-axi-dac.c index b143f7ed6847277aeb49094627d90e5d95eed71c..581a2fe55a7fb35f1a03f96f3a0e95421d1583e7 100644 --- a/drivers/iio/dac/adi-axi-dac.c +++ b/drivers/iio/dac/adi-axi-dac.c @@ -5,6 +5,7 @@ * * Copyright 2016-2024 Analog Devices Inc. */ +#include #include #include #include @@ -23,7 +24,6 @@ #include #include -#include #include #include #include diff --git a/drivers/pwm/pwm-axi-pwmgen.c b/drivers/pwm/pwm-axi-pwmgen.c index 4259a0db9ff45808eecae28680473292d165d1f6..e720191e74558d15f1b04fa18cf2984299f88809 100644 --- a/drivers/pwm/pwm-axi-pwmgen.c +++ b/drivers/pwm/pwm-axi-pwmgen.c @@ -18,10 +18,10 @@ * - Supports normal polarity. Does not support changing polarity. * - On disable, the PWM output becomes low (inactive). */ +#include #include #include #include -#include #include #include #include diff --git a/drivers/spi/spi-axi-spi-engine.c b/drivers/spi/spi-axi-spi-engine.c index 7c252126b33ea83fe6a6e80c6cb87499243069f5..d498132f1ff6adf20639bf4a21f1687903934bec 100644 --- a/drivers/spi/spi-axi-spi-engine.c +++ b/drivers/spi/spi-axi-spi-engine.c @@ -5,9 +5,9 @@ * Author: Lars-Peter Clausen */ +#include #include #include -#include #include #include #include diff --git a/include/linux/fpga/adi-axi-common.h b/include/linux/adi-axi-common.h similarity index 100% rename from include/linux/fpga/adi-axi-common.h rename to include/linux/adi-axi-common.h From patchwork Wed Jun 11 16:15:36 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Nuno_S=C3=A1_via_B4_Relay?= X-Patchwork-Id: 895739 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AFD9920E713; Wed, 11 Jun 2025 16:15:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749658528; cv=none; b=pu7AsAFMV375cxyVdkvQln8WaLNpNs5RsazLqtIBStz5cwJD6bHxOHrfaQsxDX380rhZ8Z5aO+DjHOS38caU/knN8GwGSjNEwoOWkZnh8SJxW+2i58JrE4Ddeawwv1b1A7yylXVejxH+kwryWg7tz1Iq/nGY637c4bd0rp781rk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749658528; c=relaxed/simple; bh=W24IHKj+SlDNVJOCYhxMLrPfL4h+fsCaf5OkbSZrYPE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=GzaMfSBznhB9138GzK5wf6OqHEqanZz/h79o7903x3dR8lguARKWYBbyVcoNg6xQ7MlJiNYexJK6fU8XMHHzaz9ialQag78t1vVbvyxSZtfyY2/N6C0D6IUuO6AJ13BKMRHy/tykM3vtCVCoCvEANPOJSrGJBKg2ORGrFH6qUa8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=aBC0U1cn; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="aBC0U1cn" Received: by smtp.kernel.org (Postfix) with ESMTPS id 3F3DBC4CEF1; Wed, 11 Jun 2025 16:15:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749658528; bh=W24IHKj+SlDNVJOCYhxMLrPfL4h+fsCaf5OkbSZrYPE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=aBC0U1cnZSV/tUpnp8s4uZID5pZ17rISamioIZK1ZXkqmgoCPtAcL/QFMQ4/W4BPK 71mBHV4591Wl8JNx+bEEO89SgQ277u2qsJNHHV568mBBUtFjp6TXB+Ye14iAaTFkEe DeRPIsRykXd1RUdmXiTPgpo/zlVKczM26GOGJVJ3SYO1kR8xkTf/kcqI0B98LSss0C jX84njUMzhM3TFTFRXgWBD6pWabCQKORC6354Mv69eVjNgMGDO9XH9fHJhyeu/PqkD s0mxvPLHsaDE7aIRYcUaIhbAnc31TnznjkP75Kx174wsC55eFTKFzgjRtmWgYNBPJf 1PTOBn4HqcdXA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 30346C71136; Wed, 11 Jun 2025 16:15:28 +0000 (UTC) From: =?utf-8?q?Nuno_S=C3=A1_via_B4_Relay?= Date: Wed, 11 Jun 2025 17:15:36 +0100 Subject: [PATCH v7 4/7] include: adi-axi-common: add new helper macros Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250611-dev-axi-clkgen-limits-v7-4-3e7ff89dc366@analog.com> References: <20250611-dev-axi-clkgen-limits-v7-0-3e7ff89dc366@analog.com> In-Reply-To: <20250611-dev-axi-clkgen-limits-v7-0-3e7ff89dc366@analog.com> To: linux-clk@vger.kernel.org, linux-fpga@vger.kernel.org, dmaengine@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-iio@vger.kernel.org, linux-pwm@vger.kernel.org, linux-spi@vger.kernel.org Cc: Stephen Boyd , Michael Turquette , Moritz Fischer , Wu Hao , Xu Yilun , Tom Rix , Vinod Koul , Jean Delvare , Guenter Roeck , Michael Hennerich , Jonathan Cameron , Trevor Gamblin , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , David Lechner , Mark Brown , Mike Turquette X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1749658534; l=1982; i=nuno.sa@analog.com; s=20231116; h=from:subject:message-id; bh=8E3tnJOQHd1DGzVU+4oHkcTaB0uu72Nu8VTU/0TEplU=; b=Md983xgf8ErNqhqVFV+MJfO9rlfkbsqcF4S5/wsBswB3x7fzLWdoK50y9F3701UdBFP0ou8xf k3pikImOm52Cg8OWoU6oonHFTvAgglzP2ojINKZdgC68N/eqJrvZ8lC X-Developer-Key: i=nuno.sa@analog.com; a=ed25519; pk=3NQwYA013OUYZsmDFBf8rmyyr5iQlxV/9H4/Df83o1E= X-Endpoint-Received: by B4 Relay for nuno.sa@analog.com/20231116 with auth_id=100 X-Original-From: =?utf-8?q?Nuno_S=C3=A1?= Reply-To: nuno.sa@analog.com From: Nuno Sá Add new helper macros and enums to help identifying the platform and some characteristics of it at runtime. Reviewed-by: David Lechner Signed-off-by: Nuno Sá --- include/linux/adi-axi-common.h | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/include/linux/adi-axi-common.h b/include/linux/adi-axi-common.h index 141ac3f251e6f256526812b9d55cd440a2a46e76..f64f4ad4bedae312ec450bd5fed09ceaedd5397e 100644 --- a/include/linux/adi-axi-common.h +++ b/include/linux/adi-axi-common.h @@ -12,6 +12,7 @@ #define ADI_AXI_COMMON_H_ #define ADI_AXI_REG_VERSION 0x0000 +#define ADI_AXI_REG_FPGA_INFO 0x001C #define ADI_AXI_PCORE_VER(major, minor, patch) \ (((major) << 16) | ((minor) << 8) | (patch)) @@ -20,4 +21,36 @@ #define ADI_AXI_PCORE_VER_MINOR(version) (((version) >> 8) & 0xff) #define ADI_AXI_PCORE_VER_PATCH(version) ((version) & 0xff) +#define ADI_AXI_INFO_FPGA_TECH(info) (((info) >> 24) & 0xff) +#define ADI_AXI_INFO_FPGA_FAMILY(info) (((info) >> 16) & 0xff) +#define ADI_AXI_INFO_FPGA_SPEED_GRADE(info) (((info) >> 8) & 0xff) + +enum adi_axi_fpga_technology { + ADI_AXI_FPGA_TECH_UNKNOWN = 0, + ADI_AXI_FPGA_TECH_SERIES7, + ADI_AXI_FPGA_TECH_ULTRASCALE, + ADI_AXI_FPGA_TECH_ULTRASCALE_PLUS, +}; + +enum adi_axi_fpga_family { + ADI_AXI_FPGA_FAMILY_UNKNOWN = 0, + ADI_AXI_FPGA_FAMILY_ARTIX, + ADI_AXI_FPGA_FAMILY_KINTEX, + ADI_AXI_FPGA_FAMILY_VIRTEX, + ADI_AXI_FPGA_FAMILY_ZYNQ, +}; + +enum adi_axi_fpga_speed_grade { + ADI_AXI_FPGA_SPEED_UNKNOWN = 0, + ADI_AXI_FPGA_SPEED_1 = 10, + ADI_AXI_FPGA_SPEED_1L = 11, + ADI_AXI_FPGA_SPEED_1H = 12, + ADI_AXI_FPGA_SPEED_1HV = 13, + ADI_AXI_FPGA_SPEED_1LV = 14, + ADI_AXI_FPGA_SPEED_2 = 20, + ADI_AXI_FPGA_SPEED_2L = 21, + ADI_AXI_FPGA_SPEED_2LV = 22, + ADI_AXI_FPGA_SPEED_3 = 30, +}; + #endif /* ADI_AXI_COMMON_H_ */ From patchwork Wed Jun 11 16:15:37 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Nuno_S=C3=A1_via_B4_Relay?= X-Patchwork-Id: 896616 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C5F5B20F062; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="VcTktXJv" Received: by smtp.kernel.org (Postfix) with ESMTPS id 689ECC4CEE3; Wed, 11 Jun 2025 16:15:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749658528; bh=j9/RALxD1SKb25mLlSiuMDxtfhgVeK371XMTkwVz7/k=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=VcTktXJvf08cnQr/LDqc8Yqao9ifW2193YPK/Dl7aiOhRnkQyjbSVWH/v84TJ1IPf aY7c8quGCbE16nATg7IZioktEZeJ68vguY1pYP5Nr51BQcJuyZqOrf3MFX8p5KfvhR Ww7fZhAU22AGhATKmgenSZn+2FypW+9POqC4XN0/cqSsp6+9AcMKOmkRN+el4t1RU9 VAaVPzeNEJRhj2Ej5XmqsNJ+ELD2LkmFVuGn0e1SMAz7Cyu+lqjRbrLgTodG2WEhEn BjK1AeqLM3/OroN2DN3wP4BZyG2JvkktG3czec7T7T2t5tm09cHCWEcPQJ2mIu73Cq yl8WOj/kO5XfQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5D66DC71131; Wed, 11 Jun 2025 16:15:28 +0000 (UTC) From: =?utf-8?q?Nuno_S=C3=A1_via_B4_Relay?= Date: Wed, 11 Jun 2025 17:15:37 +0100 Subject: [PATCH v7 5/7] clk: clk-axi-clkgen: detect axi_clkgen_limits at runtime Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250611-dev-axi-clkgen-limits-v7-5-3e7ff89dc366@analog.com> References: <20250611-dev-axi-clkgen-limits-v7-0-3e7ff89dc366@analog.com> In-Reply-To: <20250611-dev-axi-clkgen-limits-v7-0-3e7ff89dc366@analog.com> To: linux-clk@vger.kernel.org, linux-fpga@vger.kernel.org, dmaengine@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-iio@vger.kernel.org, linux-pwm@vger.kernel.org, linux-spi@vger.kernel.org Cc: Stephen Boyd , Michael Turquette , Moritz Fischer , Wu Hao , Xu Yilun , Tom Rix , Vinod Koul , Jean Delvare , Guenter Roeck , Michael Hennerich , Jonathan Cameron , Trevor Gamblin , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , David Lechner , Mark Brown , Mike Turquette X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1749658534; l=4033; i=nuno.sa@analog.com; s=20231116; h=from:subject:message-id; bh=oa8GDBu7Mkar5AH+bEzIfBrJjWKmaurG/C1FZ+6SxNw=; b=hJx/cE+R89xiFEIctQ8TKVT0FSinw6GZ4d8ojqOFIfY1ZwFUt7reOsEQfij1la4lVhBEa9oO7 gxDO/pgX5UaAWHOXkEv+MDOAzt5inBfZ+hKvlNReAI/5ztxTFokTMI0 X-Developer-Key: i=nuno.sa@analog.com; a=ed25519; pk=3NQwYA013OUYZsmDFBf8rmyyr5iQlxV/9H4/Df83o1E= X-Endpoint-Received: by B4 Relay for nuno.sa@analog.com/20231116 with auth_id=100 X-Original-From: =?utf-8?q?Nuno_S=C3=A1?= Reply-To: nuno.sa@analog.com From: Nuno Sá This patch adds support for setting the limits in struct axi_clkgen_limits in accordance with fpga speed grade, voltage, technology and family. This new information is extracted from two new registers implemented in the ip core that are only available for core versions higher or equal to 4. Reviewed-by: David Lechner Signed-off-by: Nuno Sá --- drivers/clk/clk-axi-clkgen.c | 65 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 64 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk-axi-clkgen.c b/drivers/clk/clk-axi-clkgen.c index 2a95f9b220234a1245024a821c50e1eb9c104ac9..f4e96394e9c25c817b09ee0c08751147083f19b7 100644 --- a/drivers/clk/clk-axi-clkgen.c +++ b/drivers/clk/clk-axi-clkgen.c @@ -6,6 +6,8 @@ * Author: Lars-Peter Clausen */ +#include +#include #include #include #include @@ -29,6 +31,9 @@ #define AXI_CLKGEN_V2_DRP_STATUS_BUSY BIT(16) +#define ADI_CLKGEN_REG_FPGA_VOLTAGE 0x0140 +#define ADI_CLKGEN_INFO_FPGA_VOLTAGE(val) ((val) & GENMASK(15, 0)) + #define MMCM_REG_CLKOUT5_2 0x07 #define MMCM_REG_CLKOUT0_1 0x08 #define MMCM_REG_CLKOUT0_2 0x09 @@ -497,6 +502,54 @@ static u8 axi_clkgen_get_parent(struct clk_hw *clk_hw) return parent; } +static int axi_clkgen_setup_limits(struct axi_clkgen *axi_clkgen, + struct device *dev) +{ + unsigned int tech, family, speed_grade, reg_value; + + axi_clkgen_read(axi_clkgen, ADI_AXI_REG_FPGA_INFO, ®_value); + tech = ADI_AXI_INFO_FPGA_TECH(reg_value); + family = ADI_AXI_INFO_FPGA_FAMILY(reg_value); + speed_grade = ADI_AXI_INFO_FPGA_SPEED_GRADE(reg_value); + + axi_clkgen->limits.fpfd_min = 10000; + axi_clkgen->limits.fvco_min = 600000; + + switch (speed_grade) { + case ADI_AXI_FPGA_SPEED_1 ... ADI_AXI_FPGA_SPEED_1LV: + axi_clkgen->limits.fvco_max = 1200000; + axi_clkgen->limits.fpfd_max = 450000; + break; + case ADI_AXI_FPGA_SPEED_2 ... ADI_AXI_FPGA_SPEED_2LV: + axi_clkgen->limits.fvco_max = 1440000; + axi_clkgen->limits.fpfd_max = 500000; + if (family == ADI_AXI_FPGA_FAMILY_KINTEX || family == ADI_AXI_FPGA_FAMILY_ARTIX) { + axi_clkgen_read(axi_clkgen, ADI_CLKGEN_REG_FPGA_VOLTAGE, + ®_value); + if (ADI_CLKGEN_INFO_FPGA_VOLTAGE(reg_value) < 950) { + axi_clkgen->limits.fvco_max = 1200000; + axi_clkgen->limits.fpfd_max = 450000; + } + } + break; + case ADI_AXI_FPGA_SPEED_3: + axi_clkgen->limits.fvco_max = 1600000; + axi_clkgen->limits.fpfd_max = 550000; + break; + default: + return dev_err_probe(dev, -ENODEV, "Unknown speed grade %d\n", + speed_grade); + }; + + /* Overwrite vco limits for ultrascale+ */ + if (tech == ADI_AXI_FPGA_TECH_ULTRASCALE_PLUS) { + axi_clkgen->limits.fvco_max = 1600000; + axi_clkgen->limits.fvco_min = 800000; + } + + return 0; +} + static const struct clk_ops axi_clkgen_ops = { .recalc_rate = axi_clkgen_recalc_rate, .determine_rate = axi_clkgen_determine_rate, @@ -511,6 +564,7 @@ static int axi_clkgen_probe(struct platform_device *pdev) { const struct axi_clkgen_limits *dflt_limits; struct axi_clkgen *axi_clkgen; + unsigned int pcore_version; struct clk_init_data init; const char *parent_names[2]; const char *clk_name; @@ -556,7 +610,16 @@ static int axi_clkgen_probe(struct platform_device *pdev) return -EINVAL; } - memcpy(&axi_clkgen->limits, dflt_limits, sizeof(axi_clkgen->limits)); + axi_clkgen_read(axi_clkgen, ADI_AXI_REG_VERSION, &pcore_version); + + if (ADI_AXI_PCORE_VER_MAJOR(pcore_version) > 0x04) { + ret = axi_clkgen_setup_limits(axi_clkgen, &pdev->dev); + if (ret) + return ret; + } else { + memcpy(&axi_clkgen->limits, dflt_limits, + sizeof(axi_clkgen->limits)); + } clk_name = pdev->dev.of_node->name; of_property_read_string(pdev->dev.of_node, "clock-output-names", From patchwork Wed Jun 11 16:15:38 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Nuno_S=C3=A1_via_B4_Relay?= X-Patchwork-Id: 895738 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C5FA720F067; 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a=ed25519-sha256; t=1749658534; l=1547; i=nuno.sa@analog.com; s=20231116; h=from:subject:message-id; bh=piuSskdq8cMRdCP+4hCdaWdOTgdc2I6WLf29pd00o00=; b=2tHpYLnoiaPEdaPdbjtDfWiBrJbsGu700SIg58vpsWt3h9J220f/DBofXHKBXPTHkVMf8zphl +tBm0n69B/IC0kWc7/D0M9S8jwSQ3dOM3w7gxaGEGOaIFNXVrb+O08L X-Developer-Key: i=nuno.sa@analog.com; a=ed25519; pk=3NQwYA013OUYZsmDFBf8rmyyr5iQlxV/9H4/Df83o1E= X-Endpoint-Received: by B4 Relay for nuno.sa@analog.com/20231116 with auth_id=100 X-Original-From: =?utf-8?q?Nuno_S=C3=A1?= Reply-To: nuno.sa@analog.com From: Nuno Sá Instead of using the type versions of min/max(), use the plain ones as now they are perfectly capable of handling different types like unsigned and non negative integers that are compiletime constant. Reviewed-by: David Lechner Signed-off-by: Nuno Sá --- drivers/clk/clk-axi-clkgen.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/clk-axi-clkgen.c b/drivers/clk/clk-axi-clkgen.c index f4e96394e9c25c817b09ee0c08751147083f19b7..63951209c460f26ed3940879da536e31ae530188 100644 --- a/drivers/clk/clk-axi-clkgen.c +++ b/drivers/clk/clk-axi-clkgen.c @@ -147,15 +147,15 @@ static void axi_clkgen_calc_params(const struct axi_clkgen_limits *limits, *best_m = 0; *best_dout = 0; - d_min = max_t(unsigned long, DIV_ROUND_UP(fin, limits->fpfd_max), 1); - d_max = min_t(unsigned long, fin / limits->fpfd_min, 80); + d_min = max(DIV_ROUND_UP(fin, limits->fpfd_max), 1); + d_max = min(fin / limits->fpfd_min, 80); again: fvco_min_fract = limits->fvco_min << fract_shift; fvco_max_fract = limits->fvco_max << fract_shift; - m_min = max_t(unsigned long, DIV_ROUND_UP(fvco_min_fract, fin) * d_min, 1); - m_max = min_t(unsigned long, fvco_max_fract * d_max / fin, 64 << fract_shift); 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b=GraR6YWaY58wFeErPEorm+z9HuGUfQ1xHElfZ90TwmswCxm4cmEHeZ/b9eYphCURb sczFyhrDhQN/c3fGZH4E+aVqsIu/qyo2PJ+egE6k677se8el5AOqsdsjhJlzg4CChE HyqKi7K/R3V2QHaTtv1yFbLnDR4o+WFWTG3VIHOe3d3a4zr22oy2maxnEB4VSgopFM ne1E1gFvtkboVpc8Cp+3AxsRJIhGVZll+ZGfrsWyx6Et75xRglSES18wufsg2fDhsT uyzCLbV8X3+fpdUFXxO62JKdaERWzsDopGsJmPAdydZFuUEg5xpGpyozCVp8LwKNOX R4WrB48waNPoA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8B9EAC71137; Wed, 11 Jun 2025 16:15:28 +0000 (UTC) From: =?utf-8?q?Nuno_S=C3=A1_via_B4_Relay?= Date: Wed, 11 Jun 2025 17:15:39 +0100 Subject: [PATCH v7 7/7] clk: clk-axi-clkgen: fix coding style issues Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250611-dev-axi-clkgen-limits-v7-7-3e7ff89dc366@analog.com> References: <20250611-dev-axi-clkgen-limits-v7-0-3e7ff89dc366@analog.com> In-Reply-To: <20250611-dev-axi-clkgen-limits-v7-0-3e7ff89dc366@analog.com> To: linux-clk@vger.kernel.org, linux-fpga@vger.kernel.org, dmaengine@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-iio@vger.kernel.org, linux-pwm@vger.kernel.org, linux-spi@vger.kernel.org Cc: Stephen Boyd , Michael Turquette , Moritz Fischer , Wu Hao , Xu Yilun , Tom Rix , Vinod Koul , Jean Delvare , Guenter Roeck , Michael Hennerich , Jonathan Cameron , Trevor Gamblin , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , David Lechner , Mark Brown , Mike Turquette X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1749658534; l=8920; i=nuno.sa@analog.com; s=20231116; h=from:subject:message-id; bh=sorHKMrAW+F3I7VGWSk76fxF6xnhAstzzbm7Y/HmTtw=; b=Nigpkwfqk9+9ZdoAIPKMwIRulpX4OzWeE0X9ugMT3oTDpjGWe/CKfgxCkOpij8oCQpa+sdsP4 sLxFm9ItelRA5tfgloKsROLbtJjp+gFI68+Oc+O3nFrA0YlpmE7sY+I X-Developer-Key: i=nuno.sa@analog.com; a=ed25519; pk=3NQwYA013OUYZsmDFBf8rmyyr5iQlxV/9H4/Df83o1E= X-Endpoint-Received: by B4 Relay for nuno.sa@analog.com/20231116 with auth_id=100 X-Original-From: =?utf-8?q?Nuno_S=C3=A1?= Reply-To: nuno.sa@analog.com From: Nuno Sá This is just cosmetics and so no functional changes intended. While at it, sort header in alphabetical order. Reviewed-by: David Lechner Signed-off-by: Nuno Sá --- drivers/clk/clk-axi-clkgen.c | 81 ++++++++++++++++++++++---------------------- 1 file changed, 41 insertions(+), 40 deletions(-) diff --git a/drivers/clk/clk-axi-clkgen.c b/drivers/clk/clk-axi-clkgen.c index 63951209c460f26ed3940879da536e31ae530188..2bb52c4dc7be5167380c1d158d96c7618d16c558 100644 --- a/drivers/clk/clk-axi-clkgen.c +++ b/drivers/clk/clk-axi-clkgen.c @@ -8,15 +8,15 @@ #include #include -#include #include #include -#include +#include #include -#include #include #include -#include +#include +#include +#include #define AXI_CLKGEN_V2_REG_RESET 0x40 #define AXI_CLKGEN_V2_REG_CLKSEL 0x44 @@ -96,7 +96,7 @@ static uint32_t axi_clkgen_lookup_filter(unsigned int m) } } -static const uint32_t axi_clkgen_lock_table[] = { +static const u32 axi_clkgen_lock_table[] = { 0x060603e8, 0x060603e8, 0x080803e8, 0x0b0b03e8, 0x0e0e03e8, 0x111103e8, 0x131303e8, 0x161603e8, 0x191903e8, 0x1c1c03e8, 0x1f1f0384, 0x1f1f0339, @@ -108,7 +108,7 @@ static const uint32_t axi_clkgen_lock_table[] = { 0x1f1f012c, 0x1f1f0113, 0x1f1f0113, 0x1f1f0113, }; -static uint32_t axi_clkgen_lookup_lock(unsigned int m) +static u32 axi_clkgen_lookup_lock(unsigned int m) { if (m < ARRAY_SIZE(axi_clkgen_lock_table)) return axi_clkgen_lock_table[m]; @@ -130,8 +130,9 @@ static const struct axi_clkgen_limits axi_clkgen_zynq_default_limits = { }; static void axi_clkgen_calc_params(const struct axi_clkgen_limits *limits, - unsigned long fin, unsigned long fout, - unsigned int *best_d, unsigned int *best_m, unsigned int *best_dout) + unsigned long fin, unsigned long fout, + unsigned int *best_d, unsigned int *best_m, + unsigned int *best_dout) { unsigned long d, d_min, d_max, _d_min, _d_max; unsigned long m, m_min, m_max; @@ -198,9 +199,9 @@ struct axi_clkgen_div_params { }; static void axi_clkgen_calc_clk_params(unsigned int divider, - unsigned int frac_divider, struct axi_clkgen_div_params *params) + unsigned int frac_divider, + struct axi_clkgen_div_params *params) { - memset(params, 0x0, sizeof(*params)); if (divider == 1) { @@ -228,7 +229,7 @@ static void axi_clkgen_calc_clk_params(unsigned int divider, if (params->edge == 0 || frac_divider == 1) params->low--; if (((params->edge == 0) ^ (frac_divider == 1)) || - (divider == 2 && frac_divider == 1)) + (divider == 2 && frac_divider == 1)) params->frac_wf_f = 1; params->frac_phase = params->edge * 4 + frac_divider / 2; @@ -236,13 +237,13 @@ static void axi_clkgen_calc_clk_params(unsigned int divider, } static void axi_clkgen_write(struct axi_clkgen *axi_clkgen, - unsigned int reg, unsigned int val) + unsigned int reg, unsigned int val) { writel(val, axi_clkgen->base + reg); } static void axi_clkgen_read(struct axi_clkgen *axi_clkgen, - unsigned int reg, unsigned int *val) + unsigned int reg, unsigned int *val) { *val = readl(axi_clkgen->base + reg); } @@ -263,7 +264,7 @@ static int axi_clkgen_wait_non_busy(struct axi_clkgen *axi_clkgen) } static int axi_clkgen_mmcm_read(struct axi_clkgen *axi_clkgen, - unsigned int reg, unsigned int *val) + unsigned int reg, unsigned int *val) { unsigned int reg_val; int ret; @@ -287,7 +288,8 @@ static int axi_clkgen_mmcm_read(struct axi_clkgen *axi_clkgen, } static int axi_clkgen_mmcm_write(struct axi_clkgen *axi_clkgen, - unsigned int reg, unsigned int val, unsigned int mask) + unsigned int reg, unsigned int val, + unsigned int mask) { unsigned int reg_val = 0; int ret; @@ -308,8 +310,7 @@ static int axi_clkgen_mmcm_write(struct axi_clkgen *axi_clkgen, return 0; } -static void axi_clkgen_mmcm_enable(struct axi_clkgen *axi_clkgen, - bool enable) +static void axi_clkgen_mmcm_enable(struct axi_clkgen *axi_clkgen, bool enable) { unsigned int val = AXI_CLKGEN_V2_RESET_ENABLE; @@ -325,31 +326,31 @@ static struct axi_clkgen *clk_hw_to_axi_clkgen(struct clk_hw *clk_hw) } static void axi_clkgen_set_div(struct axi_clkgen *axi_clkgen, - unsigned int reg1, unsigned int reg2, unsigned int reg3, - struct axi_clkgen_div_params *params) + unsigned int reg1, unsigned int reg2, + unsigned int reg3, + struct axi_clkgen_div_params *params) { axi_clkgen_mmcm_write(axi_clkgen, reg1, - (params->high << 6) | params->low, 0xefff); + (params->high << 6) | params->low, 0xefff); axi_clkgen_mmcm_write(axi_clkgen, reg2, - (params->frac << 12) | (params->frac_en << 11) | - (params->frac_wf_r << 10) | (params->edge << 7) | - (params->nocount << 6), 0x7fff); + (params->frac << 12) | (params->frac_en << 11) | + (params->frac_wf_r << 10) | (params->edge << 7) | + (params->nocount << 6), 0x7fff); if (reg3 != 0) { axi_clkgen_mmcm_write(axi_clkgen, reg3, - (params->frac_phase << 11) | (params->frac_wf_f << 10), 0x3c00); + (params->frac_phase << 11) | (params->frac_wf_f << 10), + 0x3c00); } } -static int axi_clkgen_set_rate(struct clk_hw *clk_hw, - unsigned long rate, unsigned long parent_rate) +static int axi_clkgen_set_rate(struct clk_hw *clk_hw, unsigned long rate, + unsigned long parent_rate) { struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw); const struct axi_clkgen_limits *limits = &axi_clkgen->limits; unsigned int d, m, dout; struct axi_clkgen_div_params params; - uint32_t power = 0; - uint32_t filter; - uint32_t lock; + u32 power = 0, filter, lock; if (parent_rate == 0 || rate == 0) return -EINVAL; @@ -369,22 +370,22 @@ static int axi_clkgen_set_rate(struct clk_hw *clk_hw, axi_clkgen_calc_clk_params(dout >> 3, dout & 0x7, ¶ms); axi_clkgen_set_div(axi_clkgen, MMCM_REG_CLKOUT0_1, MMCM_REG_CLKOUT0_2, - MMCM_REG_CLKOUT5_2, ¶ms); + MMCM_REG_CLKOUT5_2, ¶ms); axi_clkgen_calc_clk_params(d, 0, ¶ms); axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_CLK_DIV, - (params.edge << 13) | (params.nocount << 12) | - (params.high << 6) | params.low, 0x3fff); + (params.edge << 13) | (params.nocount << 12) | + (params.high << 6) | params.low, 0x3fff); axi_clkgen_calc_clk_params(m >> 3, m & 0x7, ¶ms); axi_clkgen_set_div(axi_clkgen, MMCM_REG_CLK_FB1, MMCM_REG_CLK_FB2, - MMCM_REG_CLKOUT6_2, ¶ms); + MMCM_REG_CLKOUT6_2, ¶ms); axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK1, lock & 0x3ff, 0x3ff); axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK2, - (((lock >> 16) & 0x1f) << 10) | 0x1, 0x7fff); + (((lock >> 16) & 0x1f) << 10) | 0x1, 0x7fff); axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK3, - (((lock >> 24) & 0x1f) << 10) | 0x3e9, 0x7fff); + (((lock >> 24) & 0x1f) << 10) | 0x3e9, 0x7fff); axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_FILTER1, filter >> 16, 0x9900); axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_FILTER2, filter, 0x9900); @@ -413,7 +414,7 @@ static int axi_clkgen_determine_rate(struct clk_hw *hw, } static unsigned int axi_clkgen_get_div(struct axi_clkgen *axi_clkgen, - unsigned int reg1, unsigned int reg2) + unsigned int reg1, unsigned int reg2) { unsigned int val1, val2; unsigned int div; @@ -440,7 +441,7 @@ static unsigned int axi_clkgen_get_div(struct axi_clkgen *axi_clkgen, } static unsigned long axi_clkgen_recalc_rate(struct clk_hw *clk_hw, - unsigned long parent_rate) + unsigned long parent_rate) { struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw); unsigned int d, m, dout; @@ -448,9 +449,9 @@ static unsigned long axi_clkgen_recalc_rate(struct clk_hw *clk_hw, unsigned int val; dout = axi_clkgen_get_div(axi_clkgen, MMCM_REG_CLKOUT0_1, - MMCM_REG_CLKOUT0_2); + MMCM_REG_CLKOUT0_2); m = axi_clkgen_get_div(axi_clkgen, MMCM_REG_CLK_FB1, - MMCM_REG_CLK_FB2); + MMCM_REG_CLK_FB2); axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_DIV, &val); if (val & MMCM_CLK_DIV_NOCOUNT) @@ -623,7 +624,7 @@ static int axi_clkgen_probe(struct platform_device *pdev) clk_name = pdev->dev.of_node->name; of_property_read_string(pdev->dev.of_node, "clock-output-names", - &clk_name); + &clk_name); init.name = clk_name; init.ops = &axi_clkgen_ops;