From patchwork Fri Jun 13 05:56:05 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pritam Manohar Sutar X-Patchwork-Id: 896208 Received: from mailout4.samsung.com (mailout4.samsung.com [203.254.224.34]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 72DF225393B for ; Fri, 13 Jun 2025 07:09:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=203.254.224.34 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749798597; cv=none; b=GICumwY4AVIfSJ4ARICdsSql+f8TLqd5fuaUUDN+b5BE6RheFR67bJOgh6zFV3/rRr4ST6Uei8tqyQ/jaSFo9hGFobeHcIZMP8TqoudCqcs1fQ8ZJnZ6dq1ANv2t7x5zIcmkF0LCPYu/kXWDDC0vjsGNs1WPuhGSzWEtB/owyqU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749798597; c=relaxed/simple; bh=OF9C70Op6jeQApfN9bL+aJV/Iljt+9XeMuFFHl7sZAc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:MIME-Version: Content-Type:References; b=DNcO9dtNk21Gt+42dCcSYZ2F9ei7G3AvoXLhVyZyTaYzMiTpnCOP3sFGXbSmaBFAnbVSgB4FJy6kbKMMQY7Osbl41dUPFiDG4nDOv75w3ZlT4WwNLfVRCC/ntE5Pb93utTxGQ5Fx5X5+5zBKl2x20dDDchOesFip9N0Lzq4RYDo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=dVhGyv7E; arc=none smtp.client-ip=203.254.224.34 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="dVhGyv7E" Received: from epcas5p1.samsung.com (unknown [182.195.41.39]) by mailout4.samsung.com (KnoxPortal) with ESMTP id 20250613070952epoutp0403de6877bd5f5d79ed597cfda6146314~IiIyZH5Nr2221522215epoutp04M for ; Fri, 13 Jun 2025 07:09:52 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout4.samsung.com 20250613070952epoutp0403de6877bd5f5d79ed597cfda6146314~IiIyZH5Nr2221522215epoutp04M DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1749798592; bh=/BRy9T3GJRyRf9B/1o6vliSFsXzSoe+6lNyeT9l/lCs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dVhGyv7E4bH4IcN/CvjW3XdsuoMJEplVpr43Z1rP/59ZIsI/O/UJhu+bTKVhTPglf pzHyjQ5FyMOQKFM/p63MsEj0Xx9Lj7Y2cifpxxAP6J96ePq3VKU4UzQwPYhTBPy5w3 ZbI3hheVjlEohR+YmbcVibTum7s8rhgAi1P2GxeQ= Received: from epsnrtp03.localdomain (unknown [182.195.42.155]) by epcas5p1.samsung.com (KnoxPortal) with ESMTPS id 20250613070951epcas5p1fdc2bff451059aec05b30db2383871db~IiIxZ79nR0357803578epcas5p1e; Fri, 13 Jun 2025 07:09:51 +0000 (GMT) Received: from epcas5p3.samsung.com (unknown [182.195.38.178]) by epsnrtp03.localdomain (Postfix) with ESMTP id 4bJVrs4Gtzz3hhTC; Fri, 13 Jun 2025 07:09:49 +0000 (GMT) Received: from epsmtip1.samsung.com (unknown [182.195.34.30]) by epcas5p3.samsung.com (KnoxPortal) with ESMTPA id 20250613055040epcas5p35219ddeddd9fe5f4632ca837db91847a~IhDouBZAM2143021430epcas5p3H; Fri, 13 Jun 2025 05:50:40 +0000 (GMT) Received: from bose.samsungds.net (unknown [107.108.83.9]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250613055037epsmtip108ea6972ed6eff7d92b617765eca97a2~IhDlulA8s0439404394epsmtip1N; Fri, 13 Jun 2025 05:50:37 +0000 (GMT) From: Pritam Manohar Sutar To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, andre.draszik@linaro.org, peter.griffin@linaro.org, kauschluss@disroot.org, ivo.ivanov.ivanov1@gmail.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, pritam.sutar@samsung.com Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, rosa.pila@samsung.com, dev.tailor@samsung.com, faraz.ata@samsung.com, muhammed.ali@samsung.com, selvarasu.g@samsung.com Subject: [PATCH v3 1/9] dt-bindings: phy: samsung,usb3-drd-phy: add ExynosAutov920 HS phy compatible Date: Fri, 13 Jun 2025 11:26:05 +0530 Message-Id: <20250613055613.866909-2-pritam.sutar@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250613055613.866909-1-pritam.sutar@samsung.com> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-CMS-MailID: 20250613055040epcas5p35219ddeddd9fe5f4632ca837db91847a X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-542,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250613055040epcas5p35219ddeddd9fe5f4632ca837db91847a References: <20250613055613.866909-1-pritam.sutar@samsung.com> Add a dedicated compatible string for USB HS phy found in this SoC. The devicetree node requires two clocks, named "phy" and "ref" (same as clocks required by Exynos850). Signed-off-by: Pritam Manohar Sutar --- Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml index cc60d2f6f70e..71db17d93c6a 100644 --- a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml +++ b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml @@ -33,6 +33,7 @@ properties: - samsung,exynos7-usbdrd-phy - samsung,exynos7870-usbdrd-phy - samsung,exynos850-usbdrd-phy + - samsung,exynosautov920-usbdrd-phy clocks: minItems: 1 @@ -217,6 +218,7 @@ allOf: - samsung,exynos5420-usbdrd-phy - samsung,exynos7870-usbdrd-phy - samsung,exynos850-usbdrd-phy + - samsung,exynosautov920-usbdrd-phy then: properties: clocks: From patchwork Fri Jun 13 05:56:06 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pritam Manohar Sutar X-Patchwork-Id: 896880 Received: from mailout1.samsung.com (mailout1.samsung.com [203.254.224.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA2B42749D1 for ; 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Fri, 13 Jun 2025 07:09:59 +0000 (GMT) Received: from epcas5p2.samsung.com (unknown [182.195.38.179]) by epsnrtp01.localdomain (Postfix) with ESMTP id 4bJVs13Fpgz6B9mK; Fri, 13 Jun 2025 07:09:57 +0000 (GMT) Received: from epsmtip1.samsung.com (unknown [182.195.34.30]) by epcas5p2.samsung.com (KnoxPortal) with ESMTPA id 20250613055043epcas5p2437abc65042529a2012a6ca80559ac80~IhDrqT3d-0491704917epcas5p2Q; Fri, 13 Jun 2025 05:50:43 +0000 (GMT) Received: from bose.samsungds.net (unknown [107.108.83.9]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250613055040epsmtip115c503777d2f161a8c24f72d273c3f09~IhDo8yKXL0400204002epsmtip1K; Fri, 13 Jun 2025 05:50:40 +0000 (GMT) From: Pritam Manohar Sutar To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, andre.draszik@linaro.org, peter.griffin@linaro.org, kauschluss@disroot.org, ivo.ivanov.ivanov1@gmail.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, pritam.sutar@samsung.com Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, rosa.pila@samsung.com, dev.tailor@samsung.com, faraz.ata@samsung.com, muhammed.ali@samsung.com, selvarasu.g@samsung.com Subject: [PATCH v3 2/9] phy: exyons5-usbdrd: support HS phy for ExynosAutov920 Date: Fri, 13 Jun 2025 11:26:06 +0530 Message-Id: <20250613055613.866909-3-pritam.sutar@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250613055613.866909-1-pritam.sutar@samsung.com> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-CMS-MailID: 20250613055043epcas5p2437abc65042529a2012a6ca80559ac80 X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-542,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250613055043epcas5p2437abc65042529a2012a6ca80559ac80 References: <20250613055613.866909-1-pritam.sutar@samsung.com> This SoC has a single USB 3.1 DRD combo phy that supports both UTMI+ (HS) and PIPE3 (SS) and three USB2.0 DRD HS phy controllers those only support the UTMI+ (HS) interface. Support only UTMI+ port for this SoC which is very similar to what the existing Exynos850 supports. The combo phy support is out of scope of this commit. Add required change in phy driver to support HS phy for this SoC. Signed-off-by: Pritam Manohar Sutar --- drivers/phy/samsung/phy-exynos5-usbdrd.c | 25 ++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c index 917a76d584f0..15965b4c6f78 100644 --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c @@ -2025,6 +2025,28 @@ static const struct exynos5_usbdrd_phy_drvdata exynos850_usbdrd_phy = { .n_regulators = ARRAY_SIZE(exynos5_regulator_names), }; +static const struct phy_ops exynosautov920_usbdrd_phy_ops = { + .init = exynos850_usbdrd_phy_init, + .exit = exynos850_usbdrd_phy_exit, + .owner = THIS_MODULE, +}; + +static const struct exynos5_usbdrd_phy_config phy_cfg_exynosautov920[] = { + { + .id = EXYNOS5_DRDPHY_UTMI, + .phy_init = exynos850_usbdrd_utmi_init, + }, +}; + +static const struct exynos5_usbdrd_phy_drvdata exynosautov920_usbdrd_phy = { + .phy_cfg = phy_cfg_exynosautov920, + .phy_ops = &exynosautov920_usbdrd_phy_ops, + .clk_names = exynos5_clk_names, + .n_clks = ARRAY_SIZE(exynos5_clk_names), + .core_clk_names = exynos5_core_clk_names, + .n_core_clks = ARRAY_SIZE(exynos5_core_clk_names), +}; + static const struct exynos5_usbdrd_phy_config phy_cfg_gs101[] = { { .id = EXYNOS5_DRDPHY_UTMI, @@ -2228,6 +2250,9 @@ static const struct of_device_id exynos5_usbdrd_phy_of_match[] = { }, { .compatible = "samsung,exynos850-usbdrd-phy", .data = &exynos850_usbdrd_phy + }, { + .compatible = "samsung,exynosautov920-usbdrd-phy", + .data = &exynosautov920_usbdrd_phy }, { }, }; From patchwork Fri Jun 13 05:56:07 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pritam Manohar Sutar X-Patchwork-Id: 896207 Received: from mailout1.samsung.com (mailout1.samsung.com [203.254.224.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5BFDC2749ED for ; Fri, 13 Jun 2025 07:10:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=203.254.224.24 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Fri, 13 Jun 2025 07:10:06 +0000 (GMT) Received: from epcas5p4.samsung.com (unknown [182.195.38.175]) by epsnrtp03.localdomain (Postfix) with ESMTP id 4bJVs820Bzz3hhTJ; Fri, 13 Jun 2025 07:10:04 +0000 (GMT) Received: from epsmtip1.samsung.com (unknown [182.195.34.30]) by epcas5p2.samsung.com (KnoxPortal) with ESMTPA id 20250613055047epcas5p220b1cd1e9b2819997a3d4747c395d13d~IhDupI1Ig2779327793epcas5p2o; Fri, 13 Jun 2025 05:50:47 +0000 (GMT) Received: from bose.samsungds.net (unknown [107.108.83.9]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250613055044epsmtip1cb3d9cf1276384ed10bb4cc76c671d7c~IhDr5JafY0439404394epsmtip1Q; Fri, 13 Jun 2025 05:50:43 +0000 (GMT) From: Pritam Manohar Sutar To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, andre.draszik@linaro.org, peter.griffin@linaro.org, kauschluss@disroot.org, ivo.ivanov.ivanov1@gmail.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, pritam.sutar@samsung.com Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, rosa.pila@samsung.com, dev.tailor@samsung.com, faraz.ata@samsung.com, muhammed.ali@samsung.com, selvarasu.g@samsung.com Subject: [PATCH v3 3/9] arm64: dts: exynos: ExynosAutov920: add USB and USB-phy nodes Date: Fri, 13 Jun 2025 11:26:07 +0530 Message-Id: <20250613055613.866909-4-pritam.sutar@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250613055613.866909-1-pritam.sutar@samsung.com> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-CMS-MailID: 20250613055047epcas5p220b1cd1e9b2819997a3d4747c395d13d X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-542,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250613055047epcas5p220b1cd1e9b2819997a3d4747c395d13d References: <20250613055613.866909-1-pritam.sutar@samsung.com> Add USB controller and USB PHY controller nodes for this SoC. The USB controller has following features: * Dual Role Device (DRD) controller * DWC3 compatible * Supports USB 3.0 host and USB 3.0 device interfaces but phy controller capability is limited to USB 2.0. * Supports full-speed (12 Mbps) and high-speed (480 Mbps) modes with USB device 2.0 interface * Supports on-chip USB PHY transceiver * Supports up to 16 bi-directional endpoints (that includes control endpoint 0) * Complies with xHCI 1.1 specification Signed-off-by: Pritam Manohar Sutar --- .../boot/dts/exynos/exynosautov920-sadk.dts | 37 ++++++ .../arm64/boot/dts/exynos/exynosautov920.dtsi | 108 ++++++++++++++++++ 2 files changed, 145 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts b/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts index a397f068ed53..984e899a2ebf 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts +++ b/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts @@ -86,3 +86,40 @@ &usi_0 { &xtcxo { clock-frequency = <38400000>; }; + +/* usb */ +&usbdrd20_phy0 { + status = "okay"; +}; + +&usbdrd20_dwc3_0 { + dr_mode = "peripheral"; +}; + +&usbdrd20_0 { + status = "okay"; +}; + +&usbdrd20_phy1 { + status = "okay"; +}; + +&usbdrd20_dwc3_1 { + dr_mode = "peripheral"; +}; + +&usbdrd20_1 { + status = "okay"; +}; + +&usbdrd20_phy2 { + status = "okay"; +}; + +&usbdrd20_dwc3_2 { + dr_mode = "peripheral"; +}; + +&usbdrd20_2 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi index 2cb8041c8a9f..b1a9d1da47f6 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi @@ -1048,6 +1048,114 @@ pinctrl_hsi1: pinctrl@16450000 { interrupts = ; }; + usbdrd20_phy0: phy@16500000 { + compatible = "samsung,exynosautov920-usbdrd-phy"; + reg = <0x16500000 0x0200>; + clocks = <&cmu_hsi1 CLK_MOUT_HSI1_NOC_USER>, + <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>; + clock-names = "phy", "ref"; + #phy-cells = <1>; + samsung,pmu-syscon = <&pmu_system_controller>; + status = "disabled"; + }; + + usbdrd20_phy1: phy@16510000 { + compatible = "samsung,exynosautov920-usbdrd-phy"; + reg = <0x16510000 0x0200>; + clocks = <&cmu_hsi1 CLK_MOUT_HSI1_NOC_USER>, + <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>; + clock-names = "phy", "ref"; + #phy-cells = <1>; + samsung,pmu-syscon = <&pmu_system_controller>; + status = "disabled"; + }; + + usbdrd20_phy2: phy@16520000 { + compatible = "samsung,exynosautov920-usbdrd-phy"; + reg = <0x16520000 0x0200>; + clocks = <&cmu_hsi1 CLK_MOUT_HSI1_NOC_USER>, + <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>; + clock-names = "phy", "ref"; + #phy-cells = <1>; + samsung,pmu-syscon = <&pmu_system_controller>; + status = "disabled"; + }; + + usbdrd20_0: usb@16700000 { + compatible = "samsung,exynosautov920-dwusb3"; + ranges = <0x0 0x16700000 0x10000>; + clocks = <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>, + <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>; + clock-names = "ref", "susp_clk"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + usbdrd20_dwc3_0: usb@0 { + compatible = "snps,dwc3"; + reg = <0x0 0x10000>; + clocks = <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>, + <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>; + clock-names = "ref", "susp_clk"; + interrupts = ; + phys = <&usbdrd20_phy0 0>; + phy-names = "usb2-phy"; + snps,has-lpm-erratum; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + }; + }; + + usbdrd20_1: usb@16800000 { + compatible = "samsung,exynosautov920-dwusb3"; + ranges = <0x0 0x16800000 0x10000>; + clocks = <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>, + <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>; + clock-names = "ref", "susp_clk"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + usbdrd20_dwc3_1: usb@0 { + compatible = "snps,dwc3"; + reg = <0x0 0x10000>; + clocks = <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>, + <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>; + clock-names = "ref", "susp_clk"; + interrupts = ; + phys = <&usbdrd20_phy1 0>; + phy-names = "usb2-phy"; + snps,has-lpm-erratum; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + }; + }; + + usbdrd20_2: usb@16900000 { + compatible = "samsung,exynosautov920-dwusb3"; + ranges = <0x0 0x16900000 0x10000>; + clocks = <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>, + <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>; + clock-names = "ref", "susp_clk"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + usbdrd20_dwc3_2: usb@0 { + compatible = "snps,dwc3"; + reg = <0x0 0x10000>; + clocks = <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>, + <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>; + clock-names = "ref", "susp_clk"; + interrupts = ; + phys = <&usbdrd20_phy2 0>; + phy-names = "usb2-phy"; + snps,has-lpm-erratum; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + }; + }; + pinctrl_hsi2: pinctrl@16c10000 { compatible = "samsung,exynosautov920-pinctrl"; reg = <0x16c10000 0x10000>; From patchwork Fri Jun 13 05:56:08 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pritam Manohar Sutar X-Patchwork-Id: 896879 Received: from mailout2.samsung.com (mailout2.samsung.com [203.254.224.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B758A27510B for ; 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Fri, 13 Jun 2025 07:10:12 +0000 (GMT) Received: from epcas5p2.samsung.com (unknown [182.195.38.178]) by epsnrtp02.localdomain (Postfix) with ESMTP id 4bJVsF75j8z2SSKj; Fri, 13 Jun 2025 07:10:09 +0000 (GMT) Received: from epsmtip1.samsung.com (unknown [182.195.34.30]) by epcas5p3.samsung.com (KnoxPortal) with ESMTPA id 20250613055050epcas5p3f995a6696ccf4f7eeb0b5d76382f71f7~IhDxlUrs13253332533epcas5p3P; Fri, 13 Jun 2025 05:50:50 +0000 (GMT) Received: from bose.samsungds.net (unknown [107.108.83.9]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250613055047epsmtip1f04e1592f84c83b804209cfdc697af15~IhDu36OMJ0400204002epsmtip1M; Fri, 13 Jun 2025 05:50:47 +0000 (GMT) From: Pritam Manohar Sutar To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, andre.draszik@linaro.org, peter.griffin@linaro.org, kauschluss@disroot.org, ivo.ivanov.ivanov1@gmail.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, pritam.sutar@samsung.com Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, rosa.pila@samsung.com, dev.tailor@samsung.com, faraz.ata@samsung.com, muhammed.ali@samsung.com, selvarasu.g@samsung.com Subject: [PATCH v3 4/9] dt-bindings: phy: samsung,usb3-drd-phy: add ExynosAutov920 combo HS phy Date: Fri, 13 Jun 2025 11:26:08 +0530 Message-Id: <20250613055613.866909-5-pritam.sutar@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250613055613.866909-1-pritam.sutar@samsung.com> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-CMS-MailID: 20250613055050epcas5p3f995a6696ccf4f7eeb0b5d76382f71f7 X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-542,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250613055050epcas5p3f995a6696ccf4f7eeb0b5d76382f71f7 References: <20250613055613.866909-1-pritam.sutar@samsung.com> Add a dedicated compatible string for USB combo HS phy found in this SoC. The devicetree node requires two clocks, named "phy" and "ref". This phy supports USB3.1 SSP+(10Gbps) protocol and is backwards compatible to the USB3.0 SS(5Gbps). 'Add-on USB2.0' phy is added to support USB2.0 HS(480Mbps), FS(12Mbps) and LS(1.5Mbps) data rates. These two phys are combined to form a combo phy. Add schema only for 'Add-on USB2.0' HS phy. Signed-off-by: Pritam Manohar Sutar --- Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml index 71db17d93c6a..26660799e3ca 100644 --- a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml +++ b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml @@ -33,6 +33,7 @@ properties: - samsung,exynos7-usbdrd-phy - samsung,exynos7870-usbdrd-phy - samsung,exynos850-usbdrd-phy + - samsung,exynosautov920-usbdrd-hsphy - samsung,exynosautov920-usbdrd-phy clocks: @@ -218,6 +219,7 @@ allOf: - samsung,exynos5420-usbdrd-phy - samsung,exynos7870-usbdrd-phy - samsung,exynos850-usbdrd-phy + - samsung,exynosautov920-usbdrd-hsphy - samsung,exynosautov920-usbdrd-phy then: properties: From patchwork Fri Jun 13 05:56:09 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pritam Manohar Sutar X-Patchwork-Id: 896206 Received: from mailout4.samsung.com (mailout4.samsung.com [203.254.224.34]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 713F927584D for ; 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Fri, 13 Jun 2025 07:10:17 +0000 (GMT) Received: from epcas5p3.samsung.com (unknown [182.195.38.178]) by epsnrtp01.localdomain (Postfix) with ESMTP id 4bJVsL324zz6B9mS; Fri, 13 Jun 2025 07:10:14 +0000 (GMT) Received: from epsmtip1.samsung.com (unknown [182.195.34.30]) by epcas5p3.samsung.com (KnoxPortal) with ESMTPA id 20250613055053epcas5p377269bcc2c8567c00a2298d86c0d26a4~IhD0lS1gb2142921429epcas5p3f; Fri, 13 Jun 2025 05:50:53 +0000 (GMT) Received: from bose.samsungds.net (unknown [107.108.83.9]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250613055050epsmtip139c9b199a62574ba703ee5deb54c66be~IhDx0u9U70399103991epsmtip1D; Fri, 13 Jun 2025 05:50:50 +0000 (GMT) From: Pritam Manohar Sutar To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, andre.draszik@linaro.org, peter.griffin@linaro.org, kauschluss@disroot.org, ivo.ivanov.ivanov1@gmail.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, pritam.sutar@samsung.com Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, rosa.pila@samsung.com, dev.tailor@samsung.com, faraz.ata@samsung.com, muhammed.ali@samsung.com, selvarasu.g@samsung.com Subject: [PATCH v3 5/9] phy: exyons5-usbdrd: support HS combo phy for ExynosAutov920 Date: Fri, 13 Jun 2025 11:26:09 +0530 Message-Id: <20250613055613.866909-6-pritam.sutar@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250613055613.866909-1-pritam.sutar@samsung.com> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-CMS-MailID: 20250613055053epcas5p377269bcc2c8567c00a2298d86c0d26a4 X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-542,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250613055053epcas5p377269bcc2c8567c00a2298d86c0d26a4 References: <20250613055613.866909-1-pritam.sutar@samsung.com> This SoC has a single USB 3.1 DRD combo phy that supports both UTMI+ (HS) and PIPE3 (SS) and three USB2.0 DRD HS phy controllers those only support the UTMI+ (HS) interface. Support UTMI+ combo phy for this SoC which is somewhat simmilar to what the existing Exynos850 support does. The difference is that some register offsets and bit fields are defferent from Exynos850. Add required change in phy driver to support combo HS phy for this SoC. Signed-off-by: Pritam Manohar Sutar --- drivers/phy/samsung/phy-exynos5-usbdrd.c | 202 +++++++++++++++++++++++ 1 file changed, 202 insertions(+) diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c index 15965b4c6f78..ac7bc1d1afd2 100644 --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c @@ -41,6 +41,13 @@ #define EXYNOS2200_CLKRST_LINK_PCLK_SEL BIT(1) #define EXYNOS2200_DRD_UTMI 0x10 + +/* ExynosAutov920 bits */ +#define UTMICTL_FORCE_UTMI_SUSPEND BIT(13) +#define UTMICTL_FORCE_UTMI_SLEEP BIT(12) +#define UTMICTL_FORCE_DPPULLDOWN BIT(9) +#define UTMICTL_FORCE_DMPULLDOWN BIT(8) + #define EXYNOS2200_UTMI_FORCE_VBUSVALID BIT(1) #define EXYNOS2200_UTMI_FORCE_BVALID BIT(0) @@ -250,6 +257,22 @@ #define EXYNOS850_DRD_HSP_TEST 0x5c #define HSP_TEST_SIDDQ BIT(24) +#define EXYNOSAUTOV920_DRD_HSP_CLKRST 0x100 +#define HSPCLKRST_PHY20_SW_PORTRESET BIT(3) +#define HSPCLKRST_PHY20_SW_POR BIT(1) +#define HSPCLKRST_PHY20_SW_POR_SEL BIT(0) + +#define EXYNOSAUTOV920_DRD_HSPCTL 0x104 +#define HSPCTRL_VBUSVLDEXTSEL BIT(13) +#define HSPCTRL_VBUSVLDEXT BIT(12) +#define HSPCTRL_EN_UTMISUSPEND BIT(9) +#define HSPCTRL_COMMONONN BIT(8) + +#define EXYNOSAUTOV920_DRD_HSP_TEST 0x10c + +#define EXYNOSAUTOV920_DRD_HSPPLLTUNE 0x110 +#define HSPPLLTUNE_FSEL GENMASK(18, 16) + /* Exynos9 - GS101 */ #define EXYNOS850_DRD_SECPMACTL 0x48 #define SECPMACTL_PMA_ROPLL_REF_CLK_SEL GENMASK(13, 12) @@ -2025,6 +2048,182 @@ static const struct exynos5_usbdrd_phy_drvdata exynos850_usbdrd_phy = { .n_regulators = ARRAY_SIZE(exynos5_regulator_names), }; +static void +exynosautov920_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd) +{ + void __iomem *reg_phy = phy_drd->reg_phy; + u32 reg; + + /* + * Disable HWACG (hardware auto clock gating control). This + * forces QACTIVE signal in Q-Channel interface to HIGH level, + * to make sure the PHY clock is not gated by the hardware. + */ + reg = readl(reg_phy + EXYNOS850_DRD_LINKCTRL); + reg |= LINKCTRL_FORCE_QACT; + writel(reg, reg_phy + EXYNOS850_DRD_LINKCTRL); + + /* De-assert link reset */ + reg = readl(reg_phy + EXYNOS2200_DRD_CLKRST); + reg &= ~CLKRST_LINK_SW_RST; + writel(reg, reg_phy + EXYNOS2200_DRD_CLKRST); + + /* Set PHY POR High */ + reg = readl(reg_phy + EXYNOSAUTOV920_DRD_HSP_CLKRST); + reg |= HSPCLKRST_PHY20_SW_POR | HSPCLKRST_PHY20_SW_POR_SEL; + writel(reg, reg_phy + EXYNOSAUTOV920_DRD_HSP_CLKRST); + + /* Enable UTMI+ */ + reg = readl(reg_phy + EXYNOS2200_DRD_UTMI); + reg &= ~(UTMICTL_FORCE_UTMI_SUSPEND | UTMICTL_FORCE_UTMI_SLEEP | + UTMICTL_FORCE_DPPULLDOWN | UTMICTL_FORCE_DMPULLDOWN); + writel(reg, reg_phy + EXYNOS2200_DRD_UTMI); + + /* set phy clock & control HS phy */ + reg = readl(reg_phy + EXYNOSAUTOV920_DRD_HSPCTL); + reg |= HSPCTRL_EN_UTMISUSPEND | HSPCTRL_COMMONONN; + writel(reg, reg_phy + EXYNOSAUTOV920_DRD_HSPCTL); + + usleep_range(100, 105); + + /* Set VBUS Valid and DP-Pull up control by VBUS pad usage */ + reg = readl(reg_phy + EXYNOS850_DRD_LINKCTRL); + reg |= FIELD_PREP_CONST(LINKCTRL_BUS_FILTER_BYPASS, 0xf); + writel(reg, reg_phy + EXYNOS850_DRD_LINKCTRL); + + reg = readl(reg_phy + EXYNOS2200_DRD_UTMI); + reg |= EXYNOS2200_UTMI_FORCE_VBUSVALID | EXYNOS2200_UTMI_FORCE_BVALID; + writel(reg, reg_phy + EXYNOS2200_DRD_UTMI); + + reg = readl(reg_phy + EXYNOSAUTOV920_DRD_HSPCTL); + reg |= HSPCTRL_VBUSVLDEXTSEL | HSPCTRL_VBUSVLDEXT; + writel(reg, reg_phy + EXYNOSAUTOV920_DRD_HSPCTL); + + /* Setting FSEL for refference clock */ + reg = readl(reg_phy + EXYNOSAUTOV920_DRD_HSPPLLTUNE); + reg &= ~HSPPLLTUNE_FSEL; + switch (phy_drd->extrefclk) { + case EXYNOS5_FSEL_50MHZ: + reg |= FIELD_PREP(HSPPLLTUNE_FSEL, 7); + break; + case EXYNOS5_FSEL_26MHZ: + reg |= FIELD_PREP(HSPPLLTUNE_FSEL, 6); + break; + case EXYNOS5_FSEL_24MHZ: + reg |= FIELD_PREP(HSPPLLTUNE_FSEL, 2); + break; + case EXYNOS5_FSEL_20MHZ: + reg |= FIELD_PREP(HSPPLLTUNE_FSEL, 1); + break; + case EXYNOS5_FSEL_19MHZ2: + reg |= FIELD_PREP(HSPPLLTUNE_FSEL, 0); + break; + default: + dev_warn(phy_drd->dev, "unsupported ref clk: %#.2x\n", + phy_drd->extrefclk); + break; + } + writel(reg, reg_phy + EXYNOSAUTOV920_DRD_HSPPLLTUNE); + + /* Enable PHY Power Mode */ + reg = readl(reg_phy + EXYNOSAUTOV920_DRD_HSP_TEST); + reg &= ~HSP_TEST_SIDDQ; + writel(reg, reg_phy + EXYNOSAUTOV920_DRD_HSP_TEST); + + /* before POR low, 10us delay is needed to Finish PHY reset */ + usleep_range(10, 15); + + /* Set PHY POR Low */ + reg = readl(reg_phy + EXYNOSAUTOV920_DRD_HSP_CLKRST); + reg |= HSPCLKRST_PHY20_SW_POR_SEL; + reg &= ~(HSPCLKRST_PHY20_SW_POR | HSPCLKRST_PHY20_SW_PORTRESET); + writel(reg, reg_phy + EXYNOSAUTOV920_DRD_HSP_CLKRST); + + /* after POR low and delay 75us, PHYCLOCK is guaranteed. */ + usleep_range(75, 80); + + /* force pipe3 signal for link */ + reg = readl(reg_phy + EXYNOS850_DRD_LINKCTRL); + reg |= LINKCTRL_FORCE_PIPE_EN; + reg &= ~LINKCTRL_FORCE_PHYSTATUS; + reg |= LINKCTRL_FORCE_RXELECIDLE; + writel(reg, reg_phy + EXYNOS850_DRD_LINKCTRL); +} + +static void +exynosautov920_usbdrd_hsphy_disable(struct exynos5_usbdrd_phy *phy_drd) +{ + u32 reg; + void __iomem *reg_phy = phy_drd->reg_phy; + + /* set phy clock & control HS phy */ + reg = readl(reg_phy + EXYNOS2200_DRD_UTMI); + reg |= UTMICTL_FORCE_UTMI_SUSPEND | UTMICTL_FORCE_UTMI_SLEEP; + reg &= ~(UTMICTL_FORCE_DPPULLDOWN | UTMICTL_FORCE_DMPULLDOWN); + writel(reg, reg_phy + EXYNOS2200_DRD_UTMI); + + /* Disable PHY Power Mode */ + reg = readl(reg_phy + EXYNOSAUTOV920_DRD_HSP_TEST); + reg |= HSP_TEST_SIDDQ; + writel(reg, reg_phy + EXYNOSAUTOV920_DRD_HSP_TEST); + + /* clear force q-channel */ + reg = readl(reg_phy + EXYNOS850_DRD_LINKCTRL); + reg &= ~LINKCTRL_FORCE_QACT; + writel(reg, reg_phy + EXYNOS850_DRD_LINKCTRL); + + /* link sw reset is need for USB_DP/DM high-z in host mode */ + reg = readl(reg_phy + EXYNOS2200_DRD_CLKRST); + reg |= CLKRST_LINK_SW_RST; + writel(reg, reg_phy + EXYNOS2200_DRD_CLKRST); +} + +static int exynosautov920_usbdrd_phy_init(struct phy *phy) +{ + return exynos850_usbdrd_phy_init(phy); +} + +static int exynosautov920_usbdrd_phy_exit(struct phy *phy) +{ + struct phy_usb_instance *inst = phy_get_drvdata(phy); + struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst); + int ret = 0; + + ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks); + if (ret) + return ret; + + if (inst->phy_cfg->id == EXYNOS5_DRDPHY_UTMI) + exynosautov920_usbdrd_hsphy_disable(phy_drd); + + clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks); + + return 0; +} + +static const struct phy_ops exynosautov920_usb31drd_phy_ops = { + .init = exynosautov920_usbdrd_phy_init, + .exit = exynosautov920_usbdrd_phy_exit, + .owner = THIS_MODULE, +}; + +static const struct +exynos5_usbdrd_phy_config usbdrd_hsphy_cfg_exynosautov920[] = { + { + .id = EXYNOS5_DRDPHY_UTMI, + .phy_init = exynosautov920_usbdrd_utmi_init, + }, +}; + +static const struct exynos5_usbdrd_phy_drvdata exynosautov920_usbdrd_hsphy = { + .phy_cfg = usbdrd_hsphy_cfg_exynosautov920, + .phy_ops = &exynosautov920_usb31drd_phy_ops, + .clk_names = exynos5_clk_names, + .n_clks = ARRAY_SIZE(exynos5_clk_names), + .core_clk_names = exynos5_core_clk_names, + .n_core_clks = ARRAY_SIZE(exynos5_core_clk_names), +}; + static const struct phy_ops exynosautov920_usbdrd_phy_ops = { .init = exynos850_usbdrd_phy_init, .exit = exynos850_usbdrd_phy_exit, @@ -2250,6 +2449,9 @@ static const struct of_device_id exynos5_usbdrd_phy_of_match[] = { }, { .compatible = "samsung,exynos850-usbdrd-phy", .data = &exynos850_usbdrd_phy + }, { + .compatible = "samsung,exynosautov920-usbdrd-hsphy", + .data = &exynosautov920_usbdrd_hsphy }, { .compatible = "samsung,exynosautov920-usbdrd-phy", .data = &exynosautov920_usbdrd_phy From patchwork Fri Jun 13 05:56:10 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pritam Manohar Sutar X-Patchwork-Id: 896878 Received: from mailout1.samsung.com (mailout1.samsung.com [203.254.224.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D2A81275866 for ; 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Fri, 13 Jun 2025 07:10:21 +0000 (GMT) Received: from epcas5p2.samsung.com (unknown [182.195.38.180]) by epsnrtp03.localdomain (Postfix) with ESMTP id 4bJVsR5hHWz3hhTD; Fri, 13 Jun 2025 07:10:19 +0000 (GMT) Received: from epsmtip1.samsung.com (unknown [182.195.34.30]) by epcas5p2.samsung.com (KnoxPortal) with ESMTPA id 20250613055056epcas5p29790d8086c89b16441f4b0a9c2a4db33~IhD3jMu_31695316953epcas5p2C; Fri, 13 Jun 2025 05:50:56 +0000 (GMT) Received: from bose.samsungds.net (unknown [107.108.83.9]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250613055053epsmtip1470e899e4987d1436f6f028fcb03a9cc~IhD0zla9h0400204002epsmtip1S; Fri, 13 Jun 2025 05:50:53 +0000 (GMT) From: Pritam Manohar Sutar To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, andre.draszik@linaro.org, peter.griffin@linaro.org, kauschluss@disroot.org, ivo.ivanov.ivanov1@gmail.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, pritam.sutar@samsung.com Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, rosa.pila@samsung.com, dev.tailor@samsung.com, faraz.ata@samsung.com, muhammed.ali@samsung.com, selvarasu.g@samsung.com Subject: [PATCH v3 6/9] arm64: dts: exynos: ExynosAutov920: add USB and USB HS combo phy nodes Date: Fri, 13 Jun 2025 11:26:10 +0530 Message-Id: <20250613055613.866909-7-pritam.sutar@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250613055613.866909-1-pritam.sutar@samsung.com> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-CMS-MailID: 20250613055056epcas5p29790d8086c89b16441f4b0a9c2a4db33 X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-542,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250613055056epcas5p29790d8086c89b16441f4b0a9c2a4db33 References: <20250613055613.866909-1-pritam.sutar@samsung.com> Add the USB 3.1 DRD controller and USB31DRD HS combo phy nodes for ExynosAutov920 soc. The USB 3.1 DRD controller has the following features: * DWC3 compatible * compliant with both USB device 3.1 and USB device 2.0 standards * compliant with USB host 3.1 and USB host 2.0 standards * supports USB device 3.1 and USB device 2.0 interfaces * supports USB host 3.1 and USB host 2.0 interfaces * full-speed (12 Mbps) and high-speed (480 Mbps) modes with USB device 2.0 interface * super-speed (5 Gbps) mode with USB device 3.1 Gen1 interface * super-speed plus (10 Gbps) mode with USB device 3.1 Gen2 interface * single USB port which can be used for USB 3.1 or USB 2.0 * on-chip USB PHY transceiver * supports up to 16 bi-directional endpoints * compliant with xHCI 1.1 specification Only UTMI+ is supported in this commit, so only UTMI+ PHY interface is specified in "phys" property (index 0) and PIPE3 is omitted (index 1). Signed-off-by: Pritam Manohar Sutar --- .../boot/dts/exynos/exynosautov920-sadk.dts | 12 +++++++ .../arm64/boot/dts/exynos/exynosautov920.dtsi | 36 +++++++++++++++++++ 2 files changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts b/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts index 984e899a2ebf..a21386bd9af3 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts +++ b/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts @@ -88,6 +88,18 @@ &xtcxo { }; /* usb */ +&usbdrd31_hsphy { + status = "okay"; +}; + +&usbdrd31_dwc3 { + dr_mode = "peripheral"; +}; + +&usbdrd31 { + status = "okay"; +}; + &usbdrd20_phy0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi index b1a9d1da47f6..4efc005cae80 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi @@ -1048,6 +1048,17 @@ pinctrl_hsi1: pinctrl@16450000 { interrupts = ; }; + usbdrd31_hsphy: phy@16490000 { + compatible = "samsung,exynosautov920-usbdrd-hsphy"; + reg = <0x16490000 0x0200>; + clocks = <&cmu_hsi1 CLK_MOUT_HSI1_NOC_USER>, + <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>; + clock-names = "phy", "ref"; + #phy-cells = <1>; + samsung,pmu-syscon = <&pmu_system_controller>; + status = "disabled"; + }; + usbdrd20_phy0: phy@16500000 { compatible = "samsung,exynosautov920-usbdrd-phy"; reg = <0x16500000 0x0200>; @@ -1081,6 +1092,31 @@ usbdrd20_phy2: phy@16520000 { status = "disabled"; }; + usbdrd31: usb@16600000 { + compatible = "samsung,exynosautov920-dwusb3"; + ranges = <0x0 0x16600000 0x10000>; + clocks = <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>, + <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>; + clock-names = "ref", "susp_clk"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + usbdrd31_dwc3: usb@0 { + compatible = "snps,dwc3"; + reg = <0x0 0x10000>; + clocks = <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>, + <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>; + clock-names = "ref", "susp_clk"; + interrupts = ; + phys = <&usbdrd31_hsphy 0>; + phy-names = "usb2-phy"; + snps,has-lpm-erratum; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + }; + }; + usbdrd20_0: usb@16700000 { compatible = "samsung,exynosautov920-dwusb3"; ranges = <0x0 0x16700000 0x10000>; From patchwork Fri Jun 13 05:56:11 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pritam Manohar Sutar X-Patchwork-Id: 896205 Received: from mailout3.samsung.com (mailout3.samsung.com [203.254.224.33]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 293A527586C for ; Fri, 13 Jun 2025 07:10:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=203.254.224.33 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749798633; cv=none; b=fctHysageVdNVFV4guAR8CmHmP44eYBYLJ4NV6rhGpo4yymeOFE9/mYAEcswFim8M1Pc0w74GA6gz2vee41BxhIU0+dCxS9cZm3DS+0dFbUYzIZ6+FiRYU9FkIKhCYw2uwz5tN7+nVSM+5bnkppKcUtQrwtpujix7q4yjOuADIY= ARC-Message-Signature: i=1; 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Fri, 13 Jun 2025 05:50:59 +0000 (GMT) Received: from bose.samsungds.net (unknown [107.108.83.9]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250613055056epsmtip1719e57bbf20b6d5bd9cead39b3a2f125~IhD3x2vw70398103981epsmtip1j; Fri, 13 Jun 2025 05:50:56 +0000 (GMT) From: Pritam Manohar Sutar To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, andre.draszik@linaro.org, peter.griffin@linaro.org, kauschluss@disroot.org, ivo.ivanov.ivanov1@gmail.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, pritam.sutar@samsung.com Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, rosa.pila@samsung.com, dev.tailor@samsung.com, faraz.ata@samsung.com, muhammed.ali@samsung.com, selvarasu.g@samsung.com Subject: [PATCH v3 7/9] dt-bindings: phy: samsung,usb3-drd-phy: add ExynosAutov920 combo SS phy Date: Fri, 13 Jun 2025 11:26:11 +0530 Message-Id: <20250613055613.866909-8-pritam.sutar@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250613055613.866909-1-pritam.sutar@samsung.com> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-CMS-MailID: 20250613055059epcas5p28b26f4ccb0f58e1bfb172e92f9903a08 X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-542,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250613055059epcas5p28b26f4ccb0f58e1bfb172e92f9903a08 References: <20250613055613.866909-1-pritam.sutar@samsung.com> Add a dedicated compatible string for USB combo phy found in this SoC. The devicetree node requires two clocks, named "phy" and "ref". This phy supports USB3.1 SSP+(10Gbps) protocol and is backwards compatible to the USB3.0 SS(5Gbps). 'Add-on USB2.0' phy is required to support USB2.0 HS(480Mbps), FS(12Mbps) and LS(1.5Mbps) data rates. These two phys are combined to form a combo phy. Add schema only for 'USB3.1 SSP+' SS phy in this commit. Signed-off-by: Pritam Manohar Sutar --- Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml index 26660799e3ca..5dd68c21c133 100644 --- a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml +++ b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml @@ -35,6 +35,7 @@ properties: - samsung,exynos850-usbdrd-phy - samsung,exynosautov920-usbdrd-hsphy - samsung,exynosautov920-usbdrd-phy + - samsung,exynosautov920-usb31drd-ssphy clocks: minItems: 1 @@ -221,6 +222,7 @@ allOf: - samsung,exynos850-usbdrd-phy - samsung,exynosautov920-usbdrd-hsphy - samsung,exynosautov920-usbdrd-phy + - samsung,exynosautov920-usb31drd-ssphy then: properties: clocks: From patchwork Fri Jun 13 05:56:12 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pritam Manohar Sutar X-Patchwork-Id: 896204 Received: from mailout4.samsung.com (mailout4.samsung.com [203.254.224.34]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C6CB52749DE for ; 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Fri, 13 Jun 2025 07:10:45 +0000 (GMT) Received: from epcas5p3.samsung.com (unknown [182.195.38.179]) by epsnrtp01.localdomain (Postfix) with ESMTP id 4bJVsv2sBYz6B9m4; Fri, 13 Jun 2025 07:10:43 +0000 (GMT) Received: from epsmtip1.samsung.com (unknown [182.195.34.30]) by epcas5p4.samsung.com (KnoxPortal) with ESMTPA id 20250613055102epcas5p44f66699e2e1f3896948b71819ffea181~IhD9hlF572100621006epcas5p4W; Fri, 13 Jun 2025 05:51:02 +0000 (GMT) Received: from bose.samsungds.net (unknown [107.108.83.9]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250613055059epsmtip1f1cb0bbb220bb2b1f0e38b66ecf73e45~IhD6uGDHA0439404394epsmtip11; Fri, 13 Jun 2025 05:50:59 +0000 (GMT) From: Pritam Manohar Sutar To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, andre.draszik@linaro.org, peter.griffin@linaro.org, kauschluss@disroot.org, ivo.ivanov.ivanov1@gmail.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, pritam.sutar@samsung.com Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, rosa.pila@samsung.com, dev.tailor@samsung.com, faraz.ata@samsung.com, muhammed.ali@samsung.com, selvarasu.g@samsung.com Subject: [PATCH v3 8/9] phy: exyons5-usbdrd: support SS combo phy for ExynosAutov920 Date: Fri, 13 Jun 2025 11:26:12 +0530 Message-Id: <20250613055613.866909-9-pritam.sutar@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250613055613.866909-1-pritam.sutar@samsung.com> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-CMS-MailID: 20250613055102epcas5p44f66699e2e1f3896948b71819ffea181 X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-542,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250613055102epcas5p44f66699e2e1f3896948b71819ffea181 References: <20250613055613.866909-1-pritam.sutar@samsung.com> This SoC has a DWC3 compatible link controller and single USB 3.1 DRD combo phy that supports both UTMI+ (HS) and PIPE3 (SS) and three USB2.0 DRD HS phy controllers those only support the UTMI+ (HS) interface. Combo phy is combination of two phys. Among these phys, one supports USB3.1 SSP+(10Gbps) protocol and is backwards compatible to the USB3.0 SS(5Gbps). 'Add-on USB2.0' phy is required to support USB2.0 HS(480Mbps), FS(12Mbps) and LS(1.5Mbps) data rates. Add required change in phy driver to support combo SS phy for this SoC. Signed-off-by: Pritam Manohar Sutar Reviewed-by: Neil Armstrong --- drivers/phy/samsung/phy-exynos5-usbdrd.c | 310 ++++++++++++++++++++++- 1 file changed, 306 insertions(+), 4 deletions(-) diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c index ac7bc1d1afd2..97a4f67b0958 100644 --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c @@ -273,6 +273,36 @@ #define EXYNOSAUTOV920_DRD_HSPPLLTUNE 0x110 #define HSPPLLTUNE_FSEL GENMASK(18, 16) +/* ExynosAutov920 phy usb31drd port reg */ +#define EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL 0x000 +#define PHY_RST_CTRL_PIPE_LANE0_RESET_N_OVRD_EN BIT(5) +#define PHY_RST_CTRL_PIPE_LANE0_RESET_N BIT(4) +#define PHY_RST_CTRL_PHY_RESET_OVRD_EN BIT(1) +#define PHY_RST_CTRL_PHY_RESET BIT(0) + +#define EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0 0x0004 +#define PHY_CR_PARA_CON0_PHY0_CR_PARA_ADDR GENMASK(31, 16) +#define PHY_CR_PARA_CON0_PHY0_CR_PARA_CLK BIT(8) +#define PHY_CR_PARA_CON0_PHY0_CR_PARA_ACK BIT(4) +#define PHY_CR_PARA_CON0_PHY0_CR_PARA_SEL BIT(0) + +#define EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON1 0x0008 + +#define EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON2 0x000c +#define PHY_CR_PARA_CON2_PHY0_CR_PARA_WR_EN BIT(0) +#define PHY_CR_PARA_CON2_PHY0_CR_PARA_WR_DATA GENMASK(31, 16) + +#define EXYNOSAUTOV920_USB31DRD_PHY_CONFIG0 0x100 +#define PHY_CONFIG0_PHY0_PMA_PWR_STABLE BIT(14) +#define PHY_CONFIG0_PHY0_PCS_PWR_STABLE BIT(13) +#define PHY_CONFIG0_PHY0_ANA_PWR_EN BIT(1) + +#define EXYNOSAUTOV920_USB31DRD_PHY_CONFIG7 0x11c +#define PHY_CONFIG7_PHY_TEST_POWERDOWN BIT(24) + +#define EXYNOSAUTOV920_USB31DRD_PHY_CONFIG4 0x110 +#define PHY_CONFIG4_PIPE_RX0_SRIS_MODE_EN BIT(2) + /* Exynos9 - GS101 */ #define EXYNOS850_DRD_SECPMACTL 0x48 #define SECPMACTL_PMA_ROPLL_REF_CLK_SEL GENMASK(13, 12) @@ -2048,6 +2078,237 @@ static const struct exynos5_usbdrd_phy_drvdata exynos850_usbdrd_phy = { .n_regulators = ARRAY_SIZE(exynos5_regulator_names), }; +static void +exynosautov920_usb31drd_cr_clk(struct exynos5_usbdrd_phy *phy_drd, bool high) +{ + void __iomem *reg_phy = phy_drd->reg_phy; + u32 reg = 0; + + reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0); + if (high) + reg |= PHY_CR_PARA_CON0_PHY0_CR_PARA_CLK; + else + reg &= ~PHY_CR_PARA_CON0_PHY0_CR_PARA_CLK; + + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0); + usleep_range(1, 2); +} + +static void +exynosautov920_usb31drd_port_phy_ready(struct exynos5_usbdrd_phy *phy_drd) +{ + struct device *dev = phy_drd->dev; + void __iomem *reg_phy = phy_drd->reg_phy; + static const unsigned int timeout_us = 20000; + static const unsigned int sleep_us = 40; + u32 reg = 0; + int err; + + /* Clear cr_para_con */ + reg &= ~(PHY_CR_PARA_CON0_PHY0_CR_PARA_CLK | + PHY_CR_PARA_CON0_PHY0_CR_PARA_ADDR); + reg |= PHY_CR_PARA_CON0_PHY0_CR_PARA_SEL; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0); + writel(0x0, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON1); + writel(0x0, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON2); + + exynosautov920_usb31drd_cr_clk(phy_drd, true); + exynosautov920_usb31drd_cr_clk(phy_drd, false); + + /* + * The maximum time from phy reset de-assertion to de-assertion of + * tx/rx_ack can be as high as 5ms in fast simulation mode. + * Time to phy ready is < 20ms + */ + err = readl_poll_timeout(reg_phy + + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0, + reg, !(reg & PHY_CR_PARA_CON0_PHY0_CR_PARA_ACK), + sleep_us, timeout_us); + if (err) + dev_err(dev, "timed out waiting for rx/tx_ack: %#.8x\n", reg); + + reg &= ~PHY_CR_PARA_CON0_PHY0_CR_PARA_CLK; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0); +} + +static void +exynosautov920_usb31drd_cr_write(struct exynos5_usbdrd_phy *phy_drd, + u16 addr, u16 data) +{ + struct device *dev = phy_drd->dev; + void __iomem *reg_phy = phy_drd->reg_phy; + u32 cnt = 0; + u32 reg = 0; + + /* Pre Clocking */ + reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0); + reg |= PHY_CR_PARA_CON0_PHY0_CR_PARA_SEL; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0); + + /* + * tx clks must be available prior to assertion of tx req. + * tx pstate p2 to p0 transition directly is not permitted. + * tx clk ready must be asserted synchronously on tx clk prior + * to internal transmit clk alignment sequence in the phy + * when entering from p2 to p1 to p0. + */ + do { + exynosautov920_usb31drd_cr_clk(phy_drd, true); + exynosautov920_usb31drd_cr_clk(phy_drd, false); + cnt++; + } while (cnt < 15); + + reg &= ~PHY_CR_PARA_CON0_PHY0_CR_PARA_SEL; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0); + + /* + * tx data path is active when tx lane is in p0 state + * and tx data en asserted. enable cr_para_wr_en. + */ + reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON2); + reg &= ~PHY_CR_PARA_CON2_PHY0_CR_PARA_WR_DATA; + reg |= FIELD_PREP(PHY_CR_PARA_CON2_PHY0_CR_PARA_WR_DATA, data) | + PHY_CR_PARA_CON2_PHY0_CR_PARA_WR_EN; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON2); + + /* write addr */ + reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0); + reg &= ~PHY_CR_PARA_CON0_PHY0_CR_PARA_ADDR; + reg |= FIELD_PREP(PHY_CR_PARA_CON0_PHY0_CR_PARA_ADDR, addr) | + PHY_CR_PARA_CON0_PHY0_CR_PARA_CLK | + PHY_CR_PARA_CON0_PHY0_CR_PARA_SEL; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0); + + /* check cr_para_ack*/ + cnt = 0; + do { + /* + * data symbols are captured by phy on rising edge of the + * tx_clk when tx data enabled. + * completion of the write cycle is acknowledged by assertion + * of the cr_para_ack. + */ + exynosautov920_usb31drd_cr_clk(phy_drd, true); + reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0); + if ((reg & PHY_CR_PARA_CON0_PHY0_CR_PARA_ACK)) + break; + + exynosautov920_usb31drd_cr_clk(phy_drd, false); + + /* + * wait for minimum of 10 cr_para_clk cycles after phy reset + * is negated, before accessing control regs to allow for + * internal resets. + */ + cnt++; + } while (cnt < 10); + + if (cnt == 10) + dev_dbg(dev, "CR write failed to 0x%04x\n", addr); + else + exynosautov920_usb31drd_cr_clk(phy_drd, false); +} + +static void +exynosautov920_usb31drd_phy_reset(struct exynos5_usbdrd_phy *phy_drd, int val) +{ + void __iomem *reg_phy = phy_drd->reg_phy; + u32 reg; + + reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL); + reg &= ~PHY_RST_CTRL_PHY_RESET_OVRD_EN; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL); + + reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL); + if (val) + reg |= PHY_RST_CTRL_PHY_RESET; + else + reg &= ~PHY_RST_CTRL_PHY_RESET; + + reg |= PHY_RST_CTRL_PHY_RESET_OVRD_EN; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL); +} + +static void +exynosautov920_usb31drd_lane0_reset(struct exynos5_usbdrd_phy *phy_drd, int val) +{ + void __iomem *reg_phy = phy_drd->reg_phy; + u32 reg; + + reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL); + reg |= PHY_RST_CTRL_PIPE_LANE0_RESET_N_OVRD_EN; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL); + + reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL); + if (val) + reg &= ~PHY_RST_CTRL_PIPE_LANE0_RESET_N; + else + reg |= PHY_RST_CTRL_PIPE_LANE0_RESET_N; + + reg &= ~PHY_RST_CTRL_PIPE_LANE0_RESET_N_OVRD_EN; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL); +} + +static void +exynosautov920_usb31drd_pipe3_init(struct exynos5_usbdrd_phy *phy_drd) +{ + void __iomem *reg_phy = phy_drd->reg_phy; + u32 reg; + + /* + * Phy and Pipe Lane reset assert. + * assert reset (phy_reset = 1). + * The lane-ack outputs are asserted during reset (tx_ack = rx_ack = 1) + */ + exynosautov920_usb31drd_phy_reset(phy_drd, 1); + exynosautov920_usb31drd_lane0_reset(phy_drd, 1); + + /* + * ANA Power En, PCS & PMA PWR Stable Set + * ramp-up power suppiles + */ + reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG0); + reg |= PHY_CONFIG0_PHY0_ANA_PWR_EN | PHY_CONFIG0_PHY0_PCS_PWR_STABLE | + PHY_CONFIG0_PHY0_PMA_PWR_STABLE; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG0); + + usleep_range(10, 15); + + /* + * phy is not functional in test_powerdown mode, test_powerdown to be + * de-asserted for normal operation + */ + reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG7); + reg &= ~PHY_CONFIG7_PHY_TEST_POWERDOWN; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG7); + + /* + * phy reset signal be asserted for minimum 10us after power + * supplies are ramped-up + */ + usleep_range(10, 15); + + /* + * Phy and Pipe Lane reset assert de-assert + */ + exynosautov920_usb31drd_phy_reset(phy_drd, 0); + exynosautov920_usb31drd_lane0_reset(phy_drd, 0); + + /* Pipe_rx0_sris_mode_en = 1 */ + reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG4); + reg |= PHY_CONFIG4_PIPE_RX0_SRIS_MODE_EN; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG4); + + /* + * wait for lane ack outputs to de-assert (tx_ack = rx_ack = 0) + * Exit from the reset state is indicated by de-assertion of *_ack + */ + exynosautov920_usb31drd_port_phy_ready(phy_drd); + + /* override values for level settings */ + exynosautov920_usb31drd_cr_write(phy_drd, 0x22, 0x00F5); +} + static void exynosautov920_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd) { @@ -2142,12 +2403,15 @@ exynosautov920_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd) /* after POR low and delay 75us, PHYCLOCK is guaranteed. */ usleep_range(75, 80); - /* force pipe3 signal for link */ + /* Disable forcing pipe interface */ reg = readl(reg_phy + EXYNOS850_DRD_LINKCTRL); - reg |= LINKCTRL_FORCE_PIPE_EN; - reg &= ~LINKCTRL_FORCE_PHYSTATUS; - reg |= LINKCTRL_FORCE_RXELECIDLE; + reg &= ~LINKCTRL_FORCE_PIPE_EN; writel(reg, reg_phy + EXYNOS850_DRD_LINKCTRL); + + /* Pclk to pipe_clk */ + reg = readl(reg_phy + EXYNOS2200_DRD_CLKRST); + reg |= EXYNOS2200_CLKRST_LINK_PCLK_SEL; + writel(reg, reg_phy + EXYNOS2200_DRD_CLKRST); } static void @@ -2183,6 +2447,22 @@ static int exynosautov920_usbdrd_phy_init(struct phy *phy) return exynos850_usbdrd_phy_init(phy); } +static void +exynosautov920_usb31drd_ssphy_disable(struct exynos5_usbdrd_phy *phy_drd) +{ + void __iomem *reg_phy = phy_drd->reg_phy; + u32 reg; + + /* 1. Assert reset (phy_reset = 1) */ + exynosautov920_usb31drd_lane0_reset(phy_drd, 1); + exynosautov920_usb31drd_phy_reset(phy_drd, 1); + + /* phy test power down */ + reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG7); + reg |= PHY_CONFIG7_PHY_TEST_POWERDOWN; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG7); +} + static int exynosautov920_usbdrd_phy_exit(struct phy *phy) { struct phy_usb_instance *inst = phy_get_drvdata(phy); @@ -2195,18 +2475,37 @@ static int exynosautov920_usbdrd_phy_exit(struct phy *phy) if (inst->phy_cfg->id == EXYNOS5_DRDPHY_UTMI) exynosautov920_usbdrd_hsphy_disable(phy_drd); + else if (inst->phy_cfg->id == EXYNOS5_DRDPHY_PIPE3) + exynosautov920_usb31drd_ssphy_disable(phy_drd); clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks); return 0; } +static const struct +exynos5_usbdrd_phy_config usb31drd_phy_cfg_exynosautov920[] = { + { + .id = EXYNOS5_DRDPHY_PIPE3, + .phy_init = exynosautov920_usb31drd_pipe3_init, + }, +}; + static const struct phy_ops exynosautov920_usb31drd_phy_ops = { .init = exynosautov920_usbdrd_phy_init, .exit = exynosautov920_usbdrd_phy_exit, .owner = THIS_MODULE, }; +static const struct exynos5_usbdrd_phy_drvdata exynosautov920_usb31drd_ssphy = { + .phy_cfg = usb31drd_phy_cfg_exynosautov920, + .phy_ops = &exynosautov920_usb31drd_phy_ops, + .clk_names = exynos5_clk_names, + .n_clks = ARRAY_SIZE(exynos5_clk_names), + .core_clk_names = exynos5_core_clk_names, + .n_core_clks = ARRAY_SIZE(exynos5_core_clk_names), +}; + static const struct exynos5_usbdrd_phy_config usbdrd_hsphy_cfg_exynosautov920[] = { { @@ -2455,6 +2754,9 @@ static const struct of_device_id exynos5_usbdrd_phy_of_match[] = { }, { .compatible = "samsung,exynosautov920-usbdrd-phy", .data = &exynosautov920_usbdrd_phy + }, { + .compatible = "samsung,exynosautov920-usb31drd-ssphy", + .data = &exynosautov920_usb31drd_ssphy }, { }, }; From patchwork Fri Jun 13 05:56:13 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pritam Manohar Sutar X-Patchwork-Id: 896877 Received: from mailout4.samsung.com (mailout4.samsung.com [203.254.224.34]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 75121277026 for ; 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Fri, 13 Jun 2025 07:10:32 +0000 (GMT) Received: from epcas5p3.samsung.com (unknown [182.195.38.182]) by epsnrtp01.localdomain (Postfix) with ESMTP id 4bJVsf62PLz6B9mP; Fri, 13 Jun 2025 07:10:30 +0000 (GMT) Received: from epsmtip1.samsung.com (unknown [182.195.34.30]) by epcas5p4.samsung.com (KnoxPortal) with ESMTPA id 20250613055106epcas5p46a2e5e2d6f0e8811644643f6282fd9ca~IhEAfFzbP2347523475epcas5p4Z; Fri, 13 Jun 2025 05:51:06 +0000 (GMT) Received: from bose.samsungds.net (unknown [107.108.83.9]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250613055103epsmtip1a1807f547f3c97abd09c8aaa059502d5~IhD9wSso20439404394epsmtip12; Fri, 13 Jun 2025 05:51:03 +0000 (GMT) From: Pritam Manohar Sutar To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, andre.draszik@linaro.org, peter.griffin@linaro.org, kauschluss@disroot.org, ivo.ivanov.ivanov1@gmail.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, pritam.sutar@samsung.com Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, rosa.pila@samsung.com, dev.tailor@samsung.com, faraz.ata@samsung.com, muhammed.ali@samsung.com, selvarasu.g@samsung.com Subject: [PATCH v3 9/9] arm64: dts: exynos: ExynosAutov920: add USB and USB SS combo phy nodes Date: Fri, 13 Jun 2025 11:26:13 +0530 Message-Id: <20250613055613.866909-10-pritam.sutar@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250613055613.866909-1-pritam.sutar@samsung.com> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-CMS-MailID: 20250613055106epcas5p46a2e5e2d6f0e8811644643f6282fd9ca X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-542,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250613055106epcas5p46a2e5e2d6f0e8811644643f6282fd9ca References: <20250613055613.866909-1-pritam.sutar@samsung.com> Update the USB 3.1 DRD controller and USB31DRD phy nodes to support SS combo phy for this soc. The USB 3.1 DRD controller has the following features: * DWC3 compatible * compliant with both USB device 3.1 and USB device 2.0 standards * compliant with USB host 3.1 and USB host 2.0 standards * supports USB device 3.1 and USB device 2.0 interfaces * supports USB host 3.1 and USB host 2.0 interfaces * full-speed (12 Mbps) and high-speed (480 Mbps) modes with USB device 2.0 interface * super-speed (5 Gbps) mode with USB device 3.1 Gen1 interface * super-speed plus (10 Gbps) mode with USB device 3.1 Gen2 interface * single USB port which can be used for USB 3.1 or USB 2.0 * on-chip USB PHY transceiver * supports up to 16 bi-directional endpoints * compliant with xHCI 1.1 specification USB3.1 SSP+(10Gbps) is supported in this commit and SS phy in combo phy only supports PIPE3 interface and it is added in index 0 of SS phy. UTMI+ and PIPE3 PHY interfaces are specified in "phys" property, UTMI+ (index 0 HS phy) and PIPE3 (index 0 SS phy). Signed-off-by: Pritam Manohar Sutar --- .../arm64/boot/dts/exynos/exynosautov920-sadk.dts | 4 ++++ arch/arm64/boot/dts/exynos/exynosautov920.dtsi | 15 +++++++++++++-- 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts b/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts index a21386bd9af3..40588f7c9998 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts +++ b/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts @@ -88,6 +88,10 @@ &xtcxo { }; /* usb */ +&usbdrd31_ssphy { + status = "okay"; +}; + &usbdrd31_hsphy { status = "okay"; }; diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi index 4efc005cae80..5ee7fad346b9 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi @@ -1048,6 +1048,17 @@ pinctrl_hsi1: pinctrl@16450000 { interrupts = ; }; + usbdrd31_ssphy: phy@16480000 { + compatible = "samsung,exynosautov920-usb31drd-ssphy"; + reg = <0x16480000 0x0200>; + clocks = <&cmu_hsi1 CLK_MOUT_HSI1_NOC_USER>, + <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>; + clock-names = "phy", "ref"; + #phy-cells = <1>; + samsung,pmu-syscon = <&pmu_system_controller>; + status = "disabled"; + }; + usbdrd31_hsphy: phy@16490000 { compatible = "samsung,exynosautov920-usbdrd-hsphy"; reg = <0x16490000 0x0200>; @@ -1109,8 +1120,8 @@ usbdrd31_dwc3: usb@0 { <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>; clock-names = "ref", "susp_clk"; interrupts = ; - phys = <&usbdrd31_hsphy 0>; - phy-names = "usb2-phy"; + phys = <&usbdrd31_hsphy 0>, <&usbdrd31_ssphy 0>; + phy-names = "usb2-phy", "usb3-phy"; snps,has-lpm-erratum; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk;