From patchwork Fri Jun 13 20:29:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Steve Siwinski X-Patchwork-Id: 896882 Received: from mail-qt1-f169.google.com (mail-qt1-f169.google.com [209.85.160.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 17628231832; Fri, 13 Jun 2025 20:29:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.160.169 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749846589; cv=none; b=Py/F2BBSexYPQDHJBA4jtr1/u73qRFnw+bhQScgQUP3187thDLFY1MBz+DkXpgsrP2BnAvFDZgWTkMxMSeOK2fCsc62UsPkBW7/dWsiSxabL/6qT6M8VRoDmawCeXxLOuJtY82BNYeKv+KAWsns6QFdbOADuj+va+kVuEBy2ju4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749846589; c=relaxed/simple; bh=itbcvkf06hHiTnVq1AuUrcdQlnPV+M8C1Bw+xbdlbmk=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=W8bOVvIsm7q4dgwsGJF53a2K9Ex0qPKrexUWcHjPnE1tSB2AEYHNAoOSs3DrHGLg+tbB6l2+VM71EuNBFMUo5NoW79uBqd2KQBjkgY1HsRRCXSgQtZOYuFTvIJFWnC2SaXbYLJyNbbe6xz9s7tgBWLE/f/PLOZ5jVOTCd7mk6aA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=Y45T6Xrd; arc=none smtp.client-ip=209.85.160.169 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Y45T6Xrd" Received: by mail-qt1-f169.google.com with SMTP id d75a77b69052e-476a720e806so22303041cf.0; Fri, 13 Jun 2025 13:29:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1749846587; x=1750451387; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=4VAbAcNIfIca2fO8o6BFv8OwTPHASyEPNSWgRMV8CwE=; b=Y45T6XrdIsEjX2SPeh+6KC7VbwNRgeMDoGz1NVdczs0osHr9HGmJwzYf9s1X6eUjnP bn1HhfO5t+IgZ9cxwO40zmmXilA80cHmC+DAOH7t8k60jLajD9r/CHsxj0fR9z+ba93w huNUNzAqlK1MTHk/BTq6fM2B7pgvqmy9OdQIsJwM6g3Pwwl4zmdOTJ+CYldqLfw0/zHv eYHO2cYkoSVDFmnyYn6+xs6jm7Vr2tW85SixfvhkB/OTwRI/WgTqq1puH3ojxx50II5R 0Fd3qvsv64sCo6B4MEgPH1rogR8JHVlpMRZim5raIjyarlDD0zSIx+zO/HvY9j3B4Zsv vPrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749846587; x=1750451387; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=4VAbAcNIfIca2fO8o6BFv8OwTPHASyEPNSWgRMV8CwE=; b=W9npPczV3pNN40j8MaUb7AQ/2zz7SDFWoaSNHXNuOMSnzcY3GMiqW8guDXB9KN2Iv8 9fM5BLUSkKtWI4LZFEtt7Oz+1JGBJv4qJo+0IEWVxmecEeQWoCOMXj8JlJZxKsyrsUno gIJMdlxpmuKoF2pjgS1xt9dXCa0moUJViE0uZBV1QhRzDpiHztKZ7EObXnCH++BuTamQ rpW85zusQDbvCXqP7r3wTrlgTXcpAUH0dk0pe6XxgOtgwMi5iOpa43qopSJmZMvxeakS SqnhHVpoehBKCZ023pf8Z3rHZRxJh+sQEpfHR4SN7xp+9/lWucOM6rAzqW/fUJBspQZO sfYQ== X-Forwarded-Encrypted: i=1; AJvYcCU0KvifMNC+ImFyHLHFF8nIf/6/4yNIZYTD9NvqZKFTXmnokym84bSvOYD66DtRf8tfy163+2OSvlZ7Sg==@vger.kernel.org, AJvYcCUsTw0dxG2a6ttV/jT5LIRNB4nCeLlD3Wq94LGpGwyvdi4/EVvweSvNG3ssR5vMsGuf+btxb2kMEF0WkJ8=@vger.kernel.org X-Gm-Message-State: AOJu0YxknP3wFKEqHY1Z9wwiRIVW8hPY0rW1866FoypVbMJqkom4BZT7 +zHC5v+l+QOZNEmAJA7iDfaC5OCGGkzbGYhfMtxGz1/UdgHbxQEGSu3c X-Gm-Gg: ASbGncu0VuhRhHskIDoa9/Cd4nKGRCu5b9ksVhGlO1VK9Lh/J+pJaMOft25xZJwprLk kz7QyABkyU+bY3+KzaSqVSKe8zGkxPeKuXmFN0tvUitx5BwvV/FfHHi82OikCLYmxmTbdL4ULqX a5RkhYK/gU1rfbi7Tl5bOs6ZsLn8+/KeasdD8vPcUnTZW1OSW4FVQdb2Y66eZafRWJ5o8H8ZvaR GctaTeOmJMaUJjLY5SYTjXLgIfbWKGD6+j5+QmT1FcmQur9JFKIkvr9woBEkxAjIaONN2L6gXcw CClzlMGHlcoO+xlHi+nqTf+/QiXSOhysg9dIXTcSAmRiFzoBEcCAB7oKOvjLFLD6d3uvaCr7sQR 4mUSfZTBoj1lkOe3dxZm/fPab X-Google-Smtp-Source: AGHT+IHxRiPAV0D7DboRmeFsi1aji9YCUVLyuuezxUhc5aYhotmHtvwODeGh9qZCM+rr5MHFknFXpQ== X-Received: by 2002:ac8:570a:0:b0:4a3:6cbf:1fb7 with SMTP id d75a77b69052e-4a73c55d17fmr9961171cf.20.1749846586862; Fri, 13 Jun 2025 13:29:46 -0700 (PDT) Received: from localhost.localdomain.com (sw.attotech.com. [208.69.85.34]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4a72a2c068esm21500411cf.1.2025.06.13.13.29.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Jun 2025 13:29:46 -0700 (PDT) From: Steve Siwinski X-Google-Original-From: Steve Siwinski To: mpi3mr-linuxdrv.pdl@broadcom.com Cc: gustavoars@kernel.org, James.Bottomley@HansenPartnership.com, kashyap.desai@broadcom.com, kees@kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, martin.petersen@oracle.com, prayas.patel@broadcom.com, ranjan.kumar@broadcom.com, sathya.prakash@broadcom.com, sreekanth.reddy@broadcom.com, ssiwinski@atto.com, sumit.saxena@broadcom.com, bgrove@atto.com, tdoedline@atto.com Subject: [PATCH 1/2] scsi: mpi3mr: Add ATTO vendor support and disable firmware download Date: Fri, 13 Jun 2025 16:29:40 -0400 Message-ID: <20250613202941.62114-1-ssiwinski@atto.com> X-Mailer: git-send-email 2.43.5 Precedence: bulk X-Mailing-List: linux-scsi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add support for ATTO HBAs by defining the ATTO vendor ID and adding an entry to the PCI device ID table for SAS4116-based ATTO devices. Since ATTO HBAs use specialized firmware, block firmware downloads to ATTO devices via the MPI3_FUNCTION_CI_DOWNLOAD command and return an error. Signed-off-by: Steve Siwinski --- drivers/scsi/mpi3mr/mpi/mpi30_cnfg.h | 1 + drivers/scsi/mpi3mr/mpi3mr_app.c | 9 +++++++++ drivers/scsi/mpi3mr/mpi3mr_os.c | 4 ++++ 3 files changed, 14 insertions(+) diff --git a/drivers/scsi/mpi3mr/mpi/mpi30_cnfg.h b/drivers/scsi/mpi3mr/mpi/mpi30_cnfg.h index 96401eb7e231..314eb058c12d 100644 --- a/drivers/scsi/mpi3mr/mpi/mpi30_cnfg.h +++ b/drivers/scsi/mpi3mr/mpi/mpi30_cnfg.h @@ -206,6 +206,7 @@ struct mpi3_config_page_header { #define MPI3_TEMP_SENSOR_LOCATION_OUTLET (0x2) #define MPI3_TEMP_SENSOR_LOCATION_DRAM (0x3) #define MPI3_MFGPAGE_VENDORID_BROADCOM (0x1000) +#define MPI3_MFGPAGE_VENDORID_ATTO (0x117C) #define MPI3_MFGPAGE_DEVID_SAS4116 (0x00a5) #define MPI3_MFGPAGE_DEVID_SAS5116_MPI (0x00b3) #define MPI3_MFGPAGE_DEVID_SAS5116_NVME (0x00b4) diff --git a/drivers/scsi/mpi3mr/mpi3mr_app.c b/drivers/scsi/mpi3mr/mpi3mr_app.c index f36663613950..7e2d23204e6c 100644 --- a/drivers/scsi/mpi3mr/mpi3mr_app.c +++ b/drivers/scsi/mpi3mr/mpi3mr_app.c @@ -2691,6 +2691,15 @@ static long mpi3mr_bsg_process_mpt_cmds(struct bsg_job *job) goto out; } + if (mrioc->pdev->subsystem_vendor == MPI3_MFGPAGE_VENDORID_ATTO && + mpi_header->function == MPI3_FUNCTION_CI_DOWNLOAD) { + dprint_bsg_err(mrioc, "%s: Firmware download not supported for ATTO HBA.\n", + __func__); + rval = -EPERM; + mutex_unlock(&mrioc->bsg_cmds.mutex); + goto out; + } + if (mpi_header->function == MPI3_BSG_FUNCTION_NVME_ENCAPSULATED) { nvme_fmt = mpi3mr_get_nvme_data_fmt( (struct mpi3_nvme_encapsulated_request *)mpi_req); diff --git a/drivers/scsi/mpi3mr/mpi3mr_os.c b/drivers/scsi/mpi3mr/mpi3mr_os.c index ce444efd859e..12914400660a 100644 --- a/drivers/scsi/mpi3mr/mpi3mr_os.c +++ b/drivers/scsi/mpi3mr/mpi3mr_os.c @@ -5931,6 +5931,10 @@ static const struct pci_device_id mpi3mr_pci_id_table[] = { PCI_DEVICE_SUB(MPI3_MFGPAGE_VENDORID_BROADCOM, MPI3_MFGPAGE_DEVID_SAS5116_MPI_MGMT, PCI_ANY_ID, PCI_ANY_ID) }, + { + PCI_DEVICE_SUB(MPI3_MFGPAGE_VENDORID_ATTO, + MPI3_MFGPAGE_DEVID_SAS4116, PCI_ANY_ID, PCI_ANY_ID) + }, { 0 } }; MODULE_DEVICE_TABLE(pci, mpi3mr_pci_id_table); From patchwork Fri Jun 13 20:29:41 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Steve Siwinski X-Patchwork-Id: 897285 Received: from mail-qt1-f177.google.com (mail-qt1-f177.google.com [209.85.160.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E766424DCE7; Fri, 13 Jun 2025 20:29:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.160.177 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749846592; cv=none; b=ghQ9mlfp131yBFhHSzL1H9iRTVJKEd9NFiKn/rpXgngjojPTr8UZngGxMRFT4t6NA775OZO8wPPI3E+zaKoQp1Y4CLI+OK/6SrcG0j1ki3uPNo7Ybno5IHNfWR5y47Z36twsKnCLpCypH3GxEU6ENUxYH5lKI8/GBstO96fdwlQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749846592; c=relaxed/simple; bh=2KGVYqT/gfCOhWt0pFzbq0xjb7zLZfIjGaLpQ/pxDG4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bzf/na/TCdcwpBqEp68ccY1dTqUD7xwG0D37SEExVC4/80vTmodeu5a/JS2KESzciZs2ckV8btsBYvfv3xNy71SqkRf8jEw9coGqdZTSzxXL15E3NRr/Ab1NihosXaUC0wlz3fRDgTl6+pmfn/+6KBDc6BAsKMteKZ5XBa0IaqE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=W4OGxwy9; arc=none smtp.client-ip=209.85.160.177 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="W4OGxwy9" Received: by mail-qt1-f177.google.com with SMTP id d75a77b69052e-4a43e277198so21086931cf.1; Fri, 13 Jun 2025 13:29:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1749846590; x=1750451390; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MzfX+a8a8S5RXERHw08wlqnrhGiHvVK3pm21dZrJp2s=; b=W4OGxwy9hBaLfip1VQwcVUvPk9SX7fwqPX7aqqAWZmoJlRMKHOqSIu31ktaFiQtnke C2FyExfoAyAa3FtJ98qQU6iWlyLVYgAl06fNOQTdGPFxOIdzLf+2coXBYIPnlVUvYbLe x4cRz0obrs0ARXeCX5pRpTqZFlOvnex4pAd+IFbBVDOH5OWjEAHNTtdH2E1tGePH2nrR FDWREkcgquRf6xvonDyRxGXouC27rU/GQLcrudhTsFLF1s9QH2YInslssVDr/VVxO60T T27WbzYKuW+ikw15bHnhKg5u9tv/ub9plxu3U0x47ncUpaA9XBAJGDm+uf4IW2zLyvDT wvpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749846590; x=1750451390; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MzfX+a8a8S5RXERHw08wlqnrhGiHvVK3pm21dZrJp2s=; b=VN13t+D9jNRMXKybKk8I2syAfaVV454oZpjtEL6G5gYfna3srBHncn83vxcaT+nYF6 NLHCX3wnHxH2fgErQERcvbPzujV2IOyixFM6G1Kp7VcuRFwGcqYtIxb7i+KZbGfL6hnL aYzC62IqAYh0FoJhCbhTNpmq+vvvndKF3UcsTS7WPNrtJoYzrfLdpM/Li2/ieO8sWPS9 cBOIvq1QMVhjNt9A5RmsSsSguvlcRJJSnRpTsIBToAW4EFGivXwKFl6DHH0CjS4aKMzC xTMU/0W/Mt7a8+NVpcpPlrU5112ZI5ylP0aXd5c4LrVSa7hBsCrss73h8N0F62o1cVlM 78jw== X-Forwarded-Encrypted: i=1; AJvYcCVqvOGiaMCW62pG6ohOVObBey34+fEzZgNO/JRV62/ImJSGjXxERGYNEJWtnvoBFJq0lY+dwTXUmYdrdA==@vger.kernel.org, AJvYcCWCLTjN3pK34z+vVx1ZiJIA5tSRU4tNH69aXirzlJCVZ+QQSIGeDwTo5LSPJwxiu4Pu/FGhaZ0FX0JIJO8=@vger.kernel.org X-Gm-Message-State: AOJu0Yxr8ycRjGU/IHPuDL6QgCvikyV7WOyBF1YtTj8+68viRyoKNS62 8vPxkE1NuHJiS6BylKDqQsJJ/xRr0zkpAYosi/zYcLAmP5XrpeBjvTfA X-Gm-Gg: ASbGncuv6Gc0vkbYek8W+7558w4A0xiFj82vEx+qYRj6GsyVjdpcu5cPi6F1FexW1N8 Lq1yyt7Zl8SEkhyYiOhkc2tj3Fr+epQ5J7/5nQWh+Kn4CZB3GxUNIIe+AS5hwNUe84IoihjMNax szEB4XBSSetRmA42SCbEyz/hlp3a1geyTqKany9axs9vR+qZoA1L/KK7InFPUMCs+fbGannBRDO uSrfTWJFJ64sNMgvxHtXjhA1+zyVEhoPiRxG1OBScwN9B/F57rV2iGnkdxQ7sRqNtR23C7Nyue+ 6hM10a/R/5simYTtKTigjuv3OJY/Ges5mRJm3ctrvUTSmXAzqIGj9f5ZnmaPMSF/0DzSgkjnjcI RG41U8RykvHqW6w== X-Google-Smtp-Source: AGHT+IG4kY/2+S5wiXhPgmmf040aKH9a6yXJZ5BptOmo+ia/b0fKT36DHshxldmdxIgGsy6X/Ak3xw== X-Received: by 2002:a05:622a:488:b0:4a4:3e89:d5c0 with SMTP id d75a77b69052e-4a73c4bec58mr8990401cf.12.1749846589722; Fri, 13 Jun 2025 13:29:49 -0700 (PDT) Received: from localhost.localdomain.com (sw.attotech.com. [208.69.85.34]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4a72a2c068esm21500411cf.1.2025.06.13.13.29.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Jun 2025 13:29:49 -0700 (PDT) From: Steve Siwinski X-Google-Original-From: Steve Siwinski To: mpi3mr-linuxdrv.pdl@broadcom.com Cc: gustavoars@kernel.org, James.Bottomley@HansenPartnership.com, kashyap.desai@broadcom.com, kees@kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, martin.petersen@oracle.com, prayas.patel@broadcom.com, ranjan.kumar@broadcom.com, sathya.prakash@broadcom.com, sreekanth.reddy@broadcom.com, ssiwinski@atto.com, sumit.saxena@broadcom.com, bgrove@atto.com, tdoedline@atto.com Subject: [PATCH 2/2] scsi: mpi3mr: Add initialization for ATTO 24Gb SAS HBAs Date: Fri, 13 Jun 2025 16:29:41 -0400 Message-ID: <20250613202941.62114-2-ssiwinski@atto.com> X-Mailer: git-send-email 2.43.5 In-Reply-To: <20250613202941.62114-1-ssiwinski@atto.com> References: <20250613202941.62114-1-ssiwinski@atto.com> Precedence: bulk X-Mailing-List: linux-scsi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 This patch adds initialization routines for ATTO 24Gb SAS HBAs. It introduces the ATTO NVRAM structure and functions to validate NVRAM contents. The `mpi3mr_atto_init` function is added to handle ATTO-specific controller initialization. This involves reading the ATTO SAS address from Driver Page 2 and then assigning unique device names and WWIDs to Manufacturing Page 5. Signed-off-by: Steve Siwinski --- drivers/scsi/mpi3mr/mpi3mr.h | 35 ++++ drivers/scsi/mpi3mr/mpi3mr_fw.c | 310 ++++++++++++++++++++++++++++++++ 2 files changed, 345 insertions(+) diff --git a/drivers/scsi/mpi3mr/mpi3mr.h b/drivers/scsi/mpi3mr/mpi3mr.h index 9bbc7cb98ca3..05583457ffaa 100644 --- a/drivers/scsi/mpi3mr/mpi3mr.h +++ b/drivers/scsi/mpi3mr/mpi3mr.h @@ -1438,6 +1438,35 @@ struct delayed_evt_ack_node { u32 event_ctx; }; +/* + * struct ATTO_SAS_NVRAM - ATTO NVRAM settings + * @signature: ATTO NVRAM signature + * @version: ATTO NVRAM version + * @checksum: NVRAM checksum + * @sasaddr: ATTO SAS address + */ +struct ATTO_SAS_NVRAM { + u8 signature[4]; + u8 version; +#define ATTO_SASNVR_VERSION 0 + + u8 checksum; +#define ATTO_SASNVR_CKSUM_SEED 0x5A + u8 pad[10]; + u8 sasaddr[8]; +#define ATTO_SAS_ADDR_ALIGN 64 + u8 reserved[232]; +}; + +#define ATTO_SAS_ADDR_DEVNAME_BIAS 63 + +union ATTO_SAS_ADDRESS { + u8 b[8]; + u16 w[4]; + u32 d[2]; + u64 q; +}; + int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc); void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc); int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc); @@ -1533,10 +1562,16 @@ int mpi3mr_cfg_get_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc, struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz); int mpi3mr_cfg_set_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc, struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz); +int mpi3mr_cfg_get_man_pg5(struct mpi3mr_ioc *mrioc, + struct mpi3_man_page5 *man_pg5, u16 pg_sz); +int mpi3mr_cfg_set_man_pg5(struct mpi3mr_ioc *mrioc, + struct mpi3_man_page5 *man_pg5, u16 pg_sz); int mpi3mr_cfg_get_driver_pg1(struct mpi3mr_ioc *mrioc, struct mpi3_driver_page1 *driver_pg1, u16 pg_sz); int mpi3mr_cfg_get_driver_pg2(struct mpi3mr_ioc *mrioc, struct mpi3_driver_page2 *driver_pg2, u16 pg_sz, u8 page_type); +int mpi3mr_cfg_get_page_size(struct mpi3mr_ioc *mrioc, + int page_type, int page_num); u8 mpi3mr_is_expander_device(u16 device_info); int mpi3mr_expander_add(struct mpi3mr_ioc *mrioc, u16 handle); diff --git a/drivers/scsi/mpi3mr/mpi3mr_fw.c b/drivers/scsi/mpi3mr/mpi3mr_fw.c index 1d7901a8f0e4..c0177ad3d200 100644 --- a/drivers/scsi/mpi3mr/mpi3mr_fw.c +++ b/drivers/scsi/mpi3mr/mpi3mr_fw.c @@ -4203,6 +4203,163 @@ static int mpi3mr_enable_events(struct mpi3mr_ioc *mrioc) return retval; } +/** + * mpi3mr_atto_validate_nvram - validate the ATTO nvram + * + * @mrioc: Adapter instance reference + * @nvram: ptr to the ATTO nvram structure + * Return: 0 for success, non-zero for failure. + */ +static int mpi3mr_atto_validate_nvram(struct mpi3mr_ioc *mrioc, struct ATTO_SAS_NVRAM *nvram) +{ + int r = -EINVAL; + union ATTO_SAS_ADDRESS *sasaddr; + u32 len; + u8 *pb; + u8 cksum; + + /* validate nvram checksum */ + pb = (u8 *) nvram; + cksum = ATTO_SASNVR_CKSUM_SEED; + len = sizeof(struct ATTO_SAS_NVRAM); + + while (len--) + cksum = cksum + pb[len]; + + if (cksum) { + ioc_err(mrioc, "Invalid ATTO NVRAM checksum\n"); + return r; + } + + sasaddr = (union ATTO_SAS_ADDRESS *) nvram->sasaddr; + + if (nvram->signature[0] != 'E' + || nvram->signature[1] != 'S' + || nvram->signature[2] != 'A' + || nvram->signature[3] != 'S') + ioc_err(mrioc, "Invalid ATTO NVRAM signature\n"); + else if (nvram->version > ATTO_SASNVR_VERSION) + ioc_info(mrioc, "Invalid ATTO NVRAM version"); + else if ((nvram->sasaddr[7] & (ATTO_SAS_ADDR_ALIGN - 1)) + || sasaddr->b[0] != 0x50 + || sasaddr->b[1] != 0x01 + || sasaddr->b[2] != 0x08 + || (sasaddr->b[3] & 0xF0) != 0x60 + || ((sasaddr->b[3] & 0x0F) | le32_to_cpu(sasaddr->d[1])) == 0) { + ioc_err(mrioc, "Invalid ATTO SAS address\n"); + } else + r = 0; + return r; +} + +/** + * mpi3mr_atto_get_sas_addr - get the ATTO SAS address from driver page 2 + * + * @mrioc: Adapter instance reference + * @*sas_address: return sas address + * Return: 0 for success, non-zero for failure. + */ +static int mpi3mr_atto_get_sas_addr(struct mpi3mr_ioc *mrioc, union ATTO_SAS_ADDRESS *sas_address) +{ + struct mpi3_driver_page2 *driver_pg2 = NULL; + struct ATTO_SAS_NVRAM *nvram; + u16 sz; + int r; + __be64 addr; + + sz = mpi3mr_cfg_get_page_size(mrioc, MPI3_CONFIG_PAGETYPE_DRIVER, 2); + driver_pg2 = kzalloc(sz, GFP_KERNEL); + if (!driver_pg2) + goto out; + + r = mpi3mr_cfg_get_driver_pg2(mrioc, driver_pg2, sz, MPI3_CONFIG_ACTION_READ_PERSISTENT); + if (r) + goto out; + + nvram = (struct ATTO_SAS_NVRAM *) &driver_pg2->trigger; + + r = mpi3mr_atto_validate_nvram(mrioc, nvram); + if (r) + goto out; + + addr = *((__be64 *) nvram->sasaddr); + sas_address->q = cpu_to_le64(be64_to_cpu(addr)); + +out: + kfree(driver_pg2); + return r; +} + +/** + * mpi3mr_atto_init - Initialize the controller + * @mrioc: Adapter instance reference + * + * This the ATTO controller initialization routine + * + * Return: 0 on success and non-zero on failure. + */ +static int mpi3mr_atto_init(struct mpi3mr_ioc *mrioc) +{ + int i, bias = 0; + u16 sz; + struct mpi3_sas_io_unit_page0 *sas_io_unit_pg0 = NULL; + struct mpi3_man_page5 *man_pg5 = NULL; + union ATTO_SAS_ADDRESS base_address; + union ATTO_SAS_ADDRESS dev_address; + union ATTO_SAS_ADDRESS sas_address; + + sz = mpi3mr_cfg_get_page_size(mrioc, MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT, 0); + sas_io_unit_pg0 = kzalloc(sz, GFP_KERNEL); + if (!sas_io_unit_pg0) + goto out; + + if (mpi3mr_cfg_get_sas_io_unit_pg0(mrioc, sas_io_unit_pg0, sz)) { + ioc_err(mrioc, "failure at %s:%d/%s()!\n", + __FILE__, __LINE__, __func__); + goto out; + } + + sz = mpi3mr_cfg_get_page_size(mrioc, MPI3_CONFIG_PAGETYPE_MANUFACTURING, 5); + man_pg5 = kzalloc(sz, GFP_KERNEL); + if (!man_pg5) + goto out; + + if (mpi3mr_cfg_get_man_pg5(mrioc, man_pg5, sz)) { + ioc_err(mrioc, "failure at %s:%d/%s()!\n", + __FILE__, __LINE__, __func__); + goto out; + } + + mpi3mr_atto_get_sas_addr(mrioc, &base_address); + + dev_address.q = base_address.q; + dev_address.b[0] += ATTO_SAS_ADDR_DEVNAME_BIAS; + + for (i = 0; i < man_pg5->num_phys; i++) { + if (sas_io_unit_pg0->phy_data[i].phy_flags & + (MPI3_SASIOUNIT0_PHYFLAGS_HOST_PHY | + MPI3_SASIOUNIT0_PHYFLAGS_VIRTUAL_PHY)) + continue; + + sas_address.q = base_address.q; + sas_address.b[0] += bias++; + + man_pg5->phy[i].device_name = dev_address.q; + man_pg5->phy[i].ioc_wwid = sas_address.q; + man_pg5->phy[i].sata_wwid = sas_address.q; + } + + if (mpi3mr_cfg_set_man_pg5(mrioc, man_pg5, sz)) + ioc_info(mrioc, "ATTO set manufacuring page 5 failed\n"); + +out: + kfree(sas_io_unit_pg0); + kfree(man_pg5); + + return 0; +} + + /** * mpi3mr_init_ioc - Initialize the controller * @mrioc: Adapter instance reference @@ -4376,6 +4533,9 @@ int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc) goto out_failed; } + if (mrioc->pdev->subsystem_vendor == MPI3_MFGPAGE_VENDORID_ATTO) + mpi3mr_atto_init(mrioc); + ioc_info(mrioc, "controller initialization completed successfully\n"); return retval; out_failed: @@ -6293,6 +6453,118 @@ int mpi3mr_cfg_set_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc, return -1; } +/** + * mpi3mr_cfg_get_man_pg5 - Read manufacturing page 5 + * @mrioc: Adapter instance reference + * @io_unit_pg5: Pointer to the manufacturing page 5 to read + * @pg_sz: Size of the memory allocated to the page pointer + * + * This is handler for config page read of manufacturing + * page 5. + * + * Return: 0 on success, non-zero on failure. + */ +int mpi3mr_cfg_get_man_pg5(struct mpi3mr_ioc *mrioc, + struct mpi3_man_page5 *man_pg5, u16 pg_sz) +{ + struct mpi3_config_page_header cfg_hdr; + struct mpi3_config_request cfg_req; + u16 ioc_status = 0; + + memset(man_pg5, 0, pg_sz); + memset(&cfg_hdr, 0, sizeof(cfg_hdr)); + memset(&cfg_req, 0, sizeof(cfg_req)); + + cfg_req.function = MPI3_FUNCTION_CONFIG; + cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; + cfg_req.page_type = MPI3_CONFIG_PAGETYPE_MANUFACTURING; + cfg_req.page_number = 5; + cfg_req.page_address = 0; + + if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, + MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { + ioc_err(mrioc, "manufacturing page5 header read failed\n"); + goto out_failed; + } + if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { + ioc_err(mrioc, "manufacturing page5 header read failed with ioc_status(0x%04x)\n", + ioc_status); + goto out_failed; + } + + cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT; + + if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, + MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, man_pg5, pg_sz)) { + ioc_err(mrioc, "manufacturing page5 read failed\n"); + goto out_failed; + } + if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { + ioc_err(mrioc, "manufacturing page5 read failed with ioc_status(0x%04x)\n", + ioc_status); + goto out_failed; + } + return 0; +out_failed: + return -1; +} + +/** + * mpi3mr_cfg_set_man_pg5 - Write manufacturing page 5 + * @mrioc: Adapter instance reference + * @io_unit_pg5: Pointer to the manufacturing page 5 to write + * @pg_sz: Size of the memory allocated to the page pointer + * + * This is handler for config page write for manufacturing + * page 5. This will modify only the current page. + * + * Return: 0 on success, non-zero on failure. + */ +int mpi3mr_cfg_set_man_pg5(struct mpi3mr_ioc *mrioc, + struct mpi3_man_page5 *man_pg5, u16 pg_sz) +{ + struct mpi3_config_page_header cfg_hdr; + struct mpi3_config_request cfg_req; + u16 ioc_status = 0; + + memset(&cfg_hdr, 0, sizeof(cfg_hdr)); + memset(&cfg_req, 0, sizeof(cfg_req)); + + cfg_req.function = MPI3_FUNCTION_CONFIG; + cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; + cfg_req.page_type = MPI3_CONFIG_PAGETYPE_MANUFACTURING; + cfg_req.page_number = 5; + cfg_req.page_address = 0; + + if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, + MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { + ioc_err(mrioc, "manufacturing page5 header read failed\n"); + goto out_failed; + } + if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { + ioc_err(mrioc, "manufacturing page5 header read failed with ioc_status(0x%04x)\n", + ioc_status); + goto out_failed; + } + + cfg_req.action = MPI3_CONFIG_ACTION_WRITE_CURRENT; + + if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, + MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, man_pg5, pg_sz)) { + ioc_err(mrioc, "manufacturing page5 write failed\n"); + goto out_failed; + } + if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { + ioc_err(mrioc, "manufacturing page5 write failed with ioc_status(0x%04x)\n", + ioc_status); + goto out_failed; + } + + return 0; +out_failed: + return -1; +} + /** * mpi3mr_cfg_get_driver_pg1 - Read current Driver page1 * @mrioc: Adapter instance reference @@ -6409,3 +6681,41 @@ int mpi3mr_cfg_get_driver_pg2(struct mpi3mr_ioc *mrioc, return -1; } +/** + * mpi3mr_cfg_get_page_size - Get the size of requested page + * @mrioc: Adapter instance reference + * @page_type: Page type (MPI3_CONFIG_PAGETYPE_XXX) + * @page_num: Page number + * + * Return the specified config page size in bytes. + * + * Return: Page size in bytes, -1 on failure. + */ +int mpi3mr_cfg_get_page_size(struct mpi3mr_ioc *mrioc, int page_type, int page_num) +{ + struct mpi3_config_page_header cfg_hdr; + struct mpi3_config_request cfg_req; + u16 ioc_status = 0; + + memset(&cfg_hdr, 0, sizeof(cfg_hdr)); + memset(&cfg_req, 0, sizeof(cfg_req)); + + cfg_req.function = MPI3_FUNCTION_CONFIG; + cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; + cfg_req.page_type = page_type; + cfg_req.page_number = page_num; + cfg_req.page_address = 0; + + if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, + MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { + ioc_err(mrioc, "header read failed\n"); + return -1; + } + if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { + ioc_err(mrioc, "header read failed with ioc_status(0x%04x)\n", + ioc_status); + return -1; + } + + return cfg_hdr.page_length * 4; +}