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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BY1PEPF0001AE18.mail.protection.outlook.com (10.167.242.100) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8835.15 via Frontend Transport; Mon, 16 Jun 2025 07:43:27 +0000 Received: from SATLEXMB05.amd.com (10.181.40.146) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 16 Jun 2025 02:43:26 -0500 Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB05.amd.com (10.181.40.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 16 Jun 2025 02:43:25 -0500 Received: from localhost (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39 via Frontend Transport; Mon, 16 Jun 2025 02:43:25 -0500 From: Michal Simek To: , , , CC: Xu Yilun , Bartosz Golaszewski , "Conor Dooley" , Krzysztof Kozlowski , Linus Walleij , Moritz Fischer , Rob Herring , Shubhrajyoti Datta , Srinivas Neeli , "Tom Rix" , Wu Hao , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "moderated list:ARM/ZYNQ ARCHITECTURE" , "open list:FPGA MANAGER FRAMEWORK" , "open list:GPIO SUBSYSTEM" Subject: [PATCH v3] dt-bindings: gpio: gpio-xilinx: Mark clocks as required property Date: Mon, 16 Jun 2025 09:43:18 +0200 Message-ID: <94151cfbcff5e4ae05894981c7e398b605d4b00a.1750059796.git.michal.simek@amd.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(376014)(7416014)(82310400026)(36860700013)(1800799024)(13003099007); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jun 2025 07:43:27.4166 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: baa66390-5dbb-4d38-f85a-08ddaca97b59 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BY1PEPF0001AE18.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5645 On Microblaze platforms there is no need to handle clocks because the system is starting with clocks enabled (can be described via fixed clock node or clock-frequency property or not described at all). With using soft IPs with SOC platforms there is mandatory to handle clocks as is explained in commit 60dbdc6e08d6 ("dt-bindings: net: emaclite: Add clock support"). That's why make clock as required in dt binding because it is present in both configurations and should be described even there is no way how to handle it on Microblaze systems. There is also need to describe missing axi gpio clock in fpga-region.yaml not to introduce new error when make dt_binding_check runs. Signed-off-by: Michal Simek Reviewed-by: Xu Yilun # fpga --- Changes in v3: - Squash 2 patches from series 2 together and update commit to cover it. Changes in v2: - Add fpga region patch to fix issue which was introduces by this change - New patch to fix reported as issue by the second patch - https://lore.kernel.org/r/174954437576.4177094.15371626866789542129.robh@kernel.org Based on discussion at https://lore.kernel.org/lkml/20241002-revivable-crummy-f780adec538c@spud/ Actually this shouldn't be only targetting GPIO but also for example xlnx,xps-timebase-wdt-1.00.a but I would like to check it first on gpio before starting to check other bindings. --- Documentation/devicetree/bindings/fpga/fpga-region.yaml | 1 + Documentation/devicetree/bindings/gpio/xlnx,gpio-xilinx.yaml | 1 + 2 files changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/fpga/fpga-region.yaml b/Documentation/devicetree/bindings/fpga/fpga-region.yaml index 77554885a6c4..7d2d3b7aa4b7 100644 --- a/Documentation/devicetree/bindings/fpga/fpga-region.yaml +++ b/Documentation/devicetree/bindings/fpga/fpga-region.yaml @@ -316,6 +316,7 @@ examples: reg = <0x40000000 0x10000>; gpio-controller; #gpio-cells = <2>; + clocks = <&clk>; }; }; diff --git a/Documentation/devicetree/bindings/gpio/xlnx,gpio-xilinx.yaml b/Documentation/devicetree/bindings/gpio/xlnx,gpio-xilinx.yaml index 8fbf12ca067e..7af4eb2d1858 100644 --- a/Documentation/devicetree/bindings/gpio/xlnx,gpio-xilinx.yaml +++ b/Documentation/devicetree/bindings/gpio/xlnx,gpio-xilinx.yaml @@ -117,6 +117,7 @@ properties: required: - reg - compatible + - clocks - gpio-controller - "#gpio-cells"