From patchwork Mon Jun 16 16:38:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anand Moon X-Patchwork-Id: 897487 Received: from mail-pg1-f182.google.com (mail-pg1-f182.google.com [209.85.215.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9997E287508; Mon, 16 Jun 2025 16:39:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750091943; cv=none; b=blW3P5fUgS9FK7IS1JNXR9HZ/2rpmEOKIyydwmIhbwJ0a/Iy3r/yBHHHVfPohZ0EO3lwxgKgQwf/g8E6snMvwtXG8vapbpYbuCQ76gR8B8PbawnRSv63ZVXckwXVxX0VZU+7VfjB/YLReM8rMRT9OrgVUtSKYlVHdIe+urSyqcE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750091943; c=relaxed/simple; bh=JHwI4bSXu2TwYqi6AtexeppNIMEdlznZcrt0pgVx8Ww=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=j7NEi2nqjTrauyZNXD6a57MGgFxIIxpwsWyNzsAsRdeZe217gHt9YnMOZ0V0oOcq+jwD//17R1SZrFQ3gtxF11vFoVNPJXTsgGM7uUqnpTNwoQVZOl4fB4At9w/boXnu2a8XUevi5jcxXHm/C6Je47+Nr9zDpvKdOsIbNzIwd7s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=KaoFuEBX; arc=none smtp.client-ip=209.85.215.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="KaoFuEBX" Received: by mail-pg1-f182.google.com with SMTP id 41be03b00d2f7-b3182c6d03bso2951915a12.0; Mon, 16 Jun 2025 09:39:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1750091941; x=1750696741; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VpVHF9b+TYLO9CyHvJ3z28yz3dh71Y+srhHA13+SNnY=; b=KaoFuEBXV7fFbtLGki2YTZDM+CNEnlahO0A0wE09Luf2gVG1G+Ml9O8BewD0yNd4Kw Kq63qmoqfyUukBDBNqsyDxREnGgoZzhTMdQrmoyHBI9yGKrJ/VqEwbcx0lag28FL9kki WZIOBkcBkIWA5NVRI8B/Xwt5tvcUlXvlukWpMO/lPIv7TPqjIw3XIjLqu8XZXl5uoGt8 rE+lOUQN859gcli1oWg3gsnf/mGFyUmnQgiGzLQK9SvH5IWVA5yxWpFNth5nDM0VJrAo zIPDVRrV6sCuEHc1L5WWVh4iyuv2fOTJuHHmkxOx9AtTUpBvLrRvtarNSzzkWKK9P4yv GzeQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750091941; x=1750696741; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VpVHF9b+TYLO9CyHvJ3z28yz3dh71Y+srhHA13+SNnY=; b=ZD5RarQDwQCvdQMR0bp925k6G2LWre5a4DsJzla6pRfRMvRtUCWd4BVeMworWRp+tR SdCS2v3yzCIAXPigkIER2GOdRuHC2VYBVVKLEINKWzwAa11QYlxHP5BeAIW+5Bb8QIs7 jGuZ74yfFtpiaM9WYstS9bdOJEz6b+maqxWRqj2ocviLu5vDqkdeCFh23NM43Kv9HoqV rbmgJzEujebeiTBmn5V1VO179zdU0s6erUsoRjvN9KcZIX1WXzYto+oFeJ+NCsPDXuCa a7eVEnIa4GUaXLqOamTX1WbwEpSSImu35MxsqtQcR4AMJhlcefey4TbfcCccmG3R4r8S Vjeg== X-Forwarded-Encrypted: i=1; AJvYcCUnzDhY/D9EWTcnKdddRc1wFplz+/BzxHmBgGFCBHdIH1j18Mozfwt7nY9lbevGDuGq7YDB7VIudykLr/SiZWGiiHU=@vger.kernel.org, AJvYcCWLcb5FWpB4estUx9cuWrTwVQ6iexiNlAAEP44RGdpBodoqtmjIYX7uAEM3WhyhRZwEVV/0Nly/5EFDQpA=@vger.kernel.org, AJvYcCXHkgjjFhJVxpSYt9VRF2NjTUjBRwvFghJVel8vLbn3s/OyEHq54OXtpZGVZLOiPQzG6Q9YZkIEWu0=@vger.kernel.org X-Gm-Message-State: AOJu0YwAaUIC2MHGLwXUvVyU3qSWY0rXnsTmrlt9wq0TQ3lV6hFqVXfY ZS6Vxe6bLLtqny9HsHsXihB/IClAKc9hPqvTpkl1ZAdMLLaQG6kENfk1 X-Gm-Gg: ASbGnctmIZZTtf0dKOx3ZLgM86uh2+57wx2T7yEUs1xbfMwTbxBxz88ccgMI7j7Xm59 mdSLK080h6Fof/21/Y+iYQgVYQ0xfOaOZsGz0Y+02qDowreGuLl/0KVXKAkB87xjN78rOhy/K3I R1hk6heGTtAdvxQAs6vyVdaTeSekWi6CUJBGGzmW4R0hWNT8lbpH4FHz97U09Toxf23hxyWJ+O3 rUUB4zCPjM6U6IoAELEzP8zNzTFT9Jb65sJcfQOQSG3pIzKMggstiW2AdKx1FA/IOcxwoUj8i/Y mG2o/vJSIDvI1ViL7X1UmkzT9UrYXOLlge8uzgbcqG3ChQPPhZvqxaytIfKbyTyzHe+j1+A8wYp xjnHfuBj77Q== X-Google-Smtp-Source: AGHT+IHksnpc6Nrc2cLyvfXLBdusiyK6+4cw/aWIy5ueWnJxdLHpYjX6PbGSrX/CQnj0tbplZYI92Q== X-Received: by 2002:a05:6a20:a115:b0:218:c01:ddce with SMTP id adf61e73a8af0-21fbd5d90aemr16898139637.40.1750091940932; Mon, 16 Jun 2025 09:39:00 -0700 (PDT) Received: from localhost.localdomain ([45.112.0.181]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b2fe1680c6asm6067882a12.42.2025.06.16.09.38.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Jun 2025 09:39:00 -0700 (PDT) From: Anand Moon To: Bartlomiej Zolnierkiewicz , Krzysztof Kozlowski , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Alim Akhtar , linux-pm@vger.kernel.org (open list:SAMSUNG THERMAL DRIVER), linux-samsung-soc@vger.kernel.org (open list:SAMSUNG THERMAL DRIVER), linux-arm-kernel@lists.infradead.org (moderated list:ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES), linux-kernel@vger.kernel.org (open list) Cc: Anand Moon Subject: [RRC v1 1/3] thermal/drivers/exynos: Remove unused base_second mapping and references Date: Mon, 16 Jun 2025 22:08:22 +0530 Message-ID: <20250616163831.8138-2-linux.amoon@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250616163831.8138-1-linux.amoon@gmail.com> References: <20250616163831.8138-1-linux.amoon@gmail.com> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Following change removes the base_second field eliminates its mapping in exynos_map_dt_data(), and updates the TRIMINFO access logic in exynos4412_tmu_initialize() to use base for both Exynos5420 and Exynos5420_TRIMINFO SoCs, as base_second is not used further in in this code. This cleanup simplifies the code and reduces unnecessary memory mapping. Signed-off-by: Anand Moon --- drivers/thermal/samsung/exynos_tmu.c | 20 +++++--------------- 1 file changed, 5 insertions(+), 15 deletions(-) diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c index 47a99b3c5395..c625eddcb9f3 100644 --- a/drivers/thermal/samsung/exynos_tmu.c +++ b/drivers/thermal/samsung/exynos_tmu.c @@ -139,12 +139,11 @@ enum soc_type { * struct exynos_tmu_data : A structure to hold the private data of the TMU * driver * @base: base address of the single instance of the TMU controller. - * @base_second: base address of the common registers of the TMU controller. * @irq: irq number of the TMU controller. * @soc: id of the SOC type. * @lock: lock to implement synchronization. * @clk: pointer to the clock structure. - * @clk_sec: pointer to the clock structure for accessing the base_second. + * @clk_sec: pointer to the clock structure for accessing the gpu clk. * @sclk: pointer to the clock structure for accessing the tmu special clk. * @cal_type: calibration type for temperature * @efuse_value: SoC defined fuse value @@ -172,7 +171,6 @@ enum soc_type { */ struct exynos_tmu_data { void __iomem *base; - void __iomem *base_second; int irq; enum soc_type soc; struct mutex lock; @@ -460,12 +458,11 @@ static void exynos4412_tmu_initialize(struct platform_device *pdev) } /* On exynos5420 the triminfo register is in the shared space */ - if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO) - trim_info = readl(data->base_second + EXYNOS_TMU_REG_TRIMINFO); - else + if (data->soc == SOC_ARCH_EXYNOS5420 || + data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO) { trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO); - - sanitize_temp_error(data, trim_info); + sanitize_temp_error(data, trim_info); + } } static void exynos5433_tmu_set_low_temp(struct exynos_tmu_data *data, u8 temp) @@ -964,13 +961,6 @@ static int exynos_map_dt_data(struct platform_device *pdev) return -ENODEV; } - data->base_second = devm_ioremap(&pdev->dev, res.start, - resource_size(&res)); - if (!data->base_second) { - dev_err(&pdev->dev, "Failed to ioremap memory\n"); - return -ENOMEM; - } - return 0; } From patchwork Mon Jun 16 16:38:23 2025 Content-Type: text/plain; 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Mon, 16 Jun 2025 09:39:09 -0700 (PDT) Received: from localhost.localdomain ([45.112.0.181]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b2fe1680c6asm6067882a12.42.2025.06.16.09.39.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Jun 2025 09:39:08 -0700 (PDT) From: Anand Moon To: Bartlomiej Zolnierkiewicz , Krzysztof Kozlowski , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Alim Akhtar , linux-pm@vger.kernel.org (open list:SAMSUNG THERMAL DRIVER), linux-samsung-soc@vger.kernel.org (open list:SAMSUNG THERMAL DRIVER), linux-arm-kernel@lists.infradead.org (moderated list:ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES), linux-kernel@vger.kernel.org (open list) Cc: Anand Moon Subject: [RRC v1 2/3] thermal/drivers/exynos: Handle temperature threshold interrupts and clear corresponding IRQs Date: Mon, 16 Jun 2025 22:08:23 +0530 Message-ID: <20250616163831.8138-3-linux.amoon@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250616163831.8138-1-linux.amoon@gmail.com> References: <20250616163831.8138-1-linux.amoon@gmail.com> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 As per the Exynos TMU user manual the interrupt status register, maps the active rising and falling edges of interrupt to the appropriate clear bit, and writes it to the interrupt clear register to acknowledge and clear the interrupt. This ensures that only the relevant interrupt is cleared and allows the system to respond appropriately to thermal events. As per the comment Exynos4210 doesn't support FALL IRQs at all. So add the check accordingly. Signed-off-by: Anand Moon --- drivers/thermal/samsung/exynos_tmu.c | 48 ++++++++++++++++++++++------ 1 file changed, 38 insertions(+), 10 deletions(-) diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c index c625eddcb9f3..b7522b7b1230 100644 --- a/drivers/thermal/samsung/exynos_tmu.c +++ b/drivers/thermal/samsung/exynos_tmu.c @@ -70,6 +70,20 @@ #define EXYNOS_EMUL_DATA_MASK 0xFF #define EXYNOS_EMUL_ENABLE 0x1 +#define INTSTAT_FALL2 BIT(24) +#define INTSTAT_FALL1 BIT(20) +#define INTSTAT_FALL0 BIT(16) +#define INTSTAT_RISE2 BIT(8) +#define INTSTAT_RISE1 BIT(4) +#define INTSTAT_RISE0 BIT(0) + +#define INTCLEAR_FALL2 BIT(24) +#define INTCLEAR_FALL1 BIT(20) +#define INTCLEAR_FALL0 BIT(16) +#define INTCLEAR_RISE2 BIT(8) +#define INTCLEAR_RISE1 BIT(4) +#define INTCLEAR_RISE0 BIT(0) + /* Exynos5260 specific */ #define EXYNOS5260_TMU_REG_INTEN 0xC0 #define EXYNOS5260_TMU_REG_INTSTAT 0xC4 @@ -773,7 +787,7 @@ static irqreturn_t exynos_tmu_threaded_irq(int irq, void *id) static void exynos4210_tmu_clear_irqs(struct exynos_tmu_data *data) { - unsigned int val_irq; + unsigned int val_irq, clearirq = 0; u32 tmu_intstat, tmu_intclear; if (data->soc == SOC_ARCH_EXYNOS5260) { @@ -791,15 +805,29 @@ static void exynos4210_tmu_clear_irqs(struct exynos_tmu_data *data) } val_irq = readl(data->base + tmu_intstat); - /* - * Clear the interrupts. Please note that the documentation for - * Exynos3250, Exynos4412, Exynos5250 and Exynos5260 incorrectly - * states that INTCLEAR register has a different placing of bits - * responsible for FALL IRQs than INTSTAT register. Exynos5420 - * and Exynos5440 documentation is correct (Exynos4210 doesn't - * support FALL IRQs at all). - */ - writel(val_irq, data->base + tmu_intclear); + + if (data->soc == SOC_ARCH_EXYNOS4210) { + writel(val_irq, data->base + tmu_intclear); + return; + } + + /* Map INTSTAT bits to INTCLEAR bits */ + if (val_irq & INTSTAT_FALL2) + clearirq |= INTCLEAR_FALL2; + else if (val_irq & INTSTAT_FALL1) + clearirq |= INTCLEAR_FALL1; + else if (val_irq & INTSTAT_FALL0) + clearirq |= INTCLEAR_FALL0; + else if (val_irq & INTSTAT_RISE2) + clearirq |= INTCLEAR_RISE2; + else if (val_irq & INTSTAT_RISE1) + clearirq |= INTCLEAR_RISE1; + else if (val_irq & INTSTAT_RISE0) + clearirq |= INTCLEAR_RISE0; + + /* Perform proper task for decrease temperature */ + if (clearirq) + writel(clearirq, data->base + tmu_intclear); } static const struct of_device_id exynos_tmu_match[] = { From patchwork Mon Jun 16 16:38:24 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anand Moon X-Patchwork-Id: 897486 Received: from mail-pg1-f170.google.com (mail-pg1-f170.google.com [209.85.215.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A638E288526; 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Mon, 16 Jun 2025 09:39:16 -0700 (PDT) Received: from localhost.localdomain ([45.112.0.181]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b2fe1680c6asm6067882a12.42.2025.06.16.09.39.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Jun 2025 09:39:16 -0700 (PDT) From: Anand Moon To: Bartlomiej Zolnierkiewicz , Krzysztof Kozlowski , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Alim Akhtar , linux-pm@vger.kernel.org (open list:SAMSUNG THERMAL DRIVER), linux-samsung-soc@vger.kernel.org (open list:SAMSUNG THERMAL DRIVER), linux-arm-kernel@lists.infradead.org (moderated list:ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES), linux-kernel@vger.kernel.org (open list) Cc: Anand Moon Subject: [RRC v1 3/3] thermal/drivers/exynos: Refactor IRQ clear logic using SoC-specific config Date: Mon, 16 Jun 2025 22:08:24 +0530 Message-ID: <20250616163831.8138-4-linux.amoon@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250616163831.8138-1-linux.amoon@gmail.com> References: <20250616163831.8138-1-linux.amoon@gmail.com> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Refactors the IRQ clear logic in the Exynos TMU driver to eliminate redundant code and enhance maintainability. Previously, the driver relied on multiple SoC-specific functions or conditional branching based on data->soc to handle differences in IRQ register behavior. Change introduces a unified exynos_tmu_clear_irqs() function that adapts its behavior using SoC-specific configuration fields (tmu_intstat, tmu_intclear, and irq_clear_direct) defined in the exynos_tmu_data structure. These fields are initialized per SoC during device setup. This refactor reduces code duplication, simplifies the addition of new SoC support, and improves overall code clarity. Signed-off-by: Anand Moon --- drivers/thermal/samsung/exynos_tmu.c | 52 +++++++++++++++++----------- 1 file changed, 31 insertions(+), 21 deletions(-) diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c index b7522b7b1230..cd21b36674c3 100644 --- a/drivers/thermal/samsung/exynos_tmu.c +++ b/drivers/thermal/samsung/exynos_tmu.c @@ -172,6 +172,9 @@ enum soc_type { * 0 < reference_voltage <= 31 * @tzd: pointer to thermal_zone_device structure * @enabled: current status of TMU device + * @tmu_intstat: interrupt status register + * @tmu_intclear: interrupt clear register + * @irq_clear_support: SoC supports clear IRQ * @tmu_set_low_temp: SoC specific method to set trip (falling threshold) * @tmu_set_high_temp: SoC specific method to set trip (rising threshold) * @tmu_set_crit_temp: SoC specific method to set critical temperature @@ -198,6 +201,9 @@ struct exynos_tmu_data { u8 reference_voltage; struct thermal_zone_device *tzd; bool enabled; + u32 tmu_intstat; + u32 tmu_intclear; + bool irq_clear_support; void (*tmu_set_low_temp)(struct exynos_tmu_data *data, u8 temp); void (*tmu_set_high_temp)(struct exynos_tmu_data *data, u8 temp); @@ -785,28 +791,15 @@ static irqreturn_t exynos_tmu_threaded_irq(int irq, void *id) return IRQ_HANDLED; } -static void exynos4210_tmu_clear_irqs(struct exynos_tmu_data *data) +static void exynos_tmu_clear_irqs(struct exynos_tmu_data *data) { unsigned int val_irq, clearirq = 0; - u32 tmu_intstat, tmu_intclear; - - if (data->soc == SOC_ARCH_EXYNOS5260) { - tmu_intstat = EXYNOS5260_TMU_REG_INTSTAT; - tmu_intclear = EXYNOS5260_TMU_REG_INTCLEAR; - } else if (data->soc == SOC_ARCH_EXYNOS7) { - tmu_intstat = EXYNOS7_TMU_REG_INTPEND; - tmu_intclear = EXYNOS7_TMU_REG_INTPEND; - } else if (data->soc == SOC_ARCH_EXYNOS5433) { - tmu_intstat = EXYNOS5433_TMU_REG_INTPEND; - tmu_intclear = EXYNOS5433_TMU_REG_INTPEND; - } else { - tmu_intstat = EXYNOS_TMU_REG_INTSTAT; - tmu_intclear = EXYNOS_TMU_REG_INTCLEAR; - } + u32 tmu_intstat = data->tmu_intstat; + u32 tmu_intclear = data->tmu_intclear; val_irq = readl(data->base + tmu_intstat); - if (data->soc == SOC_ARCH_EXYNOS4210) { + if (!data->irq_clear_support) { writel(val_irq, data->base + tmu_intclear); return; } @@ -900,12 +893,15 @@ static int exynos_map_dt_data(struct platform_device *pdev) data->tmu_initialize = exynos4210_tmu_initialize; data->tmu_control = exynos4210_tmu_control; data->tmu_read = exynos4210_tmu_read; - data->tmu_clear_irqs = exynos4210_tmu_clear_irqs; + data->tmu_clear_irqs = exynos_tmu_clear_irqs; data->gain = 15; data->reference_voltage = 7; data->efuse_value = 55; data->min_efuse_value = 40; data->max_efuse_value = 100; + data->tmu_intstat = EXYNOS_TMU_REG_INTSTAT; + data->tmu_intclear = EXYNOS_TMU_REG_INTCLEAR; + data->irq_clear_support = false; break; case SOC_ARCH_EXYNOS3250: case SOC_ARCH_EXYNOS4412: @@ -922,7 +918,7 @@ static int exynos_map_dt_data(struct platform_device *pdev) data->tmu_control = exynos4210_tmu_control; data->tmu_read = exynos4412_tmu_read; data->tmu_set_emulation = exynos4412_tmu_set_emulation; - data->tmu_clear_irqs = exynos4210_tmu_clear_irqs; + data->tmu_clear_irqs = exynos_tmu_clear_irqs; data->gain = 8; data->reference_voltage = 16; data->efuse_value = 55; @@ -932,6 +928,14 @@ static int exynos_map_dt_data(struct platform_device *pdev) else data->min_efuse_value = 0; data->max_efuse_value = 100; + data->irq_clear_support = true; + if (data->soc == SOC_ARCH_EXYNOS5260) { + data->tmu_intstat = EXYNOS5260_TMU_REG_INTSTAT; + data->tmu_intclear = EXYNOS5260_TMU_REG_INTCLEAR; + } else { + data->tmu_intstat = EXYNOS_TMU_REG_INTSTAT; + data->tmu_intclear = EXYNOS_TMU_REG_INTCLEAR; + } break; case SOC_ARCH_EXYNOS5433: data->tmu_set_low_temp = exynos5433_tmu_set_low_temp; @@ -943,7 +947,7 @@ static int exynos_map_dt_data(struct platform_device *pdev) data->tmu_control = exynos5433_tmu_control; data->tmu_read = exynos4412_tmu_read; data->tmu_set_emulation = exynos4412_tmu_set_emulation; - data->tmu_clear_irqs = exynos4210_tmu_clear_irqs; + data->tmu_clear_irqs = exynos_tmu_clear_irqs; data->gain = 8; if (res.start == EXYNOS5433_G3D_BASE) data->reference_voltage = 23; @@ -952,6 +956,9 @@ static int exynos_map_dt_data(struct platform_device *pdev) data->efuse_value = 75; data->min_efuse_value = 40; data->max_efuse_value = 150; + data->tmu_intstat = EXYNOS5433_TMU_REG_INTPEND; + data->tmu_intclear = EXYNOS5433_TMU_REG_INTPEND; + data->irq_clear_support = true; break; case SOC_ARCH_EXYNOS7: data->tmu_set_low_temp = exynos7_tmu_set_low_temp; @@ -963,12 +970,15 @@ static int exynos_map_dt_data(struct platform_device *pdev) data->tmu_control = exynos7_tmu_control; data->tmu_read = exynos7_tmu_read; data->tmu_set_emulation = exynos4412_tmu_set_emulation; - data->tmu_clear_irqs = exynos4210_tmu_clear_irqs; + data->tmu_clear_irqs = exynos_tmu_clear_irqs; data->gain = 9; data->reference_voltage = 17; data->efuse_value = 75; data->min_efuse_value = 15; data->max_efuse_value = 100; + data->tmu_intstat = EXYNOS7_TMU_REG_INTPEND; + data->tmu_intclear = EXYNOS7_TMU_REG_INTPEND; + data->irq_clear_support = true; break; default: dev_err(&pdev->dev, "Platform not supported\n");