From patchwork Mon Jun 16 22:00:46 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Anderson X-Patchwork-Id: 897309 Received: from out-188.mta1.migadu.com (out-188.mta1.migadu.com [95.215.58.188]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E53A51C4A0A for ; Mon, 16 Jun 2025 22:01:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.188 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750111276; cv=none; b=HNWsCGw55h/glG6FYEdpKksF+sdE+PqltCwf7/ZHeIM+y/8ZB/e3CMzTLvXQU6jd0gFZN48VqWtBjWVBvPEp2J1xKErBKOxjNF5ETDrdD5+wKEBpnuNwerOklKZbHCxKEa/99TqdH2u0mauZUiOnJiBPsZgXek6S1WhzGFFhiDo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750111276; c=relaxed/simple; bh=SFLO0xOMn8PJY80uuJvTi/bHhgq8BmwsE8+5yzDsMRE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=C6QNYiHMtY+d0FTfO7QoBgQ/hl8bmO+31cR2QtxOiS+bZoU7UZSbhB87dQKLlBR3PBG8Da6dnSswvOPllpR1Y6PKV/fKiRZeNReRx0vJodAq6nHCp7sSuLmFx6Ktt5/hTvnE1mxr0nW8u/JPyU6Kb9qPa3cJc5IFt5id1l1yScE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=UadQiczH; arc=none smtp.client-ip=95.215.58.188 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="UadQiczH" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1750111272; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=k02eg2nEnGNOVqzzGntSYPh+yjp3owIb+q67azvL4JA=; b=UadQiczHIeD6B2nrEfEl0KTczlznS2BpAm4IByPdlh/tvG58UEa+mIg6NA1S7Lc701VBxv 9aJRLszvcLyWiPz79MIql9Ggn/GzVrMhLou+zA/KGa5dIWESVTQRgAf7/1nO73SGVYPyHv AnUXRehC7n8USBTzD/K95i0cHdiLV48= From: Sean Anderson To: Mark Brown , Michal Simek , linux-spi@vger.kernel.org Cc: Jinjie Ruan , Miquel Raynal , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, David Lechner , Amit Kumar Mahapatra , Sean Anderson Subject: [PATCH v2 1/9] dt-bindings: spi: Add spi-buses property Date: Mon, 16 Jun 2025 18:00:46 -0400 Message-Id: <20250616220054.3968946-2-sean.anderson@linux.dev> In-Reply-To: <20250616220054.3968946-1-sean.anderson@linux.dev> References: <20250616220054.3968946-1-sean.anderson@linux.dev> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Migadu-Flow: FLOW_OUT From: David Lechner Add a spi-buses property to the spi-peripheral-props binding to allow specifying the SPI bus or buses that a peripheral is connected to in cases where the SPI controller has more than one physical SPI bus. Signed-off-by: David Lechner Signed-off-by: Sean Anderson --- Changes in v2: - New .../devicetree/bindings/spi/spi-peripheral-props.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml index 8fc17e16efb2..cfdb55071a08 100644 --- a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml +++ b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml @@ -89,6 +89,16 @@ properties: description: Delay, in microseconds, after a write transfer. + spi-buses: + description: + Array of bus numbers that describes which SPI buses of the controller are + connected to the peripheral. This only applies to peripherals connected + to specialized SPI controllers that have multiple SPI buses on a single + controller. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + default: [0] + stacked-memories: description: Several SPI memories can be wired in stacked mode. This basically means that either a device features several chip From patchwork Mon Jun 16 22:00:48 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Anderson X-Patchwork-Id: 897308 Received: from out-171.mta1.migadu.com (out-171.mta1.migadu.com [95.215.58.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1CE4E225415 for ; Mon, 16 Jun 2025 22:01:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750111279; cv=none; b=Yn7x/+xdxXde9ktv4RuJYFCcYKDEui6DE+RXjFPqjfCVFKYjxZTLXVIN8ipvKvdAyshVF7GcCRe+BMhllCG6V4TlnrG/u88BhhRh/vcG0owcvIyURvE3sfrjFw07v2cdnDrjWSR0CphsHj6X5gSEJBB9pipCAdXcTalIm2//wdY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750111279; c=relaxed/simple; bh=AcUKZuHRVnI+4gxBISBOYegc/FcNVd9I4VO+rzYErV8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=n64j8cX0gfTzrbTJy7rMqv67E15Y5Agrr67SJyjyp2PW4LLCRJSP+0Q+5jUJYo9tACWkL2+rpNiNBthHOMIF3mVpdG2LBgtpjwiYw6RQAeFf0RECRKEepqMstA82BbcAFiqvYiIxd9+vk9OaJ21/sl+SxwNjz9XK/9+i4Y0NwQM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=Mn/zUG2Q; arc=none smtp.client-ip=95.215.58.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="Mn/zUG2Q" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1750111275; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=HXSa9B9J2FkeGT4PKUZGBGTcf10cHbFGccTdZDDZdaA=; b=Mn/zUG2QLLNhYeX2c9acd3FovpjK/9Kkpa3OQ1zhNTVCTlKrWbvOT6I9mZsLdHbw1hgEN+ 4mIeXOWd3L9iz6v9oOsMWIEtmrUhBRP2rrv0g3zAkSsvUefXApCC82XXx9JKbRzOriLwoZ o8lBHp3GA6DY5eRIaDsh+nci5t86Bf0= From: Sean Anderson To: Mark Brown , Michal Simek , linux-spi@vger.kernel.org Cc: Jinjie Ruan , Miquel Raynal , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, David Lechner , Amit Kumar Mahapatra , Sean Anderson Subject: [PATCH v2 3/9] spi: Support multi-bus controllers Date: Mon, 16 Jun 2025 18:00:48 -0400 Message-Id: <20250616220054.3968946-4-sean.anderson@linux.dev> In-Reply-To: <20250616220054.3968946-1-sean.anderson@linux.dev> References: <20250616220054.3968946-1-sean.anderson@linux.dev> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Migadu-Flow: FLOW_OUT From: David Lechner Add support for SPI controllers with multiple physical SPI buses. This is common in the type of controller that can be used with parallel flash memories, but can be used for general purpose SPI as well. To indicate support, a controller just needs to set ctlr->num_buses to something greater than 1. Peripherals indicate which bus they are connected to via device tree (ACPI support can be added if needed). In the future, this can be extended to support peripherals that also have multiple SPI buses to use those buses at the same time by adding a similar bus flags field to struct spi_transfer. Signed-off-by: David Lechner Signed-off-by: Sean Anderson --- Changes in v2: - New drivers/spi/spi.c | 26 +++++++++++++++++++++++++- include/linux/spi/spi.h | 13 +++++++++++++ 2 files changed, 38 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index 1bc0fdbb1bd7..9fbf069623a8 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -2359,7 +2359,7 @@ static void of_spi_parse_dt_cs_delay(struct device_node *nc, static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi, struct device_node *nc) { - u32 value, cs[SPI_CS_CNT_MAX]; + u32 value, buses[8], cs[SPI_CS_CNT_MAX]; int rc, idx; /* Mode (clock phase/polarity/etc.) */ @@ -2460,6 +2460,29 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi, for (idx = 0; idx < rc; idx++) spi_set_chipselect(spi, idx, cs[idx]); + rc = of_property_read_variable_u32_array(nc, "spi-buses", buses, 1, + ARRAY_SIZE(buses)); + if (rc < 0 && rc != -EINVAL) { + dev_err(&ctlr->dev, "%pOF has invalid 'spi-buses' property (%d)\n", + nc, rc); + return rc; + } + + if (rc == -EINVAL) { + /* Default when property is omitted. */ + spi->buses = BIT(0); + } else { + for (idx = 0; idx < rc; idx++) { + if (buses[idx] >= ctlr->num_buses) { + dev_err(&ctlr->dev, + "%pOF has out of range 'spi-buses' property (%d)\n", + nc, buses[idx]); + return -EINVAL; + } + spi->buses |= BIT(buses[idx]); + } + } + /* * By default spi->chip_select[0] will hold the physical CS number, * so set bit 0 in spi->cs_index_mask. @@ -3070,6 +3093,7 @@ struct spi_controller *__spi_alloc_controller(struct device *dev, mutex_init(&ctlr->add_lock); ctlr->bus_num = -1; ctlr->num_chipselect = 1; + ctlr->num_buses = 1; ctlr->target = target; if (IS_ENABLED(CONFIG_SPI_SLAVE) && target) ctlr->dev.class = &spi_target_class; diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index 4789f91dae94..70e8e6555a33 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -228,6 +228,11 @@ struct spi_device { struct spi_delay cs_hold; struct spi_delay cs_inactive; + /* + * Bit flags indicating which buses this device is connected to. Only + * applicable to multi-bus controllers. + */ + u8 buses; u8 chip_select[SPI_CS_CNT_MAX]; /* @@ -574,6 +579,14 @@ struct spi_controller { */ u16 num_chipselect; + /* + * Some specialized SPI controllers can have more than one physical + * bus interface per controller. This specifies the number of buses + * in that case. Other controllers do not need to set this (defaults + * to 1). + */ + u16 num_buses; + /* Some SPI controllers pose alignment requirements on DMAable * buffers; let protocol drivers know about these requirements. */ From patchwork Mon Jun 16 22:00:50 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Anderson X-Patchwork-Id: 897307 Received: from out-170.mta1.migadu.com (out-170.mta1.migadu.com [95.215.58.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BE14E233156 for ; Mon, 16 Jun 2025 22:01:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750111283; cv=none; b=oGZGMqUBMSp+JXhOYoGOD6C0ubz8KbDlRqiMFh983vUE+p06aQzLx1GRvgePass8MZJjHaKRKEDek4SdDTajEnbf7+863TNgUJNuGNvpBI3E2J9FqrHZfjY5mt42C8RHZtSeeFPy9JSlmC5rmyVOW7+lDgySk9aX/+X/mTd8GII= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750111283; c=relaxed/simple; bh=J3HRmysUvAMuPBZHaaEJ3p7CVlln3bfpkvyA/v/2xVE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=SFuKlG1DngloKConFWFpJtfWhvBxz2AtaX7IKAJr06gvy8i1QBOdMaLCIMtNxKySQkwKVXjnpgYFj6nu8ntzmz2QtfweFgedKicw1VC0RtIIcrGg7ODLZRLbsAHErQUKE6rJVJioAq+LpU9aHTWJM4RgCOO8FAKQJi9g4ctpzvQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=jrwOh4Kh; arc=none smtp.client-ip=95.215.58.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="jrwOh4Kh" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1750111279; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=lKeCmjqMfNPPRNpjK82ZCg/Ku8sd60DeUcDOkrmPcJw=; b=jrwOh4KhAkiVpQJgns719VppdBhUkBodMTpMmBIxn1pEQ5ZOseJMmS01AU9i3k9usbeX2m AIQPuPtqEC1V3cZQr7KCdMicMohKEb8K9jjExEpMsKQxQe4Qtrmpv9A3CJW4ifwu0iDv3H RX4HjQtW2x1O3p8JTtFDKs/Ju8Y8O2A= From: Sean Anderson To: Mark Brown , Michal Simek , linux-spi@vger.kernel.org Cc: Jinjie Ruan , Miquel Raynal , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, David Lechner , Amit Kumar Mahapatra , Sean Anderson Subject: [PATCH v2 5/9] spi: zynqmp-gqspi: Support multiple buses Date: Mon, 16 Jun 2025 18:00:50 -0400 Message-Id: <20250616220054.3968946-6-sean.anderson@linux.dev> In-Reply-To: <20250616220054.3968946-1-sean.anderson@linux.dev> References: <20250616220054.3968946-1-sean.anderson@linux.dev> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Migadu-Flow: FLOW_OUT Currently, selection of the upper/lower buses is determined by the chipselect. Decouple this by allowing explicit bus selection through the spi-buses property. Signed-off-by: Sean Anderson --- Changes in v2: - New drivers/spi/spi-zynqmp-gqspi.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/spi/spi-zynqmp-gqspi.c b/drivers/spi/spi-zynqmp-gqspi.c index 595b6dc10845..add5eea12153 100644 --- a/drivers/spi/spi-zynqmp-gqspi.c +++ b/drivers/spi/spi-zynqmp-gqspi.c @@ -465,13 +465,13 @@ static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high) genfifoentry |= GQSPI_GENFIFO_MODE_SPI; if (!is_high) { - if (!spi_get_chipselect(qspi, 0)) { - xqspi->genfifobus = GQSPI_GENFIFO_BUS_LOWER; + xqspi->genfifobus = + FIELD_PREP(GQSPI_GENFIFO_BUS_MASK, qspi->buses); + if (!spi_get_chipselect(qspi, 0)) xqspi->genfifocs = GQSPI_GENFIFO_CS_LOWER; - } else { - xqspi->genfifobus = GQSPI_GENFIFO_BUS_UPPER; + else xqspi->genfifocs = GQSPI_GENFIFO_CS_UPPER; - } + genfifoentry |= xqspi->genfifobus; genfifoentry |= xqspi->genfifocs; genfifoentry |= GQSPI_GENFIFO_CS_SETUP; @@ -1316,6 +1316,8 @@ static int zynqmp_qspi_probe(struct platform_device *pdev) ctlr->num_chipselect = num_cs; } + ctlr->num_buses = 2; + ctlr->flags = SPI_CONTROLLER_DEFAULT_BUS_IS_CS; ctlr->bits_per_word_mask = SPI_BPW_MASK(8); ctlr->mem_ops = &zynqmp_qspi_mem_ops; ctlr->mem_caps = &zynqmp_qspi_mem_caps; From patchwork Mon Jun 16 22:00:51 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Anderson X-Patchwork-Id: 897306 Received: from out-188.mta1.migadu.com (out-188.mta1.migadu.com [95.215.58.188]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 36AD523505E for ; Mon, 16 Jun 2025 22:01:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.188 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750111284; cv=none; b=I+EYNJqlmMe22TBj+fICHdjJ3fLPeusATTwp+ABD22+mzgPXMDoTmLq30/sPRhlpBph1pGBp117CbluFuerkLQqJE1BcBb1zbIpYkZPhd+lWuxbKdCITH1M8rCnyaW26eNKFVjqG1+ESEXn8YSkMfi3etbHmBYidEuzqhBxIUJc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750111284; c=relaxed/simple; bh=NcmTj5O4UnDJpKrXg8mlqcQXqW5kLOfOgZhvciV6zUo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=PEd3BzsfhP5JKtVjJTsBo8s+2mN7OdZlCUgB9D88284lDeeGTJeBn7ivzOmoQYW3jR8TpAii5yLO0hZoA5Vj/wy5jeP+fqgaed4j1OkzObIkdg/+K05wPOtym/z3xbSa41sYMWQJkLqPyNGo6z0jmG8B1qYmu0jwLR8m/Jd2XCQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=udplqrxW; arc=none smtp.client-ip=95.215.58.188 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="udplqrxW" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1750111281; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=UpXv1zP1pu51TTfErAKypkJY3vjgrcKFdh3KjXTzhFA=; b=udplqrxWmGeRFbpu6YjHOGUPktFGJtRBM5UfUSsLYVTGVZ2Yt7dK+XIYp7GzFbUKRk447d nJ8irijhPldc1awyPuB+LHl3oEr9g9aOSJn+LM0DavL274LLBCCTUpZfacG1+O0+A3TrFl NjLIvzJbMesvV/uqBA2M7Ka98jjmCHQ= From: Sean Anderson To: Mark Brown , Michal Simek , linux-spi@vger.kernel.org Cc: Jinjie Ruan , Miquel Raynal , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, David Lechner , Amit Kumar Mahapatra , Sean Anderson Subject: [PATCH v2 6/9] spi: zynqmp-gqspi: Pass speed directly to config_op Date: Mon, 16 Jun 2025 18:00:51 -0400 Message-Id: <20250616220054.3968946-7-sean.anderson@linux.dev> In-Reply-To: <20250616220054.3968946-1-sean.anderson@linux.dev> References: <20250616220054.3968946-1-sean.anderson@linux.dev> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Migadu-Flow: FLOW_OUT In preparation for supporting transfer_one, which supplies the speed from the spi_transfer instead of the spi_device, convert config_op to take the speed directly. Signed-off-by: Sean Anderson --- (no changes since v1) drivers/spi/spi-zynqmp-gqspi.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/drivers/spi/spi-zynqmp-gqspi.c b/drivers/spi/spi-zynqmp-gqspi.c index add5eea12153..a17e77dc4e27 100644 --- a/drivers/spi/spi-zynqmp-gqspi.c +++ b/drivers/spi/spi-zynqmp-gqspi.c @@ -533,8 +533,8 @@ static inline u32 zynqmp_qspi_selectspimode(struct zynqmp_qspi *xqspi, /** * zynqmp_qspi_config_op - Configure QSPI controller for specified * transfer - * @xqspi: Pointer to the zynqmp_qspi structure - * @op: The memory operation to execute + * @xqspi: Pointer to the zynqmp_qspi structure + * @req_speed_hz: Requested frequency * * Sets the operational mode of QSPI controller for the next QSPI transfer and * sets the requested clock frequency. @@ -551,13 +551,10 @@ static inline u32 zynqmp_qspi_selectspimode(struct zynqmp_qspi *xqspi, * by the QSPI controller the driver will set the highest or lowest * frequency supported by controller. */ -static int zynqmp_qspi_config_op(struct zynqmp_qspi *xqspi, - const struct spi_mem_op *op) +static int zynqmp_qspi_config_op(struct zynqmp_qspi *xqspi, u32 req_speed_hz) { ulong clk_rate; - u32 config_reg, req_speed_hz, baud_rate_val = 0; - - req_speed_hz = op->max_freq; + u32 config_reg, baud_rate_val = 0; if (xqspi->speed_hz != req_speed_hz) { xqspi->speed_hz = req_speed_hz; @@ -1053,7 +1050,7 @@ static int zynqmp_qspi_exec_op(struct spi_mem *mem, u64 opaddr; mutex_lock(&xqspi->op_lock); - zynqmp_qspi_config_op(xqspi, op); + zynqmp_qspi_config_op(xqspi, op->max_freq); zynqmp_qspi_chipselect(mem->spi, false); genfifoentry |= xqspi->genfifocs; genfifoentry |= xqspi->genfifobus; From patchwork Mon Jun 16 22:00:53 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Anderson X-Patchwork-Id: 897305 Received: from out-183.mta1.migadu.com (out-183.mta1.migadu.com [95.215.58.183]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8285A23313E for ; Mon, 16 Jun 2025 22:01:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.183 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750111288; cv=none; b=TEBAAuo6p6THiAHx6BiWnUmSP1cxcnVbXeE4Woj8+xJ9JScFilDHOuf4eVm9mrluQedwFt7urid0Qwk8EWLMM8KQ8aSMAVuldA8p24bBbPyezh7DFrGGZdXheaoSauvSYkAtL1xvJrw+Tapc0W2xJ1co03rwYyOyr3Z3hPg5jn0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750111288; c=relaxed/simple; bh=GDARaksPLKEKseFYGSFlXG8ZZvfvQwPmIQyC3rwaexU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=eJW+0AET//8whJl49vy3eebz5sWFfK3PZCWNlsn3rjMy6tQ55PZh5XoIgXzN90aa3X/N9sEOi3NELY1movMh9v5ip0c8dnouo0x+JPvqJkpNMYbRqBw02j+vzLsoxqeoHSSOvHcGyrwBWnwpkW+15np3WmgmhdJ/RvQ8Fs2BSy4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=fRpI7zM8; arc=none smtp.client-ip=95.215.58.183 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="fRpI7zM8" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1750111284; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=U8s2DHgn3w9rCn5wed99fTlnLPjizNqzhROnC2hjDTA=; b=fRpI7zM8EJ3lvBmGn2ZK6cQPnRoS5fEUqpX4uEe/Q79CiQkoJ8ri/t072mO5lxXCYc/qbc 3KTVhRUQHgYXwCYzio47tXfi1X9NhHR5sreoEhqfjwuviauAq0QTq/k8y7nquFpMCUJpxW RNJwGK6tuqfrBzMKUy133m4n6EGrudc= From: Sean Anderson To: Mark Brown , Michal Simek , linux-spi@vger.kernel.org Cc: Jinjie Ruan , Miquel Raynal , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, David Lechner , Amit Kumar Mahapatra , Sean Anderson Subject: [PATCH v2 8/9] spi: zynqmp-gqspi: Support GPIO chip selects Date: Mon, 16 Jun 2025 18:00:53 -0400 Message-Id: <20250616220054.3968946-9-sean.anderson@linux.dev> In-Reply-To: <20250616220054.3968946-1-sean.anderson@linux.dev> References: <20250616220054.3968946-1-sean.anderson@linux.dev> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Migadu-Flow: FLOW_OUT GPIO chipselects use the traditional SPI API instead of the SPIMEM API. Implement it with transfer_one and set_cs (for non-GPIO chipselects). At the moment we only support half-duplex transfers, which is good enough to access SPI flashes. Signed-off-by: Sean Anderson --- Changes in v2: - Use ->buses instead of an upper/lower split drivers/spi/spi-zynqmp-gqspi.c | 93 ++++++++++++++++++++++++++++++---- 1 file changed, 84 insertions(+), 9 deletions(-) diff --git a/drivers/spi/spi-zynqmp-gqspi.c b/drivers/spi/spi-zynqmp-gqspi.c index b36159dbaff0..87d375fae653 100644 --- a/drivers/spi/spi-zynqmp-gqspi.c +++ b/drivers/spi/spi-zynqmp-gqspi.c @@ -499,6 +499,15 @@ static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high) dev_err(xqspi->dev, "Chip select timed out\n"); } +static void zynqmp_qspi_set_cs(struct spi_device *qspi, bool is_high) +{ + struct zynqmp_qspi *xqspi = spi_controller_get_devdata(qspi->controller); + + mutex_lock(&xqspi->op_lock); + zynqmp_qspi_chipselect(qspi, is_high); + mutex_unlock(&xqspi->op_lock); +} + /** * zynqmp_qspi_selectspimode - Selects SPI mode - x1 or x2 or x4. * @xqspi: xqspi is a pointer to the GQSPI instance @@ -1197,6 +1206,73 @@ static int zynqmp_qspi_exec_op(struct spi_mem *mem, return err; } +static int zynqmp_qspi_transfer_one(struct spi_controller *ctlr, + struct spi_device *spi, + struct spi_transfer *transfer) +{ + struct zynqmp_qspi *xqspi = spi_controller_get_devdata(ctlr); + unsigned long timeout; + u32 genfifoentry; + u32 mask = 0; + int ret; + + dev_dbg(xqspi->dev, "xfer %u/%u %u\n", transfer->tx_nbits, + transfer->rx_nbits, transfer->len); + + if (transfer->tx_nbits && transfer->rx_nbits) + return -EOPNOTSUPP; + + guard(mutex)(&xqspi->op_lock); + zynqmp_qspi_config_op(xqspi, transfer->speed_hz, spi->mode); + if (spi_get_csgpiod(spi, 0)) { + xqspi->genfifobus = + FIELD_PREP(GQSPI_GENFIFO_BUS_MASK, spi->buses); + xqspi->genfifocs = 0; + } + genfifoentry = xqspi->genfifocs | xqspi->genfifobus; + + reinit_completion(&xqspi->data_completion); + if (transfer->tx_nbits) { + xqspi->txbuf = transfer->tx_buf; + xqspi->rxbuf = NULL; + xqspi->bytes_to_transfer = transfer->len; + xqspi->bytes_to_receive = 0; + zynqmp_qspi_write_op(xqspi, transfer->tx_nbits, genfifoentry); + mask = GQSPI_IER_TXEMPTY_MASK | GQSPI_IER_GENFIFOEMPTY_MASK | + GQSPI_IER_TXNOT_FULL_MASK; + timeout = zynqmp_qspi_timeout(xqspi, transfer->tx_nbits, + transfer->len); + } else { + xqspi->txbuf = NULL; + xqspi->rxbuf = transfer->rx_buf; + xqspi->bytes_to_transfer = 0; + xqspi->bytes_to_receive = transfer->len; + ret = zynqmp_qspi_read_op(xqspi, transfer->rx_nbits, + genfifoentry); + if (ret) + return ret; + + if (xqspi->mode != GQSPI_MODE_DMA) + mask = GQSPI_IER_GENFIFOEMPTY_MASK | + GQSPI_IER_RXNEMPTY_MASK | GQSPI_IER_RXEMPTY_MASK; + timeout = zynqmp_qspi_timeout(xqspi, transfer->rx_nbits, + transfer->len); + } + + zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, + zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) | + GQSPI_CFG_START_GEN_FIFO_MASK); + if (mask) + zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST, mask); + else + zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_EN_OFST, + GQSPI_QSPIDMA_DST_I_EN_DONE_MASK); + + if (!wait_for_completion_timeout(&xqspi->data_completion, timeout)) + return -ETIMEDOUT; + return 0; +} + static const struct dev_pm_ops zynqmp_qspi_dev_pm_ops = { SET_RUNTIME_PM_OPS(zynqmp_runtime_suspend, zynqmp_runtime_resume, NULL) @@ -1316,27 +1392,26 @@ static int zynqmp_qspi_probe(struct platform_device *pdev) if (ret) goto clk_dis_all; + ctlr->max_native_cs = 2; ret = of_property_read_u32(np, "num-cs", &num_cs); - if (ret < 0) { + if (ret < 0) ctlr->num_chipselect = GQSPI_DEFAULT_NUM_CS; - } else if (num_cs > GQSPI_MAX_NUM_CS) { - ret = -EINVAL; - dev_err(&pdev->dev, "only %d chip selects are available\n", - GQSPI_MAX_NUM_CS); - goto clk_dis_all; - } else { + else ctlr->num_chipselect = num_cs; - } ctlr->num_buses = 2; - ctlr->flags = SPI_CONTROLLER_DEFAULT_BUS_IS_CS; + ctlr->flags = SPI_CONTROLLER_DEFAULT_BUS_IS_CS | + SPI_CONTROLLER_HALF_DUPLEX; ctlr->bits_per_word_mask = SPI_BPW_MASK(8); ctlr->mem_ops = &zynqmp_qspi_mem_ops; ctlr->mem_caps = &zynqmp_qspi_mem_caps; ctlr->setup = zynqmp_qspi_setup_op; + ctlr->set_cs = zynqmp_qspi_set_cs; + ctlr->transfer_one = zynqmp_qspi_transfer_one; ctlr->bits_per_word_mask = SPI_BPW_MASK(8); ctlr->dev.of_node = np; ctlr->auto_runtime_pm = true; + ctlr->use_gpio_descriptors = true; ret = devm_spi_register_controller(&pdev->dev, ctlr); if (ret) {