From patchwork Mon Jun 29 12:52:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 191996 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp3128205ilg; Mon, 29 Jun 2020 11:39:54 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwIrW43SVTehN1k+lIMOn/bNESl7cEeamrsfqLe4Iyl/YohoFP9R4LRzdhg+o2myfB4rZyB X-Received: by 2002:a17:906:2786:: with SMTP id j6mr14808818ejc.216.1593455994377; Mon, 29 Jun 2020 11:39:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593455994; cv=none; d=google.com; s=arc-20160816; b=DWGg+znKiqavL4r1Y/VYC7ANcbd8ij/9JDHMShTn1ApO77uNDalnAtTnaNTOi2BobW X8+PlJc7IOISI6ugWe/3Hz+i15uRgTKNJnHHRRlTsDrsNBEvjh8Ce9ZaJPvw5jRuXsIB tU97b+urgcnehO5yF/lHZ2Rpf+dYQEZlN5CNbWe6Pn32D11SXHZKcDmpeXaO/COFXAfc wXVgvGySSgaYXRrG99duhuTTdf1msQwjcUxW4jVBj5o4tC/3dhdlja7Fpq1Ysf/V37U5 NOe1d3RcqueRfrTFrpgW5UlivAlFovtm3U5lqDq0jM/qqVDEA2lNtptu66E3PfABALnD Uq4Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=P0UG0v9WZr2hySBskVuVNfPW+YNPbGGZZJtra3qz4wQ=; b=m8RJ2NJFwsKd1+8zhnk22FkjDj8+Azr59XjKtpUnsK7VxHsO4xN5imuWh+SMCVYNFS d5SaWOiTRyVpYfnsV0lLPufFQVhZPlumDTrmZd5mq0PuesxfNPFbaF+VAvwPRlsF+Ljj 01bH+9aWJ+ykiYQiiCNvsksukcxJbcOOyJWmRN8nKOq4Dg5U2Grtei97TDollinr4/0U 2EQqfOWC+P0VjyCACruMQNd7TDP+j2EQJQUAA2c9lp2G7yLLSPj7vmEFwiywBXM3Sxpr LLQyxYakEjgGw/l84Km7ud7TqrzF8dtk3HlkX2zY8ef8q1LlkTa3CxPumCj8f1O8GS8m IrQg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=BxIAXn9p; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id d21si218100edj.417.2020.06.29.11.39.54; Mon, 29 Jun 2020 11:39:54 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=BxIAXn9p; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728124AbgF2Sjs (ORCPT + 6 others); Mon, 29 Jun 2020 14:39:48 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:54506 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726084AbgF2Sjl (ORCPT ); Mon, 29 Jun 2020 14:39:41 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 05TCr25O015325; Mon, 29 Jun 2020 07:53:02 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1593435182; bh=P0UG0v9WZr2hySBskVuVNfPW+YNPbGGZZJtra3qz4wQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=BxIAXn9pA9SiL6e4p4eWsaoij0Hi+deiYTP2BN+gMGn9VYWWL8h+a8QtUv12ocBWT ia1rvJwuMw5xlXW+2Qcp23rIjoi6WqaI1lKFDDQTbRbkhwReU4auk/olLTRmX7wp79 589Web2cMuwMWtPDEhaxXItGi5nSBXxPSNyiVRr0= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 05TCr2NU111046 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 29 Jun 2020 07:53:02 -0500 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 29 Jun 2020 07:53:01 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 29 Jun 2020 07:53:01 -0500 Received: from lta0400828a.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 05TCqugw015456; Mon, 29 Jun 2020 07:52:59 -0500 From: Roger Quadros To: CC: , , , , , , Roger Quadros Subject: [PATCH v4 1/6] dt-bindings: mfd: ti, j721e-system-controller.yaml: Add J721e system controller Date: Mon, 29 Jun 2020 15:52:49 +0300 Message-ID: <20200629125254.28754-2-rogerq@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200629125254.28754-1-rogerq@ti.com> References: <20200629125254.28754-1-rogerq@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add DT binding schema for J721e system controller. Signed-off-by: Roger Quadros --- .../mfd/ti,j721e-system-controller.yaml | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki Reviewed-by: Rob Herring diff --git a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml new file mode 100644 index 000000000000..03d0a232c75e --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/ti,j721e-system-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI J721e System Controller Registers R/W Device Tree Bindings + +description: | + This represents the Control Module registers (CTRL_MMR0) on the SoC. + System controller node represents a register region containing a set + of miscellaneous registers. The registers are not cohesive enough to + represent as any specific type of device. The typical use-case is + for some other node's driver, or platform-specific code, to acquire + a reference to the syscon node (e.g. by phandle, node path, or + search using a specific compatible value), interrogate the node (or + associated OS driver) to determine the location of the registers, + and access the registers directly. + +maintainers: + - Kishon Vijay Abraham I + - Roger Quadros ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + serdes_ln_ctrl: serdes-ln-ctrl@4080 { + compatible = "mmio-mux"; + reg = <0x00004080 0x50>; + }; + }; +... From patchwork Mon Jun 29 12:52:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 191994 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp3128112ilg; Mon, 29 Jun 2020 11:39:45 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxGW2LY6/MnyNnGjXxpgzzzTzdOwZfEAWmyKlbGa8ZJ3a+x1e4ck9vU4AAtndi3m3hNnoTj X-Received: by 2002:a17:906:57c5:: with SMTP id u5mr114291ejr.311.1593455985144; Mon, 29 Jun 2020 11:39:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593455985; cv=none; d=google.com; s=arc-20160816; b=YCqBq0r0bQJtjXk+ulpvp5Ncd9SRpwRRqYVs/m7U8rhU9V/77pAHmqpSRs6EHYa2ye 3473SuOacK8wsh0FK+5x0nxECAPhoYU2EWSUAT+0D9D7aWwMMEcFxB7P79XUMNkuN5sa 87FEQ16R1KBRhWTwxujEjnCBydqZOLi/o8IXxCsooFZEP9+2WWDtriZDCK45cOxR1DzC 34B6bXBUxkRVXTSpPKS+lLkc/wZvF8HWFBp+cdTOyt/nAcDhmnvVrBewjEtVsYPlM6IC 4jr016xfim+J4rv3UT+dJLlh0/y82Yi9IXOxwFjUnP8KnZHknE3A2wbgVEWPgfQ6jndC kaTA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=prnwTOgxqOwaVzHicWh00ZrdSrVyEiINn+lOenIn0iI=; b=rjWbBrO6SMudzcoMP/g8txetxnhf9wD8DEnxv9PgZi365KeGjw40emrzH0ICy6O8S7 rR5gPQDQk1VG48LqBnVlRgzYoHr3YEnWKfWiRcLbYwZhI9oAgKVHVOA5meUWBKNz4xud +USgTZBxP1ci6iNPvaoa1HG+XgrV9TrxtRuCk3JvS2q+ccTWnQonlCMFHQhoXD31VOIm yWb+WWUBp5cKdNUkjMXoHAxlXAFsXlSSmx/eomi+ymOR4jn9QWU/Oac6sFojDsM3QNaL 0e/UPNE8/wm4LAVKysvUAFc1riJgWdJyyc9S+b+8dkEmD7foWl+sVJOfX4LyiKNTK7ys 5KoA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="KN/J4ROR"; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Roger Quadros --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 241 ++++++++++++++++++++++ 1 file changed, 241 insertions(+) -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 96c929da639d..b11cb51af747 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -4,6 +4,7 @@ * * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/ */ +#include &cbass_main { msmc_ram: sram@70000000 { @@ -277,6 +278,246 @@ pinctrl-single,function-mask = <0xffffffff>; }; + dummy_cmn_refclk: dummy-cmn-refclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + }; + + dummy_cmn_refclk1: dummy-cmn-refclk1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + }; + + serdes_wiz0: wiz@5000000 { + compatible = "ti,j721e-wiz-16g"; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>; + clock-names = "fck", "core_ref_clk", "ext_ref_clk"; + assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>; + assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>; + num-lanes = <2>; + #reset-cells = <1>; + ranges = <0x5000000 0x0 0x5000000 0x10000>; + + wiz0_pll0_refclk: pll0-refclk { + clocks = <&k3_clks 292 11>, <&dummy_cmn_refclk>; + #clock-cells = <0>; + assigned-clocks = <&wiz0_pll0_refclk>; + assigned-clock-parents = <&k3_clks 292 11>; + }; + + wiz0_pll1_refclk: pll1-refclk { + clocks = <&k3_clks 292 0>, <&dummy_cmn_refclk1>; + #clock-cells = <0>; + assigned-clocks = <&wiz0_pll1_refclk>; + assigned-clock-parents = <&k3_clks 292 0>; + }; + + wiz0_refclk_dig: refclk-dig { + clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; + #clock-cells = <0>; + assigned-clocks = <&wiz0_refclk_dig>; + assigned-clock-parents = <&k3_clks 292 11>; + }; + + wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div { + clocks = <&wiz0_refclk_dig>; + #clock-cells = <0>; + }; + + wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div { + clocks = <&wiz0_pll1_refclk>; + #clock-cells = <0>; + }; + + serdes0: serdes@5000000 { + compatible = "ti,sierra-phy-t0"; + reg-names = "serdes"; + reg = <0x5000000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&serdes_wiz0 0>; + reset-names = "sierra_reset"; + clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>; + clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; + }; + }; + + serdes_wiz1: wiz@5010000 { + compatible = "ti,j721e-wiz-16g"; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&dummy_cmn_refclk>; + clock-names = "fck", "core_ref_clk", "ext_ref_clk"; + assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>; + assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>; + num-lanes = <2>; + #reset-cells = <1>; + ranges = <0x5010000 0x0 0x5010000 0x10000>; + + wiz1_pll0_refclk: pll0-refclk { + clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>; + #clock-cells = <0>; + assigned-clocks = <&wiz1_pll0_refclk>; + assigned-clock-parents = <&k3_clks 293 13>; + }; + + wiz1_pll1_refclk: pll1-refclk { + clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>; + #clock-cells = <0>; + assigned-clocks = <&wiz1_pll1_refclk>; + assigned-clock-parents = <&k3_clks 293 0>; + }; + + wiz1_refclk_dig: refclk-dig { + clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; + #clock-cells = <0>; + assigned-clocks = <&wiz1_refclk_dig>; + assigned-clock-parents = <&k3_clks 293 13>; + }; + + wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div{ + clocks = <&wiz1_refclk_dig>; + #clock-cells = <0>; + }; + + wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div { + clocks = <&wiz1_pll1_refclk>; + #clock-cells = <0>; + }; + + serdes1: serdes@5010000 { + compatible = "ti,sierra-phy-t0"; + reg-names = "serdes"; + reg = <0x5010000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&serdes_wiz1 0>; + reset-names = "sierra_reset"; + clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>; + clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; + }; + }; + + serdes_wiz2: wiz@5020000 { + compatible = "ti,j721e-wiz-16g"; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&dummy_cmn_refclk>; + clock-names = "fck", "core_ref_clk", "ext_ref_clk"; + assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>; + assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>; + num-lanes = <2>; + #reset-cells = <1>; + ranges = <0x5020000 0x0 0x5020000 0x10000>; + + wiz2_pll0_refclk: pll0-refclk { + clocks = <&k3_clks 294 11>, <&dummy_cmn_refclk>; + #clock-cells = <0>; + assigned-clocks = <&wiz2_pll0_refclk>; + assigned-clock-parents = <&k3_clks 294 11>; + }; + + wiz2_pll1_refclk: pll1-refclk { + clocks = <&k3_clks 294 0>, <&dummy_cmn_refclk1>; + #clock-cells = <0>; + assigned-clocks = <&wiz2_pll1_refclk>; + assigned-clock-parents = <&k3_clks 294 0>; + }; + + wiz2_refclk_dig: refclk-dig { + clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; + #clock-cells = <0>; + assigned-clocks = <&wiz2_refclk_dig>; + assigned-clock-parents = <&k3_clks 294 11>; + }; + + wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div { + clocks = <&wiz2_refclk_dig>; + #clock-cells = <0>; + }; + + wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div { + clocks = <&wiz2_pll1_refclk>; + #clock-cells = <0>; + }; + + serdes2: serdes@5020000 { + compatible = "ti,sierra-phy-t0"; + reg-names = "serdes"; + reg = <0x5020000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&serdes_wiz2 0>; + reset-names = "sierra_reset"; + clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>; + clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; + }; + }; + + serdes_wiz3: wiz@5030000 { + compatible = "ti,j721e-wiz-16g"; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&dummy_cmn_refclk>; + clock-names = "fck", "core_ref_clk", "ext_ref_clk"; + assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>; + assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>; + num-lanes = <2>; + #reset-cells = <1>; + ranges = <0x5030000 0x0 0x5030000 0x10000>; + + wiz3_pll0_refclk: pll0-refclk { + clocks = <&k3_clks 295 9>, <&dummy_cmn_refclk>; + #clock-cells = <0>; + assigned-clocks = <&wiz3_pll0_refclk>; + assigned-clock-parents = <&k3_clks 295 9>; + }; + + wiz3_pll1_refclk: pll1-refclk { + clocks = <&k3_clks 295 0>, <&dummy_cmn_refclk1>; + #clock-cells = <0>; + assigned-clocks = <&wiz3_pll1_refclk>; + assigned-clock-parents = <&k3_clks 295 0>; + }; + + wiz3_refclk_dig: refclk-dig { + clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; + #clock-cells = <0>; + assigned-clocks = <&wiz3_refclk_dig>; + assigned-clock-parents = <&k3_clks 295 9>; + }; + + wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div { + clocks = <&wiz3_refclk_dig>; + #clock-cells = <0>; + }; + + wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div { + clocks = <&wiz3_pll1_refclk>; + #clock-cells = <0>; + }; + + serdes3: serdes@5030000 { + compatible = "ti,sierra-phy-t0"; + reg-names = "serdes"; + reg = <0x5030000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&serdes_wiz3 0>; + reset-names = "sierra_reset"; + clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>; + clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; + }; + }; + main_uart0: serial@2800000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x100>; From patchwork Mon Jun 29 12:52:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 192007 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp3194765ilg; Mon, 29 Jun 2020 13:16:15 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyj3SX+Csc+6xm9INNi5h2cAPP4ik+ZjPeFUSItu48+NZtfslzURNTV+dDSE/y5cu73i+dQ X-Received: by 2002:a17:906:c40d:: with SMTP id u13mr14849024ejz.519.1593461775142; Mon, 29 Jun 2020 13:16:15 -0700 (PDT) ARC-Seal: i=1; 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[23.128.96.18]) by mx.google.com with ESMTP id lz15si394390ejb.406.2020.06.29.13.16.14; Mon, 29 Jun 2020 13:16:15 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=iQ7omHAk; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730722AbgF2UQF (ORCPT + 6 others); Mon, 29 Jun 2020 16:16:05 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:51036 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730866AbgF2UQD (ORCPT ); Mon, 29 Jun 2020 16:16:03 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 05TCr6Io030020; Mon, 29 Jun 2020 07:53:06 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1593435186; bh=uZzuW2dv2cMMVtbXg7LVptpnmlAjlXYZa5nOer++PqE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=iQ7omHAk+VsckPQw1Q3g7sQs6I9blvygNXso4+lJRhWu5xJfBAb6r+6YnggH8Aw+Q 0YiQYdxhToJr+jnG1Jfe4bOez0GrgfrdW+B4PafqLthfrIlkPTT+mItKo7MqtYFPdf 1vKn6lkkqL9V4nbpt6mTHMu6o4prjA7+xaaezIiE= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 05TCr6dw015197 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 29 Jun 2020 07:53:06 -0500 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 29 Jun 2020 07:53:05 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 29 Jun 2020 07:53:05 -0500 Received: from lta0400828a.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 05TCquh0015456; Mon, 29 Jun 2020 07:53:04 -0500 From: Roger Quadros To: CC: , , , , , , Roger Quadros Subject: [PATCH v4 3/6] arm64: dts: ti: k3-j721e-main: Add system controller node and SERDES lane mux Date: Mon, 29 Jun 2020 15:52:51 +0300 Message-ID: <20200629125254.28754-4-rogerq@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200629125254.28754-1-rogerq@ti.com> References: <20200629125254.28754-1-rogerq@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Kishon Vijay Abraham I The system controller node manages the CTRL_MMR0 region. Add serdes_ln_ctrl node which is used for controlling the SERDES lane mux. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Roger Quadros --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 27 ++++++++++++ include/dt-bindings/mux/mux-j721e-wiz.h | 53 +++++++++++++++++++++++ 2 files changed, 80 insertions(+) create mode 100644 include/dt-bindings/mux/mux-j721e-wiz.h -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki Acked-by: Rob Herring diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index b11cb51af747..5f1f11b6fdff 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -5,6 +5,8 @@ * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/ */ #include +#include +#include &cbass_main { msmc_ram: sram@70000000 { @@ -19,6 +21,31 @@ }; }; + scm_conf: scm-conf@100000 { + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; + reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */ + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x00100000 0x1c000>; + + serdes_ln_ctrl: serdes-ln-ctrl@4080 { + compatible = "mmio-mux"; + reg = <0x00004080 0x50>; + #mux-control-cells = <1>; + mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ + <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ + <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ + <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */ + <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>; + /* SERDES4 lane0/1/2/3 select */ + idle-states = , , + , , + , , + , , + , , , ; + }; + }; + gic500: interrupt-controller@1800000 { compatible = "arm,gic-v3"; #address-cells = <2>; diff --git a/include/dt-bindings/mux/mux-j721e-wiz.h b/include/dt-bindings/mux/mux-j721e-wiz.h new file mode 100644 index 000000000000..fd1c4ea9fc7f --- /dev/null +++ b/include/dt-bindings/mux/mux-j721e-wiz.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for J721E WIZ. + */ + +#ifndef _DT_BINDINGS_J721E_WIZ +#define _DT_BINDINGS_J721E_WIZ + +#define SERDES0_LANE0_QSGMII_LANE1 0x0 +#define SERDES0_LANE0_PCIE0_LANE0 0x1 +#define SERDES0_LANE0_USB3_0_SWAP 0x2 + +#define SERDES0_LANE1_QSGMII_LANE2 0x0 +#define SERDES0_LANE1_PCIE0_LANE1 0x1 +#define SERDES0_LANE1_USB3_0 0x2 + +#define SERDES1_LANE0_QSGMII_LANE3 0x0 +#define SERDES1_LANE0_PCIE1_LANE0 0x1 +#define SERDES1_LANE0_USB3_1_SWAP 0x2 +#define SERDES1_LANE0_SGMII_LANE0 0x3 + +#define SERDES1_LANE1_QSGMII_LANE4 0x0 +#define SERDES1_LANE1_PCIE1_LANE1 0x1 +#define SERDES1_LANE1_USB3_1 0x2 +#define SERDES1_LANE1_SGMII_LANE1 0x3 + +#define SERDES2_LANE0_PCIE2_LANE0 0x1 +#define SERDES2_LANE0_SGMII_LANE0 0x3 +#define SERDES2_LANE0_USB3_1_SWAP 0x2 + +#define SERDES2_LANE1_PCIE2_LANE1 0x1 +#define SERDES2_LANE1_USB3_1 0x2 +#define SERDES2_LANE1_SGMII_LANE1 0x3 + +#define SERDES3_LANE0_PCIE3_LANE0 0x1 +#define SERDES3_LANE0_USB3_0_SWAP 0x2 + +#define SERDES3_LANE1_PCIE3_LANE1 0x1 +#define SERDES3_LANE1_USB3_0 0x2 + +#define SERDES4_LANE0_EDP_LANE0 0x0 +#define SERDES4_LANE0_QSGMII_LANE5 0x2 + +#define SERDES4_LANE1_EDP_LANE1 0x0 +#define SERDES4_LANE1_QSGMII_LANE6 0x2 + +#define SERDES4_LANE2_EDP_LANE2 0x0 +#define SERDES4_LANE2_QSGMII_LANE7 0x2 + +#define SERDES4_LANE3_EDP_LANE3 0x0 +#define SERDES4_LANE3_QSGMII_LANE8 0x2 + +#endif /* _DT_BINDINGS_J721E_WIZ */ From patchwork Mon Jun 29 12:52:52 2020 Content-Type: text/plain; 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[23.128.96.18]) by mx.google.com with ESMTP id v25si257227ejx.496.2020.06.29.11.39.48; Mon, 29 Jun 2020 11:39:48 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=ZVxtrVuV; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728104AbgF2Sjl (ORCPT + 6 others); Mon, 29 Jun 2020 14:39:41 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:54506 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726596AbgF2Sjk (ORCPT ); Mon, 29 Jun 2020 14:39:40 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 05TCr87A015354; Mon, 29 Jun 2020 07:53:08 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1593435188; bh=cWFMa/FmsEznGa6urrgF3YL/SYAuIrgP0F7ozOAHwSM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ZVxtrVuVtXHtTe6wHBBmkVkrpRe4NNPw3MLVx99jmgPipyB+B81uXV6UOIe1X/kTs VkgJpTK7aFZTUNLWQh4Cb11gNdPa8FZ/GIaqKsO0s531RYEV1Fb4yGAoU/u88c5bqz 9Cp1el2tuL5zTkn/ACT/u7BZDPCVK1o59OKmy6ZE= Received: from DFLE106.ent.ti.com (dfle106.ent.ti.com [10.64.6.27]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 05TCr8fI015229 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 29 Jun 2020 07:53:08 -0500 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 29 Jun 2020 07:53:08 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 29 Jun 2020 07:53:08 -0500 Received: from lta0400828a.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 05TCquh1015456; Mon, 29 Jun 2020 07:53:06 -0500 From: Roger Quadros To: CC: , , , , , , Roger Quadros , Sekhar Nori Subject: [PATCH v4 4/6] arm64: dts: ti: k3-j721e-main.dtsi: Add USB to SERDES MUX Date: Mon, 29 Jun 2020 15:52:52 +0300 Message-ID: <20200629125254.28754-5-rogerq@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200629125254.28754-1-rogerq@ti.com> References: <20200629125254.28754-1-rogerq@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The USB controllers can be connected to one of the 2 SERDESes using a MUX. Add a MUX controller node fot that. Signed-off-by: Roger Quadros Signed-off-by: Sekhar Nori --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 5f1f11b6fdff..469620aec9d4 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -44,6 +44,13 @@ , , , , , ; }; + + usb_serdes_mux: mux-controller@4000 { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */ + <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */ + }; }; gic500: interrupt-controller@1800000 { From patchwork Mon Jun 29 12:52:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 192006 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp3194681ilg; Mon, 29 Jun 2020 13:16:08 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxm1C0yYKGu/4U3PBkETJZ6P0E/a2NgV4CINfduQYYdY+p8xFX/LslpeyyfyEigKv/476cz X-Received: by 2002:a17:906:e294:: with SMTP id gg20mr14792644ejb.521.1593461768303; Mon, 29 Jun 2020 13:16:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593461768; cv=none; d=google.com; s=arc-20160816; b=NHXLaQMdPyOsd+bYLWZzn67MoHNG1LaqfAySXBi+oxuSmQejXSUTBNnialnsrYchJA OESMBnC4MtaaF6H7LL7g6dKmXtPRPvOsD35IXMl6cFpVRz3xiC4RBZMJkQuRDeZjIIgC 7qkAxSm0H2TItXm7xuCDpaw+frTBgEDCgryXOzaoeJ4KFnKiseNu0mK6Oa129w6x5rH9 ayJaqJ+j9OAs7TMDYrKhqvX+s3aLENcL7eUU3eiHAkkPrFTcmCp0Uc5n30agUupzMGON 0dL0HRRzjJhiSKQpBeqBtCXj3PX8LrTlhiqb7bJ9L3ywmeGnfCuQkocW1gJjQLvi2aEb Ahnw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=Zyt3wUw/sJh31lxjxUg6MRwKjJfwWEqPIU3SE6r/4o8=; b=hoehR0xAQrwtCxVIuKPDe/rOJUSYWxTmkai1IxK2wtwArH/ddZB4Zr+7eN4Ijy64Fs u5/p5l/pX8dguOKqgUfjCCXqxlnCK2ku4MKleMdK/6HvXFZ3+4e0nf14v9FyZAi8GvaV bNmkHu/qhn/RkGod1k8+M6QQbrrSCAdd/XBFnY4xwJ+hip20RCL+f1DA0jSgnltKqcE0 VRBj+An59YKJH2DmSsHrYfdlt8Fhp7Pxx7x7d+ySEcn9fxlJ08ELn3mZ1u/YQQHTKeQT s3LAXkikZ4S+4k8exQ5T6zpTWKoN9Ey41okWN+esZ1CtgIRN09+De10NyijKnvcCFbj4 CpIA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=cbq06d+q; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Enable that. On the EVM, USB0 uses SERDES3 for super-speed lane. Since USB0 is a type-C port, it needs to support lane swapping for cable flip support. This is provided using SERDES lane swap feature. Provide the Type-C cable orientation GPIO to the SERDES Wrapper driver. Signed-off-by: Roger Quadros Signed-off-by: Sekhar Nori --- .../dts/ti/k3-j721e-common-proc-board.dts | 32 +++++++++++++++++-- 1 file changed, 30 insertions(+), 2 deletions(-) -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 6df823aaa37c..3294b96ebba8 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -60,6 +60,7 @@ main_usbss0_pins_default: main_usbss0_pins_default { pinctrl-single,pins = < J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ + J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ >; }; @@ -335,16 +336,43 @@ status = "disabled"; }; +&usb_serdes_mux { + idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */ +}; + +&serdes_ln_ctrl { + idle-states = , , + , , + , , + , , + , , , ; +}; + +&serdes_wiz3 { + typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>; +}; + +&serdes3 { + serdes3_usb_link: link@0 { + reg = <0>; + cdns,num-lanes = <2>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>; + }; +}; + &usbss0 { pinctrl-names = "default"; pinctrl-0 = <&main_usbss0_pins_default>; - ti,usb2-only; ti,vbus-divider; }; &usb0 { dr_mode = "otg"; - maximum-speed = "high-speed"; + maximum-speed = "super-speed"; + phys = <&serdes3_usb_link>; + phy-names = "cdns3,usb3-phy"; }; &usbss1 { From patchwork Mon Jun 29 12:52:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 192004 Delivered-To: patch@linaro.org Received: by 2002:a54:3249:0:0:0:0:0 with SMTP id g9csp2835586ecs; Mon, 29 Jun 2020 12:50:57 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzFZi9ylPr1KZUO/VS3wjrkUBj9alIQ/vg+H1Q+k+OB//z4/JM0g0LmwzydL78COXGfm5HY X-Received: by 2002:a05:6402:283:: with SMTP id l3mr19512659edv.105.1593460257920; Mon, 29 Jun 2020 12:50:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593460257; cv=none; d=google.com; s=arc-20160816; b=Gw2Mjn7W1EwW+SecDTaqna7BW1ZCmzaiFbEgKqvE2gtBKEA6Egy0v9IAPpNQ1tFFOP NtulikfzK+Id6hxPIfBsmYW2x8wXV3xfiRZ1zWdjD3rBfMTHhh/hl3oRdQKNlC6oSiXR f5n9By/S9oRAdIFb4wPNz0ivxj+VvAgAMhyoC3y29YsKCTd5czXJcoriZyP3xvRMZohz sJ/Yf2NYyECGJb5TzzN0ZXsVTVSs+zv/5Cb5PsDZMlSoiLW7mcESKwd97I2lrwfUbCjN M9vcNF60W7/367vwTenvy2McdZAhc33IPQh5MBKOEoE9l/1ErE9ISpUh6qCmIOh1nikd qZbQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=ttFOPNsI8C7Qj6EFkUy2MjTPikihl8NG7soqqS4fgw8=; b=XPEAnAlU7WgudAWSbQuU/AE922h31/jwUo0UcTaSxWeixNJh775yVYwrvILmWB5ZoC j2sa4mgyXJszaEu0Rde0fMRXUq2PYj+gqICXawFmCr8dkRyF//S2pcOxgpX7vmVYQMsv yVaGpa6ybBVxnTHEZpdjrnVjJRXi2tAhs/OfQXHvUtv5/PTTveJm+7ZK2Y/ZHfBhUjBh IgIvbz1KXKuWW5oFCncERsKlF5SmFPnRXYkNz26whHJJKW592TgtWBYde6RTODJ0Ovvi Q6IyPh2XkGNa3QGyiizVt0MnWKfTcrv+3+0/Qz06+QfAb2UAfe47wEAAFgnRTVn9dxEj yb+Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=pBRjibbJ; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id a22si329821edn.364.2020.06.29.12.50.57; Mon, 29 Jun 2020 12:50:57 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=pBRjibbJ; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726753AbgF2Tup (ORCPT + 6 others); Mon, 29 Jun 2020 15:50:45 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:50840 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387812AbgF2Tuk (ORCPT ); Mon, 29 Jun 2020 15:50:40 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 05TCrDMG096114; Mon, 29 Jun 2020 07:53:13 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1593435193; bh=ttFOPNsI8C7Qj6EFkUy2MjTPikihl8NG7soqqS4fgw8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=pBRjibbJLkrIoCy4o33JgQ9f2ePI58oLNmoKiuNMb50EdVyYrM7OtDkG4xHuW3WMx hcYocsAYAUt7SCQj6bVU2oGAEV3GiUyKOqp0sPNtWI3JWUczE4fO4bCtQYmnNtIrTe lWnlhcjZ2nWayTTT9Gnm2wzzcfdaW9kAa27W5/3Y= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id 05TCrDwk066355; Mon, 29 Jun 2020 07:53:13 -0500 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 29 Jun 2020 07:53:13 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 29 Jun 2020 07:53:12 -0500 Received: from lta0400828a.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 05TCquh3015456; Mon, 29 Jun 2020 07:53:10 -0500 From: Roger Quadros To: CC: , , , , , , Roger Quadros , Sekhar Nori Subject: [PATCH v4 6/6] arm64: dts: k3-j721e-proc-board: Add wait time for sampling Type-C DIR line Date: Mon, 29 Jun 2020 15:52:54 +0300 Message-ID: <20200629125254.28754-7-rogerq@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200629125254.28754-1-rogerq@ti.com> References: <20200629125254.28754-1-rogerq@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Type-C compainon chip on the board needs ~133ms (tCCB_DEFAULT) to debounce the CC lines in order to detect attach and plug orientation and reflect the correct DIR status. [1] On the EVM however we need to wait upto 700ms before sampling the Type-C DIR line else we can get incorrect direction state. [1] http://www.ti.com/lit/ds/symlink/tusb321.pdf Signed-off-by: Roger Quadros Signed-off-by: Sekhar Nori --- arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 1 + 1 file changed, 1 insertion(+) -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 3294b96ebba8..6307fe5ccb06 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -350,6 +350,7 @@ &serdes_wiz3 { typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>; + typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */ }; &serdes3 {