From patchwork Mon Jun 29 14:49:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 194512 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4CCE9C433E1 for ; Mon, 29 Jun 2020 19:39:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2F134206F1 for ; Mon, 29 Jun 2020 19:39:37 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="VMm9xmy4" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1733125AbgF2Tje (ORCPT ); Mon, 29 Jun 2020 15:39:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47582 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1733018AbgF2Thm (ORCPT ); Mon, 29 Jun 2020 15:37:42 -0400 Received: from mail-pl1-x62e.google.com (mail-pl1-x62e.google.com [IPv6:2607:f8b0:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EB8D2C02F00E for ; Mon, 29 Jun 2020 07:49:56 -0700 (PDT) Received: by mail-pl1-x62e.google.com with SMTP id u9so3580727pls.13 for ; Mon, 29 Jun 2020 07:49:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+rSgnWvzCZALaQyW++jIaIPoFwAu7y5f4Pe2z39zw30=; b=VMm9xmy4fEZxXG+o2k/Ep6O5phF2tOBoKpXoQZKWJsm6D2ODsZbKMcOfvPBiyd7vGu Gia+WEeC0/IfACg0ngh/2oEf6QXgk8OkPFSg6CGBA6C+IfGqjgFlC0MA1V/qh2/rC9Sj VhtpRWV+R3AZ99gKUS3odKT3uY9UwZkfBiNL8UxkMv1IuZyKmvvphelcHlOljg7L1Uzl 13YZ0hTnpGyoNiDXmj3C0iOy0urruBvo/lxER1wFgVarChQx4Np6Xixcp5jzZgdCel7B ugmNn+XQg30Gwg6xt4XVcnKunmervTnThiYhHfq7ZXg/HeVd7bFUevxb17BvpPT9UKds e+oQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+rSgnWvzCZALaQyW++jIaIPoFwAu7y5f4Pe2z39zw30=; b=Ksdn+1Dj+3o7EfPgSIeNnv3MNgtiqpMk+paqtXsq394nD3lRcj8JUwFl2t3xSw0eGK ecD8HG6bSHOeOUzQg0qR3oOb2XMaLiv0FA2Kjw7+H/ilKHv0DLdlZQgNzspLqdr474A/ 3dl3eicGPckxUcMQ/Q4jOd+HqRQ6uBrfnLEcjmxzaPcRNs8+8qeFqZ25XD59UTLojmwz zZ4+p7U7PEFBt+bASjh5xlu0M3a4m5JCROyA64q0AgekdEyk9HjLng/Xh0rS1V0Ta0qA nY76fNmczYKQ3Cjc60rb7zPVcsJ4pImDq3cn9hoq05JMmWtkQhxjSrjPiUHRMgNl7JAO PNAg== X-Gm-Message-State: AOAM531hfhyEaarcsLK21NfkA/9JCzpGvH4EXMNzneFPer77ArrMNHGN p8kpkbgOyHvd67wTllEmOm0m8w== X-Google-Smtp-Source: ABdhPJyybtDmcilXfo+dhV6hyHaIxV+dSXXecI+jPSloyEVxVEQfpJbPH0b3Z7o/8Go3hKAI9uAjtg== X-Received: by 2002:a17:90a:eaca:: with SMTP id ev10mr5700130pjb.151.1593442196236; Mon, 29 Jun 2020 07:49:56 -0700 (PDT) Received: from localhost.localdomain ([80.251.214.228]) by smtp.gmail.com with ESMTPSA id bg6sm191614pjb.51.2020.06.29.07.49.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jun 2020 07:49:55 -0700 (PDT) From: Shawn Guo To: Amit Kucheria , Daniel Lezcano Cc: Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, Shawn Guo Subject: [PATCH 1/2] dt-bindings: tsens: qcom: Document MSM8939 compatible Date: Mon, 29 Jun 2020 22:49:25 +0800 Message-Id: <20200629144926.665-2-shawn.guo@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200629144926.665-1-shawn.guo@linaro.org> References: <20200629144926.665-1-shawn.guo@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Konrad Dybcio It adds compatible for MSM8939 TSENS device. Signed-off-by: Konrad Dybcio Reviewed-by: Amit Kucheria Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/thermal/qcom-tsens.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml index d7be931b42d2..8100fce2c892 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -23,6 +23,7 @@ properties: items: - enum: - qcom,msm8916-tsens + - qcom,msm8939-tsens - qcom,msm8974-tsens - const: qcom,tsens-v0_1 From patchwork Mon Jun 29 14:49:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 192003 Delivered-To: patch@linaro.org Received: by 2002:a54:3249:0:0:0:0:0 with SMTP id g9csp2829265ecs; Mon, 29 Jun 2020 12:39:30 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzUGBbEPzCyxuVOzLq5+f4SotVHHvShLoI1j37DPp4F0rndD1MpGqGwjSAP8m7yVxoXlA47 X-Received: by 2002:aa7:c887:: with SMTP id p7mr4735007eds.240.1593459570204; Mon, 29 Jun 2020 12:39:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593459570; cv=none; d=google.com; s=arc-20160816; b=stm3t4zGRHHmUCptPBYIKYcLXRq6ckw/oA+83psderHu9xRpe/tf580XoB9BZDQEuc G+/cb3Z7GNylGnXcuDrSq7jO8msHwsFMrsJaMFWLUB5+lt3mHsxXFHSGrH0qt9JGz48X kqqgStiI3Kc8ynLmj3wF8gq86ugtkRc5TOQHqw83ujfDhM9pxvOGJQ5IlWRv1n8Qtvdp EWFTiSTcOgItVT2/WkI+tyPR49sPFB2S7stXyFbXP4YtjEb3grRyjfOjzYfauuLwR/Dn FpD4WA7dIHEW+ZRlibAm8KwJKngIgLzVYUlhzhxTa1764MrHQQBQOPqHxTrUoxqnVJlr wBRA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=z33RbBxzw0A0qZX3oGdosGCurOgJdFD5wQlatBMRabs=; b=WZeCVSIjFf2l0ZjrhyNcdX1LuqpsX1/X3PNsnQyoZV0NfPzAkZG+sCvtnmWuvBr8WD ItWHa5LyWUkm4KTQWhPC+7Mhnd4xB/uImtCxDZcbCvj23NVDhgjydkQ+2WIJthQyog5Y R2fuG+v5HIwmL/e8YxQKVlPghe3ofN9EeHKEslrjRkuZX9IIWav7tVH/1tK3RKzPCMyf jpnsbbhSdPxWnWfpRxqE8K5JaYAirN4O1sK1Xw6qUaKVyCnnuoFj3rTE6yr//v2JX87S dIr+8E7iKZYd++eyvF4NmNWDmlR5qwrwIvFeHLgerNuVFYzCxMyWy8dL8l0aaESzrUj2 MFTA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FiCRpvdu; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Different from its predecessor MSM8916, where 'calib_sel' bits sit in separate qfprom word, MSM8939 has 'cailb' and 'calib_sel' bits mixed and spread on discrete offsets. That's why all qfprom bits are read as one go and later mapped to calibration data for MSM8939. Signed-off-by: Shawn Guo --- drivers/thermal/qcom/tsens-v0_1.c | 144 +++++++++++++++++++++++++++++- drivers/thermal/qcom/tsens.c | 3 + drivers/thermal/qcom/tsens.h | 2 +- 3 files changed, 147 insertions(+), 2 deletions(-) -- 2.17.1 Acked-by: Amit Kucheria diff --git a/drivers/thermal/qcom/tsens-v0_1.c b/drivers/thermal/qcom/tsens-v0_1.c index 959a9371d205..e64db5f80d90 100644 --- a/drivers/thermal/qcom/tsens-v0_1.c +++ b/drivers/thermal/qcom/tsens-v0_1.c @@ -48,6 +48,63 @@ #define MSM8916_CAL_SEL_MASK 0xe0000000 #define MSM8916_CAL_SEL_SHIFT 29 +/* eeprom layout data for 8939 */ +#define MSM8939_BASE0_MASK 0x000000ff +#define MSM8939_BASE1_MASK 0xff000000 +#define MSM8939_BASE0_SHIFT 0 +#define MSM8939_BASE1_SHIFT 24 + +#define MSM8939_S0_P1_MASK 0x000001f8 +#define MSM8939_S1_P1_MASK 0x001f8000 +#define MSM8939_S2_P1_MASK_0_4 0xf8000000 +#define MSM8939_S2_P1_MASK_5 0x00000001 +#define MSM8939_S3_P1_MASK 0x00001f80 +#define MSM8939_S4_P1_MASK 0x01f80000 +#define MSM8939_S5_P1_MASK 0x00003f00 +#define MSM8939_S6_P1_MASK 0x03f00000 +#define MSM8939_S7_P1_MASK 0x0000003f +#define MSM8939_S8_P1_MASK 0x0003f000 +#define MSM8939_S9_P1_MASK 0x07e00000 + +#define MSM8939_S0_P2_MASK 0x00007e00 +#define MSM8939_S1_P2_MASK 0x07e00000 +#define MSM8939_S2_P2_MASK 0x0000007e +#define MSM8939_S3_P2_MASK 0x0007e000 +#define MSM8939_S4_P2_MASK 0x7e000000 +#define MSM8939_S5_P2_MASK 0x000fc000 +#define MSM8939_S6_P2_MASK 0xfc000000 +#define MSM8939_S7_P2_MASK 0x00000fc0 +#define MSM8939_S8_P2_MASK 0x00fc0000 +#define MSM8939_S9_P2_MASK_0_4 0xf8000000 +#define MSM8939_S9_P2_MASK_5 0x00002000 + +#define MSM8939_S0_P1_SHIFT 3 +#define MSM8939_S1_P1_SHIFT 15 +#define MSM8939_S2_P1_SHIFT_0_4 27 +#define MSM8939_S2_P1_SHIFT_5 0 +#define MSM8939_S3_P1_SHIFT 7 +#define MSM8939_S4_P1_SHIFT 19 +#define MSM8939_S5_P1_SHIFT 8 +#define MSM8939_S6_P1_SHIFT 20 +#define MSM8939_S7_P1_SHIFT 0 +#define MSM8939_S8_P1_SHIFT 12 +#define MSM8939_S9_P1_SHIFT 21 + +#define MSM8939_S0_P2_SHIFT 9 +#define MSM8939_S1_P2_SHIFT 21 +#define MSM8939_S2_P2_SHIFT 1 +#define MSM8939_S3_P2_SHIFT 13 +#define MSM8939_S4_P2_SHIFT 25 +#define MSM8939_S5_P2_SHIFT 14 +#define MSM8939_S6_P2_SHIFT 26 +#define MSM8939_S7_P2_SHIFT 6 +#define MSM8939_S8_P2_SHIFT 18 +#define MSM8939_S9_P2_SHIFT_0_4 27 +#define MSM8939_S9_P2_SHIFT_5 13 + +#define MSM8939_CAL_SEL_MASK 0x7 +#define MSM8939_CAL_SEL_SHIFT 0 + /* eeprom layout data for 8974 */ #define BASE1_MASK 0xff #define S0_P1_MASK 0x3f00 @@ -189,6 +246,76 @@ static int calibrate_8916(struct tsens_priv *priv) return 0; } +static int calibrate_8939(struct tsens_priv *priv) +{ + int base0 = 0, base1 = 0, i; + u32 p1[10], p2[10]; + int mode = 0; + u32 *qfprom_cdata; + u32 cdata[6]; + + qfprom_cdata = (u32 *)qfprom_read(priv->dev, "calib"); + if (IS_ERR(qfprom_cdata)) + return PTR_ERR(qfprom_cdata); + + /* Mapping between qfprom nvmem and calibration data */ + cdata[0] = qfprom_cdata[12]; + cdata[1] = qfprom_cdata[13]; + cdata[2] = qfprom_cdata[0]; + cdata[3] = qfprom_cdata[1]; + cdata[4] = qfprom_cdata[22]; + cdata[5] = qfprom_cdata[21]; + + mode = (cdata[0] & MSM8939_CAL_SEL_MASK) >> MSM8939_CAL_SEL_SHIFT; + dev_dbg(priv->dev, "calibration mode is %d\n", mode); + + switch (mode) { + case TWO_PT_CALIB: + base1 = (cdata[3] & MSM8939_BASE1_MASK) >> MSM8939_BASE1_SHIFT; + p2[0] = (cdata[0] & MSM8939_S0_P2_MASK) >> MSM8939_S0_P2_SHIFT; + p2[1] = (cdata[0] & MSM8939_S1_P2_MASK) >> MSM8939_S1_P2_SHIFT; + p2[2] = (cdata[1] & MSM8939_S2_P2_MASK) >> MSM8939_S2_P2_SHIFT; + p2[3] = (cdata[1] & MSM8939_S3_P2_MASK) >> MSM8939_S3_P2_SHIFT; + p2[4] = (cdata[1] & MSM8939_S4_P2_MASK) >> MSM8939_S4_P2_SHIFT; + p2[5] = (cdata[2] & MSM8939_S5_P2_MASK) >> MSM8939_S5_P2_SHIFT; + p2[6] = (cdata[2] & MSM8939_S6_P2_MASK) >> MSM8939_S6_P2_SHIFT; + p2[7] = (cdata[3] & MSM8939_S7_P2_MASK) >> MSM8939_S7_P2_SHIFT; + p2[8] = (cdata[3] & MSM8939_S8_P2_MASK) >> MSM8939_S8_P2_SHIFT; + p2[9] = (cdata[4] & MSM8939_S9_P2_MASK_0_4) >> MSM8939_S9_P2_SHIFT_0_4; + p2[9] |= ((cdata[5] & MSM8939_S9_P2_MASK_5) >> MSM8939_S9_P2_SHIFT_5) << 5; + for (i = 0; i < priv->num_sensors; i++) + p2[i] = (base1 + p2[i]) << 2; + fallthrough; + case ONE_PT_CALIB2: + base0 = (cdata[2] & MSM8939_BASE0_MASK) >> MSM8939_BASE0_SHIFT; + p1[0] = (cdata[0] & MSM8939_S0_P1_MASK) >> MSM8939_S0_P1_SHIFT; + p1[1] = (cdata[0] & MSM8939_S1_P1_MASK) >> MSM8939_S1_P1_SHIFT; + p1[2] = (cdata[0] & MSM8939_S2_P1_MASK_0_4) >> MSM8939_S2_P1_SHIFT_0_4; + p1[2] |= ((cdata[1] & MSM8939_S2_P1_MASK_5) >> MSM8939_S2_P1_SHIFT_5) << 5; + p1[3] = (cdata[1] & MSM8939_S3_P1_MASK) >> MSM8939_S3_P1_SHIFT; + p1[4] = (cdata[1] & MSM8939_S4_P1_MASK) >> MSM8939_S4_P1_SHIFT; + p1[5] = (cdata[2] & MSM8939_S5_P1_MASK) >> MSM8939_S5_P1_SHIFT; + p1[6] = (cdata[2] & MSM8939_S6_P1_MASK) >> MSM8939_S6_P1_SHIFT; + p1[7] = (cdata[3] & MSM8939_S7_P1_MASK) >> MSM8939_S7_P1_SHIFT; + p1[8] = (cdata[3] & MSM8939_S8_P1_MASK) >> MSM8939_S8_P1_SHIFT; + p1[9] = (cdata[4] & MSM8939_S9_P1_MASK) >> MSM8939_S9_P1_SHIFT; + for (i = 0; i < priv->num_sensors; i++) + p1[i] = ((base0) + p1[i]) << 2; + break; + default: + for (i = 0; i < priv->num_sensors; i++) { + p1[i] = 500; + p2[i] = 780; + } + break; + } + + compute_intercept_slope(priv, p1, p2, mode); + kfree(qfprom_cdata); + + return 0; +} + static int calibrate_8974(struct tsens_priv *priv) { int base1 = 0, base2 = 0, i; @@ -325,7 +452,7 @@ static int calibrate_8974(struct tsens_priv *priv) return 0; } -/* v0.1: 8916, 8974 */ +/* v0.1: 8916, 8939, 8974 */ static struct tsens_features tsens_v0_1_feat = { .ver_major = VER_0_1, @@ -386,6 +513,21 @@ struct tsens_plat_data data_8916 = { .fields = tsens_v0_1_regfields, }; +static const struct tsens_ops ops_8939 = { + .init = init_common, + .calibrate = calibrate_8939, + .get_temp = get_temp_common, +}; + +struct tsens_plat_data data_8939 = { + .num_sensors = 10, + .ops = &ops_8939, + .hw_ids = (unsigned int []){ 0, 1, 2, 4, 5, 6, 7, 8, 9, 10 }, + + .feat = &tsens_v0_1_feat, + .fields = tsens_v0_1_regfields, +}; + static const struct tsens_ops ops_8974 = { .init = init_common, .calibrate = calibrate_8974, diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 8d3e94d2a9ed..52656a24f813 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -897,6 +897,9 @@ static const struct of_device_id tsens_table[] = { { .compatible = "qcom,msm8916-tsens", .data = &data_8916, + }, { + .compatible = "qcom,msm8939-tsens", + .data = &data_8939, }, { .compatible = "qcom,msm8974-tsens", .data = &data_8974, diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 59d01162c66a..f40b625f897e 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -585,7 +585,7 @@ int get_temp_common(const struct tsens_sensor *s, int *temp); extern struct tsens_plat_data data_8960; /* TSENS v0.1 targets */ -extern struct tsens_plat_data data_8916, data_8974; +extern struct tsens_plat_data data_8916, data_8939, data_8974; /* TSENS v1 targets */ extern struct tsens_plat_data data_tsens_v1, data_8976;