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[73.185.129.58]) by smtp.gmail.com with ESMTPSA id u10sm555500iow.38.2020.06.29.14.49.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jun 2020 14:49:23 -0700 (PDT) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org Cc: evgreen@chromium.org, subashab@codeaurora.org, cpratapa@codeaurora.org, bjorn.andersson@linaro.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 1/5] net: ipa: head-of-line block registers are RX only Date: Mon, 29 Jun 2020 16:49:15 -0500 Message-Id: <20200629214919.1196017-2-elder@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200629214919.1196017-1-elder@linaro.org> References: <20200629214919.1196017-1-elder@linaro.org> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The INIT_HOL_BLOCK_EN and INIT_HOL_BLOCK_TIMER endpoint registers are only valid for RX endpoints. Have ipa_endpoint_modem_hol_block_clear_all() skip writing these registers for TX endpoints. Signed-off-by: Alex Elder --- drivers/net/ipa/ipa_endpoint.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/drivers/net/ipa/ipa_endpoint.c b/drivers/net/ipa/ipa_endpoint.c index 9f50d0d11704..3f5a41fc1997 100644 --- a/drivers/net/ipa/ipa_endpoint.c +++ b/drivers/net/ipa/ipa_endpoint.c @@ -642,6 +642,8 @@ static int ipa_endpoint_init_hol_block_timer(struct ipa_endpoint *endpoint, u32 offset; u32 val; + /* assert(!endpoint->toward_ipa); */ + /* XXX We'll fix this when the register definition is clear */ if (microseconds) { struct device *dev = &ipa->pdev->dev; @@ -671,6 +673,8 @@ ipa_endpoint_init_hol_block_enable(struct ipa_endpoint *endpoint, bool enable) u32 offset; u32 val; + /* assert(!endpoint->toward_ipa); */ + val = u32_encode_bits(enable ? 1 : 0, HOL_BLOCK_EN_FMASK); offset = IPA_REG_ENDP_INIT_HOL_BLOCK_EN_N_OFFSET(endpoint_id); iowrite32(val, endpoint->ipa->reg_virt + offset); @@ -683,7 +687,7 @@ void ipa_endpoint_modem_hol_block_clear_all(struct ipa *ipa) for (i = 0; i < IPA_ENDPOINT_MAX; i++) { struct ipa_endpoint *endpoint = &ipa->endpoint[i]; - if (endpoint->ee_id != GSI_EE_MODEM) + if (endpoint->toward_ipa || endpoint->ee_id != GSI_EE_MODEM) continue; (void)ipa_endpoint_init_hol_block_timer(endpoint, 0); From patchwork Mon Jun 29 21:49:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 192028 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp3253570ilg; Mon, 29 Jun 2020 14:50:20 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyfgK1ieHetPIDxJATYnKJpwuU4p1/fBIpH/XDcUAkpZW5k/2Jxc7cYMEu7v/2Z4ZPCEcaI X-Received: by 2002:a50:b086:: with SMTP id j6mr16986178edd.6.1593467420346; Mon, 29 Jun 2020 14:50:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593467420; cv=none; d=google.com; s=arc-20160816; b=eNA7iXUh8TGoGHZ9qslZIf1WwV2PZFMZPsv+elJSRSZEGSUluzH9Ta8P+2Qt6RZm1M XI7M6bPCxGqzLhkqcQT94MROeAYJBtIMx2GAGMB2izGUhxpaR9Iu9aGa126gJuapMErp 9gwRwfKh288+9LKgNBwiR5Cz6GsCFvqiWzDp5NqQ+jcotC2JqmWUvzSnID+w1zv+FigO wmJ2nbHcDganZZu6M75iAquuDpqvr+TO+TH6x9YuXVRONlajaskx4al04XLjU1HgVduf kD99fQt5ae0va+G2LRiRhPFGudQ+BMjyOAqFXb1VxQ285SzsJzKTlC/BRO1qYqsS+764 AO/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Il6tZPozA+81DRifdvTR8dOWxcR0CVn20QskeLQXSZw=; b=fQwovBfGdrAgf7kbVaMvr5d9nlFsn1nfibgn6DZ7pff7s24QbqwpOAM0jycBBeWmbH Wa+NCqEOnxXn+nSCoM/vV5csA3lq3bcTkVTVo6q9McUBl0daVqnoANXtO7RVqZ1RetQc 5SN57OgrdWwm1+/75xV0+3/cCwBP3nePfPmQ78eHCdphRYWTxIjI/qo7U6gvF/I5SiyB /0dfHcPAw6ZAoA/ji4XmypIMOK3a13DIEafO+iv35UiADKZU/J01DrIKr2nOEwPocpYL mIOlEVsGbJhM9dORASNZs5/lE3p/pAUVG2EtQeXLZzfdIOvBKSxGeWrKWRUqP1RrsID7 tMrQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lqVFoan+; spf=pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[73.185.129.58]) by smtp.gmail.com with ESMTPSA id u10sm555500iow.38.2020.06.29.14.49.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jun 2020 14:49:24 -0700 (PDT) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org Cc: evgreen@chromium.org, subashab@codeaurora.org, cpratapa@codeaurora.org, bjorn.andersson@linaro.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 2/5] net: ipa: metadata_mask register is RX only Date: Mon, 29 Jun 2020 16:49:16 -0500 Message-Id: <20200629214919.1196017-3-elder@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200629214919.1196017-1-elder@linaro.org> References: <20200629214919.1196017-1-elder@linaro.org> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The INIT_HDR_METADATA_MASK endpoint configuration register is only valid for RX endpoints. Rather than writing a zero to that register for TX endpoints, avoid writing the register at all. Signed-off-by: Alex Elder --- drivers/net/ipa/ipa_endpoint.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/drivers/net/ipa/ipa_endpoint.c b/drivers/net/ipa/ipa_endpoint.c index 3f5a41fc1997..0c2bec166066 100644 --- a/drivers/net/ipa/ipa_endpoint.c +++ b/drivers/net/ipa/ipa_endpoint.c @@ -527,10 +527,12 @@ static void ipa_endpoint_init_hdr_metadata_mask(struct ipa_endpoint *endpoint) u32 val = 0; u32 offset; + /* assert(!endpoint->toward_ipa); */ + offset = IPA_REG_ENDP_INIT_HDR_METADATA_MASK_N_OFFSET(endpoint_id); /* Note that HDR_ENDIANNESS indicates big endian header fields */ - if (!endpoint->toward_ipa && endpoint->data->qmap) + if (endpoint->data->qmap) val = cpu_to_be32(IPA_ENDPOINT_QMAP_METADATA_MASK); iowrite32(val, endpoint->ipa->reg_virt + offset); @@ -1306,10 +1308,10 @@ static void ipa_endpoint_program(struct ipa_endpoint *endpoint) (void)ipa_endpoint_program_suspend(endpoint, false); ipa_endpoint_init_hdr_ext(endpoint); ipa_endpoint_init_aggr(endpoint); + ipa_endpoint_init_hdr_metadata_mask(endpoint); } ipa_endpoint_init_cfg(endpoint); ipa_endpoint_init_hdr(endpoint); - ipa_endpoint_init_hdr_metadata_mask(endpoint); ipa_endpoint_init_mode(endpoint); ipa_endpoint_status(endpoint); } From patchwork Mon Jun 29 21:49:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 192026 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp3253282ilg; Mon, 29 Jun 2020 14:49:50 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw7+KhjeewRiCLXZTMV0RzzBmlgveviYShXx5ApubPw/8hEXgrURIsYoFui/SLyRO0vk9mf X-Received: by 2002:a50:bc03:: with SMTP id j3mr20304415edh.234.1593467390001; Mon, 29 Jun 2020 14:49:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593467389; cv=none; d=google.com; s=arc-20160816; b=ql4MBpDCpKXGNoZx5N9aTmcdJAW5jeENGdqBeUQGxtXqtDtY42xTqjs90X8OF0kvVr LFXnW5UmxI8A6BHkd6s9gADGw1DY+PGqRRKRffF72pPdvQfVsPVXvzxbjxD587KzdafF VUnaB8V0WXZlUBYlKiFg/7HlWIk2Xamz3JpbV1gruCxKQZdeGQVN8BCBB/VnA4maDSad mYtAjO/eR1+oC5DiXwe5gpnzC6LB68FW/GVyOroUM77MKVotN9Flpn8lav/HqSlAosES BcIOhoywL88V42VChYMXF//iAn5ExqlGaG1+I6qvw+0oOnWSgNQr8g6pyD1lzmTnZ/U0 TQqw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Z6Es3pTicfd51NnmXVOTn4bo+Yv9sluHPfJcIe1Ma9M=; b=tjy2DD8tP8gEspiUGMCjJY97M3JCyHtUqR8xng5x4f7LYDUlxL7o89OOFDq+0rcLog yqtC4qPpqr1XQ99f4qOomC6/ysYPdQNGbjvR6TPNbn56WAcSDpD05eYTtmW1g8SQnpWm YispdN4maBMmjQUYSanzDwgGh8hOv+eGyB8bbvhCvaLCSRj3vzLYc6Jzkz1m0YMPAX0V jQV3KcHNOflvvXEge8sYs0cvs1Fx2kcMvWVV6ZaoHidoMOsf/T5494/8n7QIJdrpV76l X5nbEqUxFRMICcWtv/Gme30hrRd10d3seH3bsoOVaz9z2SxtxweHGtWcUDyYJCJbL5cA +dGw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Eqm3Ws9n; spf=pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[73.185.129.58]) by smtp.gmail.com with ESMTPSA id u10sm555500iow.38.2020.06.29.14.49.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jun 2020 14:49:25 -0700 (PDT) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org Cc: evgreen@chromium.org, subashab@codeaurora.org, cpratapa@codeaurora.org, bjorn.andersson@linaro.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 3/5] net: ipa: mode register is TX only Date: Mon, 29 Jun 2020 16:49:17 -0500 Message-Id: <20200629214919.1196017-4-elder@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200629214919.1196017-1-elder@linaro.org> References: <20200629214919.1196017-1-elder@linaro.org> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The INIT_MODE endpoint configuration register is only valid for TX endpoints. Rather than writing a zero to that register for RX endpoints, avoid writing the register at all. Add assertion comments communicating that TX endpoints are assumed for the DEAGGR and SEQ endpoint configuration registers to be consistent. Signed-off-by: Alex Elder --- drivers/net/ipa/ipa_endpoint.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) -- 2.25.1 diff --git a/drivers/net/ipa/ipa_endpoint.c b/drivers/net/ipa/ipa_endpoint.c index 0c2bec166066..ee8fc22c3abc 100644 --- a/drivers/net/ipa/ipa_endpoint.c +++ b/drivers/net/ipa/ipa_endpoint.c @@ -543,7 +543,9 @@ static void ipa_endpoint_init_mode(struct ipa_endpoint *endpoint) u32 offset = IPA_REG_ENDP_INIT_MODE_N_OFFSET(endpoint->endpoint_id); u32 val; - if (endpoint->toward_ipa && endpoint->data->dma_mode) { + /* assert(endpoint->toward_ipa); */ + + if (endpoint->data->dma_mode) { enum ipa_endpoint_name name = endpoint->data->dma_endpoint; u32 dma_endpoint_id; @@ -554,7 +556,7 @@ static void ipa_endpoint_init_mode(struct ipa_endpoint *endpoint) } else { val = u32_encode_bits(IPA_BASIC, MODE_FMASK); } - /* Other bitfields unspecified (and 0) */ + /* All other bits unspecified (and 0) */ iowrite32(val, endpoint->ipa->reg_virt + offset); } @@ -702,6 +704,8 @@ static void ipa_endpoint_init_deaggr(struct ipa_endpoint *endpoint) u32 offset = IPA_REG_ENDP_INIT_DEAGGR_N_OFFSET(endpoint->endpoint_id); u32 val = 0; + /* assert(endpoint->toward_ipa); */ + /* DEAGGR_HDR_LEN is 0 */ /* PACKET_OFFSET_VALID is 0 */ /* PACKET_OFFSET_LOCATION is ignored (not valid) */ @@ -716,6 +720,8 @@ static void ipa_endpoint_init_seq(struct ipa_endpoint *endpoint) u32 seq_type = endpoint->seq_type; u32 val = 0; + /* assert(endpoint->toward_ipa); */ + /* Sequencer type is made up of four nibbles */ val |= u32_encode_bits(seq_type & 0xf, HPS_SEQ_TYPE_FMASK); val |= u32_encode_bits((seq_type >> 4) & 0xf, DPS_SEQ_TYPE_FMASK); @@ -1303,6 +1309,7 @@ static void ipa_endpoint_program(struct ipa_endpoint *endpoint) ipa_endpoint_init_aggr(endpoint); ipa_endpoint_init_deaggr(endpoint); ipa_endpoint_init_seq(endpoint); + ipa_endpoint_init_mode(endpoint); } else { if (endpoint->ipa->version == IPA_VERSION_3_5_1) (void)ipa_endpoint_program_suspend(endpoint, false); @@ -1312,7 +1319,6 @@ static void ipa_endpoint_program(struct ipa_endpoint *endpoint) } ipa_endpoint_init_cfg(endpoint); ipa_endpoint_init_hdr(endpoint); - ipa_endpoint_init_mode(endpoint); ipa_endpoint_status(endpoint); } From patchwork Mon Jun 29 21:49:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 192027 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp3253305ilg; Mon, 29 Jun 2020 14:49:52 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz2ANbBuVKIlre9bEq0Tv/xjuWTYu4+I4Bn0GF+614jo+hk4CRRnS0T7TO8H1jHzBu0SY4R X-Received: by 2002:aa7:c15a:: with SMTP id r26mr19018395edp.21.1593467392726; Mon, 29 Jun 2020 14:49:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593467392; cv=none; d=google.com; s=arc-20160816; b=IaIKIUFOQLxWIend5uuqyXzahlu8HDyH+I4SOKdOgFH2u3bUsAiuXQ9u7DoAh36GTY 6AO/eA5AheloLGx4uFTbYutGmh0d3XBVN4zom+/OFz5CGDDBOjDsFtR58LCZpTDSLYpZ dZDQVYtjNPb6Wh6+ONbCJadM7PFacUXQMStGYJ4XKOc0iD8mAteu/Beh+2YOglHjClkf lRojKjrDKSWn7WBKfZ5dEx5lbMVM2jwmC8iO1iYkJCtDYyoVH2xpBVBLOF5ZnKoreVG9 RjKAy6ISHNFa15QlYk3Bz8FbCDk9+/6zgUcsTZQp5lckKUcnLrTshCi66bJW03WRyttW l9TQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=UVmv87Qr1j8KuR4CHHUPvULFMEa3w3NlP5if+cF+DAQ=; b=IPnKyuKJ6thh8U/qlOmhe4I6Ny4KFfTj73wtocw3viAbACmpbvAtYkiAB+HU1q2dII A4QySJfb3WzeC11gnV2aWN9/dEtUv0qwFrks8bfzoZ1LQCV4MmJ9YyKObS9BxnqUSnZc LqSELemsZUkpzJdj3ht3l63k7BNZtr5Vl8uaERDZdOQbfmdazdlUVqXVPxaDepJAEyav bN9W2K5rBURu7UQUafG9zht8HEWZRa5NgDzDu4skmZrGMVkdrUj46Fb36/VaR2OIEty4 vUt7Fpl2Hj04hYw3lHvV7kzB7agwK35hENkfnIbFlbysrbHgEWfh4PBZmHNvicPNwsh1 OtwA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Jqf6BHa+; spf=pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[73.185.129.58]) by smtp.gmail.com with ESMTPSA id u10sm555500iow.38.2020.06.29.14.49.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jun 2020 14:49:26 -0700 (PDT) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org Cc: evgreen@chromium.org, subashab@codeaurora.org, cpratapa@codeaurora.org, bjorn.andersson@linaro.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 4/5] net: ipa: clarify endpoint register macro constraints Date: Mon, 29 Jun 2020 16:49:18 -0500 Message-Id: <20200629214919.1196017-5-elder@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200629214919.1196017-1-elder@linaro.org> References: <20200629214919.1196017-1-elder@linaro.org> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org A handful of registers are valid only for RX endpoints, and some others are valid only for TX endpoints. For these endpoints, add a comment above their defined offset macro that indicates the endpoints to which they apply. Extend the endpoint parameter naming convention as well, to make these constraints more explicit. Signed-off-by: Alex Elder --- drivers/net/ipa/ipa_reg.h | 43 +++++++++++++++++++++++---------------- 1 file changed, 25 insertions(+), 18 deletions(-) -- 2.25.1 diff --git a/drivers/net/ipa/ipa_reg.h b/drivers/net/ipa/ipa_reg.h index 0a688d8c1d7c..10e4ac9ead68 100644 --- a/drivers/net/ipa/ipa_reg.h +++ b/drivers/net/ipa/ipa_reg.h @@ -32,10 +32,12 @@ struct ipa; * parameter is supplied to the offset macro. The "ee" value is a member of * the gsi_ee enumerated type. * - * The offset of a register dependent on endpoint id is computed by a macro - * that is supplied a parameter "ep". The "ep" value is assumed to be less - * than the maximum endpoint value for the current hardware, and that will - * not exceed IPA_ENDPOINT_MAX. + * The offset of a register dependent on endpoint ID is computed by a macro + * that is supplied a parameter "ep", "txep", or "rxep". A register with an + * "ep" parameter is valid for any endpoint; a register with a "txep" or + * "rxep" parameter is valid only for TX or RX endpoints, respectively. The + * "*ep" value is assumed to be less than the maximum valid endpoint ID + * for the current hardware, and that will not exceed IPA_ENDPOINT_MAX. * * The offset of registers related to filter and route tables is computed * by a macro that is supplied a parameter "er". The "er" represents an @@ -293,11 +295,13 @@ static inline u32 ipa_reg_idle_indication_cfg_offset(enum ipa_version version) #define HDR_TOTAL_LEN_OR_PAD_OFFSET_FMASK GENMASK(9, 4) #define HDR_PAD_TO_ALIGNMENT_FMASK GENMASK(13, 10) -#define IPA_REG_ENDP_INIT_HDR_METADATA_MASK_N_OFFSET(ep) \ - (0x00000818 + 0x0070 * (ep)) +/* Valid only for RX (IPA producer) endpoints */ +#define IPA_REG_ENDP_INIT_HDR_METADATA_MASK_N_OFFSET(rxep) \ + (0x00000818 + 0x0070 * (rxep)) -#define IPA_REG_ENDP_INIT_MODE_N_OFFSET(ep) \ - (0x00000820 + 0x0070 * (ep)) +/* Valid only for TX (IPA consumer) endpoints */ +#define IPA_REG_ENDP_INIT_MODE_N_OFFSET(txep) \ + (0x00000820 + 0x0070 * (txep)) #define MODE_FMASK GENMASK(2, 0) #define DEST_PIPE_INDEX_FMASK GENMASK(8, 4) #define BYTE_THRESHOLD_FMASK GENMASK(27, 12) @@ -316,19 +320,21 @@ static inline u32 ipa_reg_idle_indication_cfg_offset(enum ipa_version version) #define AGGR_FORCE_CLOSE_FMASK GENMASK(22, 22) #define AGGR_HARD_BYTE_LIMIT_ENABLE_FMASK GENMASK(24, 24) -#define IPA_REG_ENDP_INIT_HOL_BLOCK_EN_N_OFFSET(ep) \ - (0x0000082c + 0x0070 * (ep)) +/* Valid only for RX (IPA producer) endpoints */ +#define IPA_REG_ENDP_INIT_HOL_BLOCK_EN_N_OFFSET(rxep) \ + (0x0000082c + 0x0070 * (rxep)) #define HOL_BLOCK_EN_FMASK GENMASK(0, 0) -/* The next register is valid only for RX (IPA producer) endpoints */ -#define IPA_REG_ENDP_INIT_HOL_BLOCK_TIMER_N_OFFSET(ep) \ - (0x00000830 + 0x0070 * (ep)) +/* Valid only for RX (IPA producer) endpoints */ +#define IPA_REG_ENDP_INIT_HOL_BLOCK_TIMER_N_OFFSET(rxep) \ + (0x00000830 + 0x0070 * (rxep)) /* The next fields are present for IPA v4.2 only */ #define BASE_VALUE_FMASK GENMASK(4, 0) #define SCALE_FMASK GENMASK(12, 8) -#define IPA_REG_ENDP_INIT_DEAGGR_N_OFFSET(ep) \ - (0x00000834 + 0x0070 * (ep)) +/* Valid only for TX (IPA consumer) endpoints */ +#define IPA_REG_ENDP_INIT_DEAGGR_N_OFFSET(txep) \ + (0x00000834 + 0x0070 * (txep)) #define DEAGGR_HDR_LEN_FMASK GENMASK(5, 0) #define PACKET_OFFSET_VALID_FMASK GENMASK(7, 7) #define PACKET_OFFSET_LOCATION_FMASK GENMASK(13, 8) @@ -338,8 +344,9 @@ static inline u32 ipa_reg_idle_indication_cfg_offset(enum ipa_version version) (0x00000838 + 0x0070 * (ep)) #define RSRC_GRP_FMASK GENMASK(1, 0) -#define IPA_REG_ENDP_INIT_SEQ_N_OFFSET(ep) \ - (0x0000083c + 0x0070 * (ep)) +/* Valid only for TX (IPA consumer) endpoints */ +#define IPA_REG_ENDP_INIT_SEQ_N_OFFSET(txep) \ + (0x0000083c + 0x0070 * (txep)) #define HPS_SEQ_TYPE_FMASK GENMASK(3, 0) #define DPS_SEQ_TYPE_FMASK GENMASK(7, 4) #define HPS_REP_SEQ_TYPE_FMASK GENMASK(11, 8) @@ -353,7 +360,7 @@ static inline u32 ipa_reg_idle_indication_cfg_offset(enum ipa_version version) /* The next field is present for IPA v4.0 and above */ #define STATUS_PKT_SUPPRESS_FMASK GENMASK(9, 9) -/* "er" is either an endpoint id (for filters) or a route id (for routes) */ +/* "er" is either an endpoint ID (for filters) or a route ID (for routes) */ #define IPA_REG_ENDP_FILTER_ROUTER_HSH_CFG_N_OFFSET(er) \ (0x0000085c + 0x0070 * (er)) #define FILTER_HASH_MSK_SRC_ID_FMASK GENMASK(0, 0) From patchwork Mon Jun 29 21:49:19 2020 Content-Type: text/plain; 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[73.185.129.58]) by smtp.gmail.com with ESMTPSA id u10sm555500iow.38.2020.06.29.14.49.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jun 2020 14:49:27 -0700 (PDT) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org Cc: evgreen@chromium.org, subashab@codeaurora.org, cpratapa@codeaurora.org, bjorn.andersson@linaro.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 5/5] net: ipa: HOL_BLOCK_EN_FMASK is a 1-bit mask Date: Mon, 29 Jun 2020 16:49:19 -0500 Message-Id: <20200629214919.1196017-6-elder@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200629214919.1196017-1-elder@linaro.org> References: <20200629214919.1196017-1-elder@linaro.org> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The convention throughout the IPA driver is to directly use single-bit field mask values, rather than using (for example) u32_encode_bits() to set or clear them. Fix the one place that doesn't follow that convention, which sets HOL_BLOCK_EN_FMASK in ipa_endpoint_init_hol_block_enable(). Signed-off-by: Alex Elder --- drivers/net/ipa/ipa_endpoint.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.25.1 diff --git a/drivers/net/ipa/ipa_endpoint.c b/drivers/net/ipa/ipa_endpoint.c index ee8fc22c3abc..447dafab8f18 100644 --- a/drivers/net/ipa/ipa_endpoint.c +++ b/drivers/net/ipa/ipa_endpoint.c @@ -679,7 +679,7 @@ ipa_endpoint_init_hol_block_enable(struct ipa_endpoint *endpoint, bool enable) /* assert(!endpoint->toward_ipa); */ - val = u32_encode_bits(enable ? 1 : 0, HOL_BLOCK_EN_FMASK); + val = enable ? HOL_BLOCK_EN_FMASK : 0; offset = IPA_REG_ENDP_INIT_HOL_BLOCK_EN_N_OFFSET(endpoint_id); iowrite32(val, endpoint->ipa->reg_virt + offset); }