From patchwork Wed Aug 9 10:07:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 109699 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp646379qge; Wed, 9 Aug 2017 03:08:52 -0700 (PDT) X-Received: by 10.99.125.87 with SMTP id m23mr7097121pgn.10.1502273332518; Wed, 09 Aug 2017 03:08:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1502273332; cv=none; d=google.com; s=arc-20160816; b=z3iJ48/9c9nHbJmFbE+LbQdaW/T+WzG3A8hgJEPhR/lZndJxAVKygJRU1ofnOmvPt+ Wmzk8JMZ0TCn+J2BkGDRn0UWxIrwj/Geuh1m7JrVp4QmDtrQwkgJMlgsaU2Y0+ulJATe qfcYqoowM/Wgk0ZW6btPPUZGlhndDlVT7vk7DHA/n4UNmid6uBeO/A3Q/3GNIq0TpuFS dSYn/8dLmJx1L5ewejBxus3L5Idw8gCauaNKXCKH8jWxuOBwfpQiSk5uFl9BAUk/6Wk8 z1P9fbxDfavD7Hd62HSZEmHEHwAuzJTWGvGNktmhm/Wa8mzglLYSCNwSIpDBDDoWuKcs s4Ng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=5vnWk1Emw+HXcoY4a/ALHLSuDuKSdTt9/jzQc2G36TM=; b=w1NLZ5QTPIfy9sOvbC7GaPTBSCs/n04RGOHFm9VAMPQROTw5bq8DwQofzPNzkxcYqu SDNwCr4xoFWqgJzCD7CuEHXLwALmZHyxObuk+Re4KMNevSvs6s3ItyBjxQa3a11Y14dP RMYQiHgr1ULla0AlIxphNQqQJssIccL7z4/SY5ehTdDrPP2bv6HDLTOhCZjmhPeyhK60 VjS14V0hqaJJVakAZRIai54jv2XSWuwAx0UdJGQEr8nDdNXwqOlgWXuMYVtmgIVT+cA0 4htfqL0DQvBQcG7edLhlDIT4onD04jXRkk6A49qoLo+RDkNa2gzpTOm2acwGdJOLN7Ll VOgA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v7si2201572pgb.858.2017.08.09.03.08.52; Wed, 09 Aug 2017 03:08:52 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752836AbdHIKIu (ORCPT + 7 others); Wed, 9 Aug 2017 06:08:50 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:2598 "EHLO szxga05-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752764AbdHIKIs (ORCPT ); Wed, 9 Aug 2017 06:08:48 -0400 Received: from 172.30.72.59 (EHLO DGGEMS414-HUB.china.huawei.com) ([172.30.72.59]) by dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DEW41313; Wed, 09 Aug 2017 18:08:44 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.203.177.212) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.301.0; Wed, 9 Aug 2017 18:08:33 +0800 From: Shameer Kolothum To: , , , , , CC: , , , , , , , , , Shameer Kolothum Subject: [PATCH v6 1/3] ACPI/IORT: Add ITS address regions reservation helper Date: Wed, 9 Aug 2017 11:07:13 +0100 Message-ID: <20170809100715.870516-2-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20170809100715.870516-1-shameerali.kolothum.thodi@huawei.com> References: <20170809100715.870516-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.177.212] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020206.598ADF2D.004A, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: b4d000b63f1b84b13a1d3f66784a1115 Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org On some platforms ITS address regions have to be excluded from normal IOVA allocation in that they are detected and decoded in a HW specific way by system components and so they cannot be considered normal IOVA address space. Add an helper function that retrieves ITS address regions through IORT device <-> ITS mappings and reserves it so that these regions will not be translated by IOMMU and will be excluded from IOVA allocations. Signed-off-by: Shameer Kolothum [lorenzo.pieralisi@arm.com: updated commit log/added comments] Signed-off-by: Lorenzo Pieralisi --- drivers/acpi/arm64/iort.c | 95 ++++++++++++++++++++++++++++++++++++++-- drivers/irqchip/irq-gic-v3-its.c | 3 +- include/linux/acpi_iort.h | 7 ++- 3 files changed, 100 insertions(+), 5 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c index a3215ee..86b5a51 100644 --- a/drivers/acpi/arm64/iort.c +++ b/drivers/acpi/arm64/iort.c @@ -39,6 +39,7 @@ struct iort_its_msi_chip { struct list_head list; struct fwnode_handle *fw_node; + phys_addr_t base_addr; u32 translation_id; }; @@ -136,14 +137,16 @@ typedef acpi_status (*iort_find_node_callback) static DEFINE_SPINLOCK(iort_msi_chip_lock); /** - * iort_register_domain_token() - register domain token and related ITS ID - * to the list from where we can get it back later on. + * iort_register_domain_token() - register domain token along with related + * ITS ID and base address to the list from where we can get it back later on. * @trans_id: ITS ID. + * @base: ITS base address. * @fw_node: Domain token. * * Returns: 0 on success, -ENOMEM if no memory when allocating list element */ -int iort_register_domain_token(int trans_id, struct fwnode_handle *fw_node) +int iort_register_domain_token(int trans_id, phys_addr_t base, + struct fwnode_handle *fw_node) { struct iort_its_msi_chip *its_msi_chip; @@ -153,6 +156,7 @@ int iort_register_domain_token(int trans_id, struct fwnode_handle *fw_node) its_msi_chip->fw_node = fw_node; its_msi_chip->translation_id = trans_id; + its_msi_chip->base_addr = base; spin_lock(&iort_msi_chip_lock); list_add(&its_msi_chip->list, &iort_msi_chip_list); @@ -481,6 +485,24 @@ int iort_pmsi_get_dev_id(struct device *dev, u32 *dev_id) return -ENODEV; } +static int __maybe_unused iort_find_its_base(u32 its_id, phys_addr_t *base) +{ + struct iort_its_msi_chip *its_msi_chip; + bool match = false; + + spin_lock(&iort_msi_chip_lock); + list_for_each_entry(its_msi_chip, &iort_msi_chip_list, list) { + if (its_msi_chip->translation_id == its_id) { + *base = its_msi_chip->base_addr; + match = true; + break; + } + } + spin_unlock(&iort_msi_chip_lock); + + return match ? 0 : -ENODEV; +} + /** * iort_dev_find_its_id() - Find the ITS identifier for a device * @dev: The device. @@ -639,6 +661,71 @@ int iort_add_device_replay(const struct iommu_ops *ops, struct device *dev) return err; } + +/** + * iort_iommu_its_get_resv_regions - Reserved region driver helper + * @dev: Device from iommu_get_resv_regions() + * @list: Reserved region list from iommu_get_resv_regions() + * + * Returns: Number of reserved regions on success(0 if no associated ITS), + * appropriate error value otherwise. + */ +int iort_iommu_its_get_resv_regions(struct device *dev, struct list_head *head) +{ + struct acpi_iort_its_group *its; + struct acpi_iort_node *node, *its_node = NULL; + int i, resv = 0; + + node = iort_find_dev_node(dev); + if (!node) + return -ENODEV; + + /* + * Current logic to reserve ITS regions relies on HW topologies + * where a given PCI or named component maps its IDs to only one + * ITS group; if a PCI or named component can map its IDs to + * different ITS groups through IORT mappings this function has + * to be reworked to ensure we reserve regions for all ITS groups + * a given PCI or named component may map IDs to. + */ + if (dev_is_pci(dev)) { + u32 rid; + + pci_for_each_dma_alias(to_pci_dev(dev), __get_pci_rid, &rid); + its_node = iort_node_map_id(node, rid, NULL, IORT_MSI_TYPE); + } else { + for (i = 0; i < node->mapping_count; i++) { + its_node = iort_node_map_platform_id(node, NULL, + IORT_MSI_TYPE, i); + if (its_node) + break; + } + } + + if (!its_node) + return 0; + + /* Move to ITS specific data */ + its = (struct acpi_iort_its_group *)its_node->node_data; + + for (i = 0; i < its->its_count; i++) { + phys_addr_t base; + + if (!iort_find_its_base(its->identifiers[i], &base)) { + int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO; + struct iommu_resv_region *region; + + region = iommu_alloc_resv_region(base, SZ_128K, prot, + IOMMU_RESV_MSI); + if (region) { + list_add_tail(®ion->list, head); + resv++; + } + } + } + + return (resv == its->its_count) ? resv : -ENODEV; +} #else static inline const struct iommu_ops *iort_fwspec_iommu_ops(struct iommu_fwspec *fwspec) @@ -646,6 +733,8 @@ const struct iommu_ops *iort_fwspec_iommu_ops(struct iommu_fwspec *fwspec) static inline int iort_add_device_replay(const struct iommu_ops *ops, struct device *dev) { return 0; } +int iort_iommu_its_get_resv_regions(struct device *dev, struct list_head *head) +{ return -ENODEV; } #endif static const struct iommu_ops *iort_iommu_xlate(struct device *dev, diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index 6893287..77322b3 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -1928,7 +1928,8 @@ static int __init gic_acpi_parse_madt_its(struct acpi_subtable_header *header, return -ENOMEM; } - err = iort_register_domain_token(its_entry->translation_id, dom_handle); + err = iort_register_domain_token(its_entry->translation_id, res.start, + dom_handle); if (err) { pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n", &res.start, its_entry->translation_id); diff --git a/include/linux/acpi_iort.h b/include/linux/acpi_iort.h index 8379d40..d7ed49c 100644 --- a/include/linux/acpi_iort.h +++ b/include/linux/acpi_iort.h @@ -26,7 +26,8 @@ #define IORT_IRQ_MASK(irq) (irq & 0xffffffffULL) #define IORT_IRQ_TRIGGER_MASK(irq) ((irq >> 32) & 0xffffffffULL) -int iort_register_domain_token(int trans_id, struct fwnode_handle *fw_node); +int iort_register_domain_token(int trans_id, phys_addr_t base, + struct fwnode_handle *fw_node); void iort_deregister_domain_token(int trans_id); struct fwnode_handle *iort_find_domain_token(int trans_id); #ifdef CONFIG_ACPI_IORT @@ -38,6 +39,7 @@ /* IOMMU interface */ void iort_set_dma_mask(struct device *dev); const struct iommu_ops *iort_iommu_configure(struct device *dev); +int iort_iommu_its_get_resv_regions(struct device *dev, struct list_head *head); #else static inline void acpi_iort_init(void) { } static inline u32 iort_msi_map_rid(struct device *dev, u32 req_id) @@ -51,6 +53,9 @@ static inline void iort_set_dma_mask(struct device *dev) { } static inline const struct iommu_ops *iort_iommu_configure(struct device *dev) { return NULL; } +static inline +int iort_iommu_its_get_resv_regions(struct device *dev, struct list_head *head) +{ return -ENODEV; } #endif #endif /* __ACPI_IORT_H__ */ From patchwork Wed Aug 9 10:07:14 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 109700 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp646443qge; Wed, 9 Aug 2017 03:08:55 -0700 (PDT) X-Received: by 10.98.89.66 with SMTP id n63mr7522143pfb.137.1502273335161; Wed, 09 Aug 2017 03:08:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1502273335; cv=none; d=google.com; s=arc-20160816; b=gxUhhIBfN0bKZ/Jzo9wkoM4+dvIhHmmwRDL/7CdbEEYpkOWdE/tylNVA6QTroq1yNa o0gh6jbkwjb6CBZIHM8WrrjmpsPnrMUga3dy+8bUqFAmaTSU+EV+hrjPvove0t6BDNd4 6z4DILDxX3Fa+mavs1BXOzDnBdRqQm/EudIIBPAZVnMpbTx4R67Ey38uCuLz41vGS6P/ QzmJxRWvDPIaFP8Yr94va5hamAXxfuAdZ0tUzAY4fK8QE+5Pv8v2C39W0KeE3mHdLR0X HiwWa84mI11sadTkau45/6NhfrDgm3b0j4DEtrJ32ZcfdYddHPD2Hnm7wdxeXsa14JeB +S2g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=3TBYFP9z5+9ebCsjZY1cYmzJja1apwJqmdgVWE53spM=; b=Eoom6RNBsrj/9cPnDtJOBhXqY2XAHQKK8zyhc5W3l9HLbVfEKGrMasifEB0S9gpi54 6r9CHMfBi6K4fYKljOcgSTs//Q75FMgY6FFI2lh5KVEmgSA1UjPRL0aYoucaMwaWAmXU /nik8vtXPrEOJGuP1+GZwMbqiKvcvcr8fMuGJJC/zDAgtHMBy6W99NSWcSLQVVEPUkTO ZIcO8t04T4bEMhcFi308Ex+aZEekSK1OgXTa/zUVqOCNe4v7rV2d8OzOJtIsBy9LjPHC r6kn86SyM9aMOR88aAfRQJSOurYUI/GfH4D+oUOcVAADYvXkuUa+G2L6aLQcTutOPvqn RaiQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v7si2201572pgb.858.2017.08.09.03.08.55; Wed, 09 Aug 2017 03:08:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752839AbdHIKIx (ORCPT + 7 others); Wed, 9 Aug 2017 06:08:53 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:3478 "EHLO szxga04-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752991AbdHIKIw (ORCPT ); Wed, 9 Aug 2017 06:08:52 -0400 Received: from 172.30.72.58 (EHLO DGGEMS414-HUB.china.huawei.com) ([172.30.72.58]) by dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DEU02374; Wed, 09 Aug 2017 18:08:49 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.203.177.212) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.301.0; Wed, 9 Aug 2017 18:08:38 +0800 From: Shameer Kolothum To: , , , , , CC: , , , , , , , , , Shameer Kolothum Subject: [PATCH v6 2/3] iommu/dma: Add a helper function to reserve HW MSI address regions for IOMMU drivers Date: Wed, 9 Aug 2017 11:07:14 +0100 Message-ID: <20170809100715.870516-3-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20170809100715.870516-1-shameerali.kolothum.thodi@huawei.com> References: <20170809100715.870516-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.177.212] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A010202.598ADF32.000D, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 85f986704d28e17d6a881cce5807dd13 Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org IOMMU drivers can use this to implement their .get_resv_regions callback for HW MSI specific reservations(e.g. ARM GICv3 ITS MSI region). Signed-off-by: Shameer Kolothum --- drivers/iommu/dma-iommu.c | 19 +++++++++++++++++++ include/linux/dma-iommu.h | 7 +++++++ 2 files changed, 26 insertions(+) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c index 9d1cebe..952ecdd 100644 --- a/drivers/iommu/dma-iommu.c +++ b/drivers/iommu/dma-iommu.c @@ -19,6 +19,7 @@ * along with this program. If not, see . */ +#include #include #include #include @@ -198,6 +199,24 @@ void iommu_dma_get_resv_regions(struct device *dev, struct list_head *list) } EXPORT_SYMBOL(iommu_dma_get_resv_regions); +/** + * iommu_dma_get_msi_resv_regions - Reserved region driver helper + * @dev: Device from iommu_get_resv_regions() + * @list: Reserved region list from iommu_get_resv_regions() + * + * IOMMU drivers can use this to implement their .get_resv_regions + * callback for HW MSI specific reservations. For now, this only + * covers ITS MSI region reservation using ACPI IORT helper function. + */ +int iommu_dma_get_msi_resv_regions(struct device *dev, struct list_head *list) +{ + if (!is_of_node(dev->iommu_fwspec->iommu_fwnode)) + return iort_iommu_its_get_resv_regions(dev, list); + + return -ENODEV; +} +EXPORT_SYMBOL(iommu_dma_get_msi_resv_regions); + static int cookie_init_hw_msi_region(struct iommu_dma_cookie *cookie, phys_addr_t start, phys_addr_t end) { diff --git a/include/linux/dma-iommu.h b/include/linux/dma-iommu.h index 92f2083..6062ef0 100644 --- a/include/linux/dma-iommu.h +++ b/include/linux/dma-iommu.h @@ -74,6 +74,8 @@ void iommu_dma_unmap_resource(struct device *dev, dma_addr_t handle, void iommu_dma_map_msi_msg(int irq, struct msi_msg *msg); void iommu_dma_get_resv_regions(struct device *dev, struct list_head *list); +int iommu_dma_get_msi_resv_regions(struct device *dev, struct list_head *list); + #else struct iommu_domain; @@ -107,6 +109,11 @@ static inline void iommu_dma_get_resv_regions(struct device *dev, struct list_he { } +static inline int iommu_dma_get_msi_resv_regions(struct device *dev, struct list_head *list) +{ + return -ENODEV; +} + #endif /* CONFIG_IOMMU_DMA */ #endif /* __KERNEL__ */ #endif /* __DMA_IOMMU_H */ From patchwork Wed Aug 9 10:07:15 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 109701 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp646847qge; Wed, 9 Aug 2017 03:09:16 -0700 (PDT) X-Received: by 10.99.165.3 with SMTP id n3mr6945064pgf.233.1502273356178; Wed, 09 Aug 2017 03:09:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1502273356; cv=none; d=google.com; s=arc-20160816; b=xK8p2mUz6B2GudL1qT3Nu/V/KLJeqCwA1W5PZKXmBEFh4cRgo7ONgQDB0XvUIeRAbo fbUyFroyp75el16dQyQhquOJYbgYC3snqFaUxf915b7HW7Ra8GdLDqdAUUG3UZJ4yBKV D7PEvwPAC+c3Q1LdqZhlp6cJfDjdhp7MXyU1f5iyygNQCrsQMGVoX63wc5zry4geqr4j LywQO2xVIMVb0ER74gZQYILOwIcRhkqUNT/jPG9dBmD5bZTuDXFo5MNsf84RStLsVdo0 hb/O07nVQqVB8MWw3H0Xl/8+nj9hOhxbH41JdZJZ4N3BfbtlNbHXrhK8JI8RhCWHABUP 1WFw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=+6jvpVBqPsooqVKvLfUaAQtSizz94AlGOW0IBnxLRoM=; b=wmxJ6xXfaqPKYuh4XyCDhAqxbVEgHquyn3G7gLIFD8XFUgSkWQ0Kvj+chzJG1j0OKD ODUcOZL+8/d83A8Wx/4lHUOQcHFYP/5auHr/YjN9oHJ0T+nR90fUQjKJcT8O10qnAaZ3 1yPPmj7Cm/Lyw16+JQK1/P3xr1ILdABNFamtbw2W6J3Nqj/QoQgndOyB5Ez14M0I+IXM Fc31BNIzAskg02Jzb6VUOHHCS2q8y9tenY06T/b9jEEKSXJAmI00xKE7Y/VNc2t1H7qa iGgsIFG5Ae4r6icZssTxdox9kgqS0VfsCLAPhe01TwEZkEvyRGmK+zGaI00Un+eF2fAA VS8w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l25si2513050pli.878.2017.08.09.03.09.16; Wed, 09 Aug 2017 03:09:16 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753059AbdHIKI5 (ORCPT + 7 others); Wed, 9 Aug 2017 06:08:57 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:2599 "EHLO szxga05-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752991AbdHIKI4 (ORCPT ); Wed, 9 Aug 2017 06:08:56 -0400 Received: from 172.30.72.59 (EHLO DGGEMS414-HUB.china.huawei.com) ([172.30.72.59]) by dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DEW41340; Wed, 09 Aug 2017 18:08:54 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.203.177.212) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.301.0; Wed, 9 Aug 2017 18:08:42 +0800 From: Shameer Kolothum To: , , , , , CC: , , , , , , , , , Shameer Kolothum Subject: [PATCH v6 3/3] iommu/arm-smmu-v3:Enable ACPI based HiSilicon erratum 161010801 Date: Wed, 9 Aug 2017 11:07:15 +0100 Message-ID: <20170809100715.870516-4-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20170809100715.870516-1-shameerali.kolothum.thodi@huawei.com> References: <20170809100715.870516-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.177.212] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020206.598ADF36.0188, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 470a28ce7285a20a312d68bf87d2484c Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org The HiSilicon erratum 161010801 describes the limitation of HiSilicon platforms Hip06/Hip07 to support the SMMU mappings for MSI transactions. On these platforms GICv3 ITS translator is presented with the deviceID by extending the MSI payload data to 64 bits to include the deviceID. Hence, the PCIe controller on this platforms has to differentiate the MSI payload against other DMA payload and has to modify the MSI payload. This basically makes it difficult for this platforms to have a SMMU translation for MSI. This patch implements a ACPI table based quirk to reserve the hw msi regions in the smmu-v3 driver which means these address regions will not be translated and will be excluded from iova allocations. Signed-off-by: Shameer Kolothum --- drivers/iommu/arm-smmu-v3.c | 27 ++++++++++++++++++++++----- 1 file changed, 22 insertions(+), 5 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index 568c400..6f21dd7 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -608,6 +608,7 @@ struct arm_smmu_device { #define ARM_SMMU_OPT_SKIP_PREFETCH (1 << 0) #define ARM_SMMU_OPT_PAGE0_REGS_ONLY (1 << 1) +#define ARM_SMMU_OPT_RESV_HW_MSI (1 << 2) u32 options; struct arm_smmu_cmdq cmdq; @@ -1934,14 +1935,29 @@ static void arm_smmu_get_resv_regions(struct device *dev, struct list_head *head) { struct iommu_resv_region *region; + struct arm_smmu_master_data *master = dev->iommu_fwspec->iommu_priv; + struct arm_smmu_device *smmu = master->smmu; int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO; + int resv = 0; - region = iommu_alloc_resv_region(MSI_IOVA_BASE, MSI_IOVA_LENGTH, - prot, IOMMU_RESV_SW_MSI); - if (!region) - return; + if ((smmu->options & ARM_SMMU_OPT_RESV_HW_MSI)) { - list_add_tail(®ion->list, head); + resv = iommu_dma_get_msi_resv_regions(dev, head); + + if (resv < 0) { + dev_warn(dev, "HW MSI region resv failed: %d\n", resv); + return; + } + } + + if (!resv) { + region = iommu_alloc_resv_region(MSI_IOVA_BASE, MSI_IOVA_LENGTH, + prot, IOMMU_RESV_SW_MSI); + if (!region) + return; + + list_add_tail(®ion->list, head); + } iommu_dma_get_resv_regions(dev, head); } @@ -2667,6 +2683,7 @@ static void acpi_smmu_get_options(u32 model, struct arm_smmu_device *smmu) break; case ACPI_IORT_SMMU_HISILICON_HI161X: smmu->options |= ARM_SMMU_OPT_SKIP_PREFETCH; + smmu->options |= ARM_SMMU_OPT_RESV_HW_MSI; break; }