From patchwork Thu Apr 30 22:06:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 201255 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1FE8C47258 for ; Thu, 30 Apr 2020 22:07:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C55B52173E for ; Thu, 30 Apr 2020 22:07:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="W9lUgU66" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726336AbgD3WGn (ORCPT ); Thu, 30 Apr 2020 18:06:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48226 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727879AbgD3WGm (ORCPT ); Thu, 30 Apr 2020 18:06:42 -0400 Received: from mail-ed1-x542.google.com (mail-ed1-x542.google.com [IPv6:2a00:1450:4864:20::542]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 154B5C035494; Thu, 30 Apr 2020 15:06:42 -0700 (PDT) Received: by mail-ed1-x542.google.com with SMTP id d16so5842970edv.8; Thu, 30 Apr 2020 15:06:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CgTrzh3Tu5k7J4C6anuKQZFd/nJ6FehtS7rnu7w0aik=; b=W9lUgU66nDUDMQXEq+6WhaUSOwFR89PMCUiEzi9uQtlmrbT3JUKTTX8N/YvWpmGRZM bflOf5xiTdbtWJrHBNFVSeEm+ltIVGx/x7kqByJXaZjP5RSgebWF8zkpfKGiVBBrqo+T ulnFiY7CxTNRRJVS1U+SxBPB6cN2KjoeJv4TFmlMl0RcQgP8zt1Mw+q4KYnW8qbjribj cebgHLKEyWmZnHu7OovETEUUJJb+W+jfYrjGT4pL1C/FniBrTOWpRtNF9NWvapGi2zVC 3gRUTaf7+pzMeMkHewo63L90kIIiHdlTHSIb3lrak94otqyrmZYWcNxMj1JToDaELXRv HOuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CgTrzh3Tu5k7J4C6anuKQZFd/nJ6FehtS7rnu7w0aik=; b=i6bZXrlmltDhgXTV5Vy/4J2iIoHJmytlZ14dOSVsgTsX883D/VbJZFkSJT51CcdUZO 72m7WiZQbKLzCjP6fi+zXSQG/y7h6e3Y8Y5+1zcI1bVY9LUES/IZrZa+3Y2YgN/IGGvX JH+oS3q5/0qVsvtXZqkerEefTIRaX0f409OJclmX0+fuJ7QVfpYOEiJg9vOhr9xildMY efa+rcg7kdEbdkU4tlA7zOKc2rjH/Z4nLWR3QED9y7CkH2u0PU/2Ow1zBwShKRO+9seG EE8KZwghfvCLIZaStCUH+sOw6cFi+ozZevuqX2vHwWQtQIfdla/zJEl2DwX2+UR23Jc1 +s5w== X-Gm-Message-State: AGi0PuaJ+/vu2EPYNKIjW652gg63xmA+SuZGyW0UDZ3LCWfwf2ok16u8 qAwsJ+s2JZ6RK6KCrnGvg2Q= X-Google-Smtp-Source: APiQypKAWtOnJY37BTq1roF1i90+nc9Z/fJC/RtNKvUzlpXZZWc8QxpkmmWxFQpUlmKLLpjH1nhY7g== X-Received: by 2002:a05:6402:95e:: with SMTP id h30mr1049680edz.117.1588284400719; Thu, 30 Apr 2020 15:06:40 -0700 (PDT) Received: from Ansuel-XPS.localdomain ([79.37.253.240]) by smtp.googlemail.com with ESMTPSA id t17sm54185edq.88.2020.04.30.15.06.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Apr 2020 15:06:40 -0700 (PDT) From: Ansuel Smith To: Bjorn Andersson Cc: Abhishek Sahu , Ansuel Smith , Andy Gross , Bjorn Helgaas , Rob Herring , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 03/11] PCI: qcom: change duplicate PCI reset to phy reset Date: Fri, 1 May 2020 00:06:10 +0200 Message-Id: <20200430220619.3169-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200430220619.3169-1-ansuelsmth@gmail.com> References: <20200430220619.3169-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Abhishek Sahu The deinit issues reset_control_assert for PCI twice and does not contain phy reset. Signed-off-by: Abhishek Sahu Signed-off-by: Ansuel Smith --- drivers/pci/controller/dwc/pcie-qcom.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 2a39dfdccfc8..7a8901efc031 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -280,14 +280,14 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; + clk_disable_unprepare(res->phy_clk); reset_control_assert(res->pci_reset); reset_control_assert(res->axi_reset); reset_control_assert(res->ahb_reset); reset_control_assert(res->por_reset); - reset_control_assert(res->pci_reset); + reset_control_assert(res->phy_reset); clk_disable_unprepare(res->iface_clk); clk_disable_unprepare(res->core_clk); - clk_disable_unprepare(res->phy_clk); clk_disable_unprepare(res->aux_clk); clk_disable_unprepare(res->ref_clk); regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); @@ -325,12 +325,6 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) goto err_clk_core; } - ret = clk_prepare_enable(res->phy_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable phy clock\n"); - goto err_clk_phy; - } - if (res->aux_clk) { ret = clk_prepare_enable(res->aux_clk); if (ret) { @@ -387,6 +381,12 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) return ret; } + ret = clk_prepare_enable(res->phy_clk); + if (ret) { + dev_err(dev, "cannot prepare/enable phy clock\n"); + goto err_deassert_ahb; + } + /* wait for clock acquisition */ usleep_range(1000, 1500); @@ -404,8 +404,6 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) err_clk_ref: clk_disable_unprepare(res->aux_clk); err_clk_aux: - clk_disable_unprepare(res->phy_clk); -err_clk_phy: clk_disable_unprepare(res->core_clk); err_clk_core: clk_disable_unprepare(res->iface_clk); From patchwork Thu Apr 30 22:06:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 201256 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C4428C47257 for ; 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Thu, 30 Apr 2020 15:06:46 -0700 (PDT) Received: from Ansuel-XPS.localdomain ([79.37.253.240]) by smtp.googlemail.com with ESMTPSA id t17sm54185edq.88.2020.04.30.15.06.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Apr 2020 15:06:45 -0700 (PDT) From: Ansuel Smith To: Bjorn Andersson Cc: Ansuel Smith , Rob Herring , Andy Gross , Bjorn Helgaas , Rob Herring , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 05/11] devicetree: bindings: pci: add ext reset to qcom, pcie Date: Fri, 1 May 2020 00:06:12 +0200 Message-Id: <20200430220619.3169-6-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200430220619.3169-1-ansuelsmth@gmail.com> References: <20200430220619.3169-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document ext reset used in ipq8064 SoC by qcom PCIe driver. Signed-off-by: Ansuel Smith Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/qcom,pcie.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index becdbdc0fffa..6efcef040741 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -179,6 +179,7 @@ - "pwr" PWR reset - "ahb" AHB reset - "phy_ahb" PHY AHB reset + - "ext" EXT reset - reset-names: Usage: required for ipq8074 @@ -287,8 +288,9 @@ <&gcc PCIE_HCLK_RESET>, <&gcc PCIE_POR_RESET>, <&gcc PCIE_PCI_RESET>, - <&gcc PCIE_PHY_RESET>; - reset-names = "axi", "ahb", "por", "pci", "phy"; + <&gcc PCIE_PHY_RESET>, + <&gcc PCIE_EXT_RESET>; + reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; pinctrl-0 = <&pcie_pins_default>; pinctrl-names = "default"; }; From patchwork Thu Apr 30 22:06:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 201257 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C06D8C47257 for ; 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Thu, 30 Apr 2020 15:06:52 -0700 (PDT) Received: from Ansuel-XPS.localdomain ([79.37.253.240]) by smtp.googlemail.com with ESMTPSA id t17sm54185edq.88.2020.04.30.15.06.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Apr 2020 15:06:51 -0700 (PDT) From: Ansuel Smith To: Bjorn Andersson Cc: Ansuel Smith , stable@vger.kernel.org, Andy Gross , Bjorn Helgaas , Rob Herring , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 07/11] PCI: qcom: add support for defining some PARF params Date: Fri, 1 May 2020 00:06:14 +0200 Message-Id: <20200430220619.3169-8-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200430220619.3169-1-ansuelsmth@gmail.com> References: <20200430220619.3169-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support for Tx De-Emphasis, Tx Swing and Rx equalization definition needed on some ipq8064 based device (Netgear R7800 for example). This cause a total lock of the system on kernel load. Fixes: 82a823833f4e PCI: qcom: Add Qualcomm PCIe controller driver Signed-off-by: Ansuel Smith Cc: stable@vger.kernel.org # v4.5+ --- drivers/pci/controller/dwc/pcie-qcom.c | 47 ++++++++++++++++++++++++-- 1 file changed, 45 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index a4fd5baada34..da8058fd1925 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -46,6 +46,9 @@ #define PCIE20_PARF_PHY_CTRL 0x40 #define PCIE20_PARF_PHY_REFCLK 0x4C +#define PHY_REFCLK_SSP_EN BIT(16) +#define PHY_REFCLK_USE_PAD BIT(12) + #define PCIE20_PARF_DBI_BASE_ADDR 0x168 #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C #define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174 @@ -77,6 +80,18 @@ #define DBI_RO_WR_EN 1 #define PERST_DELAY_US 1000 +/* PARF registers */ +#define PCIE20_PARF_PCS_DEEMPH 0x34 +#define PCS_DEEMPH_TX_DEEMPH_GEN1(x) ((x) << 16) +#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) ((x) << 8) +#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) ((x) << 0) + +#define PCIE20_PARF_PCS_SWING 0x38 +#define PCS_SWING_TX_SWING_FULL(x) ((x) << 8) +#define PCS_SWING_TX_SWING_LOW(x) ((x) << 0) + +#define PCIE20_PARF_CONFIG_BITS 0x50 +#define PHY_RX0_EQ(x) ((x) << 24) #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358 #define SLV_ADDR_SPACE_SZ 0x10000000 @@ -97,6 +112,12 @@ struct qcom_pcie_resources_2_1_0 { struct reset_control *phy_reset; struct reset_control *ext_reset; struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY]; + u32 tx_deemph_gen1; + u32 tx_deemph_gen2_3p5db; + u32 tx_deemph_gen2_6db; + u32 tx_swing_full; + u32 tx_swing_low; + u32 rx0_eq; }; struct qcom_pcie_resources_1_0_0 { @@ -234,8 +255,21 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie) struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; struct dw_pcie *pci = pcie->pci; struct device *dev = pci->dev; + struct device_node *node = dev->of_node; int ret; + of_property_read_u32(node, "qcom,tx-deemph-gen1", + &res->tx_deemph_gen1); + of_property_read_u32(node, "qcom,tx-deemph-gen2-3p5db", + &res->tx_deemph_gen2_3p5db); + of_property_read_u32(node, "qcom,tx-deemph-gen2-6db", + &res->tx_deemph_gen2_6db); + of_property_read_u32(node, "qcom,tx-swing-full", + &res->tx_swing_full); + of_property_read_u32(node, "qcom,tx-swing-low", + &res->tx_swing_low); + of_property_read_u32(node, "qcom,rx0-eq", &res->rx0_eq); + res->supplies[0].supply = "vdda"; res->supplies[1].supply = "vdda_phy"; res->supplies[2].supply = "vdda_refclk"; @@ -368,9 +402,18 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) /* enable PCIe clocks and resets */ qcom_clear_and_set_dword(pcie->parf + PCIE20_PARF_PHY_CTRL, BIT(0), 0); + writel(PCS_DEEMPH_TX_DEEMPH_GEN1(res->tx_deemph_gen1) | + PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(res->tx_deemph_gen2_3p5db) | + PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(res->tx_deemph_gen2_6db), + pcie->parf + PCIE20_PARF_PCS_DEEMPH); + writel(PCS_SWING_TX_SWING_FULL(res->tx_swing_full) | + PCS_SWING_TX_SWING_LOW(res->tx_swing_low), + pcie->parf + PCIE20_PARF_PCS_SWING); + writel(PHY_RX0_EQ(res->rx0_eq), pcie->parf + PCIE20_PARF_CONFIG_BITS); + /* enable external reference clock */ - qcom_clear_and_set_dword(pcie->parf + PCIE20_PARF_PHY_REFCLK, 0, - BIT(16)); + qcom_clear_and_set_dword(pcie->parf + PCIE20_PARF_PHY_REFCLK, + PHY_REFCLK_USE_PAD, PHY_REFCLK_SSP_EN; ret = reset_control_deassert(res->phy_reset); if (ret) { From patchwork Thu Apr 30 22:06:15 2020 Content-Type: text/plain; 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Thu, 30 Apr 2020 15:06:54 -0700 (PDT) From: Ansuel Smith To: Bjorn Andersson Cc: Ansuel Smith , Andy Gross , Bjorn Helgaas , Rob Herring , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 08/11] devicetree: bindings: pci: document PARF params bindings Date: Fri, 1 May 2020 00:06:15 +0200 Message-Id: <20200430220619.3169-9-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200430220619.3169-1-ansuelsmth@gmail.com> References: <20200430220619.3169-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org It is now supported the editing of Tx De-Emphasis, Tx Swing and Rx equalization params on ipq8064. Document this new optional params. Signed-off-by: Ansuel Smith --- .../devicetree/bindings/pci/qcom,pcie.txt | 36 +++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index 6efcef040741..8cc5aea8a1da 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -254,6 +254,42 @@ - "perst-gpios" PCIe endpoint reset signal line - "wake-gpios" PCIe endpoint wake signal line +- qcom,tx-deemph-gen1: + Usage: optional (available for ipq/apq8064) + Value type: + Definition: Gen1 De-emphasis value. + For ipq806x should be set to 24. + +- qcom,tx-deemph-gen2-3p5db: + Usage: optional (available for ipq/apq8064) + Value type: + Definition: Gen2 (3.5db) De-emphasis value. + For ipq806x should be set to 24. + +- qcom,tx-deemph-gen2-6db: + Usage: optional (available for ipq/apq8064) + Value type: + Definition: Gen2 (6db) De-emphasis value. + For ipq806x should be set to 34. + +- qcom,tx-swing-full: + Usage: optional (available for ipq/apq8064) + Value type: + Definition: TX launch amplitude swing_full value. + For ipq806x should be set to 120. + +- qcom,tx-swing-low: + Usage: optional (available for ipq/apq8064) + Value type: + Definition: TX launch amplitude swing_low value. + For ipq806x should be set to 120. + +- qcom,rx0-eq: + Usage: optional (available for ipq/apq8064) + Value type: + Definition: RX0 equalization value. + For ipq806x should be set to 4. + * Example for ipq/apq8064 pcie@1b500000 { compatible = "qcom,pcie-apq8064", "qcom,pcie-ipq8064", "snps,dw-pcie"; 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Thu, 30 Apr 2020 15:07:00 -0700 (PDT) From: Ansuel Smith To: Bjorn Andersson Cc: Ansuel Smith , Andy Gross , Bjorn Helgaas , Rob Herring , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 10/11] devicetree: bindings: pci: add ipq8064 rev 2 variant to qcom, pcie Date: Fri, 1 May 2020 00:06:17 +0200 Message-Id: <20200430220619.3169-11-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200430220619.3169-1-ansuelsmth@gmail.com> References: <20200430220619.3169-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document qcom,pcie-ipq8064-v2 needed to use different phy_tx0_term_offset. In ipq8064 phy_tx0_term_offset is 7. In ipq8064 v2 other SoC it's set to 0 by default. Signed-off-by: Ansuel Smith --- Documentation/devicetree/bindings/pci/qcom,pcie.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index 8cc5aea8a1da..c7102863d855 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -5,6 +5,7 @@ Value type: Definition: Value should contain - "qcom,pcie-ipq8064" for ipq8064 + - "qcom,pcie-ipq8064-v2" for ipq8064 rev 2 or ipq8065 - "qcom,pcie-apq8064" for apq8064 - "qcom,pcie-apq8084" for apq8084 - "qcom,pcie-msm8996" for msm8996 or apq8096