From patchwork Fri Mar 20 18:34:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 203030 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E8A09C4332D for ; Fri, 20 Mar 2020 18:35:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9C9AA20739 for ; Fri, 20 Mar 2020 18:35:05 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="hj0Gjr3w" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727232AbgCTSfF (ORCPT ); Fri, 20 Mar 2020 14:35:05 -0400 Received: from mail-ed1-f65.google.com ([209.85.208.65]:35005 "EHLO mail-ed1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727178AbgCTSfF (ORCPT ); Fri, 20 Mar 2020 14:35:05 -0400 Received: by mail-ed1-f65.google.com with SMTP id a20so8339174edj.2; Fri, 20 Mar 2020 11:35:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=PjUrNIBTHiGRlXltBoWnInenBouwnlz0OaURyGduRc8=; b=hj0Gjr3w7oKqG+/bfA2jN473nqLzbMpQSum+y5Z1mOejc+pz4plw/F1SS2BcZJPin1 3hSggqTP+ZKnFEorHvTKwBJGC6D8k1fe3lMlhlWO+2edrUDp6pA4DxdGmDFa6YWp2ZwF PIn2YbAmk2uwlWE9sBGAJdkhdTPUQxPi6XtXdgjZ6QP5+rhGhBPpJsuQ7UYyWxVO5xQE yNi9T6f9F575tiLs0KnMRN71falp6acddOa3YP63mskZDGNGzTPlJ7OVRd/JwfMH7aYs YOXt/F81Or2DZUD4kotD8mSSK6xX1Fy4UV9u3qjEWjQOyhgPsmTL8MQRZ6luhDX5Cby1 Z6tw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=PjUrNIBTHiGRlXltBoWnInenBouwnlz0OaURyGduRc8=; b=V//eSk71K+jJ0M1/9cIqbRYeYz1ReHdm/nG1efntCPLms48H66U9AlhCZqZXVwogur YoteZvx8qjlmVF4TbxG1nxK/CFezhyR+wcdqbBTF48c4yAcryDDaxikRjA7xRFfuM2+/ oe6EANzOl6D05Fz3hIVqWdWHvL2ODrevJqS+y2dEevbCA595XJ2WMQOqUP2sHOOkW6DZ 9SBIMIWIkaERxvJI5ARdmmYpR+4rCVfa1hHPwvve+CMiY5W40ovsZzfYFkAYYU5dW663 cbkl6HEpaeN0nbGqPd6kgmMiJAv0TIRu88l6u2KTc+0w+urBx1h4eM1LwxdZkUe70VwJ YRwQ== X-Gm-Message-State: ANhLgQ14xGU74G0MIYLKqQZbUVZE6IWltNkoag/2LwmBF2WK4jysqrE9 5AmCdCtaAAKmYIXnU4hTT5A= X-Google-Smtp-Source: ADFU+vvHAO5MesgNDreNBT9MSjyANUd4rdBiCnfzEigRlv0T/4Z7d4CGHTe31T+t2ccvEkSD2uqiZQ== X-Received: by 2002:a50:cdc7:: with SMTP id h7mr9669266edj.208.1584729302756; Fri, 20 Mar 2020 11:35:02 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host203-232-dynamic.53-79-r.retail.telecomitalia.it. [79.53.232.203]) by smtp.googlemail.com with ESMTPSA id y13sm172916eje.3.2020.03.20.11.35.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Mar 2020 11:35:02 -0700 (PDT) From: Ansuel Smith To: Stanimir Varbanov Cc: Ansuel Smith , Sham Muthayyan , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Rob Herring , Mark Rutland , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 01/12] pcie: qcom: add missing ipq806x clocks in pcie driver Date: Fri, 20 Mar 2020 19:34:43 +0100 Message-Id: <20200320183455.21311-1-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Aux and Ref clk are missing in pcie qcom driver. Add support in the driver to fix pcie inizialization in ipq806x Signed-off-by: Sham Muthayyan Signed-off-by: Ansuel Smith --- drivers/pci/controller/dwc/pcie-qcom.c | 38 ++++++++++++++++++++++---- 1 file changed, 33 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 5ea527a6bd9f..f958c535de6e 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -88,6 +88,8 @@ struct qcom_pcie_resources_2_1_0 { struct clk *iface_clk; struct clk *core_clk; struct clk *phy_clk; + struct clk *aux_clk; + struct clk *ref_clk; struct reset_control *pci_reset; struct reset_control *axi_reset; struct reset_control *ahb_reset; @@ -246,6 +248,14 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie) if (IS_ERR(res->phy_clk)) return PTR_ERR(res->phy_clk); + res->aux_clk = devm_clk_get(dev, "aux"); + if (IS_ERR(res->aux_clk)) + return PTR_ERR(res->aux_clk); + + res->ref_clk = devm_clk_get(dev, "ref"); + if (IS_ERR(res->ref_clk)) + return PTR_ERR(res->ref_clk); + res->pci_reset = devm_reset_control_get_exclusive(dev, "pci"); if (IS_ERR(res->pci_reset)) return PTR_ERR(res->pci_reset); @@ -278,6 +288,8 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) clk_disable_unprepare(res->iface_clk); clk_disable_unprepare(res->core_clk); clk_disable_unprepare(res->phy_clk); + clk_disable_unprepare(res->aux_clk); + clk_disable_unprepare(res->ref_clk); regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); } @@ -307,16 +319,28 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) goto err_assert_ahb; } + ret = clk_prepare_enable(res->core_clk); + if (ret) { + dev_err(dev, "cannot prepare/enable core clock\n"); + goto err_clk_core; + } + ret = clk_prepare_enable(res->phy_clk); if (ret) { dev_err(dev, "cannot prepare/enable phy clock\n"); goto err_clk_phy; } - ret = clk_prepare_enable(res->core_clk); + ret = clk_prepare_enable(res->aux_clk); if (ret) { - dev_err(dev, "cannot prepare/enable core clock\n"); - goto err_clk_core; + dev_err(dev, "cannot prepare/enable aux clock\n"); + goto err_clk_aux; + } + + ret = clk_prepare_enable(res->ref_clk); + if (ret) { + dev_err(dev, "cannot prepare/enable ref clock\n"); + goto err_clk_ref; } ret = reset_control_deassert(res->ahb_reset); @@ -372,10 +396,14 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) return 0; err_deassert_ahb: - clk_disable_unprepare(res->core_clk); -err_clk_core: + clk_disable_unprepare(res->ref_clk); +err_clk_ref: + clk_disable_unprepare(res->aux_clk); +err_clk_aux: clk_disable_unprepare(res->phy_clk); err_clk_phy: + clk_disable_unprepare(res->core_clk); +err_clk_core: clk_disable_unprepare(res->iface_clk); err_assert_ahb: regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); From patchwork Fri Mar 20 18:34:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 203025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0C50EC4332E for ; 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[79.53.232.203]) by smtp.googlemail.com with ESMTPSA id y13sm172916eje.3.2020.03.20.11.35.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Mar 2020 11:35:09 -0700 (PDT) From: Ansuel Smith To: Stanimir Varbanov Cc: Abhishek Sahu , Ansuel Smith , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Rob Herring , Mark Rutland , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 03/12] pcie: qcom: change duplicate pci reset to phy reset Date: Fri, 20 Mar 2020 19:34:45 +0100 Message-Id: <20200320183455.21311-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200320183455.21311-1-ansuelsmth@gmail.com> References: <20200320183455.21311-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Abhishek Sahu The deinit issues reset_control_assert for pci twice and does not contain phy reset. Signed-off-by: Abhishek Sahu Signed-off-by: Ansuel Smith --- drivers/pci/controller/dwc/pcie-qcom.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index f958c535de6e..1fcc7fed8443 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -284,7 +284,7 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) reset_control_assert(res->axi_reset); reset_control_assert(res->ahb_reset); reset_control_assert(res->por_reset); - reset_control_assert(res->pci_reset); + reset_control_assert(res->phy_reset); clk_disable_unprepare(res->iface_clk); clk_disable_unprepare(res->core_clk); clk_disable_unprepare(res->phy_clk); From patchwork Fri Mar 20 18:34:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 203029 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D99F2C4332D for ; Fri, 20 Mar 2020 18:35:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B595820775 for ; Fri, 20 Mar 2020 18:35:26 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="TUer9SL6" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727492AbgCTSfW (ORCPT ); Fri, 20 Mar 2020 14:35:22 -0400 Received: from mail-ed1-f67.google.com ([209.85.208.67]:36097 "EHLO mail-ed1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727464AbgCTSfV (ORCPT ); Fri, 20 Mar 2020 14:35:21 -0400 Received: by mail-ed1-f67.google.com with SMTP id b18so8337943edu.3; Fri, 20 Mar 2020 11:35:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=N1VYvZyyGPZyXdBVA/5CvMYrP4xt0r9STQ96DGzN2ng=; b=TUer9SL6kQp1I9bams9QQ+Ex4s09SBwSnMPFcQ+gqCS1zCUsiAEkvUgO5SUYWYrYDm /UYaBac2EmNPJC28HooJSUdEBQKVTsilUYvtXuib7IZ/t7D+GrKIn1SxjhsNHdZW7do0 vcwq8z0RGarsMhcFi+42RDga/gEiNA+6EbSeW/puwxfa3IMqaQcEZmDDw4NhOsaZ2MMm QNYeJqGfJfL7+0y3LWdFJZHhzkuawj1JIdQZeDsjPHahqb3BugargO5ixegVnB/7KDtO HOypDSoBznyVZfHpa/0DfBz02xaVsQIrDao7Y3OrKarvNS8FuSPn/S8SV0WA1s8zudgF hsTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=N1VYvZyyGPZyXdBVA/5CvMYrP4xt0r9STQ96DGzN2ng=; b=GNTGAhovJR2BHVM1gLDsrEL3bnp4d+JGKSG0VzG/Vw70bXNM412FaNigxE4cTqk/FX byTACxW4px7JstlJuAuJ6Iw5/iVX9Ph05wdcpdxfd6+i/r1sBI2CAOQ90WJnt54s9oaS ne1LCGwqLkXaRTBldd04syo1h9+EMb1qAId6WmTSAcniDUyO3jaWi6utNwT98T0s+m4Z GmRiWmFwpVZFmLeQ/gW3hCY5RwUC49R69Lk0jqOc0k6SgJAILGD21iJNciGYS0C46p6Z 0SDyb+wYgwAkr9eaOB7yCoQCYfOMIhyizTbdm4c2S1zQJrntQaspYJ9iGcXsuhxPj1AP pNXw== X-Gm-Message-State: ANhLgQ2z1tszdb9h/yVfyuuVUcBxoUA61lULIg8LvYpH7WsLvke95rYa m1X1n27+Wn46XfFGtFvohg0= X-Google-Smtp-Source: ADFU+vs4niaWE6EQ2dqQSFkoRr8yu9PRvGsmXL8eUFpJcYsno4Gykm4xqHp4FYdJgx2adWgljr2PMw== X-Received: by 2002:a17:906:c4f:: with SMTP id t15mr9821145ejf.193.1584729318447; Fri, 20 Mar 2020 11:35:18 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host203-232-dynamic.53-79-r.retail.telecomitalia.it. [79.53.232.203]) by smtp.googlemail.com with ESMTPSA id y13sm172916eje.3.2020.03.20.11.35.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Mar 2020 11:35:17 -0700 (PDT) From: Ansuel Smith To: Stanimir Varbanov Cc: Ansuel Smith , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Rob Herring , Mark Rutland , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 06/12] devicetree: bindings: pci: add ext reset to qcom, pcie Date: Fri, 20 Mar 2020 19:34:48 +0100 Message-Id: <20200320183455.21311-6-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200320183455.21311-1-ansuelsmth@gmail.com> References: <20200320183455.21311-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document ext reset used in ipq806x soc by qcom pcie driver Signed-off-by: Ansuel Smith --- Documentation/devicetree/bindings/pci/qcom,pcie.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index becdbdc0fffa..6efcef040741 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -179,6 +179,7 @@ - "pwr" PWR reset - "ahb" AHB reset - "phy_ahb" PHY AHB reset + - "ext" EXT reset - reset-names: Usage: required for ipq8074 @@ -287,8 +288,9 @@ <&gcc PCIE_HCLK_RESET>, <&gcc PCIE_POR_RESET>, <&gcc PCIE_PCI_RESET>, - <&gcc PCIE_PHY_RESET>; - reset-names = "axi", "ahb", "por", "pci", "phy"; + <&gcc PCIE_PHY_RESET>, + <&gcc PCIE_EXT_RESET>; + reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; pinctrl-0 = <&pcie_pins_default>; pinctrl-names = "default"; }; From patchwork Fri Mar 20 18:34:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 203026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40EECC4332E for ; Fri, 20 Mar 2020 18:36:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1D2D720781 for ; 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[79.53.232.203]) by smtp.googlemail.com with ESMTPSA id y13sm172916eje.3.2020.03.20.11.35.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Mar 2020 11:35:22 -0700 (PDT) From: Ansuel Smith To: Stanimir Varbanov Cc: Ansuel Smith , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Rob Herring , Mark Rutland , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 08/12] devicetree: bindings: pci: add phy-tx0-term-offset to qcom, pcie Date: Fri, 20 Mar 2020 19:34:50 +0100 Message-Id: <20200320183455.21311-8-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200320183455.21311-1-ansuelsmth@gmail.com> References: <20200320183455.21311-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document phy-tx0-term-offset propriety to qcom pcie driver Signed-off-by: Ansuel Smith --- Documentation/devicetree/bindings/pci/qcom,pcie.txt | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index 6efcef040741..8c1d014f37b0 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -254,6 +254,12 @@ - "perst-gpios" PCIe endpoint reset signal line - "wake-gpios" PCIe endpoint wake signal line +- phy-tx0-term-offset: + Usage: optional + Value type: + Definition: If not defined is 0. In ipq806x is set to 7. In newer + revision (v2.0) the offset is zero. + * Example for ipq/apq8064 pcie@1b500000 { compatible = "qcom,pcie-apq8064", "qcom,pcie-ipq8064", "snps,dw-pcie"; @@ -293,6 +299,7 @@ reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; pinctrl-0 = <&pcie_pins_default>; pinctrl-names = "default"; + phy-tx0-term-offset = <7>; }; * Example for apq8084 From patchwork Fri Mar 20 18:34:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 203027 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0798C4332E for ; Fri, 20 Mar 2020 18:35:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8D5B820786 for ; Fri, 20 Mar 2020 18:35:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="rBAXr6Sf" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727542AbgCTSfb (ORCPT ); Fri, 20 Mar 2020 14:35:31 -0400 Received: from mail-ed1-f66.google.com ([209.85.208.66]:44481 "EHLO mail-ed1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725446AbgCTSfb (ORCPT ); Fri, 20 Mar 2020 14:35:31 -0400 Received: by mail-ed1-f66.google.com with SMTP id z3so8266718edq.11; Fri, 20 Mar 2020 11:35:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tGZNkaeSgH2Ia/qzhM5CNeT0pv+X7+3+Gb2pdjSMGCU=; b=rBAXr6Sf2nZ5TYuifwsb71mUsVZl34Q5Nb/L02j2b8yzwjCUnPFUuz4XfHWFlw4was dVfwR6ftScUpNVUNOgGxJG7kcFsd63d4Pb6k7apa0UdiiQKaPEkIYRqe3txhde/xN+Dp kpH6x0wvGtKloqgHtc2G7T235cg2aAG3mo/fZp3mVC0bBSgAnbfAaDL8lixk6bhbYumH maKA9PbACjkGTMJFWGLDeu1l59O2H+hBfz4F31ruUtWui6ZTnV3lie+PsJYiBCGcONTL n/gyeYQs0cgmsT8VU6cssE3r4YHFYzlj3f8vSPcLIp/yHwJKtA7jd5o83veckyVYjcYP nlXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tGZNkaeSgH2Ia/qzhM5CNeT0pv+X7+3+Gb2pdjSMGCU=; b=rGDooNJ06IH7gOBsDvkqTG1AqDGGyJYQtsznOXkp0Tuhksiod+vEL/YKe2APn1u2Kw +aaZxLNisxRqlVIFG+tRQuNm87c4xpn93nqT/78cOBYQs/VryJ402aPj93fN0p9TqvRe CzZqcZvXWuJL+v039rWQAsYxnuDWbzHvWYmX0hW/vvuZIsN56MdkblUu1hRxcdA+VRaa v151msPYzsuK1CAdvrfYjdH7uUaPTNRBbBUcUlknnkYRVuHyhW/VyhFSPIu5vl+5XTQw xZmuXZ/+myvh9FD1SADjbfVLfiuzmIq2clZF+rSe1UZjEjt4wq7JSj/7U8PA76UEqr9I fnxg== X-Gm-Message-State: ANhLgQ2hWa9PJCdS2+brg5dkUz/SZQyZq8M3hHgHrRjevEpCPU60Lm/Y jjShIeWB3IAUlK58p+ArFlo= X-Google-Smtp-Source: ADFU+vviOQwMW3HASaguuY6rBmj6IAJbDOHwyuY4ghziSVXDR/mOHFhjkk1oj9CihWdLHFXlxW8pyw== X-Received: by 2002:a17:906:fc01:: with SMTP id ov1mr9556367ejb.65.1584729329072; Fri, 20 Mar 2020 11:35:29 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host203-232-dynamic.53-79-r.retail.telecomitalia.it. [79.53.232.203]) by smtp.googlemail.com with ESMTPSA id y13sm172916eje.3.2020.03.20.11.35.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Mar 2020 11:35:28 -0700 (PDT) From: Ansuel Smith To: Stanimir Varbanov Cc: Sham Muthayyan , Ansuel Smith , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Rob Herring , Mark Rutland , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 10/12] pcie: qcom: add Force GEN1 support Date: Fri, 20 Mar 2020 19:34:52 +0100 Message-Id: <20200320183455.21311-10-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200320183455.21311-1-ansuelsmth@gmail.com> References: <20200320183455.21311-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Sham Muthayyan Add Force GEN1 support needed in some ipq806x board that needs to limit some pcie line to gen1 for some hardware limitation Signed-off-by: Sham Muthayyan Signed-off-by: Ansuel Smith --- drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index e26ba8f63d4f..03130a3206b4 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -123,6 +123,8 @@ #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358 #define SLV_ADDR_SPACE_SZ 0x10000000 +#define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xA0 + #define DEVICE_TYPE_RC 0x4 #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3 @@ -223,6 +225,7 @@ struct qcom_pcie { struct phy *phy; struct gpio_desc *reset; const struct qcom_pcie_ops *ops; + uint32_t force_gen1; }; #define to_qcom_pcie(x) dev_get_drvdata((x)->dev) @@ -515,6 +518,11 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) /* wait for clock acquisition */ usleep_range(1000, 1500); + if (pcie->force_gen1) { + writel_relaxed((readl_relaxed( + pcie->pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2) | 1), + pcie->pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2); + } /* Set the Max TLP size to 2K, instead of using default of 4K */ @@ -1487,6 +1495,8 @@ static int qcom_pcie_probe(struct platform_device *pdev) struct dw_pcie *pci; struct qcom_pcie *pcie; int ret; + uint32_t force_gen1 = 0; + struct device_node *np = pdev->dev.of_node; pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); if (!pcie) @@ -1517,6 +1527,9 @@ static int qcom_pcie_probe(struct platform_device *pdev) goto err_pm_runtime_put; } + of_property_read_u32(np, "force_gen1", &force_gen1); + pcie->force_gen1 = force_gen1; + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf"); pcie->parf = devm_ioremap_resource(dev, res); if (IS_ERR(pcie->parf)) { From patchwork Fri Mar 20 18:34:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 203028 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 049C3C4332D for ; Fri, 20 Mar 2020 18:35:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CAFAD20775 for ; Fri, 20 Mar 2020 18:35:46 +0000 (UTC) Authentication-Results: mail.kernel.org; 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[79.53.232.203]) by smtp.googlemail.com with ESMTPSA id y13sm172916eje.3.2020.03.20.11.35.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Mar 2020 11:35:33 -0700 (PDT) From: Ansuel Smith To: Stanimir Varbanov Cc: Sriram Palanisamy , Ansuel Smith , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Rob Herring , Mark Rutland , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 12/12] pcie: qcom: Set PCIE MRRS and MPS to 256B Date: Fri, 20 Mar 2020 19:34:54 +0100 Message-Id: <20200320183455.21311-12-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200320183455.21311-1-ansuelsmth@gmail.com> References: <20200320183455.21311-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Sriram Palanisamy Set Max Read Request Size and Max Payload Size to 256 bytes, per chip team recommendation. Signed-off-by: Gokul Sriram Palanisamy Signed-off-by: Ansuel Smith --- drivers/pci/controller/dwc/pcie-qcom.c | 37 ++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 03130a3206b4..ad437c6f49a0 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -125,6 +125,14 @@ #define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xA0 +#define __set(v, a, b) (((v) << (b)) & GENMASK(a, b)) +#define __mask(a, b) (((1 << ((a) + 1)) - 1) & ~((1 << (b)) - 1)) +#define PCIE20_DEV_CAS 0x78 +#define PCIE20_MRRS_MASK __mask(14, 12) +#define PCIE20_MRRS(x) __set(x, 14, 12) +#define PCIE20_MPS_MASK __mask(7, 5) +#define PCIE20_MPS(x) __set(x, 7, 5) + #define DEVICE_TYPE_RC 0x4 #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3 @@ -1595,6 +1603,35 @@ static int qcom_pcie_probe(struct platform_device *pdev) return ret; } +static void qcom_pcie_fixup_final(struct pci_dev *pcidev) +{ + int cap, err; + u16 ctl, reg_val; + + cap = pci_pcie_cap(pcidev); + if (!cap) + return; + + err = pci_read_config_word(pcidev, cap + PCI_EXP_DEVCTL, &ctl); + + if (err) + return; + + reg_val = ctl; + + if (((reg_val & PCIE20_MRRS_MASK) >> 12) > 1) + reg_val = (reg_val & ~(PCIE20_MRRS_MASK)) | PCIE20_MRRS(0x1); + + if (((ctl & PCIE20_MPS_MASK) >> 5) > 1) + reg_val = (reg_val & ~(PCIE20_MPS_MASK)) | PCIE20_MPS(0x1); + + err = pci_write_config_word(pcidev, cap + PCI_EXP_DEVCTL, reg_val); + + if (err) + dev_err(&pcidev->dev, "pcie config write failed %d\n", err); +} +DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, qcom_pcie_fixup_final); + static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-apq8084", .data = &ops_1_0_0 }, { .compatible = "qcom,pcie-ipq8064", .data = &ops_2_1_0 },