From patchwork Mon Aug 21 07:20:52 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lokesh Vutla X-Patchwork-Id: 110495 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp931322qge; Mon, 21 Aug 2017 00:30:06 -0700 (PDT) X-Received: by 10.80.195.15 with SMTP id a15mr11927188edb.264.1503300606419; Mon, 21 Aug 2017 00:30:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1503300606; cv=none; d=google.com; s=arc-20160816; b=Z3R/7ygkRDl6AnjgVUMaBrPjrndeNjpmhQ5brhWVA2/M4MJK9ihqJpXOVzBDrKq/AS g0YySh/MeJzMUcziFtFuv8LEPBHUTRDYY0aaUBXMv8Bjnlqms1I/d1ZWUm5ASs18dhj6 AzNhN4kbmlfbfwRPR2WwCTH1/Sx/c406dXtlavx78OtWKcqpQuLKw9ZP+tFLxn9jgSl5 Rpkoc1oBD3ZS7InPqmAk86+cZF7aaSuEIOUzn2ycfGEtof4HP2hZuKVnbw7DR4dPOc2T eMvlInRcUe2BN3yOjSf29bZX4J6OnV3j7/hf2UPHilS9kQfCu4QSoyikhbdhzq6JB9cP b6og== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :cc:mime-version:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=Z9kfJNMZu0aozukuwJBk+9DdVK9k8xdaJM3Fx7/8VO8=; b=qFvBU39Q7Gb9DpbMnjHCOMxeqJMgTuS631tWw0LVo1JssoKEdqnPl85+EqTt51/3jl 5uzrWL0GAdxF8Uy/YysymYKDpdyR5IRl8Ao6U+7Q0hGVcrVC9joPHQ1PZpk/pFIsi18k bxXe2qPu/AwnH0j4ho3FuFYpJAKhrGtxAR5W8OdmOMl1L8oIIcOmFckVxz1d/OF5mjnK bdw/5WYfyPCHsxDE1xIm2XEYsJpzMfsK4Q3SWREEWdNe0xaBWZ2SJZ8J11pDw36mIlsa h27fhmVl880EtC9dL1ljLZxNQTWA7D6u3WQe2LuAZnW+EE87zUUJAoyxCBqVe2XcqRo9 44/Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=upgYyFHP; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id j7si9862644edl.487.2017.08.21.00.30.06; Mon, 21 Aug 2017 00:30:06 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=upgYyFHP; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 021F9C220A4; Mon, 21 Aug 2017 07:30:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 4BA71C2202C; Mon, 21 Aug 2017 07:25:34 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 8CFC9C21E28; Mon, 21 Aug 2017 07:25:20 +0000 (UTC) Received: from fllnx210.ext.ti.com (fllnx210.ext.ti.com [198.47.19.17]) by lists.denx.de (Postfix) with ESMTPS id 17EFCC22012 for ; Mon, 21 Aug 2017 07:25:15 +0000 (UTC) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id v7L7PDL3031300; Mon, 21 Aug 2017 02:25:13 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1503300313; bh=mghHnaBmHU3rM5/9M+EccOF+tf3PrykVFrrFO4goMKs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=upgYyFHP1iKJMbZbAXvhALv12cYHfX9X/cEf9VUvJgVS6yj6hV1QmJ8PbDm+oTP2w E17H6BQ1RA67EuB0vZI4uMxE0uXtGLi+mlYFA/+sId66E/VvVVvl5ibO2ODhWQRERv cAXy3gmtI9bCNaqxvRql1ZOWyvc5Js8A0csrXF/g= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7L7PD2V003905; Mon, 21 Aug 2017 02:25:13 -0500 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Mon, 21 Aug 2017 02:25:13 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Mon, 21 Aug 2017 02:25:13 -0500 Received: from a0131933.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7L7P3Ze010673; Mon, 21 Aug 2017 02:25:11 -0500 From: Lokesh Vutla To: Tom Rini , Date: Mon, 21 Aug 2017 12:50:52 +0530 Message-ID: <20170821072101.29375-5-lokeshvutla@ti.com> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20170821072101.29375-1-lokeshvutla@ti.com> References: <20170821072101.29375-1-lokeshvutla@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: Tero Kristo , Praneeth Bajjuri Subject: [U-Boot] [PATCH v2 04/13] arm: dra76: Add support for ES1.0 detection X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Praneeth Bajjuri dra76 family is a high-performance, infotainment application device, based on OMAP architecture on a 28-nm technology. This contains most of the subsystems, peripherals that are available on dra74, dra72 family. This SoC mainly features Subsystems: - 2 x Cortex-A15 with max speed of 1.8GHz - 2 X DSP - 2 X Cortex-M4 IPU - ISS - CAL - DSS - VPE - VIP Connectivity peripherals: - 1 USB3.0 and 3 USB2.0 subsystems - 1 x SATA - 2 x PCI Express Gen2 - 3-port Gigabit ethernet switch - 2 x CAN - MCAN Adding CPU detection support for the dra76 ES1.0 soc and update prcm, control module, dplls data. Reviewed-by: Tom Rini Signed-off-by: Praneeth Bajjuri Signed-off-by: Lokesh Vutla --- arch/arm/include/asm/arch-omap5/omap.h | 1 + arch/arm/include/asm/omap_common.h | 8 ++++++++ arch/arm/mach-omap2/omap5/hw_data.c | 27 +++++++++++++++++++++++++++ arch/arm/mach-omap2/omap5/hwinit.c | 3 +++ 4 files changed, 39 insertions(+) diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index b047f0d650..87a3d23ecb 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -58,6 +58,7 @@ #define OMAP5430_CONTROL_ID_CODE_ES2_0 0x1B94202F #define OMAP5432_CONTROL_ID_CODE_ES1_0 0x0B99802F #define OMAP5432_CONTROL_ID_CODE_ES2_0 0x1B99802F +#define DRA762_CONTROL_ID_CODE_ES1_0 0x0BB5002F #define DRA752_CONTROL_ID_CODE_ES1_0 0x0B99002F #define DRA752_CONTROL_ID_CODE_ES1_1 0x1B99002F #define DRA752_CONTROL_ID_CODE_ES2_0 0x2B99002F diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index ef5c481349..e951b232d6 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -722,6 +722,7 @@ static inline u8 is_omap54xx(void) #define DRA7XX 0x07000000 #define DRA72X 0x07200000 +#define DRA76X 0x07600000 static inline u8 is_dra7xx(void) { @@ -734,6 +735,12 @@ static inline u8 is_dra72x(void) extern u32 *const omap_si_rev; return (*omap_si_rev & 0xFFF00000) == DRA72X; } + +static inline u8 is_dra76x(void) +{ + extern u32 *const omap_si_rev; + return (*omap_si_rev & 0xFFF00000) == DRA76X; +} #endif /* @@ -761,6 +768,7 @@ static inline u8 is_dra72x(void) #define OMAP5432_ES2_0 0x54320200 /* DRA7XX */ +#define DRA762_ES1_0 0x07620100 #define DRA752_ES1_0 0x07520100 #define DRA752_ES1_1 0x07520110 #define DRA752_ES2_0 0x07520200 diff --git a/arch/arm/mach-omap2/omap5/hw_data.c b/arch/arm/mach-omap2/omap5/hw_data.c index 4ad6b530d2..19a8d10cef 100644 --- a/arch/arm/mach-omap2/omap5/hw_data.c +++ b/arch/arm/mach-omap2/omap5/hw_data.c @@ -113,6 +113,16 @@ static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = { {10, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 38.4 MHz */ }; +static const struct dpll_params per_dpll_params_768mhz_dra76x[NUM_SYS_CLKS] = { + {32, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 12 MHz */ + {96, 4, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 20 MHz */ + {160, 6, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 16.8 MHz */ + {20, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 19.2 MHz */ + {192, 12, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {10, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 38.4 MHz */ +}; + static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = { {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ @@ -234,6 +244,17 @@ struct dplls omap5_dplls_es2 = { .ddr = NULL }; +struct dplls dra76x_dplls = { + .mpu = mpu_dpll_params_1ghz, + .core = core_dpll_params_2128mhz_dra7xx, + .per = per_dpll_params_768mhz_dra76x, + .abe = abe_dpll_params_sysclk2_361267khz, + .iva = iva_dpll_params_2330mhz_dra7xx, + .usb = usb_dpll_params_1920mhz, + .ddr = ddr_dpll_params_2664mhz, + .gmac = gmac_dpll_params_2000mhz, +}; + struct dplls dra7xx_dplls = { .mpu = mpu_dpll_params_1ghz, .core = core_dpll_params_2128mhz_dra7xx, @@ -709,6 +730,12 @@ void __weak hw_data_init(void) *ctrl = &omap5_ctrl; break; + case DRA762_ES1_0: + *prcm = &dra7xx_prcm; + *dplls_data = &dra76x_dplls; + *ctrl = &dra7xx_ctrl; + break; + case DRA752_ES1_0: case DRA752_ES1_1: case DRA752_ES2_0: diff --git a/arch/arm/mach-omap2/omap5/hwinit.c b/arch/arm/mach-omap2/omap5/hwinit.c index 85d3518e94..c520a633c4 100644 --- a/arch/arm/mach-omap2/omap5/hwinit.c +++ b/arch/arm/mach-omap2/omap5/hwinit.c @@ -362,6 +362,9 @@ void init_omap_revision(void) case OMAP5432_CONTROL_ID_CODE_ES2_0: *omap_si_rev = OMAP5432_ES2_0; break; + case DRA762_CONTROL_ID_CODE_ES1_0: + *omap_si_rev = DRA762_ES1_0; + break; case DRA752_CONTROL_ID_CODE_ES1_0: *omap_si_rev = DRA752_ES1_0; break;