From patchwork Mon Feb 17 06:42:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 204705 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9A4D2C7619E for ; Mon, 17 Feb 2020 06:45:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 72C91206F4 for ; Mon, 17 Feb 2020 06:45:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=sholland.org header.i=@sholland.org header.b="VjDVnylg"; dkim=pass (2048-bit key) header.d=messagingengine.com header.i=@messagingengine.com header.b="O7JOvtlF" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726795AbgBQGmy (ORCPT ); Mon, 17 Feb 2020 01:42:54 -0500 Received: from new2-smtp.messagingengine.com ([66.111.4.224]:49705 "EHLO new2-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726704AbgBQGmx (ORCPT ); Mon, 17 Feb 2020 01:42:53 -0500 Received: from compute5.internal (compute5.nyi.internal [10.202.2.45]) by mailnew.nyi.internal (Postfix) with ESMTP id 77391522A; Mon, 17 Feb 2020 01:42:52 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute5.internal (MEProxy); Mon, 17 Feb 2020 01:42:52 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=fm2; bh=/Gz9CsMmbdcrp 9kMVCWTTsaDhYUcCaxrF9/HDAwTHKU=; b=VjDVnylgG2LGyvcpl9mBpyl6stR8G 4uFkbuK8eeuIrCdclOr3vVR9riQxRH/LkG9Fi17pSK5flP/1IGrTCZmGFIlXfMrm EA2VMOwM5bma7VA9qJ2BtyO7oWLYxzCX5UgMkzD+n2RWcPNUIqZajkEJZJlyA8Jc llyYBpj1n7TKAOVGjuFWmLChB784wazfndfdwfQBdxsTnChr1P9v850p4MaQZd+s I/j+2JsSX6yzkMCQSKKe+lda4OSYn6nDzInlNYOu1sgH0C7GoLcu1t/AbGkJmteD qBhhD7nnVnffarL8PPQc7jigc2RJF9HL/D9b/GPhMsWnFjHzW00jyhdEQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm2; bh=/Gz9CsMmbdcrp9kMVCWTTsaDhYUcCaxrF9/HDAwTHKU=; b=O7JOvtlF REuRqYr0lwuabjfsdDy0gu4A7Yxpk3C5u6yZhZtVrqiKxKf1BuNEQjCc5rHaADF7 8fJB13eCs25DGL9K9wulZWIA4UzoiZHMndCodSAkLoAYcCfFgw7rju+2M8HJvcKl s9ThTKwbVm4Y4s9NpXoWoWO0XgzJ60ua6lC19P4+oyJX/TX0xUUw6FqGw7v4pyPa a/25vT1v1h/6A7GuMyyGL5Axy/o7IxVToCeLAEKY9DAVxh9JDGk0um3oH9oGOcrZ xsoQMciqWus28A1Y8k7gcN+dMAGw6dxZ2Wwd1Gcp4CbTMJS/KouYrwGwNOZ8tyRF 0ICr1Y8bQxcVtg== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedugedrjeehgdelkecutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenuc fjughrpefhvffufffkofgjfhgggfestdekredtredttdenucfhrhhomhepufgrmhhuvghl ucfjohhllhgrnhguuceoshgrmhhuvghlsehshhholhhlrghnugdrohhrgheqnecukfhppe ejtddrudefhedrudegkedrudehudenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgr mhepmhgrihhlfhhrohhmpehsrghmuhgvlhesshhhohhllhgrnhgurdhorhhg X-ME-Proxy: Received: from titanium.stl.sholland.net (70-135-148-151.lightspeed.stlsmo.sbcglobal.net [70.135.148.151]) by mail.messagingengine.com (Postfix) with ESMTPA id AFF183280065; Mon, 17 Feb 2020 01:42:51 -0500 (EST) From: Samuel Holland To: Mark Brown , Liam Girdwood , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Vasily Khoruzhick , =?utf-8?q?Myl=C3=A8ne_Josseran?= =?utf-8?q?d?= , Jaroslav Kysela , Takashi Iwai Cc: alsa-devel@alsa-project.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Samuel Holland , stable@kernel.org Subject: [RFC PATCH 02/34] ASoC: sun8i-codec: LRCK is not inverted on A64 Date: Mon, 17 Feb 2020 00:42:18 -0600 Message-Id: <20200217064250.15516-3-samuel@sholland.org> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200217064250.15516-1-samuel@sholland.org> References: <20200217064250.15516-1-samuel@sholland.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On the A64 (tested with the Pinephone), the current code causes the left/right channels to be swapped during I2S playback from the CPU on AIF1, and breaks DSP_A communication with the modem on AIF2. Trusting that the comment in the code is correct, the existing behavior is kept for the A33. Cc: stable@kernel.org Fixes: ec4a95409d5c ("arm64: dts: allwinner: a64: add nodes necessary for analog sound support") Signed-off-by: Samuel Holland --- sound/soc/sunxi/sun8i-codec.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index 55798bc8eae2..14cf31f5c535 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -89,6 +90,7 @@ struct sun8i_codec { struct regmap *regmap; struct clk *clk_module; struct clk *clk_bus; + bool inverted_lrck; }; static int sun8i_codec_runtime_resume(struct device *dev) @@ -209,18 +211,19 @@ static int sun8i_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) value << SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV); /* - * It appears that the DAI and the codec don't share the same - * polarity for the LRCK signal when they mean 'normal' and - * 'inverted' in the datasheet. + * It appears that the DAI and the codec in the A33 SoC don't + * share the same polarity for the LRCK signal when they mean + * 'normal' and 'inverted' in the datasheet. * * Since the DAI here is our regular i2s driver that have been * tested with way more codecs than just this one, it means * that the codec probably gets it backward, and we have to * invert the value here. */ + value ^= scodec->inverted_lrck; regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, BIT(SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV), - !value << SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV); + value << SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV); /* DAI format */ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { @@ -568,6 +571,8 @@ static int sun8i_codec_probe(struct platform_device *pdev) return PTR_ERR(scodec->regmap); } + scodec->inverted_lrck = (uintptr_t)of_device_get_match_data(&pdev->dev); + platform_set_drvdata(pdev, scodec); pm_runtime_enable(&pdev->dev); @@ -606,7 +611,14 @@ static int sun8i_codec_remove(struct platform_device *pdev) } static const struct of_device_id sun8i_codec_of_match[] = { - { .compatible = "allwinner,sun8i-a33-codec" }, + { + .compatible = "allwinner,sun8i-a33-codec", + .data = (void *)1, + }, + { + .compatible = "allwinner,sun50i-a64-codec", + .data = (void *)0, + }, {} }; MODULE_DEVICE_TABLE(of, sun8i_codec_of_match); From patchwork Mon Feb 17 06:42:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 204707 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F3D9AC7619E for ; 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Mon, 17 Feb 2020 01:42:54 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=fm2; bh=if7xr+Sp8ss0f 9YqwMqw18AX7QTuXK6q1CEVj33p/34=; b=nQN89O1nFLZtQYlqH89I0Kmx5EBrM JMjAqr2aBnz9Jw97GauexifTLIRYSYN5hIxTERMKL/QnzrjwN5aKGUtkEqk6vYOi OQFo+90INsKRq+6zr0XagjGvUqLrKOQ+ZYJNLFYuw5h6Ru23GFvWhXGMQohg7HFO mHUpYtDKm1vwTBT7biF9+Ip7G7q0S47GxfFFRkl8ruwXjvGxDqORdboD5d+P7L7v DdyWxwzb0ML3LLFNeU8py2b+wJQiTNxDFhaPQlr/AlgqAuucOWVW95cdkX42zqop XKe2THxeuGSxNzUgTDwkJQynH0mG5K1Seqtyi+t/0J+Rm68wEtBQloIbQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm2; bh=if7xr+Sp8ss0f9YqwMqw18AX7QTuXK6q1CEVj33p/34=; b=NWebf0hC YRw2t54WE710Iix4f2kX216aODyK7MaXe40G22nwq4NM1S8E83ycvMWxTFOngoJy 96tGCTRiGTZsHFpu6iAcP6MXTy/Am8MqItLB46CyXmq8KI1YHtFZ8OVwIupjheOA RT4VNK1gopc22IkSlHqBZcHKl0EQNEMZcrfnvQBkYdPSxuFQv9UpDPtzrxIJk7vm fPiBrvRoofsLEAsnwMHHVqHdz3MiWBpm93ykAsX+BVrF2T5hMr6QnyeTgw3y4oes SSKUAVa6PetTsGFM81A/MZloxu0pHtl/jivQVWKA2eYdFJaPJwrP5oWHd+LbzCRs d/tC/IzkTI1oHg== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedugedrjeehgdelkecutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenuc fjughrpefhvffufffkofgjfhgggfestdekredtredttdenucfhrhhomhepufgrmhhuvghl ucfjohhllhgrnhguuceoshgrmhhuvghlsehshhholhhlrghnugdrohhrgheqnecukfhppe ejtddrudefhedrudegkedrudehudenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgr mhepmhgrihhlfhhrohhmpehsrghmuhgvlhesshhhohhllhgrnhgurdhorhhg X-ME-Proxy: Received: from titanium.stl.sholland.net (70-135-148-151.lightspeed.stlsmo.sbcglobal.net [70.135.148.151]) by mail.messagingengine.com (Postfix) with ESMTPA id 935FC328005E; Mon, 17 Feb 2020 01:42:53 -0500 (EST) From: Samuel Holland To: Mark Brown , Liam Girdwood , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Vasily Khoruzhick , =?utf-8?q?Myl=C3=A8ne_Josseran?= =?utf-8?q?d?= , Jaroslav Kysela , Takashi Iwai Cc: alsa-devel@alsa-project.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Samuel Holland , stable@kernel.org Subject: [RFC PATCH 05/34] ASoC: sun8i-codec: Remove incorrect SND_SOC_DAIFMT_DSP_B Date: Mon, 17 Feb 2020 00:42:21 -0600 Message-Id: <20200217064250.15516-6-samuel@sholland.org> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200217064250.15516-1-samuel@sholland.org> References: <20200217064250.15516-1-samuel@sholland.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org DSP_A and DSP_B are not interchangeable. The timing used by the codec in DSP mode is consistent with DSP_A. This is verified with an EG25-G modem connected to AIF2, as well as by comparing with the BSP driver. Remove the DSP_B option, as it is not supported by the hardware. Cc: stable@kernel.org Fixes: 36c684936fae ("ASoC: Add sun8i digital audio codec") Signed-off-by: Samuel Holland --- sound/soc/sunxi/sun8i-codec.c | 1 - 1 file changed, 1 deletion(-) diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index 33ffbc2be47c..32b7410540c6 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -236,7 +236,6 @@ static int sun8i_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) value = 0x2; break; case SND_SOC_DAIFMT_DSP_A: - case SND_SOC_DAIFMT_DSP_B: value = 0x3; break; default: From patchwork Mon Feb 17 06:42:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 204706 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8849AC35242 for ; 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Mon, 17 Feb 2020 01:42:54 -0500 (EST) From: Samuel Holland To: Mark Brown , Liam Girdwood , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Vasily Khoruzhick , =?utf-8?q?Myl=C3=A8ne_Josseran?= =?utf-8?q?d?= , Jaroslav Kysela , Takashi Iwai Cc: alsa-devel@alsa-project.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Samuel Holland , stable@kernel.org Subject: [RFC PATCH 07/34] ASoC: sun8i-codec: Remove extraneous widgets Date: Mon, 17 Feb 2020 00:42:23 -0600 Message-Id: <20200217064250.15516-8-samuel@sholland.org> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200217064250.15516-1-samuel@sholland.org> References: <20200217064250.15516-1-samuel@sholland.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This driver is for the digital part of the codec, which has no microphone input. These widgets look like they were copied from sun4i-codec. Since they do not belong here, remove them. Cc: stable@kernel.org Fixes: eda85d1fee05 ("ASoC: sun8i-codec: Add ADC support for a33") Signed-off-by: Samuel Holland --- sound/soc/sunxi/sun8i-codec.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index cb3867644363..0eca75d22f13 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -441,10 +441,6 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { SUN8I_MOD_RST_CTL_DAC, 0, NULL, 0), SND_SOC_DAPM_SUPPLY("RST ADC", SUN8I_MOD_RST_CTL, SUN8I_MOD_RST_CTL_ADC, 0, NULL, 0), - - SND_SOC_DAPM_MIC("Headset Mic", NULL), - SND_SOC_DAPM_MIC("Mic", NULL), - }; static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = { From patchwork Mon Feb 17 06:42:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 204708 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4E7EC35242 for ; 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Mon, 17 Feb 2020 01:42:56 -0500 (EST) From: Samuel Holland To: Mark Brown , Liam Girdwood , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Vasily Khoruzhick , =?utf-8?q?Myl=C3=A8ne_Josseran?= =?utf-8?q?d?= , Jaroslav Kysela , Takashi Iwai Cc: alsa-devel@alsa-project.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Samuel Holland , stable@kernel.org Subject: [RFC PATCH 10/34] ASoC: sun8i-codec: Advertise only hardware-supported rates Date: Mon, 17 Feb 2020 00:42:26 -0600 Message-Id: <20200217064250.15516-11-samuel@sholland.org> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200217064250.15516-1-samuel@sholland.org> References: <20200217064250.15516-1-samuel@sholland.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The hardware does not support 64kHz, 88.2kHz, or 176.4kHz sample rates, so the driver should not advertise them. The hardware can handle two additional non-standard sample rates: 12kHz and 24kHz, so declare support for them via SNDRV_PCM_RATE_KNOT. Cc: stable@kernel.org Fixes: 36c684936fae ("ASoC: Add sun8i digital audio codec") Fixes: eda85d1fee05 ("ASoC: sun8i-codec: Add ADC support for a33") Signed-off-by: Samuel Holland --- sound/soc/sunxi/sun8i-codec.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index dca6f4b9d4b8..bf12f5199e96 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -86,6 +86,11 @@ #define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK GENMASK(8, 6) #define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK GENMASK(12, 9) +#define SUN8I_AIF_PCM_RATES (SNDRV_PCM_RATE_8000_48000|\ + SNDRV_PCM_RATE_96000|\ + SNDRV_PCM_RATE_192000|\ + SNDRV_PCM_RATE_KNOT) + struct sun8i_codec { struct regmap *regmap; struct clk *clk_module; @@ -515,7 +520,7 @@ static struct snd_soc_dai_driver sun8i_codec_dai = { .stream_name = "Playback", .channels_min = 1, .channels_max = 2, - .rates = SNDRV_PCM_RATE_8000_192000, + .rates = SUN8I_AIF_PCM_RATES, .formats = SNDRV_PCM_FMTBIT_S16_LE, }, /* capture capabilities */ @@ -523,7 +528,7 @@ static struct snd_soc_dai_driver sun8i_codec_dai = { .stream_name = "Capture", .channels_min = 1, .channels_max = 2, - .rates = SNDRV_PCM_RATE_8000_192000, + .rates = SUN8I_AIF_PCM_RATES, .formats = SNDRV_PCM_FMTBIT_S16_LE, .sig_bits = 24, }, From patchwork Mon Feb 17 06:42:28 2020 Content-Type: text/plain; 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Mon, 17 Feb 2020 01:42:58 -0500 (EST) From: Samuel Holland To: Mark Brown , Liam Girdwood , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Vasily Khoruzhick , =?utf-8?q?Myl=C3=A8ne_Josseran?= =?utf-8?q?d?= , Jaroslav Kysela , Takashi Iwai Cc: alsa-devel@alsa-project.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Samuel Holland Subject: [RFC PATCH 12/34] ASoC: sun8i-codec: Fix AIF1 MODCLK widget name Date: Mon, 17 Feb 2020 00:42:28 -0600 Message-Id: <20200217064250.15516-13-samuel@sholland.org> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200217064250.15516-1-samuel@sholland.org> References: <20200217064250.15516-1-samuel@sholland.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org It should be "AIF1", not "AFI1". Fixes: 36c684936fae ("ASoC: Add sun8i digital audio codec") Fixes: eda85d1fee05 ("ASoC: sun8i-codec: Add ADC support for a33") Signed-off-by: Samuel Holland --- sound/soc/sunxi/sun8i-codec.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index 3d5ed2f4575a..03cfe4e17ff7 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -430,7 +430,7 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { SND_SOC_DAPM_PGA("ADC Right", SND_SOC_NOPM, 0, 0, NULL, 0), /* Clocks */ - SND_SOC_DAPM_SUPPLY("MODCLK AFI1", SUN8I_MOD_CLK_ENA, + SND_SOC_DAPM_SUPPLY("MODCLK AIF1", SUN8I_MOD_CLK_ENA, SUN8I_MOD_CLK_ENA_AIF1, 0, NULL, 0), SND_SOC_DAPM_SUPPLY("MODCLK DAC", SUN8I_MOD_CLK_ENA, SUN8I_MOD_CLK_ENA_DAC, 0, NULL, 0), @@ -461,9 +461,9 @@ static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = { { "AIF1", NULL, "SYSCLK AIF1" }, { "AIF1 PLL", NULL, "AIF1" }, { "RST AIF1", NULL, "AIF1 PLL" }, - { "MODCLK AFI1", NULL, "RST AIF1" }, - { "DAC", NULL, "MODCLK AFI1" }, - { "ADC", NULL, "MODCLK AFI1" }, + { "MODCLK AIF1", NULL, "RST AIF1" }, + { "DAC", NULL, "MODCLK AIF1" }, + { "ADC", NULL, "MODCLK AIF1" }, { "RST DAC", NULL, "SYSCLK" }, { "MODCLK DAC", NULL, "RST DAC" }, From patchwork Mon Feb 17 06:42:29 2020 Content-Type: text/plain; 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Mon, 17 Feb 2020 01:42:58 -0500 (EST) From: Samuel Holland To: Mark Brown , Liam Girdwood , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Vasily Khoruzhick , =?utf-8?q?Myl=C3=A8ne_Josseran?= =?utf-8?q?d?= , Jaroslav Kysela , Takashi Iwai Cc: alsa-devel@alsa-project.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Samuel Holland Subject: [RFC PATCH 13/34] ASoC: sun8i-codec: Fix AIF1_ADCDAT_CTRL field names Date: Mon, 17 Feb 2020 00:42:29 -0600 Message-Id: <20200217064250.15516-14-samuel@sholland.org> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200217064250.15516-1-samuel@sholland.org> References: <20200217064250.15516-1-samuel@sholland.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org They are controlling "AD0" (AIF1 slot 0), not "DA0". Fixes: eda85d1fee05 ("ASoC: sun8i-codec: Add ADC support for a33") Signed-off-by: Samuel Holland --- sound/soc/sunxi/sun8i-codec.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index 03cfe4e17ff7..8b08cb34c503 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -49,8 +49,8 @@ #define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_16 (1 << 4) #define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT 2 #define SUN8I_AIF1_ADCDAT_CTRL 0x044 -#define SUN8I_AIF1_ADCDAT_CTRL_AIF1_DA0L_ENA 15 -#define SUN8I_AIF1_ADCDAT_CTRL_AIF1_DA0R_ENA 14 +#define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_ENA 15 +#define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_ENA 14 #define SUN8I_AIF1_DACDAT_CTRL 0x048 #define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA 15 #define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA 14 @@ -406,10 +406,10 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { /* Analog ADC AIF */ SND_SOC_DAPM_AIF_OUT("AIF1 Slot 0 Left ADC", "Capture", 0, SUN8I_AIF1_ADCDAT_CTRL, - SUN8I_AIF1_ADCDAT_CTRL_AIF1_DA0L_ENA, 0), + SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_ENA, 0), SND_SOC_DAPM_AIF_OUT("AIF1 Slot 0 Right ADC", "Capture", 0, SUN8I_AIF1_ADCDAT_CTRL, - SUN8I_AIF1_ADCDAT_CTRL_AIF1_DA0R_ENA, 0), + SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_ENA, 0), /* Main DAC Outputs (connected to analog codec DAPM context) */ SND_SOC_DAPM_PGA("DAC Left", SND_SOC_NOPM, 0, 0, NULL, 0), From patchwork Mon Feb 17 06:42:30 2020 Content-Type: text/plain; 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Mon, 17 Feb 2020 01:42:59 -0500 (EST) From: Samuel Holland To: Mark Brown , Liam Girdwood , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Vasily Khoruzhick , =?utf-8?q?Myl=C3=A8ne_Josseran?= =?utf-8?q?d?= , Jaroslav Kysela , Takashi Iwai Cc: alsa-devel@alsa-project.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Samuel Holland Subject: [RFC PATCH 14/34] ASoC: sun8i-codec: Fix AIF1_MXR_SRC field names Date: Mon, 17 Feb 2020 00:42:30 -0600 Message-Id: <20200217064250.15516-15-samuel@sholland.org> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200217064250.15516-1-samuel@sholland.org> References: <20200217064250.15516-1-samuel@sholland.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Even though they are for the left channel mixer, they are documented as "MXR_SRC". This matches the naming scheme used for the main DAC. Fixes: eda85d1fee05 ("ASoC: sun8i-codec: Add ADC support for a33") Signed-off-by: Samuel Holland --- sound/soc/sunxi/sun8i-codec.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index 8b08cb34c503..6c2fe8549668 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -55,10 +55,10 @@ #define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA 15 #define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA 14 #define SUN8I_AIF1_MXR_SRC 0x04c -#define SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_AIF1DA0L 15 -#define SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_AIF2DACL 14 -#define SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_ADCL 13 -#define SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_AIF2DACR 12 +#define SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF1DA0L 15 +#define SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACL 14 +#define SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_ADCL 13 +#define SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACR 12 #define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF1DA0R 11 #define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACR 10 #define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_ADCR 9 @@ -373,18 +373,18 @@ static const struct snd_kcontrol_new sun8i_dac_mixer_controls[] = { static const struct snd_kcontrol_new sun8i_input_mixer_controls[] = { SOC_DAPM_DOUBLE("AIF1 Slot 0 Digital ADC Capture Switch", SUN8I_AIF1_MXR_SRC, - SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_AIF1DA0L, + SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF1DA0L, SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF1DA0R, 1, 0), SOC_DAPM_DOUBLE("AIF2 Digital ADC Capture Switch", SUN8I_AIF1_MXR_SRC, - SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_AIF2DACL, + SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACL, SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACR, 1, 0), SOC_DAPM_DOUBLE("AIF1 Data Digital ADC Capture Switch", SUN8I_AIF1_MXR_SRC, - SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_ADCL, + SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_ADCL, SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_ADCR, 1, 0), SOC_DAPM_DOUBLE("AIF2 Inv Digital ADC Capture Switch", SUN8I_AIF1_MXR_SRC, - SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_AIF2DACR, + SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACR, SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACL, 1, 0), }; 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Mon, 17 Feb 2020 01:43:01 -0500 (EST) From: Samuel Holland To: Mark Brown , Liam Girdwood , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Vasily Khoruzhick , =?utf-8?q?Myl=C3=A8ne_Josseran?= =?utf-8?q?d?= , Jaroslav Kysela , Takashi Iwai Cc: alsa-devel@alsa-project.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Samuel Holland Subject: [RFC PATCH 17/34] ASoC: sun8i-codec: Sort masks in a consistent order Date: Mon, 17 Feb 2020 00:42:33 -0600 Message-Id: <20200217064250.15516-18-samuel@sholland.org> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200217064250.15516-1-samuel@sholland.org> References: <20200217064250.15516-1-samuel@sholland.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org All other definitions are sorted from largest to smallest bit number. This makes the AIF1CLK_CTRL mask constants consistent with them. Signed-off-by: Samuel Holland --- sound/soc/sunxi/sun8i-codec.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index 559dec719956..36ce281286b5 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -81,10 +81,10 @@ #define SUN8I_SYS_SR_CTRL_AIF1_FS_MASK GENMASK(15, 12) #define SUN8I_SYS_SR_CTRL_AIF2_FS_MASK GENMASK(11, 8) -#define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT_MASK GENMASK(3, 2) -#define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK GENMASK(5, 4) -#define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK GENMASK(8, 6) #define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK GENMASK(12, 9) +#define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK GENMASK(8, 6) +#define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK GENMASK(5, 4) +#define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT_MASK GENMASK(3, 2) #define SUN8I_AIF_PCM_RATES (SNDRV_PCM_RATE_8000_48000|\ SNDRV_PCM_RATE_96000|\ From patchwork Mon Feb 17 06:42:34 2020 Content-Type: text/plain; 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Mon, 17 Feb 2020 01:43:01 -0500 (EST) From: Samuel Holland To: Mark Brown , Liam Girdwood , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Vasily Khoruzhick , =?utf-8?q?Myl=C3=A8ne_Josseran?= =?utf-8?q?d?= , Jaroslav Kysela , Takashi Iwai Cc: alsa-devel@alsa-project.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Samuel Holland Subject: [RFC PATCH 18/34] ASoC: sun8i-codec: Allow all clock inversion permutations Date: Mon, 17 Feb 2020 00:42:34 -0600 Message-Id: <20200217064250.15516-19-samuel@sholland.org> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200217064250.15516-1-samuel@sholland.org> References: <20200217064250.15516-1-samuel@sholland.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Since the hardware has separate bits for BCLK and LRCK inversion, we can support any combination of normal and inverted clocks. Signed-off-by: Samuel Holland --- sound/soc/sunxi/sun8i-codec.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index 36ce281286b5..f8cde149a92b 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -41,8 +41,7 @@ #define SUN8I_SYS_SR_CTRL_AIF2_FS 8 #define SUN8I_AIF1CLK_CTRL 0x040 #define SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD 15 -#define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV 14 -#define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV 13 +#define SUN8I_AIF1CLK_CTRL_AIF1_CLK_INV 13 #define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV 9 #define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV 6 #define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ 4 @@ -81,6 +80,7 @@ #define SUN8I_SYS_SR_CTRL_AIF1_FS_MASK GENMASK(15, 12) #define SUN8I_SYS_SR_CTRL_AIF2_FS_MASK GENMASK(11, 8) +#define SUN8I_AIF1CLK_CTRL_AIF1_CLK_INV_MASK GENMASK(14, 13) #define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK GENMASK(12, 9) #define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK GENMASK(8, 6) #define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK GENMASK(5, 4) @@ -205,16 +205,18 @@ static int sun8i_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) case SND_SOC_DAIFMT_NB_NF: /* Normal */ value = 0x0; break; - case SND_SOC_DAIFMT_IB_IF: /* Inversion */ + case SND_SOC_DAIFMT_NB_IF: /* Inverted LRCK */ value = 0x1; break; + case SND_SOC_DAIFMT_IB_NF: /* Inverted BCLK */ + value = 0x2; + break; + case SND_SOC_DAIFMT_IB_IF: /* Both inverted */ + value = 0x3; + break; default: return -EINVAL; } - regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, - BIT(SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV), - value << SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV); - /* * It appears that the DAI and the codec in the A33 SoC don't * share the same polarity for the LRCK signal when they mean @@ -227,8 +229,8 @@ static int sun8i_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) */ value ^= scodec->inverted_lrck; regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, - BIT(SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV), - value << SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV); + SUN8I_AIF1CLK_CTRL_AIF1_CLK_INV_MASK, + value << SUN8I_AIF1CLK_CTRL_AIF1_CLK_INV); /* DAI format */ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { From patchwork Mon Feb 17 06:42:36 2020 Content-Type: text/plain; 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Mon, 17 Feb 2020 01:43:02 -0500 (EST) From: Samuel Holland To: Mark Brown , Liam Girdwood , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Vasily Khoruzhick , =?utf-8?q?Myl=C3=A8ne_Josseran?= =?utf-8?q?d?= , Jaroslav Kysela , Takashi Iwai Cc: alsa-devel@alsa-project.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Samuel Holland Subject: [RFC PATCH 20/34] ASoC: sun8i-codec: Support 8/20/24-bit word sizes Date: Mon, 17 Feb 2020 00:42:36 -0600 Message-Id: <20200217064250.15516-21-samuel@sholland.org> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200217064250.15516-1-samuel@sholland.org> References: <20200217064250.15516-1-samuel@sholland.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The codec hardware natively supports 8, 16, 20, and 24-bit word sizes. However, it only supports slot widths that are a multiple of 16 bits. So we can only support the 20-bit and 24-bit formats that are padded to 32 bits. This doesn't cost anything, because the DMA controller on the CPU side only supports power-of-two byte sizes anyway. S8, S16_LE, and S24_LE were tested using a modified version of the sun4i-i2s driver as the CPU end of the DAI link. S20_LE was not tested due to poor userspace support; it should work the same. In 8 bit mono mode, the computed BCLK/LRCK divider will be less than the minimum value 16. This is fine; there will just be padding after the data bits, similar to how S20_LE and S24_LE always have padding. Signed-off-by: Samuel Holland --- sound/soc/sunxi/sun8i-codec.c | 47 ++++++++++++++++++++++++----------- 1 file changed, 32 insertions(+), 15 deletions(-) diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index 2df899daec67..b915e62fa005 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -45,7 +45,6 @@ #define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV 9 #define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV 6 #define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ 4 -#define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_16 (1 << 4) #define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT 2 #define SUN8I_AIF1CLK_CTRL_AIF1_MONO_PCM 1 #define SUN8I_AIF1_ADCDAT_CTRL 0x044 @@ -87,6 +86,10 @@ #define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK GENMASK(5, 4) #define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT_MASK GENMASK(3, 2) +#define SUN8I_AIF_PCM_FMTS (SNDRV_PCM_FMTBIT_S8|\ + SNDRV_PCM_FMTBIT_S16_LE|\ + SNDRV_PCM_FMTBIT_S20_LE|\ + SNDRV_PCM_FMTBIT_S24_LE) #define SUN8I_AIF_PCM_RATES (SNDRV_PCM_RATE_8000_48000|\ SNDRV_PCM_RATE_96000|\ SNDRV_PCM_RATE_192000|\ @@ -307,7 +310,9 @@ static int sun8i_codec_get_lrck_div(unsigned int channels, { unsigned int div = word_size * channels; - if (div < 16 || div > 256) + if (div < 16) + div = 16; + if (div > 256) return -EINVAL; return ilog2(div) - 4; @@ -318,27 +323,19 @@ static int sun8i_codec_hw_params(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { struct sun8i_codec *scodec = snd_soc_component_get_drvdata(dai->component); + unsigned int slot_width = params_physical_width(params); unsigned int channels = params_channels(params); int sample_rate, lrck_div; u8 bclk_div; u32 value; - /* - * The CPU DAI handles only a sample of 16 bits. Configure the - * codec to handle this type of sample resolution. - */ - regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, - SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK, - SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_16); - bclk_div = sun8i_codec_get_bclk_div(scodec, params_rate(params), - channels, 16); + channels, slot_width); regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK, bclk_div << SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV); - lrck_div = sun8i_codec_get_lrck_div(channels, - params_physical_width(params)); + lrck_div = sun8i_codec_get_lrck_div(channels, slot_width); if (lrck_div < 0) return lrck_div; @@ -346,6 +343,26 @@ static int sun8i_codec_hw_params(struct snd_pcm_substream *substream, SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK, lrck_div << SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV); + switch (params_width(params)) { + case 8: + value = 0x0; + break; + case 16: + value = 0x1; + break; + case 20: + value = 0x2; + break; + case 24: + value = 0x3; + break; + default: + return -EINVAL; + } + regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, + SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK, + value << SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ); + value = channels == 1; regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, BIT(SUN8I_AIF1CLK_CTRL_AIF1_MONO_PCM), @@ -533,7 +550,7 @@ static struct snd_soc_dai_driver sun8i_codec_dai = { .channels_min = 1, .channels_max = 2, .rates = SUN8I_AIF_PCM_RATES, - .formats = SNDRV_PCM_FMTBIT_S16_LE, + .formats = SUN8I_AIF_PCM_FMTS, }, /* capture capabilities */ .capture = { @@ -541,7 +558,7 @@ static struct snd_soc_dai_driver sun8i_codec_dai = { .channels_min = 1, .channels_max = 2, .rates = SUN8I_AIF_PCM_RATES, - .formats = SNDRV_PCM_FMTBIT_S16_LE, + .formats = SUN8I_AIF_PCM_FMTS, .sig_bits = 24, }, /* pcm operations */ From patchwork Mon Feb 17 06:42:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 204714 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D3A8C7619B for ; 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Mon, 17 Feb 2020 01:43:04 -0500 (EST) From: Samuel Holland To: Mark Brown , Liam Girdwood , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Vasily Khoruzhick , =?utf-8?q?Myl=C3=A8ne_Josseran?= =?utf-8?q?d?= , Jaroslav Kysela , Takashi Iwai Cc: alsa-devel@alsa-project.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Samuel Holland Subject: [RFC PATCH 23/34] ASoC: sun8i-codec: Clean up DAC widgets Date: Mon, 17 Feb 2020 00:42:39 -0600 Message-Id: <20200217064250.15516-24-samuel@sholland.org> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200217064250.15516-1-samuel@sholland.org> References: <20200217064250.15516-1-samuel@sholland.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Again, rename the widgets and controls to match their actual function (and disambiguate the mixers), then sort the widgets and routes in a topological sink<-source ordering. Signed-off-by: Samuel Holland --- sound/soc/sunxi/sun8i-codec.c | 61 ++++++++++++++++++----------------- 1 file changed, 32 insertions(+), 29 deletions(-) diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index 6f589e93850a..5dfaf656b5b1 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -384,23 +384,6 @@ static int sun8i_codec_hw_params(struct snd_pcm_substream *substream, return 0; } -static const struct snd_kcontrol_new sun8i_dac_mixer_controls[] = { - SOC_DAPM_DOUBLE("AIF1 Slot 0 Digital DAC Playback Switch", - SUN8I_DAC_MXR_SRC, - SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA0L, - SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA0R, 1, 0), - SOC_DAPM_DOUBLE("AIF1 Slot 1 Digital DAC Playback Switch", - SUN8I_DAC_MXR_SRC, - SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA1L, - SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA1R, 1, 0), - SOC_DAPM_DOUBLE("AIF2 Digital DAC Playback Switch", SUN8I_DAC_MXR_SRC, - SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF2DACL, - SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF2DACR, 1, 0), - SOC_DAPM_DOUBLE("ADC Digital DAC Playback Switch", SUN8I_DAC_MXR_SRC, - SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_ADCL, - SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR, 1, 0), -}; - static const struct snd_kcontrol_new sun8i_aif1_ad0_mixer_controls[] = { SOC_DAPM_DOUBLE("AIF1 AD0 Mixer AIF1 DA0 Capture Switch", SUN8I_AIF1_MXR_SRC, @@ -420,6 +403,25 @@ static const struct snd_kcontrol_new sun8i_aif1_ad0_mixer_controls[] = { SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACL, 1, 0), }; +static const struct snd_kcontrol_new sun8i_dac_mixer_controls[] = { + SOC_DAPM_DOUBLE("DAC Mixer AIF1 DA0 Playback Switch", + SUN8I_DAC_MXR_SRC, + SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA0L, + SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA0R, 1, 0), + SOC_DAPM_DOUBLE("DAC Mixer AIF1 DA1 Playback Switch", + SUN8I_DAC_MXR_SRC, + SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA1L, + SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA1R, 1, 0), + SOC_DAPM_DOUBLE("DAC Mixer AIF2 DAC Playback Switch", + SUN8I_DAC_MXR_SRC, + SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF2DACL, + SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF2DACR, 1, 0), + SOC_DAPM_DOUBLE("DAC Mixer ADC Playback Switch", + SUN8I_DAC_MXR_SRC, + SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_ADCL, + SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR, 1, 0), +}; + static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { /* AIF "ADC" Outputs */ SND_SOC_DAPM_AIF_OUT("AIF1 AD0 Left", "Capture", 0, @@ -450,10 +452,10 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { SND_SOC_DAPM_SUPPLY("DAC", SUN8I_DAC_DIG_CTRL, SUN8I_DAC_DIG_CTRL_ENDA, 0, NULL, 0), - /* DAC and ADC Mixers */ - SOC_MIXER_ARRAY("Left Digital DAC Mixer", SND_SOC_NOPM, 0, 0, + /* Main DAC Mixers */ + SOC_MIXER_ARRAY("DAC Left Mixer", SND_SOC_NOPM, 0, 0, sun8i_dac_mixer_controls), - SOC_MIXER_ARRAY("Right Digital DAC Mixer", SND_SOC_NOPM, 0, 0, + SOC_MIXER_ARRAY("DAC Right Mixer", SND_SOC_NOPM, 0, 0, sun8i_dac_mixer_controls), /* Main ADC Inputs (connected to analog codec DAPM context) */ @@ -505,20 +507,21 @@ static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = { { "AIF1 DA0 Left", NULL, "AIF1CLK" }, { "AIF1 DA0 Right", NULL, "AIF1CLK" }, - /* DAC Routes */ - { "DAC Left", NULL, "Left Digital DAC Mixer" }, - { "DAC Right", NULL, "Right Digital DAC Mixer" }, + /* Main DAC Output Routes */ + { "DAC Left", NULL, "DAC Left Mixer" }, + { "DAC Right", NULL, "DAC Right Mixer" }, { "DAC Left", NULL, "DAC" }, { "DAC Right", NULL, "DAC" }, - /* DAC Mixer Routes */ - { "Left Digital DAC Mixer", "AIF1 Slot 0 Digital DAC Playback Switch", - "AIF1 DA0 Left"}, - { "Right Digital DAC Mixer", "AIF1 Slot 0 Digital DAC Playback Switch", - "AIF1 DA0 Right"}, + /* Main DAC Mixer Routes */ + { "DAC Left Mixer", "DAC Mixer AIF1 DA0 Playback Switch", "AIF1 DA0 Left" }, + { "DAC Left Mixer", "DAC Mixer ADC Playback Switch", "ADC Left" }, + + { "DAC Right Mixer", "DAC Mixer AIF1 DA0 Playback Switch", "AIF1 DA0 Right" }, + { "DAC Right Mixer", "DAC Mixer ADC Playback Switch", "ADC Right" }, - /* ADC Routes */ + /* Main ADC Input Routes */ { "ADC Left", NULL, "ADC" }, { "ADC Right", NULL, "ADC" }, From patchwork Mon Feb 17 06:42:42 2020 Content-Type: text/plain; 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Mon, 17 Feb 2020 01:43:06 -0500 (EST) From: Samuel Holland To: Mark Brown , Liam Girdwood , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Vasily Khoruzhick , =?utf-8?q?Myl=C3=A8ne_Josseran?= =?utf-8?q?d?= , Jaroslav Kysela , Takashi Iwai Cc: alsa-devel@alsa-project.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Samuel Holland Subject: [RFC PATCH 26/34] ASoC: sun8i-codec: Add support for AIF3 Date: Mon, 17 Feb 2020 00:42:42 -0600 Message-Id: <20200217064250.15516-27-samuel@sholland.org> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200217064250.15516-1-samuel@sholland.org> References: <20200217064250.15516-1-samuel@sholland.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds the new DAI, clocks, widgets, and routes for AIF2. AIF3 lacks some of the configuration of the other AIFs. Skip setting bits that are unavailable on AIF3. It is not documented what the actual settings for AIF3 are, so those parameters cannot be validated. AIF3 can pull its bitclock from AIF1 or AIF2. Since the normal usage of AIF3 is for low-bitrate mono audio, similar to AIF2, let's set the AIF3 clock to AIF2 for now. Signed-off-by: Samuel Holland --- sound/soc/sunxi/sun8i-codec.c | 241 +++++++++++++++++++++++++--------- 1 file changed, 178 insertions(+), 63 deletions(-) diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index ce7038bcbdc1..71c4c1f47201 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -34,11 +34,13 @@ #define SUN8I_MOD_CLK_ENA 0x010 #define SUN8I_MOD_CLK_ENA_AIF1 15 #define SUN8I_MOD_CLK_ENA_AIF2 14 +#define SUN8I_MOD_CLK_ENA_AIF3 13 #define SUN8I_MOD_CLK_ENA_ADC 3 #define SUN8I_MOD_CLK_ENA_DAC 2 #define SUN8I_MOD_RST_CTL 0x014 #define SUN8I_MOD_RST_CTL_AIF1 15 #define SUN8I_MOD_RST_CTL_AIF2 14 +#define SUN8I_MOD_RST_CTL_AIF3 13 #define SUN8I_MOD_RST_CTL_ADC 3 #define SUN8I_MOD_RST_CTL_DAC 2 #define SUN8I_SYS_SR_CTRL 0x018 @@ -81,6 +83,15 @@ #define SUN8I_AIF2_MXR_SRC_ADCR_MXR_SRC_AIF1DA1R 10 #define SUN8I_AIF2_MXR_SRC_ADCR_MXR_SRC_AIF2DACL 9 #define SUN8I_AIF2_MXR_SRC_ADCR_MXR_SRC_ADCR 8 +#define SUN8I_AIF3_CLK_CTRL_AIF3_CLOCK_SRC_AIF1 (0x0 << 0) +#define SUN8I_AIF3_CLK_CTRL_AIF3_CLOCK_SRC_AIF2 (0x1 << 0) +#define SUN8I_AIF3_CLK_CTRL_AIF3_CLOCK_SRC_AIF1CLK (0x2 << 0) +#define SUN8I_AIF3_DACDAT_CTRL 0x0c8 +#define SUN8I_AIF3_DACDAT_CTRL_AIF3_LOOP_ENA 0 +#define SUN8I_AIF3_PATH_CTRL 0x0cc +#define SUN8I_AIF3_PATH_CTRL_AIF3_ADC_SRC 10 +#define SUN8I_AIF3_PATH_CTRL_AIF2_DAC_SRC 8 +#define SUN8I_AIF3_PATH_CTRL_AIF3_PINS_TRI 7 #define SUN8I_ADC_DIG_CTRL 0x100 #define SUN8I_ADC_DIG_CTRL_ENAD 15 #define SUN8I_ADC_DIG_CTRL_ADOUT_DTS 2 @@ -105,6 +116,7 @@ #define SUN8I_AIF_CLK_CTRL_LRCK_DIV_MASK GENMASK(8, 6) #define SUN8I_AIF_CLK_CTRL_WORD_SIZ_MASK GENMASK(5, 4) #define SUN8I_AIF_CLK_CTRL_DATA_FMT_MASK GENMASK(3, 2) +#define SUN8I_AIF3_CLK_CTRL_AIF3_CLOCK_SRC_MASK GENMASK(1, 0) #define SUN8I_AIF_PCM_FMTS (SNDRV_PCM_FMTBIT_S8|\ SNDRV_PCM_FMTBIT_S16_LE|\ @@ -210,20 +222,22 @@ static int sun8i_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) unsigned int reg = SUN8I_AIF_CLK_CTRL(dai->id); u32 value; - /* clock masters */ - switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { - case SND_SOC_DAIFMT_CBS_CFS: /* Codec slave, DAI master */ - value = 0x1; - break; - case SND_SOC_DAIFMT_CBM_CFM: /* Codec Master, DAI slave */ - value = 0x0; - break; - default: - return -EINVAL; + if (dai->id < 3) { + /* clock masters */ + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBS_CFS: /* Codec slave, DAI master */ + value = 0x1; + break; + case SND_SOC_DAIFMT_CBM_CFM: /* Codec Master, DAI slave */ + value = 0x0; + break; + default: + return -EINVAL; + } + regmap_update_bits(scodec->regmap, reg, + BIT(SUN8I_AIF_CLK_CTRL_MSTR_MOD), + value << SUN8I_AIF_CLK_CTRL_MSTR_MOD); } - regmap_update_bits(scodec->regmap, reg, - BIT(SUN8I_AIF_CLK_CTRL_MSTR_MOD), - value << SUN8I_AIF_CLK_CTRL_MSTR_MOD); /* clock inversion */ switch (fmt & SND_SOC_DAIFMT_INV_MASK) { @@ -257,26 +271,28 @@ static int sun8i_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) SUN8I_AIF_CLK_CTRL_CLK_INV_MASK, value << SUN8I_AIF_CLK_CTRL_CLK_INV); - /* DAI format */ - switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { - case SND_SOC_DAIFMT_I2S: - value = 0x0; - break; - case SND_SOC_DAIFMT_LEFT_J: - value = 0x1; - break; - case SND_SOC_DAIFMT_RIGHT_J: - value = 0x2; - break; - case SND_SOC_DAIFMT_DSP_A: - value = 0x3; - break; - default: - return -EINVAL; + if (dai->id < 3) { + /* DAI format */ + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + value = 0x0; + break; + case SND_SOC_DAIFMT_LEFT_J: + value = 0x1; + break; + case SND_SOC_DAIFMT_RIGHT_J: + value = 0x2; + break; + case SND_SOC_DAIFMT_DSP_A: + value = 0x3; + break; + default: + return -EINVAL; + } + regmap_update_bits(scodec->regmap, reg, + SUN8I_AIF_CLK_CTRL_DATA_FMT_MASK, + value << SUN8I_AIF_CLK_CTRL_DATA_FMT); } - regmap_update_bits(scodec->regmap, reg, - SUN8I_AIF_CLK_CTRL_DATA_FMT_MASK, - value << SUN8I_AIF_CLK_CTRL_DATA_FMT); return 0; } @@ -351,19 +367,25 @@ static int sun8i_codec_hw_params(struct snd_pcm_substream *substream, u8 bclk_div; u32 value; - bclk_div = sun8i_codec_get_bclk_div(scodec, params_rate(params), - channels, slot_width); - regmap_update_bits(scodec->regmap, reg, - SUN8I_AIF_CLK_CTRL_BCLK_DIV_MASK, - bclk_div << SUN8I_AIF_CLK_CTRL_BCLK_DIV); - - lrck_div = sun8i_codec_get_lrck_div(channels, slot_width); - if (lrck_div < 0) - return lrck_div; - - regmap_update_bits(scodec->regmap, reg, - SUN8I_AIF_CLK_CTRL_LRCK_DIV_MASK, - lrck_div << SUN8I_AIF_CLK_CTRL_LRCK_DIV); + if (dai->id < 3) { + bclk_div = sun8i_codec_get_bclk_div(scodec, params_rate(params), + channels, slot_width); + regmap_update_bits(scodec->regmap, reg, + SUN8I_AIF_CLK_CTRL_BCLK_DIV_MASK, + bclk_div << SUN8I_AIF_CLK_CTRL_BCLK_DIV); + + lrck_div = sun8i_codec_get_lrck_div(channels, slot_width); + if (lrck_div < 0) + return lrck_div; + + regmap_update_bits(scodec->regmap, reg, + SUN8I_AIF_CLK_CTRL_LRCK_DIV_MASK, + lrck_div << SUN8I_AIF_CLK_CTRL_LRCK_DIV); + } else { + regmap_update_bits(scodec->regmap, reg, + SUN8I_AIF3_CLK_CTRL_AIF3_CLOCK_SRC_MASK, + SUN8I_AIF3_CLK_CTRL_AIF3_CLOCK_SRC_AIF2); + } switch (params_width(params)) { case 8: @@ -385,18 +407,20 @@ static int sun8i_codec_hw_params(struct snd_pcm_substream *substream, SUN8I_AIF_CLK_CTRL_WORD_SIZ_MASK, value << SUN8I_AIF_CLK_CTRL_WORD_SIZ); - value = channels == 1; - regmap_update_bits(scodec->regmap, reg, - BIT(SUN8I_AIF_CLK_CTRL_MONO_PCM), - value << SUN8I_AIF_CLK_CTRL_MONO_PCM); + if (dai->id < 3) { + value = channels == 1; + regmap_update_bits(scodec->regmap, reg, + BIT(SUN8I_AIF_CLK_CTRL_MONO_PCM), + value << SUN8I_AIF_CLK_CTRL_MONO_PCM); - sample_rate = sun8i_codec_get_hw_rate(params); - if (sample_rate < 0) - return sample_rate; + sample_rate = sun8i_codec_get_hw_rate(params); + if (sample_rate < 0) + return sample_rate; - regmap_update_bits(scodec->regmap, SUN8I_SYS_SR_CTRL, - SUN8I_SYS_SR_CTRL_AIF_FS_MASK(dai->id), - sample_rate << SUN8I_SYS_SR_CTRL_AIF_FS(dai->id)); + regmap_update_bits(scodec->regmap, SUN8I_SYS_SR_CTRL, + SUN8I_SYS_SR_CTRL_AIF_FS_MASK(dai->id), + sample_rate << SUN8I_SYS_SR_CTRL_AIF_FS(dai->id)); + } return 0; } @@ -459,8 +483,56 @@ static struct snd_soc_dai_driver sun8i_codec_dais[] = { .symmetric_channels = 1, .symmetric_samplebits = 1, }, + { + .name = "sun8i-codec-aif3", + .id = 3, + /* playback capabilities */ + .playback = { + .stream_name = "AIF3 Playback", + .channels_min = 1, + .channels_max = 1, + .rates = SUN8I_AIF_PCM_RATES, + .formats = SUN8I_AIF_PCM_FMTS, + }, + /* capture capabilities */ + .capture = { + .stream_name = "AIF3 Capture", + .channels_min = 1, + .channels_max = 1, + .rates = SUN8I_AIF_PCM_RATES, + .formats = SUN8I_AIF_PCM_FMTS, + .sig_bits = 24, + }, + /* pcm operations */ + .ops = &sun8i_codec_dai_ops, + .symmetric_rates = 1, + .symmetric_channels = 1, + .symmetric_samplebits = 1, + }, }; +static const char *const sun8i_aif3_mux_enum_names[] = { + "None", "AIF2 Left", "AIF2 Right" +}; + +static SOC_ENUM_SINGLE_DECL(sun8i_aif3_adc_mux_enum, + SUN8I_AIF3_PATH_CTRL, + SUN8I_AIF3_PATH_CTRL_AIF3_ADC_SRC, + sun8i_aif3_mux_enum_names); + +static const struct snd_kcontrol_new sun8i_aif3_adc_mux_control = + SOC_DAPM_ENUM("AIF3 ADC Capture Route", + sun8i_aif3_adc_mux_enum); + +static SOC_ENUM_SINGLE_DECL(sun8i_aif2_dac_mux_enum, + SUN8I_AIF3_PATH_CTRL, + SUN8I_AIF3_PATH_CTRL_AIF2_DAC_SRC, + sun8i_aif3_mux_enum_names); + +static const struct snd_kcontrol_new sun8i_aif2_dac_mux_control = + SOC_DAPM_ENUM("AIF3 DAC Playback Route", + sun8i_aif2_dac_mux_enum); + static const struct snd_kcontrol_new sun8i_aif1_ad0_mixer_controls[] = { SOC_DAPM_DOUBLE("AIF1 AD0 Mixer AIF1 DA0 Capture Switch", SUN8I_AIF1_MXR_SRC, @@ -534,6 +606,13 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { SUN8I_AIF2_ADCDAT_CTRL, SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCR_ENA, 0), + SND_SOC_DAPM_AIF_OUT("AIF3 ADC", "AIF3 Capture", 0, + SND_SOC_NOPM, 0, 0), + + /* AIF "ADC" Muxes */ + SND_SOC_DAPM_MUX("AIF3 ADC Capture Route", SND_SOC_NOPM, 0, 0, + &sun8i_aif3_adc_mux_control), + /* AIF "ADC" Mixers */ SOC_MIXER_ARRAY("AIF1 AD0 Left Mixer", SND_SOC_NOPM, 0, 0, sun8i_aif1_ad0_mixer_controls), @@ -545,6 +624,12 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { SOC_MIXER_ARRAY("AIF2 ADC Right Mixer", SND_SOC_NOPM, 0, 0, sun8i_aif2_adc_mixer_controls), + /* AIF "DAC" Muxes */ + SND_SOC_DAPM_MUX("AIF2 DAC Left Mux", SND_SOC_NOPM, 0, 0, + &sun8i_aif2_dac_mux_control), + SND_SOC_DAPM_MUX("AIF2 DAC Right Mux", SND_SOC_NOPM, 0, 0, + &sun8i_aif2_dac_mux_control), + /* AIF "DAC" Inputs */ SND_SOC_DAPM_AIF_IN("AIF1 DA0 Left", "AIF1 Playback", 0, SUN8I_AIF1_DACDAT_CTRL, @@ -560,6 +645,9 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { SUN8I_AIF2_DACDAT_CTRL, SUN8I_AIF2_DACDAT_CTRL_AIF2_DACR_ENA, 0), + SND_SOC_DAPM_AIF_IN("AIF3 DAC", "AIF3 Playback", 0, + SND_SOC_NOPM, 0, 0), + /* Main DAC Outputs (connected to analog codec DAPM context) */ SND_SOC_DAPM_PGA("DAC Left", SND_SOC_NOPM, 0, 0, NULL, 0), SND_SOC_DAPM_PGA("DAC Right", SND_SOC_NOPM, 0, 0, NULL, 0), @@ -585,6 +673,8 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { SUN8I_MOD_RST_CTL_AIF1, 0, NULL, 0), SND_SOC_DAPM_SUPPLY("RST AIF2", SUN8I_MOD_RST_CTL, SUN8I_MOD_RST_CTL_AIF2, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("RST AIF3", SUN8I_MOD_RST_CTL, + SUN8I_MOD_RST_CTL_AIF3, 0, NULL, 0), SND_SOC_DAPM_SUPPLY("RST ADC", SUN8I_MOD_RST_CTL, SUN8I_MOD_RST_CTL_ADC, 0, NULL, 0), SND_SOC_DAPM_SUPPLY("RST DAC", SUN8I_MOD_RST_CTL, @@ -595,6 +685,8 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { SUN8I_MOD_CLK_ENA_AIF1, 0, NULL, 0), SND_SOC_DAPM_SUPPLY("MODCLK AIF2", SUN8I_MOD_CLK_ENA, SUN8I_MOD_CLK_ENA_AIF2, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("MODCLK AIF3", SUN8I_MOD_CLK_ENA, + SUN8I_MOD_CLK_ENA_AIF3, 0, NULL, 0), SND_SOC_DAPM_SUPPLY("MODCLK ADC", SUN8I_MOD_CLK_ENA, SUN8I_MOD_CLK_ENA_ADC, 0, NULL, 0), SND_SOC_DAPM_SUPPLY("MODCLK DAC", SUN8I_MOD_CLK_ENA, @@ -623,25 +715,40 @@ static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = { { "AIF2 ADC Left", NULL, "AIF2CLK" }, { "AIF2 ADC Right", NULL, "AIF2CLK" }, + { "AIF3 ADC", NULL, "AIF3 ADC Capture Route" }, + + /* AIF "ADC" Mux Routes */ + { "AIF3 ADC Capture Route", "AIF2 Left", "AIF2 ADC Left Mixer" }, + { "AIF3 ADC Capture Route", "AIF2 Right", "AIF2 ADC Right Mixer" }, + /* AIF "ADC" Mixer Routes */ { "AIF1 AD0 Left Mixer", "AIF1 AD0 Mixer AIF1 DA0 Capture Switch", "AIF1 DA0 Left" }, - { "AIF1 AD0 Left Mixer", "AIF1 AD0 Mixer AIF2 DAC Capture Switch", "AIF2 DAC Left" }, + { "AIF1 AD0 Left Mixer", "AIF1 AD0 Mixer AIF2 DAC Capture Switch", "AIF2 DAC Left Mux" }, { "AIF1 AD0 Left Mixer", "AIF1 AD0 Mixer ADC Capture Switch", "ADC Left" }, - { "AIF1 AD0 Left Mixer", "AIF1 AD0 Mixer AIF2 DAC Rev Capture Switch", "AIF2 DAC Right" }, + { "AIF1 AD0 Left Mixer", "AIF1 AD0 Mixer AIF2 DAC Rev Capture Switch", "AIF2 DAC Right Mux" }, { "AIF1 AD0 Right Mixer", "AIF1 AD0 Mixer AIF1 DA0 Capture Switch", "AIF1 DA0 Right" }, - { "AIF1 AD0 Right Mixer", "AIF1 AD0 Mixer AIF2 DAC Capture Switch", "AIF2 DAC Right" }, + { "AIF1 AD0 Right Mixer", "AIF1 AD0 Mixer AIF2 DAC Capture Switch", "AIF2 DAC Right Mux" }, { "AIF1 AD0 Right Mixer", "AIF1 AD0 Mixer ADC Capture Switch", "ADC Right" }, - { "AIF1 AD0 Right Mixer", "AIF1 AD0 Mixer AIF2 DAC Rev Capture Switch", "AIF2 DAC Left" }, + { "AIF1 AD0 Right Mixer", "AIF1 AD0 Mixer AIF2 DAC Rev Capture Switch", "AIF2 DAC Left Mux" }, { "AIF2 ADC Left Mixer", "AIF2 ADC Mixer AIF1 DA0 Capture Switch", "AIF1 DA0 Left" }, - { "AIF2 ADC Left Mixer", "AIF2 ADC Mixer AIF2 DAC Rev Capture Switch", "AIF2 DAC Right" }, + { "AIF2 ADC Left Mixer", "AIF2 ADC Mixer AIF2 DAC Rev Capture Switch", "AIF2 DAC Right Mux" }, { "AIF2 ADC Left Mixer", "AIF2 ADC Mixer ADC Capture Switch", "ADC Left" }, { "AIF2 ADC Right Mixer", "AIF2 ADC Mixer AIF1 DA0 Capture Switch", "AIF1 DA0 Right" }, - { "AIF2 ADC Right Mixer", "AIF2 ADC Mixer AIF2 DAC Rev Capture Switch", "AIF2 DAC Left" }, + { "AIF2 ADC Right Mixer", "AIF2 ADC Mixer AIF2 DAC Rev Capture Switch", "AIF2 DAC Left Mux" }, { "AIF2 ADC Right Mixer", "AIF2 ADC Mixer ADC Capture Switch", "ADC Right" }, + /* AIF "DAC" Mux Routes */ + { "AIF2 DAC Left Mux", "None", "AIF2 DAC Left" }, + { "AIF2 DAC Left Mux", "AIF2 Left", "AIF3 DAC" }, + { "AIF2 DAC Left Mux", "AIF2 Right", "AIF2 DAC Left" }, + + { "AIF2 DAC Right Mux", "None", "AIF2 DAC Right" }, + { "AIF2 DAC Right Mux", "AIF2 Left", "AIF2 DAC Right" }, + { "AIF2 DAC Right Mux", "AIF2 Right", "AIF3 DAC" }, + /* AIF "DAC" Input Routes */ { "AIF1 DA0 Left", NULL, "AIF1CLK" }, { "AIF1 DA0 Right", NULL, "AIF1CLK" }, @@ -658,11 +765,11 @@ static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = { /* Main DAC Mixer Routes */ { "DAC Left Mixer", "DAC Mixer AIF1 DA0 Playback Switch", "AIF1 DA0 Left" }, - { "DAC Left Mixer", "DAC Mixer AIF2 DAC Playback Switch", "AIF2 DAC Left" }, + { "DAC Left Mixer", "DAC Mixer AIF2 DAC Playback Switch", "AIF2 DAC Left Mux" }, { "DAC Left Mixer", "DAC Mixer ADC Playback Switch", "ADC Left" }, { "DAC Right Mixer", "DAC Mixer AIF1 DA0 Playback Switch", "AIF1 DA0 Right" }, - { "DAC Right Mixer", "DAC Mixer AIF2 DAC Playback Switch", "AIF2 DAC Right" }, + { "DAC Right Mixer", "DAC Mixer AIF2 DAC Playback Switch", "AIF2 DAC Right Mux" }, { "DAC Right Mixer", "DAC Mixer ADC Playback Switch", "ADC Right" }, /* Main ADC Input Routes */ @@ -680,18 +787,26 @@ static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = { { "AIF2 DAC Left", NULL, "RST AIF2" }, { "AIF2 DAC Right", NULL, "RST AIF2" }, + /* AIF3 gets its bitclock from AIF2 */ + { "AIF3 ADC", NULL, "RST AIF2" }, + { "AIF3 ADC", NULL, "RST AIF3" }, + { "AIF3 DAC", NULL, "RST AIF2" }, + { "AIF3 DAC", NULL, "RST AIF3" }, + { "ADC", NULL, "RST ADC" }, { "DAC", NULL, "RST DAC" }, /* Module Reset Routes */ { "RST AIF1", NULL, "MODCLK AIF1" }, { "RST AIF2", NULL, "MODCLK AIF2" }, + { "RST AIF3", NULL, "MODCLK AIF3" }, { "RST ADC", NULL, "MODCLK ADC" }, { "RST DAC", NULL, "MODCLK DAC" }, /* Module Clock Routes */ { "MODCLK AIF1", NULL, "SYSCLK" }, { "MODCLK AIF2", NULL, "SYSCLK" }, + { "MODCLK AIF3", NULL, "SYSCLK" }, { "MODCLK ADC", NULL, "SYSCLK" }, { "MODCLK DAC", NULL, "SYSCLK" }, From patchwork Mon Feb 17 06:42:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 204719 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) 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mail.messagingengine.com (Postfix) with ESMTPA id 27F223280059; Mon, 17 Feb 2020 01:43:07 -0500 (EST) From: Samuel Holland To: Mark Brown , Liam Girdwood , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Vasily Khoruzhick , =?utf-8?q?Myl=C3=A8ne_Josseran?= =?utf-8?q?d?= , Jaroslav Kysela , Takashi Iwai Cc: alsa-devel@alsa-project.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Samuel Holland Subject: [RFC PATCH 27/34] ASoC: sun8i-codec: Add AIF mono/stereo controls Date: Mon, 17 Feb 2020 00:42:43 -0600 Message-Id: <20200217064250.15516-28-samuel@sholland.org> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200217064250.15516-1-samuel@sholland.org> References: <20200217064250.15516-1-samuel@sholland.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This allows changing the channel mapping for each digital input/output. This is useful when the DAI (or the device on the other end of the link) supports a different number of channels than are desired for routing, for example when using an I2S-format DAI link with a mono endpoint. Signed-off-by: Samuel Holland --- sound/soc/sunxi/sun8i-codec.c | 160 +++++++++++++++++++++++++++++++--- 1 file changed, 146 insertions(+), 14 deletions(-) diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index 71c4c1f47201..fdb9bf346cc2 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -56,9 +56,13 @@ #define SUN8I_AIF1_ADCDAT_CTRL 0x044 #define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_ENA 15 #define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_ENA 14 +#define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_SRC 10 +#define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_SRC 8 #define SUN8I_AIF1_DACDAT_CTRL 0x048 #define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA 15 #define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA 14 +#define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_SRC 10 +#define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_SRC 8 #define SUN8I_AIF1_MXR_SRC 0x04c #define SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF1DA0L 15 #define SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACL 14 @@ -71,9 +75,13 @@ #define SUN8I_AIF2_ADCDAT_CTRL 0x084 #define SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCL_ENA 15 #define SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCR_ENA 14 +#define SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCL_SRC 10 +#define SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCR_SRC 8 #define SUN8I_AIF2_DACDAT_CTRL 0x088 #define SUN8I_AIF2_DACDAT_CTRL_AIF2_DACL_ENA 15 #define SUN8I_AIF2_DACDAT_CTRL_AIF2_DACR_ENA 14 +#define SUN8I_AIF2_DACDAT_CTRL_AIF2_DACL_SRC 10 +#define SUN8I_AIF2_DACDAT_CTRL_AIF2_DACR_SRC 8 #define SUN8I_AIF2_MXR_SRC 0x08c #define SUN8I_AIF2_MXR_SRC_ADCL_MXR_SRC_AIF1DA0L 15 #define SUN8I_AIF2_MXR_SRC_ADCL_MXR_SRC_AIF1DA1L 14 @@ -511,6 +519,50 @@ static struct snd_soc_dai_driver sun8i_codec_dais[] = { }, }; +static const char *const sun8i_aif_stereo_mux_enum_names[] = { + "Stereo", "Reverse Stereo", "Sum Mono", "Mix Mono" +}; + +static SOC_ENUM_DOUBLE_DECL(sun8i_aif1_ad0_stereo_mux_enum, + SUN8I_AIF1_ADCDAT_CTRL, + SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_SRC, + SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_SRC, + sun8i_aif_stereo_mux_enum_names); + +static const struct snd_kcontrol_new sun8i_aif1_ad0_stereo_mux_control = + SOC_DAPM_ENUM("AIF1 AD0 Stereo Capture Route", + sun8i_aif1_ad0_stereo_mux_enum); + +static SOC_ENUM_DOUBLE_DECL(sun8i_aif1_da0_stereo_mux_enum, + SUN8I_AIF1_DACDAT_CTRL, + SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_SRC, + SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_SRC, + sun8i_aif_stereo_mux_enum_names); + +static const struct snd_kcontrol_new sun8i_aif1_da0_stereo_mux_control = + SOC_DAPM_ENUM("AIF1 DA0 Stereo Playback Route", + sun8i_aif1_da0_stereo_mux_enum); + +static SOC_ENUM_DOUBLE_DECL(sun8i_aif2_adc_stereo_mux_enum, + SUN8I_AIF2_ADCDAT_CTRL, + SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCL_SRC, + SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCR_SRC, + sun8i_aif_stereo_mux_enum_names); + +static const struct snd_kcontrol_new sun8i_aif2_adc_stereo_mux_control = + SOC_DAPM_ENUM("AIF2 ADC Stereo Capture Route", + sun8i_aif2_adc_stereo_mux_enum); + +static SOC_ENUM_DOUBLE_DECL(sun8i_aif2_dac_stereo_mux_enum, + SUN8I_AIF2_DACDAT_CTRL, + SUN8I_AIF2_DACDAT_CTRL_AIF2_DACL_SRC, + SUN8I_AIF2_DACDAT_CTRL_AIF2_DACR_SRC, + sun8i_aif_stereo_mux_enum_names); + +static const struct snd_kcontrol_new sun8i_aif2_dac_stereo_mux_control = + SOC_DAPM_ENUM("AIF2 DAC Stereo Playback Route", + sun8i_aif2_dac_stereo_mux_enum); + static const char *const sun8i_aif3_mux_enum_names[] = { "None", "AIF2 Left", "AIF2 Right" }; @@ -609,6 +661,17 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { SND_SOC_DAPM_AIF_OUT("AIF3 ADC", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0), + /* AIF "ADC" Mono/Stereo Muxes */ + SND_SOC_DAPM_MUX("AIF1 AD0 Left Stereo Mux", SND_SOC_NOPM, 0, 0, + &sun8i_aif1_ad0_stereo_mux_control), + SND_SOC_DAPM_MUX("AIF1 AD0 Right Stereo Mux", SND_SOC_NOPM, 0, 0, + &sun8i_aif1_ad0_stereo_mux_control), + + SND_SOC_DAPM_MUX("AIF2 ADC Left Stereo Mux", SND_SOC_NOPM, 0, 0, + &sun8i_aif2_adc_stereo_mux_control), + SND_SOC_DAPM_MUX("AIF2 ADC Right Stereo Mux", SND_SOC_NOPM, 0, 0, + &sun8i_aif2_adc_stereo_mux_control), + /* AIF "ADC" Muxes */ SND_SOC_DAPM_MUX("AIF3 ADC Capture Route", SND_SOC_NOPM, 0, 0, &sun8i_aif3_adc_mux_control), @@ -630,6 +693,17 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { SND_SOC_DAPM_MUX("AIF2 DAC Right Mux", SND_SOC_NOPM, 0, 0, &sun8i_aif2_dac_mux_control), + /* AIF "DAC" Mono/Stereo Muxes */ + SND_SOC_DAPM_MUX("AIF1 DA0 Left Stereo Mux", SND_SOC_NOPM, 0, 0, + &sun8i_aif1_da0_stereo_mux_control), + SND_SOC_DAPM_MUX("AIF1 DA0 Right Stereo Mux", SND_SOC_NOPM, 0, 0, + &sun8i_aif1_da0_stereo_mux_control), + + SND_SOC_DAPM_MUX("AIF2 DAC Left Stereo Mux", SND_SOC_NOPM, 0, 0, + &sun8i_aif2_dac_stereo_mux_control), + SND_SOC_DAPM_MUX("AIF2 DAC Right Stereo Mux", SND_SOC_NOPM, 0, 0, + &sun8i_aif2_dac_stereo_mux_control), + /* AIF "DAC" Inputs */ SND_SOC_DAPM_AIF_IN("AIF1 DA0 Left", "AIF1 Playback", 0, SUN8I_AIF1_DACDAT_CTRL, @@ -703,52 +777,110 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = { /* AIF "ADC" Output Routes */ - { "AIF1 AD0 Left", NULL, "AIF1 AD0 Left Mixer" }, - { "AIF1 AD0 Right", NULL, "AIF1 AD0 Right Mixer" }, + { "AIF1 AD0 Left", NULL, "AIF1 AD0 Left Stereo Mux" }, + { "AIF1 AD0 Right", NULL, "AIF1 AD0 Right Stereo Mux" }, { "AIF1 AD0 Left", NULL, "AIF1CLK" }, { "AIF1 AD0 Right", NULL, "AIF1CLK" }, - { "AIF2 ADC Left", NULL, "AIF2 ADC Left Mixer" }, - { "AIF2 ADC Right", NULL, "AIF2 ADC Right Mixer" }, + { "AIF2 ADC Left", NULL, "AIF2 ADC Left Stereo Mux" }, + { "AIF2 ADC Right", NULL, "AIF2 ADC Right Stereo Mux" }, { "AIF2 ADC Left", NULL, "AIF2CLK" }, { "AIF2 ADC Right", NULL, "AIF2CLK" }, { "AIF3 ADC", NULL, "AIF3 ADC Capture Route" }, + /* AIF "ADC" Mono/Stereo Mux Routes */ + { "AIF1 AD0 Left Stereo Mux", "Stereo", "AIF1 AD0 Left Mixer" }, + { "AIF1 AD0 Left Stereo Mux", "Reverse Stereo", "AIF1 AD0 Right Mixer" }, + { "AIF1 AD0 Left Stereo Mux", "Sum Mono", "AIF1 AD0 Left Mixer" }, + { "AIF1 AD0 Left Stereo Mux", "Sum Mono", "AIF1 AD0 Right Mixer" }, + { "AIF1 AD0 Left Stereo Mux", "Mix Mono", "AIF1 AD0 Left Mixer" }, + { "AIF1 AD0 Left Stereo Mux", "Mix Mono", "AIF1 AD0 Right Mixer" }, + + { "AIF1 AD0 Right Stereo Mux", "Stereo", "AIF1 AD0 Right Mixer" }, + { "AIF1 AD0 Right Stereo Mux", "Reverse Stereo", "AIF1 AD0 Left Mixer" }, + { "AIF1 AD0 Right Stereo Mux", "Sum Mono", "AIF1 AD0 Left Mixer" }, + { "AIF1 AD0 Right Stereo Mux", "Sum Mono", "AIF1 AD0 Right Mixer" }, + { "AIF1 AD0 Right Stereo Mux", "Mix Mono", "AIF1 AD0 Left Mixer" }, + { "AIF1 AD0 Right Stereo Mux", "Mix Mono", "AIF1 AD0 Right Mixer" }, + + { "AIF2 ADC Left Stereo Mux", "Stereo", "AIF2 ADC Left Mixer" }, + { "AIF2 ADC Left Stereo Mux", "Reverse Stereo", "AIF2 ADC Right Mixer" }, + { "AIF2 ADC Left Stereo Mux", "Sum Mono", "AIF2 ADC Left Mixer" }, + { "AIF2 ADC Left Stereo Mux", "Sum Mono", "AIF2 ADC Right Mixer" }, + { "AIF2 ADC Left Stereo Mux", "Mix Mono", "AIF2 ADC Left Mixer" }, + { "AIF2 ADC Left Stereo Mux", "Mix Mono", "AIF2 ADC Right Mixer" }, + + { "AIF2 ADC Right Stereo Mux", "Stereo", "AIF2 ADC Right Mixer" }, + { "AIF2 ADC Right Stereo Mux", "Reverse Stereo", "AIF2 ADC Left Mixer" }, + { "AIF2 ADC Right Stereo Mux", "Sum Mono", "AIF2 ADC Left Mixer" }, + { "AIF2 ADC Right Stereo Mux", "Sum Mono", "AIF2 ADC Right Mixer" }, + { "AIF2 ADC Right Stereo Mux", "Mix Mono", "AIF2 ADC Left Mixer" }, + { "AIF2 ADC Right Stereo Mux", "Mix Mono", "AIF2 ADC Right Mixer" }, + /* AIF "ADC" Mux Routes */ { "AIF3 ADC Capture Route", "AIF2 Left", "AIF2 ADC Left Mixer" }, { "AIF3 ADC Capture Route", "AIF2 Right", "AIF2 ADC Right Mixer" }, /* AIF "ADC" Mixer Routes */ - { "AIF1 AD0 Left Mixer", "AIF1 AD0 Mixer AIF1 DA0 Capture Switch", "AIF1 DA0 Left" }, + { "AIF1 AD0 Left Mixer", "AIF1 AD0 Mixer AIF1 DA0 Capture Switch", "AIF1 DA0 Left Stereo Mux" }, { "AIF1 AD0 Left Mixer", "AIF1 AD0 Mixer AIF2 DAC Capture Switch", "AIF2 DAC Left Mux" }, { "AIF1 AD0 Left Mixer", "AIF1 AD0 Mixer ADC Capture Switch", "ADC Left" }, { "AIF1 AD0 Left Mixer", "AIF1 AD0 Mixer AIF2 DAC Rev Capture Switch", "AIF2 DAC Right Mux" }, - { "AIF1 AD0 Right Mixer", "AIF1 AD0 Mixer AIF1 DA0 Capture Switch", "AIF1 DA0 Right" }, + { "AIF1 AD0 Right Mixer", "AIF1 AD0 Mixer AIF1 DA0 Capture Switch", "AIF1 DA0 Right Stereo Mux" }, { "AIF1 AD0 Right Mixer", "AIF1 AD0 Mixer AIF2 DAC Capture Switch", "AIF2 DAC Right Mux" }, { "AIF1 AD0 Right Mixer", "AIF1 AD0 Mixer ADC Capture Switch", "ADC Right" }, { "AIF1 AD0 Right Mixer", "AIF1 AD0 Mixer AIF2 DAC Rev Capture Switch", "AIF2 DAC Left Mux" }, - { "AIF2 ADC Left Mixer", "AIF2 ADC Mixer AIF1 DA0 Capture Switch", "AIF1 DA0 Left" }, + { "AIF2 ADC Left Mixer", "AIF2 ADC Mixer AIF1 DA0 Capture Switch", "AIF1 DA0 Left Stereo Mux" }, { "AIF2 ADC Left Mixer", "AIF2 ADC Mixer AIF2 DAC Rev Capture Switch", "AIF2 DAC Right Mux" }, { "AIF2 ADC Left Mixer", "AIF2 ADC Mixer ADC Capture Switch", "ADC Left" }, - { "AIF2 ADC Right Mixer", "AIF2 ADC Mixer AIF1 DA0 Capture Switch", "AIF1 DA0 Right" }, + { "AIF2 ADC Right Mixer", "AIF2 ADC Mixer AIF1 DA0 Capture Switch", "AIF1 DA0 Right Stereo Mux" }, { "AIF2 ADC Right Mixer", "AIF2 ADC Mixer AIF2 DAC Rev Capture Switch", "AIF2 DAC Left Mux" }, { "AIF2 ADC Right Mixer", "AIF2 ADC Mixer ADC Capture Switch", "ADC Right" }, /* AIF "DAC" Mux Routes */ - { "AIF2 DAC Left Mux", "None", "AIF2 DAC Left" }, + { "AIF2 DAC Left Mux", "None", "AIF2 DAC Left Stereo Mux" }, { "AIF2 DAC Left Mux", "AIF2 Left", "AIF3 DAC" }, - { "AIF2 DAC Left Mux", "AIF2 Right", "AIF2 DAC Left" }, + { "AIF2 DAC Left Mux", "AIF2 Right", "AIF2 DAC Left Stereo Mux" }, - { "AIF2 DAC Right Mux", "None", "AIF2 DAC Right" }, - { "AIF2 DAC Right Mux", "AIF2 Left", "AIF2 DAC Right" }, + { "AIF2 DAC Right Mux", "None", "AIF2 DAC Right Stereo Mux" }, + { "AIF2 DAC Right Mux", "AIF2 Left", "AIF2 DAC Right Stereo Mux" }, { "AIF2 DAC Right Mux", "AIF2 Right", "AIF3 DAC" }, + /* AIF "DAC" Mono/Stereo Mux Routes */ + { "AIF1 DA0 Left Stereo Mux", "Stereo", "AIF1 DA0 Left" }, + { "AIF1 DA0 Left Stereo Mux", "Reverse Stereo", "AIF1 DA0 Right" }, + { "AIF1 DA0 Left Stereo Mux", "Sum Mono", "AIF1 DA0 Left" }, + { "AIF1 DA0 Left Stereo Mux", "Sum Mono", "AIF1 DA0 Right" }, + { "AIF1 DA0 Left Stereo Mux", "Mix Mono", "AIF1 DA0 Left" }, + { "AIF1 DA0 Left Stereo Mux", "Mix Mono", "AIF1 DA0 Right" }, + + { "AIF1 DA0 Right Stereo Mux", "Stereo", "AIF1 DA0 Right" }, + { "AIF1 DA0 Right Stereo Mux", "Reverse Stereo", "AIF1 DA0 Left" }, + { "AIF1 DA0 Right Stereo Mux", "Sum Mono", "AIF1 DA0 Left" }, + { "AIF1 DA0 Right Stereo Mux", "Sum Mono", "AIF1 DA0 Right" }, + { "AIF1 DA0 Right Stereo Mux", "Mix Mono", "AIF1 DA0 Left" }, + { "AIF1 DA0 Right Stereo Mux", "Mix Mono", "AIF1 DA0 Right" }, + + { "AIF2 DAC Left Stereo Mux", "Stereo", "AIF2 DAC Left" }, + { "AIF2 DAC Left Stereo Mux", "Reverse Stereo", "AIF2 DAC Right" }, + { "AIF2 DAC Left Stereo Mux", "Sum Mono", "AIF2 DAC Left" }, + { "AIF2 DAC Left Stereo Mux", "Sum Mono", "AIF2 DAC Right" }, + { "AIF2 DAC Left Stereo Mux", "Mix Mono", "AIF2 DAC Left" }, + { "AIF2 DAC Left Stereo Mux", "Mix Mono", "AIF2 DAC Right" }, + + { "AIF2 DAC Right Stereo Mux", "Stereo", "AIF2 DAC Right" }, + { "AIF2 DAC Right Stereo Mux", "Reverse Stereo", "AIF2 DAC Left" }, + { "AIF2 DAC Right Stereo Mux", "Sum Mono", "AIF2 DAC Left" }, + { "AIF2 DAC Right Stereo Mux", "Sum Mono", "AIF2 DAC Right" }, + { "AIF2 DAC Right Stereo Mux", "Mix Mono", "AIF2 DAC Left" }, + { "AIF2 DAC Right Stereo Mux", "Mix Mono", "AIF2 DAC Right" }, + /* AIF "DAC" Input Routes */ { "AIF1 DA0 Left", NULL, "AIF1CLK" }, { "AIF1 DA0 Right", NULL, "AIF1CLK" }, @@ -764,11 +896,11 @@ static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = { { "DAC Right", NULL, "DAC" }, /* Main DAC Mixer Routes */ - { "DAC Left Mixer", "DAC Mixer AIF1 DA0 Playback Switch", "AIF1 DA0 Left" }, + { "DAC Left Mixer", "DAC Mixer AIF1 DA0 Playback Switch", "AIF1 DA0 Left Stereo Mux" }, { "DAC Left Mixer", "DAC Mixer AIF2 DAC Playback Switch", "AIF2 DAC Left Mux" }, { "DAC Left Mixer", "DAC Mixer ADC Playback Switch", "ADC Left" }, - { "DAC Right Mixer", "DAC Mixer AIF1 DA0 Playback Switch", "AIF1 DA0 Right" }, + { "DAC Right Mixer", "DAC Mixer AIF1 DA0 Playback Switch", "AIF1 DA0 Right Stereo Mux" }, { "DAC Right Mixer", "DAC Mixer AIF2 DAC Playback Switch", "AIF2 DAC Right Mux" }, { "DAC Right Mixer", "DAC Mixer ADC Playback Switch", "ADC Right" }, From patchwork Mon Feb 17 06:42:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 204717 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 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Received: from titanium.stl.sholland.net (70-135-148-151.lightspeed.stlsmo.sbcglobal.net [70.135.148.151]) by mail.messagingengine.com (Postfix) with ESMTPA id 5CBEE3280059; Mon, 17 Feb 2020 01:43:08 -0500 (EST) From: Samuel Holland To: Mark Brown , Liam Girdwood , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Vasily Khoruzhick , =?utf-8?q?Myl=C3=A8ne_Josseran?= =?utf-8?q?d?= , Jaroslav Kysela , Takashi Iwai Cc: alsa-devel@alsa-project.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Samuel Holland Subject: [RFC PATCH 29/34] ASoC: sun8i-codec: Add AIF, ADC, and DAC volume controls Date: Mon, 17 Feb 2020 00:42:45 -0600 Message-Id: <20200217064250.15516-30-samuel@sholland.org> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200217064250.15516-1-samuel@sholland.org> References: <20200217064250.15516-1-samuel@sholland.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This allows changing the volume of each digital input/output independently, and provides the only "master volume" for the DAC. (The ADC also has a gain control on the analog side.) While the hardware supports volumes up to +72dB, the controls here are limited to +24dB maximum, as anything more makes volume sliders difficult to use, and is extremely likely to cause clipping (this is simple digital gain). Signed-off-by: Samuel Holland --- sound/soc/sunxi/sun8i-codec.c | 56 +++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index 245145e36357..71cd7646a895 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -21,6 +21,7 @@ #include #include #include +#include #define SUN8I_SYSCLK_CTL 0x00c #define SUN8I_SYSCLK_CTL_AIF1CLK_ENA 11 @@ -73,6 +74,12 @@ #define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACR 10 #define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_ADCR 9 #define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACL 8 +#define SUN8I_AIF1_VOL_CTRL1 0x050 +#define SUN8I_AIF1_VOL_CTRL1_AD0L_VOL 8 +#define SUN8I_AIF1_VOL_CTRL1_AD0R_VOL 0 +#define SUN8I_AIF1_VOL_CTRL3 0x058 +#define SUN8I_AIF1_VOL_CTRL3_DA0L_VOL 8 +#define SUN8I_AIF1_VOL_CTRL3_DA0R_VOL 0 #define SUN8I_AIF2_ADCDAT_CTRL 0x084 #define SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCL_ENA 15 #define SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCR_ENA 14 @@ -93,6 +100,12 @@ #define SUN8I_AIF2_MXR_SRC_ADCR_MXR_SRC_AIF1DA1R 10 #define SUN8I_AIF2_MXR_SRC_ADCR_MXR_SRC_AIF2DACL 9 #define SUN8I_AIF2_MXR_SRC_ADCR_MXR_SRC_ADCR 8 +#define SUN8I_AIF2_VOL_CTRL1 0x090 +#define SUN8I_AIF2_VOL_CTRL1_ADCL_VOL 8 +#define SUN8I_AIF2_VOL_CTRL1_ADCR_VOL 0 +#define SUN8I_AIF2_VOL_CTRL2 0x098 +#define SUN8I_AIF2_VOL_CTRL2_DACL_VOL 8 +#define SUN8I_AIF2_VOL_CTRL2_DACR_VOL 0 #define SUN8I_AIF3_CLK_CTRL_AIF3_CLOCK_SRC_AIF1 (0x0 << 0) #define SUN8I_AIF3_CLK_CTRL_AIF3_CLOCK_SRC_AIF2 (0x1 << 0) #define SUN8I_AIF3_CLK_CTRL_AIF3_CLOCK_SRC_AIF1CLK (0x2 << 0) @@ -106,8 +119,14 @@ #define SUN8I_ADC_DIG_CTRL_ENAD 15 #define SUN8I_ADC_DIG_CTRL_ADOUT_DTS 2 #define SUN8I_ADC_DIG_CTRL_ADOUT_DLY 1 +#define SUN8I_ADC_VOL_CTRL 0x104 +#define SUN8I_ADC_VOL_CTRL_ADCL_VOL 8 +#define SUN8I_ADC_VOL_CTRL_ADCR_VOL 0 #define SUN8I_DAC_DIG_CTRL 0x120 #define SUN8I_DAC_DIG_CTRL_ENDA 15 +#define SUN8I_DAC_VOL_CTRL 0x124 +#define SUN8I_DAC_VOL_CTRL_DACL_VOL 8 +#define SUN8I_DAC_VOL_CTRL_DACR_VOL 0 #define SUN8I_DAC_MXR_SRC 0x130 #define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA0L 15 #define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA1L 14 @@ -521,6 +540,41 @@ static struct snd_soc_dai_driver sun8i_codec_dais[] = { }, }; +static const DECLARE_TLV_DB_SCALE(sun8i_codec_vol_scale, -12000, 75, 1); + +static const struct snd_kcontrol_new sun8i_codec_controls[] = { + SOC_DOUBLE_TLV("AIF1 AD0 Capture Volume", + SUN8I_AIF1_VOL_CTRL1, + SUN8I_AIF1_VOL_CTRL1_AD0L_VOL, + SUN8I_AIF1_VOL_CTRL1_AD0R_VOL, + 0xc0, 0, sun8i_codec_vol_scale), + SOC_DOUBLE_TLV("AIF1 DA0 Playback Volume", + SUN8I_AIF1_VOL_CTRL3, + SUN8I_AIF1_VOL_CTRL3_DA0L_VOL, + SUN8I_AIF1_VOL_CTRL3_DA0R_VOL, + 0xc0, 0, sun8i_codec_vol_scale), + SOC_DOUBLE_TLV("AIF2 ADC Capture Volume", + SUN8I_AIF2_VOL_CTRL1, + SUN8I_AIF2_VOL_CTRL1_ADCL_VOL, + SUN8I_AIF2_VOL_CTRL1_ADCR_VOL, + 0xc0, 0, sun8i_codec_vol_scale), + SOC_DOUBLE_TLV("AIF2 DAC Playback Volume", + SUN8I_AIF2_VOL_CTRL2, + SUN8I_AIF2_VOL_CTRL2_DACL_VOL, + SUN8I_AIF2_VOL_CTRL2_DACR_VOL, + 0xc0, 0, sun8i_codec_vol_scale), + SOC_DOUBLE_TLV("ADC Capture Volume", + SUN8I_ADC_VOL_CTRL, + SUN8I_ADC_VOL_CTRL_ADCL_VOL, + SUN8I_ADC_VOL_CTRL_ADCR_VOL, + 0xc0, 0, sun8i_codec_vol_scale), + SOC_DOUBLE_TLV("DAC Playback Volume", + SUN8I_DAC_VOL_CTRL, + SUN8I_DAC_VOL_CTRL_DACL_VOL, + SUN8I_DAC_VOL_CTRL_DACR_VOL, + 0xc0, 0, sun8i_codec_vol_scale), +}; + static const struct snd_kcontrol_new sun8i_aif1_loopback_switch = SOC_DAPM_SINGLE("AIF1 Loopback Switch", SUN8I_AIF1_DACDAT_CTRL, @@ -1017,6 +1071,8 @@ static int sun8i_codec_component_probe(struct snd_soc_component *component) } static const struct snd_soc_component_driver sun8i_soc_component = { + .controls = sun8i_codec_controls, + .num_controls = ARRAY_SIZE(sun8i_codec_controls), .dapm_widgets = sun8i_codec_dapm_widgets, .num_dapm_widgets = ARRAY_SIZE(sun8i_codec_dapm_widgets), .dapm_routes = sun8i_codec_dapm_routes, From patchwork Mon Feb 17 06:42:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 204716 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 775CBC35242 for ; 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Mon, 17 Feb 2020 01:43:09 -0500 (EST) From: Samuel Holland To: Mark Brown , Liam Girdwood , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Vasily Khoruzhick , =?utf-8?q?Myl=C3=A8ne_Josseran?= =?utf-8?q?d?= , Jaroslav Kysela , Takashi Iwai Cc: alsa-devel@alsa-project.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Samuel Holland Subject: [RFC PATCH 31/34] ARM: dts: sun8i-a33: Allow using multiple codec DAIs Date: Mon, 17 Feb 2020 00:42:47 -0600 Message-Id: <20200217064250.15516-32-samuel@sholland.org> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200217064250.15516-1-samuel@sholland.org> References: <20200217064250.15516-1-samuel@sholland.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The generic ASoC OF code supports a sound-dai-cells value of 0 or 1 with no impact to the driver. Bump sound-dai-cells to 1 to allow using the secondary DAIs in the codec. Signed-off-by: Samuel Holland --- arch/arm/boot/dts/sun8i-a33.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi index 40b903fa73da..a16c2ca11131 100644 --- a/arch/arm/boot/dts/sun8i-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a33.dtsi @@ -200,7 +200,7 @@ simple-audio-card,cpu { }; link_codec: simple-audio-card,codec { - sound-dai = <&codec>; + sound-dai = <&codec 0>; }; }; @@ -240,7 +240,7 @@ dai: dai@1c22c00 { }; codec: codec@1c22e00 { - #sound-dai-cells = <0>; + #sound-dai-cells = <1>; compatible = "allwinner,sun8i-a33-codec"; reg = <0x01c22e00 0x400>; interrupts = ; From patchwork Mon Feb 17 06:42:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 204718 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1185C35242 for ; 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Mon, 17 Feb 2020 01:43:11 -0500 (EST) From: Samuel Holland To: Mark Brown , Liam Girdwood , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Vasily Khoruzhick , =?utf-8?q?Myl=C3=A8ne_Josseran?= =?utf-8?q?d?= , Jaroslav Kysela , Takashi Iwai Cc: alsa-devel@alsa-project.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Samuel Holland Subject: [RFC PATCH 34/34] arm64: dts: allwinner: a64: Add pinmux for AIF2/AIF3 Date: Mon, 17 Feb 2020 00:42:50 -0600 Message-Id: <20200217064250.15516-35-samuel@sholland.org> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200217064250.15516-1-samuel@sholland.org> References: <20200217064250.15516-1-samuel@sholland.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Now that the codec driver supports AIF2 and AIF3, boards can use them in DAI links. Add the pinmux nodes. Signed-off-by: Samuel Holland --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 78353893c3b9..ee09a2dd6f69 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -605,6 +605,18 @@ pio: pinctrl@1c20800 { interrupt-controller; #interrupt-cells = <3>; + /omit-if-no-ref/ + aif2_pins: aif2-pins { + pins = "PB4", "PB5", "PB6", "PB7"; + function = "aif2"; + }; + + /omit-if-no-ref/ + aif3_pins: aif3-pins { + pins = "PG10", "PG11", "PG12", "PG13"; + function = "aif3"; + }; + csi_pins: csi-pins { pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", "PE7", "PE8", "PE9", "PE10", "PE11";