From patchwork Mon Feb 10 09:27:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 204996 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 699ACC352A4 for ; Mon, 10 Feb 2020 09:27:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 42CD221739 for ; Mon, 10 Feb 2020 09:27:27 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="VVAHUdjU" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726796AbgBJJ10 (ORCPT ); Mon, 10 Feb 2020 04:27:26 -0500 Received: from mail-lf1-f68.google.com ([209.85.167.68]:35318 "EHLO mail-lf1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726231AbgBJJ10 (ORCPT ); Mon, 10 Feb 2020 04:27:26 -0500 Received: by mail-lf1-f68.google.com with SMTP id z18so3672902lfe.2 for ; Mon, 10 Feb 2020 01:27:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RAQUA12B8fw61LvmbPVXA4Z+BIR0fWuOuilM7HoszrE=; b=VVAHUdjUGOnhNSSOTwO8j8iNwA8OvvwXz0HNaG7Z4v7KdXZEC9tZABemYa3hh1LtLx ND90NS9rpW4koGVStj6d/23RX8gMUD1meNrKBOer/0ZFwfbIbvv9r3MKojNgxzwIyqwD pOkd3gf1bnfDlNthtxURSoLOmMiy6aFkN6K2CwxxQTchydoy8vJoj1uV/c73a2YI0hei O6zwEchtmBMANO145rD1iSLknThL3aJxkTqDQ10icgrPfMGzsEL8U/bWaFBAwrbt+hab EcbqHPv9dTUE7Rcv/WP7yuzPusS31Vgswsd0CUowBqJ3ionGsxwZCEnt1O/VDGw1yWBQ dsCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RAQUA12B8fw61LvmbPVXA4Z+BIR0fWuOuilM7HoszrE=; b=nLFKgKVpnEvsBsJzXzPcew+YiHaIDAvOkCVEjVktxMkLeqDMVIBY9KTtg4dYzSCXbk ACt5Ft96HNExpRDSXm9jdXvN6S2w6ztetPKYbnqYmM3LyoLOX4jSHWK2+Ns/q26oR4GX 6t/4KsX4lL6KIJjhb3qhsrNHNu+LXDdXq66yKQgU8TOB6pcrPa6UOVMP79f0TJ7jEkPO MUpx1/4XAwGctRDjaWR8MNFs6HjX0q7lmgFKlMZVSFf0mMHG49mYnpcdNQvidzFfP2yu eVNBZ0ErdDarLhHuraHt3B2amQ4zDADcEviF4N36U8P0BUvs+rOThN4dz4oEk3G/cyqe wuOw== X-Gm-Message-State: APjAAAWKOo2kKk2VWVNwNVVUuybPm3o1mEZVeyyEZ9LiGU7xYo0QhQ1F WuMAEQB8a7lrdVXwLQgDHGF0dIESwss= X-Google-Smtp-Source: APXvYqxk9fdmZSurzHFLqkRZoeIFcEx44ID1iOZ53/3SGlp3Mue3CfnavApkhrRwMAMIk3wHf4b9Aw== X-Received: by 2002:a19:4f57:: with SMTP id a23mr257463lfk.145.1581326844610; Mon, 10 Feb 2020 01:27:24 -0800 (PST) Received: from genomnajs.ideon.se ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id d9sm5989882lja.73.2020.02.10.01.27.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Feb 2020 01:27:24 -0800 (PST) From: Linus Walleij To: devicetree@vger.kernel.org, Rob Herring , Sudeep Holla , Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, Linus Walleij Subject: [PATCH 1/7] ARM: dts: Versatile: Use syscon as node name for IB2 Date: Mon, 10 Feb 2020 10:27:07 +0100 Message-Id: <20200210092713.279105-2-linus.walleij@linaro.org> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200210092713.279105-1-linus.walleij@linaro.org> References: <20200210092713.279105-1-linus.walleij@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The IB2 syscon should not have any funny names, just call it syscon@ as per the convention so the schema will apply properly. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/versatile-ab-ib2.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/versatile-ab-ib2.dts b/arch/arm/boot/dts/versatile-ab-ib2.dts index 5890cb974f78..c577ff4bb4be 100644 --- a/arch/arm/boot/dts/versatile-ab-ib2.dts +++ b/arch/arm/boot/dts/versatile-ab-ib2.dts @@ -10,7 +10,7 @@ model = "ARM Versatile AB + IB2 board"; /* Special IB2 control register */ - ib2_syscon@27000000 { + syscon@27000000 { compatible = "arm,versatile-ib2-syscon", "syscon", "simple-mfd"; reg = <0x27000000 0x4>; From patchwork Mon Feb 10 09:27:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 204995 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4A9DC352A4 for ; Mon, 10 Feb 2020 09:27:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8EA96214DB for ; Mon, 10 Feb 2020 09:27:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="llFDLP5P" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726968AbgBJJ1d (ORCPT ); Mon, 10 Feb 2020 04:27:33 -0500 Received: from mail-lj1-f195.google.com ([209.85.208.195]:45095 "EHLO mail-lj1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726231AbgBJJ1d (ORCPT ); Mon, 10 Feb 2020 04:27:33 -0500 Received: by mail-lj1-f195.google.com with SMTP id f25so6254165ljg.12 for ; Mon, 10 Feb 2020 01:27:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kFLmtO0qC4EaVwrrh7e6Vy7NDWK/PC6a9SN2FOBadcg=; b=llFDLP5PXba6ytakgS+GATLFcR2XiettUpM9VuIsmtRN1KDHgz7FiuqPhhN55QFqPo ZNoaSbCkrNCtyK5rVmiGGoo0G9rtk+VeBzYPYCEAENyAvRUCtgH3h31Q9VLefU2VHhXx PTpYphtDHVz9LBNJi/zayDaz/TOJbRhAUHatni0uTEkM2we0Yn/rqLX7Xw1o8yvBCY0h kh7jwwSIKowH5nr3a5wR5QgjYQgHEt/H+eZtYVszOxERRW/rzvp5DDCu1Zfv8q4XgKYn VEcKWp+pU7cQGpSNimPaWyPq77bgsPSCc1We167QrVR7DxsHijMSub5zgj5zfwE2+kuI vjZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kFLmtO0qC4EaVwrrh7e6Vy7NDWK/PC6a9SN2FOBadcg=; b=jq8QvROcmiUyPv7i7jwCGm1R0Dl3sLCiMfU5Ivoxq9P8E7p6+7UXZrJdHmRHkhxDAQ f61ETeyEyqTpnp9x7y3S3V2HMhC1P115CdndGmseBUvLwWUqtpVUaH2uLk52HgGNfm94 MSiT5CLrNVvVapiLuAKfBFFznjnmNxzSsvsIFb3zCNHiuIgh0Z88o4qJLXxMf7le4zzV 3vDli6Y5y9QjGo1o1umCdZcCg7EjfBis4YHWTavgEufsf9z+HbMbNo8XDQc8DA4zLTs/ 9pYaNT6E4hwiVfOMY6rgaTNST1RFdn9PM4Mje609OdzG26C6U9zQWk6Ugwr3lKpNPUq8 fiLw== X-Gm-Message-State: APjAAAVR1FgmVuX9VG7cRMLM+D5U+u+2hF4vnbmjLEzandGzjG5Bgnm0 pQpvt0GeXaXg9fNxBl0NGW7JPiizx7U= X-Google-Smtp-Source: APXvYqyU75R1YbtpR14fLyyJdEq9Jb+9J2i6jY+AOWmEwmycd6oAX99ys9OUonkjlzRZ46ED4WhDKw== X-Received: by 2002:a2e:7812:: with SMTP id t18mr302226ljc.289.1581326849944; Mon, 10 Feb 2020 01:27:29 -0800 (PST) Received: from genomnajs.ideon.se ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id d9sm5989882lja.73.2020.02.10.01.27.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Feb 2020 01:27:29 -0800 (PST) From: Linus Walleij To: devicetree@vger.kernel.org, Rob Herring , Sudeep Holla , Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, Linus Walleij Subject: [PATCH 3/7] dt-bindings: arm: Add Integrator YAML schema Date: Mon, 10 Feb 2020 10:27:09 +0100 Message-Id: <20200210092713.279105-4-linus.walleij@linaro.org> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200210092713.279105-1-linus.walleij@linaro.org> References: <20200210092713.279105-1-linus.walleij@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This implements the top-level schema for the ARM Integrator platforms. Cc: Sudeep Holla Signed-off-by: Linus Walleij --- .../bindings/arm/arm,integrator.yaml | 85 +++++++++++++++++++ 1 file changed, 85 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/arm,integrator.yaml diff --git a/Documentation/devicetree/bindings/arm/arm,integrator.yaml b/Documentation/devicetree/bindings/arm/arm,integrator.yaml new file mode 100644 index 000000000000..39aa3e31f934 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,integrator.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,integrator.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Integrator Boards Device Tree Bindings + +maintainers: + - Linus Walleij + +description: |+ + These were the first ARM platforms officially supported by ARM Ltd. + They are ARMv4, ARMv5 and ARMv6-capable using different core tiles, + so the system is modular and can host a variety of CPU tiles called + "core tiles" and referred to in the device tree as "core modules". + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: ARM Integrator Application Platform, this board has a PCI + host and several PCI slots, as well as a number of slots for logical + expansion modules, it is referred to as an "ASIC Development + Motherboard" and is extended with custom FPGA and is intended for + rapid prototyping. See ARM DUI 0098B. This board can physically come + pre-packaged in a PC Tower form factor called Integrator/PP1 or a + special metal fixture called Integrator/PP2, see ARM DUI 0169A. + items: + - const: arm,integrator-ap + - description: ARM Integrator Compact Platform (HBI-0086), this board has + a compact form factor and mainly consists of the bare minimum + peripherals to make use of the core module. See ARM DUI 0159B. + items: + - const: arm,integrator-cp + - description: ARM Integrator Standard Development Board (SDB) Platform, + this board is a PCI-based board conforming to the Microsoft SDB + (HARP) specification. See ARM DUI 0099A. + items: + - const: arm,integrator-sp + + syscon: + description: All Integrator boards must provide a system controller as a + node in the root of the device tree. + type: object + properties: + compatible: + oneOf: + - items: + - const: arm,integrator-ap-syscon + - const: syscon + - items: + - const: arm,integrator-cp-syscon + - const: syscon + - items: + - const: arm,integrator-sp-syscon + - const: syscon + required: + - compatible + - reg + +patternProperties: + "^core-module@[0-9a-f]+$": + type: object + description: the root node in the Integrator platforms must contain + a core module child node. They are always at physical address + 0x10000000 in all the Integrator variants. + properties: + compatible: + contains: + const: arm,core-module-integrator + description: this node is the core module node, it can be compatible + with syscon and simple-bus as well + + required: + - compatible + - reg + +required: + - compatible + - syscon + - core-module@10000000 + +... From patchwork Mon Feb 10 09:27:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 204994 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E2C7AC352A4 for ; Mon, 10 Feb 2020 09:27:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B4A4F21739 for ; Mon, 10 Feb 2020 09:27:37 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="l7uQesG6" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727029AbgBJJ1h (ORCPT ); Mon, 10 Feb 2020 04:27:37 -0500 Received: from mail-lf1-f68.google.com ([209.85.167.68]:46217 "EHLO mail-lf1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726950AbgBJJ1h (ORCPT ); Mon, 10 Feb 2020 04:27:37 -0500 Received: by mail-lf1-f68.google.com with SMTP id z26so3622185lfg.13 for ; Mon, 10 Feb 2020 01:27:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BjsYE7IwesPMmpyoWDFFmaPCx/RAfe1hi/tzhTSvSdg=; b=l7uQesG6M28SqAQiPO0DR6OQH5YRu7JpfAa5/C+Bk02mHPFeXFB/4gQTiDc7CRf/JV Co6nbjws7QBm14CGymRUqxWdw3lFnD4GnIy0rupegH1pA9zo3ozlcc6oSlwom2RfeSXs PDbFDZLY2BQZsvo3+CgcCsUNd84ZLKER1LT6p23rK5XFr9xea/dkN/pa42w3dnOqD//Z QBBvlMkh2pl8te1B3vaW39HaeLxo2XaU+Uz92E/su7EoD9iPrWpSanYtAWVo5C5r1Q/f BCl9QezSH6nMBCoQKIt5mSQzG996FDRJY6ew2/88xak5v9jzgT/cDdsT/nRmfR4rupBz faTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BjsYE7IwesPMmpyoWDFFmaPCx/RAfe1hi/tzhTSvSdg=; b=Fp4sSloppeOI6MaPdK+P6JQWLXKyvTbUsYEbrf2mC+7iWfPe5MSwG8tbwIUTG/R8S+ azxg2uFUPJXcWHYGYbAeedHLzEoLwbOri1ixgxztmhXjKkf/zK5fBj7Wi//IDeG2039r XsCFmEsNsmgghSvuc4IlJRlRMbJLN/+QTOTPoMrkFiSmmnegznQA/wGa4vKoN0x9GN3Q gGhU/qARPjwsBX6L8waftngjN0CwDaUS7vz3ij6WLaT+/NVnd0gZNL5e6d2JyFg7wlV7 dzMSwRkg+aIpzW5d0Ia8CYEr9u5RaKEss9y4SMmuO1fFNSKzDE+yfNBGGDSwoIGICSyp k9Ow== X-Gm-Message-State: APjAAAVdMvmTGB5bp8tjqhzQLfE0fzFaZG0utnWv6jQutsQK56wGYi8L qE1bvMepkv9h/1jjKQ/yrmvQ9x7ZhnE= X-Google-Smtp-Source: APXvYqxZpnyyWZKheyuaFsm0KonLKcLW4pxi4HBtcPnzMpiGrdOf5lVgPrYFRID8AvhcdlKw6rauYw== X-Received: by 2002:a19:c3ce:: with SMTP id t197mr286769lff.174.1581326853563; Mon, 10 Feb 2020 01:27:33 -0800 (PST) Received: from genomnajs.ideon.se ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id d9sm5989882lja.73.2020.02.10.01.27.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Feb 2020 01:27:33 -0800 (PST) From: Linus Walleij To: devicetree@vger.kernel.org, Rob Herring , Sudeep Holla , Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, Linus Walleij Subject: [PATCH 5/7] dt-bindings: arm: Add RealView YAML schema Date: Mon, 10 Feb 2020 10:27:11 +0100 Message-Id: <20200210092713.279105-6-linus.walleij@linaro.org> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200210092713.279105-1-linus.walleij@linaro.org> References: <20200210092713.279105-1-linus.walleij@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This implements the top-level schema for the ARM RealView platforms. Cc: Sudeep Holla Signed-off-by: Linus Walleij --- .../devicetree/bindings/arm/arm,realview.yaml | 123 ++++++++++++++++++ 1 file changed, 123 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/arm,realview.yaml diff --git a/Documentation/devicetree/bindings/arm/arm,realview.yaml b/Documentation/devicetree/bindings/arm/arm,realview.yaml new file mode 100644 index 000000000000..d6e85d198afe --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,realview.yaml @@ -0,0 +1,123 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,realview.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM RealView Boards Device Tree Bindings + +maintainers: + - Linus Walleij + +description: |+ + The ARM RealView series of reference designs were built to explore the ARM + 11, Cortex A-8 and Cortex A-9 CPUs. This included new features compared to + the earlier CPUs such as TrustZone and multicore (MPCore). + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: ARM RealView Emulation Baseboard (HBI-0140) was created + as a generic platform to test different FPGA designs, and has + pluggable CPU modules, see ARM DUI 0303E. + items: + - const: arm,realview-eb + - description: ARM RealView Platform Baseboard for ARM1176JZF-S + (HBI-0147) was created as a development board to test ARM TrustZone, + CoreSight and Intelligent Energy Management (IEM) see ARM DUI 0425F. + items: + - const: arm,realview-pb1176 + - description: ARM RealView Platform Baseboard for ARM 11 MPCore + (HBI-0159, HBI-0175 and HBI-0176) was created to showcase + multiprocessing with ARM11 using MPCore using symmetric + multiprocessing (SMP). See ARM DUI 0351E. + items: + - const: arm,realview-pb11mp + - description: ARM RealView Platform Baseboard for Cortex-A8 (HBI-0178, + HBI-0176 and HBI-0175) was the first reference platform for the + Cortex CPU family, including a Cortex-A8 test chip. + items: + - const: arm,realview-pba8 + - description: ARM RealView Platform Baseboard Explore for Cortex-A9 + (HBI-0182 and HBI-0183) was the reference platform for the Cortex-A9 + CPU. + items: + - const: arm,realview-pbx + + soc: + description: All RealView boards must provide a soc node in the root of the + device tree, representing the System-on-Chip since these test chips are + rather complex. + type: object + properties: + compatible: + oneOf: + - items: + - const: arm,realview-eb-soc + - const: simple-bus + - items: + - const: arm,realview-pb1176-soc + - const: simple-bus + - items: + - const: arm,realview-pb11mp-soc + - const: simple-bus + - items: + - const: arm,realview-pba8-soc + - const: simple-bus + - items: + - const: arm,realview-pbx-soc + - const: simple-bus + + patternProperties: + "^.*syscon@[0-9a-f]+$": + type: object + description: All RealView boards must provide a syscon system controller + node inside the soc node. + properties: + compatible: + oneOf: + - items: + - const: arm,realview-eb11mp-revb-syscon + - const: arm,realview-eb-syscon + - const: syscon + - const: simple-mfd + - items: + - const: arm,realview-eb11mp-revc-syscon + - const: arm,realview-eb-syscon + - const: syscon + - const: simple-mfd + - items: + - const: arm,realview-eb-syscon + - const: syscon + - const: simple-mfd + - items: + - const: arm,realview-pb1176-syscon + - const: syscon + - const: simple-mfd + - items: + - const: arm,realview-pb11mp-syscon + - const: syscon + - const: simple-mfd + - items: + - const: arm,realview-pba8-syscon + - const: syscon + - const: simple-mfd + - items: + - const: arm,realview-pbx-syscon + - const: syscon + - const: simple-mfd + + required: + - compatible + - reg + + required: + - compatible + +required: + - compatible + - soc + +... From patchwork Mon Feb 10 09:27:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 204993 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 561CCC352A4 for ; Mon, 10 Feb 2020 09:27:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1A4DE21739 for ; Mon, 10 Feb 2020 09:27:41 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="bnDgasZx" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727079AbgBJJ1k (ORCPT ); Mon, 10 Feb 2020 04:27:40 -0500 Received: from mail-lf1-f65.google.com ([209.85.167.65]:40982 "EHLO mail-lf1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727022AbgBJJ1k (ORCPT ); Mon, 10 Feb 2020 04:27:40 -0500 Received: by mail-lf1-f65.google.com with SMTP id m30so3652805lfp.8 for ; Mon, 10 Feb 2020 01:27:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9DYrjgcgN/gmkzWo2n47z0tVLHfKB7efeWqTbGxlDWk=; b=bnDgasZxqiZxivCthCDYByZp5efUcOrfcdL2EaGagQugoimCM0C2Xqf+Px4BTuxq+t 2umLTfEl1+JXd5P2tcTsBwllWgCBcvkr51qYbNsLd1n2EAclY186kbSaZo5JbUjbKXVT 0fN5Zx3odGTVpgQEl0leOKCOek9SgIgdwh0tGg+27QAmbUmBhFa7o5JHMx8xEkVNtNeH t5KqXplL9Kqox3I3IfiVnR+7lowGmw4cKu+o/+RmQn0ZKRiJiQBOukUGXnNnLvD/YnHj CpaTgyqylQKeNw3FHfNkBpBRqMnuZa0MSbIczIcPlQLQSlJP4+ss0wDE3gJIQ5+pcPmm p5tg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9DYrjgcgN/gmkzWo2n47z0tVLHfKB7efeWqTbGxlDWk=; b=QN2uWD/edvHQPIj2jJ4B4S0LYzPFk3u6zm//WvN7tNJzM9paQNAa+r1ZAKOXeYxulI AWdb0QyTVELQ5+kHOSZrjrWcUsn9Fq0UK4Oya+63fMi1MHa2nKNYdTZhxSbI8cjucvGs 0Mp6DVv7gNjF3B2FzMs2ssryslF1tyrntCfFoprOuROOvWP/viH+PGeynIuO2sxtkV9s q/6RyqXhMXTNP3OB7Z8jPO3gNio5GQg6drIiUpYgK5la66KeI6yALVD+ESB+sAHPI8Bi PjLQ/YSzhZe7VVQx5Qe1WhdJw1y5wYuZF/afoVsrcP+RIKvOhGr2XwuJ1wqf2NwQgIvc lvfg== X-Gm-Message-State: APjAAAWrmTaGINnDRQDchiL0IpnW8bPw5iEgAp2cmgrmqcGkVMD9f/nH djwcQbKKpmlXiU0uDy61/OCs6Hr3p5A= X-Google-Smtp-Source: APXvYqzg7mdOX98+5omh8tNoKKlPahZs74HFUwLcb5mM0PPoHvgZr8PVn/JZSfjN1r1A7oWcIKuguQ== X-Received: by 2002:a19:ee1a:: with SMTP id g26mr255071lfb.147.1581326857010; Mon, 10 Feb 2020 01:27:37 -0800 (PST) Received: from genomnajs.ideon.se ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id d9sm5989882lja.73.2020.02.10.01.27.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Feb 2020 01:27:36 -0800 (PST) From: Linus Walleij To: devicetree@vger.kernel.org, Rob Herring , Sudeep Holla , Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, Linus Walleij Subject: [PATCH 7/7] dt-bindings: arm: Drop the non-YAML bindings Date: Mon, 10 Feb 2020 10:27:13 +0100 Message-Id: <20200210092713.279105-8-linus.walleij@linaro.org> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200210092713.279105-1-linus.walleij@linaro.org> References: <20200210092713.279105-1-linus.walleij@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org We created new bindings for the ARM Board using YAML so delete the old human-parseable-only bindings. Cc: Sudeep Holla Signed-off-by: Linus Walleij --- .../devicetree/bindings/arm/arm-boards | 237 ------------------ .../devicetree/bindings/arm/vexpress.txt | 229 ----------------- 2 files changed, 466 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/arm-boards delete mode 100644 Documentation/devicetree/bindings/arm/vexpress.txt diff --git a/Documentation/devicetree/bindings/arm/arm-boards b/Documentation/devicetree/bindings/arm/arm-boards deleted file mode 100644 index 96b1dad58253..000000000000 --- a/Documentation/devicetree/bindings/arm/arm-boards +++ /dev/null @@ -1,237 +0,0 @@ -ARM Integrator/AP (Application Platform) and Integrator/CP (Compact Platform) ------------------------------------------------------------------------------ -ARM's oldest Linux-supported platform with connectors for different core -tiles of ARMv4, ARMv5 and ARMv6 type. - -Required properties (in root node): - compatible = "arm,integrator-ap"; /* Application Platform */ - compatible = "arm,integrator-cp"; /* Compact Platform */ - -FPGA type interrupt controllers, see the versatile-fpga-irq binding doc. - -Required nodes: - -- core-module: the root node to the Integrator platforms must have - a core-module with regs and the compatible string - "arm,core-module-integrator" -- external-bus-interface: the root node to the Integrator platforms - must have an external bus interface with regs and the - compatible-string "arm,external-bus-interface" - - Required properties for the core module: - - regs: the location and size of the core module registers, one - range of 0x200 bytes. - -- syscon: the root node of the Integrator platforms must have a - system controller node pointing to the control registers, - with the compatible string - "arm,integrator-ap-syscon" - "arm,integrator-cp-syscon" - respectively. - - Required properties for the system controller: - - regs: the location and size of the system controller registers, - one range of 0x100 bytes. - - Required properties for the AP system controller: - - interrupts: the AP syscon node must include the logical module - interrupts, stated in order of module instance , - , ... for the CP system controller this - is not required not of any use. - -/dts-v1/; -/include/ "integrator.dtsi" - -/ { - model = "ARM Integrator/AP"; - compatible = "arm,integrator-ap"; - - core-module@10000000 { - compatible = "arm,core-module-integrator"; - reg = <0x10000000 0x200>; - }; - - ebi@12000000 { - compatible = "arm,external-bus-interface"; - reg = <0x12000000 0x100>; - }; - - syscon { - compatible = "arm,integrator-ap-syscon"; - reg = <0x11000000 0x100>; - interrupt-parent = <&pic>; - /* These are the logic module IRQs */ - interrupts = <9>, <10>, <11>, <12>; - }; -}; - - -ARM Versatile Application and Platform Baseboards -------------------------------------------------- -ARM's development hardware platform with connectors for customizable -core tiles. The hardware configuration of the Versatile boards is -highly customizable. - -Required properties (in root node): - compatible = "arm,versatile-ab"; /* Application baseboard */ - compatible = "arm,versatile-pb"; /* Platform baseboard */ - -Interrupt controllers: -- VIC required properties: - compatible = "arm,versatile-vic"; - interrupt-controller; - #interrupt-cells = <1>; - -- SIC required properties: - compatible = "arm,versatile-sic"; - interrupt-controller; - #interrupt-cells = <1>; - -Required nodes: - -- core-module: the root node to the Versatile platforms must have - a core-module with regs and the compatible strings - "arm,core-module-versatile", "syscon" - -Optional nodes: - -- arm,versatile-ib2-syscon : if the Versatile has an IB2 interface - board mounted, this has a separate system controller that is - defined in this node. - Required properties: - compatible = "arm,versatile-ib2-syscon", "syscon" - -ARM RealView Boards -------------------- -The RealView boards cover tailored evaluation boards that are used to explore -the ARM11 and Cortex A-8 and Cortex A-9 processors. - -Required properties (in root node): - /* RealView Emulation Baseboard */ - compatible = "arm,realview-eb"; - /* RealView Platform Baseboard for ARM1176JZF-S */ - compatible = "arm,realview-pb1176"; - /* RealView Platform Baseboard for ARM11 MPCore */ - compatible = "arm,realview-pb11mp"; - /* RealView Platform Baseboard for Cortex A-8 */ - compatible = "arm,realview-pba8"; - /* RealView Platform Baseboard Explore for Cortex A-9 */ - compatible = "arm,realview-pbx"; - -Required nodes: - -- soc: some node of the RealView platforms must be the SoC - node that contain the SoC-specific devices, with the compatible - string set to one of these tuples: - "arm,realview-eb-soc", "simple-bus" - "arm,realview-pb1176-soc", "simple-bus" - "arm,realview-pb11mp-soc", "simple-bus" - "arm,realview-pba8-soc", "simple-bus" - "arm,realview-pbx-soc", "simple-bus" - -- syscon: some subnode of the RealView SoC node must be a - system controller node pointing to the control registers, - with the compatible string set to one of these: - "arm,realview-eb11mp-revb-syscon", "arm,realview-eb-syscon", "syscon" - "arm,realview-eb11mp-revc-syscon", "arm,realview-eb-syscon", "syscon" - "arm,realview-eb-syscon", "syscon" - "arm,realview-pb1176-syscon", "syscon" - "arm,realview-pb11mp-syscon", "syscon" - "arm,realview-pba8-syscon", "syscon" - "arm,realview-pbx-syscon", "syscon" - - Required properties for the system controller: - - regs: the location and size of the system controller registers, - one range of 0x1000 bytes. - -Example: - -/dts-v1/; -#include - -/ { - model = "ARM RealView PB1176 with device tree"; - compatible = "arm,realview-pb1176"; - #address-cells = <1>; - #size-cells = <1>; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "arm,realview-pb1176-soc", "simple-bus"; - ranges; - - syscon: syscon@10000000 { - compatible = "arm,realview-syscon", "syscon"; - reg = <0x10000000 0x1000>; - }; - - }; -}; - -ARM Versatile Express Boards ------------------------------ -For details on the device tree bindings for ARM Versatile Express boards -please consult the vexpress.txt file in the same directory as this file. - -ARM Juno Boards ----------------- -The Juno boards are targeting development for AArch64 systems. The first -iteration, Juno r0, is a vehicle for evaluating big.LITTLE on AArch64, -with the second iteration, Juno r1, mainly aimed at development of PCIe -based systems. Juno r1 also has support for AXI masters placed on the TLX -connectors to join the coherency domain. - -Juno boards are described in a similar way to ARM Versatile Express boards, -with the motherboard part of the hardware being described in a separate file -to highlight the fact that is part of the support infrastructure for the SoC. -Juno device tree bindings also share the Versatile Express bindings as -described under the RS1 memory mapping. - -Required properties (in root node): - compatible = "arm,juno"; /* For Juno r0 board */ - compatible = "arm,juno-r1"; /* For Juno r1 board */ - compatible = "arm,juno-r2"; /* For Juno r2 board */ - -Required nodes: -The description for the board must include: - - a "psci" node describing the boot method used for the secondary CPUs. - A detailed description of the bindings used for "psci" nodes is present - in the psci.yaml file. - - a "cpus" node describing the available cores and their associated - "enable-method"s. For more details see cpus.yaml file. - -Example: - -/dts-v1/; -/ { - model = "ARM Juno development board (r0)"; - compatible = "arm,juno", "arm,vexpress"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - A57_0: cpu@0 { - compatible = "arm,cortex-a57"; - reg = <0x0 0x0>; - device_type = "cpu"; - enable-method = "psci"; - }; - - ..... - - A53_0: cpu@100 { - compatible = "arm,cortex-a53"; - reg = <0x0 0x100>; - device_type = "cpu"; - enable-method = "psci"; - }; - - ..... - }; - -}; diff --git a/Documentation/devicetree/bindings/arm/vexpress.txt b/Documentation/devicetree/bindings/arm/vexpress.txt deleted file mode 100644 index 39844cd0bcce..000000000000 --- a/Documentation/devicetree/bindings/arm/vexpress.txt +++ /dev/null @@ -1,229 +0,0 @@ -ARM Versatile Express boards family ------------------------------------ - -ARM's Versatile Express platform consists of a motherboard and one -or more daughterboards (tiles). The motherboard provides a set of -peripherals. Processor and RAM "live" on the tiles. - -The motherboard and each core tile should be described by a separate -Device Tree source file, with the tile's description including -the motherboard file using a /include/ directive. As the motherboard -can be initialized in one of two different configurations ("memory -maps"), care must be taken to include the correct one. - - -Root node ---------- - -Required properties in the root node: -- compatible value: - compatible = "arm,vexpress,", "arm,vexpress"; - where is the full tile model name (as used in the tile's - Technical Reference Manual), eg.: - - for Coretile Express A5x2 (V2P-CA5s): - compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress"; - - for Coretile Express A9x4 (V2P-CA9): - compatible = "arm,vexpress,v2p-ca9", "arm,vexpress"; - If a tile comes in several variants or can be used in more then one - configuration, the compatible value should be: - compatible = "arm,vexpress,,", \ - "arm,vexpress,", "arm,vexpress"; - eg: - - Coretile Express A15x2 (V2P-CA15) with Tech Chip 1: - compatible = "arm,vexpress,v2p-ca15,tc1", \ - "arm,vexpress,v2p-ca15", "arm,vexpress"; - - LogicTile Express 13MG (V2F-2XV6) running Cortex-A7 (3 cores) SMM: - compatible = "arm,vexpress,v2f-2xv6,ca7x3", \ - "arm,vexpress,v2f-2xv6", "arm,vexpress"; - -Optional properties in the root node: -- tile model name (use name from the tile's Technical Reference - Manual, eg. "V2P-CA5s") - model = ""; -- tile's HBI number (unique ARM's board model ID, visible on the - PCB's silkscreen) in hexadecimal transcription: - arm,hbi = <0xhbi> - eg: - - for Coretile Express A5x2 (V2P-CA5s) HBI-0191: - arm,hbi = <0x191>; - - Coretile Express A9x4 (V2P-CA9) HBI-0225: - arm,hbi = <0x225>; - - -CPU nodes ---------- - -Top-level standard "cpus" node is required. It must contain a node -with device_type = "cpu" property for every available core, eg.: - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a5"; - reg = <0>; - }; - }; - - -Configuration infrastructure ----------------------------- - -The platform has an elaborated configuration system, consisting of -microcontrollers residing on the mother- and daughterboards known -as Motherboard/Daughterboard Configuration Controller (MCC and DCC). -The controllers are responsible for the platform initialization -(reset generation, flash programming, FPGA bitfiles loading etc.) -but also control clock generators, voltage regulators, gather -environmental data like temperature, power consumption etc. Even -the video output switch (FPGA) is controlled that way. - -The controllers are not mapped into normal memory address space -and must be accessed through bridges - other devices capable -of generating transactions on the configuration bus. - -The nodes describing configuration controllers must define -the following properties: -- compatible value: - compatible = "arm,vexpress,config-bus"; -- bridge phandle: - arm,vexpress,config-bridge = ; -and children describing available functions. - - -Platform topology ------------------ - -As Versatile Express can be configured in number of physically -different setups, the device tree should describe platform topology. -Root node and main motherboard node must define the following -property, describing physical location of the children nodes: -- site number: - arm,vexpress,site = ; - where 0 means motherboard, 1 or 2 are daugtherboard sites, - 0xf means "master" site (site containing main CPU tile) -- when daughterboards are stacked on one site, their position - in the stack be be described with: - arm,vexpress,position = ; -- when describing tiles consisting more than one DCC, its number - can be described with: - arm,vexpress,dcc = ; - -Any of the numbers above defaults to zero if not defined in -the node or any of its parent. - - -Motherboard ------------ - -The motherboard description file provides a single "motherboard" node -using 2 address cells corresponding to the Static Memory Bus used -between the motherboard and the tile. The first cell defines the Chip -Select (CS) line number, the second cell address offset within the CS. -All interrupt lines between the motherboard and the tile are active -high and are described using single cell. - -Optional properties of the "motherboard" node: -- motherboard's memory map variant: - arm,v2m-memory-map = ""; - where name is one of: - - "rs1" - for RS1 map (i.a. peripherals on CS3); this map is also - referred to as "ARM Cortex-A Series memory map": - arm,v2m-memory-map = "rs1"; - When this property is missing, the motherboard is using the original - memory map (also known as the "Legacy memory map", primarily used - with the original CoreTile Express A9x4) with peripherals on CS7. - -Motherboard .dtsi files provide a set of labelled peripherals that -can be used to obtain required phandle in the tile's "aliases" node: -- UARTs, note that the numbers correspond to the physical connectors - on the motherboard's back panel: - v2m_serial0, v2m_serial1, v2m_serial2 and v2m_serial3 -- I2C controllers: - v2m_i2c_dvi and v2m_i2c_pcie -- SP804 timers: - v2m_timer01 and v2m_timer23 - -The tile description should define a "smb" node, describing the -Static Memory Bus between the tile and motherboard. It must define -the following properties: -- "simple-bus" compatible value (to ensure creation of the children) - compatible = "simple-bus"; -- mapping of the SMB CS/offset addresses into main address space: - #address-cells = <2>; - #size-cells = <1>; - ranges = <...>; -- interrupts mapping: - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 63>; - interrupt-map = <...>; - - -Example of a VE tile description (simplified) ---------------------------------------------- - -/dts-v1/; - -/ { - model = "V2P-CA5s"; - arm,hbi = <0x225>; - arm,vexpress,site = <0xf>; - compatible = "arm,vexpress-v2p-ca5s", "arm,vexpress"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - chosen { }; - - aliases { - serial0 = &v2m_serial0; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a5"; - reg = <0>; - }; - }; - - gic: interrupt-controller@2c001000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x2c001000 0x1000>, - <0x2c000100 0x100>; - }; - - dcc { - compatible = "arm,vexpress,config-bus"; - arm,vexpress,config-bridge = <&v2m_sysreg>; - - osc@0 { - compatible = "arm,vexpress-osc"; - }; - }; - - smb { - compatible = "simple-bus"; - - #address-cells = <2>; - #size-cells = <1>; - /* CS0 is visible at 0x08000000 */ - ranges = <0 0 0x08000000 0x04000000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 63>; - /* Active high IRQ 0 is connected to GIC's SPI0 */ - interrupt-map = <0 0 0 &gic 0 0 4>; - - /include/ "vexpress-v2m-rs1.dtsi" - }; -}; -