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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id i84sm6633646pfj.139.2017.08.29.13.48.02 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 Aug 2017 13:48:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 29 Aug 2017 13:47:52 -0700 Message-Id: <20170829204759.6853-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170829204759.6853-1-richard.henderson@linaro.org> References: <20170829204759.6853-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::233 Subject: [Qemu-devel] [PATCH 1/8] tcg/s390: Fully convert tcg_target_op_def X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: borntraeger@de.ibm.com, cohuck@redhat.com, agraf@suse.de, Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Use a switch instead of searching a table. Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.inc.c | 278 +++++++++++++++++++++++++--------------------- 1 file changed, 154 insertions(+), 124 deletions(-) -- 2.13.5 Reviewed-by: Philippe Mathieu-Daudé diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index 5d7083e90c..d34649eb13 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -2246,134 +2246,164 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, } } -static const TCGTargetOpDef s390_op_defs[] = { - { INDEX_op_exit_tb, { } }, - { INDEX_op_goto_tb, { } }, - { INDEX_op_br, { } }, - { INDEX_op_goto_ptr, { "r" } }, - - { INDEX_op_ld8u_i32, { "r", "r" } }, - { INDEX_op_ld8s_i32, { "r", "r" } }, - { INDEX_op_ld16u_i32, { "r", "r" } }, - { INDEX_op_ld16s_i32, { "r", "r" } }, - { INDEX_op_ld_i32, { "r", "r" } }, - { INDEX_op_st8_i32, { "r", "r" } }, - { INDEX_op_st16_i32, { "r", "r" } }, - { INDEX_op_st_i32, { "r", "r" } }, - - { INDEX_op_add_i32, { "r", "r", "ri" } }, - { INDEX_op_sub_i32, { "r", "0", "ri" } }, - { INDEX_op_mul_i32, { "r", "0", "rK" } }, - - { INDEX_op_div2_i32, { "b", "a", "0", "1", "r" } }, - { INDEX_op_divu2_i32, { "b", "a", "0", "1", "r" } }, - - { INDEX_op_and_i32, { "r", "0", "ri" } }, - { INDEX_op_or_i32, { "r", "0", "rO" } }, - { INDEX_op_xor_i32, { "r", "0", "rX" } }, - - { INDEX_op_neg_i32, { "r", "r" } }, - - { INDEX_op_shl_i32, { "r", "0", "ri" } }, - { INDEX_op_shr_i32, { "r", "0", "ri" } }, - { INDEX_op_sar_i32, { "r", "0", "ri" } }, - - { INDEX_op_rotl_i32, { "r", "r", "ri" } }, - { INDEX_op_rotr_i32, { "r", "r", "ri" } }, - - { INDEX_op_ext8s_i32, { "r", "r" } }, - { INDEX_op_ext8u_i32, { "r", "r" } }, - { INDEX_op_ext16s_i32, { "r", "r" } }, - { INDEX_op_ext16u_i32, { "r", "r" } }, - - { INDEX_op_bswap16_i32, { "r", "r" } }, - { INDEX_op_bswap32_i32, { "r", "r" } }, - - { INDEX_op_add2_i32, { "r", "r", "0", "1", "rA", "r" } }, - { INDEX_op_sub2_i32, { "r", "r", "0", "1", "rA", "r" } }, - - { INDEX_op_brcond_i32, { "r", "rC" } }, - { INDEX_op_setcond_i32, { "r", "r", "rC" } }, - { INDEX_op_movcond_i32, { "r", "r", "rC", "r", "0" } }, - { INDEX_op_deposit_i32, { "r", "rZ", "r" } }, - { INDEX_op_extract_i32, { "r", "r" } }, - - { INDEX_op_qemu_ld_i32, { "r", "L" } }, - { INDEX_op_qemu_ld_i64, { "r", "L" } }, - { INDEX_op_qemu_st_i32, { "L", "L" } }, - { INDEX_op_qemu_st_i64, { "L", "L" } }, - - { INDEX_op_ld8u_i64, { "r", "r" } }, - { INDEX_op_ld8s_i64, { "r", "r" } }, - { INDEX_op_ld16u_i64, { "r", "r" } }, - { INDEX_op_ld16s_i64, { "r", "r" } }, - { INDEX_op_ld32u_i64, { "r", "r" } }, - { INDEX_op_ld32s_i64, { "r", "r" } }, - { INDEX_op_ld_i64, { "r", "r" } }, - - { INDEX_op_st8_i64, { "r", "r" } }, - { INDEX_op_st16_i64, { "r", "r" } }, - { INDEX_op_st32_i64, { "r", "r" } }, - { INDEX_op_st_i64, { "r", "r" } }, - - { INDEX_op_add_i64, { "r", "r", "ri" } }, - { INDEX_op_sub_i64, { "r", "0", "ri" } }, - { INDEX_op_mul_i64, { "r", "0", "rK" } }, - - { INDEX_op_div2_i64, { "b", "a", "0", "1", "r" } }, - { INDEX_op_divu2_i64, { "b", "a", "0", "1", "r" } }, - { INDEX_op_mulu2_i64, { "b", "a", "0", "r" } }, - - { INDEX_op_and_i64, { "r", "0", "ri" } }, - { INDEX_op_or_i64, { "r", "0", "rO" } }, - { INDEX_op_xor_i64, { "r", "0", "rX" } }, - - { INDEX_op_neg_i64, { "r", "r" } }, - - { INDEX_op_shl_i64, { "r", "r", "ri" } }, - { INDEX_op_shr_i64, { "r", "r", "ri" } }, - { INDEX_op_sar_i64, { "r", "r", "ri" } }, - - { INDEX_op_rotl_i64, { "r", "r", "ri" } }, - { INDEX_op_rotr_i64, { "r", "r", "ri" } }, - - { INDEX_op_ext8s_i64, { "r", "r" } }, - { INDEX_op_ext8u_i64, { "r", "r" } }, - { INDEX_op_ext16s_i64, { "r", "r" } }, - { INDEX_op_ext16u_i64, { "r", "r" } }, - { INDEX_op_ext32s_i64, { "r", "r" } }, - { INDEX_op_ext32u_i64, { "r", "r" } }, - - { INDEX_op_ext_i32_i64, { "r", "r" } }, - { INDEX_op_extu_i32_i64, { "r", "r" } }, - - { INDEX_op_bswap16_i64, { "r", "r" } }, - { INDEX_op_bswap32_i64, { "r", "r" } }, - { INDEX_op_bswap64_i64, { "r", "r" } }, - - { INDEX_op_clz_i64, { "r", "r", "ri" } }, - - { INDEX_op_add2_i64, { "r", "r", "0", "1", "rA", "r" } }, - { INDEX_op_sub2_i64, { "r", "r", "0", "1", "rA", "r" } }, - - { INDEX_op_brcond_i64, { "r", "rC" } }, - { INDEX_op_setcond_i64, { "r", "r", "rC" } }, - { INDEX_op_movcond_i64, { "r", "r", "rC", "r", "0" } }, - { INDEX_op_deposit_i64, { "r", "0", "r" } }, - { INDEX_op_extract_i64, { "r", "r" } }, - - { INDEX_op_mb, { } }, - { -1 }, -}; - static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) { - int i, n = ARRAY_SIZE(s390_op_defs); + static const TCGTargetOpDef r = { .args_ct_str = { "r" } }; + static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } }; + static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } }; + static const TCGTargetOpDef L_L = { .args_ct_str = { "L", "L" } }; + static const TCGTargetOpDef r_rC = { .args_ct_str = { "r", "rC" } }; + static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } }; + static const TCGTargetOpDef r_0_ri = { .args_ct_str = { "r", "0", "ri" } }; + static const TCGTargetOpDef r_0_rK = { .args_ct_str = { "r", "0", "rK" } }; + static const TCGTargetOpDef r_0_rO = { .args_ct_str = { "r", "0", "rO" } }; + static const TCGTargetOpDef r_0_rX = { .args_ct_str = { "r", "0", "rX" } }; + + switch (op) { + case INDEX_op_goto_ptr: + return &r; + + case INDEX_op_ld8u_i32: + case INDEX_op_ld8u_i64: + case INDEX_op_ld8s_i32: + case INDEX_op_ld8s_i64: + case INDEX_op_ld16u_i32: + case INDEX_op_ld16u_i64: + case INDEX_op_ld16s_i32: + case INDEX_op_ld16s_i64: + case INDEX_op_ld_i32: + case INDEX_op_ld32u_i64: + case INDEX_op_ld32s_i64: + case INDEX_op_ld_i64: + case INDEX_op_st8_i32: + case INDEX_op_st8_i64: + case INDEX_op_st16_i32: + case INDEX_op_st16_i64: + case INDEX_op_st_i32: + case INDEX_op_st32_i64: + case INDEX_op_st_i64: + return &r_r; + + case INDEX_op_add_i32: + case INDEX_op_add_i64: + return &r_r_ri; + case INDEX_op_sub_i32: + case INDEX_op_sub_i64: + return &r_0_ri; + case INDEX_op_mul_i32: + case INDEX_op_mul_i64: + return &r_0_rK; + case INDEX_op_or_i32: + case INDEX_op_or_i64: + return &r_0_rO; + case INDEX_op_xor_i32: + case INDEX_op_xor_i64: + return &r_0_rX; + case INDEX_op_and_i32: + case INDEX_op_and_i64: + return &r_0_ri; + + case INDEX_op_shl_i32: + case INDEX_op_shr_i32: + case INDEX_op_sar_i32: + return &r_0_ri; + + case INDEX_op_shl_i64: + case INDEX_op_shr_i64: + case INDEX_op_sar_i64: + return &r_r_ri; + + case INDEX_op_rotl_i32: + case INDEX_op_rotl_i64: + case INDEX_op_rotr_i32: + case INDEX_op_rotr_i64: + return &r_r_ri; + + case INDEX_op_brcond_i32: + case INDEX_op_brcond_i64: + return &r_rC; + + case INDEX_op_bswap16_i32: + case INDEX_op_bswap16_i64: + case INDEX_op_bswap32_i32: + case INDEX_op_bswap32_i64: + case INDEX_op_bswap64_i64: + case INDEX_op_neg_i32: + case INDEX_op_neg_i64: + case INDEX_op_ext8s_i32: + case INDEX_op_ext8s_i64: + case INDEX_op_ext8u_i32: + case INDEX_op_ext8u_i64: + case INDEX_op_ext16s_i32: + case INDEX_op_ext16s_i64: + case INDEX_op_ext16u_i32: + case INDEX_op_ext16u_i64: + case INDEX_op_ext32s_i64: + case INDEX_op_ext32u_i64: + case INDEX_op_ext_i32_i64: + case INDEX_op_extu_i32_i64: + case INDEX_op_extract_i32: + case INDEX_op_extract_i64: + return &r_r; + + case INDEX_op_clz_i64: + return &r_r_ri; + + case INDEX_op_qemu_ld_i32: + case INDEX_op_qemu_ld_i64: + return &r_L; + case INDEX_op_qemu_st_i64: + case INDEX_op_qemu_st_i32: + return &L_L; - for (i = 0; i < n; ++i) { - if (s390_op_defs[i].op == op) { - return &s390_op_defs[i]; + case INDEX_op_deposit_i32: + case INDEX_op_deposit_i64: + { + static const TCGTargetOpDef dep + = { .args_ct_str = { "r", "rZ", "r" } }; + return &dep; } + case INDEX_op_setcond_i32: + case INDEX_op_setcond_i64: + { + static const TCGTargetOpDef setc + = { .args_ct_str = { "r", "r", "rC" } }; + return &setc; + } + case INDEX_op_movcond_i32: + case INDEX_op_movcond_i64: + { + static const TCGTargetOpDef movc + = { .args_ct_str = { "r", "r", "rC", "r", "0" } }; + return &movc; + } + case INDEX_op_div2_i32: + case INDEX_op_div2_i64: + case INDEX_op_divu2_i32: + case INDEX_op_divu2_i64: + { + static const TCGTargetOpDef div2 + = { .args_ct_str = { "b", "a", "0", "1", "r" } }; + return &div2; + } + case INDEX_op_mulu2_i64: + { + static const TCGTargetOpDef mul2 + = { .args_ct_str = { "b", "a", "0", "r" } }; + return &mul2; + } + case INDEX_op_add2_i32: + case INDEX_op_add2_i64: + case INDEX_op_sub2_i32: + case INDEX_op_sub2_i64: + { + static const TCGTargetOpDef arith2 + = { .args_ct_str = { "r", "r", "0", "1", "rA", "r" } }; + return &arith2; + } + + default: + break; } return NULL; } From patchwork Tue Aug 29 20:47:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 111251 Delivered-To: patch@linaro.org Received: by 10.140.95.112 with SMTP id h103csp1924941qge; Tue, 29 Aug 2017 13:48:32 -0700 (PDT) X-Received: by 10.200.36.48 with SMTP id c45mr7260385qtc.263.1504039712676; Tue, 29 Aug 2017 13:48:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504039712; cv=none; d=google.com; s=arc-20160816; b=T1Q5EkiYPTKpFCzuCJ4rpxZw9kikFcUbxe6glR9RtC0VJkQ4D74re1HWbFMDED2DwN eFT7tpTHkYeC4MEJCuhM3nJaps4hKfzLxb+GotauHsP36/6t9NM1O4MBedGaJl6a22sm SyTylPJlVsOEeNWOKhiYfMNycycA/wUV2a4lIrOfdJYYSPx7HwTEbB3lZVqCqc6gW661 Wo1yDchOu6Xbv0XRaFkpXJaidJFVr1w6Nq+bTeY0Wf7xXuxH3QWYkFbW8cQYmYQ+AZ+0 +onvxvOcMnYHE6JxHnx6xI7eqTjlXfRkxLwgJRn1ZKH9Q+4P9pYx4iAX5l3O8ZOmZo4M JwiQ== ARC-Message-Signature: i=1; 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id i84sm6633646pfj.139.2017.08.29.13.48.03 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 Aug 2017 13:48:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 29 Aug 2017 13:47:53 -0700 Message-Id: <20170829204759.6853-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170829204759.6853-1-richard.henderson@linaro.org> References: <20170829204759.6853-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22e Subject: [Qemu-devel] [PATCH 2/8] tcg/s390: Merge cmpi facilities check to tcg_target_op_def X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: borntraeger@de.ibm.com, cohuck@redhat.com, agraf@suse.de, Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.inc.c | 68 +++++++++++++++++++++-------------------------- 1 file changed, 30 insertions(+), 38 deletions(-) -- 2.13.5 diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index d34649eb13..e075b4844a 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -41,7 +41,7 @@ #define TCG_CT_CONST_MULI 0x100 #define TCG_CT_CONST_ORI 0x200 #define TCG_CT_CONST_XORI 0x400 -#define TCG_CT_CONST_CMPI 0x800 +#define TCG_CT_CONST_U31 0x800 #define TCG_CT_CONST_ADLI 0x1000 #define TCG_CT_CONST_ZERO 0x2000 @@ -398,7 +398,18 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, ct->ct |= TCG_CT_CONST_XORI; break; case 'C': - ct->ct |= TCG_CT_CONST_CMPI; + /* ??? We have no insight here into whether the comparison is + signed or unsigned. The COMPARE IMMEDIATE insn uses a 32-bit + signed immediate, and the COMPARE LOGICAL IMMEDIATE insn uses + a 32-bit unsigned immediate. If we were to use the (semi) + obvious "val == (int32_t)val" we would be enabling unsigned + comparisons vs very large numbers. The only solution is to + take the intersection of the ranges. */ + /* ??? Another possible solution is to simply lie and allow all + constants here and force the out-of-range values into a temp + register in tgen_cmp when we have knowledge of the actual + comparison code in use. */ + ct->ct |= TCG_CT_CONST_U31; break; case 'Z': ct->ct |= TCG_CT_CONST_ZERO; @@ -463,35 +474,6 @@ static int tcg_match_xori(TCGType type, tcg_target_long val) return 1; } -/* Imediates to be used with comparisons. */ - -static int tcg_match_cmpi(TCGType type, tcg_target_long val) -{ - if (s390_facilities & FACILITY_EXT_IMM) { - /* The COMPARE IMMEDIATE instruction is available. */ - if (type == TCG_TYPE_I32) { - /* We have a 32-bit immediate and can compare against anything. */ - return 1; - } else { - /* ??? We have no insight here into whether the comparison is - signed or unsigned. The COMPARE IMMEDIATE insn uses a 32-bit - signed immediate, and the COMPARE LOGICAL IMMEDIATE insn uses - a 32-bit unsigned immediate. If we were to use the (semi) - obvious "val == (int32_t)val" we would be enabling unsigned - comparisons vs very large numbers. The only solution is to - take the intersection of the ranges. */ - /* ??? Another possible solution is to simply lie and allow all - constants here and force the out-of-range values into a temp - register in tgen_cmp when we have knowledge of the actual - comparison code in use. */ - return val >= 0 && val <= 0x7fffffff; - } - } else { - /* Only the LOAD AND TEST instruction is available. */ - return val == 0; - } -} - /* Immediates to be used with add2/sub2. */ static int tcg_match_add2i(TCGType type, tcg_target_long val) @@ -537,8 +519,8 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type, return tcg_match_ori(type, val); } else if (ct & TCG_CT_CONST_XORI) { return tcg_match_xori(type, val); - } else if (ct & TCG_CT_CONST_CMPI) { - return tcg_match_cmpi(type, val); + } else if (ct & TCG_CT_CONST_U31) { + return val >= 0 && val <= 0x7fffffff; } else if (ct & TCG_CT_CONST_ZERO) { return val == 0; } @@ -2252,7 +2234,9 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } }; static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } }; static const TCGTargetOpDef L_L = { .args_ct_str = { "L", "L" } }; + static const TCGTargetOpDef r_ri = { .args_ct_str = { "r", "ri" } }; static const TCGTargetOpDef r_rC = { .args_ct_str = { "r", "rC" } }; + static const TCGTargetOpDef r_rZ = { .args_ct_str = { "r", "rZ" } }; static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } }; static const TCGTargetOpDef r_0_ri = { .args_ct_str = { "r", "0", "ri" } }; static const TCGTargetOpDef r_0_rK = { .args_ct_str = { "r", "0", "rK" } }; @@ -2320,8 +2304,10 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) return &r_r_ri; case INDEX_op_brcond_i32: + /* Without EXT_IMM, only the LOAD AND TEST insn is available. */ + return (s390_facilities & FACILITY_EXT_IMM ? &r_ri : &r_rZ); case INDEX_op_brcond_i64: - return &r_rC; + return (s390_facilities & FACILITY_EXT_IMM ? &r_rC : &r_rZ); case INDEX_op_bswap16_i32: case INDEX_op_bswap16_i64: @@ -2366,16 +2352,22 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_setcond_i32: case INDEX_op_setcond_i64: { - static const TCGTargetOpDef setc + /* Without EXT_IMM, only the LOAD AND TEST insn is available. */ + static const TCGTargetOpDef setc_z + = { .args_ct_str = { "r", "r", "rZ" } }; + static const TCGTargetOpDef setc_c = { .args_ct_str = { "r", "r", "rC" } }; - return &setc; + return (s390_facilities & FACILITY_EXT_IMM ? &setc_c : &setc_z); } case INDEX_op_movcond_i32: case INDEX_op_movcond_i64: { - static const TCGTargetOpDef movc + /* Without EXT_IMM, only the LOAD AND TEST insn is available. */ + static const TCGTargetOpDef movc_z + = { .args_ct_str = { "r", "r", "rZ", "r", "0" } }; + static const TCGTargetOpDef movc_c = { .args_ct_str = { "r", "r", "rC", "r", "0" } }; - return &movc; + return (s390_facilities & FACILITY_EXT_IMM ? &movc_c : &movc_z); } case INDEX_op_div2_i32: case INDEX_op_div2_i64: From patchwork Tue Aug 29 20:47:54 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 111255 Delivered-To: patch@linaro.org Received: by 10.140.95.112 with SMTP id h103csp1929271qge; Tue, 29 Aug 2017 13:52:50 -0700 (PDT) X-Received: by 10.55.204.137 with SMTP id n9mr7388495qkl.125.1504039970134; Tue, 29 Aug 2017 13:52:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504039970; cv=none; d=google.com; s=arc-20160816; b=zcztZ8Xp/03TE2U543E3ARlv117BM7SbttJ3bJjl2TsrjzLb+f2bUEAuaCkPG7e4p0 lUM8kvUH614J0n/KOKBIW2+T57iahZqFDAicBG4hHLQv/JvS0m6nRmOa3t/9iWoa1XZs Im/eQLK1aunzkBMU3MB61EOSK1EDsVPLEzBQNUdCxgEy8YHiR+d0cA6SRXvRO/y+nEfQ 084DOSIGkYAIDPx5yWiiKzsXBti20e8nbZuxhradc19UAbY+sWZk75/ld5yTdy6foMj/ b05+fCUr3c6qKUKcM06ODsbXw8YaX1Jg3GRqXH4TXmxHWAY3qIsp7a+ydQQtyPNdSVq7 kapA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=0RJY26L+wluBLiCwy06P1bcCFRjSUiVl+17C88pqpyA=; b=jyeOwNvcjl9ismnnooYBalezz7b2lbGKl2NUFTx9x3Lr7R/4ldDMDuhwJXmrhmOSI/ 4bVUcz8CzeFEdTalxny2VaxEyY20TN/9UmCUHvWmNhZL0A3Qqum7+YzLBXERBonIhLXB 4EoMm6+qGNE66FG3D1Xx1IPLKNYt/G2ArbYln7x7I2EGUJ9gJYkFPiC/95+QvhjgwDpk umOuwVu8sCc0cMucQjKjFIs1m/2kop2WQfdzHXk/CvAv2kr47f1o1RoInb80yBHrJIeU mh/WNV7US0rSCUJ/yyRL/jvM1DyWMAncQ1OsMK58FkMSA53whQkEDzgD6VZY8thxCH+7 SDZg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=a/x906Qp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id i84sm6633646pfj.139.2017.08.29.13.48.05 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 Aug 2017 13:48:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 29 Aug 2017 13:47:54 -0700 Message-Id: <20170829204759.6853-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170829204759.6853-1-richard.henderson@linaro.org> References: <20170829204759.6853-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::231 Subject: [Qemu-devel] [PATCH 3/8] tcg/s390: Merge muli facilities check to tcg_target_op_def X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: borntraeger@de.ibm.com, cohuck@redhat.com, agraf@suse.de, Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.inc.c | 45 +++++++++++++++++++++++++-------------------- 1 file changed, 25 insertions(+), 20 deletions(-) -- 2.13.5 diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index e075b4844a..ff3f644f8e 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -38,12 +38,13 @@ a 32-bit displacement here Just In Case. */ #define USE_LONG_BRANCHES 0 -#define TCG_CT_CONST_MULI 0x100 -#define TCG_CT_CONST_ORI 0x200 -#define TCG_CT_CONST_XORI 0x400 -#define TCG_CT_CONST_U31 0x800 -#define TCG_CT_CONST_ADLI 0x1000 -#define TCG_CT_CONST_ZERO 0x2000 +#define TCG_CT_CONST_S16 0x100 +#define TCG_CT_CONST_S32 0x200 +#define TCG_CT_CONST_ORI 0x400 +#define TCG_CT_CONST_XORI 0x800 +#define TCG_CT_CONST_U31 0x1000 +#define TCG_CT_CONST_ADLI 0x2000 +#define TCG_CT_CONST_ZERO 0x4000 /* Several places within the instruction set 0 means "no register" rather than TCG_REG_R0. */ @@ -388,8 +389,11 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, case 'A': ct->ct |= TCG_CT_CONST_ADLI; break; - case 'K': - ct->ct |= TCG_CT_CONST_MULI; + case 'I': + ct->ct |= TCG_CT_CONST_S16; + break; + case 'J': + ct->ct |= TCG_CT_CONST_S32; break; case 'O': ct->ct |= TCG_CT_CONST_ORI; @@ -503,16 +507,10 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type, } /* The following are mutually exclusive. */ - if (ct & TCG_CT_CONST_MULI) { - /* Immediates that may be used with multiply. If we have the - general-instruction-extensions, then we have MULTIPLY SINGLE - IMMEDIATE with a signed 32-bit, otherwise we have only - MULTIPLY HALFWORD IMMEDIATE, with a signed 16-bit. */ - if (s390_facilities & FACILITY_GEN_INST_EXT) { - return val == (int32_t)val; - } else { - return val == (int16_t)val; - } + if (ct & TCG_CT_CONST_S16) { + return val == (int16_t)val; + } else if (ct & TCG_CT_CONST_S32) { + return val == (int32_t)val; } else if (ct & TCG_CT_CONST_ADLI) { return tcg_match_add2i(type, val); } else if (ct & TCG_CT_CONST_ORI) { @@ -2239,7 +2237,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) static const TCGTargetOpDef r_rZ = { .args_ct_str = { "r", "rZ" } }; static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } }; static const TCGTargetOpDef r_0_ri = { .args_ct_str = { "r", "0", "ri" } }; - static const TCGTargetOpDef r_0_rK = { .args_ct_str = { "r", "0", "rK" } }; + static const TCGTargetOpDef r_0_rI = { .args_ct_str = { "r", "0", "rI" } }; + static const TCGTargetOpDef r_0_rJ = { .args_ct_str = { "r", "0", "rJ" } }; static const TCGTargetOpDef r_0_rO = { .args_ct_str = { "r", "0", "rO" } }; static const TCGTargetOpDef r_0_rX = { .args_ct_str = { "r", "0", "rX" } }; @@ -2274,9 +2273,15 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_sub_i32: case INDEX_op_sub_i64: return &r_0_ri; + case INDEX_op_mul_i32: + /* If we have the general-instruction-extensions, then we have + MULTIPLY SINGLE IMMEDIATE with a signed 32-bit, otherwise we + have only MULTIPLY HALFWORD IMMEDIATE, with a signed 16-bit. */ + return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_ri : &r_0_rI); case INDEX_op_mul_i64: - return &r_0_rK; + return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_rJ : &r_0_rI); + case INDEX_op_or_i32: case INDEX_op_or_i64: return &r_0_rO; From patchwork Tue Aug 29 20:47:55 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 111257 Delivered-To: patch@linaro.org Received: by 10.140.95.112 with SMTP id h103csp1931732qge; Tue, 29 Aug 2017 13:55:19 -0700 (PDT) X-Received: by 10.237.51.37 with SMTP id u34mr7406268qtd.257.1504040119793; Tue, 29 Aug 2017 13:55:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504040119; cv=none; d=google.com; s=arc-20160816; b=dkRMdGTsKdh1DMEtAlNRzjeX++Y/6w70BNrt/0me+dTGQ0UhyLcISWCNjWBs2AoDDa l4boO2JrmfLP7frlwHR8nOrZQPC/KKERQO8SwgHgH2zeopjikVtSghmyFR0J908e9mQ7 dqDBSj65MCLCKYls4fgnQMUM453m09iMGrBSCMQ1aLovM47Zp4geQviHjmI9G9FFaloJ 2WZjkCu16QxUkNuAF6Vg1GkuNAE8svhAgTyjGevdZilG7Bql7lFL7cqu/t/my2ClOSQZ sj2S1syu6p1jvt36UONmMeW0sS2UCA44kgQ5GIGzOaTlMFMo18qBEYjfvGf/CKN4ubS4 GNCQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=+xk74aQne64nnvSHJDOsLuL5qJmlj3IuSazRcsfg9Ns=; b=jlpOBWV0PDPQpKxoH+U0S4kT4Yw1B/M/ZqyRsMIqvzXKOdw3XdU3xLGQerqh8do1Dw QL/GwRjsZ8+W9BH67TRQsAJOdmMPmNeZhQlTKtOfahxv6eTDSMHnneXrsZT76dzhXMiD BJhJDSI6SY2pDbM3qZ73ayt1amcl57vV9w9Ib/Vfy3xh3/O8KIOEdiJyCFQ6Pd9ieT7F l/inP4/oyMiHoA7AwVmOVVsRMWAAaq+PwKpEbiDWZ2A8v3JjMX4G4rvbZyyow8R/sNqb JGXLzawEworAxJ1YSc+FZ4gF7sZD3li44JpbJUEHJ30GlbzM76dsuzaXPt7CKruo1r96 ZIsA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=UXB8wM10; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id i84sm6633646pfj.139.2017.08.29.13.48.07 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 Aug 2017 13:48:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 29 Aug 2017 13:47:55 -0700 Message-Id: <20170829204759.6853-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170829204759.6853-1-richard.henderson@linaro.org> References: <20170829204759.6853-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22a Subject: [Qemu-devel] [PATCH 4/8] tcg/s390: Merge add2i facilities check to tcg_target_op_def X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: borntraeger@de.ibm.com, cohuck@redhat.com, agraf@suse.de, Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.inc.c | 38 ++++++++++++++------------------------ 1 file changed, 14 insertions(+), 24 deletions(-) -- 2.13.5 diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index ff3f644f8e..6b08ccea6d 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -43,7 +43,7 @@ #define TCG_CT_CONST_ORI 0x400 #define TCG_CT_CONST_XORI 0x800 #define TCG_CT_CONST_U31 0x1000 -#define TCG_CT_CONST_ADLI 0x2000 +#define TCG_CT_CONST_S33 0x2000 #define TCG_CT_CONST_ZERO 0x4000 /* Several places within the instruction set 0 means "no register" @@ -387,7 +387,7 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, tcg_regset_set_reg(ct->u.regs, TCG_REG_R3); break; case 'A': - ct->ct |= TCG_CT_CONST_ADLI; + ct->ct |= TCG_CT_CONST_S33; break; case 'I': ct->ct |= TCG_CT_CONST_S16; @@ -478,20 +478,6 @@ static int tcg_match_xori(TCGType type, tcg_target_long val) return 1; } -/* Immediates to be used with add2/sub2. */ - -static int tcg_match_add2i(TCGType type, tcg_target_long val) -{ - if (s390_facilities & FACILITY_EXT_IMM) { - if (type == TCG_TYPE_I32) { - return 1; - } else if (val >= -0xffffffffll && val <= 0xffffffffll) { - return 1; - } - } - return 0; -} - /* Test if a constant matches the constraint. */ static int tcg_target_const_match(tcg_target_long val, TCGType type, const TCGArgConstraint *arg_ct) @@ -511,8 +497,8 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type, return val == (int16_t)val; } else if (ct & TCG_CT_CONST_S32) { return val == (int32_t)val; - } else if (ct & TCG_CT_CONST_ADLI) { - return tcg_match_add2i(type, val); + } else if (ct & TCG_CT_CONST_S33) { + return val >= -0xffffffffll && val <= 0xffffffffll; } else if (ct & TCG_CT_CONST_ORI) { return tcg_match_ori(type, val); } else if (ct & TCG_CT_CONST_XORI) { @@ -2241,6 +2227,12 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) static const TCGTargetOpDef r_0_rJ = { .args_ct_str = { "r", "0", "rJ" } }; static const TCGTargetOpDef r_0_rO = { .args_ct_str = { "r", "0", "rO" } }; static const TCGTargetOpDef r_0_rX = { .args_ct_str = { "r", "0", "rX" } }; + static const TCGTargetOpDef a2_r + = { .args_ct_str = { "r", "r", "0", "1", "r", "r" } }; + static const TCGTargetOpDef a2_ri + = { .args_ct_str = { "r", "r", "0", "1", "ri", "r" } }; + static const TCGTargetOpDef a2_rA + = { .args_ct_str = { "r", "r", "0", "1", "rA", "r" } }; switch (op) { case INDEX_op_goto_ptr: @@ -2389,15 +2381,13 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) = { .args_ct_str = { "b", "a", "0", "r" } }; return &mul2; } + case INDEX_op_add2_i32: - case INDEX_op_add2_i64: case INDEX_op_sub2_i32: + return (s390_facilities & FACILITY_EXT_IMM ? &a2_ri : &a2_r); + case INDEX_op_add2_i64: case INDEX_op_sub2_i64: - { - static const TCGTargetOpDef arith2 - = { .args_ct_str = { "r", "r", "0", "1", "rA", "r" } }; - return &arith2; - } + return (s390_facilities & FACILITY_EXT_IMM ? &a2_rA : &a2_r); default: break; From patchwork Tue Aug 29 20:47:56 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 111256 Delivered-To: patch@linaro.org Received: by 10.140.95.112 with SMTP id h103csp1929288qge; Tue, 29 Aug 2017 13:52:51 -0700 (PDT) X-Received: by 10.237.53.115 with SMTP id b48mr7341549qte.299.1504039971423; Tue, 29 Aug 2017 13:52:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504039971; cv=none; d=google.com; s=arc-20160816; b=uufc4Ck1JweXNVP5MAz/5DYRlMZwyGS8jdAUZZQnvKWhTagl7nFtYP/TPK+yUoodFX T7KLoagg5Pt3e5LYrmm7P3dd2sNNUdIVDmifA/sFd2tqeGaDbldfMVH9K8sayzLWtBa0 JVZDO0SiKsiPQjTUPXB63yfv895+LP2J1kK3f3tu+JkL7PvEuMQRFdm/aV9ifgN51QCU gMWJVJxDKs7qtvs6zFhH+ofWTj560VjzEGBplp8pwFBGloBMtviLXt24umYi2naCjVkn QiPUb03SfpNlOHHy1qI8hw1NftnoIq+7QX6sK/dOXYMJURZ6WUoYcFCV4QAC8WpL6WrS HGDA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=z1QnsbS9MFumUozer0g7J9ZIxQh46hRZoXAWdZEeU2g=; b=a0Hkv8psmYAb2nth5qWXegatYHuH9wGb+e4smloQdFWqFkE2+sriLro+XwiPRtnft+ nFGLLar9fah+daZ5OeHXA8xqeNYzJLxAzrv8Hng54bpwB2mfHFcI2hPvTM9Ef6LERaA0 We8C856pKyFOIxQr7ghyUPv7Yx8Tyrpn6189uazkPdor/nuRjdV5MQXXrZFkLm8xp1Am 5JJi3/dDVWQp/brenozPFd3U5oXa1D93+oagOh6WYnKFWPbwwWyLey8eZ8yOLu1TLIW+ m2oUOYupzJbCAEAKGoQEG6oo8DcIrCCET2IvdrYTjuCugxvbx/V0smCVu7MpJMNBLV3e Tpxg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=BYS8IDyG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id i84sm6633646pfj.139.2017.08.29.13.48.08 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 Aug 2017 13:48:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 29 Aug 2017 13:47:56 -0700 Message-Id: <20170829204759.6853-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170829204759.6853-1-richard.henderson@linaro.org> References: <20170829204759.6853-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22a Subject: [Qemu-devel] [PATCH 5/8] tcg/s390: Merge ori+xori facilities check to tcg_target_op_def X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: borntraeger@de.ibm.com, cohuck@redhat.com, agraf@suse.de, Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.inc.c | 101 +++++++++++++++------------------------------- 1 file changed, 33 insertions(+), 68 deletions(-) -- 2.13.5 diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index 6b08ccea6d..5414c9d879 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -40,8 +40,8 @@ #define TCG_CT_CONST_S16 0x100 #define TCG_CT_CONST_S32 0x200 -#define TCG_CT_CONST_ORI 0x400 -#define TCG_CT_CONST_XORI 0x800 +#define TCG_CT_CONST_NN16 0x400 +#define TCG_CT_CONST_NN32 0x800 #define TCG_CT_CONST_U31 0x1000 #define TCG_CT_CONST_S33 0x2000 #define TCG_CT_CONST_ZERO 0x4000 @@ -395,11 +395,11 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, case 'J': ct->ct |= TCG_CT_CONST_S32; break; - case 'O': - ct->ct |= TCG_CT_CONST_ORI; + case 'N': + ct->ct |= TCG_CT_CONST_NN16; break; - case 'X': - ct->ct |= TCG_CT_CONST_XORI; + case 'M': + ct->ct |= TCG_CT_CONST_NN32; break; case 'C': /* ??? We have no insight here into whether the comparison is @@ -424,60 +424,6 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, return ct_str; } -/* Immediates to be used with logical OR. This is an optimization only, - since a full 64-bit immediate OR can always be performed with 4 sequential - OI[LH][LH] instructions. What we're looking for is immediates that we - can load efficiently, and the immediate load plus the reg-reg OR is - smaller than the sequential OI's. */ - -static int tcg_match_ori(TCGType type, tcg_target_long val) -{ - if (s390_facilities & FACILITY_EXT_IMM) { - if (type == TCG_TYPE_I32) { - /* All 32-bit ORs can be performed with 1 48-bit insn. */ - return 1; - } - } - - /* Look for negative values. These are best to load with LGHI. */ - if (val < 0) { - if (val == (int16_t)val) { - return 0; - } - if (s390_facilities & FACILITY_EXT_IMM) { - if (val == (int32_t)val) { - return 0; - } - } - } - - return 1; -} - -/* Immediates to be used with logical XOR. This is almost, but not quite, - only an optimization. XOR with immediate is only supported with the - extended-immediate facility. That said, there are a few patterns for - which it is better to load the value into a register first. */ - -static int tcg_match_xori(TCGType type, tcg_target_long val) -{ - if ((s390_facilities & FACILITY_EXT_IMM) == 0) { - return 0; - } - - if (type == TCG_TYPE_I32) { - /* All 32-bit XORs can be performed with 1 48-bit insn. */ - return 1; - } - - /* Look for negative values. These are best to load with LGHI. */ - if (val < 0 && val == (int32_t)val) { - return 0; - } - - return 1; -} - /* Test if a constant matches the constraint. */ static int tcg_target_const_match(tcg_target_long val, TCGType type, const TCGArgConstraint *arg_ct) @@ -499,10 +445,10 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type, return val == (int32_t)val; } else if (ct & TCG_CT_CONST_S33) { return val >= -0xffffffffll && val <= 0xffffffffll; - } else if (ct & TCG_CT_CONST_ORI) { - return tcg_match_ori(type, val); - } else if (ct & TCG_CT_CONST_XORI) { - return tcg_match_xori(type, val); + } else if (ct & TCG_CT_CONST_NN16) { + return !(val < 0 && val == (int16_t)val); + } else if (ct & TCG_CT_CONST_NN32) { + return !(val < 0 && val == (int32_t)val); } else if (ct & TCG_CT_CONST_U31) { return val >= 0 && val <= 0x7fffffff; } else if (ct & TCG_CT_CONST_ZERO) { @@ -2222,11 +2168,12 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) static const TCGTargetOpDef r_rC = { .args_ct_str = { "r", "rC" } }; static const TCGTargetOpDef r_rZ = { .args_ct_str = { "r", "rZ" } }; static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } }; + static const TCGTargetOpDef r_0_r = { .args_ct_str = { "r", "0", "r" } }; static const TCGTargetOpDef r_0_ri = { .args_ct_str = { "r", "0", "ri" } }; static const TCGTargetOpDef r_0_rI = { .args_ct_str = { "r", "0", "rI" } }; static const TCGTargetOpDef r_0_rJ = { .args_ct_str = { "r", "0", "rJ" } }; - static const TCGTargetOpDef r_0_rO = { .args_ct_str = { "r", "0", "rO" } }; - static const TCGTargetOpDef r_0_rX = { .args_ct_str = { "r", "0", "rX" } }; + static const TCGTargetOpDef r_0_rN = { .args_ct_str = { "r", "0", "rN" } }; + static const TCGTargetOpDef r_0_rM = { .args_ct_str = { "r", "0", "rM" } }; static const TCGTargetOpDef a2_r = { .args_ct_str = { "r", "r", "0", "1", "r", "r" } }; static const TCGTargetOpDef a2_ri @@ -2275,11 +2222,29 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_rJ : &r_0_rI); case INDEX_op_or_i32: + /* The use of [iNM] constraints are optimization only, since a full + 64-bit immediate OR can always be performed with 4 sequential + OI[LH][LH] instructions. By rejecting certain negative ranges, + the immediate load plus the reg-reg OR is smaller. */ + return (s390_facilities & FACILITY_EXT_IMM + ? &r_0_ri + : &r_0_rN); case INDEX_op_or_i64: - return &r_0_rO; + return (s390_facilities & FACILITY_EXT_IMM + ? &r_0_rM + : &r_0_rN); + case INDEX_op_xor_i32: + /* Without EXT_IMM, no immediates are supported. Otherwise, + rejecting certain negative ranges leads to smaller code. */ + return (s390_facilities & FACILITY_EXT_IMM + ? &r_0_ri + : &r_0_r); case INDEX_op_xor_i64: - return &r_0_rX; + return (s390_facilities & FACILITY_EXT_IMM + ? &r_0_rM + : &r_0_r); + case INDEX_op_and_i32: case INDEX_op_and_i64: return &r_0_ri; From patchwork Tue Aug 29 20:47:57 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 111258 Delivered-To: patch@linaro.org Received: by 10.140.95.112 with SMTP id h103csp1934289qge; Tue, 29 Aug 2017 13:57:54 -0700 (PDT) X-Received: by 10.55.164.136 with SMTP id n130mr7120899qke.221.1504040274621; Tue, 29 Aug 2017 13:57:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504040274; cv=none; d=google.com; s=arc-20160816; b=BZ0JB6kimEFMsAQ67m60E5m7WLb261VCN7n7Q1VIgzXCN86HD9PZkZ2H66aQAl5WB5 5qyz6n/44CeQL/sUzf3TLA/RviY8+Z75m7mlpsQy8yVHjMHnjA5Rv0+atAOcaOY85AGx tX8j9/jx8juQcGhwJDXtin91v7bpXG53KVk4r6AiimExl/GqodvUrGBUzso3i7jCr4X6 9vvIahH+KfWJb8ARQNaQOKzrX39vHCA+e4BMfih9WWgZCRE3to02ROQSlzPRYuF/AqZN In8remjk5zwtivLgSGWwI5FSl3Imqz0WMqt4uP8m0ItvBTSCjjwz9cSNd+WlcCmlNfxv 1k8w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=g8yP4qkSZz+fxQ+4zsqNUcLQi6JaL8uvacalBHt62FU=; b=bwMeH9Su6Mlu5M0tkKtL9R7nE2b1YWJKijG3VtEVp1e/Q0/O28Ghh2sucJG2PvJz/o EBSyz6tvcdqKUhzMHupwweapOHL/LD5vGC6URt6hVY6PwOdhvO3OOm84j5M/ZK0tP/jR 6sFqDnDxCcUOkLxj3nnoUWqy8L/NW2GSphLDW1IJK00UwG7XDwdcLx2MO8rSSWxLaKh3 v5qQaJxNzexpDAjwLz9IOx++0DHIRVShE0CuiLJXZVAcToDB+eP4ncPBjNV109SrQdMj Vih1IDyC2r/90R9V6Cp/TyqUdR2jCTP0Og3wG/D65cFk5M0Y+4H+alzofWOChxBENrnD pjJQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=YfBHJhA+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id i84sm6633646pfj.139.2017.08.29.13.48.10 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 Aug 2017 13:48:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 29 Aug 2017 13:47:57 -0700 Message-Id: <20170829204759.6853-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170829204759.6853-1-richard.henderson@linaro.org> References: <20170829204759.6853-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22c Subject: [Qemu-devel] [PATCH 6/8] tcg/s390: Use distinct-operands facility X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: borntraeger@de.ibm.com, cohuck@redhat.com, agraf@suse.de, Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson This allows using a 3-operand insn form for some arithmetic, logicals and shifts. Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.h | 1 + tcg/s390/tcg-target.inc.c | 118 +++++++++++++++++++++++++++++++++++----------- 2 files changed, 91 insertions(+), 28 deletions(-) -- 2.13.5 diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 957f0c0afe..1b5eb22c26 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -58,6 +58,7 @@ typedef enum TCGReg { #define FACILITY_GEN_INST_EXT (1ULL << (63 - 34)) #define FACILITY_LOAD_ON_COND (1ULL << (63 - 45)) #define FACILITY_FAST_BCR_SER FACILITY_LOAD_ON_COND +#define FACILITY_DISTINCT_OPS FACILITY_LOAD_ON_COND extern uint64_t s390_facilities; diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index 5414c9d879..a80b07db65 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -159,6 +159,16 @@ typedef enum S390Opcode { RRF_LOCR = 0xb9f2, RRF_LOCGR = 0xb9e2, + RRF_NRK = 0xb9f4, + RRF_NGRK = 0xb9e4, + RRF_ORK = 0xb9f6, + RRF_OGRK = 0xb9e6, + RRF_SRK = 0xb9f9, + RRF_SGRK = 0xb9e9, + RRF_SLRK = 0xb9fb, + RRF_SLGRK = 0xb9eb, + RRF_XRK = 0xb9f7, + RRF_XGRK = 0xb9e7, RR_AR = 0x1a, RR_ALR = 0x1e, @@ -179,8 +189,11 @@ typedef enum S390Opcode { RSY_RLL = 0xeb1d, RSY_RLLG = 0xeb1c, RSY_SLLG = 0xeb0d, + RSY_SLLK = 0xebdf, RSY_SRAG = 0xeb0a, + RSY_SRAK = 0xebdc, RSY_SRLG = 0xeb0c, + RSY_SRLK = 0xebde, RS_SLL = 0x89, RS_SRA = 0x8a, @@ -1065,23 +1078,29 @@ static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond, case TCG_COND_GEU: do_geu: /* We need "real" carry semantics, so use SUBTRACT LOGICAL - instead of COMPARE LOGICAL. This needs an extra move. */ - tcg_out_mov(s, type, TCG_TMP0, c1); + instead of COMPARE LOGICAL. This may need an extra move. */ if (c2const) { - tcg_out_movi(s, TCG_TYPE_I64, dest, 0); + tcg_out_mov(s, type, TCG_TMP0, c1); if (type == TCG_TYPE_I32) { tcg_out_insn(s, RIL, SLFI, TCG_TMP0, c2); } else { tcg_out_insn(s, RIL, SLGFI, TCG_TMP0, c2); } + } else if (s390_facilities & FACILITY_DISTINCT_OPS) { + if (type == TCG_TYPE_I32) { + tcg_out_insn(s, RRF, SLRK, TCG_TMP0, c1, c2); + } else { + tcg_out_insn(s, RRF, SLGRK, TCG_TMP0, c1, c2); + } } else { + tcg_out_mov(s, type, TCG_TMP0, c1); if (type == TCG_TYPE_I32) { tcg_out_insn(s, RR, SLR, TCG_TMP0, c2); } else { tcg_out_insn(s, RRE, SLGR, TCG_TMP0, c2); } - tcg_out_movi(s, TCG_TYPE_I64, dest, 0); } + tcg_out_movi(s, TCG_TYPE_I64, dest, 0); tcg_out_insn(s, RRE, ALCGR, dest, dest); return; @@ -1648,7 +1667,7 @@ static void tcg_out_qemu_st(TCGContext* s, TCGReg data_reg, TCGReg addr_reg, static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, const int *const_args) { - S390Opcode op; + S390Opcode op, op2; TCGArg a0, a1, a2; switch (opc) { @@ -1753,29 +1772,44 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, if (const_args[2]) { a2 = -a2; goto do_addi_32; + } else if (a0 == a1) { + tcg_out_insn(s, RR, SR, a0, a2); + } else { + tcg_out_insn(s, RRF, SRK, a0, a1, a2); } - tcg_out_insn(s, RR, SR, args[0], args[2]); break; case INDEX_op_and_i32: + a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; if (const_args[2]) { - tgen_andi(s, TCG_TYPE_I32, args[0], args[2]); + tcg_out_mov(s, TCG_TYPE_I32, a0, a1); + tgen_andi(s, TCG_TYPE_I32, a0, a2); + } else if (a0 == a1) { + tcg_out_insn(s, RR, NR, a0, a2); } else { - tcg_out_insn(s, RR, NR, args[0], args[2]); + tcg_out_insn(s, RRF, NRK, a0, a1, a2); } break; case INDEX_op_or_i32: + a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; if (const_args[2]) { - tgen64_ori(s, args[0], args[2] & 0xffffffff); + tcg_out_mov(s, TCG_TYPE_I32, a0, a1); + tgen64_ori(s, a0, a2); + } else if (a0 == a1) { + tcg_out_insn(s, RR, OR, a0, a2); } else { - tcg_out_insn(s, RR, OR, args[0], args[2]); + tcg_out_insn(s, RRF, ORK, a0, a1, a2); } break; case INDEX_op_xor_i32: + a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; if (const_args[2]) { - tgen64_xori(s, args[0], args[2] & 0xffffffff); - } else { + tcg_out_mov(s, TCG_TYPE_I32, a0, a1); + tgen64_xori(s, a0, a2); + } else if (a0 == a1) { tcg_out_insn(s, RR, XR, args[0], args[2]); + } else { + tcg_out_insn(s, RRF, XRK, a0, a1, a2); } break; @@ -1804,18 +1838,31 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_shl_i32: op = RS_SLL; + op2 = RSY_SLLK; do_shift32: - if (const_args[2]) { - tcg_out_sh32(s, op, args[0], TCG_REG_NONE, args[2]); + a0 = args[0], a1 = args[1], a2 = (int32_t)args[2]; + if (a0 == a1) { + if (const_args[2]) { + tcg_out_sh32(s, op, a0, TCG_REG_NONE, a2); + } else { + tcg_out_sh32(s, op, a0, a2, 0); + } } else { - tcg_out_sh32(s, op, args[0], args[2], 0); + /* Using tcg_out_sh64 here for the format; it is a 32-bit shift. */ + if (const_args[2]) { + tcg_out_sh64(s, op2, a0, a1, TCG_REG_NONE, a2); + } else { + tcg_out_sh64(s, op2, a0, a1, a2, 0); + } } break; case INDEX_op_shr_i32: op = RS_SRL; + op2 = RSY_SRLK; goto do_shift32; case INDEX_op_sar_i32: op = RS_SRA; + op2 = RSY_SRAK; goto do_shift32; case INDEX_op_rotl_i32: @@ -1957,30 +2004,44 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, if (const_args[2]) { a2 = -a2; goto do_addi_64; + } else if (a0 == a1) { + tcg_out_insn(s, RRE, SGR, a0, a2); } else { - tcg_out_insn(s, RRE, SGR, args[0], args[2]); + tcg_out_insn(s, RRF, SGRK, a0, a1, a2); } break; case INDEX_op_and_i64: + a0 = args[0], a1 = args[1], a2 = args[2]; if (const_args[2]) { + tcg_out_mov(s, TCG_TYPE_I64, a0, a1); tgen_andi(s, TCG_TYPE_I64, args[0], args[2]); - } else { + } else if (a0 == a1) { tcg_out_insn(s, RRE, NGR, args[0], args[2]); + } else { + tcg_out_insn(s, RRF, NGRK, a0, a1, a2); } break; case INDEX_op_or_i64: + a0 = args[0], a1 = args[1], a2 = args[2]; if (const_args[2]) { - tgen64_ori(s, args[0], args[2]); + tcg_out_mov(s, TCG_TYPE_I64, a0, a1); + tgen64_ori(s, a0, a2); + } else if (a0 == a1) { + tcg_out_insn(s, RRE, OGR, a0, a2); } else { - tcg_out_insn(s, RRE, OGR, args[0], args[2]); + tcg_out_insn(s, RRF, OGRK, a0, a1, a2); } break; case INDEX_op_xor_i64: + a0 = args[0], a1 = args[1], a2 = args[2]; if (const_args[2]) { - tgen64_xori(s, args[0], args[2]); + tcg_out_mov(s, TCG_TYPE_I64, a0, a1); + tgen64_xori(s, a0, a2); + } else if (a0 == a1) { + tcg_out_insn(s, RRE, XGR, a0, a2); } else { - tcg_out_insn(s, RRE, XGR, args[0], args[2]); + tcg_out_insn(s, RRF, XGRK, a0, a1, a2); } break; @@ -2168,6 +2229,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) static const TCGTargetOpDef r_rC = { .args_ct_str = { "r", "rC" } }; static const TCGTargetOpDef r_rZ = { .args_ct_str = { "r", "rZ" } }; static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } }; + static const TCGTargetOpDef r_r_rM = { .args_ct_str = { "r", "r", "rM" } }; static const TCGTargetOpDef r_0_r = { .args_ct_str = { "r", "0", "r" } }; static const TCGTargetOpDef r_0_ri = { .args_ct_str = { "r", "0", "ri" } }; static const TCGTargetOpDef r_0_rI = { .args_ct_str = { "r", "0", "rI" } }; @@ -2211,7 +2273,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) return &r_r_ri; case INDEX_op_sub_i32: case INDEX_op_sub_i64: - return &r_0_ri; + return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri); case INDEX_op_mul_i32: /* If we have the general-instruction-extensions, then we have @@ -2227,32 +2289,32 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) OI[LH][LH] instructions. By rejecting certain negative ranges, the immediate load plus the reg-reg OR is smaller. */ return (s390_facilities & FACILITY_EXT_IMM - ? &r_0_ri + ? (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri) : &r_0_rN); case INDEX_op_or_i64: return (s390_facilities & FACILITY_EXT_IMM - ? &r_0_rM + ? (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_rM : &r_0_rM) : &r_0_rN); case INDEX_op_xor_i32: /* Without EXT_IMM, no immediates are supported. Otherwise, rejecting certain negative ranges leads to smaller code. */ return (s390_facilities & FACILITY_EXT_IMM - ? &r_0_ri + ? (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri) : &r_0_r); case INDEX_op_xor_i64: return (s390_facilities & FACILITY_EXT_IMM - ? &r_0_rM + ? (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_rM : &r_0_rM) : &r_0_r); case INDEX_op_and_i32: case INDEX_op_and_i64: - return &r_0_ri; + return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri); case INDEX_op_shl_i32: case INDEX_op_shr_i32: case INDEX_op_sar_i32: - return &r_0_ri; + return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri); case INDEX_op_shl_i64: case INDEX_op_shr_i64: From patchwork Tue Aug 29 20:47:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 111259 Delivered-To: patch@linaro.org Received: by 10.140.95.112 with SMTP id h103csp1936654qge; Tue, 29 Aug 2017 14:00:12 -0700 (PDT) X-Received: by 10.55.48.71 with SMTP id w68mr7163131qkw.345.1504040412941; Tue, 29 Aug 2017 14:00:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504040412; cv=none; d=google.com; s=arc-20160816; b=QB9Hfg2fNC6IxZMft2LCvXXo2LVttrJswvMob0ivL8ipY2yjTWXL+IaoGi34BTS+r1 DQ0f4hWt4l9yHrIAwc0wZ37Q+BTMSCPzm7lWdAIAAWrUaZVLQbHJAZpHfSB0amN1F0dq zOshZgrLJzR6rEj+Sw3hlrjjOqMSwQv2biqf37Xi5+qx8fOqyBJiyjZLt5UFHRzMoeD7 hHFnK8XXAQ26QzJobq52CA3qf1M271nzAdIsEI96Bn+90FxTa9M0RgkSnMu5dPrOdMuP V3DpDHUH8JvqwQprRCl/HDbqfKgfvRY17Z8HjenhRRXHoLQN+CK+KOfJmNa/Sk/zn2wi K+OQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=kDmH5DemrkbAsivBHhbt4U1wgoxR7gHo6X6o0mKr35Y=; b=NLmsh376391OTDyEi6Jep2tbcZg/8s781cuxt3D8ujoo7zDzwwXBxgLCBv3+XjTnKj 1kPZLfRvVT+VJDJ0U6HuLPM9GqzqdD2rudGaciY2ET05lS+O1ajnOteM83xd29tpo+QO NOT1Bskgp/X2brazVtYWNp8eOL964UyIZ8VN0a1DfoVm1KuD53ydSZ7V+sRPbbTy+osd rE6sPklbPZHN4bp90t6dPWhudLjoOThx8QkBFwL/CCv+8HG2w8XbU/Jl4PkkkjZYoBz6 KostQoTX8YRtz4UWiEYC5/J2pP7MQjOp8Cc9GCw1DpYyguIQ38pZbBW+AUkddzYgrIO3 viXA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=hECew1pg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id i84sm6633646pfj.139.2017.08.29.13.48.11 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 Aug 2017 13:48:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 29 Aug 2017 13:47:58 -0700 Message-Id: <20170829204759.6853-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170829204759.6853-1-richard.henderson@linaro.org> References: <20170829204759.6853-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::235 Subject: [Qemu-devel] [PATCH 7/8] tcg/s390: Use load-on-condition-2 facility X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: borntraeger@de.ibm.com, cohuck@redhat.com, agraf@suse.de, Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson This allows LOAD HALFWORD IMMEDIATE ON CONDITION, eliminating one insn in some common cases. Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.h | 1 + tcg/s390/tcg-target.inc.c | 79 +++++++++++++++++++++++++++++++++++++---------- 2 files changed, 63 insertions(+), 17 deletions(-) -- 2.13.5 diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 1b5eb22c26..81fc179459 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -59,6 +59,7 @@ typedef enum TCGReg { #define FACILITY_LOAD_ON_COND (1ULL << (63 - 45)) #define FACILITY_FAST_BCR_SER FACILITY_LOAD_ON_COND #define FACILITY_DISTINCT_OPS FACILITY_LOAD_ON_COND +#define FACILITY_LOAD_ON_COND2 (1ULL << (63 - 53)) extern uint64_t s390_facilities; diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index a80b07db65..0de968fde2 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -122,6 +122,7 @@ typedef enum S390Opcode { RIE_CLGIJ = 0xec7d, RIE_CLRJ = 0xec77, RIE_CRJ = 0xec76, + RIE_LOCGHI = 0xec46, RIE_RISBG = 0xec55, RRE_AGR = 0xb908, @@ -495,6 +496,13 @@ static void tcg_out_insn_RI(TCGContext *s, S390Opcode op, TCGReg r1, int i2) tcg_out32(s, (op << 16) | (r1 << 20) | (i2 & 0xffff)); } +static void tcg_out_insn_RIE(TCGContext *s, S390Opcode op, TCGReg r1, + int i2, int m3) +{ + tcg_out16(s, (op & 0xff00) | (r1 << 4) | m3); + tcg_out32(s, (i2 << 16) | (op & 0xff)); +} + static void tcg_out_insn_RIL(TCGContext *s, S390Opcode op, TCGReg r1, int i2) { tcg_out16(s, op | (r1 << 4)); @@ -1063,7 +1071,20 @@ static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond, TCGReg dest, TCGReg c1, TCGArg c2, int c2const) { int cc; + bool have_loc; + /* With LOC2, we can always emit the minimum 3 insns. */ + if (s390_facilities & FACILITY_LOAD_ON_COND2) { + /* Emit: d = 0, d = (cc ? 1 : d). */ + cc = tgen_cmp(s, type, cond, c1, c2, c2const, false); + tcg_out_movi(s, TCG_TYPE_I64, dest, 0); + tcg_out_insn(s, RIE, LOCGHI, dest, 1, cc); + return; + } + + have_loc = (s390_facilities & FACILITY_LOAD_ON_COND) != 0; + + /* For HAVE_LOC, only the path through do_greater is smaller. */ switch (cond) { case TCG_COND_GTU: case TCG_COND_GT: @@ -1076,6 +1097,9 @@ static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond, return; case TCG_COND_GEU: + if (have_loc) { + goto do_loc; + } do_geu: /* We need "real" carry semantics, so use SUBTRACT LOGICAL instead of COMPARE LOGICAL. This may need an extra move. */ @@ -1105,10 +1129,17 @@ static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond, return; case TCG_COND_LEU: + if (have_loc) { + goto do_loc; + } + /* fallthru */ case TCG_COND_LTU: case TCG_COND_LT: /* Swap operands so that we can use GEU/GTU/GT. */ if (c2const) { + if (have_loc) { + goto do_loc; + } tcg_out_movi(s, type, TCG_TMP0, c2); c2 = c1; c2const = 0; @@ -1133,6 +1164,9 @@ static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond, break; case TCG_COND_EQ: + if (have_loc) { + goto do_loc; + } /* X == 0 is X <= 0 is 0 >= X. */ if (c2const && c2 == 0) { tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 0); @@ -1148,33 +1182,39 @@ static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond, } cc = tgen_cmp(s, type, cond, c1, c2, c2const, false); - if (s390_facilities & FACILITY_LOAD_ON_COND) { - /* Emit: d = 0, t = 1, d = (cc ? t : d). */ - tcg_out_movi(s, TCG_TYPE_I64, dest, 0); - tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 1); - tcg_out_insn(s, RRF, LOCGR, dest, TCG_TMP0, cc); - } else { - /* Emit: d = 1; if (cc) goto over; d = 0; over: */ - tcg_out_movi(s, type, dest, 1); - tcg_out_insn(s, RI, BRC, cc, (4 + 4) >> 1); - tcg_out_movi(s, type, dest, 0); - } + /* Emit: d = 1; if (cc) goto over; d = 0; over: */ + tcg_out_movi(s, type, dest, 1); + tcg_out_insn(s, RI, BRC, cc, (4 + 4) >> 1); + tcg_out_movi(s, type, dest, 0); + return; + + do_loc: + cc = tgen_cmp(s, type, cond, c1, c2, c2const, false); + /* Emit: d = 0, t = 1, d = (cc ? t : d). */ + tcg_out_movi(s, TCG_TYPE_I64, dest, 0); + tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 1); + tcg_out_insn(s, RRF, LOCGR, dest, TCG_TMP0, cc); } static void tgen_movcond(TCGContext *s, TCGType type, TCGCond c, TCGReg dest, - TCGReg c1, TCGArg c2, int c2const, TCGReg r3) + TCGReg c1, TCGArg c2, int c2const, + TCGArg v3, int v3const) { int cc; if (s390_facilities & FACILITY_LOAD_ON_COND) { cc = tgen_cmp(s, type, c, c1, c2, c2const, false); - tcg_out_insn(s, RRF, LOCGR, dest, r3, cc); + if (v3const) { + tcg_out_insn(s, RIE, LOCGHI, dest, v3, cc); + } else { + tcg_out_insn(s, RRF, LOCGR, dest, v3, cc); + } } else { c = tcg_invert_cond(c); cc = tgen_cmp(s, type, c, c1, c2, c2const, false); /* Emit: if (cc) goto over; dest = r3; over: */ tcg_out_insn(s, RI, BRC, cc, (4 + 4) >> 1); - tcg_out_insn(s, RRE, LGR, dest, r3); + tcg_out_insn(s, RRE, LGR, dest, v3); } } @@ -1937,7 +1977,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_movcond_i32: tgen_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], - args[2], const_args[2], args[3]); + args[2], const_args[2], args[3], const_args[3]); break; case INDEX_op_qemu_ld_i32: @@ -2170,7 +2210,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_movcond_i64: tgen_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], - args[2], const_args[2], args[3]); + args[2], const_args[2], args[3], const_args[3]); break; OP_32_64(deposit): @@ -2391,7 +2431,12 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) = { .args_ct_str = { "r", "r", "rZ", "r", "0" } }; static const TCGTargetOpDef movc_c = { .args_ct_str = { "r", "r", "rC", "r", "0" } }; - return (s390_facilities & FACILITY_EXT_IMM ? &movc_c : &movc_z); + static const TCGTargetOpDef movc_l + = { .args_ct_str = { "r", "r", "rC", "rI", "0" } }; + return (s390_facilities & FACILITY_EXT_IMM + ? (s390_facilities & FACILITY_LOAD_ON_COND2 + ? &movc_l : &movc_c) + : &movc_z); } case INDEX_op_div2_i32: case INDEX_op_div2_i64: From patchwork Tue Aug 29 20:47:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 111254 Delivered-To: patch@linaro.org Received: by 10.140.95.112 with SMTP id h103csp1929251qge; Tue, 29 Aug 2017 13:52:49 -0700 (PDT) X-Received: by 10.55.12.132 with SMTP id 126mr3212525qkm.316.1504039969164; Tue, 29 Aug 2017 13:52:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504039969; cv=none; d=google.com; s=arc-20160816; b=uFULngY3vz7iraOJdG4palFDFhnkuSuzCcA6m2isLTqBBdjYvx0MtddHZyzflquGZt pOiZSKbcVs3wJyHNeJ15vHE1AzbiQNGKeuxzNQKr9KtoA9jNlGkWvMnVOxaphQoAokP6 w4WdDpgeCbaNR3LYINeHUdBI84tffNR6QKD239LFTL2U2sMUz+iHWRv2BvuzXAB1uo6Q SAsFh148pj6Yb/0Px6wahHa6M1OOsrKPuauU3XjDg0qpJ/Oq6mVAyBp8NX3dKtkdJuc3 CKE0kFf/B3JtA3kGPLuOKZqDAgtnJuv4hxEyBq30Lypy5zZ592ASXGWttmmjzgnbV9YB Gz8g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=7EKO1ayOrpPVDOid0Oz0SpWK65aO/ZVIVhQGxN0Ans4=; b=fsfz477n9MIvlyxjPdXC0jNkcPGJln/GpGZEXbqkzBD/+pWVVDEsPsGAD1Ah13sCyE il+6dXSOaKR4AjOfKsXIIgkMRZPcXKkC3RndCUmiPtfiSAwsWE3lXhp3IRaRdr8QZpCS +1OSChxSHhUnn3zG4wKRNk4jMnn7ekoge+zoFD5o/aysVavhjS0a+dEV7MnA4NkuPxrG CS7Z1txURoMeoEefK7W4KNSmQySDLHUYwaFHt1TCt2LyAKYetmjA8gzcS6BvzFSji6/N otVvzTxxcpiojCtrIr1ekL6OU5aiLRLLjX1LemvZ6pjEB3g1hNPWieezkgVpjGnXh+zc WGUw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=QS2vjLqT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id i84sm6633646pfj.139.2017.08.29.13.48.13 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 Aug 2017 13:48:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 29 Aug 2017 13:47:59 -0700 Message-Id: <20170829204759.6853-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170829204759.6853-1-richard.henderson@linaro.org> References: <20170829204759.6853-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22b Subject: [Qemu-devel] [PATCH 8/8] tcg/s390: Use slbgr for setcond le and leu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: borntraeger@de.ibm.com, cohuck@redhat.com, agraf@suse.de, Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.inc.c | 119 +++++++++++++++++----------------------------- 1 file changed, 43 insertions(+), 76 deletions(-) -- 2.13.5 diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index 0de968fde2..38b9e791ee 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -1084,11 +1084,20 @@ static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond, have_loc = (s390_facilities & FACILITY_LOAD_ON_COND) != 0; - /* For HAVE_LOC, only the path through do_greater is smaller. */ + /* For HAVE_LOC, only the paths through GTU/GT/LEU/LE are smaller. */ + restart: switch (cond) { + case TCG_COND_NE: + /* X != 0 is X > 0. */ + if (c2const && c2 == 0) { + cond = TCG_COND_GTU; + } else { + break; + } + /* fallthru */ + case TCG_COND_GTU: case TCG_COND_GT: - do_greater: /* The result of a compare has CC=2 for GT and CC=3 unused. ADD LOGICAL WITH CARRY considers (CC & 2) the carry bit. */ tgen_cmp(s, type, cond, c1, c2, c2const, true); @@ -1096,49 +1105,33 @@ static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond, tcg_out_insn(s, RRE, ALCGR, dest, dest); return; - case TCG_COND_GEU: - if (have_loc) { - goto do_loc; - } - do_geu: - /* We need "real" carry semantics, so use SUBTRACT LOGICAL - instead of COMPARE LOGICAL. This may need an extra move. */ - if (c2const) { - tcg_out_mov(s, type, TCG_TMP0, c1); - if (type == TCG_TYPE_I32) { - tcg_out_insn(s, RIL, SLFI, TCG_TMP0, c2); - } else { - tcg_out_insn(s, RIL, SLGFI, TCG_TMP0, c2); - } - } else if (s390_facilities & FACILITY_DISTINCT_OPS) { - if (type == TCG_TYPE_I32) { - tcg_out_insn(s, RRF, SLRK, TCG_TMP0, c1, c2); - } else { - tcg_out_insn(s, RRF, SLGRK, TCG_TMP0, c1, c2); - } + case TCG_COND_EQ: + /* X == 0 is X <= 0. */ + if (c2const && c2 == 0) { + cond = TCG_COND_LEU; } else { - tcg_out_mov(s, type, TCG_TMP0, c1); - if (type == TCG_TYPE_I32) { - tcg_out_insn(s, RR, SLR, TCG_TMP0, c2); - } else { - tcg_out_insn(s, RRE, SLGR, TCG_TMP0, c2); - } + break; } - tcg_out_movi(s, TCG_TYPE_I64, dest, 0); - tcg_out_insn(s, RRE, ALCGR, dest, dest); - return; + /* fallthru */ case TCG_COND_LEU: - if (have_loc) { - goto do_loc; - } - /* fallthru */ + case TCG_COND_LE: + /* As above, but we're looking for borrow, or !carry. + The second insn computes d - d - borrow, or -1 for true + and 0 for false. So we must mask to 1 bit afterward. */ + tgen_cmp(s, type, cond, c1, c2, c2const, true); + tcg_out_insn(s, RRE, SLBGR, dest, dest); + tgen_andi(s, type, dest, 1); + return; + + case TCG_COND_GEU: case TCG_COND_LTU: case TCG_COND_LT: - /* Swap operands so that we can use GEU/GTU/GT. */ + case TCG_COND_GE: + /* Swap operands so that we can use LEU/GTU/GT/LE. */ if (c2const) { if (have_loc) { - goto do_loc; + break; } tcg_out_movi(s, type, TCG_TMP0, c2); c2 = c1; @@ -1149,51 +1142,25 @@ static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond, c1 = c2; c2 = t; } - if (cond == TCG_COND_LEU) { - goto do_geu; - } cond = tcg_swap_cond(cond); - goto do_greater; - - case TCG_COND_NE: - /* X != 0 is X > 0. */ - if (c2const && c2 == 0) { - cond = TCG_COND_GTU; - goto do_greater; - } - break; - - case TCG_COND_EQ: - if (have_loc) { - goto do_loc; - } - /* X == 0 is X <= 0 is 0 >= X. */ - if (c2const && c2 == 0) { - tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 0); - c2 = c1; - c2const = 0; - c1 = TCG_TMP0; - goto do_geu; - } - break; + goto restart; default: - break; + g_assert_not_reached(); } cc = tgen_cmp(s, type, cond, c1, c2, c2const, false); - /* Emit: d = 1; if (cc) goto over; d = 0; over: */ - tcg_out_movi(s, type, dest, 1); - tcg_out_insn(s, RI, BRC, cc, (4 + 4) >> 1); - tcg_out_movi(s, type, dest, 0); - return; - - do_loc: - cc = tgen_cmp(s, type, cond, c1, c2, c2const, false); - /* Emit: d = 0, t = 1, d = (cc ? t : d). */ - tcg_out_movi(s, TCG_TYPE_I64, dest, 0); - tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 1); - tcg_out_insn(s, RRF, LOCGR, dest, TCG_TMP0, cc); + if (have_loc) { + /* Emit: d = 0, t = 1, d = (cc ? t : d). */ + tcg_out_movi(s, TCG_TYPE_I64, dest, 0); + tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 1); + tcg_out_insn(s, RRF, LOCGR, dest, TCG_TMP0, cc); + } else { + /* Emit: d = 1; if (cc) goto over; d = 0; over: */ + tcg_out_movi(s, type, dest, 1); + tcg_out_insn(s, RI, BRC, cc, (4 + 4) >> 1); + tcg_out_movi(s, type, dest, 0); + } } static void tgen_movcond(TCGContext *s, TCGType type, TCGCond c, TCGReg dest,