From patchwork Thu Aug 31 13:08:27 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 111387 Delivered-To: patch@linaro.org Received: by 10.140.95.112 with SMTP id h103csp2521273qge; Thu, 31 Aug 2017 06:08:44 -0700 (PDT) X-Google-Smtp-Source: ADKCNb6VuuZrm+Mr8H36utVVmdbd/wllQ/U1Id7U8C2Lmy86dY5JXw9y404tv3TLZn8EiiRlH9ay X-Received: by 10.84.210.196 with SMTP id a62mr2539294pli.382.1504184924730; Thu, 31 Aug 2017 06:08:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504184924; cv=none; d=google.com; s=arc-20160816; b=YjtfmFoB3JFivYPXH97zQCwqI5DyoDH/IBJwgBaDPzOv1RMcNxEdyCqNDaGcR8BVeW skkBKmp2z57ANR7T2VFz00NuKFviGUyaDCMxc5qSUDBNCGVmjzTW6NP0tIQHlscgbtqf jCsCtlIW+yWmccaFVioGKdHiGDU9RksRbdmGRT0BEkh5T1PhuLsB2vNjrk65TULixfgP XtFsgqhgGL5nDNkPjkun4OIknKva4rEKDT76SU9Vgmj2qB08zgEOWqHg37fNvYpd7Lmu AZ67tcHOrDv8XU3kfkiQlp/cI1phCoaPc9ho2JceOHgUGJIRrEKni3mQvCvdaX4ErDW9 ug0w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=z9cBE+ouWn3xFiPRCvovPedFQ4zlm7eEZxbLSopYofM=; b=yJz6zlzDeCn9oNUzy1wtCmqy8cYrjbGOy5WwbUe0AbVfUsZhk5ujOUPG5PKY1j5ZH8 ltA3ZWkZzuVebofEID/N9x/6pY0gM24OpT2MT7lxYkMa6+CeII/3tAuPPtSnaUo+0bzs lHHQyYX8JQnFBSJQg3NtGK4lNJG32S86t8OIG4IVwh2HODyAtsJXvIt17nVdbto0xmh6 UAf/KjvQPYe+GzgmPQCZyCuwRdzBNqQmM4ST3vm6VI+5nm28TtL48deY8s0i15UugkR7 rnd652jHrT6CgfHMQ5R4qGkXSHjjueWwMbI2jtvjiIlkJbLVkBksLazOKhWe8M599aeY sYzQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=E8bczuc/; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [2001:19d0:306:5::1]) by mx.google.com with ESMTPS id b7si6453681pge.727.2017.08.31.06.08.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 31 Aug 2017 06:08:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=E8bczuc/; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id AF38321EB529D; Thu, 31 Aug 2017 06:05:59 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received: from mail-wm0-x22a.google.com (mail-wm0-x22a.google.com [IPv6:2a00:1450:400c:c09::22a]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 570F621EB529B for ; Thu, 31 Aug 2017 06:05:58 -0700 (PDT) Received: by mail-wm0-x22a.google.com with SMTP id v2so4507104wmf.0 for ; Thu, 31 Aug 2017 06:08:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=sOpO9EmG8qTqsE7+miruXtj8DT3wH5zN2mGDgyOGSrY=; b=E8bczuc/VK29k6U7AmMOH0YPmo0FI5ETFRyOG+PmosmxPohD+keQvSITI0WF5v9zng 3kW9hpy+OzZ8XGeW7T+SMoZUirAdFiogtKSRqxQcoQjY02WOjht1M5Cx+4/oDvwkSo2H 9uO4CQTRHcYV5pOAAAT6r/OOHuFbLcFZsE4zk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=sOpO9EmG8qTqsE7+miruXtj8DT3wH5zN2mGDgyOGSrY=; b=JfO3f7/eLmqZpXP+qt77iUTLEVcyrdSabhnTuB7L8darTAyH8NYG+qpzTnMxI5vHDC uolmCPN5qKuElM95VdrBJzy6zaQrHoG2YDKAjz2UsoteRGmi5ZRec6dxXCcn2sPBbNJG S4rywqG1VqG7N92mzT17XtFDYTK99pRNI1D7MgR2U+tDLWj4UrRLJe+Mer4TpnSJ+VjW 4YDzZrqo7eBVhoxi7QPUWg39ZR+vceJ5onwrK7Tb+M+Yd1H4F7knHrYFHkCcSeO297Th z6R5irDSjF/ycP3ihzdwWOKf2nQ4zXn5qBCPfts9Np2x+X4p7OUjF2xKW4ziS8Bd1J/1 tn4A== X-Gm-Message-State: AHPjjUgE+SwRqqkt7BAYFKxf97e8CNYiY80oePk4HsOdI9RduRbvqGzJ yA/YbgEugcA3s2usV8sTTQ== X-Received: by 10.28.153.202 with SMTP id b193mr470382wme.117.1504184919625; Thu, 31 Aug 2017 06:08:39 -0700 (PDT) Received: from localhost.localdomain ([154.144.95.132]) by smtp.gmail.com with ESMTPSA id u38sm5571203wrb.12.2017.08.31.06.08.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 31 Aug 2017 06:08:38 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Thu, 31 Aug 2017 14:08:27 +0100 Message-Id: <20170831130830.12833-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170831130830.12833-1-ard.biesheuvel@linaro.org> References: <20170831130830.12833-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms v2 1/4] Platform/OverdriveBoard: move device tree compilation into build X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alan@softiron.com, Ard Biesheuvel , liming.gao@intel.com, leif.lindholm@linaro.org MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Use the proposed BaseTools support for device tree compilation to build the device tree binary from source at build time. Give it its own .inf and a build rule so the tools take care of everything. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Platform/AMD/OverdriveBoard/FdtBlob/styx-overdrive.dtb | Bin 9357 -> 0 bytes Platform/AMD/OverdriveBoard/OverdriveBoard.dsc | 1 + Platform/AMD/OverdriveBoard/OverdriveBoard.fdf | 9 ++++--- Platform/AMD/OverdriveBoard/{FdtBlob/styx-overdrive.dts => OverdriveBoardDeviceTree/OverdriveBoardDeviceTree.dts} | 0 Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoardDeviceTree.inf | 28 ++++++++++++++++++++ 5 files changed, 34 insertions(+), 4 deletions(-) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/AMD/OverdriveBoard/FdtBlob/styx-overdrive.dtb b/Platform/AMD/OverdriveBoard/FdtBlob/styx-overdrive.dtb deleted file mode 100644 index c8e5fd980bce305186214aab10a7d399faa22500..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 9357 zcmdT~O>7-k6`rw)A*6q4AOZx68>b{vrSMPo6pFwcq`#}(#4}ym-;d%e>`K#U!qCFXYpJ__@2FbM7^7V1BMQld1p?MBm$Ds5ad}xfF@t2T|YT2sY7j8RrH{5Pg!KMhmsiH-m1D>f)@g2B zC)A(B#<;AXkD6N65u@he-XM6Je%P=3JpPc!zt`~+r^>r970j>+rm8eAG81*zDyl_K zf5%a1ulRL-Q6>>8dFK8Flok<=P?%(^n0fiil_g0n+i)DGmeWnsi;`@ZtkO{9yhs70 z@~;m3dt2rE!CZ@b**ttMS*NVB`Gao$u?55tm9*bioTJYidIe1x7kLb>B}u_BzE8;? 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All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = OverdriveBoardDeviceTree + FILE_GUID = 25462CDA-221F-47DF-AC1D-259CFAA4E326 # gDtPlatformDefaultDtbFileGuid + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + +[Sources] + OverdriveBoardDeviceTree.dts + +[Packages] + MdePkg/MdePkg.dec From patchwork Thu Aug 31 13:08:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 111388 Delivered-To: patch@linaro.org Received: by 10.140.95.112 with SMTP id h103csp2521338qge; Thu, 31 Aug 2017 06:08:47 -0700 (PDT) X-Google-Smtp-Source: ADKCNb7MKTmgUTTxosGkANrLNvi8pFUUbBnrGg4K/kMz8o8UtlxO8f0c9kCn/5Lwz1vEa9AuqCXK X-Received: by 10.99.44.69 with SMTP id s66mr2267325pgs.255.1504184927644; Thu, 31 Aug 2017 06:08:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504184927; cv=none; d=google.com; s=arc-20160816; b=QHRaxJ8DbYHfhiiu/S/f7L5cOK5al2f0eDu0V7qUKR0p1wmH9aIGcR/MVEgNNuW08S wKhE+jd38zsBjmODErWKeFi16+c8w7L2paysGBYH8LntpS2dIVv3+OFErdLwadkzGitV bsKGJ3KW86HEjXGunKJm4iwd11+7m8mtuIj6DbkpfiUd4jIk9azjO7m59d3dZBhOZpea hH/Fp0Nm/GloXRB8bZnrjsjPcywMjS5Kl2JUFrXAVFU6oHYUwu0phDfZwDSAjIlMY2ij xhnipzCg6lPLcfwyiztWx/21C9wkS1L3reFE+ZvOAXXCiB1nOwghM4rNEPWyuhHCNdqH 7EIw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=fCU3RO0x9/4jUbAh6kmqvxr5U8CTm9qFs2yd0h0WlSc=; b=z5sKutWi91KNLj9UwhBiN0xLgMdn2siXKAzoMDi7dGTlWRswtRZmnSkoQ7qxz1BfGq rQrLulgBOcFKGcqLaggR1Ba6X4z520cjZWn/D0tfmeMk8kBisbLgtCVAxMM37RMTSNG9 96uXOw9uxY5fWUsfO9uOhXD+5uGnog5zQz7ybyXW+V8QS67ts1u4t7T5tfX6/XeJvcz1 r/b1DtOBVLYPQxWIHCPo9zoRovAT4BpZTXR0efEM2mMGnjiggQ+b8EUaCFvxkOJfIW6G ak4+rH2uDgOdX39mKeJret3TXcv3KBS1e1qDVr6m6OUinEdh3cTC4hJH1cdmnRT7uPTo YkxQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=koPu3DPZ; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [2001:19d0:306:5::1]) by mx.google.com with ESMTPS id 3si6518140plv.356.2017.08.31.06.08.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 31 Aug 2017 06:08:47 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=koPu3DPZ; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id EC88F21EB529B; Thu, 31 Aug 2017 06:06:01 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received: from mail-wm0-x230.google.com (mail-wm0-x230.google.com [IPv6:2a00:1450:400c:c09::230]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id E362F21EB529F for ; Thu, 31 Aug 2017 06:06:00 -0700 (PDT) Received: by mail-wm0-x230.google.com with SMTP id u26so4174803wma.0 for ; Thu, 31 Aug 2017 06:08:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Tbe8mZLAxAbzLmQN0oQvyXwe7xLwIk6DMc3Y9Rq466g=; b=koPu3DPZfADOkIOQgxb5OrfX6zaweLTVYhZbHLEAw3PUTcBdolMWKJ7UsrkbAd73g6 Ci1Hqcf1iMrHZAKyjhxzumYuqXUcOdsckhUPCuI9nXPEyO8J0/V7WiavYMo/0Nz7R4yt 8qn6Wfgdl3uk2QFYLWyTREZLwpl+8+VaJojs4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Tbe8mZLAxAbzLmQN0oQvyXwe7xLwIk6DMc3Y9Rq466g=; b=guRZXdBFXDF+Wd2CCy229puMepR1QNhQaPxsvER884+drADrE0HoiBUyfwSSc83xPq f01wpoD6qtvLkqE1Qzk8ITUhjAhwgqCU1rrRutMhfdoytQUcFQGMKLi32OHXIYK7cl8J A1oDnY83Mjjol/lGdSsle9xWe9rYgOYsJRqjWKc6rCuxJUE6Abzt5+UgIYlYq0lYpjG6 PYfsE1adOMUNciGyx7I8CxglCs/DhTY6Cp9AMqnRkKySRiVinJ7TMPIt33OjAE+91/vh RvLZRGACB1237tuk8gNxz9s99KcoAunoRjx8vqTzqzHidyGLzMGLfIJRsjPMeFk5rB4f iOrQ== X-Gm-Message-State: AHPjjUhQIyXjNsBCbbwsoojBEJCpe7d3iRHevjACHXyYk+tJkMPbna06 wOrO2ybloSEngcGDl1Hfig== X-Received: by 10.28.70.69 with SMTP id t66mr470955wma.123.1504184922226; Thu, 31 Aug 2017 06:08:42 -0700 (PDT) Received: from localhost.localdomain ([154.144.95.132]) by smtp.gmail.com with ESMTPSA id u38sm5571203wrb.12.2017.08.31.06.08.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 31 Aug 2017 06:08:41 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Thu, 31 Aug 2017 14:08:28 +0100 Message-Id: <20170831130830.12833-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170831130830.12833-1-ard.biesheuvel@linaro.org> References: <20170831130830.12833-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms v2 2/4] Platform/OverdriveBoard: clean up device tree source file X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alan@softiron.com, Ard Biesheuvel , liming.gao@intel.com, leif.lindholm@linaro.org MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Clean up the device tree source file, by switching to Tianocore conventions for line endings and whitespace etc, and by replacing open coded values with symbol constants and/or phandle references. The resulting .dtb will likely not be identical at the bit level, but the modifications are cosmetic only. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoardDeviceTree.dts | 957 ++++++++++---------- 1 file changed, 467 insertions(+), 490 deletions(-) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoardDeviceTree.dts b/Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoardDeviceTree.dts index 4039f666004a..81477fe43cdd 100644 --- a/Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoardDeviceTree.dts +++ b/Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoardDeviceTree.dts @@ -2,6 +2,7 @@ * DTS file for AMD Seattle (Rev.B) Overdrive Development Board * * Copyright 2015 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * Copyright 2015 - 2017 Linaro, Ltd. All Rights Reserved. * * This program and the accompanying materials are licensed and made available * under the terms and conditions of the BSD License which accompanies this @@ -14,497 +15,473 @@ * */ +#define GIC_SPI 0 +#define GIC_PPI 1 + +#define IRQ_TYPE_NONE 0 +#define IRQ_TYPE_EDGE_RISING 1 +#define IRQ_TYPE_EDGE_FALLING 2 +#define IRQ_TYPE_LEVEL_HIGH 4 +#define IRQ_TYPE_LEVEL_LOW 8 + +#define GIC_CPU_MASK(num) (((1 << (num)) - 1) << 8) + /dts-v1/; / { - model = "AMD Seattle (Rev.B) Development Board (Overdrive)"; - compatible = "amd,seattle-overdrive", "amd,seattle"; - interrupt-parent = <0x1>; - #address-cells = <0x2>; - #size-cells = <0x2>; - - interrupt-controller@e1101000 { - compatible = "arm,gic-400", "arm,cortex-a15-gic"; - interrupt-controller; - #interrupt-cells = <0x3>; - #address-cells = <0x2>; - #size-cells = <0x2>; - reg = <0x0 0xe1110000 0x0 0x1000>, - <0x0 0xe112f000 0x0 0x2000>, - <0x0 0xe1140000 0x0 0x2000>, - <0x0 0xe1160000 0x0 0x2000>; - interrupts = <0x1 0x9 0xf04>; - ranges = <0x0 0x0 0x0 0xe1100000 0x0 0x100000>; - linux,phandle = <0x1>; - phandle = <0x1>; - - v2m@e0080000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x0 0x80000 0x0 0x1000>; - linux,phandle = <0x4>; - phandle = <0x4>; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <0x1 0xd 0xff04>, - <0x1 0xe 0xff04>, - <0x1 0xb 0xff04>, - <0x1 0xa 0xff04>; - }; - - smb { - compatible = "simple-bus"; - #address-cells = <0x2>; - #size-cells = <0x2>; - ranges; - /* - * dma-ranges is 40-bit address space containing: - * - GICv2m MSI register is at 0xe0080000 - * - DRAM range [0x8000000000 to 0xffffffffff] - */ - dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; - - clk100mhz_0 { - compatible = "fixed-clock"; - #clock-cells = <0x0>; - clock-frequency = <100000000>; - clock-output-names = "adl3clk_100mhz"; - }; - - clk375mhz { - compatible = "fixed-clock"; - #clock-cells = <0x0>; - clock-frequency = <375000000>; - clock-output-names = "ccpclk_375mhz"; - }; - - clk333mhz { - compatible = "fixed-clock"; - #clock-cells = <0x0>; - clock-frequency = <333000000>; - clock-output-names = "sataclk_333mhz"; - linux,phandle = <0x2>; - phandle = <0x2>; - }; - - clk500mhz_0 { - compatible = "fixed-clock"; - #clock-cells = <0x0>; - clock-frequency = <500000000>; - clock-output-names = "pcieclk_500mhz"; - }; - - clk500mhz_1 { - compatible = "fixed-clock"; - #clock-cells = <0x0>; - clock-frequency = <500000000>; - clock-output-names = "dmaclk_500mhz"; - }; - - clk250mhz_4 { - compatible = "fixed-clock"; - #clock-cells = <0x0>; - clock-frequency = <250000000>; - clock-output-names = "miscclk_250mhz"; - linux,phandle = <0xd>; - phandle = <0xd>; - }; - - clk100mhz_1 { - compatible = "fixed-clock"; - #clock-cells = <0x0>; - clock-frequency = <100000000>; - clock-output-names = "uartspiclk_100mhz"; - linux,phandle = <0x3>; - phandle = <0x3>; - }; - - sata0_smmu: smmu@e0200000 { - compatible = "arm,mmu-401"; - reg = <0 0xe0200000 0 0x10000>; - #global-interrupts = <1>; - interrupts = /* Uses combined intr for both - * global and context - */ - <0 332 4>, - <0 332 4>; - #iommu-cells = <2>; - dma-coherent; - }; - - sata1_smmu: smmu@e0c00000 { - compatible = "arm,mmu-401"; - reg = <0 0xe0c00000 0 0x10000>; - #global-interrupts = <1>; - interrupts = /* Uses combined intr for both - * global and context - */ - <0 331 4>, - <0 331 4>; - #iommu-cells = <2>; - dma-coherent; - }; - - sata@e0300000 { - compatible = "snps,dwc-ahci"; - reg = <0x0 0xe0300000 0x0 0xf0000>; - interrupts = <0x0 0x163 0x4>; - clocks = <0x2>; - dma-coherent; - iommus = <&sata0_smmu 0x00 0x1f>; /* 0-31 */ - }; - - sata@e0d00000 { - status = "disabled"; - compatible = "snps,dwc-ahci"; - reg = <0x0 0xe0d00000 0x0 0xf0000>; - interrupts = <0x0 0x162 0x4>; - clocks = <0x2>; - dma-coherent; - iommus = <&sata1_smmu 0x00 0x1f>; /* 0-31 */ - }; - - i2c@e1000000 { - compatible = "snps,designware-i2c"; - reg = <0x0 0xe1000000 0x0 0x1000>; - interrupts = <0x0 0x165 0x4>; - clocks = <0xd>; - }; - - i2c@e0050000 { - compatible = "snps,designware-i2c"; - reg = <0x0 0xe0050000 0x0 0x1000>; - interrupts = <0x0 0x154 0x4>; - clocks = <0xd>; - }; - - serial@e1010000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xe1010000 0x0 0x1000>; - interrupts = <0x0 0x148 0x4>; - clocks = <0x3 0x3>; - clock-names = "uartclk", "apb_pclk"; - }; - - ssp@e1020000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x0 0xe1020000 0x0 0x1000>; - spi-controller; - interrupts = <0x0 0x14a 0x4>; - clocks = <0x3>; - clock-names = "apb_pclk"; - }; - - ssp@e1030000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x0 0xe1030000 0x0 0x1000>; - spi-controller; - interrupts = <0x0 0x149 0x4>; - clocks = <0x3>; - clock-names = "apb_pclk"; - num-cs = <0x1>; - #address-cells = <0x1>; - #size-cells = <0x0>; - - sdcard@0 { - compatible = "mmc-spi-slot"; - reg = <0x0>; - spi-max-frequency = <20000000>; - voltage-ranges = <3200 3400>; - pl022,hierarchy = <0x0>; - pl022,interface = <0x0>; - pl022,com-mode = <0x0>; - pl022,rx-level-trig = <0x0>; - pl022,tx-level-trig = <0x0>; - }; - }; - - gpio@e1050000 { /* [0 : 7] */ - compatible = "arm,pl061", "arm,primecell"; - #gpio-cells = <0x2>; - reg = <0x0 0xe1050000 0x0 0x1000>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <0x2>; - interrupts = <0x0 0x166 0x4>; - clocks = <0x3>; - clock-names = "apb_pclk"; - }; - - gpio@e0020000 { /* [8 : 15] */ - status = "disabled"; - compatible = "arm,pl061", "arm,primecell"; - #gpio-cells = <0x2>; - reg = <0x0 0xe0020000 0x0 0x1000>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <0x2>; - interrupts = <0x0 0x16e 0x4>; - clocks = <0x3>; - clock-names = "apb_pclk"; - }; - - gpio@e0030000 { /* [16 : 23] */ - status = "disabled"; - compatible = "arm,pl061", "arm,primecell"; - #gpio-cells = <0x2>; - reg = <0x0 0xe0030000 0x0 0x1000>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <0x2>; - interrupts = <0x0 0x16d 0x4>; - clocks = <0x3>; - clock-names = "apb_pclk"; - }; - - gpio@e0080000 { /* [24] */ - compatible = "arm,pl061", "arm,primecell"; - #gpio-cells = <0x2>; - reg = <0x0 0xe0080000 0x0 0x1000>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <0x2>; - interrupts = <0x0 0x169 0x4>; - clocks = <0x3>; - clock-names = "apb_pclk"; - }; - - ccp: ccp@e0100000 { - compatible = "amd,ccp-seattle-v1a"; - reg = <0x0 0xe0100000 0x0 0x10000>; - interrupts = <0x0 0x3 0x4>; - dma-coherent; - amd,zlib-support = <0x1>; - }; - - pcie: pcie@f0000000 { - compatible = "pci-host-ecam-generic"; - #address-cells = <0x3>; - #size-cells = <0x2>; - #interrupt-cells = <0x1>; - iommu-map = <0x0 &pcie_smmu 0x0 0x10000>; - device_type = "pci"; - bus-range = <0x0 0x7f>; - msi-parent = <0x4>; - reg = <0x0 0xf0000000 0x0 0x10000000>; - interrupt-map-mask = <0xff00 0x0 0x0 0x7>; - interrupt-map = <0x1100 0x0 0x0 0x1 0x1 0x0 0x0 0x0 0x120 0x1>, - <0x1100 0x0 0x0 0x2 0x1 0x0 0x0 0x0 0x121 0x1>, - <0x1100 0x0 0x0 0x3 0x1 0x0 0x0 0x0 0x122 0x1>, - <0x1100 0x0 0x0 0x4 0x1 0x0 0x0 0x0 0x123 0x1>, - - <0x1200 0x0 0x0 0x1 0x1 0x0 0x0 0x0 0x124 0x1>, - <0x1200 0x0 0x0 0x2 0x1 0x0 0x0 0x0 0x125 0x1>, - <0x1200 0x0 0x0 0x3 0x1 0x0 0x0 0x0 0x126 0x1>, - <0x1200 0x0 0x0 0x4 0x1 0x0 0x0 0x0 0x127 0x1>, - - <0x1300 0x0 0x0 0x1 0x1 0x0 0x0 0x0 0x128 0x1>, - <0x1300 0x0 0x0 0x2 0x1 0x0 0x0 0x0 0x129 0x1>, - <0x1300 0x0 0x0 0x3 0x1 0x0 0x0 0x0 0x12a 0x1>, - <0x1300 0x0 0x0 0x4 0x1 0x0 0x0 0x0 0x12b 0x1>; - dma-coherent; - dma-ranges = <0x43000000 0x0 0x0 0x0 0x0 0x100 0x0>; - ranges = <0x1000000 0x0 0x00000000 0x0 0xefff0000 0x00 0x00010000>, /* I/O Memory (size=64K) */ - <0x2000000 0x0 0x40000000 0x0 0x40000000 0x00 0x80000000>, /* 32-bit MMIO (size=2G) */ - <0x3000000 0x1 0x00000000 0x1 0x00000000 0x7f 0x00000000>; /* 64-bit MMIO (size= 124G) */ - }; - - pcie_smmu: smmu@e0a00000 { - compatible = "arm,mmu-401"; - reg = <0 0xe0a00000 0 0x10000>; - #global-interrupts = <1>; - interrupts = /* Uses combined intr for both - * global and context - */ - <0 333 4>, - <0 333 4>; - #iommu-cells = <1>; - dma-coherent; - }; - - ccn@0xe8000000 { - compatible = "arm,ccn-504"; - reg = <0x0 0xe8000000 0x0 0x1000000>; - interrupts = <0x0 0x17c 0x4>; - }; - - gwdt@e0bb0000 { - status = "disabled"; - compatible = "arm,sbsa-gwdt"; - reg = <0x0 0xe0bb0000 0x0 0x10000 - 0x0 0xe0bc0000 0x0 0x10000>; - reg-names = "refresh", "control"; - interrupts = <0x0 0x151 0x4>; - interrupt-names = "ws0"; - }; - - kcs@e0010000 { - status = "disabled"; - compatible = "ipmi-kcs"; - device_type = "ipmi"; - reg = <0x0 0xe0010000 0 0x8>; - interrupts = <0 389 4>; - interrupt-names = "ipmi_kcs"; - reg-size = <1>; - reg-spacing = <4>; - }; - - clk250mhz_0 { - compatible = "fixed-clock"; - #clock-cells = <0x0>; - clock-frequency = <250000000>; - clock-output-names = "xgmacclk0_dma_250mhz"; - linux,phandle = <0x5>; - phandle = <0x5>; - }; - - clk250mhz_1 { - compatible = "fixed-clock"; - #clock-cells = <0x0>; - clock-frequency = <250000000>; - clock-output-names = "xgmacclk0_ptp_250mhz"; - linux,phandle = <0x6>; - phandle = <0x6>; - }; - - clk250mhz_2 { - compatible = "fixed-clock"; - #clock-cells = <0x0>; - clock-frequency = <250000000>; - clock-output-names = "xgmacclk1_dma_250mhz"; - linux,phandle = <0x7>; - phandle = <0x7>; - }; - - clk250mhz_3 { - compatible = "fixed-clock"; - #clock-cells = <0x0>; - clock-frequency = <250000000>; - clock-output-names = "xgmacclk1_ptp_250mhz"; - linux,phandle = <0x8>; - phandle = <0x8>; - }; - - phy@e1240800 { - status = "disabled"; - compatible = "amd,xgbe-phy-seattle-v1a"; - reg = <0x0 0xe1240800 0x0 0x0400>, /* SERDES RX/TX0 */ - <0x0 0xe1250000 0x0 0x0060>, /* SERDES IR 1/2 */ - <0x0 0xe12500f8 0x0 0x0004>; /* SERDES IR 2/2 */ - interrupts = <0x0 0x143 0x4>; - amd,speed-set = <0x0>; - amd,serdes-blwc = <0x1 0x1 0x0>; - amd,serdes-cdr-rate = <0x2 0x2 0x7>; - amd,serdes-pq-skew = <0xa 0xa 0x12>; - amd,serdes-tx-amp = <0xf 0xf 0xa>; - amd,serdes-dfe-tap-config = <0x3 0x3 0x1>; - amd,serdes-dfe-tap-enable = <0x0 0x0 0x7f>; - linux,phandle = <0x9>; - phandle = <0x9>; - }; - - phy@e1240c00 { - status = "disabled"; - compatible = "amd,xgbe-phy-seattle-v1a"; - reg = <0x0 0xe1240c00 0x0 0x0400>, /* SERDES RX/TX0 */ - <0x0 0xe1250080 0x0 0x0060>, /* SERDES IR 1/2 */ - <0x0 0xe12500fc 0x0 0x0004>; /* SERDES IR 2/2 */ - interrupts = <0x0 0x142 0x4>; - amd,speed-set = <0x0>; - amd,serdes-blwc = <0x1 0x1 0x0>; - amd,serdes-cdr-rate = <0x2 0x2 0x7>; - amd,serdes-pq-skew = <0xa 0xa 0x12>; - amd,serdes-tx-amp = <0xf 0xf 0xa>; - amd,serdes-dfe-tap-config = <0x3 0x3 0x1>; - amd,serdes-dfe-tap-enable = <0x0 0x0 0x7f>; - linux,phandle = <0xa>; - phandle = <0xa>; - }; - - xgmac0_smmu: smmu@e0600000 { - compatible = "arm,mmu-401"; - reg = <0 0xe0600000 0 0x10000>; - #global-interrupts = <1>; - interrupts = /* Uses combined intr for both - * global and context - */ - <0 336 4>, - <0 336 4>; - #iommu-cells = <2>; - dma-coherent; - }; - - xgmac1_smmu: smmu@e0800000 { - compatible = "arm,mmu-401"; - reg = <0 0xe0800000 0 0x10000>; - #global-interrupts = <1>; - interrupts = /* Uses combined intr for both - * global and context - */ - <0 335 4>, - <0 335 4>; - #iommu-cells = <2>; - dma-coherent; - }; - - xgmac@e0700000 { - status = "disabled"; - compatible = "amd,xgbe-seattle-v1a"; - reg = <0x0 0xe0700000 0x0 0x80000 0x0 0xe0780000 0x0 0x80000>; - interrupts = <0x0 0x145 0x4>, - <0x0 0x15a 0x1>, - <0x0 0x15b 0x1>, - <0x0 0x15c 0x1>, - <0x0 0x15d 0x1>; - amd,per-channel-interrupt; - mac-address = [02 a1 a2 a3 a4 a5]; - clocks = <0x5 0x6>; - clock-names = "dma_clk", "ptp_clk"; - phy-handle = <0x9>; - phy-mode = "xgmii"; - dma-coherent; - iommus = <&xgmac0_smmu 0x00 0x1f>; /* 0-31 */ - linux,phandle = <0xb>; - phandle = <0xb>; - }; - - xgmac@e0900000 { - status = "disabled"; - compatible = "amd,xgbe-seattle-v1a"; - reg = <0x0 0xe0900000 0x0 0x80000 0x0 0xe0980000 0x0 0x80000>; - interrupts = <0x0 0x144 0x4>, - <0x0 0x155 0x1>, - <0x0 0x156 0x1>, - <0x0 0x157 0x1>, - <0x0 0x158 0x1>; - amd,per-channel-interrupt; - mac-address = [02 b1 b2 b3 b4 b5]; - clocks = <0x7 0x8>; - clock-names = "dma_clk", "ptp_clk"; - phy-handle = <0xa>; - phy-mode = "xgmii"; - dma-coherent; - iommus = <&xgmac1_smmu 0x00 0x1f>; /* 0-31 */ - linux,phandle = <0xc>; - phandle = <0xc>; - }; - }; - - chosen { - stdout-path = "/smb/serial@e1010000"; - /* Note: - * Linux support for pci-probe-only DT is not - * stable. Disable this for now and let Linux - * take care of the resource assignment. - */ - // linux,pci-probe-only; - }; - - psci { - compatible = "arm,psci-0.2", "arm,psci"; - method = "smc"; - }; + model = "AMD Seattle (Rev.B) Development Board (Overdrive)"; + compatible = "amd,seattle-overdrive", "amd,seattle"; + interrupt-parent = <&gic>; + #address-cells = <0x2>; + #size-cells = <0x2>; + + gic: interrupt-controller@e1101000 { + compatible = "arm,gic-400", "arm,cortex-a15-gic"; + interrupt-controller; + #interrupt-cells = <0x3>; + #address-cells = <0x2>; + #size-cells = <0x2>; + reg = <0x0 0xe1110000 0x0 0x1000>, + <0x0 0xe112f000 0x0 0x2000>, + <0x0 0xe1140000 0x0 0x2000>, + <0x0 0xe1160000 0x0 0x2000>; + interrupts = ; + ranges = <0x0 0x0 0x0 0xe1100000 0x0 0x100000>; + + msi: v2m@e0080000 { + compatible = "arm,gic-v2m-frame"; + reg = <0x0 0x80000 0x0 0x1000>; + msi-controller; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + smb { + compatible = "simple-bus"; + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + /* + * dma-ranges is 40-bit address space containing: + * - GICv2m MSI register is at 0xe0080000 + * - DRAM range [0x8000000000 to 0xffffffffff] + */ + dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; + + adl3clk: clk100mhz_0 { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <100000000>; + clock-output-names = "adl3clk_100mhz"; + }; + + ccpclk: clk375mhz { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <375000000>; + clock-output-names = "ccpclk_375mhz"; + }; + + sataclk: clk333mhz { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <333000000>; + clock-output-names = "sataclk_333mhz"; + }; + + pcieclk: clk500mhz_0 { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <500000000>; + clock-output-names = "pcieclk_500mhz"; + }; + + dmaclk: clk500mhz_1 { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <500000000>; + clock-output-names = "dmaclk_500mhz"; + }; + + miscclk: clk250mhz_4 { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <250000000>; + clock-output-names = "miscclk_250mhz"; + }; + + uartspiclk: clk100mhz_1 { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <100000000>; + clock-output-names = "uartspiclk_100mhz"; + }; + + sata0_smmu: smmu@e0200000 { + compatible = "arm,mmu-401"; + reg = <0 0xe0200000 0 0x10000>; + + /* Uses combined intr for both global and context */ + #global-interrupts = <1>; + interrupts = , + ; + #iommu-cells = <2>; + dma-coherent; + }; + + sata1_smmu: smmu@e0c00000 { + compatible = "arm,mmu-401"; + reg = <0 0xe0c00000 0 0x10000>; + + /* Uses combined intr for both global and context */ + #global-interrupts = <1>; + interrupts = , + ; + #iommu-cells = <2>; + dma-coherent; + }; + + sata@e0300000 { + compatible = "snps,dwc-ahci"; + reg = <0x0 0xe0300000 0x0 0xf0000>; + interrupts = ; + clocks = <&sataclk>; + dma-coherent; + iommus = <&sata0_smmu 0x00 0x1f>; /* 0-31 */ + }; + + sata@e0d00000 { + status = "disabled"; + compatible = "snps,dwc-ahci"; + reg = <0x0 0xe0d00000 0x0 0xf0000>; + interrupts = ; + clocks = <&sataclk>; + dma-coherent; + iommus = <&sata1_smmu 0x00 0x1f>; /* 0-31 */ + }; + + i2c@e1000000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xe1000000 0x0 0x1000>; + interrupts = ; + clocks = <&miscclk>; + }; + + i2c@e0050000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xe0050000 0x0 0x1000>; + interrupts = ; + clocks = <&miscclk>; + }; + + serial@e1010000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xe1010000 0x0 0x1000>; + interrupts = ; + clocks = <&uartspiclk &uartspiclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + ssp@e1020000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0xe1020000 0x0 0x1000>; + spi-controller; + interrupts = ; + clocks = <&uartspiclk>; + clock-names = "apb_pclk"; + }; + + ssp@e1030000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0xe1030000 0x0 0x1000>; + spi-controller; + interrupts = ; + clocks = <&uartspiclk>; + clock-names = "apb_pclk"; + num-cs = <0x1>; + #address-cells = <0x1>; + #size-cells = <0x0>; + + sdcard@0 { + compatible = "mmc-spi-slot"; + reg = <0x0>; + spi-max-frequency = <20000000>; + voltage-ranges = <3200 3400>; + pl022,hierarchy = <0x0>; + pl022,interface = <0x0>; + pl022,com-mode = <0x0>; + pl022,rx-level-trig = <0x0>; + pl022,tx-level-trig = <0x0>; + }; + }; + + gpio@e1050000 { /* [0 : 7] */ + compatible = "arm,pl061", "arm,primecell"; + #gpio-cells = <0x2>; + reg = <0x0 0xe1050000 0x0 0x1000>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <0x2>; + interrupts = ; + clocks = <&uartspiclk>; + clock-names = "apb_pclk"; + }; + + gpio@e0020000 { /* [8 : 15] */ + status = "disabled"; + compatible = "arm,pl061", "arm,primecell"; + #gpio-cells = <0x2>; + reg = <0x0 0xe0020000 0x0 0x1000>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <0x2>; + interrupts = ; + clocks = <&uartspiclk>; + clock-names = "apb_pclk"; + }; + + gpio@e0030000 { /* [16 : 23] */ + status = "disabled"; + compatible = "arm,pl061", "arm,primecell"; + #gpio-cells = <0x2>; + reg = <0x0 0xe0030000 0x0 0x1000>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <0x2>; + interrupts = ; + clocks = <&uartspiclk>; + clock-names = "apb_pclk"; + }; + + gpio@e0080000 { /* [24] */ + compatible = "arm,pl061", "arm,primecell"; + #gpio-cells = <0x2>; + reg = <0x0 0xe0080000 0x0 0x1000>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <0x2>; + interrupts = ; + clocks = <&uartspiclk>; + clock-names = "apb_pclk"; + }; + + ccp: ccp@e0100000 { + compatible = "amd,ccp-seattle-v1a"; + reg = <0x0 0xe0100000 0x0 0x10000>; + interrupts = ; + dma-coherent; + amd,zlib-support = <0x1>; + }; + + pcie: pcie@f0000000 { + compatible = "pci-host-ecam-generic"; + #address-cells = <0x3>; + #size-cells = <0x2>; + #interrupt-cells = <0x1>; + iommu-map = <0x0 &pcie_smmu 0x0 0x10000>; + device_type = "pci"; + bus-range = <0x0 0x7f>; + msi-parent = <&msi>; + reg = <0x0 0xf0000000 0x0 0x10000000>; + interrupt-map-mask = <0xff00 0x0 0x0 0x7>; + interrupt-map = <0x1100 0x0 0x0 0x1 &gic 0x0 0x0 GIC_SPI 0x120 IRQ_TYPE_EDGE_RISING>, + <0x1100 0x0 0x0 0x2 &gic 0x0 0x0 GIC_SPI 0x121 IRQ_TYPE_EDGE_RISING>, + <0x1100 0x0 0x0 0x3 &gic 0x0 0x0 GIC_SPI 0x122 IRQ_TYPE_EDGE_RISING>, + <0x1100 0x0 0x0 0x4 &gic 0x0 0x0 GIC_SPI 0x123 IRQ_TYPE_EDGE_RISING>, + + <0x1200 0x0 0x0 0x1 &gic 0x0 0x0 GIC_SPI 0x124 IRQ_TYPE_EDGE_RISING>, + <0x1200 0x0 0x0 0x2 &gic 0x0 0x0 GIC_SPI 0x125 IRQ_TYPE_EDGE_RISING>, + <0x1200 0x0 0x0 0x3 &gic 0x0 0x0 GIC_SPI 0x126 IRQ_TYPE_EDGE_RISING>, + <0x1200 0x0 0x0 0x4 &gic 0x0 0x0 GIC_SPI 0x127 IRQ_TYPE_EDGE_RISING>, + + <0x1300 0x0 0x0 0x1 &gic 0x0 0x0 GIC_SPI 0x128 IRQ_TYPE_EDGE_RISING>, + <0x1300 0x0 0x0 0x2 &gic 0x0 0x0 GIC_SPI 0x129 IRQ_TYPE_EDGE_RISING>, + <0x1300 0x0 0x0 0x3 &gic 0x0 0x0 GIC_SPI 0x12a IRQ_TYPE_EDGE_RISING>, + <0x1300 0x0 0x0 0x4 &gic 0x0 0x0 GIC_SPI 0x12b IRQ_TYPE_EDGE_RISING>; + dma-coherent; + dma-ranges = <0x43000000 0x0 0x0 0x0 0x0 0x100 0x0>; + ranges = <0x1000000 0x0 0x00000000 0x0 0xefff0000 0x00 0x00010000>, /* I/O Memory (size=64K) */ + <0x2000000 0x0 0x40000000 0x0 0x40000000 0x00 0x80000000>, /* 32-bit MMIO (size=2G) */ + <0x3000000 0x1 0x00000000 0x1 0x00000000 0x7f 0x00000000>; /* 64-bit MMIO (size= 124G) */ + }; + + pcie_smmu: smmu@e0a00000 { + compatible = "arm,mmu-401"; + reg = <0 0xe0a00000 0 0x10000>; + + /* Uses combined intr for both global and context */ + #global-interrupts = <1>; + interrupts = , + ; + #iommu-cells = <1>; + dma-coherent; + }; + + ccn@0xe8000000 { + compatible = "arm,ccn-504"; + reg = <0x0 0xe8000000 0x0 0x1000000>; + interrupts = ; + }; + + gwdt@e0bb0000 { + status = "disabled"; + compatible = "arm,sbsa-gwdt"; + reg = <0x0 0xe0bb0000 0x0 0x10000 + 0x0 0xe0bc0000 0x0 0x10000>; + reg-names = "refresh", "control"; + interrupts = ; + interrupt-names = "ws0"; + }; + + kcs@e0010000 { + status = "disabled"; + compatible = "ipmi-kcs"; + device_type = "ipmi"; + reg = <0x0 0xe0010000 0 0x8>; + interrupts = ; + interrupt-names = "ipmi_kcs"; + reg-size = <1>; + reg-spacing = <4>; + }; + + xgmacclk0_dma: clk250mhz_0 { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <250000000>; + clock-output-names = "xgmacclk0_dma_250mhz"; + }; + + xgmacclk0_ptp: clk250mhz_1 { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <250000000>; + clock-output-names = "xgmacclk0_ptp_250mhz"; + }; + + xgmacclk1_dma: clk250mhz_2 { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <250000000>; + clock-output-names = "xgmacclk1_dma_250mhz"; + }; + + xgmacclk1_ptp: clk250mhz_3 { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <250000000>; + clock-output-names = "xgmacclk1_ptp_250mhz"; + }; + + xgmac0_phy: phy@e1240800 { + compatible = "amd,xgbe-phy-seattle-v1a"; + reg = <0x0 0xe1240800 0x0 0x0400>, /* SERDES RX/TX0 */ + <0x0 0xe1250000 0x0 0x0060>, /* SERDES IR 1/2 */ + <0x0 0xe12500f8 0x0 0x0004>; /* SERDES IR 2/2 */ + interrupts = ; + amd,speed-set = <0x0>; + amd,serdes-blwc = <0x1 0x1 0x0>; + amd,serdes-cdr-rate = <0x2 0x2 0x7>; + amd,serdes-pq-skew = <0xa 0xa 0x12>; + amd,serdes-tx-amp = <0xf 0xf 0xa>; + amd,serdes-dfe-tap-config = <0x3 0x3 0x1>; + amd,serdes-dfe-tap-enable = <0x0 0x0 0x7f>; + status = "disabled"; + }; + + xgmac1_phy: phy@e1240c00 { + compatible = "amd,xgbe-phy-seattle-v1a"; + reg = <0x0 0xe1240c00 0x0 0x0400>, /* SERDES RX/TX0 */ + <0x0 0xe1250080 0x0 0x0060>, /* SERDES IR 1/2 */ + <0x0 0xe12500fc 0x0 0x0004>; /* SERDES IR 2/2 */ + interrupts = ; + amd,speed-set = <0x0>; + amd,serdes-blwc = <0x1 0x1 0x0>; + amd,serdes-cdr-rate = <0x2 0x2 0x7>; + amd,serdes-pq-skew = <0xa 0xa 0x12>; + amd,serdes-tx-amp = <0xf 0xf 0xa>; + amd,serdes-dfe-tap-config = <0x3 0x3 0x1>; + amd,serdes-dfe-tap-enable = <0x0 0x0 0x7f>; + status = "disabled"; + }; + + xgmac0_smmu: smmu@e0600000 { + compatible = "arm,mmu-401"; + reg = <0 0xe0600000 0 0x10000>; + + /* Uses combined intr for both global and context */ + #global-interrupts = <1>; + interrupts = , + ; + #iommu-cells = <2>; + dma-coherent; + }; + + xgmac1_smmu: smmu@e0800000 { + compatible = "arm,mmu-401"; + reg = <0 0xe0800000 0 0x10000>; + + /* Uses combined intr for both global and context */ + #global-interrupts = <1>; + interrupts = , + ; + #iommu-cells = <2>; + dma-coherent; + }; + + xgmac@e0700000 { + compatible = "amd,xgbe-seattle-v1a"; + reg = <0x0 0xe0700000 0x0 0x80000 0x0 0xe0780000 0x0 0x80000>; + interrupts = , + , + , + , + ; + amd,per-channel-interrupt; + mac-address = [02 a1 a2 a3 a4 a5]; + clocks = <&xgmacclk0_dma &xgmacclk0_ptp>; + clock-names = "dma_clk", "ptp_clk"; + phy-handle = <&xgmac0_phy>; + phy-mode = "xgmii"; + + iommus = <&xgmac0_smmu 0x00 0x1f>; /* 0-31 */ + dma-coherent; + status = "disabled"; + }; + + xgmac@e0900000 { + compatible = "amd,xgbe-seattle-v1a"; + reg = <0x0 0xe0900000 0x0 0x80000 0x0 0xe0980000 0x0 0x80000>; + interrupts = , + , + , + , + ; + amd,per-channel-interrupt; + mac-address = [02 b1 b2 b3 b4 b5]; + clocks = <&xgmacclk1_dma &xgmacclk1_ptp>; + clock-names = "dma_clk", "ptp_clk"; + phy-handle = <&xgmac1_phy>; + phy-mode = "xgmii"; + + iommus = <&xgmac1_smmu 0x00 0x1f>; /* 0-31 */ + dma-coherent; + status = "disabled"; + }; + }; + + chosen { + stdout-path = "/smb/serial@e1010000"; + }; + + psci { + compatible = "arm,psci-0.2", "arm,psci"; + method = "smc"; + }; }; From patchwork Thu Aug 31 13:08:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 111389 Delivered-To: patch@linaro.org Received: by 10.140.95.112 with SMTP id h103csp2521440qge; Thu, 31 Aug 2017 06:08:51 -0700 (PDT) X-Google-Smtp-Source: ADKCNb7E2EyW3qsAzlTW6Lw5MDS410YkqlqMF3uYPd43hp2yQDp4VDwBhl3w8ACYqK5EhkEI7r4+ X-Received: by 10.99.167.6 with SMTP id d6mr2283090pgf.383.1504184930976; Thu, 31 Aug 2017 06:08:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504184930; cv=none; d=google.com; s=arc-20160816; b=hqVzNpLgixFeMc8/gVRzc7K1WUcN2Xqq7EP9IQLR6j3pZHjzt+koykAvIqLpzLJxC8 NkjQujhZDAFYlpBTNQA4h2b0b2z46I4KWVWg9XOCSl1Di9tK9i7mO/KT8aOfbIq7f2+R BTKzlLdcZI+v0fzl2OOuoJ2yG9Cs0LnEapM34SmD0yqOQKv3CUqy9p1v3k2bCnX/tZxl 9XMpYJxORvmSeI3XRDSoV2d7RO4aQAPPJ2Mp9i2ETcPKzmLx9PuoSSviGNARNB1QIhy8 5Pq5BgtKypY4D/1HUKWdckz7hAEGq/pvsORGFrzp9I/XAeNV0OSH6V6yV9uIweotS9BM DwtA== ARC-Message-Signature: i=1; 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[2001:19d0:306:5::1]) by mx.google.com with ESMTPS id j10si6547885plg.5.2017.08.31.06.08.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 31 Aug 2017 06:08:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=i/rMDRJc; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 321412095BB64; Thu, 31 Aug 2017 06:06:05 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received: from mail-wm0-x234.google.com (mail-wm0-x234.google.com [IPv6:2a00:1450:400c:c09::234]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 7C5AA208F7AD6 for ; Thu, 31 Aug 2017 06:06:03 -0700 (PDT) Received: by mail-wm0-x234.google.com with SMTP id 187so4137171wmn.1 for ; Thu, 31 Aug 2017 06:08:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=MF0lroNQNzh7kEu/y9kDkInWrMAAfd7m8HgikGHgtdM=; b=i/rMDRJcCUqlomy9aUnhnN7NT7kp5DfmGq/iCzJYb3vTvFiacPvjEaR0TjeYvzV4Rj dsWumE9RvyWKFYdi7mTQdeP39XoUsYxQp5BDpjN+wXuc5QILBveFE4PRyvFp13ZNp6g8 xZxwMIOifHpxLxZJwZHLxb0QtM9FFHD0ZLQjs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=MF0lroNQNzh7kEu/y9kDkInWrMAAfd7m8HgikGHgtdM=; b=RFJhCyO+zA1pohf1clRpY/p4xo7E2K2x/so22QBvQOt6mr9d0Bhqx3shM7JJvPEzFc uMdYrxEiB+eHnaG+O6Yh6B6mRl/bZnBsZJQfz3ohXqPrxmtNhc5vc4O5Bqv+vOd/D3C4 1s96/eQGpplDNtHBOEdZhgNjs5h+EoUBkfaiQUEXNpEPdBAfsTQ+iSXMHaVZEmDB2+rE LJEQU0TmQNBxp9EGIRlJCGfBUn034jRw2aSxt3bU0PQK3jnWKWPKM+4d1avrGSX44YXH DFChtmSmG5EqKvIwxkWrgzIc92swuws2ecdksM1I2wr544/hrCr0kanSfjSFpVoJt98v DM0w== X-Gm-Message-State: AHYfb5jFDZfooWV332o+x1ImufulxoBZ9OdUW+h0VZGdr7TS0FuqtNup Bsnxw6Ypgdmo/AwBFBNoZQ== X-Received: by 10.28.0.196 with SMTP id 187mr480349wma.178.1504184925026; Thu, 31 Aug 2017 06:08:45 -0700 (PDT) Received: from localhost.localdomain ([154.144.95.132]) by smtp.gmail.com with ESMTPSA id u38sm5571203wrb.12.2017.08.31.06.08.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 31 Aug 2017 06:08:43 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Thu, 31 Aug 2017 14:08:29 +0100 Message-Id: <20170831130830.12833-4-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170831130830.12833-1-ard.biesheuvel@linaro.org> References: <20170831130830.12833-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms v2 3/4] Platform/OverdriveBoard: fix CPU affinity for vGIC maintenace interrupt X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alan@softiron.com, Ard Biesheuvel , liming.gao@intel.com, leif.lindholm@linaro.org MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" The CPU affinity for the vGIC maintenance interrupt was set to CPUs #0 .. #3 for no good reason. So set it to all CPUs instead. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoardDeviceTree.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoardDeviceTree.dts b/Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoardDeviceTree.dts index 81477fe43cdd..e57e702029ba 100644 --- a/Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoardDeviceTree.dts +++ b/Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoardDeviceTree.dts @@ -45,7 +45,7 @@ <0x0 0xe112f000 0x0 0x2000>, <0x0 0xe1140000 0x0 0x2000>, <0x0 0xe1160000 0x0 0x2000>; - interrupts = ; + interrupts = ; ranges = <0x0 0x0 0x0 0xe1100000 0x0 0x100000>; msi: v2m@e0080000 { From patchwork Thu Aug 31 13:08:30 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 111390 Delivered-To: patch@linaro.org Received: by 10.140.95.112 with SMTP id h103csp2521527qge; Thu, 31 Aug 2017 06:08:54 -0700 (PDT) X-Google-Smtp-Source: ADKCNb6eH4i9ZnWIOyK2achnnMWeg9lj28+IpXnma3jUlKqjKFGvLTWRAjCq97IHwywv8JnIT8Ot X-Received: by 10.98.156.208 with SMTP id u77mr2233698pfk.229.1504184934243; Thu, 31 Aug 2017 06:08:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504184934; cv=none; d=google.com; s=arc-20160816; b=cZGZH+jkKGNwT43vye0eDTAq4g2kZppDAW1rVZdMg7wTY7lT+teBP1s8e/IJwDs+Z4 ZBLLC4IMQioAWa39L3TdHMLDxbQpw8K4ovwhLhN8lmUi2F4dfWp922bWflPn+JHx2HBM nHyicA8FF8KsrZ24iJA4CGziY3NeVljBreVLOHh9K6uhcLvW5HA42ztYEuRnU0F7u2pQ 2RBzghy3K/KgJUMaiEHL48iq+wsnIngmlm2w55vQlXXQ+4K9iBcMCJVYpf2exmjbjbv/ cPrxF6UUhOP+Cx63KOrf3uVlYF4kRv0L3wYJCpGCMQqQc/peKG1rNNMiEbFDBzZIZ/O6 G6hQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=4bPUcz00EyP6jOxqnixoF7+g6JxR3T44SBOfkSO8dOA=; b=mQ7aa745LGwPz0NArfy80fGXzAY/YPxLMIOD9Acyo9ouraKv12DG1Tj6GaiFb93lNu d+4xSyaomjwxsf0kd/fQs8ibLDYZlB7ijOO+wgoGXmxxej+kzd03kqN2o8nfKLEMT6zu xYYyKvYBjlGI4P765F08AT+s5dfhdtwkoJ9n5SVABVe44QC8mtqEQConi8Hh67PQmK+3 7VJkVo1JqyB21qRapcMM/BCrSFW+fkUEkUL2aD5lyQm8shvl3N5if64GAjTh/qibfEO7 kfGAYpx+y2UtLyrkTLaLL8k38JOIX8TBa8DsJGKe+bZbCWgVNmTV1rLEmOYFgaJpQtyL lYbw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=LIB4hexR; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [2001:19d0:306:5::1]) by mx.google.com with ESMTPS id e5si6471502pgu.599.2017.08.31.06.08.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 31 Aug 2017 06:08:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=LIB4hexR; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 6E8A42095BB8A; Thu, 31 Aug 2017 06:06:07 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received: from mail-wm0-x233.google.com (mail-wm0-x233.google.com [IPv6:2a00:1450:400c:c09::233]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3881C208F7AD6 for ; Thu, 31 Aug 2017 06:06:06 -0700 (PDT) Received: by mail-wm0-x233.google.com with SMTP id f127so4483153wmf.1 for ; Thu, 31 Aug 2017 06:08:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=CSKk8eg/zbzLr82Du/n3YaH9vhPak8FyK8CHCSxNpA0=; b=LIB4hexRr9EPGsI9J2oQmIvJeLHgQY3t/fyeH5hQsCiaH1Y1PurZ+dMyFkrAaCVLnO 795n4qec8FfzrgjrOW9HajA7XWbFbw8GgiaNOFA0XjI2sH5e+OPeLLxPegDF9LW6OKEQ YfhgP5FOHRbv/sNFcX4Prkq5yAOh9D0Kesr6s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=CSKk8eg/zbzLr82Du/n3YaH9vhPak8FyK8CHCSxNpA0=; b=ld6Zh0jFgRvCv1vaH0VNNAu+FPG1t0WVKIhk1vK3qDDvz18AL1lJ5heBnD1ayq2Dim IoVBPu5AnjMqcOeRppWQLF22y7YH6UTLKKJ4QhIA6KbA1BS7fqoylzBBr10qwPBd8J3h hpkIk5mXEdoASbrz2bnFJ00po2obaGAABkgmZOnSn15ttkfE8gWAr0nc9GSwTnKg0grm WWL+0z4tknCJuC6xHZPWGDI4dFZn5CcocS6/wjv/sFLd3quTb9SNuxtsUvVXXcJbUQXE SIhX0++U5cTJaTk52J/VozUCHu3l7EBo5I9vpt75txMXphC6j3E0SLI+PZoj778cYMJP bdag== X-Gm-Message-State: AHYfb5ibgzm0LVVWF+oyW4+UHAoCudBe7wSy7zkkAxOBodlDh3uXKXnp +6DrLRWaC1qQvBclHQv3rw== X-Received: by 10.28.113.207 with SMTP id d76mr486446wmi.140.1504184927725; Thu, 31 Aug 2017 06:08:47 -0700 (PDT) Received: from localhost.localdomain ([154.144.95.132]) by smtp.gmail.com with ESMTPSA id u38sm5571203wrb.12.2017.08.31.06.08.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 31 Aug 2017 06:08:46 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Thu, 31 Aug 2017 14:08:30 +0100 Message-Id: <20170831130830.12833-5-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170831130830.12833-1-ard.biesheuvel@linaro.org> References: <20170831130830.12833-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms v2 4/4] Platform/OverdriveBoard: classify legacy INTx interrupts as level high X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alan@softiron.com, Ard Biesheuvel , liming.gao@intel.com, leif.lindholm@linaro.org MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Fix the trigger type of the legacy INTx interrupts. The Seattle SoC manual classifies them as level high, not rising edge. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoardDeviceTree.dts | 28 ++++++++++---------- 1 file changed, 14 insertions(+), 14 deletions(-) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoardDeviceTree.dts b/Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoardDeviceTree.dts index e57e702029ba..2c05fdbb8b71 100644 --- a/Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoardDeviceTree.dts +++ b/Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoardDeviceTree.dts @@ -291,20 +291,20 @@ msi-parent = <&msi>; reg = <0x0 0xf0000000 0x0 0x10000000>; interrupt-map-mask = <0xff00 0x0 0x0 0x7>; - interrupt-map = <0x1100 0x0 0x0 0x1 &gic 0x0 0x0 GIC_SPI 0x120 IRQ_TYPE_EDGE_RISING>, - <0x1100 0x0 0x0 0x2 &gic 0x0 0x0 GIC_SPI 0x121 IRQ_TYPE_EDGE_RISING>, - <0x1100 0x0 0x0 0x3 &gic 0x0 0x0 GIC_SPI 0x122 IRQ_TYPE_EDGE_RISING>, - <0x1100 0x0 0x0 0x4 &gic 0x0 0x0 GIC_SPI 0x123 IRQ_TYPE_EDGE_RISING>, - - <0x1200 0x0 0x0 0x1 &gic 0x0 0x0 GIC_SPI 0x124 IRQ_TYPE_EDGE_RISING>, - <0x1200 0x0 0x0 0x2 &gic 0x0 0x0 GIC_SPI 0x125 IRQ_TYPE_EDGE_RISING>, - <0x1200 0x0 0x0 0x3 &gic 0x0 0x0 GIC_SPI 0x126 IRQ_TYPE_EDGE_RISING>, - <0x1200 0x0 0x0 0x4 &gic 0x0 0x0 GIC_SPI 0x127 IRQ_TYPE_EDGE_RISING>, - - <0x1300 0x0 0x0 0x1 &gic 0x0 0x0 GIC_SPI 0x128 IRQ_TYPE_EDGE_RISING>, - <0x1300 0x0 0x0 0x2 &gic 0x0 0x0 GIC_SPI 0x129 IRQ_TYPE_EDGE_RISING>, - <0x1300 0x0 0x0 0x3 &gic 0x0 0x0 GIC_SPI 0x12a IRQ_TYPE_EDGE_RISING>, - <0x1300 0x0 0x0 0x4 &gic 0x0 0x0 GIC_SPI 0x12b IRQ_TYPE_EDGE_RISING>; + interrupt-map = <0x1100 0x0 0x0 0x1 &gic 0x0 0x0 GIC_SPI 0x120 IRQ_TYPE_LEVEL_HIGH>, + <0x1100 0x0 0x0 0x2 &gic 0x0 0x0 GIC_SPI 0x121 IRQ_TYPE_LEVEL_HIGH>, + <0x1100 0x0 0x0 0x3 &gic 0x0 0x0 GIC_SPI 0x122 IRQ_TYPE_LEVEL_HIGH>, + <0x1100 0x0 0x0 0x4 &gic 0x0 0x0 GIC_SPI 0x123 IRQ_TYPE_LEVEL_HIGH>, + + <0x1200 0x0 0x0 0x1 &gic 0x0 0x0 GIC_SPI 0x124 IRQ_TYPE_LEVEL_HIGH>, + <0x1200 0x0 0x0 0x2 &gic 0x0 0x0 GIC_SPI 0x125 IRQ_TYPE_LEVEL_HIGH>, + <0x1200 0x0 0x0 0x3 &gic 0x0 0x0 GIC_SPI 0x126 IRQ_TYPE_LEVEL_HIGH>, + <0x1200 0x0 0x0 0x4 &gic 0x0 0x0 GIC_SPI 0x127 IRQ_TYPE_LEVEL_HIGH>, + + <0x1300 0x0 0x0 0x1 &gic 0x0 0x0 GIC_SPI 0x128 IRQ_TYPE_LEVEL_HIGH>, + <0x1300 0x0 0x0 0x2 &gic 0x0 0x0 GIC_SPI 0x129 IRQ_TYPE_LEVEL_HIGH>, + <0x1300 0x0 0x0 0x3 &gic 0x0 0x0 GIC_SPI 0x12a IRQ_TYPE_LEVEL_HIGH>, + <0x1300 0x0 0x0 0x4 &gic 0x0 0x0 GIC_SPI 0x12b IRQ_TYPE_LEVEL_HIGH>; dma-coherent; dma-ranges = <0x43000000 0x0 0x0 0x0 0x0 0x100 0x0>; ranges = <0x1000000 0x0 0x00000000 0x0 0xefff0000 0x00 0x00010000>, /* I/O Memory (size=64K) */