From patchwork Mon Mar 23 17:52:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 210491 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 11C4CC54FD6 for ; Mon, 23 Mar 2020 17:53:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DF20620774 for ; Mon, 23 Mar 2020 17:53:22 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="J71bVAk8" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727110AbgCWRwi (ORCPT ); Mon, 23 Mar 2020 13:52:38 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:14743 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726986AbgCWRwi (ORCPT ); Mon, 23 Mar 2020 13:52:38 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 23 Mar 2020 10:51:53 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 23 Mar 2020 10:52:37 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 23 Mar 2020 10:52:37 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 23 Mar 2020 17:52:37 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Mon, 23 Mar 2020 17:52:37 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.160.78]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 23 Mar 2020 10:52:37 -0700 From: Sowjanya Komatineni To: , , , , , CC: , , , , , , Subject: [RFC PATCH v5 1/9] arm64: tegra: Fix sor powergate clocks and reset Date: Mon, 23 Mar 2020 10:52:27 -0700 Message-ID: <1584985955-19101-2-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1584985955-19101-1-git-send-email-skomatineni@nvidia.com> References: <1584985955-19101-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1584985913; bh=PTc2SyRS9NP+68XdMh+c6cj6nLmKTNHZwxALx6dnzdM=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=J71bVAk8mBk+hwQro1QjM7SO9SwRQibgoVQdkGOW2dGaeQnqs1AYtN9As1zmtq/PH KmT4v6Vst6FLPJ6RuNTgpzr9kJrsCmKMBIkKAWg9FsSRWmloyD/dDNvejeCKR6eU43 pdwS2DTOpXUxYQl0eHA4XdJrfssUQaRR8EzKPPQlSrOH0TX/JVOXiMNnGycFlgpuOo Q5HfikyW2yXRTXC+K+sMJ3DKijs+iMqwOKI18uT6ZvdkF8/n0+ZFWttERIVk7lVhFy gQqIYdCJ5SvX60ghx/zz7u67Ux4J3sWAx1aZSgtxp4//+3xzJzYYRxM00kQSDmO/d5 v/lYdISp6P6fw== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Tegra210 device tree lists csi clock and reset under SOR powergate node. But Tegra210 has csicil in SOR partition and csi in VENC partition. So, this patch includes fix for sor powergate node. Signed-off-by: Sowjanya Komatineni --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 64c46ce..d0eff92 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -796,7 +796,9 @@ pd_sor: sor { clocks = <&tegra_car TEGRA210_CLK_SOR0>, <&tegra_car TEGRA210_CLK_SOR1>, - <&tegra_car TEGRA210_CLK_CSI>, + <&tegra_car TEGRA210_CLK_CILAB>, + <&tegra_car TEGRA210_CLK_CILCD>, + <&tegra_car TEGRA210_CLK_CILE>, <&tegra_car TEGRA210_CLK_DSIA>, <&tegra_car TEGRA210_CLK_DSIB>, <&tegra_car TEGRA210_CLK_DPAUX>, @@ -804,7 +806,6 @@ <&tegra_car TEGRA210_CLK_MIPI_CAL>; resets = <&tegra_car TEGRA210_CLK_SOR0>, <&tegra_car TEGRA210_CLK_SOR1>, - <&tegra_car TEGRA210_CLK_CSI>, <&tegra_car TEGRA210_CLK_DSIA>, <&tegra_car TEGRA210_CLK_DSIB>, <&tegra_car TEGRA210_CLK_DPAUX>, From patchwork Mon Mar 23 17:52:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 210493 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25735C54FCF for ; Mon, 23 Mar 2020 17:53:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 021CA2072E for ; Mon, 23 Mar 2020 17:53:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="VnDozmx8" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727673AbgCWRwl (ORCPT ); Mon, 23 Mar 2020 13:52:41 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:15190 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726986AbgCWRwl (ORCPT ); Mon, 23 Mar 2020 13:52:41 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 23 Mar 2020 10:52:26 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 23 Mar 2020 10:52:39 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 23 Mar 2020 10:52:39 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 23 Mar 2020 17:52:39 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Mon, 23 Mar 2020 17:52:39 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.160.78]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 23 Mar 2020 10:52:39 -0700 From: Sowjanya Komatineni To: , , , , , CC: , , , , , , Subject: [RFC PATCH v5 4/9] clk: tegra: Add Tegra210 CSI TPG clock gate Date: Mon, 23 Mar 2020 10:52:30 -0700 Message-ID: <1584985955-19101-5-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1584985955-19101-1-git-send-email-skomatineni@nvidia.com> References: <1584985955-19101-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1584985946; bh=OGs3CNdnpPztJ28S1nwc0JHJg2nXou6ljJssqTIUQtQ=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=VnDozmx8MyAuMN2X66e3c8VMfk8zDGOCgd6a/JlZ34lB19gtQshhPtEZsbGGr49cP I9ZQ8mREItmblekPjAp63x4rgXtNDA1OBm5y8R4nKLeWG44I3nlkEL5fGw+VqCLc1M 7HJ6Mi3Sg3EgSvkoyh3olVApUqqFvStvvR369lRctNfe7qCmwf2R8ctTGL9vJHiHuZ 3+lnTo+JO2pqsILcq/fAbxRKNOzRTnzS7M1/EWUNfSzTHeAY0njyFtxhIKS/WDz4Sj Z/vR9hmh5fK1hknUocmwuT/Ru6sepUh98AWWY0V20rEIfTVLmr6wYwTi2vDs8BAiI1 mWwA4mIsyy4Iw== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Tegra210 CSI hardware internally uses PLLD for internal test pattern generator logic. PLLD_BASE register in CAR has a bit CSI_CLK_SOURCE to enable PLLD out to CSI during TPG mode. This patch adds this CSI TPG clock gate to Tegra210 clock driver to allow Tegra video driver to ungate CSI TPG clock during TPG mode and gate during non TPG mode. Acked-by: Stephen Boyd Signed-off-by: Sowjanya Komatineni --- drivers/clk/tegra/clk-tegra210.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index c6304f5..58a67c7 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -3035,6 +3035,13 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base, periph_clk_enb_refcnt); clks[TEGRA210_CLK_DSIB] = clk; + /* csi_tpg */ + clk = clk_register_gate(NULL, "csi_tpg", "pll_d_out0", + CLK_SET_RATE_PARENT, clk_base + PLLD_BASE, + 23, 0, &pll_d_lock); + clk_register_clkdev(clk, "csi_tpg", NULL); + clks[TEGRA210_CLK_CSI_TPG] = clk; + /* la */ clk = tegra_clk_register_periph("la", la_parents, ARRAY_SIZE(la_parents), &tegra210_la, clk_base, From patchwork Mon Mar 23 17:52:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 210492 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B985FC54FD1 for ; Mon, 23 Mar 2020 17:53:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 987E420774 for ; Mon, 23 Mar 2020 17:53:14 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="GCzLV99+" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727927AbgCWRxO (ORCPT ); Mon, 23 Mar 2020 13:53:14 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:14758 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727569AbgCWRwl (ORCPT ); Mon, 23 Mar 2020 13:52:41 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 23 Mar 2020 10:51:56 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 23 Mar 2020 10:52:40 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 23 Mar 2020 10:52:40 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 23 Mar 2020 17:52:40 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Mon, 23 Mar 2020 17:52:40 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.160.78]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 23 Mar 2020 10:52:40 -0700 From: Sowjanya Komatineni To: , , , , , CC: , , , , , , Subject: [RFC PATCH v5 5/9] dt-binding: tegra: Add VI and CSI bindings Date: Mon, 23 Mar 2020 10:52:31 -0700 Message-ID: <1584985955-19101-6-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1584985955-19101-1-git-send-email-skomatineni@nvidia.com> References: <1584985955-19101-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1584985916; bh=x52xXIXK6pPK6/ZlFIxKUYbjv7dRay6339W/L0ntpdo=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=GCzLV99+uLAtWSNQpT1zL5Ly59zV2wKX1Sjt4yZIyWtuLQ48VJytAw1cPUu4+D7EE NLxz8zOBaa+koB/YJipoOZFVVg4NdXZDY86T0xRWHforh2FvpKJWWBjRh0OAMX5twE aWZIpad3+8TSEqeIF36r6LH67hnerVVR1lS0TI1tUJTyigxuqtvQp7GPIRSAxFFNTq HWoTPPaWT6WMNunz0X1Jv6jUdYLiL0LYo8UFzqaOQbyC/By5Mgc75bt6WUBoii2yhb Rf7o84iYE9igETV125rwfZbUGpYD4hxKrKkccCzn/b6Xu037pORzzNw4dHL7v3fdJP enarff3ELwhlQ== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Tegra contains VI controller which can support up to 6 MIPI CSI camera sensors. Each Tegra CSI port from CSI unit can be one-to-one mapper to VI channel and can capture from an external camera sensor or from built-in test pattern generator. This patch adds dt-bindings for Tegra VI and CSI. Signed-off-by: Sowjanya Komatineni --- .../display/tegra/nvidia,tegra20-host1x.txt | 67 +++++++++++++++++----- 1 file changed, 54 insertions(+), 13 deletions(-) diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt index 9999255..9421569 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt @@ -40,14 +40,25 @@ of the following host1x client modules: Required properties: - compatible: "nvidia,tegra-vi" - - reg: Physical base address and length of the controller's registers. + - reg: Physical base address and length of the controller registers. - interrupts: The interrupt outputs from the controller. - - clocks: Must contain one entry, for the module clock. + - clocks: Must contain an entry for the module clock "vi" See ../clocks/clock-bindings.txt for details. - - resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. - - reset-names: Must include the following entries: - - vi + - power-domains: Must include venc powergate node as vi is in VE partition. + + Tegra210 has CSI part of VI sharing same host interface and register + space. So, VI device node should have CSI child node. + + - csi: mipi csi interface to vi + + Required properties: + - compatible: "nvidia,tegra-csi" + - reg: Physical base address offset to parent and length of the controller + registers. + - clocks: Must contain entries csi, cilab, cilcd, cile clocks. + See ../clocks/clock-bindings.txt for details. + - power-domains: Must include sor powergate node as csicil is in + SOR partition. - epp: encoder pre-processor @@ -309,13 +320,43 @@ Example: reset-names = "mpe"; }; - vi { - compatible = "nvidia,tegra20-vi"; - reg = <0x54080000 0x00040000>; - interrupts = <0 69 0x04>; - clocks = <&tegra_car TEGRA20_CLK_VI>; - resets = <&tegra_car 100>; - reset-names = "vi"; + vi@54080000 { + compatible = "nvidia,tegra210-vi"; + reg = <0x0 0x54080000 0x0 0x700>; + interrupts = ; + assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; + + clocks = <&tegra_car TEGRA210_CLK_VI>; + clock-names = "vi"; + power-domains = <&pd_venc>; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x0 0x0 0x54080000 0x2000>; + + csi@838 { + compatible = "nvidia,tegra210-csi"; + reg = <0x838 0x1300>; + assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, + <&tegra_car TEGRA210_CLK_CILCD>, + <&tegra_car TEGRA210_CLK_CILE>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, + <&tegra_car TEGRA210_CLK_PLL_P>, + <&tegra_car TEGRA210_CLK_PLL_P>; + assigned-clock-rates = <102000000>, + <102000000>, + <102000000>; + + clocks = <&tegra_car TEGRA210_CLK_CSI>, + <&tegra_car TEGRA210_CLK_CILAB>, + <&tegra_car TEGRA210_CLK_CILCD>, + <&tegra_car TEGRA210_CLK_CILE>; + clock-names = "csi", "cilab", "cilcd", "cile"; + power-domains = <&pd_sor>; + }; + }; epp { From patchwork Mon Mar 23 17:52:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 210495 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2096DC54FD0 for ; Mon, 23 Mar 2020 17:52:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F16DF2072E for ; Mon, 23 Mar 2020 17:52:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="SfqWGgOy" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727843AbgCWRwq (ORCPT ); Mon, 23 Mar 2020 13:52:46 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:15195 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727758AbgCWRwn (ORCPT ); Mon, 23 Mar 2020 13:52:43 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 23 Mar 2020 10:52:29 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Mon, 23 Mar 2020 10:52:42 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Mon, 23 Mar 2020 10:52:42 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 23 Mar 2020 17:52:42 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Mon, 23 Mar 2020 17:52:42 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.160.78]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 23 Mar 2020 10:52:42 -0700 From: Sowjanya Komatineni To: , , , , , CC: , , , , , , Subject: [RFC PATCH v5 8/9] dt-bindings: reset: Add ID for Tegra210 VI reset Date: Mon, 23 Mar 2020 10:52:34 -0700 Message-ID: <1584985955-19101-9-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1584985955-19101-1-git-send-email-skomatineni@nvidia.com> References: <1584985955-19101-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1584985949; bh=L8ndW8+Uxj7JNOHxtp4ihFZmkMPUeCnBtUyBLpK+IFo=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=SfqWGgOyvC4bs4m2L9x991tdetDB2p+2AanuGAqD7sLe1OSeU8/kuQxIiBN/4A5jd +swAjow7D2dZutziVTFrNRiI7/gNQhl5yTyUdPayA3uzNbWVa9E9S9Sw0UvxxwiQ/4 BiLa4WyUvbmP8yLaWkRUNTOi1tq8iL1jd5nm7lKGesQIx1XWhKXYJ6MeYRDkCRdrRr kWhRok/P695NCBwEivDJ0NqaXacG2aXfZu4HweoHnz9ifgbLVJF3ldGQYd2vnltVTa AKtpLCVttHSeoO9y9/lGROSzE0FabWhlUMh4yjBCLDQFroOesz13b9+jGQylC9RYOz H2oHx62ianwxA== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org This patch adds ID for Tegra210 VI controller reset to use with device tree. Signed-off-by: Sowjanya Komatineni --- include/dt-bindings/reset/tegra210-car.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/reset/tegra210-car.h b/include/dt-bindings/reset/tegra210-car.h index 9dc84ec..8755946 100644 --- a/include/dt-bindings/reset/tegra210-car.h +++ b/include/dt-bindings/reset/tegra210-car.h @@ -10,5 +10,6 @@ #define TEGRA210_RESET(x) (7 * 32 + (x)) #define TEGRA210_RST_DFLL_DVCO TEGRA210_RESET(0) #define TEGRA210_RST_ADSP TEGRA210_RESET(1) +#define TEGRA210_RST_VI 20 #endif /* _DT_BINDINGS_RESET_TEGRA210_CAR_H */ From patchwork Mon Mar 23 17:52:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 210494 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20847C54FD2 for ; Mon, 23 Mar 2020 17:52:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F3FD120753 for ; Mon, 23 Mar 2020 17:52:57 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="kFzaIrtx" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727828AbgCWRwp (ORCPT ); Mon, 23 Mar 2020 13:52:45 -0400 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:17093 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727803AbgCWRwo (ORCPT ); Mon, 23 Mar 2020 13:52:44 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 23 Mar 2020 10:51:13 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Mon, 23 Mar 2020 10:52:43 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Mon, 23 Mar 2020 10:52:43 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 23 Mar 2020 17:52:43 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Mon, 23 Mar 2020 17:52:42 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.160.78]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 23 Mar 2020 10:52:42 -0700 From: Sowjanya Komatineni To: , , , , , CC: , , , , , , Subject: [RFC PATCH v5 9/9] arm64: tegra: Add Tegra VI CSI support in device tree Date: Mon, 23 Mar 2020 10:52:35 -0700 Message-ID: <1584985955-19101-10-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1584985955-19101-1-git-send-email-skomatineni@nvidia.com> References: <1584985955-19101-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1584985873; bh=qg4/50YwdGiG0ifmC8NW2wUPpPGLSESHVND184P5UFw=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=kFzaIrtxtdihQI5PAHWVWD/UqOIby7BGGDpM+ZaaV/ObTaFIMJs+ZJWEWARzbmnXT Ca204D+JfmYqEQNxS8Rh24W/uHV2S3AhvYPNR6ZQgEmZhYyLa4CH9oOu1+XLiiBtaF zZqG/v/6VGz9uuAS1exEQMqWOkOKo6mDGJmhVvSLmcYvLnkh1fBPVH8J36Jmhn14Rg yzHqgp0rFSHyF6z5PcjxpQVFLNW1phlCBNXTIiRIe10ZnjaaGjO9zkHzbPS/kMwIrN 6UgbN+jg/cWGn+mTW9SyomtuhIZYwvL1Be1T1gKqRdQS8ktM0A26X4/z6O1tuD8Pv4 t0wEW0mA7D7Tg== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Tegra210 contains VI controller for video input capture from MIPI CSI camera sensors and also supports built-in test pattern generator. CSI ports can be one-to-one mapped to VI channels for capturing from an external sensor or from built-in test pattern generator. This patch adds support for VI and CSI and enables them in Tegra210 device tree. Signed-off-by: Sowjanya Komatineni --- arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 10 ++++++ arch/arm64/boot/dts/nvidia/tegra210.dtsi | 45 +++++++++++++++++++++++++- 2 files changed, 54 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi index 313a4c2..b57d837 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi @@ -14,6 +14,16 @@ status = "okay"; }; + vi@54080000 { + status = "okay"; + + avdd-dsi-csi-supply = <&vdd_dsi_csi>; + + csi@838 { + status = "okay"; + }; + }; + sor@54580000 { status = "okay"; diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 5b1dfd8..2deba87 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -137,9 +137,43 @@ vi@54080000 { compatible = "nvidia,tegra210-vi"; - reg = <0x0 0x54080000 0x0 0x00040000>; + reg = <0x0 0x54080000 0x0 0x700>; interrupts = ; status = "disabled"; + assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; + + clocks = <&tegra_car TEGRA210_CLK_VI>; + clock-names = "vi"; + power-domains = <&pd_venc>; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x0 0x0 0x54080000 0x2000>; + + csi@838 { + compatible = "nvidia,tegra210-csi"; + reg = <0x838 0x1300>; + status = "disabled"; + assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, + <&tegra_car TEGRA210_CLK_CILCD>, + <&tegra_car TEGRA210_CLK_CILE>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, + <&tegra_car TEGRA210_CLK_PLL_P>, + <&tegra_car TEGRA210_CLK_PLL_P>; + assigned-clock-rates = <102000000>, + <102000000>, + <102000000>; + + clocks = <&tegra_car TEGRA210_CLK_CSI>, + <&tegra_car TEGRA210_CLK_CILAB>, + <&tegra_car TEGRA210_CLK_CILCD>, + <&tegra_car TEGRA210_CLK_CILE>; + clock-names = "csi", "cilab", "cilcd", "cile"; + power-domains = <&pd_sor>; + }; + }; tsec@54100000 { @@ -839,6 +873,15 @@ reset-names = "vic"; #power-domain-cells = <0>; }; + + pd_venc: venc { + clocks = <&tegra_car TEGRA210_CLK_VI>, + <&tegra_car TEGRA210_CLK_CSI>; + resets = <&mc TEGRA210_MC_RESET_VI>, + <&tegra_car TEGRA210_RST_VI>, + <&tegra_car TEGRA210_CLK_CSI>; + #power-domain-cells = <0>; + }; }; sdmmc1_3v3: sdmmc1-3v3 {