From patchwork Tue Feb 18 17:13:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring \(Arm\)" X-Patchwork-Id: 212817 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CBEFEC34048 for ; Tue, 18 Feb 2020 17:15:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A387F2465D for ; Tue, 18 Feb 2020 17:15:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1582046101; bh=LePWQPdw0yLe3gcSpPm0E4sHYbV16oulKoL2D/G26dk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=vaNy/YBAke1X+OGaODwVWWC5VSKc6CEmGk58Z6ra1I+IWhqxpLf95euIYf4T7ym6k bX1I9TeEFEUlQFQwu2ciX9g1cg6UL2uWHUxaP20gm7LHe+f+W+yWcIM6R/hgxwcpVl s/ujFDokxedjm30LLp4WzB9H8dKI+0hgdz5J1nFQ= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726826AbgBRRN0 (ORCPT ); Tue, 18 Feb 2020 12:13:26 -0500 Received: from mail-ot1-f68.google.com ([209.85.210.68]:45975 "EHLO mail-ot1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726750AbgBRRN0 (ORCPT ); Tue, 18 Feb 2020 12:13:26 -0500 Received: by mail-ot1-f68.google.com with SMTP id 59so20239284otp.12; Tue, 18 Feb 2020 09:13:25 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4LxZR/H/qWaW6PLZe7czUDlSa5Ov9S/K1kfsaVdcFug=; b=Y+eIkOh/8pk4ibBhldw3l0arntaaYotKXwiF29K9P325mXl//DMJJ5zkNVaug/4nYL QxyS2BT+5uhwcpZtmXSQu1FoKhp0nGrIregfSKKiL08DsKekbeVrf7y2hwFGGm+4DrYo RHHY3XwWgBgA7d+t4bgLWfob/LcH7cJqxt6wR4zwByA4gPE13GNyqyRfOTZ8WrimDQqH NYgxtWncTVZP+7d/AE6vBllHbSITaEnfafPlsLurijhLCx0/L59iEL8CPkFQ3GA+2E9c NyzHyiIEWshdjhFRa2oJhP3OPTD42OkWPS2qTSwTfqs5WKXla0V8vUr27tdnwNMs54Yx nGYw== X-Gm-Message-State: APjAAAXtoWxEyliSONOWPlZayTiwMT1c2rBDm8UveOkJaugQbWyFOT0R ei2xdoRadJxzUeyHpFYHMA== X-Google-Smtp-Source: APXvYqzcQiA7Kz1hw5DSMbv4x/r+JIz0TrIbtjHbvB5jqm2ONigiZ49RPglyPaLbn09y6q4zITnNIw== X-Received: by 2002:a05:6830:1f0c:: with SMTP id u12mr16226750otg.253.1582046005180; Tue, 18 Feb 2020 09:13:25 -0800 (PST) Received: from xps15.herring.priv (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.googlemail.com with ESMTPSA id y25sm1545755oto.27.2020.02.18.09.13.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Feb 2020 09:13:24 -0800 (PST) From: Rob Herring To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, soc@kernel.org, Andre Przywara , Robert Richter , Jon Loeliger , Alexander Graf , Matthias Brugger , Mark Langsdorf Cc: Alex Williamson , Borislav Petkov , Cornelia Huck , Daniel Lezcano , "David S. Miller" , devicetree@vger.kernel.org, Eric Auger , iommu@lists.linux-foundation.org, James Morse , Jens Axboe , Joerg Roedel , kvm@vger.kernel.org, linux-clk@vger.kernel.org, linux-edac@vger.kernel.org, linux-ide@vger.kernel.org, linux-pm@vger.kernel.org, Mauro Carvalho Chehab , netdev@vger.kernel.org, "Rafael J. Wysocki" , Robin Murphy , Stephen Boyd , Tony Luck , Viresh Kumar , Will Deacon Subject: [RFC PATCH 01/11] vfio: Remove Calxeda XGMAC reset driver Date: Tue, 18 Feb 2020 11:13:11 -0600 Message-Id: <20200218171321.30990-2-robh@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200218171321.30990-1-robh@kernel.org> References: <20200218171321.30990-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Cc: Eric Auger Cc: Alex Williamson Cc: Cornelia Huck Cc: kvm@vger.kernel.org Signed-off-by: Rob Herring --- Do not apply yet. drivers/vfio/platform/reset/Kconfig | 8 -- drivers/vfio/platform/reset/Makefile | 2 - .../reset/vfio_platform_calxedaxgmac.c | 74 ------------------- 3 files changed, 84 deletions(-) delete mode 100644 drivers/vfio/platform/reset/vfio_platform_calxedaxgmac.c -- 2.20.1 diff --git a/drivers/vfio/platform/reset/Kconfig b/drivers/vfio/platform/reset/Kconfig index 1edbe9ee7356..3668d1d92909 100644 --- a/drivers/vfio/platform/reset/Kconfig +++ b/drivers/vfio/platform/reset/Kconfig @@ -1,12 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only -config VFIO_PLATFORM_CALXEDAXGMAC_RESET - tristate "VFIO support for calxeda xgmac reset" - depends on VFIO_PLATFORM - help - Enables the VFIO platform driver to handle reset for Calxeda xgmac - - If you don't know what to do here, say N. - config VFIO_PLATFORM_AMDXGBE_RESET tristate "VFIO support for AMD XGBE reset" depends on VFIO_PLATFORM diff --git a/drivers/vfio/platform/reset/Makefile b/drivers/vfio/platform/reset/Makefile index 7294c5ea122e..be7960ce5dbc 100644 --- a/drivers/vfio/platform/reset/Makefile +++ b/drivers/vfio/platform/reset/Makefile @@ -1,7 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 -vfio-platform-calxedaxgmac-y := vfio_platform_calxedaxgmac.o vfio-platform-amdxgbe-y := vfio_platform_amdxgbe.o -obj-$(CONFIG_VFIO_PLATFORM_CALXEDAXGMAC_RESET) += vfio-platform-calxedaxgmac.o obj-$(CONFIG_VFIO_PLATFORM_AMDXGBE_RESET) += vfio-platform-amdxgbe.o obj-$(CONFIG_VFIO_PLATFORM_BCMFLEXRM_RESET) += vfio_platform_bcmflexrm.o diff --git a/drivers/vfio/platform/reset/vfio_platform_calxedaxgmac.c b/drivers/vfio/platform/reset/vfio_platform_calxedaxgmac.c deleted file mode 100644 index 09a9453b75c5..000000000000 --- a/drivers/vfio/platform/reset/vfio_platform_calxedaxgmac.c +++ /dev/null @@ -1,74 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * VFIO platform driver specialized for Calxeda xgmac reset - * reset code is inherited from calxeda xgmac native driver - * - * Copyright 2010-2011 Calxeda, Inc. - * Copyright (c) 2015 Linaro Ltd. - * www.linaro.org - */ - -#include -#include -#include -#include - -#include "../vfio_platform_private.h" - -#define DRIVER_VERSION "0.1" -#define DRIVER_AUTHOR "Eric Auger " -#define DRIVER_DESC "Reset support for Calxeda xgmac vfio platform device" - -/* XGMAC Register definitions */ -#define XGMAC_CONTROL 0x00000000 /* MAC Configuration */ - -/* DMA Control and Status Registers */ -#define XGMAC_DMA_CONTROL 0x00000f18 /* Ctrl (Operational Mode) */ -#define XGMAC_DMA_INTR_ENA 0x00000f1c /* Interrupt Enable */ - -/* DMA Control registe defines */ -#define DMA_CONTROL_ST 0x00002000 /* Start/Stop Transmission */ -#define DMA_CONTROL_SR 0x00000002 /* Start/Stop Receive */ - -/* Common MAC defines */ -#define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */ -#define MAC_ENABLE_RX 0x00000004 /* Receiver Enable */ - -static inline void xgmac_mac_disable(void __iomem *ioaddr) -{ - u32 value = readl(ioaddr + XGMAC_DMA_CONTROL); - - value &= ~(DMA_CONTROL_ST | DMA_CONTROL_SR); - writel(value, ioaddr + XGMAC_DMA_CONTROL); - - value = readl(ioaddr + XGMAC_CONTROL); - value &= ~(MAC_ENABLE_TX | MAC_ENABLE_RX); - writel(value, ioaddr + XGMAC_CONTROL); -} - -static int vfio_platform_calxedaxgmac_reset(struct vfio_platform_device *vdev) -{ - struct vfio_platform_region *reg = &vdev->regions[0]; - - if (!reg->ioaddr) { - reg->ioaddr = - ioremap(reg->addr, reg->size); - if (!reg->ioaddr) - return -ENOMEM; - } - - /* disable IRQ */ - writel(0, reg->ioaddr + XGMAC_DMA_INTR_ENA); - - /* Disable the MAC core */ - xgmac_mac_disable(reg->ioaddr); - - return 0; -} - -module_vfio_reset_handler("calxeda,hb-xgmac", vfio_platform_calxedaxgmac_reset); - -MODULE_VERSION(DRIVER_VERSION); -MODULE_LICENSE("GPL v2"); -MODULE_AUTHOR(DRIVER_AUTHOR); -MODULE_DESCRIPTION(DRIVER_DESC); From patchwork Tue Feb 18 17:13:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring \(Arm\)" X-Patchwork-Id: 212822 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.3 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNWANTED_LANGUAGE_BODY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9D4C8C34026 for ; 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[24.155.109.49]) by smtp.googlemail.com with ESMTPSA id y25sm1545755oto.27.2020.02.18.09.13.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Feb 2020 09:13:26 -0800 (PST) From: Rob Herring To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, soc@kernel.org, Andre Przywara , Robert Richter , Jon Loeliger , Alexander Graf , Matthias Brugger , Mark Langsdorf Cc: Alex Williamson , Borislav Petkov , Cornelia Huck , Daniel Lezcano , "David S. Miller" , devicetree@vger.kernel.org, Eric Auger , iommu@lists.linux-foundation.org, James Morse , Jens Axboe , Joerg Roedel , kvm@vger.kernel.org, linux-clk@vger.kernel.org, linux-edac@vger.kernel.org, linux-ide@vger.kernel.org, linux-pm@vger.kernel.org, Mauro Carvalho Chehab , netdev@vger.kernel.org, "Rafael J. Wysocki" , Robin Murphy , Stephen Boyd , Tony Luck , Viresh Kumar , Will Deacon Subject: [RFC PATCH 02/11] ata: Remove Calxeda AHCI driver Date: Tue, 18 Feb 2020 11:13:12 -0600 Message-Id: <20200218171321.30990-3-robh@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200218171321.30990-1-robh@kernel.org> References: <20200218171321.30990-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Cc: Jens Axboe Cc: linux-ide@vger.kernel.org Signed-off-by: Rob Herring --- Do not apply yet. drivers/ata/Kconfig | 9 - drivers/ata/Makefile | 1 - drivers/ata/sata_highbank.c | 635 ------------------------------------ 3 files changed, 645 deletions(-) delete mode 100644 drivers/ata/sata_highbank.c -- 2.20.1 diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index a6beb2c5a692..687ddd9f4188 100644 --- a/drivers/ata/Kconfig +++ b/drivers/ata/Kconfig @@ -395,15 +395,6 @@ config SATA_DWC_VDEBUG help This option enables the taskfile dumping and NCQ debugging. -config SATA_HIGHBANK - tristate "Calxeda Highbank SATA support" - depends on ARCH_HIGHBANK || COMPILE_TEST - help - This option enables support for the Calxeda Highbank SoC's - onboard SATA. - - If unsure, say N. - config SATA_MV tristate "Marvell SATA support" depends on PCI || ARCH_DOVE || ARCH_MV78XX0 || \ diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile index d8cc2e04a6c7..08f26d674ed7 100644 --- a/drivers/ata/Makefile +++ b/drivers/ata/Makefile @@ -12,7 +12,6 @@ obj-$(CONFIG_SATA_GEMINI) += sata_gemini.o obj-$(CONFIG_SATA_INIC162X) += sata_inic162x.o obj-$(CONFIG_SATA_SIL24) += sata_sil24.o obj-$(CONFIG_SATA_DWC) += sata_dwc_460ex.o -obj-$(CONFIG_SATA_HIGHBANK) += sata_highbank.o libahci.o obj-$(CONFIG_AHCI_BRCM) += ahci_brcm.o libahci.o libahci_platform.o obj-$(CONFIG_AHCI_CEVA) += ahci_ceva.o libahci.o libahci_platform.o obj-$(CONFIG_AHCI_DA850) += ahci_da850.o libahci.o libahci_platform.o diff --git a/drivers/ata/sata_highbank.c b/drivers/ata/sata_highbank.c deleted file mode 100644 index ad3893c62572..000000000000 --- a/drivers/ata/sata_highbank.c +++ /dev/null @@ -1,635 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Calxeda Highbank AHCI SATA platform driver - * Copyright 2012 Calxeda, Inc. - * - * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "ahci.h" - -#define CPHY_MAP(dev, addr) ((((dev) & 0x1f) << 7) | (((addr) >> 9) & 0x7f)) -#define CPHY_ADDR(addr) (((addr) & 0x1ff) << 2) -#define SERDES_CR_CTL 0x80a0 -#define SERDES_CR_ADDR 0x80a1 -#define SERDES_CR_DATA 0x80a2 -#define CR_BUSY 0x0001 -#define CR_START 0x0001 -#define CR_WR_RDN 0x0002 -#define CPHY_TX_INPUT_STS 0x2001 -#define CPHY_RX_INPUT_STS 0x2002 -#define CPHY_SATA_TX_OVERRIDE 0x8000 -#define CPHY_SATA_RX_OVERRIDE 0x4000 -#define CPHY_TX_OVERRIDE 0x2004 -#define CPHY_RX_OVERRIDE 0x2005 -#define SPHY_LANE 0x100 -#define SPHY_HALF_RATE 0x0001 -#define CPHY_SATA_DPLL_MODE 0x0700 -#define CPHY_SATA_DPLL_SHIFT 8 -#define CPHY_SATA_DPLL_RESET (1 << 11) -#define CPHY_SATA_TX_ATTEN 0x1c00 -#define CPHY_SATA_TX_ATTEN_SHIFT 10 -#define CPHY_PHY_COUNT 6 -#define CPHY_LANE_COUNT 4 -#define CPHY_PORT_COUNT (CPHY_PHY_COUNT * CPHY_LANE_COUNT) - -static DEFINE_SPINLOCK(cphy_lock); -/* Each of the 6 phys can have up to 4 sata ports attached to i. Map 0-based - * sata ports to their phys and then to their lanes within the phys - */ -struct phy_lane_info { - void __iomem *phy_base; - u8 lane_mapping; - u8 phy_devs; - u8 tx_atten; -}; -static struct phy_lane_info port_data[CPHY_PORT_COUNT]; - -static DEFINE_SPINLOCK(sgpio_lock); -#define SCLOCK 0 -#define SLOAD 1 -#define SDATA 2 -#define SGPIO_PINS 3 -#define SGPIO_PORTS 8 - -struct ecx_plat_data { - u32 n_ports; - /* number of extra clocks that the SGPIO PIC controller expects */ - u32 pre_clocks; - u32 post_clocks; - struct gpio_desc *sgpio_gpiod[SGPIO_PINS]; - u32 sgpio_pattern; - u32 port_to_sgpio[SGPIO_PORTS]; -}; - -#define SGPIO_SIGNALS 3 -#define ECX_ACTIVITY_BITS 0x300000 -#define ECX_ACTIVITY_SHIFT 0 -#define ECX_LOCATE_BITS 0x80000 -#define ECX_LOCATE_SHIFT 1 -#define ECX_FAULT_BITS 0x400000 -#define ECX_FAULT_SHIFT 2 -static inline int sgpio_bit_shift(struct ecx_plat_data *pdata, u32 port, - u32 shift) -{ - return 1 << (3 * pdata->port_to_sgpio[port] + shift); -} - -static void ecx_parse_sgpio(struct ecx_plat_data *pdata, u32 port, u32 state) -{ - if (state & ECX_ACTIVITY_BITS) - pdata->sgpio_pattern |= sgpio_bit_shift(pdata, port, - ECX_ACTIVITY_SHIFT); - else - pdata->sgpio_pattern &= ~sgpio_bit_shift(pdata, port, - ECX_ACTIVITY_SHIFT); - if (state & ECX_LOCATE_BITS) - pdata->sgpio_pattern |= sgpio_bit_shift(pdata, port, - ECX_LOCATE_SHIFT); - else - pdata->sgpio_pattern &= ~sgpio_bit_shift(pdata, port, - ECX_LOCATE_SHIFT); - if (state & ECX_FAULT_BITS) - pdata->sgpio_pattern |= sgpio_bit_shift(pdata, port, - ECX_FAULT_SHIFT); - else - pdata->sgpio_pattern &= ~sgpio_bit_shift(pdata, port, - ECX_FAULT_SHIFT); -} - -/* - * Tell the LED controller that the signal has changed by raising the clock - * line for 50 uS and then lowering it for 50 uS. - */ -static void ecx_led_cycle_clock(struct ecx_plat_data *pdata) -{ - gpiod_set_value(pdata->sgpio_gpiod[SCLOCK], 1); - udelay(50); - gpiod_set_value(pdata->sgpio_gpiod[SCLOCK], 0); - udelay(50); -} - -static ssize_t ecx_transmit_led_message(struct ata_port *ap, u32 state, - ssize_t size) -{ - struct ahci_host_priv *hpriv = ap->host->private_data; - struct ecx_plat_data *pdata = hpriv->plat_data; - struct ahci_port_priv *pp = ap->private_data; - unsigned long flags; - int pmp, i; - struct ahci_em_priv *emp; - u32 sgpio_out; - - /* get the slot number from the message */ - pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; - if (pmp < EM_MAX_SLOTS) - emp = &pp->em_priv[pmp]; - else - return -EINVAL; - - if (!(hpriv->em_msg_type & EM_MSG_TYPE_LED)) - return size; - - spin_lock_irqsave(&sgpio_lock, flags); - ecx_parse_sgpio(pdata, ap->port_no, state); - sgpio_out = pdata->sgpio_pattern; - for (i = 0; i < pdata->pre_clocks; i++) - ecx_led_cycle_clock(pdata); - - gpiod_set_value(pdata->sgpio_gpiod[SLOAD], 1); - ecx_led_cycle_clock(pdata); - gpiod_set_value(pdata->sgpio_gpiod[SLOAD], 0); - /* - * bit-bang out the SGPIO pattern, by consuming a bit and then - * clocking it out. - */ - for (i = 0; i < (SGPIO_SIGNALS * pdata->n_ports); i++) { - gpiod_set_value(pdata->sgpio_gpiod[SDATA], sgpio_out & 1); - sgpio_out >>= 1; - ecx_led_cycle_clock(pdata); - } - for (i = 0; i < pdata->post_clocks; i++) - ecx_led_cycle_clock(pdata); - - /* save off new led state for port/slot */ - emp->led_state = state; - - spin_unlock_irqrestore(&sgpio_lock, flags); - return size; -} - -static void highbank_set_em_messages(struct device *dev, - struct ahci_host_priv *hpriv, - struct ata_port_info *pi) -{ - struct device_node *np = dev->of_node; - struct ecx_plat_data *pdata = hpriv->plat_data; - int i; - - for (i = 0; i < SGPIO_PINS; i++) { - struct gpio_desc *gpiod; - - gpiod = devm_gpiod_get_index(dev, "calxeda,sgpio", i, - GPIOD_OUT_HIGH); - if (IS_ERR(gpiod)) { - dev_err(dev, "failed to get GPIO %d\n", i); - continue; - } - gpiod_set_consumer_name(gpiod, "CX SGPIO"); - - pdata->sgpio_gpiod[i] = gpiod; - } - of_property_read_u32_array(np, "calxeda,led-order", - pdata->port_to_sgpio, - pdata->n_ports); - if (of_property_read_u32(np, "calxeda,pre-clocks", &pdata->pre_clocks)) - pdata->pre_clocks = 0; - if (of_property_read_u32(np, "calxeda,post-clocks", - &pdata->post_clocks)) - pdata->post_clocks = 0; - - /* store em_loc */ - hpriv->em_loc = 0; - hpriv->em_buf_sz = 4; - hpriv->em_msg_type = EM_MSG_TYPE_LED; - pi->flags |= ATA_FLAG_EM | ATA_FLAG_SW_ACTIVITY; -} - -static u32 __combo_phy_reg_read(u8 sata_port, u32 addr) -{ - u32 data; - u8 dev = port_data[sata_port].phy_devs; - spin_lock(&cphy_lock); - writel(CPHY_MAP(dev, addr), port_data[sata_port].phy_base + 0x800); - data = readl(port_data[sata_port].phy_base + CPHY_ADDR(addr)); - spin_unlock(&cphy_lock); - return data; -} - -static void __combo_phy_reg_write(u8 sata_port, u32 addr, u32 data) -{ - u8 dev = port_data[sata_port].phy_devs; - spin_lock(&cphy_lock); - writel(CPHY_MAP(dev, addr), port_data[sata_port].phy_base + 0x800); - writel(data, port_data[sata_port].phy_base + CPHY_ADDR(addr)); - spin_unlock(&cphy_lock); -} - -static void combo_phy_wait_for_ready(u8 sata_port) -{ - while (__combo_phy_reg_read(sata_port, SERDES_CR_CTL) & CR_BUSY) - udelay(5); -} - -static u32 combo_phy_read(u8 sata_port, u32 addr) -{ - combo_phy_wait_for_ready(sata_port); - __combo_phy_reg_write(sata_port, SERDES_CR_ADDR, addr); - __combo_phy_reg_write(sata_port, SERDES_CR_CTL, CR_START); - combo_phy_wait_for_ready(sata_port); - return __combo_phy_reg_read(sata_port, SERDES_CR_DATA); -} - -static void combo_phy_write(u8 sata_port, u32 addr, u32 data) -{ - combo_phy_wait_for_ready(sata_port); - __combo_phy_reg_write(sata_port, SERDES_CR_ADDR, addr); - __combo_phy_reg_write(sata_port, SERDES_CR_DATA, data); - __combo_phy_reg_write(sata_port, SERDES_CR_CTL, CR_WR_RDN | CR_START); -} - -static void highbank_cphy_disable_overrides(u8 sata_port) -{ - u8 lane = port_data[sata_port].lane_mapping; - u32 tmp; - if (unlikely(port_data[sata_port].phy_base == NULL)) - return; - tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS + lane * SPHY_LANE); - tmp &= ~CPHY_SATA_RX_OVERRIDE; - combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp); -} - -static void cphy_override_tx_attenuation(u8 sata_port, u32 val) -{ - u8 lane = port_data[sata_port].lane_mapping; - u32 tmp; - - if (val & 0x8) - return; - - tmp = combo_phy_read(sata_port, CPHY_TX_INPUT_STS + lane * SPHY_LANE); - tmp &= ~CPHY_SATA_TX_OVERRIDE; - combo_phy_write(sata_port, CPHY_TX_OVERRIDE + lane * SPHY_LANE, tmp); - - tmp |= CPHY_SATA_TX_OVERRIDE; - combo_phy_write(sata_port, CPHY_TX_OVERRIDE + lane * SPHY_LANE, tmp); - - tmp |= (val << CPHY_SATA_TX_ATTEN_SHIFT) & CPHY_SATA_TX_ATTEN; - combo_phy_write(sata_port, CPHY_TX_OVERRIDE + lane * SPHY_LANE, tmp); -} - -static void cphy_override_rx_mode(u8 sata_port, u32 val) -{ - u8 lane = port_data[sata_port].lane_mapping; - u32 tmp; - tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS + lane * SPHY_LANE); - tmp &= ~CPHY_SATA_RX_OVERRIDE; - combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp); - - tmp |= CPHY_SATA_RX_OVERRIDE; - combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp); - - tmp &= ~CPHY_SATA_DPLL_MODE; - tmp |= val << CPHY_SATA_DPLL_SHIFT; - combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp); - - tmp |= CPHY_SATA_DPLL_RESET; - combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp); - - tmp &= ~CPHY_SATA_DPLL_RESET; - combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp); - - msleep(15); -} - -static void highbank_cphy_override_lane(u8 sata_port) -{ - u8 lane = port_data[sata_port].lane_mapping; - u32 tmp, k = 0; - - if (unlikely(port_data[sata_port].phy_base == NULL)) - return; - do { - tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS + - lane * SPHY_LANE); - } while ((tmp & SPHY_HALF_RATE) && (k++ < 1000)); - cphy_override_rx_mode(sata_port, 3); - cphy_override_tx_attenuation(sata_port, port_data[sata_port].tx_atten); -} - -static int highbank_initialize_phys(struct device *dev, void __iomem *addr) -{ - struct device_node *sata_node = dev->of_node; - int phy_count = 0, phy, port = 0, i; - void __iomem *cphy_base[CPHY_PHY_COUNT] = {}; - struct device_node *phy_nodes[CPHY_PHY_COUNT] = {}; - u32 tx_atten[CPHY_PORT_COUNT] = {}; - - memset(port_data, 0, sizeof(struct phy_lane_info) * CPHY_PORT_COUNT); - - do { - u32 tmp; - struct of_phandle_args phy_data; - if (of_parse_phandle_with_args(sata_node, - "calxeda,port-phys", "#phy-cells", - port, &phy_data)) - break; - for (phy = 0; phy < phy_count; phy++) { - if (phy_nodes[phy] == phy_data.np) - break; - } - if (phy_nodes[phy] == NULL) { - phy_nodes[phy] = phy_data.np; - cphy_base[phy] = of_iomap(phy_nodes[phy], 0); - if (cphy_base[phy] == NULL) { - return 0; - } - phy_count += 1; - } - port_data[port].lane_mapping = phy_data.args[0]; - of_property_read_u32(phy_nodes[phy], "phydev", &tmp); - port_data[port].phy_devs = tmp; - port_data[port].phy_base = cphy_base[phy]; - of_node_put(phy_data.np); - port += 1; - } while (port < CPHY_PORT_COUNT); - of_property_read_u32_array(sata_node, "calxeda,tx-atten", - tx_atten, port); - for (i = 0; i < port; i++) - port_data[i].tx_atten = (u8) tx_atten[i]; - return 0; -} - -/* - * The Calxeda SATA phy intermittently fails to bring up a link with Gen3 - * Retrying the phy hard reset can work around the issue, but the drive - * may fail again. In less than 150 out of 15000 test runs, it took more - * than 10 tries for the link to be established (but never more than 35). - * Triple the maximum observed retry count to provide plenty of margin for - * rare events and to guarantee that the link is established. - * - * Also, the default 2 second time-out on a failed drive is too long in - * this situation. The uboot implementation of the same driver function - * uses a much shorter time-out period and never experiences a time out - * issue. Reducing the time-out to 500ms improves the responsiveness. - * The other timing constants were kept the same as the stock AHCI driver. - * This change was also tested 15000 times on 24 drives and none of them - * experienced a time out. - */ -static int ahci_highbank_hardreset(struct ata_link *link, unsigned int *class, - unsigned long deadline) -{ - static const unsigned long timing[] = { 5, 100, 500}; - struct ata_port *ap = link->ap; - struct ahci_port_priv *pp = ap->private_data; - struct ahci_host_priv *hpriv = ap->host->private_data; - u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; - struct ata_taskfile tf; - bool online; - u32 sstatus; - int rc; - int retry = 100; - - hpriv->stop_engine(ap); - - /* clear D2H reception area to properly wait for D2H FIS */ - ata_tf_init(link->device, &tf); - tf.command = ATA_BUSY; - ata_tf_to_fis(&tf, 0, 0, d2h_fis); - - do { - highbank_cphy_disable_overrides(link->ap->port_no); - rc = sata_link_hardreset(link, timing, deadline, &online, NULL); - highbank_cphy_override_lane(link->ap->port_no); - - /* If the status is 1, we are connected, but the link did not - * come up. So retry resetting the link again. - */ - if (sata_scr_read(link, SCR_STATUS, &sstatus)) - break; - if (!(sstatus & 0x3)) - break; - } while (!online && retry--); - - hpriv->start_engine(ap); - - if (online) - *class = ahci_dev_classify(ap); - - return rc; -} - -static struct ata_port_operations ahci_highbank_ops = { - .inherits = &ahci_ops, - .hardreset = ahci_highbank_hardreset, - .transmit_led_message = ecx_transmit_led_message, -}; - -static const struct ata_port_info ahci_highbank_port_info = { - .flags = AHCI_FLAG_COMMON, - .pio_mask = ATA_PIO4, - .udma_mask = ATA_UDMA6, - .port_ops = &ahci_highbank_ops, -}; - -static struct scsi_host_template ahci_highbank_platform_sht = { - AHCI_SHT("sata_highbank"), -}; - -static const struct of_device_id ahci_of_match[] = { - { .compatible = "calxeda,hb-ahci" }, - {}, -}; -MODULE_DEVICE_TABLE(of, ahci_of_match); - -static int ahci_highbank_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct ahci_host_priv *hpriv; - struct ecx_plat_data *pdata; - struct ata_host *host; - struct resource *mem; - int irq; - int i; - int rc; - u32 n_ports; - struct ata_port_info pi = ahci_highbank_port_info; - const struct ata_port_info *ppi[] = { &pi, NULL }; - - mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!mem) { - dev_err(dev, "no mmio space\n"); - return -EINVAL; - } - - irq = platform_get_irq(pdev, 0); - if (irq <= 0) { - dev_err(dev, "no irq\n"); - return -EINVAL; - } - - hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); - if (!hpriv) { - dev_err(dev, "can't alloc ahci_host_priv\n"); - return -ENOMEM; - } - pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); - if (!pdata) { - dev_err(dev, "can't alloc ecx_plat_data\n"); - return -ENOMEM; - } - - hpriv->irq = irq; - hpriv->flags |= (unsigned long)pi.private_data; - - hpriv->mmio = devm_ioremap(dev, mem->start, resource_size(mem)); - if (!hpriv->mmio) { - dev_err(dev, "can't map %pR\n", mem); - return -ENOMEM; - } - - rc = highbank_initialize_phys(dev, hpriv->mmio); - if (rc) - return rc; - - - ahci_save_initial_config(dev, hpriv); - - /* prepare host */ - if (hpriv->cap & HOST_CAP_NCQ) - pi.flags |= ATA_FLAG_NCQ; - - if (hpriv->cap & HOST_CAP_PMP) - pi.flags |= ATA_FLAG_PMP; - - if (hpriv->cap & HOST_CAP_64) - dma_set_coherent_mask(dev, DMA_BIT_MASK(64)); - - /* CAP.NP sometimes indicate the index of the last enabled - * port, at other times, that of the last possible port, so - * determining the maximum port number requires looking at - * both CAP.NP and port_map. - */ - n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map)); - - pdata->n_ports = n_ports; - hpriv->plat_data = pdata; - highbank_set_em_messages(dev, hpriv, &pi); - - host = ata_host_alloc_pinfo(dev, ppi, n_ports); - if (!host) { - rc = -ENOMEM; - goto err0; - } - - host->private_data = hpriv; - - if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss) - host->flags |= ATA_HOST_PARALLEL_SCAN; - - for (i = 0; i < host->n_ports; i++) { - struct ata_port *ap = host->ports[i]; - - ata_port_desc(ap, "mmio %pR", mem); - ata_port_desc(ap, "port 0x%x", 0x100 + ap->port_no * 0x80); - - /* set enclosure management message type */ - if (ap->flags & ATA_FLAG_EM) - ap->em_message_type = hpriv->em_msg_type; - - /* disabled/not-implemented port */ - if (!(hpriv->port_map & (1 << i))) - ap->ops = &ata_dummy_port_ops; - } - - rc = ahci_reset_controller(host); - if (rc) - goto err0; - - ahci_init_controller(host); - ahci_print_info(host, "platform"); - - rc = ahci_host_activate(host, &ahci_highbank_platform_sht); - if (rc) - goto err0; - - return 0; -err0: - return rc; -} - -#ifdef CONFIG_PM_SLEEP -static int ahci_highbank_suspend(struct device *dev) -{ - struct ata_host *host = dev_get_drvdata(dev); - struct ahci_host_priv *hpriv = host->private_data; - void __iomem *mmio = hpriv->mmio; - u32 ctl; - int rc; - - if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) { - dev_err(dev, "firmware update required for suspend/resume\n"); - return -EIO; - } - - /* - * AHCI spec rev1.1 section 8.3.3: - * Software must disable interrupts prior to requesting a - * transition of the HBA to D3 state. - */ - ctl = readl(mmio + HOST_CTL); - ctl &= ~HOST_IRQ_EN; - writel(ctl, mmio + HOST_CTL); - readl(mmio + HOST_CTL); /* flush */ - - rc = ata_host_suspend(host, PMSG_SUSPEND); - if (rc) - return rc; - - return 0; -} - -static int ahci_highbank_resume(struct device *dev) -{ - struct ata_host *host = dev_get_drvdata(dev); - int rc; - - if (dev->power.power_state.event == PM_EVENT_SUSPEND) { - rc = ahci_reset_controller(host); - if (rc) - return rc; - - ahci_init_controller(host); - } - - ata_host_resume(host); - - return 0; -} -#endif - -static SIMPLE_DEV_PM_OPS(ahci_highbank_pm_ops, - ahci_highbank_suspend, ahci_highbank_resume); - -static struct platform_driver ahci_highbank_driver = { - .remove = ata_platform_remove_one, - .driver = { - .name = "highbank-ahci", - .of_match_table = ahci_of_match, - .pm = &ahci_highbank_pm_ops, - }, - .probe = ahci_highbank_probe, -}; - -module_platform_driver(ahci_highbank_driver); - -MODULE_DESCRIPTION("Calxeda Highbank AHCI SATA platform driver"); -MODULE_AUTHOR("Mark Langsdorf "); -MODULE_LICENSE("GPL"); -MODULE_ALIAS("sata:highbank"); From patchwork Tue Feb 18 17:13:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring \(Arm\)" X-Patchwork-Id: 212818 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B8AB7C34055 for ; Tue, 18 Feb 2020 17:14:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 88018208C4 for ; Tue, 18 Feb 2020 17:14:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; 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[24.155.109.49]) by smtp.googlemail.com with ESMTPSA id y25sm1545755oto.27.2020.02.18.09.13.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Feb 2020 09:13:31 -0800 (PST) From: Rob Herring To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, soc@kernel.org, Andre Przywara , Robert Richter , Jon Loeliger , Alexander Graf , Matthias Brugger , Mark Langsdorf Cc: Alex Williamson , Borislav Petkov , Cornelia Huck , Daniel Lezcano , "David S. Miller" , devicetree@vger.kernel.org, Eric Auger , iommu@lists.linux-foundation.org, James Morse , Jens Axboe , Joerg Roedel , kvm@vger.kernel.org, linux-clk@vger.kernel.org, linux-edac@vger.kernel.org, linux-ide@vger.kernel.org, linux-pm@vger.kernel.org, Mauro Carvalho Chehab , netdev@vger.kernel.org, "Rafael J. Wysocki" , Robin Murphy , Stephen Boyd , Tony Luck , Viresh Kumar , Will Deacon Subject: [RFC PATCH 05/11] EDAC: Remove Calxeda drivers Date: Tue, 18 Feb 2020 11:13:15 -0600 Message-Id: <20200218171321.30990-6-robh@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200218171321.30990-1-robh@kernel.org> References: <20200218171321.30990-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Cc: Borislav Petkov Cc: Mauro Carvalho Chehab Cc: Tony Luck Cc: James Morse Cc: Robert Richter Cc: linux-edac@vger.kernel.org Signed-off-by: Rob Herring --- Do not apply yet. MAINTAINERS | 6 - drivers/edac/Kconfig | 14 -- drivers/edac/Makefile | 3 - drivers/edac/highbank_l2_edac.c | 142 ----------------- drivers/edac/highbank_mc_edac.c | 272 -------------------------------- 5 files changed, 437 deletions(-) delete mode 100644 drivers/edac/highbank_l2_edac.c delete mode 100644 drivers/edac/highbank_mc_edac.c -- 2.20.1 diff --git a/MAINTAINERS b/MAINTAINERS index a0d86490c2c6..4732bb268299 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5964,12 +5964,6 @@ M: Shravan Kumar Ramani S: Supported F: drivers/edac/bluefield_edac.c -EDAC-CALXEDA -M: Robert Richter -L: linux-edac@vger.kernel.org -S: Maintained -F: drivers/edac/highbank* - EDAC-CAVIUM OCTEON M: Ralf Baechle M: Robert Richter diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index b3c99bb5fe77..f3ff75e5ed9b 100644 --- a/drivers/edac/Kconfig +++ b/drivers/edac/Kconfig @@ -334,20 +334,6 @@ config EDAC_CPC925 a companion chip to the PowerPC 970 family of processors. -config EDAC_HIGHBANK_MC - tristate "Highbank Memory Controller" - depends on ARCH_HIGHBANK - help - Support for error detection and correction on the - Calxeda Highbank memory controller. - -config EDAC_HIGHBANK_L2 - tristate "Highbank L2 Cache" - depends on ARCH_HIGHBANK - help - Support for error detection and correction on the - Calxeda Highbank memory controller. - config EDAC_OCTEON_PC tristate "Cavium Octeon Primary Caches" depends on CPU_CAVIUM_OCTEON diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile index d77200c9680b..9a563db39bc3 100644 --- a/drivers/edac/Makefile +++ b/drivers/edac/Makefile @@ -69,9 +69,6 @@ obj-$(CONFIG_EDAC_PPC4XX) += ppc4xx_edac.o obj-$(CONFIG_EDAC_AMD8111) += amd8111_edac.o obj-$(CONFIG_EDAC_AMD8131) += amd8131_edac.o -obj-$(CONFIG_EDAC_HIGHBANK_MC) += highbank_mc_edac.o -obj-$(CONFIG_EDAC_HIGHBANK_L2) += highbank_l2_edac.o - obj-$(CONFIG_EDAC_OCTEON_PC) += octeon_edac-pc.o obj-$(CONFIG_EDAC_OCTEON_L2C) += octeon_edac-l2c.o obj-$(CONFIG_EDAC_OCTEON_LMC) += octeon_edac-lmc.o diff --git a/drivers/edac/highbank_l2_edac.c b/drivers/edac/highbank_l2_edac.c deleted file mode 100644 index c4549cec788b..000000000000 --- a/drivers/edac/highbank_l2_edac.c +++ /dev/null @@ -1,142 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2011-2012 Calxeda, Inc. - */ -#include -#include -#include -#include -#include -#include -#include - -#include "edac_module.h" - -#define SR_CLR_SB_ECC_INTR 0x0 -#define SR_CLR_DB_ECC_INTR 0x4 - -struct hb_l2_drvdata { - void __iomem *base; - int sb_irq; - int db_irq; -}; - -static irqreturn_t highbank_l2_err_handler(int irq, void *dev_id) -{ - struct edac_device_ctl_info *dci = dev_id; - struct hb_l2_drvdata *drvdata = dci->pvt_info; - - if (irq == drvdata->sb_irq) { - writel(1, drvdata->base + SR_CLR_SB_ECC_INTR); - edac_device_handle_ce(dci, 0, 0, dci->ctl_name); - } - if (irq == drvdata->db_irq) { - writel(1, drvdata->base + SR_CLR_DB_ECC_INTR); - edac_device_handle_ue(dci, 0, 0, dci->ctl_name); - } - - return IRQ_HANDLED; -} - -static const struct of_device_id hb_l2_err_of_match[] = { - { .compatible = "calxeda,hb-sregs-l2-ecc", }, - {}, -}; -MODULE_DEVICE_TABLE(of, hb_l2_err_of_match); - -static int highbank_l2_err_probe(struct platform_device *pdev) -{ - const struct of_device_id *id; - struct edac_device_ctl_info *dci; - struct hb_l2_drvdata *drvdata; - struct resource *r; - int res = 0; - - dci = edac_device_alloc_ctl_info(sizeof(*drvdata), "cpu", - 1, "L", 1, 2, NULL, 0, 0); - if (!dci) - return -ENOMEM; - - drvdata = dci->pvt_info; - dci->dev = &pdev->dev; - platform_set_drvdata(pdev, dci); - - if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) - return -ENOMEM; - - r = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!r) { - dev_err(&pdev->dev, "Unable to get mem resource\n"); - res = -ENODEV; - goto err; - } - - if (!devm_request_mem_region(&pdev->dev, r->start, - resource_size(r), dev_name(&pdev->dev))) { - dev_err(&pdev->dev, "Error while requesting mem region\n"); - res = -EBUSY; - goto err; - } - - drvdata->base = devm_ioremap(&pdev->dev, r->start, resource_size(r)); - if (!drvdata->base) { - dev_err(&pdev->dev, "Unable to map regs\n"); - res = -ENOMEM; - goto err; - } - - id = of_match_device(hb_l2_err_of_match, &pdev->dev); - dci->mod_name = pdev->dev.driver->name; - dci->ctl_name = id ? id->compatible : "unknown"; - dci->dev_name = dev_name(&pdev->dev); - - if (edac_device_add_device(dci)) - goto err; - - drvdata->db_irq = platform_get_irq(pdev, 0); - res = devm_request_irq(&pdev->dev, drvdata->db_irq, - highbank_l2_err_handler, - 0, dev_name(&pdev->dev), dci); - if (res < 0) - goto err2; - - drvdata->sb_irq = platform_get_irq(pdev, 1); - res = devm_request_irq(&pdev->dev, drvdata->sb_irq, - highbank_l2_err_handler, - 0, dev_name(&pdev->dev), dci); - if (res < 0) - goto err2; - - devres_close_group(&pdev->dev, NULL); - return 0; -err2: - edac_device_del_device(&pdev->dev); -err: - devres_release_group(&pdev->dev, NULL); - edac_device_free_ctl_info(dci); - return res; -} - -static int highbank_l2_err_remove(struct platform_device *pdev) -{ - struct edac_device_ctl_info *dci = platform_get_drvdata(pdev); - - edac_device_del_device(&pdev->dev); - edac_device_free_ctl_info(dci); - return 0; -} - -static struct platform_driver highbank_l2_edac_driver = { - .probe = highbank_l2_err_probe, - .remove = highbank_l2_err_remove, - .driver = { - .name = "hb_l2_edac", - .of_match_table = hb_l2_err_of_match, - }, -}; - -module_platform_driver(highbank_l2_edac_driver); - -MODULE_LICENSE("GPL v2"); -MODULE_AUTHOR("Calxeda, Inc."); -MODULE_DESCRIPTION("EDAC Driver for Calxeda Highbank L2 Cache"); diff --git a/drivers/edac/highbank_mc_edac.c b/drivers/edac/highbank_mc_edac.c deleted file mode 100644 index 61b76ec226af..000000000000 --- a/drivers/edac/highbank_mc_edac.c +++ /dev/null @@ -1,272 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2011-2012 Calxeda, Inc. - */ -#include -#include -#include -#include -#include -#include -#include -#include - -#include "edac_module.h" - -/* DDR Ctrlr Error Registers */ - -#define HB_DDR_ECC_ERR_BASE 0x128 -#define MW_DDR_ECC_ERR_BASE 0x1b4 - -#define HB_DDR_ECC_OPT 0x00 -#define HB_DDR_ECC_U_ERR_ADDR 0x08 -#define HB_DDR_ECC_U_ERR_STAT 0x0c -#define HB_DDR_ECC_U_ERR_DATAL 0x10 -#define HB_DDR_ECC_U_ERR_DATAH 0x14 -#define HB_DDR_ECC_C_ERR_ADDR 0x18 -#define HB_DDR_ECC_C_ERR_STAT 0x1c -#define HB_DDR_ECC_C_ERR_DATAL 0x20 -#define HB_DDR_ECC_C_ERR_DATAH 0x24 - -#define HB_DDR_ECC_OPT_MODE_MASK 0x3 -#define HB_DDR_ECC_OPT_FWC 0x100 -#define HB_DDR_ECC_OPT_XOR_SHIFT 16 - -/* DDR Ctrlr Interrupt Registers */ - -#define HB_DDR_ECC_INT_BASE 0x180 -#define MW_DDR_ECC_INT_BASE 0x218 - -#define HB_DDR_ECC_INT_STATUS 0x00 -#define HB_DDR_ECC_INT_ACK 0x04 - -#define HB_DDR_ECC_INT_STAT_CE 0x8 -#define HB_DDR_ECC_INT_STAT_DOUBLE_CE 0x10 -#define HB_DDR_ECC_INT_STAT_UE 0x20 -#define HB_DDR_ECC_INT_STAT_DOUBLE_UE 0x40 - -struct hb_mc_drvdata { - void __iomem *mc_err_base; - void __iomem *mc_int_base; -}; - -static irqreturn_t highbank_mc_err_handler(int irq, void *dev_id) -{ - struct mem_ctl_info *mci = dev_id; - struct hb_mc_drvdata *drvdata = mci->pvt_info; - u32 status, err_addr; - - /* Read the interrupt status register */ - status = readl(drvdata->mc_int_base + HB_DDR_ECC_INT_STATUS); - - if (status & HB_DDR_ECC_INT_STAT_UE) { - err_addr = readl(drvdata->mc_err_base + HB_DDR_ECC_U_ERR_ADDR); - edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, - err_addr >> PAGE_SHIFT, - err_addr & ~PAGE_MASK, 0, - 0, 0, -1, - mci->ctl_name, ""); - } - if (status & HB_DDR_ECC_INT_STAT_CE) { - u32 syndrome = readl(drvdata->mc_err_base + HB_DDR_ECC_C_ERR_STAT); - syndrome = (syndrome >> 8) & 0xff; - err_addr = readl(drvdata->mc_err_base + HB_DDR_ECC_C_ERR_ADDR); - edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, - err_addr >> PAGE_SHIFT, - err_addr & ~PAGE_MASK, syndrome, - 0, 0, -1, - mci->ctl_name, ""); - } - - /* clear the error, clears the interrupt */ - writel(status, drvdata->mc_int_base + HB_DDR_ECC_INT_ACK); - return IRQ_HANDLED; -} - -static void highbank_mc_err_inject(struct mem_ctl_info *mci, u8 synd) -{ - struct hb_mc_drvdata *pdata = mci->pvt_info; - u32 reg; - - reg = readl(pdata->mc_err_base + HB_DDR_ECC_OPT); - reg &= HB_DDR_ECC_OPT_MODE_MASK; - reg |= (synd << HB_DDR_ECC_OPT_XOR_SHIFT) | HB_DDR_ECC_OPT_FWC; - writel(reg, pdata->mc_err_base + HB_DDR_ECC_OPT); -} - -#define to_mci(k) container_of(k, struct mem_ctl_info, dev) - -static ssize_t highbank_mc_inject_ctrl(struct device *dev, - struct device_attribute *attr, const char *buf, size_t count) -{ - struct mem_ctl_info *mci = to_mci(dev); - u8 synd; - - if (kstrtou8(buf, 16, &synd)) - return -EINVAL; - - highbank_mc_err_inject(mci, synd); - - return count; -} - -static DEVICE_ATTR(inject_ctrl, S_IWUSR, NULL, highbank_mc_inject_ctrl); - -static struct attribute *highbank_dev_attrs[] = { - &dev_attr_inject_ctrl.attr, - NULL -}; - -ATTRIBUTE_GROUPS(highbank_dev); - -struct hb_mc_settings { - int err_offset; - int int_offset; -}; - -static struct hb_mc_settings hb_settings = { - .err_offset = HB_DDR_ECC_ERR_BASE, - .int_offset = HB_DDR_ECC_INT_BASE, -}; - -static struct hb_mc_settings mw_settings = { - .err_offset = MW_DDR_ECC_ERR_BASE, - .int_offset = MW_DDR_ECC_INT_BASE, -}; - -static const struct of_device_id hb_ddr_ctrl_of_match[] = { - { .compatible = "calxeda,hb-ddr-ctrl", .data = &hb_settings }, - { .compatible = "calxeda,ecx-2000-ddr-ctrl", .data = &mw_settings }, - {}, -}; -MODULE_DEVICE_TABLE(of, hb_ddr_ctrl_of_match); - -static int highbank_mc_probe(struct platform_device *pdev) -{ - const struct of_device_id *id; - const struct hb_mc_settings *settings; - struct edac_mc_layer layers[2]; - struct mem_ctl_info *mci; - struct hb_mc_drvdata *drvdata; - struct dimm_info *dimm; - struct resource *r; - void __iomem *base; - u32 control; - int irq; - int res = 0; - - id = of_match_device(hb_ddr_ctrl_of_match, &pdev->dev); - if (!id) - return -ENODEV; - - layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; - layers[0].size = 1; - layers[0].is_virt_csrow = true; - layers[1].type = EDAC_MC_LAYER_CHANNEL; - layers[1].size = 1; - layers[1].is_virt_csrow = false; - mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, - sizeof(struct hb_mc_drvdata)); - if (!mci) - return -ENOMEM; - - mci->pdev = &pdev->dev; - drvdata = mci->pvt_info; - platform_set_drvdata(pdev, mci); - - if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) - return -ENOMEM; - - r = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!r) { - dev_err(&pdev->dev, "Unable to get mem resource\n"); - res = -ENODEV; - goto err; - } - - if (!devm_request_mem_region(&pdev->dev, r->start, - resource_size(r), dev_name(&pdev->dev))) { - dev_err(&pdev->dev, "Error while requesting mem region\n"); - res = -EBUSY; - goto err; - } - - base = devm_ioremap(&pdev->dev, r->start, resource_size(r)); - if (!base) { - dev_err(&pdev->dev, "Unable to map regs\n"); - res = -ENOMEM; - goto err; - } - - settings = id->data; - drvdata->mc_err_base = base + settings->err_offset; - drvdata->mc_int_base = base + settings->int_offset; - - control = readl(drvdata->mc_err_base + HB_DDR_ECC_OPT) & 0x3; - if (!control || (control == 0x2)) { - dev_err(&pdev->dev, "No ECC present, or ECC disabled\n"); - res = -ENODEV; - goto err; - } - - mci->mtype_cap = MEM_FLAG_DDR3; - mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; - mci->edac_cap = EDAC_FLAG_SECDED; - mci->mod_name = pdev->dev.driver->name; - mci->ctl_name = id->compatible; - mci->dev_name = dev_name(&pdev->dev); - mci->scrub_mode = SCRUB_SW_SRC; - - /* Only a single 4GB DIMM is supported */ - dimm = *mci->dimms; - dimm->nr_pages = (~0UL >> PAGE_SHIFT) + 1; - dimm->grain = 8; - dimm->dtype = DEV_X8; - dimm->mtype = MEM_DDR3; - dimm->edac_mode = EDAC_SECDED; - - res = edac_mc_add_mc_with_groups(mci, highbank_dev_groups); - if (res < 0) - goto err; - - irq = platform_get_irq(pdev, 0); - res = devm_request_irq(&pdev->dev, irq, highbank_mc_err_handler, - 0, dev_name(&pdev->dev), mci); - if (res < 0) { - dev_err(&pdev->dev, "Unable to request irq %d\n", irq); - goto err2; - } - - devres_close_group(&pdev->dev, NULL); - return 0; -err2: - edac_mc_del_mc(&pdev->dev); -err: - devres_release_group(&pdev->dev, NULL); - edac_mc_free(mci); - return res; -} - -static int highbank_mc_remove(struct platform_device *pdev) -{ - struct mem_ctl_info *mci = platform_get_drvdata(pdev); - - edac_mc_del_mc(&pdev->dev); - edac_mc_free(mci); - return 0; -} - -static struct platform_driver highbank_mc_edac_driver = { - .probe = highbank_mc_probe, - .remove = highbank_mc_remove, - .driver = { - .name = "hb_mc_edac", - .of_match_table = hb_ddr_ctrl_of_match, - }, -}; - -module_platform_driver(highbank_mc_edac_driver); - -MODULE_LICENSE("GPL v2"); -MODULE_AUTHOR("Calxeda, Inc."); -MODULE_DESCRIPTION("EDAC Driver for Calxeda Highbank"); From patchwork Tue Feb 18 17:13:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring \(Arm\)" X-Patchwork-Id: 212819 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4116C3404E for ; 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[24.155.109.49]) by smtp.googlemail.com with ESMTPSA id y25sm1545755oto.27.2020.02.18.09.13.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Feb 2020 09:13:36 -0800 (PST) From: Rob Herring To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, soc@kernel.org, Andre Przywara , Robert Richter , Jon Loeliger , Alexander Graf , Matthias Brugger , Mark Langsdorf Cc: Alex Williamson , Borislav Petkov , Cornelia Huck , Daniel Lezcano , "David S. Miller" , devicetree@vger.kernel.org, Eric Auger , iommu@lists.linux-foundation.org, James Morse , Jens Axboe , Joerg Roedel , kvm@vger.kernel.org, linux-clk@vger.kernel.org, linux-edac@vger.kernel.org, linux-ide@vger.kernel.org, linux-pm@vger.kernel.org, Mauro Carvalho Chehab , netdev@vger.kernel.org, "Rafael J. Wysocki" , Robin Murphy , Stephen Boyd , Tony Luck , Viresh Kumar , Will Deacon Subject: [RFC PATCH 08/11] clk: Remove Calxeda driver Date: Tue, 18 Feb 2020 11:13:18 -0600 Message-Id: <20200218171321.30990-9-robh@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200218171321.30990-1-robh@kernel.org> References: <20200218171321.30990-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Cc: Stephen Boyd Cc: linux-clk@vger.kernel.org Signed-off-by: Rob Herring --- Do not apply yet. drivers/clk/Makefile | 1 - drivers/clk/clk-highbank.c | 329 ------------------------------------- 2 files changed, 330 deletions(-) delete mode 100644 drivers/clk/clk-highbank.c -- 2.20.1 diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index f4169cc2fd31..cb71dfaf1ac7 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -33,7 +33,6 @@ obj-$(CONFIG_COMMON_CLK_FSL_SAI) += clk-fsl-sai.o obj-$(CONFIG_COMMON_CLK_GEMINI) += clk-gemini.o obj-$(CONFIG_COMMON_CLK_ASPEED) += clk-aspeed.o obj-$(CONFIG_MACH_ASPEED_G6) += clk-ast2600.o -obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o obj-$(CONFIG_CLK_HSDK) += clk-hsdk-pll.o obj-$(CONFIG_COMMON_CLK_LOCHNAGAR) += clk-lochnagar.o obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o diff --git a/drivers/clk/clk-highbank.c b/drivers/clk/clk-highbank.c deleted file mode 100644 index 2a0cea2946f9..000000000000 --- a/drivers/clk/clk-highbank.c +++ /dev/null @@ -1,329 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2011-2012 Calxeda, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include - -#define HB_PLL_LOCK_500 0x20000000 -#define HB_PLL_LOCK 0x10000000 -#define HB_PLL_DIVF_SHIFT 20 -#define HB_PLL_DIVF_MASK 0x0ff00000 -#define HB_PLL_DIVQ_SHIFT 16 -#define HB_PLL_DIVQ_MASK 0x00070000 -#define HB_PLL_DIVR_SHIFT 8 -#define HB_PLL_DIVR_MASK 0x00001f00 -#define HB_PLL_RANGE_SHIFT 4 -#define HB_PLL_RANGE_MASK 0x00000070 -#define HB_PLL_BYPASS 0x00000008 -#define HB_PLL_RESET 0x00000004 -#define HB_PLL_EXT_BYPASS 0x00000002 -#define HB_PLL_EXT_ENA 0x00000001 - -#define HB_PLL_VCO_MIN_FREQ 2133000000 -#define HB_PLL_MAX_FREQ HB_PLL_VCO_MIN_FREQ -#define HB_PLL_MIN_FREQ (HB_PLL_VCO_MIN_FREQ / 64) - -#define HB_A9_BCLK_DIV_MASK 0x00000006 -#define HB_A9_BCLK_DIV_SHIFT 1 -#define HB_A9_PCLK_DIV 0x00000001 - -struct hb_clk { - struct clk_hw hw; - void __iomem *reg; - char *parent_name; -}; -#define to_hb_clk(p) container_of(p, struct hb_clk, hw) - -static int clk_pll_prepare(struct clk_hw *hwclk) - { - struct hb_clk *hbclk = to_hb_clk(hwclk); - u32 reg; - - reg = readl(hbclk->reg); - reg &= ~HB_PLL_RESET; - writel(reg, hbclk->reg); - - while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0) - ; - while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0) - ; - - return 0; -} - -static void clk_pll_unprepare(struct clk_hw *hwclk) -{ - struct hb_clk *hbclk = to_hb_clk(hwclk); - u32 reg; - - reg = readl(hbclk->reg); - reg |= HB_PLL_RESET; - writel(reg, hbclk->reg); -} - -static int clk_pll_enable(struct clk_hw *hwclk) -{ - struct hb_clk *hbclk = to_hb_clk(hwclk); - u32 reg; - - reg = readl(hbclk->reg); - reg |= HB_PLL_EXT_ENA; - writel(reg, hbclk->reg); - - return 0; -} - -static void clk_pll_disable(struct clk_hw *hwclk) -{ - struct hb_clk *hbclk = to_hb_clk(hwclk); - u32 reg; - - reg = readl(hbclk->reg); - reg &= ~HB_PLL_EXT_ENA; - writel(reg, hbclk->reg); -} - -static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk, - unsigned long parent_rate) -{ - struct hb_clk *hbclk = to_hb_clk(hwclk); - unsigned long divf, divq, vco_freq, reg; - - reg = readl(hbclk->reg); - if (reg & HB_PLL_EXT_BYPASS) - return parent_rate; - - divf = (reg & HB_PLL_DIVF_MASK) >> HB_PLL_DIVF_SHIFT; - divq = (reg & HB_PLL_DIVQ_MASK) >> HB_PLL_DIVQ_SHIFT; - vco_freq = parent_rate * (divf + 1); - - return vco_freq / (1 << divq); -} - -static void clk_pll_calc(unsigned long rate, unsigned long ref_freq, - u32 *pdivq, u32 *pdivf) -{ - u32 divq, divf; - unsigned long vco_freq; - - if (rate < HB_PLL_MIN_FREQ) - rate = HB_PLL_MIN_FREQ; - if (rate > HB_PLL_MAX_FREQ) - rate = HB_PLL_MAX_FREQ; - - for (divq = 1; divq <= 6; divq++) { - if ((rate * (1 << divq)) >= HB_PLL_VCO_MIN_FREQ) - break; - } - - vco_freq = rate * (1 << divq); - divf = (vco_freq + (ref_freq / 2)) / ref_freq; - divf--; - - *pdivq = divq; - *pdivf = divf; -} - -static long clk_pll_round_rate(struct clk_hw *hwclk, unsigned long rate, - unsigned long *parent_rate) -{ - u32 divq, divf; - unsigned long ref_freq = *parent_rate; - - clk_pll_calc(rate, ref_freq, &divq, &divf); - - return (ref_freq * (divf + 1)) / (1 << divq); -} - -static int clk_pll_set_rate(struct clk_hw *hwclk, unsigned long rate, - unsigned long parent_rate) -{ - struct hb_clk *hbclk = to_hb_clk(hwclk); - u32 divq, divf; - u32 reg; - - clk_pll_calc(rate, parent_rate, &divq, &divf); - - reg = readl(hbclk->reg); - if (divf != ((reg & HB_PLL_DIVF_MASK) >> HB_PLL_DIVF_SHIFT)) { - /* Need to re-lock PLL, so put it into bypass mode */ - reg |= HB_PLL_EXT_BYPASS; - writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg); - - writel(reg | HB_PLL_RESET, hbclk->reg); - reg &= ~(HB_PLL_DIVF_MASK | HB_PLL_DIVQ_MASK); - reg |= (divf << HB_PLL_DIVF_SHIFT) | (divq << HB_PLL_DIVQ_SHIFT); - writel(reg | HB_PLL_RESET, hbclk->reg); - writel(reg, hbclk->reg); - - while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0) - ; - while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0) - ; - reg |= HB_PLL_EXT_ENA; - reg &= ~HB_PLL_EXT_BYPASS; - } else { - writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg); - reg &= ~HB_PLL_DIVQ_MASK; - reg |= divq << HB_PLL_DIVQ_SHIFT; - writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg); - } - writel(reg, hbclk->reg); - - return 0; -} - -static const struct clk_ops clk_pll_ops = { - .prepare = clk_pll_prepare, - .unprepare = clk_pll_unprepare, - .enable = clk_pll_enable, - .disable = clk_pll_disable, - .recalc_rate = clk_pll_recalc_rate, - .round_rate = clk_pll_round_rate, - .set_rate = clk_pll_set_rate, -}; - -static unsigned long clk_cpu_periphclk_recalc_rate(struct clk_hw *hwclk, - unsigned long parent_rate) -{ - struct hb_clk *hbclk = to_hb_clk(hwclk); - u32 div = (readl(hbclk->reg) & HB_A9_PCLK_DIV) ? 8 : 4; - return parent_rate / div; -} - -static const struct clk_ops a9periphclk_ops = { - .recalc_rate = clk_cpu_periphclk_recalc_rate, -}; - -static unsigned long clk_cpu_a9bclk_recalc_rate(struct clk_hw *hwclk, - unsigned long parent_rate) -{ - struct hb_clk *hbclk = to_hb_clk(hwclk); - u32 div = (readl(hbclk->reg) & HB_A9_BCLK_DIV_MASK) >> HB_A9_BCLK_DIV_SHIFT; - - return parent_rate / (div + 2); -} - -static const struct clk_ops a9bclk_ops = { - .recalc_rate = clk_cpu_a9bclk_recalc_rate, -}; - -static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk, - unsigned long parent_rate) -{ - struct hb_clk *hbclk = to_hb_clk(hwclk); - u32 div; - - div = readl(hbclk->reg) & 0x1f; - div++; - div *= 2; - - return parent_rate / div; -} - -static long clk_periclk_round_rate(struct clk_hw *hwclk, unsigned long rate, - unsigned long *parent_rate) -{ - u32 div; - - div = *parent_rate / rate; - div++; - div &= ~0x1; - - return *parent_rate / div; -} - -static int clk_periclk_set_rate(struct clk_hw *hwclk, unsigned long rate, - unsigned long parent_rate) -{ - struct hb_clk *hbclk = to_hb_clk(hwclk); - u32 div; - - div = parent_rate / rate; - if (div & 0x1) - return -EINVAL; - - writel(div >> 1, hbclk->reg); - return 0; -} - -static const struct clk_ops periclk_ops = { - .recalc_rate = clk_periclk_recalc_rate, - .round_rate = clk_periclk_round_rate, - .set_rate = clk_periclk_set_rate, -}; - -static void __init hb_clk_init(struct device_node *node, const struct clk_ops *ops, unsigned long clkflags) -{ - u32 reg; - struct hb_clk *hb_clk; - const char *clk_name = node->name; - const char *parent_name; - struct clk_init_data init; - struct device_node *srnp; - int rc; - - rc = of_property_read_u32(node, "reg", ®); - if (WARN_ON(rc)) - return; - - hb_clk = kzalloc(sizeof(*hb_clk), GFP_KERNEL); - if (WARN_ON(!hb_clk)) - return; - - /* Map system registers */ - srnp = of_find_compatible_node(NULL, NULL, "calxeda,hb-sregs"); - hb_clk->reg = of_iomap(srnp, 0); - of_node_put(srnp); - BUG_ON(!hb_clk->reg); - hb_clk->reg += reg; - - of_property_read_string(node, "clock-output-names", &clk_name); - - init.name = clk_name; - init.ops = ops; - init.flags = clkflags; - parent_name = of_clk_get_parent_name(node, 0); - init.parent_names = &parent_name; - init.num_parents = 1; - - hb_clk->hw.init = &init; - - rc = clk_hw_register(NULL, &hb_clk->hw); - if (WARN_ON(rc)) { - kfree(hb_clk); - return; - } - of_clk_add_hw_provider(node, of_clk_hw_simple_get, &hb_clk->hw); -} - -static void __init hb_pll_init(struct device_node *node) -{ - hb_clk_init(node, &clk_pll_ops, 0); -} -CLK_OF_DECLARE(hb_pll, "calxeda,hb-pll-clock", hb_pll_init); - -static void __init hb_a9periph_init(struct device_node *node) -{ - hb_clk_init(node, &a9periphclk_ops, 0); -} -CLK_OF_DECLARE(hb_a9periph, "calxeda,hb-a9periph-clock", hb_a9periph_init); - -static void __init hb_a9bus_init(struct device_node *node) -{ - hb_clk_init(node, &a9bclk_ops, CLK_IS_CRITICAL); -} -CLK_OF_DECLARE(hb_a9bus, "calxeda,hb-a9bus-clock", hb_a9bus_init); - -static void __init hb_emmc_init(struct device_node *node) -{ - hb_clk_init(node, &periclk_ops, 0); -} -CLK_OF_DECLARE(hb_emmc, "calxeda,hb-emmc-clock", hb_emmc_init); From patchwork Tue Feb 18 17:13:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring \(Arm\)" X-Patchwork-Id: 212820 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 61B84C3404C for ; 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[24.155.109.49]) by smtp.googlemail.com with ESMTPSA id y25sm1545755oto.27.2020.02.18.09.13.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Feb 2020 09:13:37 -0800 (PST) From: Rob Herring To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, soc@kernel.org, Andre Przywara , Robert Richter , Jon Loeliger , Alexander Graf , Matthias Brugger , Mark Langsdorf Cc: Alex Williamson , Borislav Petkov , Cornelia Huck , Daniel Lezcano , "David S. Miller" , devicetree@vger.kernel.org, Eric Auger , iommu@lists.linux-foundation.org, James Morse , Jens Axboe , Joerg Roedel , kvm@vger.kernel.org, linux-clk@vger.kernel.org, linux-edac@vger.kernel.org, linux-ide@vger.kernel.org, linux-pm@vger.kernel.org, Mauro Carvalho Chehab , netdev@vger.kernel.org, "Rafael J. Wysocki" , Robin Murphy , Stephen Boyd , Tony Luck , Viresh Kumar , Will Deacon Subject: [RFC PATCH 09/11] ARM: Remove Calxeda platform support Date: Tue, 18 Feb 2020 11:13:19 -0600 Message-Id: <20200218171321.30990-10-robh@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200218171321.30990-1-robh@kernel.org> References: <20200218171321.30990-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Signed-off-by: Rob Herring --- MAINTAINERS | 8 -- arch/arm/Kconfig | 2 - arch/arm/Kconfig.debug | 12 +- arch/arm/Makefile | 1 - arch/arm/configs/multi_v7_defconfig | 5 - arch/arm/mach-highbank/Kconfig | 19 --- arch/arm/mach-highbank/Makefile | 4 - arch/arm/mach-highbank/core.h | 18 --- arch/arm/mach-highbank/highbank.c | 175 ---------------------------- arch/arm/mach-highbank/pm.c | 49 -------- arch/arm/mach-highbank/smc.S | 25 ---- arch/arm/mach-highbank/sysregs.h | 75 ------------ arch/arm/mach-highbank/system.c | 22 ---- 13 files changed, 1 insertion(+), 414 deletions(-) delete mode 100644 arch/arm/mach-highbank/Kconfig delete mode 100644 arch/arm/mach-highbank/Makefile delete mode 100644 arch/arm/mach-highbank/core.h delete mode 100644 arch/arm/mach-highbank/highbank.c delete mode 100644 arch/arm/mach-highbank/pm.c delete mode 100644 arch/arm/mach-highbank/smc.S delete mode 100644 arch/arm/mach-highbank/sysregs.h delete mode 100644 arch/arm/mach-highbank/system.c diff --git a/MAINTAINERS b/MAINTAINERS index 4732bb268299..551aaa9d2dab 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1604,14 +1604,6 @@ F: Documentation/devicetree/bindings/arm/bitmain.yaml F: Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.yaml F: Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.txt -ARM/CALXEDA HIGHBANK ARCHITECTURE -M: Rob Herring -L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -S: Maintained -F: arch/arm/mach-highbank/ -F: arch/arm/boot/dts/highbank.dts -F: arch/arm/boot/dts/ecx-*.dts* - ARM/CAVIUM NETWORKS CNS3XXX MACHINE SUPPORT M: Krzysztof Halasa S: Maintained diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 97864aabc2a6..6f8ce7b38a46 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -640,8 +640,6 @@ source "arch/arm/mach-footbridge/Kconfig" source "arch/arm/mach-gemini/Kconfig" -source "arch/arm/mach-highbank/Kconfig" - source "arch/arm/mach-hisi/Kconfig" source "arch/arm/mach-imx/Kconfig" diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index b70d7debf5ca..66413f98cae9 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -346,14 +346,6 @@ choice Say Y here if you want kernel low-level debugging support on HI3620 UART. - config DEBUG_HIGHBANK_UART - bool "Kernel low-level debugging messages via Highbank UART" - depends on ARCH_HIGHBANK - select DEBUG_UART_PL01X - help - Say Y here if you want the debug print routines to direct - their output to the UART on Highbank based devices. - config DEBUG_HIP01_UART bool "Hisilicon Hip01 Debug UART" depends on ARCH_HIP01 @@ -1692,7 +1684,6 @@ config DEBUG_UART_PHYS default 0xffc03000 if DEBUG_SOCFPGA_CYCLONE5_UART1 default 0xffe40000 if DEBUG_RCAR_GEN1_SCIF0 default 0xffe42000 if DEBUG_RCAR_GEN1_SCIF2 - default 0xfff36000 if DEBUG_HIGHBANK_UART default 0xfffb0000 if DEBUG_OMAP1UART1 || DEBUG_OMAP7XXUART1 default 0xfffb0800 if DEBUG_OMAP1UART2 || DEBUG_OMAP7XXUART2 default 0xfffb9800 if DEBUG_OMAP1UART3 || DEBUG_OMAP7XXUART3 @@ -1810,7 +1801,6 @@ config DEBUG_UART_VIRT default 0xfee20000 if DEBUG_NSPIRE_CLASSIC_UART || DEBUG_NSPIRE_CX_UART default 0xfef00000 if ARCH_IXP4XX && !CPU_BIG_ENDIAN default 0xfef00003 if ARCH_IXP4XX && CPU_BIG_ENDIAN - default 0xfef36000 if DEBUG_HIGHBANK_UART default 0xfefb0000 if DEBUG_OMAP1UART1 || DEBUG_OMAP7XXUART1 default 0xfefb0800 if DEBUG_OMAP1UART2 || DEBUG_OMAP7XXUART2 default 0xfefb9800 if DEBUG_OMAP1UART3 || DEBUG_OMAP7XXUART3 @@ -1873,7 +1863,7 @@ config DEBUG_UNCOMPRESS When this option is set, the selected DEBUG_LL output method will be re-used for normal decompressor output on multiplatform kernels. - + config UNCOMPRESS_INCLUDE string diff --git a/arch/arm/Makefile b/arch/arm/Makefile index db857d07114f..fa3bc920e3ac 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -178,7 +178,6 @@ machine-$(CONFIG_ARCH_EP93XX) += ep93xx machine-$(CONFIG_ARCH_EXYNOS) += exynos machine-$(CONFIG_ARCH_FOOTBRIDGE) += footbridge machine-$(CONFIG_ARCH_GEMINI) += gemini -machine-$(CONFIG_ARCH_HIGHBANK) += highbank machine-$(CONFIG_ARCH_HISI) += hisi machine-$(CONFIG_ARCH_INTEGRATOR) += integrator machine-$(CONFIG_ARCH_IOP32X) += iop32x diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 017d65f86eba..69eb62f831c7 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -31,7 +31,6 @@ CONFIG_MACH_BERLIN_BG2CD=y CONFIG_MACH_BERLIN_BG2Q=y CONFIG_ARCH_DIGICOLOR=y CONFIG_ARCH_EXYNOS=y -CONFIG_ARCH_HIGHBANK=y CONFIG_ARCH_HISI=y CONFIG_ARCH_HI3xxx=y CONFIG_ARCH_HIP01=y @@ -236,7 +235,6 @@ CONFIG_AHCI_ST=y CONFIG_AHCI_IMX=y CONFIG_AHCI_SUNXI=y CONFIG_AHCI_TEGRA=y -CONFIG_SATA_HIGHBANK=y CONFIG_SATA_MV=y CONFIG_SATA_RCAR=y CONFIG_NETDEVICES=y @@ -250,7 +248,6 @@ CONFIG_BCMGENET=m CONFIG_BGMAC_BCMA=y CONFIG_SYSTEMPORT=m CONFIG_MACB=y -CONFIG_NET_CALXEDA_XGMAC=y CONFIG_FTGMAC100=m CONFIG_GIANFAR=y CONFIG_HIX5HD2_GMAC=y @@ -866,8 +863,6 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=y CONFIG_LEDS_TRIGGER_TRANSIENT=y CONFIG_LEDS_TRIGGER_CAMERA=y CONFIG_EDAC=y -CONFIG_EDAC_HIGHBANK_MC=y -CONFIG_EDAC_HIGHBANK_L2=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_AC100=y CONFIG_RTC_DRV_AS3722=y diff --git a/arch/arm/mach-highbank/Kconfig b/arch/arm/mach-highbank/Kconfig deleted file mode 100644 index 1bc68913d62c..000000000000 --- a/arch/arm/mach-highbank/Kconfig +++ /dev/null @@ -1,19 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -config ARCH_HIGHBANK - bool "Calxeda ECX-1000/2000 (Highbank/Midway)" - depends on ARCH_MULTI_V7 - select ARCH_HAS_HOLES_MEMORYMODEL - select ARCH_SUPPORTS_BIG_ENDIAN - select ARM_AMBA - select ARM_ERRATA_764369 if SMP - select ARM_ERRATA_775420 - select ARM_ERRATA_798181 if SMP - select ARM_GIC - select ARM_PSCI - select ARM_TIMER_SP804 - select CACHE_L2X0 - select HAVE_ARM_SCU - select HAVE_ARM_TWD if SMP - select MAILBOX - select PL320_MBOX - select ZONE_DMA if ARM_LPAE diff --git a/arch/arm/mach-highbank/Makefile b/arch/arm/mach-highbank/Makefile deleted file mode 100644 index 71cc68041d92..000000000000 --- a/arch/arm/mach-highbank/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -obj-y := highbank.o system.o smc.o - -obj-$(CONFIG_PM_SLEEP) += pm.o diff --git a/arch/arm/mach-highbank/core.h b/arch/arm/mach-highbank/core.h deleted file mode 100644 index 3991a6594ae5..000000000000 --- a/arch/arm/mach-highbank/core.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __HIGHBANK_CORE_H -#define __HIGHBANK_CORE_H - -#include - -extern void highbank_restart(enum reboot_mode, const char *); -extern void __iomem *scu_base_addr; - -#ifdef CONFIG_PM_SLEEP -extern void highbank_pm_init(void); -#else -static inline void highbank_pm_init(void) {} -#endif - -extern void highbank_smc1(int fn, int arg); - -#endif diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c deleted file mode 100644 index 56bf29523c65..000000000000 --- a/arch/arm/mach-highbank/highbank.c +++ /dev/null @@ -1,175 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2010-2011 Calxeda, Inc. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "core.h" -#include "sysregs.h" - -void __iomem *sregs_base; -void __iomem *scu_base_addr; - -static void __init highbank_scu_map_io(void) -{ - unsigned long base; - - /* Get SCU base */ - asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base)); - - scu_base_addr = ioremap(base, SZ_4K); -} - - -static void highbank_l2c310_write_sec(unsigned long val, unsigned reg) -{ - if (reg == L2X0_CTRL) - highbank_smc1(0x102, val); - else - WARN_ONCE(1, "Highbank L2C310: ignoring write to reg 0x%x\n", - reg); -} - -static void __init highbank_init_irq(void) -{ - irqchip_init(); - - if (of_find_compatible_node(NULL, NULL, "arm,cortex-a9")) - highbank_scu_map_io(); -} - -static void highbank_power_off(void) -{ - highbank_set_pwr_shutdown(); - - while (1) - cpu_do_idle(); -} - -static int highbank_platform_notifier(struct notifier_block *nb, - unsigned long event, void *__dev) -{ - struct resource *res; - int reg = -1; - u32 val; - struct device *dev = __dev; - - if (event != BUS_NOTIFY_ADD_DEVICE) - return NOTIFY_DONE; - - if (of_device_is_compatible(dev->of_node, "calxeda,hb-ahci")) - reg = 0xc; - else if (of_device_is_compatible(dev->of_node, "calxeda,hb-sdhci")) - reg = 0x18; - else if (of_device_is_compatible(dev->of_node, "arm,pl330")) - reg = 0x20; - else if (of_device_is_compatible(dev->of_node, "calxeda,hb-xgmac")) { - res = platform_get_resource(to_platform_device(dev), - IORESOURCE_MEM, 0); - if (res) { - if (res->start == 0xfff50000) - reg = 0; - else if (res->start == 0xfff51000) - reg = 4; - } - } - - if (reg < 0) - return NOTIFY_DONE; - - if (of_property_read_bool(dev->of_node, "dma-coherent")) { - val = readl(sregs_base + reg); - writel(val | 0xff01, sregs_base + reg); - set_dma_ops(dev, &arm_coherent_dma_ops); - } - - return NOTIFY_OK; -} - -static struct notifier_block highbank_amba_nb = { - .notifier_call = highbank_platform_notifier, -}; - -static struct notifier_block highbank_platform_nb = { - .notifier_call = highbank_platform_notifier, -}; - -static struct platform_device highbank_cpuidle_device = { - .name = "cpuidle-calxeda", -}; - -static int hb_keys_notifier(struct notifier_block *nb, unsigned long event, void *data) -{ - u32 key = *(u32 *)data; - - if (event != 0x1000) - return 0; - - if (key == KEY_POWER) - orderly_poweroff(false); - else if (key == 0xffff) - ctrl_alt_del(); - - return 0; -} -static struct notifier_block hb_keys_nb = { - .notifier_call = hb_keys_notifier, -}; - -static void __init highbank_init(void) -{ - struct device_node *np; - - /* Map system registers */ - np = of_find_compatible_node(NULL, NULL, "calxeda,hb-sregs"); - sregs_base = of_iomap(np, 0); - WARN_ON(!sregs_base); - - pm_power_off = highbank_power_off; - highbank_pm_init(); - - bus_register_notifier(&platform_bus_type, &highbank_platform_nb); - bus_register_notifier(&amba_bustype, &highbank_amba_nb); - - pl320_ipc_register_notifier(&hb_keys_nb); - - if (psci_ops.cpu_suspend) - platform_device_register(&highbank_cpuidle_device); -} - -static const char *const highbank_match[] __initconst = { - "calxeda,highbank", - "calxeda,ecx-2000", - NULL, -}; - -DT_MACHINE_START(HIGHBANK, "Highbank") -#if defined(CONFIG_ZONE_DMA) && defined(CONFIG_ARM_LPAE) - .dma_zone_size = (4ULL * SZ_1G), -#endif - .l2c_aux_val = 0, - .l2c_aux_mask = ~0, - .l2c_write_sec = highbank_l2c310_write_sec, - .init_irq = highbank_init_irq, - .init_machine = highbank_init, - .dt_compat = highbank_match, - .restart = highbank_restart, -MACHINE_END diff --git a/arch/arm/mach-highbank/pm.c b/arch/arm/mach-highbank/pm.c deleted file mode 100644 index 561941baeda9..000000000000 --- a/arch/arm/mach-highbank/pm.c +++ /dev/null @@ -1,49 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2011 Calxeda, Inc. - */ - -#include -#include -#include -#include - -#include - -#include - -#define HIGHBANK_SUSPEND_PARAM \ - ((0 << PSCI_0_2_POWER_STATE_ID_SHIFT) | \ - (1 << PSCI_0_2_POWER_STATE_AFFL_SHIFT) | \ - (PSCI_POWER_STATE_TYPE_POWER_DOWN << PSCI_0_2_POWER_STATE_TYPE_SHIFT)) - -static int highbank_suspend_finish(unsigned long val) -{ - return psci_ops.cpu_suspend(HIGHBANK_SUSPEND_PARAM, __pa(cpu_resume)); -} - -static int highbank_pm_enter(suspend_state_t state) -{ - cpu_pm_enter(); - cpu_cluster_pm_enter(); - - cpu_suspend(0, highbank_suspend_finish); - - cpu_cluster_pm_exit(); - cpu_pm_exit(); - - return 0; -} - -static const struct platform_suspend_ops highbank_pm_ops = { - .enter = highbank_pm_enter, - .valid = suspend_valid_only_mem, -}; - -void __init highbank_pm_init(void) -{ - if (!psci_ops.cpu_suspend) - return; - - suspend_set_ops(&highbank_pm_ops); -} diff --git a/arch/arm/mach-highbank/smc.S b/arch/arm/mach-highbank/smc.S deleted file mode 100644 index 78b3f19e7f37..000000000000 --- a/arch/arm/mach-highbank/smc.S +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copied from omap44xx-smc.S Copyright (C) 2010 Texas Instruments, Inc. - * Copyright 2012 Calxeda, Inc. - */ - -#include - -/* - * This is common routine to manage secure monitor API - * used to modify the PL310 secure registers. - * 'r0' contains the value to be modified and 'r12' contains - * the monitor API number. - * Function signature : void highbank_smc1(u32 fn, u32 arg) - */ - .arch armv7-a - .arch_extension sec -ENTRY(highbank_smc1) - stmfd sp!, {r4-r11, lr} - mov r12, r0 - mov r0, r1 - dsb - smc #0 - ldmfd sp!, {r4-r11, pc} -ENDPROC(highbank_smc1) diff --git a/arch/arm/mach-highbank/sysregs.h b/arch/arm/mach-highbank/sysregs.h deleted file mode 100644 index 3c13fdcafb1e..000000000000 --- a/arch/arm/mach-highbank/sysregs.h +++ /dev/null @@ -1,75 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2011 Calxeda, Inc. - */ -#ifndef _MACH_HIGHBANK__SYSREGS_H_ -#define _MACH_HIGHBANK__SYSREGS_H_ - -#include -#include -#include -#include -#include "core.h" - -extern void __iomem *sregs_base; - -#define HB_SREG_A9_PWR_REQ 0xf00 -#define HB_SREG_A9_BOOT_STAT 0xf04 -#define HB_SREG_A9_BOOT_DATA 0xf08 - -#define HB_PWR_SUSPEND 0 -#define HB_PWR_SOFT_RESET 1 -#define HB_PWR_HARD_RESET 2 -#define HB_PWR_SHUTDOWN 3 - -#define SREG_CPU_PWR_CTRL(c) (0x200 + ((c) * 4)) - -static inline void highbank_set_core_pwr(void) -{ - int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0); - if (scu_base_addr) - scu_power_mode(scu_base_addr, SCU_PM_POWEROFF); - else - writel_relaxed(1, sregs_base + SREG_CPU_PWR_CTRL(cpu)); -} - -static inline void highbank_clear_core_pwr(void) -{ - int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0); - if (scu_base_addr) - scu_power_mode(scu_base_addr, SCU_PM_NORMAL); - else - writel_relaxed(0, sregs_base + SREG_CPU_PWR_CTRL(cpu)); -} - -static inline void highbank_set_pwr_suspend(void) -{ - writel(HB_PWR_SUSPEND, sregs_base + HB_SREG_A9_PWR_REQ); - highbank_set_core_pwr(); -} - -static inline void highbank_set_pwr_shutdown(void) -{ - writel(HB_PWR_SHUTDOWN, sregs_base + HB_SREG_A9_PWR_REQ); - highbank_set_core_pwr(); -} - -static inline void highbank_set_pwr_soft_reset(void) -{ - writel(HB_PWR_SOFT_RESET, sregs_base + HB_SREG_A9_PWR_REQ); - highbank_set_core_pwr(); -} - -static inline void highbank_set_pwr_hard_reset(void) -{ - writel(HB_PWR_HARD_RESET, sregs_base + HB_SREG_A9_PWR_REQ); - highbank_set_core_pwr(); -} - -static inline void highbank_clear_pwr_request(void) -{ - writel(~0UL, sregs_base + HB_SREG_A9_PWR_REQ); - highbank_clear_core_pwr(); -} - -#endif diff --git a/arch/arm/mach-highbank/system.c b/arch/arm/mach-highbank/system.c deleted file mode 100644 index b749c4a6ddf5..000000000000 --- a/arch/arm/mach-highbank/system.c +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2011 Calxeda, Inc. - */ -#include -#include -#include - -#include "core.h" -#include "sysregs.h" - -void highbank_restart(enum reboot_mode mode, const char *cmd) -{ - if (mode == REBOOT_HARD) - highbank_set_pwr_hard_reset(); - else - highbank_set_pwr_soft_reset(); - - while (1) - cpu_do_idle(); -} - From patchwork Tue Feb 18 17:13:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring \(Arm\)" X-Patchwork-Id: 212821 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 435B4C34048 for ; Tue, 18 Feb 2020 17:13:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0B316208C4 for ; Tue, 18 Feb 2020 17:13:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1582046031; bh=bM8YN2ZfJudIpOdoYqa4P1Zkj3Pg0uPLLJygiEJ4s1o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=mMiuEAYhSGYZWcbldxTVhafzFlL4YDjGUYLzhsX03xdTKkkTW+SrwSD80dNebhIjF yopN+vNZcz7/284xOkjc6VdpAhzX46DlYdYTGLedNhlvc2SWSXNTnA8Pn+pf7++dI1 FzriyXutWvgXk6tSDwsP/7M3uebKuOdjaR7hFoTI= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727785AbgBRRNn (ORCPT ); Tue, 18 Feb 2020 12:13:43 -0500 Received: from mail-ot1-f65.google.com ([209.85.210.65]:34869 "EHLO mail-ot1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727727AbgBRRNm (ORCPT ); Tue, 18 Feb 2020 12:13:42 -0500 Received: by mail-ot1-f65.google.com with SMTP id r16so20278718otd.2; Tue, 18 Feb 2020 09:13:40 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FoqaseM22NqKzdP6diWbwHzzLAglDjPvVApnWfidhno=; b=cVH/YljX8Fkq2glbR+L1DlM9yhbPK0scnU/5LTLA5XkubLGU8P23KmW/yU8PSbXXuT kEz/+jI7IYaGu1/kI1WHtiMHqBAxM+jG4gvzaplsQrjJv5snxsdW69BsvD1o1K+udpSp 1i+tilKQsTu1Yqgem8z+zPgmy8GYDcMLgdNb2Za90ouceJT9W9EVMRL4JSPYDjJX0KKe XDMk3WnKcPmOXCDCnYOPqi4AMUZ7hO6/u9WYvu9TeC624hz8W06GnxqpYKYLVSXpoDtZ Qau8/bQlxCkcpqlqt6XY6qL0UEVdjtK3iQYXP+J3xcpChDmddLuFbgzrZTa7mBd/XezD Nw0Q== X-Gm-Message-State: APjAAAU/Bo3DNEb119gvRHV8oWRbfH0a9rj1BfKSzYyN9+v515fXluYZ XVHIKwobc9LDb0NXKoSlaw== X-Google-Smtp-Source: APXvYqw4vgSmdpsSYxMVMymSrQmGp8BN32RULVNjVRuf9KGXenrEyhdhKj6dTUd1/cfRh69w0KzQXA== X-Received: by 2002:a9d:de9:: with SMTP id 96mr16562460ots.222.1582046020074; Tue, 18 Feb 2020 09:13:40 -0800 (PST) Received: from xps15.herring.priv (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.googlemail.com with ESMTPSA id y25sm1545755oto.27.2020.02.18.09.13.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Feb 2020 09:13:39 -0800 (PST) From: Rob Herring To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, soc@kernel.org, Andre Przywara , Robert Richter , Jon Loeliger , Alexander Graf , Matthias Brugger , Mark Langsdorf Cc: Alex Williamson , Borislav Petkov , Cornelia Huck , Daniel Lezcano , "David S. Miller" , devicetree@vger.kernel.org, Eric Auger , iommu@lists.linux-foundation.org, James Morse , Jens Axboe , Joerg Roedel , kvm@vger.kernel.org, linux-clk@vger.kernel.org, linux-edac@vger.kernel.org, linux-ide@vger.kernel.org, linux-pm@vger.kernel.org, Mauro Carvalho Chehab , netdev@vger.kernel.org, "Rafael J. Wysocki" , Robin Murphy , Stephen Boyd , Tony Luck , Viresh Kumar , Will Deacon Subject: [RFC PATCH 10/11] ARM: dts: Remove Calxeda platforms Date: Tue, 18 Feb 2020 11:13:20 -0600 Message-Id: <20200218171321.30990-11-robh@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200218171321.30990-1-robh@kernel.org> References: <20200218171321.30990-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Rob Herring --- arch/arm/boot/dts/Makefile | 3 - arch/arm/boot/dts/ecx-2000.dts | 103 ------------- arch/arm/boot/dts/ecx-common.dtsi | 230 ------------------------------ arch/arm/boot/dts/highbank.dts | 161 --------------------- 4 files changed, 497 deletions(-) delete mode 100644 arch/arm/boot/dts/ecx-2000.dts delete mode 100644 arch/arm/boot/dts/ecx-common.dtsi delete mode 100644 arch/arm/boot/dts/highbank.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index d6546d2676b9..a78da2e25966 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -224,9 +224,6 @@ dtb-$(CONFIG_ARCH_GEMINI) += \ gemini-wbd222.dtb dtb-$(CONFIG_ARCH_HI3xxx) += \ hi3620-hi4511.dtb -dtb-$(CONFIG_ARCH_HIGHBANK) += \ - highbank.dtb \ - ecx-2000.dtb dtb-$(CONFIG_ARCH_HIP01) += \ hip01-ca9x2.dtb dtb-$(CONFIG_ARCH_HIP04) += \ diff --git a/arch/arm/boot/dts/ecx-2000.dts b/arch/arm/boot/dts/ecx-2000.dts deleted file mode 100644 index 5651ae6dc969..000000000000 --- a/arch/arm/boot/dts/ecx-2000.dts +++ /dev/null @@ -1,103 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2011-2012 Calxeda, Inc. - */ - -/dts-v1/; - -/* First 4KB has pen for secondary cores. */ -/memreserve/ 0x00000000 0x0001000; - -/ { - model = "Calxeda ECX-2000"; - compatible = "calxeda,ecx-2000"; - #address-cells = <2>; - #size-cells = <2>; - clock-ranges; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <0>; - clocks = <&a9pll>; - clock-names = "cpu"; - }; - - cpu@1 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <1>; - clocks = <&a9pll>; - clock-names = "cpu"; - }; - - cpu@2 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <2>; - clocks = <&a9pll>; - clock-names = "cpu"; - }; - - cpu@3 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <3>; - clocks = <&a9pll>; - clock-names = "cpu"; - }; - }; - - memory@0 { - name = "memory"; - device_type = "memory"; - reg = <0x00000000 0x00000000 0x00000000 0xff800000>; - }; - - memory@200000000 { - name = "memory"; - device_type = "memory"; - reg = <0x00000002 0x00000000 0x00000003 0x00000000>; - }; - - soc { - ranges = <0x00000000 0x00000000 0x00000000 0xffffffff>; - - timer { - compatible = "arm,cortex-a15-timer", "arm,armv7-timer"; interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; - }; - - memory-controller@fff00000 { - compatible = "calxeda,ecx-2000-ddr-ctrl"; - reg = <0xfff00000 0x1000>; - interrupts = <0 91 4>; - }; - - intc: interrupt-controller@fff11000 { - compatible = "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - #size-cells = <0>; - #address-cells = <1>; - interrupt-controller; - interrupts = <1 9 0xf04>; - reg = <0xfff11000 0x1000>, - <0xfff12000 0x2000>, - <0xfff14000 0x2000>, - <0xfff16000 0x2000>; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>; - }; - }; -}; - -/include/ "ecx-common.dtsi" diff --git a/arch/arm/boot/dts/ecx-common.dtsi b/arch/arm/boot/dts/ecx-common.dtsi deleted file mode 100644 index 66ee1d34f72b..000000000000 --- a/arch/arm/boot/dts/ecx-common.dtsi +++ /dev/null @@ -1,230 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2011-2012 Calxeda, Inc. - */ - -/ { - chosen { - bootargs = "console=ttyAMA0"; - }; - - psci { - compatible = "arm,psci"; - method = "smc"; - cpu_suspend = <0x84000002>; - cpu_off = <0x84000004>; - cpu_on = <0x84000006>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&intc>; - - sata@ffe08000 { - compatible = "calxeda,hb-ahci"; - reg = <0xffe08000 0x10000>; - interrupts = <0 83 4>; - dma-coherent; - calxeda,port-phys = <&combophy5 0 &combophy0 0 - &combophy0 1 &combophy0 2 - &combophy0 3>; - calxeda,sgpio-gpio =<&gpioh 5 1 &gpioh 6 1 &gpioh 7 1>; - calxeda,led-order = <4 0 1 2 3>; - }; - - sdhci@ffe0e000 { - compatible = "calxeda,hb-sdhci"; - reg = <0xffe0e000 0x1000>; - interrupts = <0 90 4>; - clocks = <&eclk>; - status = "disabled"; - }; - - ipc@fff20000 { - compatible = "arm,pl320", "arm,primecell"; - reg = <0xfff20000 0x1000>; - interrupts = <0 7 4>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - gpioe: gpio@fff30000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0xfff30000 0x1000>; - interrupts = <0 14 4>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpiof: gpio@fff31000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0xfff31000 0x1000>; - interrupts = <0 15 4>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpiog: gpio@fff32000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0xfff32000 0x1000>; - interrupts = <0 16 4>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpioh: gpio@fff33000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0xfff33000 0x1000>; - interrupts = <0 17 4>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - timer@fff34000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0xfff34000 0x1000>; - interrupts = <0 18 4>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - rtc@fff35000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0xfff35000 0x1000>; - interrupts = <0 19 4>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - serial@fff36000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xfff36000 0x1000>; - interrupts = <0 20 4>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - smic@fff3a000 { - compatible = "ipmi-smic"; - device_type = "ipmi"; - reg = <0xfff3a000 0x1000>; - interrupts = <0 24 4>; - reg-size = <4>; - reg-spacing = <4>; - }; - - sregs@fff3c000 { - compatible = "calxeda,hb-sregs"; - reg = <0xfff3c000 0x1000>; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - osc: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <33333000>; - }; - - ddrpll: ddrpll { - #clock-cells = <0>; - compatible = "calxeda,hb-pll-clock"; - clocks = <&osc>; - reg = <0x108>; - }; - - a9pll: a9pll { - #clock-cells = <0>; - compatible = "calxeda,hb-pll-clock"; - clocks = <&osc>; - reg = <0x100>; - }; - - a9periphclk: a9periphclk { - #clock-cells = <0>; - compatible = "calxeda,hb-a9periph-clock"; - clocks = <&a9pll>; - reg = <0x104>; - }; - - a9bclk: a9bclk { - #clock-cells = <0>; - compatible = "calxeda,hb-a9bus-clock"; - clocks = <&a9pll>; - reg = <0x104>; - }; - - emmcpll: emmcpll { - #clock-cells = <0>; - compatible = "calxeda,hb-pll-clock"; - clocks = <&osc>; - reg = <0x10C>; - }; - - eclk: eclk { - #clock-cells = <0>; - compatible = "calxeda,hb-emmc-clock"; - clocks = <&emmcpll>; - reg = <0x114>; - }; - - pclk: pclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <150000000>; - }; - }; - }; - - dma@fff3d000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0xfff3d000 0x1000>; - interrupts = <0 92 4>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - ethernet@fff50000 { - compatible = "calxeda,hb-xgmac"; - reg = <0xfff50000 0x1000>; - interrupts = <0 77 4 0 78 4 0 79 4>; - dma-coherent; - }; - - ethernet@fff51000 { - compatible = "calxeda,hb-xgmac"; - reg = <0xfff51000 0x1000>; - interrupts = <0 80 4 0 81 4 0 82 4>; - dma-coherent; - }; - - combophy0: combo-phy@fff58000 { - compatible = "calxeda,hb-combophy"; - #phy-cells = <1>; - reg = <0xfff58000 0x1000>; - phydev = <5>; - }; - - combophy5: combo-phy@fff5d000 { - compatible = "calxeda,hb-combophy"; - #phy-cells = <1>; - reg = <0xfff5d000 0x1000>; - phydev = <31>; - }; - }; -}; diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts deleted file mode 100644 index f4e4dca6f7e7..000000000000 --- a/arch/arm/boot/dts/highbank.dts +++ /dev/null @@ -1,161 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2011-2012 Calxeda, Inc. - */ - -/dts-v1/; - -/* First 4KB has pen for secondary cores. */ -/memreserve/ 0x00000000 0x0001000; - -/ { - model = "Calxeda Highbank"; - compatible = "calxeda,highbank"; - #address-cells = <1>; - #size-cells = <1>; - clock-ranges; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@900 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0x900>; - next-level-cache = <&L2>; - clocks = <&a9pll>; - clock-names = "cpu"; - operating-points = < - /* kHz ignored */ - 1300000 1000000 - 1200000 1000000 - 1100000 1000000 - 800000 1000000 - 400000 1000000 - 200000 1000000 - >; - clock-latency = <100000>; - }; - - cpu@901 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0x901>; - next-level-cache = <&L2>; - clocks = <&a9pll>; - clock-names = "cpu"; - operating-points = < - /* kHz ignored */ - 1300000 1000000 - 1200000 1000000 - 1100000 1000000 - 800000 1000000 - 400000 1000000 - 200000 1000000 - >; - clock-latency = <100000>; - }; - - cpu@902 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0x902>; - next-level-cache = <&L2>; - clocks = <&a9pll>; - clock-names = "cpu"; - operating-points = < - /* kHz ignored */ - 1300000 1000000 - 1200000 1000000 - 1100000 1000000 - 800000 1000000 - 400000 1000000 - 200000 1000000 - >; - clock-latency = <100000>; - }; - - cpu@903 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0x903>; - next-level-cache = <&L2>; - clocks = <&a9pll>; - clock-names = "cpu"; - operating-points = < - /* kHz ignored */ - 1300000 1000000 - 1200000 1000000 - 1100000 1000000 - 800000 1000000 - 400000 1000000 - 200000 1000000 - >; - clock-latency = <100000>; - }; - }; - - memory { - name = "memory"; - device_type = "memory"; - reg = <0x00000000 0xff900000>; - }; - - soc { - ranges = <0x00000000 0x00000000 0xffffffff>; - - memory-controller@fff00000 { - compatible = "calxeda,hb-ddr-ctrl"; - reg = <0xfff00000 0x1000>; - interrupts = <0 91 4>; - }; - - timer@fff10600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xfff10600 0x20>; - interrupts = <1 13 0xf01>; - clocks = <&a9periphclk>; - }; - - watchdog@fff10620 { - compatible = "arm,cortex-a9-twd-wdt"; - reg = <0xfff10620 0x20>; - interrupts = <1 14 0xf01>; - clocks = <&a9periphclk>; - }; - - intc: interrupt-controller@fff11000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #size-cells = <0>; - #address-cells = <1>; - interrupt-controller; - reg = <0xfff11000 0x1000>, - <0xfff10100 0x100>; - }; - - L2: l2-cache { - compatible = "arm,pl310-cache"; - reg = <0xfff12000 0x1000>; - interrupts = <0 70 4>; - cache-unified; - cache-level = <2>; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>; - }; - - - sregs@fff3c200 { - compatible = "calxeda,hb-sregs-l2-ecc"; - reg = <0xfff3c200 0x100>; - interrupts = <0 71 4 0 72 4>; - }; - - }; -}; - -/include/ "ecx-common.dtsi"