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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id s68sm412051pfd.72.2017.09.07.11.19.40 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Sep 2017 11:19:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 7 Sep 2017 11:19:35 -0700 Message-Id: <20170907181938.3948-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170907181938.3948-1-richard.henderson@linaro.org> References: <20170907181938.3948-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::229 Subject: [Qemu-devel] [PULL 1/4] target/alpha: Convert to DisasJumpType X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson --- target/alpha/translate.c | 132 ++++++++++++++++++++--------------------------- 1 file changed, 55 insertions(+), 77 deletions(-) -- 2.13.5 diff --git a/target/alpha/translate.c b/target/alpha/translate.c index f465752208..a75bf5dd90 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -25,11 +25,10 @@ #include "exec/exec-all.h" #include "tcg-op.h" #include "exec/cpu_ldst.h" - #include "exec/helper-proto.h" #include "exec/helper-gen.h" - #include "trace-tcg.h" +#include "exec/translator.h" #include "exec/log.h" @@ -73,32 +72,12 @@ struct DisasContext { bool singlestep_enabled; }; -/* Return values from translate_one, indicating the state of the TB. - Note that zero indicates that we are not exiting the TB. */ - -typedef enum { - NO_EXIT, - - /* We have emitted one or more goto_tb. No fixup required. */ - EXIT_GOTO_TB, - - /* We are not using a goto_tb (for whatever reason), but have updated - the PC (for whatever reason), so there's no need to do it again on - exiting the TB. */ - EXIT_PC_UPDATED, - EXIT_PC_UPDATED_NOCHAIN, - - /* We are exiting the TB, but have neither emitted a goto_tb, nor - updated the PC for the next instruction to be executed. */ - EXIT_PC_STALE, - - /* We are exiting the TB due to page crossing or space constraints. */ - EXIT_FALLTHRU, - - /* We are ending the TB with a noreturn function call, e.g. longjmp. - No following code will be executed. */ - EXIT_NORETURN, -} ExitStatus; +/* Target-specific return values from translate_one, indicating the + state of the TB. Note that DISAS_NEXT indicates that we are not + exiting the TB. */ +#define DISAS_PC_UPDATED_NOCHAIN DISAS_TARGET_0 +#define DISAS_PC_UPDATED DISAS_TARGET_1 +#define DISAS_PC_STALE DISAS_TARGET_2 /* global register indexes */ static TCGv_env cpu_env; @@ -301,14 +280,14 @@ static void gen_excp_1(int exception, int error_code) tcg_temp_free_i32(tmp1); } -static ExitStatus gen_excp(DisasContext *ctx, int exception, int error_code) +static DisasJumpType gen_excp(DisasContext *ctx, int exception, int error_code) { tcg_gen_movi_i64(cpu_pc, ctx->pc); gen_excp_1(exception, error_code); - return EXIT_NORETURN; + return DISAS_NORETURN; } -static inline ExitStatus gen_invalid(DisasContext *ctx) +static inline DisasJumpType gen_invalid(DisasContext *ctx) { return gen_excp(ctx, EXCP_OPCDEC, 0); } @@ -434,9 +413,9 @@ static inline void gen_store_mem(DisasContext *ctx, tcg_temp_free(tmp); } -static ExitStatus gen_store_conditional(DisasContext *ctx, int ra, int rb, - int32_t disp16, int mem_idx, - TCGMemOp op) +static DisasJumpType gen_store_conditional(DisasContext *ctx, int ra, int rb, + int32_t disp16, int mem_idx, + TCGMemOp op) { TCGLabel *lab_fail, *lab_done; TCGv addr, val; @@ -468,7 +447,7 @@ static ExitStatus gen_store_conditional(DisasContext *ctx, int ra, int rb, gen_set_label(lab_done); tcg_gen_movi_i64(cpu_lock_addr, -1); - return NO_EXIT; + return DISAS_NEXT; } static bool in_superpage(DisasContext *ctx, int64_t addr) @@ -507,7 +486,7 @@ static bool use_goto_tb(DisasContext *ctx, uint64_t dest) #endif } -static ExitStatus gen_bdirect(DisasContext *ctx, int ra, int32_t disp) +static DisasJumpType gen_bdirect(DisasContext *ctx, int ra, int32_t disp) { uint64_t dest = ctx->pc + (disp << 2); @@ -522,15 +501,15 @@ static ExitStatus gen_bdirect(DisasContext *ctx, int ra, int32_t disp) tcg_gen_goto_tb(0); tcg_gen_movi_i64(cpu_pc, dest); tcg_gen_exit_tb((uintptr_t)ctx->tb); - return EXIT_GOTO_TB; + return DISAS_NORETURN; } else { tcg_gen_movi_i64(cpu_pc, dest); - return EXIT_PC_UPDATED; + return DISAS_PC_UPDATED; } } -static ExitStatus gen_bcond_internal(DisasContext *ctx, TCGCond cond, - TCGv cmp, int32_t disp) +static DisasJumpType gen_bcond_internal(DisasContext *ctx, TCGCond cond, + TCGv cmp, int32_t disp) { uint64_t dest = ctx->pc + (disp << 2); TCGLabel *lab_true = gen_new_label(); @@ -547,7 +526,7 @@ static ExitStatus gen_bcond_internal(DisasContext *ctx, TCGCond cond, tcg_gen_movi_i64(cpu_pc, dest); tcg_gen_exit_tb((uintptr_t)ctx->tb + 1); - return EXIT_GOTO_TB; + return DISAS_NORETURN; } else { TCGv_i64 z = tcg_const_i64(0); TCGv_i64 d = tcg_const_i64(dest); @@ -558,16 +537,16 @@ static ExitStatus gen_bcond_internal(DisasContext *ctx, TCGCond cond, tcg_temp_free_i64(z); tcg_temp_free_i64(d); tcg_temp_free_i64(p); - return EXIT_PC_UPDATED; + return DISAS_PC_UPDATED; } } -static ExitStatus gen_bcond(DisasContext *ctx, TCGCond cond, int ra, - int32_t disp, int mask) +static DisasJumpType gen_bcond(DisasContext *ctx, TCGCond cond, int ra, + int32_t disp, int mask) { if (mask) { TCGv tmp = tcg_temp_new(); - ExitStatus ret; + DisasJumpType ret; tcg_gen_andi_i64(tmp, load_gpr(ctx, ra), 1); ret = gen_bcond_internal(ctx, cond, tmp, disp); @@ -609,11 +588,11 @@ static void gen_fold_mzero(TCGCond cond, TCGv dest, TCGv src) } } -static ExitStatus gen_fbcond(DisasContext *ctx, TCGCond cond, int ra, - int32_t disp) +static DisasJumpType gen_fbcond(DisasContext *ctx, TCGCond cond, int ra, + int32_t disp) { TCGv cmp_tmp = tcg_temp_new(); - ExitStatus ret; + DisasJumpType ret; gen_fold_mzero(cond, cmp_tmp, load_fpr(ctx, ra)); ret = gen_bcond_internal(ctx, cond, cmp_tmp, disp); @@ -1159,7 +1138,7 @@ static void gen_rx(DisasContext *ctx, int ra, int set) tcg_temp_free(tmp); } -static ExitStatus gen_call_pal(DisasContext *ctx, int palcode) +static DisasJumpType gen_call_pal(DisasContext *ctx, int palcode) { /* We're emulating OSF/1 PALcode. Many of these are trivial access to internal cpu registers. */ @@ -1185,7 +1164,7 @@ static ExitStatus gen_call_pal(DisasContext *ctx, int palcode) palcode &= 0xbf; goto do_call_pal; } - return NO_EXIT; + return DISAS_NEXT; } #ifndef CONFIG_USER_ONLY @@ -1232,7 +1211,7 @@ static ExitStatus gen_call_pal(DisasContext *ctx, int palcode) /* Allow interrupts to be recognized right away. */ tcg_gen_movi_i64(cpu_pc, ctx->pc); - return EXIT_PC_UPDATED_NOCHAIN; + return DISAS_PC_UPDATED_NOCHAIN; case 0x36: /* RDPS */ @@ -1270,7 +1249,7 @@ static ExitStatus gen_call_pal(DisasContext *ctx, int palcode) palcode &= 0x3f; goto do_call_pal; } - return NO_EXIT; + return DISAS_NEXT; } #endif return gen_invalid(ctx); @@ -1307,10 +1286,10 @@ static ExitStatus gen_call_pal(DisasContext *ctx, int palcode) tcg_gen_goto_tb(0); tcg_gen_movi_i64(cpu_pc, entry); tcg_gen_exit_tb((uintptr_t)ctx->tb); - return EXIT_GOTO_TB; + return DISAS_NORETURN; } else { tcg_gen_movi_i64(cpu_pc, entry); - return EXIT_PC_UPDATED; + return DISAS_PC_UPDATED; } } #endif @@ -1344,7 +1323,7 @@ static int cpu_pr_data(int pr) return 0; } -static ExitStatus gen_mfpr(DisasContext *ctx, TCGv va, int regno) +static DisasJumpType gen_mfpr(DisasContext *ctx, TCGv va, int regno) { void (*helper)(TCGv); int data; @@ -1366,7 +1345,7 @@ static ExitStatus gen_mfpr(DisasContext *ctx, TCGv va, int regno) gen_io_start(); helper(va); gen_io_end(); - return EXIT_PC_STALE; + return DISAS_PC_STALE; } else { helper(va); } @@ -1393,10 +1372,10 @@ static ExitStatus gen_mfpr(DisasContext *ctx, TCGv va, int regno) break; } - return NO_EXIT; + return DISAS_NEXT; } -static ExitStatus gen_mtpr(DisasContext *ctx, TCGv vb, int regno) +static DisasJumpType gen_mtpr(DisasContext *ctx, TCGv vb, int regno) { int data; @@ -1424,7 +1403,7 @@ static ExitStatus gen_mtpr(DisasContext *ctx, TCGv vb, int regno) case 252: /* HALT */ gen_helper_halt(vb); - return EXIT_PC_STALE; + return DISAS_PC_STALE; case 251: /* ALARM */ @@ -1438,7 +1417,7 @@ static ExitStatus gen_mtpr(DisasContext *ctx, TCGv vb, int regno) that ended with a CALL_PAL. Since the base register usually only changes during boot, flushing everything works well. */ gen_helper_tb_flush(cpu_env); - return EXIT_PC_STALE; + return DISAS_PC_STALE; case 32 ... 39: /* Accessing the "non-shadow" general registers. */ @@ -1467,7 +1446,7 @@ static ExitStatus gen_mtpr(DisasContext *ctx, TCGv vb, int regno) break; } - return NO_EXIT; + return DISAS_NEXT; } #endif /* !USER_ONLY*/ @@ -1499,7 +1478,7 @@ static ExitStatus gen_mtpr(DisasContext *ctx, TCGv vb, int regno) } \ } while (0) -static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) +static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn) { int32_t disp21, disp16, disp12 __attribute__((unused)); uint16_t fn11; @@ -1507,7 +1486,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) bool islit, real_islit; TCGv va, vb, vc, tmp, tmp2; TCGv_i32 t32; - ExitStatus ret; + DisasJumpType ret; /* Decode all instruction fields */ opc = extract32(insn, 26, 6); @@ -1530,7 +1509,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) lit = 0; } - ret = NO_EXIT; + ret = DISAS_NEXT; switch (opc) { case 0x00: /* CALL_PAL */ @@ -2432,7 +2411,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) gen_io_start(); gen_helper_load_pcc(va, cpu_env); gen_io_end(); - ret = EXIT_PC_STALE; + ret = DISAS_PC_STALE; } else { gen_helper_load_pcc(va, cpu_env); } @@ -2480,7 +2459,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) if (ra != 31) { tcg_gen_movi_i64(ctx->ir[ra], ctx->pc); } - ret = EXIT_PC_UPDATED; + ret = DISAS_PC_UPDATED; break; case 0x1B: @@ -2738,7 +2717,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) tcg_temp_free(tmp); tcg_gen_andi_i64(cpu_pc, vb, ~3); /* Allow interrupts to be recognized right away. */ - ret = EXIT_PC_UPDATED_NOCHAIN; + ret = DISAS_PC_UPDATED_NOCHAIN; break; #else goto invalid_opc; @@ -2959,7 +2938,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) target_ulong pc_start; target_ulong pc_mask; uint32_t insn; - ExitStatus ret; + DisasJumpType ret; int num_insns; int max_insns; @@ -3040,41 +3019,40 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) /* If we reach a page boundary, are single stepping, or exhaust instruction count, stop generation. */ - if (ret == NO_EXIT + if (ret == DISAS_NEXT && ((ctx.pc & pc_mask) == 0 || tcg_op_buf_full() || num_insns >= max_insns || singlestep || ctx.singlestep_enabled)) { - ret = EXIT_FALLTHRU; + ret = DISAS_TOO_MANY; } - } while (ret == NO_EXIT); + } while (ret == DISAS_NEXT); if (tb->cflags & CF_LAST_IO) { gen_io_end(); } switch (ret) { - case EXIT_GOTO_TB: - case EXIT_NORETURN: + case DISAS_NORETURN: break; - case EXIT_FALLTHRU: + case DISAS_TOO_MANY: if (use_goto_tb(&ctx, ctx.pc)) { tcg_gen_goto_tb(0); tcg_gen_movi_i64(cpu_pc, ctx.pc); tcg_gen_exit_tb((uintptr_t)ctx.tb); } /* FALLTHRU */ - case EXIT_PC_STALE: + case DISAS_PC_STALE: tcg_gen_movi_i64(cpu_pc, ctx.pc); /* FALLTHRU */ - case EXIT_PC_UPDATED: + case DISAS_PC_UPDATED: if (!use_exit_tb(&ctx)) { tcg_gen_lookup_and_goto_ptr(cpu_pc); break; } /* FALLTHRU */ - case EXIT_PC_UPDATED_NOCHAIN: + case DISAS_PC_UPDATED_NOCHAIN: if (ctx.singlestep_enabled) { gen_excp_1(EXCP_DEBUG, 0); } else { From patchwork Thu Sep 7 18:19:36 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 111959 Delivered-To: patch@linaro.org Received: by 10.37.128.210 with SMTP id c18csp522118ybm; Thu, 7 Sep 2017 11:24:02 -0700 (PDT) X-Received: by 10.55.16.4 with SMTP id a4mr320885qkh.115.1504808642037; Thu, 07 Sep 2017 11:24:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504808642; cv=none; d=google.com; s=arc-20160816; b=FnADOAux5os345g+AIkto/aWzQ3eUB0ne7tYtwMlQG1jezuST9TLoffEG6P+SQa0uC 2dz78spBE/ruWyHBLpzheFTt0GY1sZ/WMAzsyza5qFVtDgVVGTR0H5XlpFeEWDgdFhNP 99nVkEluPwTfZvo3W0dL/fEKokZmufMqCT55gs9mRkuNelXHMlLRAuTF792ldSWVyXTf ljuI8P3T1ZlLMf4HBNvTunyxUICKrKLdfyyJxY/NE/qIIH4pDwDPn5xrgA+Q/uw6Iqm/ 7mUf0NF+rr/t6OoRJKjFhkP680diLk6o4ApqnfKLayj5JOrFISOeyN5AEkqEbLg+HHjQ 36NA== ARC-Message-Signature: i=1; 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id s68sm412051pfd.72.2017.09.07.11.19.41 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Sep 2017 11:19:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 7 Sep 2017 11:19:36 -0700 Message-Id: <20170907181938.3948-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170907181938.3948-1-richard.henderson@linaro.org> References: <20170907181938.3948-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::230 Subject: [Qemu-devel] [PULL 2/4] target/alpha: Convert to DisasContextBase X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson --- target/alpha/translate.c | 78 ++++++++++++++++++++++++------------------------ 1 file changed, 39 insertions(+), 39 deletions(-) -- 2.13.5 diff --git a/target/alpha/translate.c b/target/alpha/translate.c index a75bf5dd90..ba38717e0f 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -43,8 +43,8 @@ typedef struct DisasContext DisasContext; struct DisasContext { - struct TranslationBlock *tb; - uint64_t pc; + DisasContextBase base; + #ifndef CONFIG_USER_ONLY uint64_t palbr; #endif @@ -68,8 +68,6 @@ struct DisasContext { TCGv sink; /* Temporary for immediate constants. */ TCGv lit; - - bool singlestep_enabled; }; /* Target-specific return values from translate_one, indicating the @@ -282,7 +280,7 @@ static void gen_excp_1(int exception, int error_code) static DisasJumpType gen_excp(DisasContext *ctx, int exception, int error_code) { - tcg_gen_movi_i64(cpu_pc, ctx->pc); + tcg_gen_movi_i64(cpu_pc, ctx->base.pc_next); gen_excp_1(exception, error_code); return DISAS_NORETURN; } @@ -463,8 +461,8 @@ static bool in_superpage(DisasContext *ctx, int64_t addr) static bool use_exit_tb(DisasContext *ctx) { - return ((ctx->tb->cflags & CF_LAST_IO) - || ctx->singlestep_enabled + return ((ctx->base.tb->cflags & CF_LAST_IO) + || ctx->base.singlestep_enabled || singlestep); } @@ -480,7 +478,7 @@ static bool use_goto_tb(DisasContext *ctx, uint64_t dest) return true; } /* Check for the dest on the same page as the start of the TB. */ - return ((ctx->tb->pc ^ dest) & TARGET_PAGE_MASK) == 0; + return ((ctx->base.tb->pc ^ dest) & TARGET_PAGE_MASK) == 0; #else return true; #endif @@ -488,10 +486,10 @@ static bool use_goto_tb(DisasContext *ctx, uint64_t dest) static DisasJumpType gen_bdirect(DisasContext *ctx, int ra, int32_t disp) { - uint64_t dest = ctx->pc + (disp << 2); + uint64_t dest = ctx->base.pc_next + (disp << 2); if (ra != 31) { - tcg_gen_movi_i64(ctx->ir[ra], ctx->pc); + tcg_gen_movi_i64(ctx->ir[ra], ctx->base.pc_next); } /* Notice branch-to-next; used to initialize RA with the PC. */ @@ -500,7 +498,7 @@ static DisasJumpType gen_bdirect(DisasContext *ctx, int ra, int32_t disp) } else if (use_goto_tb(ctx, dest)) { tcg_gen_goto_tb(0); tcg_gen_movi_i64(cpu_pc, dest); - tcg_gen_exit_tb((uintptr_t)ctx->tb); + tcg_gen_exit_tb((uintptr_t)ctx->base.tb); return DISAS_NORETURN; } else { tcg_gen_movi_i64(cpu_pc, dest); @@ -511,26 +509,26 @@ static DisasJumpType gen_bdirect(DisasContext *ctx, int ra, int32_t disp) static DisasJumpType gen_bcond_internal(DisasContext *ctx, TCGCond cond, TCGv cmp, int32_t disp) { - uint64_t dest = ctx->pc + (disp << 2); + uint64_t dest = ctx->base.pc_next + (disp << 2); TCGLabel *lab_true = gen_new_label(); if (use_goto_tb(ctx, dest)) { tcg_gen_brcondi_i64(cond, cmp, 0, lab_true); tcg_gen_goto_tb(0); - tcg_gen_movi_i64(cpu_pc, ctx->pc); - tcg_gen_exit_tb((uintptr_t)ctx->tb); + tcg_gen_movi_i64(cpu_pc, ctx->base.pc_next); + tcg_gen_exit_tb((uintptr_t)ctx->base.tb); gen_set_label(lab_true); tcg_gen_goto_tb(1); tcg_gen_movi_i64(cpu_pc, dest); - tcg_gen_exit_tb((uintptr_t)ctx->tb + 1); + tcg_gen_exit_tb((uintptr_t)ctx->base.tb + 1); return DISAS_NORETURN; } else { TCGv_i64 z = tcg_const_i64(0); TCGv_i64 d = tcg_const_i64(dest); - TCGv_i64 p = tcg_const_i64(ctx->pc); + TCGv_i64 p = tcg_const_i64(ctx->base.pc_next); tcg_gen_movcond_i64(cond, cpu_pc, cmp, z, d, p); @@ -1210,7 +1208,7 @@ static DisasJumpType gen_call_pal(DisasContext *ctx, int palcode) } /* Allow interrupts to be recognized right away. */ - tcg_gen_movi_i64(cpu_pc, ctx->pc); + tcg_gen_movi_i64(cpu_pc, ctx->base.pc_next); return DISAS_PC_UPDATED_NOCHAIN; case 0x36: @@ -1260,7 +1258,7 @@ static DisasJumpType gen_call_pal(DisasContext *ctx, int palcode) #else { TCGv tmp = tcg_temp_new(); - uint64_t exc_addr = ctx->pc; + uint64_t exc_addr = ctx->base.pc_next; uint64_t entry = ctx->palbr; if (ctx->tbflags & ENV_FLAG_PAL_MODE) { @@ -1285,7 +1283,7 @@ static DisasJumpType gen_call_pal(DisasContext *ctx, int palcode) if (!use_exit_tb(ctx)) { tcg_gen_goto_tb(0); tcg_gen_movi_i64(cpu_pc, entry); - tcg_gen_exit_tb((uintptr_t)ctx->tb); + tcg_gen_exit_tb((uintptr_t)ctx->base.tb); return DISAS_NORETURN; } else { tcg_gen_movi_i64(cpu_pc, entry); @@ -2407,7 +2405,7 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn) case 0xC000: /* RPCC */ va = dest_gpr(ctx, ra); - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (ctx->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); gen_helper_load_pcc(va, cpu_env); gen_io_end(); @@ -2457,7 +2455,7 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn) vb = load_gpr(ctx, rb); tcg_gen_andi_i64(cpu_pc, vb, ~3); if (ra != 31) { - tcg_gen_movi_i64(ctx->ir[ra], ctx->pc); + tcg_gen_movi_i64(ctx->ir[ra], ctx->base.pc_next); } ret = DISAS_PC_UPDATED; break; @@ -2944,13 +2942,14 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) pc_start = tb->pc; - ctx.tb = tb; - ctx.pc = pc_start; + ctx.base.tb = tb; + ctx.base.pc_next = pc_start; + ctx.base.singlestep_enabled = cs->singlestep_enabled; + ctx.tbflags = tb->flags; ctx.mem_idx = cpu_mmu_index(env, false); ctx.implver = env->implver; ctx.amask = env->amask; - ctx.singlestep_enabled = cs->singlestep_enabled; #ifdef CONFIG_USER_ONLY ctx.ir = cpu_std_ir; @@ -2992,39 +2991,40 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) tcg_clear_temp_count(); do { - tcg_gen_insn_start(ctx.pc); + tcg_gen_insn_start(ctx.base.pc_next); num_insns++; - if (unlikely(cpu_breakpoint_test(cs, ctx.pc, BP_ANY))) { + if (unlikely(cpu_breakpoint_test(cs, ctx.base.pc_next, BP_ANY))) { ret = gen_excp(&ctx, EXCP_DEBUG, 0); /* The address covered by the breakpoint must be included in [tb->pc, tb->pc + tb->size) in order to for it to be properly cleared -- thus we increment the PC here so that the logic setting tb->size below does the right thing. */ - ctx.pc += 4; + ctx.base.pc_next += 4; break; } if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); } - insn = cpu_ldl_code(env, ctx.pc); + insn = cpu_ldl_code(env, ctx.base.pc_next); - ctx.pc += 4; + ctx.base.pc_next += 4; ret = translate_one(ctxp, insn); free_context_temps(ctxp); if (tcg_check_temp_count()) { - qemu_log("TCG temporary leak before "TARGET_FMT_lx"\n", ctx.pc); + qemu_log("TCG temporary leak before "TARGET_FMT_lx"\n", + ctx.base.pc_next); } /* If we reach a page boundary, are single stepping, or exhaust instruction count, stop generation. */ if (ret == DISAS_NEXT - && ((ctx.pc & pc_mask) == 0 + && ((ctx.base.pc_next & pc_mask) == 0 || tcg_op_buf_full() || num_insns >= max_insns || singlestep - || ctx.singlestep_enabled)) { + || ctx.base.singlestep_enabled)) { ret = DISAS_TOO_MANY; } } while (ret == DISAS_NEXT); @@ -3037,14 +3037,14 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) case DISAS_NORETURN: break; case DISAS_TOO_MANY: - if (use_goto_tb(&ctx, ctx.pc)) { + if (use_goto_tb(&ctx, ctx.base.pc_next)) { tcg_gen_goto_tb(0); - tcg_gen_movi_i64(cpu_pc, ctx.pc); - tcg_gen_exit_tb((uintptr_t)ctx.tb); + tcg_gen_movi_i64(cpu_pc, ctx.base.pc_next); + tcg_gen_exit_tb((uintptr_t)ctx.base.tb); } /* FALLTHRU */ case DISAS_PC_STALE: - tcg_gen_movi_i64(cpu_pc, ctx.pc); + tcg_gen_movi_i64(cpu_pc, ctx.base.pc_next); /* FALLTHRU */ case DISAS_PC_UPDATED: if (!use_exit_tb(&ctx)) { @@ -3053,7 +3053,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) } /* FALLTHRU */ case DISAS_PC_UPDATED_NOCHAIN: - if (ctx.singlestep_enabled) { + if (ctx.base.singlestep_enabled) { gen_excp_1(EXCP_DEBUG, 0); } else { tcg_gen_exit_tb(0); @@ -3065,7 +3065,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) gen_tb_end(tb, num_insns); - tb->size = ctx.pc - pc_start; + tb->size = ctx.base.pc_next - pc_start; tb->icount = num_insns; #ifdef DEBUG_DISAS @@ -3073,7 +3073,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) && qemu_log_in_addr_range(pc_start)) { qemu_log_lock(); qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, ctx.pc - pc_start, 1); + log_target_disas(cs, pc_start, ctx.base.pc_next - pc_start, 1); qemu_log("\n"); qemu_log_unlock(); } From patchwork Thu Sep 7 18:19:37 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 111956 Delivered-To: patch@linaro.org Received: by 10.37.128.210 with SMTP id c18csp519760ybm; Thu, 7 Sep 2017 11:21:49 -0700 (PDT) X-Received: by 10.200.4.146 with SMTP id s18mr262980qtg.240.1504808509034; Thu, 07 Sep 2017 11:21:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504808509; cv=none; d=google.com; s=arc-20160816; b=Sh8mCSW+/LiatJtOENMFBHcIeJuXhJeDvDfe0Xp4tCCSpFHzpy/oqFLwjX2CohNRL0 bx70VG123+H1vtfQG3lGndUMXT/kMUn2Q76qVxvxuNBCQvJkzLBQ6HXNqBRJ0WeaVCny mlLVjNO2S2rLfCdQgKwjLDpADzFWF4xkq8ILiwKhSZtK52xMzXYq5myeFWgCVGT3Dyl7 oYNcsXRWUh9vRdVOCwM3bRdLwSPfNS8BbuBWo4FGsCbCW9qTTe4eyCNcYrHp1s6+jdU9 m02RGmVNKnYUebLLeYDvBDTN2Ze1UngFJh625nQJOeZQS422okkVcFlvlY/aUOuOAnM9 2FUQ== ARC-Message-Signature: i=1; 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id s68sm412051pfd.72.2017.09.07.11.19.43 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Sep 2017 11:19:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 7 Sep 2017 11:19:37 -0700 Message-Id: <20170907181938.3948-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170907181938.3948-1-richard.henderson@linaro.org> References: <20170907181938.3948-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22f Subject: [Qemu-devel] [PULL 3/4] target/alpha: Convert to TranslatorOps X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson --- target/alpha/translate.c | 185 ++++++++++++++++++++++------------------------- 1 file changed, 86 insertions(+), 99 deletions(-) -- 2.13.5 diff --git a/target/alpha/translate.c b/target/alpha/translate.c index ba38717e0f..5a92c4accb 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -2929,33 +2929,23 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn) return ret; } -void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) +static int alpha_tr_init_disas_context(DisasContextBase *dcbase, + CPUState *cpu, int max_insns) { - CPUAlphaState *env = cs->env_ptr; - DisasContext ctx, *ctxp = &ctx; - target_ulong pc_start; - target_ulong pc_mask; - uint32_t insn; - DisasJumpType ret; - int num_insns; - int max_insns; - - pc_start = tb->pc; - - ctx.base.tb = tb; - ctx.base.pc_next = pc_start; - ctx.base.singlestep_enabled = cs->singlestep_enabled; + DisasContext *ctx = container_of(dcbase, DisasContext, base); + CPUAlphaState *env = cpu->env_ptr; + int64_t bound, mask; - ctx.tbflags = tb->flags; - ctx.mem_idx = cpu_mmu_index(env, false); - ctx.implver = env->implver; - ctx.amask = env->amask; + ctx->tbflags = ctx->base.tb->flags; + ctx->mem_idx = cpu_mmu_index(env, false); + ctx->implver = env->implver; + ctx->amask = env->amask; #ifdef CONFIG_USER_ONLY - ctx.ir = cpu_std_ir; + ctx->ir = cpu_std_ir; #else - ctx.palbr = env->palbr; - ctx.ir = (ctx.tbflags & ENV_FLAG_PAL_MODE ? cpu_pal_ir : cpu_std_ir); + ctx->palbr = env->palbr; + ctx->ir = (ctx->tbflags & ENV_FLAG_PAL_MODE ? cpu_pal_ir : cpu_std_ir); #endif /* ??? Every TB begins with unset rounding mode, to be initialized on @@ -2964,96 +2954,87 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) to reset the FP_STATUS to that default at the end of any TB that changes the default. We could even (gasp) dynamiclly figure out what default would be most efficient given the running program. */ - ctx.tb_rm = -1; + ctx->tb_rm = -1; /* Similarly for flush-to-zero. */ - ctx.tb_ftz = -1; + ctx->tb_ftz = -1; - TCGV_UNUSED_I64(ctx.zero); - TCGV_UNUSED_I64(ctx.sink); - TCGV_UNUSED_I64(ctx.lit); - - num_insns = 0; - max_insns = tb->cflags & CF_COUNT_MASK; - if (max_insns == 0) { - max_insns = CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns = TCG_MAX_INSNS; - } + TCGV_UNUSED_I64(ctx->zero); + TCGV_UNUSED_I64(ctx->sink); + TCGV_UNUSED_I64(ctx->lit); - if (in_superpage(&ctx, pc_start)) { - pc_mask = (1ULL << 41) - 1; + /* Bound the number of insns to execute to those left on the page. */ + if (in_superpage(ctx, ctx->base.pc_first)) { + mask = -1ULL << 41; } else { - pc_mask = ~TARGET_PAGE_MASK; + mask = TARGET_PAGE_MASK; } + bound = -(ctx->base.pc_first | mask) / 4; - gen_tb_start(tb); - tcg_clear_temp_count(); + return MIN(max_insns, bound); +} - do { - tcg_gen_insn_start(ctx.base.pc_next); - num_insns++; +static void alpha_tr_tb_start(DisasContextBase *db, CPUState *cpu) +{ +} - if (unlikely(cpu_breakpoint_test(cs, ctx.base.pc_next, BP_ANY))) { - ret = gen_excp(&ctx, EXCP_DEBUG, 0); - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ - ctx.base.pc_next += 4; - break; - } - if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { - gen_io_start(); - } - insn = cpu_ldl_code(env, ctx.base.pc_next); +static void alpha_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) +{ + tcg_gen_insn_start(dcbase->pc_next); +} - ctx.base.pc_next += 4; - ret = translate_one(ctxp, insn); - free_context_temps(ctxp); +static bool alpha_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, + const CPUBreakpoint *bp) +{ + DisasContext *ctx = container_of(dcbase, DisasContext, base); - if (tcg_check_temp_count()) { - qemu_log("TCG temporary leak before "TARGET_FMT_lx"\n", - ctx.base.pc_next); - } + ctx->base.is_jmp = gen_excp(ctx, EXCP_DEBUG, 0); - /* If we reach a page boundary, are single stepping, - or exhaust instruction count, stop generation. */ - if (ret == DISAS_NEXT - && ((ctx.base.pc_next & pc_mask) == 0 - || tcg_op_buf_full() - || num_insns >= max_insns - || singlestep - || ctx.base.singlestep_enabled)) { - ret = DISAS_TOO_MANY; - } - } while (ret == DISAS_NEXT); + /* The address covered by the breakpoint must be included in + [tb->pc, tb->pc + tb->size) in order to for it to be + properly cleared -- thus we increment the PC here so that + the logic setting tb->size below does the right thing. */ + ctx->base.pc_next += 4; + return true; +} - if (tb->cflags & CF_LAST_IO) { - gen_io_end(); - } +static void alpha_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *ctx = container_of(dcbase, DisasContext, base); + CPUAlphaState *env = cpu->env_ptr; + uint32_t insn = cpu_ldl_code(env, ctx->base.pc_next); + + ctx->base.pc_next += 4; + ctx->base.is_jmp = translate_one(ctx, insn); + + free_context_temps(ctx); + translator_loop_temp_check(&ctx->base); +} + +static void alpha_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *ctx = container_of(dcbase, DisasContext, base); - switch (ret) { + switch (ctx->base.is_jmp) { case DISAS_NORETURN: break; case DISAS_TOO_MANY: - if (use_goto_tb(&ctx, ctx.base.pc_next)) { + if (use_goto_tb(ctx, ctx->base.pc_next)) { tcg_gen_goto_tb(0); - tcg_gen_movi_i64(cpu_pc, ctx.base.pc_next); - tcg_gen_exit_tb((uintptr_t)ctx.base.tb); + tcg_gen_movi_i64(cpu_pc, ctx->base.pc_next); + tcg_gen_exit_tb((uintptr_t)ctx->base.tb); } /* FALLTHRU */ case DISAS_PC_STALE: - tcg_gen_movi_i64(cpu_pc, ctx.base.pc_next); + tcg_gen_movi_i64(cpu_pc, ctx->base.pc_next); /* FALLTHRU */ case DISAS_PC_UPDATED: - if (!use_exit_tb(&ctx)) { + if (!use_exit_tb(ctx)) { tcg_gen_lookup_and_goto_ptr(cpu_pc); break; } /* FALLTHRU */ case DISAS_PC_UPDATED_NOCHAIN: - if (ctx.base.singlestep_enabled) { + if (ctx->base.singlestep_enabled) { gen_excp_1(EXCP_DEBUG, 0); } else { tcg_gen_exit_tb(0); @@ -3062,22 +3043,28 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) default: g_assert_not_reached(); } +} - gen_tb_end(tb, num_insns); - - tb->size = ctx.base.pc_next - pc_start; - tb->icount = num_insns; +static void alpha_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) +{ + qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); + log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size, 1); +} + +static const TranslatorOps alpha_tr_ops = { + .init_disas_context = alpha_tr_init_disas_context, + .tb_start = alpha_tr_tb_start, + .insn_start = alpha_tr_insn_start, + .breakpoint_check = alpha_tr_breakpoint_check, + .translate_insn = alpha_tr_translate_insn, + .tb_stop = alpha_tr_tb_stop, + .disas_log = alpha_tr_disas_log, +}; -#ifdef DEBUG_DISAS - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) - && qemu_log_in_addr_range(pc_start)) { - qemu_log_lock(); - qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, ctx.base.pc_next - pc_start, 1); - qemu_log("\n"); - qemu_log_unlock(); - } -#endif +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) +{ + DisasContext dc; + translator_loop(&alpha_tr_ops, &dc.base, cpu, tb); } void restore_state_to_opc(CPUAlphaState *env, TranslationBlock *tb, From patchwork Thu Sep 7 18:19:38 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 111958 Delivered-To: patch@linaro.org Received: by 10.37.128.210 with SMTP id c18csp520507ybm; Thu, 7 Sep 2017 11:22:30 -0700 (PDT) X-Received: by 10.55.186.1 with SMTP id k1mr376170qkf.28.1504808550088; Thu, 07 Sep 2017 11:22:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504808550; cv=none; d=google.com; s=arc-20160816; b=MH9jgJR1OaCCx6F3DDVL4P56L5VHPvDP4X89u/JXBTBBHbk7IMsP2RY6UeARCRT3tf l00880VTN8mjJMnClwKo5piNrG/nLqyzoLGG+/attNYIm+QPaBgFqa0fBzk5nTysbas/ l3BKY9iufTOiDUZWNUspRyUuHbFHnnYsbK65RVkPcpogr5vNyZrEGWtScLtFCY9O4vSQ DehtbSll8m3eCmMoNMnYBmL84qMYoWo4ujBVW9pM0+UcTmrkMoPH5rX+cD1Hh8rkGIcz Ej1LIq8M4ju272cCeWijvW2497E8LvwKb6tvVpS/J86u6hdGZFBlVr5jqIFh35iuM+vP UVNg== ARC-Message-Signature: i=1; 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id s68sm412051pfd.72.2017.09.07.11.19.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Sep 2017 11:19:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 7 Sep 2017 11:19:38 -0700 Message-Id: <20170907181938.3948-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170907181938.3948-1-richard.henderson@linaro.org> References: <20170907181938.3948-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::236 Subject: [Qemu-devel] [PULL 4/4] target/alpha: Switch to do_transaction_failed() hook X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Peter Maydell Switch the alpha target from the old unassigned_access hook to the new do_transaction_failed hook. This allows us to resolve a ??? in the old hook implementation. The only part of the alpha target that does physical memory accesses is reading the page table -- add a TODO comment there to the effect that we should handle bus faults on page table walks. (Since the palcode doesn't actually do anything useful on a bus fault anyway it's a bit moot for now.) Signed-off-by: Peter Maydell Message-Id: <1502196172-13818-1-git-send-email-peter.maydell@linaro.org> Signed-off-by: Richard Henderson --- target/alpha/cpu.c | 2 +- target/alpha/cpu.h | 8 +++++--- target/alpha/helper.c | 8 ++++++++ target/alpha/mem_helper.c | 19 ++++++++++--------- 4 files changed, 24 insertions(+), 13 deletions(-) -- 2.13.5 diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 1ea597b9dd..e6c6aabdf0 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -297,7 +297,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data) #ifdef CONFIG_USER_ONLY cc->handle_mmu_fault = alpha_cpu_handle_mmu_fault; #else - cc->do_unassigned_access = alpha_cpu_unassigned_access; + cc->do_transaction_failed = alpha_cpu_do_transaction_failed; cc->do_unaligned_access = alpha_cpu_do_unaligned_access; cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug; dc->vmsd = &vmstate_alpha_cpu; diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 0738e97d6d..6ae240969b 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -486,9 +486,11 @@ void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val); uint64_t cpu_alpha_load_gr(CPUAlphaState *env, unsigned reg); void cpu_alpha_store_gr(CPUAlphaState *env, unsigned reg, uint64_t val); #ifndef CONFIG_USER_ONLY -QEMU_NORETURN void alpha_cpu_unassigned_access(CPUState *cpu, hwaddr addr, - bool is_write, bool is_exec, - int unused, unsigned size); +void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, + vaddr addr, unsigned size, + MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t retaddr); #endif static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *pc, diff --git a/target/alpha/helper.c b/target/alpha/helper.c index 34121f4cad..36407f77f5 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -163,6 +163,14 @@ static int get_physical_address(CPUAlphaState *env, target_ulong addr, pt = env->ptbr; + /* TODO: rather than using ldq_phys() to read the page table we should + * use address_space_ldq() so that we can handle the case when + * the page table read gives a bus fault, rather than ignoring it. + * For the existing code the zero data that ldq_phys will return for + * an access to invalid memory will result in our treating the page + * table as invalid, which may even be the right behaviour. + */ + /* L1 page table read. */ index = (addr >> (TARGET_PAGE_BITS + 20)) & 0x3ff; L1pte = ldq_phys(cs->as, pt + index*8); diff --git a/target/alpha/mem_helper.c b/target/alpha/mem_helper.c index 78a7d45590..3c06baa93a 100644 --- a/target/alpha/mem_helper.c +++ b/target/alpha/mem_helper.c @@ -49,22 +49,23 @@ void alpha_cpu_do_unaligned_access(CPUState *cs, vaddr addr, cpu_loop_exit(cs); } -void alpha_cpu_unassigned_access(CPUState *cs, hwaddr addr, - bool is_write, bool is_exec, int unused, - unsigned size) +void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, + vaddr addr, unsigned size, + MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t retaddr) { AlphaCPU *cpu = ALPHA_CPU(cs); CPUAlphaState *env = &cpu->env; + if (retaddr) { + cpu_restore_state(cs, retaddr); + } + env->trap_arg0 = addr; - env->trap_arg1 = is_write ? 1 : 0; + env->trap_arg1 = access_type == MMU_DATA_STORE ? 1 : 0; cs->exception_index = EXCP_MCHK; env->error_code = 0; - - /* ??? We should cpu_restore_state to the faulting insn, but this hook - does not have access to the retaddr value from the original helper. - It's all moot until the QEMU PALcode grows an MCHK handler. */ - cpu_loop_exit(cs); }