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[90.118.159.96]) by smtp.googlemail.com with ESMTPSA id l19sm684566wrl.47.2017.09.08.00.14.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Sep 2017 00:14:08 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Corentin Labbe Subject: [PATCH v5 01/10] arm64: dts: allwinner: Restore EMAC changes Date: Fri, 8 Sep 2017 09:11:47 +0200 Message-Id: <20170908071156.5115-2-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170908071156.5115-1-clabbe.montjoie@gmail.com> References: <20170908071156.5115-1-clabbe.montjoie@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch restore arm64 DT about dwmac-sun8i This reverts commit 87e1f5e8bb4b ("arm64: dts: allwinner: Revert EMAC changes") Signed-off-by: Corentin Labbe --- .../boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 16 ++++++++++++++++ .../boot/dts/allwinner/sun50i-a64-pine64-plus.dts | 15 +++++++++++++++ arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 17 +++++++++++++++++ .../dts/allwinner/sun50i-a64-sopine-baseboard.dts | 16 ++++++++++++++++ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 20 ++++++++++++++++++++ .../boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts | 17 +++++++++++++++++ .../boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts | 17 +++++++++++++++++ .../boot/dts/allwinner/sun50i-h5-orangepi-prime.dts | 17 +++++++++++++++++ 8 files changed, 135 insertions(+) -- 2.13.5 diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts index d347f52e27f6..45bdbfb96126 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts @@ -51,6 +51,7 @@ compatible = "sinovoip,bananapi-m64", "allwinner,sun50i-a64"; aliases { + ethernet0 = &emac; serial0 = &uart0; serial1 = &uart1; }; @@ -69,6 +70,14 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + phy-mode = "rgmii"; + phy-handle = <&ext_rgmii_phy>; + status = "okay"; +}; + &i2c1 { pinctrl-names = "default"; pinctrl-0 = <&i2c1_pins>; @@ -79,6 +88,13 @@ bias-pull-up; }; +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts index f82ccf332c0f..24f1aac366d6 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts @@ -48,3 +48,18 @@ /* TODO: Camera, touchscreen, etc. */ }; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + phy-mode = "rgmii"; + phy-handle = <&ext_rgmii_phy>; + status = "okay"; +}; + +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts index caf8b6fbe5e3..6f209bb10a2f 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts @@ -51,6 +51,7 @@ compatible = "pine64,pine64", "allwinner,sun50i-a64"; aliases { + ethernet0 = &emac; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; @@ -78,6 +79,15 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&rmii_pins>; + phy-mode = "rmii"; + phy-handle = <&ext_rmii_phy1>; + status = "okay"; + +}; + &i2c1 { pinctrl-names = "default"; pinctrl-0 = <&i2c1_pins>; @@ -88,6 +98,13 @@ bias-pull-up; }; +&mdio { + ext_rmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts index 17ccc12b58df..0eb2acedf8c3 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts @@ -53,6 +53,7 @@ "allwinner,sun50i-a64"; aliases { + ethernet0 = &emac; serial0 = &uart0; }; @@ -76,6 +77,21 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + phy-mode = "rgmii"; + phy-handle = <&ext_rgmii_phy>; + status = "okay"; +}; + +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 75e8d3182535..4dd9ffef0d80 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -461,6 +461,26 @@ #size-cells = <0>; }; + emac: ethernet@1c30000 { + compatible = "allwinner,sun50i-a64-emac"; + syscon = <&syscon>; + reg = <0x01c30000 0x10000>; + interrupts = ; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + gic: interrupt-controller@1c81000 { compatible = "arm,gic-400"; reg = <0x01c81000 0x1000>, diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts index 1c2387bd5df6..968908761194 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts @@ -50,6 +50,7 @@ compatible = "friendlyarm,nanopi-neo2", "allwinner,sun50i-h5"; aliases { + ethernet0 = &emac; serial0 = &uart0; }; @@ -108,6 +109,22 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + status = "okay"; +}; + +&mdio { + ext_rgmii_phy: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <7>; + }; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts index 4f77c8470f6c..a8296feee884 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts @@ -59,6 +59,7 @@ }; aliases { + ethernet0 = &emac; serial0 = &uart0; }; @@ -136,12 +137,28 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + status = "okay"; +}; + &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; status = "okay"; }; +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts index 6be06873e5af..d906b302cbcd 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts @@ -54,6 +54,7 @@ compatible = "xunlong,orangepi-prime", "allwinner,sun50i-h5"; aliases { + ethernet0 = &emac; serial0 = &uart0; }; @@ -143,12 +144,28 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + status = "okay"; +}; + &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; status = "okay"; }; +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; From patchwork Fri Sep 8 07:11:48 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 112012 Delivered-To: patch@linaro.org Received: by 10.140.94.239 with SMTP id g102csp1125545qge; Fri, 8 Sep 2017 00:14:20 -0700 (PDT) X-Received: by 10.98.89.91 with SMTP id n88mr2158706pfb.280.1504854860353; Fri, 08 Sep 2017 00:14:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504854860; cv=none; d=google.com; s=arc-20160816; b=CIL8k0tbazhwKopD5VQ6tzSgVtBHHMjXWvqqbd5Elug143CPllNKSqIO9+/41OdD38 eQU1d6doqiZ4vJcY8KH5Qb+QYxSTPmWPsDGyclff/kGaDGaPs8e/3Ox9Jl+EN2nR0LJK tPST0y6csPPawn9izUm3kyqeAbdKboiG3oRMQxncmbia7n7jEOiQDjydKCmRLsDA/yjR EkVlytVJ3yh7UKKXidLweixsDis+8ht/dcUtP6I82SUf3soLGwxa1QDvHmVq1OtZuDBA fFh3YJkFEYyIOY2qoQrqid6x3tiJcHvRltF+wLIcQ3KmY7vioGkum6Tcrs+Ql7GI50i+ WqXQ== ARC-Message-Signature: i=1; a=rsa-sha256; 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[90.118.159.96]) by smtp.googlemail.com with ESMTPSA id l19sm684566wrl.47.2017.09.08.00.14.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Sep 2017 00:14:09 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Corentin Labbe Subject: [PATCH v5 02/10] dt-bindings: net: Restore sun8i dwmac binding Date: Fri, 8 Sep 2017 09:11:48 +0200 Message-Id: <20170908071156.5115-3-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170908071156.5115-1-clabbe.montjoie@gmail.com> References: <20170908071156.5115-1-clabbe.montjoie@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch restore dt-bindings documentation about dwmac-sun8i This reverts commit 8aa33ec2f481 ("dt-bindings: net: Revert sun8i dwmac binding") Signed-off-by: Corentin Labbe --- .../devicetree/bindings/net/dwmac-sun8i.txt | 84 ++++++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/dwmac-sun8i.txt -- 2.13.5 Acked-by: Rob Herring diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt new file mode 100644 index 000000000000..725f3b187886 --- /dev/null +++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt @@ -0,0 +1,84 @@ +* Allwinner sun8i GMAC ethernet controller + +This device is a platform glue layer for stmmac. +Please see stmmac.txt for the other unchanged properties. + +Required properties: +- compatible: should be one of the following string: + "allwinner,sun8i-a83t-emac" + "allwinner,sun8i-h3-emac" + "allwinner,sun8i-v3s-emac" + "allwinner,sun50i-a64-emac" +- reg: address and length of the register for the device. +- interrupts: interrupt for the device +- interrupt-names: should be "macirq" +- clocks: A phandle to the reference clock for this device +- clock-names: should be "stmmaceth" +- resets: A phandle to the reset control for this device +- reset-names: should be "stmmaceth" +- phy-mode: See ethernet.txt +- phy-handle: See ethernet.txt +- #address-cells: shall be 1 +- #size-cells: shall be 0 +- syscon: A phandle to the syscon of the SoC with one of the following + compatible string: + - allwinner,sun8i-h3-system-controller + - allwinner,sun8i-v3s-system-controller + - allwinner,sun50i-a64-system-controller + - allwinner,sun8i-a83t-system-controller + +Optional properties: +- allwinner,tx-delay-ps: TX clock delay chain value in ps. Range value is 0-700. Default is 0) +- allwinner,rx-delay-ps: RX clock delay chain value in ps. Range value is 0-3100. Default is 0) +Both delay properties need to be a multiple of 100. They control the delay for +external PHY. + +Optional properties for the following compatibles: + - "allwinner,sun8i-h3-emac", + - "allwinner,sun8i-v3s-emac": +- allwinner,leds-active-low: EPHY LEDs are active low + +Required child node of emac: +- mdio bus node: should be named mdio + +Required properties of the mdio node: +- #address-cells: shall be 1 +- #size-cells: shall be 0 + +The device node referenced by "phy" or "phy-handle" should be a child node +of the mdio node. See phy.txt for the generic PHY bindings. + +Required properties of the phy node with the following compatibles: + - "allwinner,sun8i-h3-emac", + - "allwinner,sun8i-v3s-emac": +- clocks: a phandle to the reference clock for the EPHY +- resets: a phandle to the reset control for the EPHY + +Example: + +emac: ethernet@1c0b000 { + compatible = "allwinner,sun8i-h3-emac"; + syscon = <&syscon>; + reg = <0x01c0b000 0x104>; + interrupts = ; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + #address-cells = <1>; + #size-cells = <0>; + + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + int_mii_phy: ethernet-phy@1 { + reg = <1>; + clocks = <&ccu CLK_BUS_EPHY>; + resets = <&ccu RST_BUS_EPHY>; + }; + }; +}; From patchwork Fri Sep 8 07:11:51 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 112018 Delivered-To: patch@linaro.org Received: by 10.140.94.239 with SMTP id g102csp1127313qge; Fri, 8 Sep 2017 00:16:14 -0700 (PDT) X-Received: by 10.99.4.88 with SMTP id 85mr2159245pge.410.1504854974796; Fri, 08 Sep 2017 00:16:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504854974; cv=none; d=google.com; s=arc-20160816; b=Qkh4kb508aHpl4ASHToy1qe1MlWNpWXkySQ5gKgmkan/AcVVLAqCbT9mOPPXKvIKu4 f2YC/hmPf6Ow1/pQr8iFPLNvWUBQK69GAJ1eKDBUAk/ExmD3q9hcFRISMv1I0WsWeQTa JpHF7TcXuKWSf0co2Z5CbYTbNYQVCxyY0i3StT20LwgFikVPVgQOhijDeScBi/X6nbsJ aMWhEL/wCKW2IoJMgvWRwGUNvGmzlhb9Fi1M2L5ji4dji5EEF4vnboZuG1oHGoBm/u4I vxMLIXqtCcY1CL5tqXGj8PS99//uRcA73+htM1NoeJLbsqHgx8AkrtosUhJQYsLR5n2k eVxg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=v3OUF9wjayWVPy9qPBPci63XPYFyt5bnNKMvxB0Ytbc=; b=IhtlN7hENkVC0Q84h7saX+Gdi0SZfGJfKR8od4++6xLN6UKXg1kIgms6XhAHhaHYb8 j3d/ST8/3rw1flkjeC04+3OIQ/SJFc6a36z6HKJgA2WxZpqHDmclZSVcfeQuCaiL3NxI icnro83/7MbSuhVZ9txLjlqjpaLDNffWqKsPMqER6pgBOiUyDQiWWu34sTLi6jZXBd37 cbLu0Q/O2FFyUmcPYzpB7MxkJhWtCENA4guRi/AIPw3aggN4p+KfV8fVWwPzk12eRrXd HV4D0J6nphPCnyj6OSO0xDFCjxGzT5PdR5bwL6H3IdeOISZNd/RRiAvGfJVFwtrA+p/j RsFA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=cOT/WfUU; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[90.118.159.96]) by smtp.googlemail.com with ESMTPSA id l19sm684566wrl.47.2017.09.08.00.14.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Sep 2017 00:14:12 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Corentin Labbe Subject: [PATCH v5 05/10] dt-bindings: net: dwmac-sun8i: update documentation about integrated PHY Date: Fri, 8 Sep 2017 09:11:51 +0200 Message-Id: <20170908071156.5115-6-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170908071156.5115-1-clabbe.montjoie@gmail.com> References: <20170908071156.5115-1-clabbe.montjoie@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch add documentation about the MDIO switch used on sun8i-h3-emac for integrated PHY. Signed-off-by: Corentin Labbe --- .../devicetree/bindings/net/dwmac-sun8i.txt | 127 +++++++++++++++++++-- 1 file changed, 120 insertions(+), 7 deletions(-) -- 2.13.5 diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt index 725f3b187886..3fa0e54825ea 100644 --- a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt +++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt @@ -39,7 +39,7 @@ Optional properties for the following compatibles: - allwinner,leds-active-low: EPHY LEDs are active low Required child node of emac: -- mdio bus node: should be named mdio +- mdio bus node: should be labelled mdio Required properties of the mdio node: - #address-cells: shall be 1 @@ -48,14 +48,28 @@ Required properties of the mdio node: The device node referenced by "phy" or "phy-handle" should be a child node of the mdio node. See phy.txt for the generic PHY bindings. -Required properties of the phy node with the following compatibles: +The following compatibles require an mdio-mux node called "mdio-mux": + - "allwinner,sun8i-h3-emac" + - "allwinner,sun8i-v3s-emac": +Required properties for the mdio-mux node: + - compatible = "mdio-mux" + - one child mdio for the integrated mdio + - one child mdio for the external mdio if present (V3s have none) +Required properties for the mdio-mux children node: + - reg: 0 for internal MDIO bus, 1 for external MDIO bus + +The following compatibles require a PHY node representing the integrated +PHY, under the integrated MDIO bus node if an mdio-mux node is used: - "allwinner,sun8i-h3-emac", - "allwinner,sun8i-v3s-emac": + +Required properties of the integrated phy node: - clocks: a phandle to the reference clock for the EPHY - resets: a phandle to the reset control for the EPHY +- phy-is-integrated +- Should be a child of the integrated mdio -Example: - +Example with integrated PHY: emac: ethernet@1c0b000 { compatible = "allwinner,sun8i-h3-emac"; syscon = <&syscon>; @@ -72,13 +86,112 @@ emac: ethernet@1c0b000 { phy-handle = <&int_mii_phy>; phy-mode = "mii"; allwinner,leds-active-low; + + mdio0: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + }; + + mdio-mux { + compatible = "mdio-mux"; + #address-cells = <1>; + #size-cells = <0>; + + int_mdio: mdio@1 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + int_mii_phy: ethernet-phy@1 { + reg = <1>; + clocks = <&ccu CLK_BUS_EPHY>; + resets = <&ccu RST_BUS_EPHY>; + phy-is-integrated + }; + }; + ext_mdio: mdio@0 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +Example with external PHY: +emac: ethernet@1c0b000 { + compatible = "allwinner,sun8i-h3-emac"; + syscon = <&syscon>; + reg = <0x01c0b000 0x104>; + interrupts = ; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + #address-cells = <1>; + #size-cells = <0>; + + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + allwinner,leds-active-low; + + mdio0: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + }; + + mdio-mux { + compatible = "mdio-mux"; + #address-cells = <1>; + #size-cells = <0>; + + int_mdio: mdio@1 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + int_mii_phy: ethernet-phy@1 { + reg = <1>; + clocks = <&ccu CLK_BUS_EPHY>; + resets = <&ccu RST_BUS_EPHY>; + phy-is-integrated + }; + }; + ext_mdio: mdio@0 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + ext_rgmii_phy: ethernet-phy@1 { + reg = <1>; + }; + }; + }; +}; + +Example with SoC without integrated PHY + +emac: ethernet@1c0b000 { + compatible = "allwinner,sun8i-a83t-emac"; + syscon = <&syscon>; + reg = <0x01c0b000 0x104>; + interrupts = ; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + #address-cells = <1>; + #size-cells = <0>; + + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + mdio: mdio { + compatible = "snps,dwmac-mdio"; #address-cells = <1>; #size-cells = <0>; - int_mii_phy: ethernet-phy@1 { + ext_rgmii_phy: ethernet-phy@1 { reg = <1>; - clocks = <&ccu CLK_BUS_EPHY>; - resets = <&ccu RST_BUS_EPHY>; }; }; }; From patchwork Fri Sep 8 07:11:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 112013 Delivered-To: patch@linaro.org Received: by 10.140.94.239 with SMTP id g102csp1125592qge; Fri, 8 Sep 2017 00:14:24 -0700 (PDT) X-Received: by 10.99.186.5 with SMTP id k5mr2097899pgf.31.1504854864593; Fri, 08 Sep 2017 00:14:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504854864; cv=none; d=google.com; s=arc-20160816; b=OOyZQJBwHQu2cqYUBqe1NZl2b2Zwze/Pj68TZLiuJVcvNGs367C0hwKuHjYwzdY6Ok dtd5H3qOnErz7hF2tsqlP+eZ+guL/SW0dVVLJj/P6arp7ljQQ1NTmwFCx/zgCSHBSVY7 sQSkCpp4BAQ6SpzBpPhO7f0k2qi2412PbBBiV4IFrMMQ/OD76AaI3wnc/7UAQP1AGHIe hS7623q6wlk0xrMtfMuT6RT9fVlEzG9GxAQJPgpTpNo/0SfcKXxMymlTEblT5mg/wH2g 6J0DBRh75pmCFbHiHYW2kkFwU6ek6JKjTZzqoLR2oUw4kzPoIArO7OHwQ8rajkANLOmX jAeQ== ARC-Message-Signature: i=1; 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[90.118.159.96]) by smtp.googlemail.com with ESMTPSA id l19sm684566wrl.47.2017.09.08.00.14.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Sep 2017 00:14:15 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Corentin Labbe Subject: [PATCH v5 07/10] arm64: dts: allwinner: add snps, dwmac-mdio compatible to emac/mdio Date: Fri, 8 Sep 2017 09:11:53 +0200 Message-Id: <20170908071156.5115-8-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170908071156.5115-1-clabbe.montjoie@gmail.com> References: <20170908071156.5115-1-clabbe.montjoie@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org stmmac bindings docs said that its mdio node must have compatible = "snps,dwmac-mdio"; Since dwmac-sun8i does not have any good reasons to not doing it, all their MDIO node must have it. Signed-off-by: Corentin Labbe --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 + 1 file changed, 1 insertion(+) -- 2.13.5 diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 4dd9ffef0d80..5dceebd81f09 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -476,6 +476,7 @@ #size-cells = <0>; mdio: mdio { + compatible = "snps,dwmac-mdio"; #address-cells = <1>; #size-cells = <0>; }; From patchwork Fri Sep 8 07:11:54 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 112016 Delivered-To: patch@linaro.org Received: by 10.140.94.239 with SMTP id g102csp1126589qge; Fri, 8 Sep 2017 00:15:27 -0700 (PDT) X-Received: by 10.84.216.73 with SMTP id f9mr2449333plj.169.1504854927780; Fri, 08 Sep 2017 00:15:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504854927; cv=none; d=google.com; s=arc-20160816; b=X+LdfpnzzZIisBBeJCuJS3g+bQuvf7RThIItWH+VdAM1DZ8otYP9spGRLfRtAQW21X DNLZfd+KTquLQ72f12S5YS2qmkHdHS85ya15lAq5ADKWG6SlVZnTfha3BUBGXw5yNk2f XLtJbdlz1DJKxBSR7DQJ1JFCzVOoTtRwvq+ChRFRYgsmwYAjSvYT9iK1dIvdb5BvS3yM pWPPMrkuXWrvrEzsdWc1xKbo6kf5EO0te1Xx/C9o56JHx8YyqgDQyAnnEBOi22l/SnkG CZa2DCgXp5S//0Hn/SueFsuWmhdM1nLMd5PzFLvXR6dzZnbOPOPrgrps3647PQlFTcZv c13A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=ZDRqn6oM7YLvC7qyulEsdiG4u/Ek3wP9CmcxSAqe5YU=; b=H0cMbASOJ4OWMIj28ZK0G+fu//RCMECA66npFZQRBbLCYe1zMS128qazJ/l/JFEQuc Jkc6wWj+VkZrxcGSUQ2PClik63qmCx9Ryec+hLqi6nDjbOOme8Tew4baY5GpO6u/oz5O CUTZQtUSO6dBINDHmBW0rOkCs690qajA8bP5UrABc3VzBKR6U3JdZ6okEHmrNdfEJQG+ oXhYwXGJEFp41JU1uKaZwlih/WHvchLLwVd/SZH2Rr/hn6GxRcgHllac5Z7aTFe8yK9F EhDMPedQQwg+sgX19X71eWmibDejatjZhPql9HB/sAPwqgoNzsLvLOcJmw8fkKbuor8V D6XQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=Gx4ouKee; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[90.118.159.96]) by smtp.googlemail.com with ESMTPSA id l19sm684566wrl.47.2017.09.08.00.14.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Sep 2017 00:14:16 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Corentin Labbe Subject: [PATCH v5 08/10] net: stmmac: dwmac-sun8i: choose internal PHY via phy-is-integrated Date: Fri, 8 Sep 2017 09:11:54 +0200 Message-Id: <20170908071156.5115-9-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170908071156.5115-1-clabbe.montjoie@gmail.com> References: <20170908071156.5115-1-clabbe.montjoie@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The current way to find if the phy is internal is to compare DT phy-mode and emac_variant/internal_phy. But it will negate a possible future SoC where an external PHY use the same phy mode than the internal one. This patch adds a new way to find if the PHY is internal, via the phy-is-integrated property. Since the internal_phy variable does not need anymore to contain the xMII mode used by the internal PHY, it is still used for knowing the presence of an internal PHY, so it is modified to a boolean soc_has_internal_phy. Signed-off-by: Corentin Labbe Acked-by: Chen-Yu Tsai Reviewed-by: Florian Fainelli --- drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) -- 2.13.5 diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c index fffd6d5fc907..672553b652bd 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c @@ -41,14 +41,14 @@ * This value is used for disabling properly EMAC * and used as a good starting value in case of the * boot process(uboot) leave some stuff. - * @internal_phy: Does the MAC embed an internal PHY + * @soc_has_internal_phy: Does the MAC embed an internal PHY * @support_mii: Does the MAC handle MII * @support_rmii: Does the MAC handle RMII * @support_rgmii: Does the MAC handle RGMII */ struct emac_variant { u32 default_syscon_value; - int internal_phy; + bool soc_has_internal_phy; bool support_mii; bool support_rmii; bool support_rgmii; @@ -75,7 +75,7 @@ struct sunxi_priv_data { static const struct emac_variant emac_variant_h3 = { .default_syscon_value = 0x58000, - .internal_phy = PHY_INTERFACE_MODE_MII, + .soc_has_internal_phy = true, .support_mii = true, .support_rmii = true, .support_rgmii = true @@ -83,20 +83,20 @@ static const struct emac_variant emac_variant_h3 = { static const struct emac_variant emac_variant_v3s = { .default_syscon_value = 0x38000, - .internal_phy = PHY_INTERFACE_MODE_MII, + .soc_has_internal_phy = true, .support_mii = true }; static const struct emac_variant emac_variant_a83t = { .default_syscon_value = 0, - .internal_phy = 0, + .soc_has_internal_phy = false, .support_mii = true, .support_rgmii = true }; static const struct emac_variant emac_variant_a64 = { .default_syscon_value = 0, - .internal_phy = 0, + .soc_has_internal_phy = false, .support_mii = true, .support_rmii = true, .support_rgmii = true @@ -648,7 +648,7 @@ static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv) "Current syscon value is not the default %x (expect %x)\n", val, reg); - if (gmac->variant->internal_phy) { + if (gmac->variant->soc_has_internal_phy) { if (!gmac->use_internal_phy) { /* switch to external PHY interface */ reg &= ~H3_EPHY_SELECT; @@ -932,7 +932,7 @@ static int sun8i_dwmac_probe(struct platform_device *pdev) } plat_dat->interface = of_get_phy_mode(dev->of_node); - if (plat_dat->interface == gmac->variant->internal_phy) { + if (of_property_read_bool(plat_dat->phy_node, "phy-is-integrated")) { dev_info(&pdev->dev, "Will use internal PHY\n"); gmac->use_internal_phy = true; gmac->ephy_clk = of_clk_get(plat_dat->phy_node, 0); From patchwork Fri Sep 8 07:11:55 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 112015 Delivered-To: patch@linaro.org Received: by 10.140.94.239 with SMTP id g102csp1126116qge; Fri, 8 Sep 2017 00:14:58 -0700 (PDT) X-Received: by 10.99.113.94 with SMTP id b30mr2130057pgn.312.1504854897921; Fri, 08 Sep 2017 00:14:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504854897; cv=none; d=google.com; s=arc-20160816; b=VyLEZ2OxcLJNMtS2st5ebOlmatYE+3dsmMnbyLTcmVijfhcCIy1xPfcWdSYtDEck8X f0cONrnqoKf4ZDX8Z8hKdnYMaJQajuou3ZIEvppHY2Ux/x80TRihxI++djDBz94wCZ2X LfqOKQMHC7oWOE5N5/ppk+wW31Zk+PUxSJPWjFR7KuK7cJEeTtD2lRlRvmVsOAZYcpSg 1+2sxh/tcaZWfSVC/NqWiXGt1KstB8Q+Ky2vlZ/cMXab3BikqDsRle7j1V3X4gaw3Xed s9t5YzicFVS3MlwMR7MfKLFZFqetQln5B1QlBSbQkYfRL9WpFuS6Z6I6OTB5494LaRMh OuHA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=rJe9dMTgNrAKeH47d5eX7NcMOipT/COvEYhifR+x3YI=; b=ShiEgKtzCePp9yyJa5q5U+hJLhgpREqK1v3DZaVZwjqgRkxmkBch+Ob4RmqvyArojr Okcmyu+X0jq0uQxu+Of+EMHIOsXG6VP745wy3XzeInCt3GTz1UGBmHhizx/9VKkB8r6D /Nj3EDssQMyweiiahXus73BS9wT04w2oK0ielC8Y4f0RR+tazde91tsrjAs39G6rmpnz dNto6h9L23o6ampALOFNgQT58lhjwnVVTNJcgmcKuFxhj8/vHfJdpMWEy4woL7+MES0e VObPPpeMxFC4kGpZfo5UKJ2Rhx/h58uJmru3qfoXZQ+PUATjbDx3zqLiK0GK7z6IqeHm rweA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=Y7mNh5XT; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[90.118.159.96]) by smtp.googlemail.com with ESMTPSA id l19sm684566wrl.47.2017.09.08.00.14.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Sep 2017 00:14:17 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Corentin Labbe Subject: [PATCH v5 09/10] net: stmmac: snps, dwmac-mdio MDIOs are automatically registered Date: Fri, 8 Sep 2017 09:11:55 +0200 Message-Id: <20170908071156.5115-10-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170908071156.5115-1-clabbe.montjoie@gmail.com> References: <20170908071156.5115-1-clabbe.montjoie@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org stmmac bindings docs said that its mdio node must have compatible = "snps,dwmac-mdio"; Since dwmac-sun8i does not have any good reasons to not doing it, all their MDIO node must have it. Since these compatible is automatically registered, dwmac-sun8i compatible does not need to be in need_mdio_ids. Signed-off-by: Corentin Labbe --- drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 4 ---- 1 file changed, 4 deletions(-) -- 2.13.5 diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c index a366b3747eeb..3de5501e34fe 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c @@ -311,10 +311,6 @@ static int stmmac_dt_phy(struct plat_stmmacenet_data *plat, bool mdio = true; static const struct of_device_id need_mdio_ids[] = { { .compatible = "snps,dwc-qos-ethernet-4.10" }, - { .compatible = "allwinner,sun8i-a83t-emac" }, - { .compatible = "allwinner,sun8i-h3-emac" }, - { .compatible = "allwinner,sun8i-v3s-emac" }, - { .compatible = "allwinner,sun50i-a64-emac" }, }; /* If phy-handle property is passed from DT, use it as the PHY */ From patchwork Fri Sep 8 07:11:56 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 112014 Delivered-To: patch@linaro.org Received: by 10.140.94.239 with SMTP id g102csp1125685qge; Fri, 8 Sep 2017 00:14:30 -0700 (PDT) X-Received: by 10.99.114.76 with SMTP id c12mr2068743pgn.296.1504854869990; Fri, 08 Sep 2017 00:14:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504854869; cv=none; d=google.com; s=arc-20160816; b=uBdkl22Gy9ruHI4VkMASUXqv1SevkrqEO7yiemMH9uMdbjTdbCCeLLXBOXD+KhioDU 11eyvyFuvu1rj7nZ1N/ReByOGeHbWqhLIGxl3558UyHnko6bUMvELDddhB1OXEkv3aFD EOAzISJ7mB7B6SvIe8qobpbdFhdMsNN995eCYRkdReKyjLDlUrOxoYQ0FuQs7BIT1XLz NZ6JEddk5EEjtlOII3NicwlMawFxMIj+XePLq6lv2HR2xyqUGmHbaznLGNUivpsVxQ07 armvU1c4+h0MyaRTNXoxqTlMt5Ggxbg1xRSzrbbrkAkHGnKp/sXo/CuEjz8xXpXE9GAy C+rQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=4u7/ZPCRQyQggk4YAw5FLvttfswqgq4S5B8xflhFWNU=; b=BhGgfGjH1/d8bZmzxbVKnGbjqmhEmBlLOrYmB4Fjjc0jGBJDz8arC3pKpKsQrPnut6 EoKdPUweKkSK90nRQy8azODtd7LNRLb9GeXIfVfDcYmeyrvWfnjXQ2EzBQDWf9CaataY /E1lqONM8qji7Ex8H3XGoRGz4tuooRPbWpVY4Qy7GySStScrXCEPbpsNAhprfr1pMd/k x8caXkjXn6MhD4hOvBmSEKI40kegAmecq1xpyiDyV+8QSnZNvDyuGTsGT3Hzjrd2AnCm I5tDXgkSSeKLgzmzVKgBmDImZqhYmxpNVQ2ctSTBefC17HRWSqszD/xdfL36gQmZu4cO lpdQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=TbnzA1YB; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[90.118.159.96]) by smtp.googlemail.com with ESMTPSA id l19sm684566wrl.47.2017.09.08.00.14.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Sep 2017 00:14:18 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Corentin Labbe Subject: [PATCH v5 10/10] net: stmmac: dwmac-sun8i: Handle integrated/external MDIOs Date: Fri, 8 Sep 2017 09:11:56 +0200 Message-Id: <20170908071156.5115-11-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170908071156.5115-1-clabbe.montjoie@gmail.com> References: <20170908071156.5115-1-clabbe.montjoie@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Allwinner H3 SoC have two distinct MDIO bus, only one could be active at the same time. The selection of the active MDIO bus are done via some bits in the EMAC register of the system controller. This patch implement this MDIO switch via a custom MDIO-mux. Signed-off-by: Corentin Labbe --- drivers/net/ethernet/stmicro/stmmac/Kconfig | 1 + drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 116 +++++++++++++++++++--- 2 files changed, 104 insertions(+), 13 deletions(-) -- 2.13.5 diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig index 97035766c291..e28c0d2c58e9 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig @@ -159,6 +159,7 @@ config DWMAC_SUN8I tristate "Allwinner sun8i GMAC support" default ARCH_SUNXI depends on OF && (ARCH_SUNXI || COMPILE_TEST) + select MDIO_BUS_MUX ---help--- Support for Allwinner H3 A83T A64 EMAC ethernet controllers. diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c index 672553b652bd..ddd5695886ac 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -71,6 +72,7 @@ struct sunxi_priv_data { const struct emac_variant *variant; struct regmap *regmap; bool use_internal_phy; + void *mux_handle; }; static const struct emac_variant emac_variant_h3 = { @@ -195,6 +197,9 @@ static const struct emac_variant emac_variant_a64 = { #define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */ #define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */ #define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */ +#define H3_EPHY_MUX_MASK (H3_EPHY_SHUTDOWN | H3_EPHY_SELECT) +#define DWMAC_sUN8I_MDIO_MUX_INTERNAL_ID 0 +#define DWMAC_sUN8I_MDIO_MUX_EXTERNAL_ID 1 /* H3/A64 specific bits */ #define SYSCON_RMII_EN BIT(13) /* 1: enable RMII (overrides EPIT) */ @@ -634,6 +639,76 @@ static int sun8i_dwmac_reset(struct stmmac_priv *priv) return 0; } +/* MDIO multiplexing switch function + * This function is called by the mdio-mux layer when it thinks the mdio bus + * multiplexer needs to switch. + * 'current_child' is the current value of the mux register + * 'desired_child' is the value of the 'reg' property of the target child MDIO + * node. + * The first time this function is called, current_child == -1. + * If current_child == desired_child, then the mux is already set to the + * correct bus. + * + * Note that we do not use reg/mask like mdio-mux-mmioreg because we need to + * know easily which bus is used (reset must be done only for desired bus). + */ +static int mdio_mux_syscon_switch_fn(int current_child, int desired_child, + void *data) +{ + struct stmmac_priv *priv = data; + struct sunxi_priv_data *gmac = priv->plat->bsp_priv; + u32 reg, val; + int ret = 0; + bool need_reset = false; + + if (current_child ^ desired_child) { + regmap_read(gmac->regmap, SYSCON_EMAC_REG, ®); + switch (desired_child) { + case DWMAC_sUN8I_MDIO_MUX_INTERNAL_ID: + dev_info(priv->device, "Switch mux to internal PHY"); + val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SELECT; + if (gmac->use_internal_phy) + need_reset = true; + break; + case DWMAC_sUN8I_MDIO_MUX_EXTERNAL_ID: + dev_info(priv->device, "Switch mux to external PHY"); + val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SHUTDOWN; + if (!gmac->use_internal_phy) + need_reset = true; + break; + default: + dev_err(priv->device, "Invalid child id %x\n", desired_child); + return -EINVAL; + } + regmap_write(gmac->regmap, SYSCON_EMAC_REG, val); + /* After changing syscon value, the MAC need reset or it will use + * the last value (and so the last PHY set). + * Reset is necessary only when we reach the needed MDIO, + * it timeout in other case. + */ + if (need_reset) + ret = sun8i_dwmac_reset(priv); + else + dev_dbg(priv->device, "skipped reset\n"); + } + return ret; +} + +static int sun8i_dwmac_register_mdio_mux(struct stmmac_priv *priv) +{ + int ret; + struct device_node *mdio_mux; + struct sunxi_priv_data *gmac = priv->plat->bsp_priv; + + mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux"); + if (!mdio_mux) + return -ENODEV; + + ret = mdio_mux_init(priv->device, mdio_mux, mdio_mux_syscon_switch_fn, + &gmac->mux_handle, priv, priv->mii); + return ret; +} + static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv) { struct sunxi_priv_data *gmac = priv->plat->bsp_priv; @@ -649,12 +724,7 @@ static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv) val, reg); if (gmac->variant->soc_has_internal_phy) { - if (!gmac->use_internal_phy) { - /* switch to external PHY interface */ - reg &= ~H3_EPHY_SELECT; - } else { - reg |= H3_EPHY_SELECT; - reg &= ~H3_EPHY_SHUTDOWN; + if (gmac->use_internal_phy) { dev_dbg(priv->device, "Select internal_phy %x\n", reg); if (of_property_read_bool(priv->plat->phy_node, @@ -743,6 +813,8 @@ static void sun8i_dwmac_unset_syscon(struct sunxi_priv_data *gmac) { u32 reg = gmac->variant->default_syscon_value; + if (gmac->variant->soc_has_internal_phy) + mdio_mux_uninit(gmac->mux_handle); regmap_write(gmac->regmap, SYSCON_EMAC_REG, reg); } @@ -801,12 +873,6 @@ static int sun8i_power_phy(struct stmmac_priv *priv) if (ret) return ret; - /* After changing syscon value, the MAC need reset or it will use - * the last value (and so the last PHY set. - */ - ret = sun8i_dwmac_reset(priv); - if (ret) - return ret; return 0; } @@ -889,6 +955,8 @@ static int sun8i_dwmac_probe(struct platform_device *pdev) struct sunxi_priv_data *gmac; struct device *dev = &pdev->dev; int ret; + struct stmmac_priv *priv; + struct net_device *ndev; ret = stmmac_get_platform_resources(pdev, &stmmac_res); if (ret) @@ -973,9 +1041,31 @@ static int sun8i_dwmac_probe(struct platform_device *pdev) ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); if (ret) - sun8i_dwmac_exit(pdev, plat_dat->bsp_priv); + goto dwmac_exit; + + ndev = dev_get_drvdata(&pdev->dev); + priv = netdev_priv(ndev); + /* The mux must be registered after parent MDIO + * so after stmmac_dvr_probe() + */ + if (gmac->variant->soc_has_internal_phy) { + ret = sun8i_dwmac_register_mdio_mux(priv); + if (ret) { + dev_err(&pdev->dev, "Failed to register mux\n"); + goto dwmac_mux; + } + } else { + ret = sun8i_dwmac_reset(priv); + if (ret) + goto dwmac_exit; + } return ret; +dwmac_mux: + sun8i_dwmac_unset_syscon(gmac); +dwmac_exit: + sun8i_dwmac_exit(pdev, plat_dat->bsp_priv); +return ret; } static const struct of_device_id sun8i_dwmac_match[] = {