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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR03MB2692 Subject: [dpdk-dev] [PATCH v3 01/27] bus/fslmc: qbman replace word copy with memcpy X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Haiying Wang The word_copy is not as efficient as expected, so remove it from this driver. Signed-off-by: Haiying Wang Signed-off-by: Hemant Agrawal --- drivers/bus/fslmc/qbman/include/compat.h | 42 -------------------------------- drivers/bus/fslmc/qbman/qbman_portal.c | 12 ++++----- drivers/bus/fslmc/qbman/qbman_sys.h | 9 ------- 3 files changed, 5 insertions(+), 58 deletions(-) -- 2.7.4 diff --git a/drivers/bus/fslmc/qbman/include/compat.h b/drivers/bus/fslmc/qbman/include/compat.h index 529f1ea..7b69fd1 100644 --- a/drivers/bus/fslmc/qbman/include/compat.h +++ b/drivers/bus/fslmc/qbman/include/compat.h @@ -229,48 +229,6 @@ typedef uint32_t phandle; #define __raw_readl(p) (*(const volatile unsigned int *)(p)) #define __raw_writel(v, p) {*(volatile unsigned int *)(p) = (v); } -/* memcpy() stuff - when you know alignments in advance */ -#ifdef CONFIG_TRY_BETTER_MEMCPY -static inline void copy_words(void *dest, const void *src, size_t sz) -{ - u32 *__dest = dest; - const u32 *__src = src; - size_t __sz = sz >> 2; - - QBMAN_BUG_ON((unsigned long)dest & 0x3); - QBMAN_BUG_ON((unsigned long)src & 0x3); - QBMAN_BUG_ON(sz & 0x3); - while (__sz--) - *(__dest++) = *(__src++); -} - -static inline void copy_shorts(void *dest, const void *src, size_t sz) -{ - u16 *__dest = dest; - const u16 *__src = src; - size_t __sz = sz >> 1; - - QBMAN_BUG_ON((unsigned long)dest & 0x1); - QBMAN_BUG_ON((unsigned long)src & 0x1); - QBMAN_BUG_ON(sz & 0x1); - while (__sz--) - *(__dest++) = *(__src++); -} - -static inline void copy_bytes(void *dest, const void *src, size_t sz) -{ - u8 *__dest = dest; - const u8 *__src = src; - - while (sz--) - *(__dest++) = *(__src++); -} -#else -#define copy_words memcpy -#define copy_shorts memcpy -#define copy_bytes memcpy -#endif - /* Completion stuff */ #define DECLARE_COMPLETION(n) int n = 0 #define complete(n) { *n = 1; } diff --git a/drivers/bus/fslmc/qbman/qbman_portal.c b/drivers/bus/fslmc/qbman/qbman_portal.c index dd62e9a..f360760 100644 --- a/drivers/bus/fslmc/qbman/qbman_portal.c +++ b/drivers/bus/fslmc/qbman/qbman_portal.c @@ -480,8 +480,8 @@ static int qbman_swp_enqueue_array_mode(struct qbman_swp *s, return -EBUSY; p = qbman_cena_write_start_wo_shadow(&s->sys, QBMAN_CENA_SWP_EQCR(EQAR_IDX(eqar))); - word_copy(&p[1], &cl[1], 7); - word_copy(&p[8], fd, sizeof(*fd) >> 2); + memcpy(&p[1], &cl[1], 28); + memcpy(&p[8], fd, sizeof(*fd)); /* Set the verb byte, have to substitute in the valid-bit */ lwsync(); p[0] = cl[0] | EQAR_VB(eqar); @@ -512,8 +512,8 @@ static int qbman_swp_enqueue_ring_mode(struct qbman_swp *s, p = qbman_cena_write_start_wo_shadow(&s->sys, QBMAN_CENA_SWP_EQCR(s->eqcr.pi & 7)); - word_copy(&p[1], &cl[1], 7); - word_copy(&p[8], fd, sizeof(*fd) >> 2); + memcpy(&p[1], &cl[1], 28); + memcpy(&p[8], fd, sizeof(*fd)); lwsync(); /* Set the verb byte, have to substitute in the valid-bit */ p[0] = cl[0] | s->eqcr.pi_vb; @@ -549,9 +549,7 @@ int qbman_swp_fill_ring(struct qbman_swp *s, } p = qbman_cena_write_start_wo_shadow(&s->sys, QBMAN_CENA_SWP_EQCR((s->eqcr.pi/* +burst_index */) & 7)); - /* word_copy(&p[1], &cl[1], 7); */ memcpy(&p[1], &cl[1], 7 * 4); - /* word_copy(&p[8], fd, sizeof(*fd) >> 2); */ memcpy(&p[8], fd, sizeof(struct qbman_fd)); /* lwsync(); */ @@ -799,7 +797,7 @@ int qbman_swp_pull(struct qbman_swp *s, struct qbman_pull_desc *d) */ qb_attr_code_encode(&code_pull_token, cl, s->desc.idx + 1); p = qbman_cena_write_start_wo_shadow(&s->sys, QBMAN_CENA_SWP_VDQCR); - word_copy(&p[1], &cl[1], 3); + memcpy(&p[1], &cl[1], 12); /* Set the verb byte, have to substitute in the valid-bit */ lwsync(); p[0] = cl[0] | s->vdq.valid_bit; diff --git a/drivers/bus/fslmc/qbman/qbman_sys.h b/drivers/bus/fslmc/qbman/qbman_sys.h index 5dbcaa5..9ea55de 100644 --- a/drivers/bus/fslmc/qbman/qbman_sys.h +++ b/drivers/bus/fslmc/qbman/qbman_sys.h @@ -47,15 +47,6 @@ #undef QBMAN_CINH_TRACE #undef QBMAN_CENA_TRACE -static inline void word_copy(void *d, const void *s, unsigned int cnt) -{ - uint32_t *dd = d; - const uint32_t *ss = s; - - while (cnt--) - *(dd++) = *(ss++); -} - /* Currently, the CENA support code expects each 32-bit word to be written in * host order, and these are converted to hardware (little-endian) order on * command submission. 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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN2PR03MB2368 Subject: [dpdk-dev] [PATCH v3 02/27] bus/fslmc: remove the export for qbman version function X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This func is not required to be used outside of the qbman driver. Signed-off-by: Hemant Agrawal --- drivers/bus/fslmc/qbman/include/fsl_qbman_base.h | 4 ---- drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h | 2 -- drivers/bus/fslmc/qbman/qbman_portal.c | 7 ------- drivers/bus/fslmc/qbman/qbman_portal.h | 1 + drivers/bus/fslmc/qbman/qbman_private.h | 4 ++++ 5 files changed, 5 insertions(+), 13 deletions(-) -- 2.7.4 diff --git a/drivers/bus/fslmc/qbman/include/fsl_qbman_base.h b/drivers/bus/fslmc/qbman/include/fsl_qbman_base.h index ee4b772..1415960 100644 --- a/drivers/bus/fslmc/qbman/include/fsl_qbman_base.h +++ b/drivers/bus/fslmc/qbman/include/fsl_qbman_base.h @@ -38,10 +38,6 @@ typedef uint64_t dma_addr_t; * */ -#define QMAN_REV_4000 0x04000000 -#define QMAN_REV_4100 0x04010000 -#define QMAN_REV_4101 0x04010001 - /** * struct qbman_block_desc - qbman block descriptor structure * @ccsr_reg_bar: CCSR register map. diff --git a/drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h b/drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h index 9e9047e..23c3d13 100644 --- a/drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h +++ b/drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h @@ -1132,6 +1132,4 @@ int qbman_swp_send_multiple(struct qbman_swp *s, int qbman_check_command_complete(struct qbman_swp *s, const struct qbman_result *dq); - -int qbman_get_version(void); #endif /* !_FSL_QBMAN_PORTAL_H */ diff --git a/drivers/bus/fslmc/qbman/qbman_portal.c b/drivers/bus/fslmc/qbman/qbman_portal.c index f360760..97df703 100644 --- a/drivers/bus/fslmc/qbman/qbman_portal.c +++ b/drivers/bus/fslmc/qbman/qbman_portal.c @@ -105,8 +105,6 @@ struct qb_attr_code code_sdqcr_dqsrc = QB_CODE(0, 0, 16); #define MAX_QBMAN_PORTALS 35 static struct qbman_swp *portal_idx_map[MAX_QBMAN_PORTALS]; -uint32_t qman_version; - /*********************************/ /* Portal constructor/destructor */ /*********************************/ @@ -1579,8 +1577,3 @@ int qbman_swp_send_multiple(struct qbman_swp *s, return sent; } - -int qbman_get_version(void) -{ - return qman_version; -} diff --git a/drivers/bus/fslmc/qbman/qbman_portal.h b/drivers/bus/fslmc/qbman/qbman_portal.h index 7aa1d4f..8018048 100644 --- a/drivers/bus/fslmc/qbman/qbman_portal.h +++ b/drivers/bus/fslmc/qbman/qbman_portal.h @@ -29,6 +29,7 @@ #include "qbman_private.h" #include +uint32_t qman_version; /* All QBMan command and result structures use this "valid bit" encoding */ #define QB_VALID_BIT ((uint32_t)0x80) diff --git a/drivers/bus/fslmc/qbman/qbman_private.h b/drivers/bus/fslmc/qbman/qbman_private.h index 292ec6a..b98c330 100644 --- a/drivers/bus/fslmc/qbman/qbman_private.h +++ b/drivers/bus/fslmc/qbman/qbman_private.h @@ -171,4 +171,8 @@ static inline void hexdump(const void *ptr, size_t sz) __hexdump(start, end, p, sz, c); } +#define QMAN_REV_4000 0x04000000 +#define QMAN_REV_4100 0x04010000 +#define QMAN_REV_4101 0x04010001 + #include "qbman_sys.h" From patchwork Sat Sep 16 10:52:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemant Agrawal X-Patchwork-Id: 112785 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp1614642qgf; Sat, 16 Sep 2017 03:53:47 -0700 (PDT) X-Google-Smtp-Source: ADKCNb65Bd4+Ph0P19AZ1Ye7Ywm0eFDBiGm+aBLkVDdGRLQaSsyD0JdkIHUFVp6XIXRFUqYmJVML X-Received: by 10.223.165.29 with SMTP id i29mr23163546wrb.163.1505559227147; Sat, 16 Sep 2017 03:53:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505559227; cv=none; d=google.com; s=arc-20160816; b=S4eb2sbDdcuUok+DeL+rBeF0yH7pLaNdcKo4o5w74ssBcBwatszl2Gy8OgXGaSl01m uEJG9ExqkW2/bo7EFLhdyiDf9eFCc00YOxrgo98nDpt+H427cibr/vLHtaUmfqIc6uxS 1w/fJssgoHPekxIHSpqqvectriwmCuKaaaKeqw4jBcZrAmSlHQZlBKmKDPZTmsRSuKU1 5psrbh+SfLQWK0KDJi662Dwwl29m8HXAISzs12aeVnpv+gkxH2K2yp/nRoWKbEmKUTYu PMiyM9UVyMw66s9YKy0SgqyNruXivoDKpkoUhU0WNcPyxEFTKgpB3UPswRAdx8HbOdzG 62DQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:spamdiagnosticmetadata :spamdiagnosticoutput:mime-version:references:in-reply-to:message-id :date:cc:to:from:arc-authentication-results; bh=T+AeHQS+nzkgRGzh2aSeyds13Sq4qKUkHzK3UHQlfUs=; b=C+Zp5apLNEiNbOeT499yYqQ8EtID02ixqKAmJq6TI7niTuBSC9n73Yw2ykzJJRb5+r CyfNGs6df+n0LtV6S0PJEZMd86zyy85L0fBlNrD1fbxGOp3ajX+HSquTkzazCCOw4A23 dVsiORJmEmnvawnvSRfdM+xGuT06nGhfkdpHYMSixYFtPHthbfPWNspr7YjMGWGY295p /21aRol6f1zOQobXWA87p1G5QCa7wtQXLEiz0zagnleQ1cOOm8bye0jkHIoS1OezNXsL QiZZvHfePNw7XOKRn5E2yNymFgvtIBUFsvBntcA8A2vEHS5fMj5u4XEV27Rl14iE3nw4 Hmgw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from dpdk.org (dpdk.org. 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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR03MB2694 Subject: [dpdk-dev] [PATCH v3 03/27] bus/fslmc: add qbman API to do enqueue with multiple frames X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Haiying Wang Clean it up and update the prototype. Signed-off-by: Haiying Wang Signed-off-by: Hemant Agrawal --- drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h | 32 ++-- drivers/bus/fslmc/qbman/qbman_portal.c | 200 +++++++-------------- drivers/bus/fslmc/rte_bus_fslmc_version.map | 3 +- drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 2 +- drivers/event/dpaa2/dpaa2_eventdev.c | 2 +- drivers/net/dpaa2/dpaa2_rxtx.c | 2 +- 6 files changed, 83 insertions(+), 158 deletions(-) -- 2.7.4 diff --git a/drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h b/drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h index 23c3d13..fe1cc94 100644 --- a/drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h +++ b/drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h @@ -914,19 +914,33 @@ void qbman_eq_desc_set_dca(struct qbman_eq_desc *d, int enable, int qbman_swp_enqueue(struct qbman_swp *s, const struct qbman_eq_desc *d, const struct qbman_fd *fd); /** - * qbman_swp_enqueue_multiple_eqdesc() - Enqueue multiple frames with separte - * enqueue descriptors. + * qbman_swp_enqueue_multiple() - Enqueue multiple frames with same + eq descriptor * @s: the software portal used for enqueue. - * @d: the enqueue descriptors + * @d: the enqueue descriptor. * @fd: the frame descriptor to be enqueued. * @num_frames: the number of the frames to be enqueued. * * Return the number of enqueued frames, -EBUSY if the EQCR is not ready. */ -int qbman_swp_enqueue_multiple_eqdesc(struct qbman_swp *s, +int qbman_swp_enqueue_multiple(struct qbman_swp *s, const struct qbman_eq_desc *d, const struct qbman_fd *fd, int num_frames); +/** + * qbman_swp_enqueue_multiple_desc() - Enqueue multiple frames with + * individual eq descriptor. + * @s: the software portal used for enqueue. + * @d: the enqueue descriptor. + * @fd: the frame descriptor to be enqueued. + * @num_frames: the number of the frames to be enqueued. + * + * Return the number of enqueued frames, -EBUSY if the EQCR is not ready. + */ +int qbman_swp_enqueue_multiple_desc(struct qbman_swp *s, + const struct qbman_eq_desc *d, + const struct qbman_fd *fd, + int num_frames); /* TODO: * qbman_swp_enqueue_thresh() - Set threshold for EQRI interrupt. @@ -1119,16 +1133,6 @@ int qbman_swp_CDAN_disable(struct qbman_swp *s, uint16_t channelid); */ int qbman_swp_CDAN_set_context_enable(struct qbman_swp *s, uint16_t channelid, uint64_t ctx); -int qbman_swp_fill_ring(struct qbman_swp *s, - const struct qbman_eq_desc *d, - const struct qbman_fd *fd, - uint8_t burst_index); -int qbman_swp_flush_ring(struct qbman_swp *s); -void qbman_sync(void); -int qbman_swp_send_multiple(struct qbman_swp *s, - const struct qbman_eq_desc *d, - const struct qbman_fd *fd, - int frames_to_send); int qbman_check_command_complete(struct qbman_swp *s, const struct qbman_result *dq); diff --git a/drivers/bus/fslmc/qbman/qbman_portal.c b/drivers/bus/fslmc/qbman/qbman_portal.c index 97df703..f212829 100644 --- a/drivers/bus/fslmc/qbman/qbman_portal.c +++ b/drivers/bus/fslmc/qbman/qbman_portal.c @@ -525,15 +525,26 @@ static int qbman_swp_enqueue_ring_mode(struct qbman_swp *s, return 0; } -int qbman_swp_fill_ring(struct qbman_swp *s, - const struct qbman_eq_desc *d, - const struct qbman_fd *fd, - __attribute__((unused)) uint8_t burst_index) +int qbman_swp_enqueue(struct qbman_swp *s, const struct qbman_eq_desc *d, + const struct qbman_fd *fd) +{ + if (s->sys.eqcr_mode == qman_eqcr_vb_array) + return qbman_swp_enqueue_array_mode(s, d, fd); + else /* Use ring mode by default */ + return qbman_swp_enqueue_ring_mode(s, d, fd); +} + +int qbman_swp_enqueue_multiple(struct qbman_swp *s, + const struct qbman_eq_desc *d, + const struct qbman_fd *fd, + int num_frames) { uint32_t *p; const uint32_t *cl = qb_cl(d); - uint32_t eqcr_ci; + uint32_t eqcr_ci, eqcr_pi; uint8_t diff; + int i, num_enqueued = 0; + uint64_t addr_cena; if (!s->eqcr.available) { eqcr_ci = s->eqcr.ci; @@ -543,62 +554,58 @@ int qbman_swp_fill_ring(struct qbman_swp *s, eqcr_ci, s->eqcr.ci); s->eqcr.available += diff; if (!diff) - return -EBUSY; + return 0; } - p = qbman_cena_write_start_wo_shadow(&s->sys, - QBMAN_CENA_SWP_EQCR((s->eqcr.pi/* +burst_index */) & 7)); - memcpy(&p[1], &cl[1], 7 * 4); - memcpy(&p[8], fd, sizeof(struct qbman_fd)); - - /* lwsync(); */ - p[0] = cl[0] | s->eqcr.pi_vb; - - s->eqcr.pi++; - s->eqcr.pi &= 0xF; - s->eqcr.available--; - if (!(s->eqcr.pi & 7)) - s->eqcr.pi_vb ^= QB_VALID_BIT; - - return 0; -} -int qbman_swp_flush_ring(struct qbman_swp *s) -{ - void *ptr = s->sys.addr_cena; + eqcr_pi = s->eqcr.pi; + num_enqueued = (s->eqcr.available < num_frames) ? + s->eqcr.available : num_frames; + s->eqcr.available -= num_enqueued; + /* Fill in the EQCR ring */ + for (i = 0; i < num_enqueued; i++) { + p = qbman_cena_write_start_wo_shadow(&s->sys, + QBMAN_CENA_SWP_EQCR(eqcr_pi & 7)); + memcpy(&p[1], &cl[1], 28); + memcpy(&p[8], &fd[i], sizeof(*fd)); + eqcr_pi++; + eqcr_pi &= 0xF; + } - dcbf((uint64_t)ptr); - dcbf((uint64_t)ptr + 0x40); - dcbf((uint64_t)ptr + 0x80); - dcbf((uint64_t)ptr + 0xc0); - dcbf((uint64_t)ptr + 0x100); - dcbf((uint64_t)ptr + 0x140); - dcbf((uint64_t)ptr + 0x180); - dcbf((uint64_t)ptr + 0x1c0); + lwsync(); - return 0; -} + /* Set the verb byte, have to substitute in the valid-bit */ + eqcr_pi = s->eqcr.pi; + for (i = 0; i < num_enqueued; i++) { + p = qbman_cena_write_start_wo_shadow(&s->sys, + QBMAN_CENA_SWP_EQCR(eqcr_pi & 7)); + p[0] = cl[0] | s->eqcr.pi_vb; + eqcr_pi++; + eqcr_pi &= 0xF; + if (!(eqcr_pi & 7)) + s->eqcr.pi_vb ^= QB_VALID_BIT; + } -void qbman_sync(void) -{ - lwsync(); -} + /* Flush all the cacheline without load/store in between */ + eqcr_pi = s->eqcr.pi; + addr_cena = (uint64_t)s->sys.addr_cena; + for (i = 0; i < num_enqueued; i++) { + dcbf((uint64_t *)(addr_cena + + QBMAN_CENA_SWP_EQCR(eqcr_pi & 7))); + eqcr_pi++; + eqcr_pi &= 0xF; + } + s->eqcr.pi = eqcr_pi; -int qbman_swp_enqueue(struct qbman_swp *s, const struct qbman_eq_desc *d, - const struct qbman_fd *fd) -{ - if (s->sys.eqcr_mode == qman_eqcr_vb_array) - return qbman_swp_enqueue_array_mode(s, d, fd); - else /* Use ring mode by default */ - return qbman_swp_enqueue_ring_mode(s, d, fd); + return num_enqueued; } -int qbman_swp_enqueue_multiple_eqdesc(struct qbman_swp *s, - const struct qbman_eq_desc *d, - const struct qbman_fd *fd, - int num_frames) +int qbman_swp_enqueue_multiple_desc(struct qbman_swp *s, + const struct qbman_eq_desc *d, + const struct qbman_fd *fd, + int num_frames) { uint32_t *p; - const uint32_t *cl = qb_cl(d); + const uint32_t *cl; uint32_t eqcr_ci, eqcr_pi; uint8_t diff; int i, num_enqueued = 0; @@ -623,29 +630,26 @@ int qbman_swp_enqueue_multiple_eqdesc(struct qbman_swp *s, for (i = 0; i < num_enqueued; i++) { p = qbman_cena_write_start_wo_shadow(&s->sys, QBMAN_CENA_SWP_EQCR(eqcr_pi & 7)); + cl = qb_cl(&d[i]); memcpy(&p[1], &cl[1], 28); memcpy(&p[8], &fd[i], sizeof(*fd)); eqcr_pi++; eqcr_pi &= 0xF; - /*Pointing to the next enqueue descriptor*/ - cl += (sizeof(struct qbman_eq_desc) / sizeof(uint32_t)); } lwsync(); /* Set the verb byte, have to substitute in the valid-bit */ eqcr_pi = s->eqcr.pi; - cl = qb_cl(d); for (i = 0; i < num_enqueued; i++) { p = qbman_cena_write_start_wo_shadow(&s->sys, QBMAN_CENA_SWP_EQCR(eqcr_pi & 7)); + cl = qb_cl(&d[i]); p[0] = cl[0] | s->eqcr.pi_vb; eqcr_pi++; eqcr_pi &= 0xF; if (!(eqcr_pi & 7)) s->eqcr.pi_vb ^= QB_VALID_BIT; - /*Pointing to the next enqueue descriptor*/ - cl += (sizeof(struct qbman_eq_desc) / sizeof(uint32_t)); } /* Flush all the cacheline without load/store in between */ @@ -1493,87 +1497,3 @@ struct qbman_result *qbman_get_dqrr_from_idx(struct qbman_swp *s, uint8_t idx) dq = qbman_cena_read(&s->sys, QBMAN_CENA_SWP_DQRR(idx)); return dq; } - -int qbman_swp_send_multiple(struct qbman_swp *s, - const struct qbman_eq_desc *d, - const struct qbman_fd *fd, - int frames_to_send) -{ - uint32_t *p; - const uint32_t *cl = qb_cl(d); - uint32_t eqcr_ci; - uint8_t diff; - int sent = 0; - int i; - int initial_pi = s->eqcr.pi; - uint64_t start_pointer; - - if (!s->eqcr.available) { - eqcr_ci = s->eqcr.ci; - s->eqcr.ci = qbman_cena_read_reg(&s->sys, - QBMAN_CENA_SWP_EQCR_CI) & 0xF; - diff = qm_cyc_diff(QBMAN_EQCR_SIZE, - eqcr_ci, s->eqcr.ci); - if (!diff) - goto done; - s->eqcr.available += diff; - } - - /* we are trying to send frames_to_send, - * if we have enough space in the ring - */ - while (s->eqcr.available && frames_to_send--) { - p = qbman_cena_write_start_wo_shadow_fast(&s->sys, - QBMAN_CENA_SWP_EQCR((initial_pi) & 7)); - /* Write command (except of first byte) and FD */ - memcpy(&p[1], &cl[1], 7 * 4); - memcpy(&p[8], &fd[sent], sizeof(struct qbman_fd)); - - initial_pi++; - initial_pi &= 0xF; - s->eqcr.available--; - sent++; - } - -done: - initial_pi = s->eqcr.pi; - lwsync(); - - /* in order for flushes to complete faster: - * we use a following trick: we record all lines in 32 bit word - */ - - initial_pi = s->eqcr.pi; - for (i = 0; i < sent; i++) { - p = qbman_cena_write_start_wo_shadow_fast(&s->sys, - QBMAN_CENA_SWP_EQCR((initial_pi) & 7)); - - p[0] = cl[0] | s->eqcr.pi_vb; - initial_pi++; - initial_pi &= 0xF; - - if (!(initial_pi & 7)) - s->eqcr.pi_vb ^= QB_VALID_BIT; - } - - initial_pi = s->eqcr.pi; - - /* We need to flush all the lines but without - * load/store operations between them. - * We assign start_pointer before we start loop so that - * in loop we do not read it from memory - */ - start_pointer = (uint64_t)s->sys.addr_cena; - for (i = 0; i < sent; i++) { - p = (uint32_t *)(start_pointer - + QBMAN_CENA_SWP_EQCR(initial_pi & 7)); - dcbf((uint64_t)p); - initial_pi++; - initial_pi &= 0xF; - } - - /* Update producer index for the next call */ - s->eqcr.pi = initial_pi; - - return sent; -} diff --git a/drivers/bus/fslmc/rte_bus_fslmc_version.map b/drivers/bus/fslmc/rte_bus_fslmc_version.map index 6ac256d..13fb46a 100644 --- a/drivers/bus/fslmc/rte_bus_fslmc_version.map +++ b/drivers/bus/fslmc/rte_bus_fslmc_version.map @@ -69,7 +69,8 @@ DPDK_17.08 { qbman_result_SCN_state_in_mem; qbman_swp_dqrr_consume; qbman_swp_dqrr_next; - qbman_swp_enqueue_multiple_eqdesc; + qbman_swp_enqueue_multiple; + qbman_swp_enqueue_multiple_desc; qbman_swp_interrupt_clear_status; qbman_swp_push_set; rte_dpaa2_alloc_dpci_dev; diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c index 95c3951..094cf30 100644 --- a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c +++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c @@ -634,7 +634,7 @@ dpaa2_sec_enqueue_burst(void *qp, struct rte_crypto_op **ops, } loop = 0; while (loop < frames_to_send) { - loop += qbman_swp_send_multiple(swp, &eqdesc, + loop += qbman_swp_enqueue_multiple(swp, &eqdesc, &fd_arr[loop], frames_to_send - loop); } diff --git a/drivers/event/dpaa2/dpaa2_eventdev.c b/drivers/event/dpaa2/dpaa2_eventdev.c index cf2d274..81286a8 100644 --- a/drivers/event/dpaa2/dpaa2_eventdev.c +++ b/drivers/event/dpaa2/dpaa2_eventdev.c @@ -144,7 +144,7 @@ dpaa2_eventdev_enqueue_burst(void *port, const struct rte_event ev[], } loop = 0; while (loop < frames_to_send) { - loop += qbman_swp_enqueue_multiple_eqdesc(swp, + loop += qbman_swp_enqueue_multiple_desc(swp, &eqdesc[loop], &fd_arr[loop], frames_to_send - loop); } diff --git a/drivers/net/dpaa2/dpaa2_rxtx.c b/drivers/net/dpaa2/dpaa2_rxtx.c index 3c057a3..4342c73 100644 --- a/drivers/net/dpaa2/dpaa2_rxtx.c +++ b/drivers/net/dpaa2/dpaa2_rxtx.c @@ -622,7 +622,7 @@ dpaa2_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts) } loop = 0; while (loop < frames_to_send) { - loop += qbman_swp_send_multiple(swp, &eqdesc, + loop += qbman_swp_enqueue_multiple(swp, &eqdesc, &fd_arr[loop], frames_to_send - loop); } From patchwork Sat Sep 16 10:52:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemant Agrawal X-Patchwork-Id: 112786 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp1614771qgf; Sat, 16 Sep 2017 03:53:59 -0700 (PDT) X-Google-Smtp-Source: ADKCNb59rTnKk37aOEsYl4cXy5K4qbcK5W8qv25h1QCSKi98eEGHPFZz/v1fgsOU9R3GB44NkPJG X-Received: by 10.223.178.166 with SMTP id g35mr24784443wrd.262.1505559239032; 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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR03MB2362 Subject: [dpdk-dev] [PATCH v3 04/27] bus/fslmc: support up to 32 frames in one volatile dequeue X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Haiying Wang QMan5.0 supports up to 32 frames in one volatile dequeue command. For the older Qman versions which only support up to 16 frames, the highest bit in NUMF will be ignored. Signed-off-by: Haiying Wang Signed-off-by: Hemant Agrawal --- drivers/bus/fslmc/qbman/qbman_portal.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) -- 2.7.4 diff --git a/drivers/bus/fslmc/qbman/qbman_portal.c b/drivers/bus/fslmc/qbman/qbman_portal.c index f212829..7fc78cd 100644 --- a/drivers/bus/fslmc/qbman/qbman_portal.c +++ b/drivers/bus/fslmc/qbman/qbman_portal.c @@ -704,7 +704,7 @@ static struct qb_attr_code code_pull_dct = QB_CODE(0, 0, 2); static struct qb_attr_code code_pull_dt = QB_CODE(0, 2, 2); static struct qb_attr_code code_pull_rls = QB_CODE(0, 4, 1); static struct qb_attr_code code_pull_stash = QB_CODE(0, 5, 1); -static struct qb_attr_code code_pull_numframes = QB_CODE(0, 8, 4); +static struct qb_attr_code code_pull_numframes = QB_CODE(0, 8, 5); static struct qb_attr_code code_pull_token = QB_CODE(0, 16, 8); static struct qb_attr_code code_pull_dqsource = QB_CODE(1, 0, 24); static struct qb_attr_code code_pull_rsp_lo = QB_CODE(2, 0, 32); @@ -743,7 +743,6 @@ void qbman_pull_desc_set_numframes(struct qbman_pull_desc *d, uint8_t numframes) { uint32_t *cl = qb_cl(d); - QBMAN_BUG_ON(!numframes || (numframes > 16)); qb_attr_code_encode(&code_pull_numframes, cl, (uint32_t)(numframes - 1)); } From patchwork Sat Sep 16 10:52:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemant Agrawal X-Patchwork-Id: 112787 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp1614885qgf; Sat, 16 Sep 2017 03:54:09 -0700 (PDT) X-Google-Smtp-Source: AOwi7QAUKn+4NcXTL2/DZgNJhdux5EqHBPAadx8RrAKO8aPOfZV48RZ1wtfAp0Gl/EBXwqQxqWfO X-Received: by 10.28.209.14 with SMTP id i14mr4523788wmg.156.1505559249715; Sat, 16 Sep 2017 03:54:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505559249; cv=none; d=google.com; s=arc-20160816; b=0qAC9u+ChzduqO7AUL+1HGd5C/FA/kWnAVkEUx4hv2MXjXw2hvaaHIS+QhCBaCLQl3 joqq0T4ZV2V/kttxkymFQIrya+Ur+313Tgd5+uWs638T3E2M290mMbceksfVDvW0cPBP SjD7BRZnhVzYnzZNG1fjiOT21FtXWNvRRrD/5KVcWwQrkrt1Dae79mJeGksmLtjlrNMZ QB58DeXV/EpZp94gPE+0tuOC12fVppmBkOPACnjcDpevMjX0B7Fl2Nl9uRXgJfF3DSPI tiq9ttPX/+5qEBoEg4gKk44rQ6bdG1HmrGsEMv2YcKElXV3eOjcpmBot2oLmAbmgmtH/ W0gw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:spamdiagnosticmetadata :spamdiagnosticoutput:mime-version:references:in-reply-to:message-id :date:cc:to:from:arc-authentication-results; bh=NHGgHteCwlDEIUOVi9SnyjM5Z06s7Fs6QP7z4K/1IEk=; b=GEm9zqNtanJ57JG/dPIngpImJNo6mgMld/69aCc5WKx3tznalAv+0DxK8A6pXvkmnx bx/MTX7XImxItyvM7fLy4Yzs3ro7vDb9XmAb+qESpf5d1y6OMhEEUfrw3NvmV0eWtE4W nRjuf34ckkmps4f7TeZwUyiJsb/aF/iz0M5xP7wp3UAzAMQGstSpekcusdXSjPr/0FY5 WZ/fwgzYse0Z3Amjk8S8tj4D0d04nZIASmhTlkhkeQ6eYea/84eo85Cjr7ilw03pBF2G qWcIygsQyphdcLtK8t4dZOeJDIrfhc3Fgr3kGfH1tkJuZbfxqRNT4XSL5Wu0+hXBT8bm O47Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from dpdk.org (dpdk.org. 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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN3PR03MB2354 Subject: [dpdk-dev] [PATCH v3 05/27] bus/fslmc: enhance the QBMAN CENA mode X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Haiying Wang Signed-off-by: Haiying Wang Signed-off-by: Hemant Agrawal --- drivers/bus/fslmc/qbman/qbman_sys.h | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) -- 2.7.4 diff --git a/drivers/bus/fslmc/qbman/qbman_sys.h b/drivers/bus/fslmc/qbman/qbman_sys.h index 9ea55de..47da595 100644 --- a/drivers/bus/fslmc/qbman/qbman_sys.h +++ b/drivers/bus/fslmc/qbman/qbman_sys.h @@ -217,7 +217,6 @@ static inline void qbman_cena_write_complete_wo_shadow(struct qbman_swp_sys *s, #ifdef QBMAN_CENA_TRACE pr_info("qbman_cena_write_complete(%p:%d:0x%03x)\n", s->addr_cena, s->idx, offset); - hexdump(cmd, 64); #endif dcbf(s->addr_cena + offset); } @@ -251,11 +250,7 @@ static inline void *qbman_cena_read_wo_shadow(struct qbman_swp_sys *s, { #ifdef QBMAN_CENA_TRACE pr_info("qbman_cena_read(%p:%d:0x%03x) %p\n", - s->addr_cena, s->idx, offset, shadow); -#endif - -#ifdef QBMAN_CENA_TRACE - hexdump(shadow, 64); + s->addr_cena, s->idx, offset); #endif return s->addr_cena + offset; } From patchwork Sat Sep 16 10:52:20 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemant Agrawal X-Patchwork-Id: 112788 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp1615033qgf; Sat, 16 Sep 2017 03:54:22 -0700 (PDT) X-Google-Smtp-Source: ADKCNb7MdqbiceVspc8NJCw1Y25tHi/2+KTda54bTIHkzoIQYX2aBx+B8cCo6CjbgeZDp78bZbAx X-Received: by 10.223.150.19 with SMTP id b19mr26306411wra.68.1505559261995; Sat, 16 Sep 2017 03:54:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505559261; cv=none; d=google.com; s=arc-20160816; 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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR03MB2701 Subject: [dpdk-dev] [PATCH v3 06/27] bus/fslmc: qbman remove unused funcs and align names X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" name alignment for check command and result functions putting them as separate functions instead of changing the original functions. Signed-off-by: Hemant Agrawal --- drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h | 146 ++-- drivers/bus/fslmc/qbman/qbman_portal.c | 731 ++++++++++----------- drivers/bus/fslmc/qbman/qbman_portal.h | 6 +- drivers/bus/fslmc/qbman/qbman_private.h | 2 +- drivers/bus/fslmc/qbman/qbman_sys.h | 12 - drivers/bus/fslmc/rte_bus_fslmc_version.map | 3 +- drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 4 +- drivers/net/dpaa2/dpaa2_rxtx.c | 10 +- 8 files changed, 449 insertions(+), 465 deletions(-) -- 2.7.4 diff --git a/drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h b/drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h index fe1cc94..24a6d4b 100644 --- a/drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h +++ b/drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h @@ -194,11 +194,38 @@ void qbman_swp_interrupt_set_inhibit(struct qbman_swp *p, int inhibit); /** * struct qbman_result - structure for qbman dequeue response and/or * notification. - * @dont_manipulate_directly: the 16 32bit data to represent the whole + * @donot_manipulate_directly: the 16 32bit data to represent the whole * possible qbman dequeue result. */ struct qbman_result { - uint32_t dont_manipulate_directly[16]; + union { + struct common { + uint8_t verb; + uint8_t reserved[63]; + } common; + struct dq { + uint8_t verb; + uint8_t stat; + __le16 seqnum; + __le16 oprid; + uint8_t reserved; + uint8_t tok; + __le32 fqid; + uint32_t reserved2; + __le32 fq_byte_cnt; + __le32 fq_frm_cnt; + __le64 fqd_ctx; + uint8_t fd[32]; + } dq; + struct scn { + uint8_t verb; + uint8_t stat; + uint8_t state; + uint8_t reserved; + __le32 rid_tok; + __le64 ctx; + } scn; + }; }; /* TODO: @@ -254,11 +281,21 @@ void qbman_swp_push_set(struct qbman_swp *s, uint8_t channel_idx, int enable); /** * struct qbman_pull_desc - the structure for pull dequeue descriptor - * @dont_manipulate_directly: the 6 32bit data to represent the whole - * possible settings for pull dequeue descriptor. */ struct qbman_pull_desc { - uint32_t dont_manipulate_directly[6]; + union { + uint32_t donot_manipulate_directly[16]; + struct pull { + uint8_t verb; + uint8_t numf; + uint8_t tok; + uint8_t reserved; + uint32_t dq_src; + uint64_t rsp_addr; + uint64_t rsp_addr_virt; + uint8_t padding[40]; + } pull; + }; }; enum qbman_pull_type_e { @@ -415,7 +452,20 @@ struct qbman_result *qbman_get_dqrr_from_idx(struct qbman_swp *s, uint8_t idx); * dequeue result. */ int qbman_result_has_new_result(struct qbman_swp *s, - const struct qbman_result *dq); + struct qbman_result *dq); + +/** + * qbman_check_command_complete() - Check if the previous issued dq commnd + * is completed and results are available in memory. + * @s: the software portal object. + * @dq: the dequeue result read from the memory. + * + * Return 1 for getting a valid dequeue result, or 0 for not getting a valid + * dequeue result. + */ +int qbman_check_command_complete(struct qbman_result *dq); + +int qbman_check_new_result(struct qbman_result *dq); /* -------------------------------------------------------- */ /* Parsing dequeue entries (DQRR and user-provided storage) */ @@ -537,7 +587,7 @@ int qbman_result_is_FQPN(const struct qbman_result *dq); * * Return the state field. */ -uint32_t qbman_result_DQ_flags(const struct qbman_result *dq); +uint8_t qbman_result_DQ_flags(const struct qbman_result *dq); /** * qbman_result_DQ_is_pull() - Check whether the dq response is from a pull @@ -648,24 +698,6 @@ uint32_t qbman_result_SCN_rid(const struct qbman_result *scn); */ uint64_t qbman_result_SCN_ctx(const struct qbman_result *scn); -/** - * qbman_result_SCN_state_in_mem() - Get the state in notification written - * in memory - * @scn: the state change notification. - * - * Return the state. - */ -uint8_t qbman_result_SCN_state_in_mem(const struct qbman_result *scn); - -/** - * qbman_result_SCN_rid_in_mem() - Get the resource id in notification written - * in memory. - * @scn: the state change notification. - * - * Return the resource id. - */ -uint32_t qbman_result_SCN_rid_in_mem(const struct qbman_result *scn); - /* Type-specific "resource IDs". Mainly for illustration purposes, though it * also gives the appropriate type widths. */ @@ -746,22 +778,36 @@ uint64_t qbman_result_cgcu_icnt(const struct qbman_result *scn); /* Enqueues */ /************/ -/** - * struct qbman_eq_desc - structure of enqueue descriptor - * @dont_manipulate_directly: the 8 32bit data to represent the whole - * possible qbman enqueue setting in enqueue descriptor. - */ +/* struct qbman_eq_desc - structure of enqueue descriptor */ struct qbman_eq_desc { - uint32_t dont_manipulate_directly[8]; + union { + uint32_t donot_manipulate_directly[8]; + struct eq { + uint8_t verb; + uint8_t dca; + uint16_t seqnum; + uint16_t orpid; + uint16_t reserved1; + uint32_t tgtid; + uint32_t tag; + uint16_t qdbin; + uint8_t qpri; + uint8_t reserved[3]; + uint8_t wae; + uint8_t rspid; + uint64_t rsp_addr; + uint8_t fd[32]; + } eq; + }; }; /** * struct qbman_eq_response - structure of enqueue response - * @dont_manipulate_directly: the 16 32bit data to represent the whole + * @donot_manipulate_directly: the 16 32bit data to represent the whole * enqueue response. */ struct qbman_eq_response { - uint32_t dont_manipulate_directly[16]; + uint32_t donot_manipulate_directly[16]; }; /** @@ -801,7 +847,7 @@ void qbman_eq_desc_set_no_orp(struct qbman_eq_desc *d, int respond_success); * sequeue number. */ void qbman_eq_desc_set_orp(struct qbman_eq_desc *d, int respond_success, - uint32_t opr_id, uint32_t seqnum, int incomplete); + uint16_t opr_id, uint16_t seqnum, int incomplete); /** * qbman_eq_desc_set_orp_hole() - fill a hole in the order-restoration sequence @@ -810,8 +856,8 @@ void qbman_eq_desc_set_orp(struct qbman_eq_desc *d, int respond_success, * @opr_id: the order point record id. * @seqnum: the order restoration sequence number. */ -void qbman_eq_desc_set_orp_hole(struct qbman_eq_desc *d, uint32_t opr_id, - uint32_t seqnum); +void qbman_eq_desc_set_orp_hole(struct qbman_eq_desc *d, uint16_t opr_id, + uint16_t seqnum); /** * qbman_eq_desc_set_orp_nesn() - advance NESN (Next Expected Sequence Number) @@ -820,8 +866,8 @@ void qbman_eq_desc_set_orp_hole(struct qbman_eq_desc *d, uint32_t opr_id, * @opr_id: the order point record id. * @seqnum: the order restoration sequence number. */ -void qbman_eq_desc_set_orp_nesn(struct qbman_eq_desc *d, uint32_t opr_id, - uint32_t seqnum); +void qbman_eq_desc_set_orp_nesn(struct qbman_eq_desc *d, uint16_t opr_id, + uint16_t seqnum); /** * qbman_eq_desc_set_response() - Set the enqueue response info. * @d: the enqueue descriptor @@ -873,7 +919,7 @@ void qbman_eq_desc_set_fq(struct qbman_eq_desc *d, uint32_t fqid); * @qd_prio: the queuing destination priority. */ void qbman_eq_desc_set_qd(struct qbman_eq_desc *d, uint32_t qdid, - uint32_t qd_bin, uint32_t qd_prio); + uint16_t qd_bin, uint8_t qd_prio); /** * qbman_eq_desc_set_eqdi() - enable/disable EQDI interrupt @@ -898,7 +944,7 @@ void qbman_eq_desc_set_eqdi(struct qbman_eq_desc *d, int enable); * being rescheduled.) */ void qbman_eq_desc_set_dca(struct qbman_eq_desc *d, int enable, - uint32_t dqrr_idx, int park); + uint8_t dqrr_idx, int park); /** * qbman_swp_enqueue() - Issue an enqueue command. @@ -957,11 +1003,20 @@ int qbman_swp_enqueue_thresh(struct qbman_swp *s, unsigned int thresh); /*******************/ /** * struct qbman_release_desc - The structure for buffer release descriptor - * @dont_manipulate_directly: the 32bit data to represent the whole + * @donot_manipulate_directly: the 32bit data to represent the whole * possible settings of qbman release descriptor. */ struct qbman_release_desc { - uint32_t dont_manipulate_directly[1]; + union { + uint32_t donot_manipulate_directly[16]; + struct br { + uint8_t verb; + uint8_t reserved; + uint16_t bpid; + uint32_t reserved2; + uint64_t buf[7]; + } br; + }; }; /** @@ -975,7 +1030,7 @@ void qbman_release_desc_clear(struct qbman_release_desc *d); * qbman_release_desc_set_bpid() - Set the ID of the buffer pool to release to * @d: the qbman release descriptor. */ -void qbman_release_desc_set_bpid(struct qbman_release_desc *d, uint32_t bpid); +void qbman_release_desc_set_bpid(struct qbman_release_desc *d, uint16_t bpid); /** * qbman_release_desc_set_rcdi() - Determines whether or not the portal's RCDI @@ -1018,7 +1073,7 @@ int qbman_swp_release_thresh(struct qbman_swp *s, unsigned int thresh); * Return 0 for success, or negative error code if the acquire command * fails. */ -int qbman_swp_acquire(struct qbman_swp *s, uint32_t bpid, uint64_t *buffers, +int qbman_swp_acquire(struct qbman_swp *s, uint16_t bpid, uint64_t *buffers, unsigned int num_buffers); /*****************/ @@ -1133,7 +1188,4 @@ int qbman_swp_CDAN_disable(struct qbman_swp *s, uint16_t channelid); */ int qbman_swp_CDAN_set_context_enable(struct qbman_swp *s, uint16_t channelid, uint64_t ctx); - -int qbman_check_command_complete(struct qbman_swp *s, - const struct qbman_result *dq); #endif /* !_FSL_QBMAN_PORTAL_H */ diff --git a/drivers/bus/fslmc/qbman/qbman_portal.c b/drivers/bus/fslmc/qbman/qbman_portal.c index 7fc78cd..cd903c1 100644 --- a/drivers/bus/fslmc/qbman/qbman_portal.c +++ b/drivers/bus/fslmc/qbman/qbman_portal.c @@ -69,21 +69,23 @@ /* Pre-defined attribute codes */ /*******************************/ -struct qb_attr_code code_generic_verb = QB_CODE(0, 0, 7); -struct qb_attr_code code_generic_rslt = QB_CODE(0, 8, 8); +#define QBMAN_RESPONSE_VERB_MASK 0x7f /*************************/ /* SDQCR attribute codes */ /*************************/ +#define QB_SDQCR_FC_SHIFT 29 +#define QB_SDQCR_FC_MASK 0x1 +#define QB_SDQCR_DCT_SHIFT 24 +#define QB_SDQCR_DCT_MASK 0x3 +#define QB_SDQCR_TOK_SHIFT 16 +#define QB_SDQCR_TOK_MASK 0xff +#define QB_SDQCR_SRC_SHIFT 0 +#define QB_SDQCR_SRC_MASK 0xffff + +/* opaque token for static dequeues */ +#define QMAN_SDQCR_TOKEN 0xbb -/* we put these here because at least some of them are required by - * qbman_swp_init() - */ -struct qb_attr_code code_sdqcr_dct = QB_CODE(0, 24, 2); -struct qb_attr_code code_sdqcr_fc = QB_CODE(0, 29, 1); -struct qb_attr_code code_sdqcr_tok = QB_CODE(0, 16, 8); -static struct qb_attr_code code_eq_dca_idx; -#define CODE_SDQCR_DQSRC(n) QB_CODE(0, n, 1) enum qbman_sdqcr_dct { qbman_sdqcr_dct_null = 0, qbman_sdqcr_dct_prio_ics, @@ -96,13 +98,11 @@ enum qbman_sdqcr_fc { qbman_sdqcr_fc_up_to_3 = 1 }; -struct qb_attr_code code_sdqcr_dqsrc = QB_CODE(0, 0, 16); - /* We need to keep track of which SWP triggered a pull command * so keep an array of portal IDs and use the token field to * be able to find the proper portal */ -#define MAX_QBMAN_PORTALS 35 +#define MAX_QBMAN_PORTALS 64 static struct qbman_swp *portal_idx_map[MAX_QBMAN_PORTALS]; /*********************************/ @@ -136,9 +136,10 @@ struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc *d) #endif p->mc.valid_bit = QB_VALID_BIT; p->sdq = 0; - qb_attr_code_encode(&code_sdqcr_dct, &p->sdq, qbman_sdqcr_dct_prio_ics); - qb_attr_code_encode(&code_sdqcr_fc, &p->sdq, qbman_sdqcr_fc_up_to_3); - qb_attr_code_encode(&code_sdqcr_tok, &p->sdq, 0xbb); + p->sdq |= qbman_sdqcr_dct_prio_ics << QB_SDQCR_DCT_SHIFT; + p->sdq |= qbman_sdqcr_fc_up_to_3 << QB_SDQCR_FC_SHIFT; + p->sdq |= QMAN_SDQCR_TOKEN << QB_SDQCR_TOK_SHIFT; + atomic_set(&p->vdq.busy, 1); p->vdq.valid_bit = QB_VALID_BIT; p->dqrr.next_idx = 0; @@ -147,13 +148,9 @@ struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc *d) if ((qman_version & 0xFFFF0000) < QMAN_REV_4100) { p->dqrr.dqrr_size = 4; p->dqrr.reset_bug = 1; - /* Set size of DQRR to 4, encoded in 2 bits */ - code_eq_dca_idx = (struct qb_attr_code)QB_CODE(0, 8, 2); } else { p->dqrr.dqrr_size = 8; p->dqrr.reset_bug = 0; - /* Set size of DQRR to 8, encoded in 3 bits */ - code_eq_dca_idx = (struct qb_attr_code)QB_CODE(0, 8, 3); } ret = qbman_swp_sys_init(&p->sys, d, p->dqrr.dqrr_size); @@ -165,7 +162,7 @@ struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc *d) /* SDQCR needs to be initialized to 0 when no channels are * being dequeued from or else the QMan HW will indicate an * error. The values that were calculated above will be - * applied when dequeues from a specific channel are enabled + * applied when dequeues from a specific channel are enabled. */ qbman_cinh_write(&p->sys, QBMAN_CINH_SWP_SDQCR, 0); eqcr_pi = qbman_cinh_read(&p->sys, QBMAN_CINH_SWP_EQCR_PI); @@ -280,9 +277,9 @@ void *qbman_swp_mc_start(struct qbman_swp *p) return ret; } -void qbman_swp_mc_submit(struct qbman_swp *p, void *cmd, uint32_t cmd_verb) +void qbman_swp_mc_submit(struct qbman_swp *p, void *cmd, uint8_t cmd_verb) { - uint32_t *v = cmd; + uint8_t *v = cmd; #ifdef QBMAN_CHECKING QBMAN_BUG_ON(!(p->mc.check != swp_mc_can_submit)); #endif @@ -323,35 +320,22 @@ void *qbman_swp_mc_result(struct qbman_swp *p) /* Enqueue */ /***********/ -/* These should be const, eventually */ -static struct qb_attr_code code_eq_cmd = QB_CODE(0, 0, 2); -static struct qb_attr_code code_eq_eqdi = QB_CODE(0, 3, 1); -static struct qb_attr_code code_eq_dca_en = QB_CODE(0, 15, 1); -static struct qb_attr_code code_eq_dca_pk = QB_CODE(0, 14, 1); -/* Can't set code_eq_dca_idx width. Need qman version. Read at runtime */ -static struct qb_attr_code code_eq_orp_en = QB_CODE(0, 2, 1); -static struct qb_attr_code code_eq_orp_is_nesn = QB_CODE(0, 31, 1); -static struct qb_attr_code code_eq_orp_nlis = QB_CODE(0, 30, 1); -static struct qb_attr_code code_eq_orp_seqnum = QB_CODE(0, 16, 14); -static struct qb_attr_code code_eq_opr_id = QB_CODE(1, 0, 16); -static struct qb_attr_code code_eq_tgt_id = QB_CODE(2, 0, 24); -/* static struct qb_attr_code code_eq_tag = QB_CODE(3, 0, 32); */ -static struct qb_attr_code code_eq_qd_en = QB_CODE(0, 4, 1); -static struct qb_attr_code code_eq_qd_bin = QB_CODE(4, 0, 16); -static struct qb_attr_code code_eq_qd_pri = QB_CODE(4, 16, 4); -static struct qb_attr_code code_eq_rsp_stash = QB_CODE(5, 16, 1); -static struct qb_attr_code code_eq_rsp_id = QB_CODE(5, 24, 8); -static struct qb_attr_code code_eq_rsp_lo = QB_CODE(6, 0, 32); - -enum qbman_eq_cmd_e { - /* No enqueue, primarily for plugging ORP gaps for dropped frames */ - qbman_eq_cmd_empty, - /* DMA an enqueue response once complete */ - qbman_eq_cmd_respond, - /* DMA an enqueue response only if the enqueue fails */ - qbman_eq_cmd_respond_reject +#define QB_ENQUEUE_CMD_OPTIONS_SHIFT 0 +enum qb_enqueue_commands { + enqueue_empty = 0, + enqueue_response_always = 1, + enqueue_rejects_to_fq = 2 }; +#define QB_ENQUEUE_CMD_EC_OPTION_MASK 0x3 +#define QB_ENQUEUE_CMD_ORP_ENABLE_SHIFT 2 +#define QB_ENQUEUE_CMD_IRQ_ON_DISPATCH_SHIFT 3 +#define QB_ENQUEUE_CMD_TARGET_TYPE_SHIFT 4 +#define QB_ENQUEUE_CMD_DCA_PK_SHIFT 6 +#define QB_ENQUEUE_CMD_DCA_EN_SHIFT 7 +#define QB_ENQUEUE_CMD_NLIS_SHIFT 14 +#define QB_ENQUEUE_CMD_IS_NESN_SHIFT 15 + void qbman_eq_desc_clear(struct qbman_eq_desc *d) { memset(d, 0, sizeof(*d)); @@ -359,115 +343,110 @@ void qbman_eq_desc_clear(struct qbman_eq_desc *d) void qbman_eq_desc_set_no_orp(struct qbman_eq_desc *d, int respond_success) { - uint32_t *cl = qb_cl(d); - - qb_attr_code_encode(&code_eq_orp_en, cl, 0); - qb_attr_code_encode(&code_eq_cmd, cl, - respond_success ? qbman_eq_cmd_respond : - qbman_eq_cmd_respond_reject); + d->eq.verb &= ~(1 << QB_ENQUEUE_CMD_ORP_ENABLE_SHIFT); + if (respond_success) + d->eq.verb |= enqueue_response_always; + else + d->eq.verb |= enqueue_rejects_to_fq; } void qbman_eq_desc_set_orp(struct qbman_eq_desc *d, int respond_success, - uint32_t opr_id, uint32_t seqnum, int incomplete) + uint16_t opr_id, uint16_t seqnum, int incomplete) { - uint32_t *cl = qb_cl(d); + d->eq.verb |= 1 << QB_ENQUEUE_CMD_ORP_ENABLE_SHIFT; + if (respond_success) + d->eq.verb |= enqueue_response_always; + else + d->eq.verb |= enqueue_rejects_to_fq; - qb_attr_code_encode(&code_eq_orp_en, cl, 1); - qb_attr_code_encode(&code_eq_cmd, cl, - respond_success ? qbman_eq_cmd_respond : - qbman_eq_cmd_respond_reject); - qb_attr_code_encode(&code_eq_opr_id, cl, opr_id); - qb_attr_code_encode(&code_eq_orp_seqnum, cl, seqnum); - qb_attr_code_encode(&code_eq_orp_nlis, cl, !!incomplete); + d->eq.orpid = opr_id; + d->eq.seqnum = seqnum; + if (incomplete) + d->eq.seqnum |= 1 << QB_ENQUEUE_CMD_NLIS_SHIFT; + else + d->eq.seqnum &= ~(1 << QB_ENQUEUE_CMD_NLIS_SHIFT); } -void qbman_eq_desc_set_orp_hole(struct qbman_eq_desc *d, uint32_t opr_id, - uint32_t seqnum) +void qbman_eq_desc_set_orp_hole(struct qbman_eq_desc *d, uint16_t opr_id, + uint16_t seqnum) { - uint32_t *cl = qb_cl(d); - - qb_attr_code_encode(&code_eq_orp_en, cl, 1); - qb_attr_code_encode(&code_eq_cmd, cl, qbman_eq_cmd_empty); - qb_attr_code_encode(&code_eq_opr_id, cl, opr_id); - qb_attr_code_encode(&code_eq_orp_seqnum, cl, seqnum); - qb_attr_code_encode(&code_eq_orp_nlis, cl, 0); - qb_attr_code_encode(&code_eq_orp_is_nesn, cl, 0); + d->eq.verb |= 1 << QB_ENQUEUE_CMD_ORP_ENABLE_SHIFT; + d->eq.verb &= ~QB_ENQUEUE_CMD_EC_OPTION_MASK; + d->eq.orpid = opr_id; + d->eq.seqnum = seqnum; + d->eq.seqnum &= ~(1 << QB_ENQUEUE_CMD_NLIS_SHIFT); + d->eq.seqnum &= ~(1 << QB_ENQUEUE_CMD_IS_NESN_SHIFT); } -void qbman_eq_desc_set_orp_nesn(struct qbman_eq_desc *d, uint32_t opr_id, - uint32_t seqnum) +void qbman_eq_desc_set_orp_nesn(struct qbman_eq_desc *d, uint16_t opr_id, + uint16_t seqnum) { - uint32_t *cl = qb_cl(d); - - qb_attr_code_encode(&code_eq_orp_en, cl, 1); - qb_attr_code_encode(&code_eq_cmd, cl, qbman_eq_cmd_empty); - qb_attr_code_encode(&code_eq_opr_id, cl, opr_id); - qb_attr_code_encode(&code_eq_orp_seqnum, cl, seqnum); - qb_attr_code_encode(&code_eq_orp_nlis, cl, 0); - qb_attr_code_encode(&code_eq_orp_is_nesn, cl, 1); + d->eq.verb |= 1 << QB_ENQUEUE_CMD_ORP_ENABLE_SHIFT; + d->eq.verb &= ~QB_ENQUEUE_CMD_EC_OPTION_MASK; + d->eq.orpid = opr_id; + d->eq.seqnum = seqnum; + d->eq.seqnum &= ~(1 << QB_ENQUEUE_CMD_NLIS_SHIFT); + d->eq.seqnum |= 1 << QB_ENQUEUE_CMD_IS_NESN_SHIFT; } void qbman_eq_desc_set_response(struct qbman_eq_desc *d, dma_addr_t storage_phys, int stash) { - uint32_t *cl = qb_cl(d); - - qb_attr_code_encode_64(&code_eq_rsp_lo, (uint64_t *)cl, storage_phys); - qb_attr_code_encode(&code_eq_rsp_stash, cl, !!stash); + d->eq.rsp_addr = storage_phys; + d->eq.wae = stash; } void qbman_eq_desc_set_token(struct qbman_eq_desc *d, uint8_t token) { - uint32_t *cl = qb_cl(d); - - qb_attr_code_encode(&code_eq_rsp_id, cl, (uint32_t)token); + d->eq.rspid = token; } void qbman_eq_desc_set_fq(struct qbman_eq_desc *d, uint32_t fqid) { - uint32_t *cl = qb_cl(d); - - qb_attr_code_encode(&code_eq_qd_en, cl, 0); - qb_attr_code_encode(&code_eq_tgt_id, cl, fqid); + d->eq.verb &= ~(1 << QB_ENQUEUE_CMD_TARGET_TYPE_SHIFT); + d->eq.tgtid = fqid; } void qbman_eq_desc_set_qd(struct qbman_eq_desc *d, uint32_t qdid, - uint32_t qd_bin, uint32_t qd_prio) + uint16_t qd_bin, uint8_t qd_prio) { - uint32_t *cl = qb_cl(d); - - qb_attr_code_encode(&code_eq_qd_en, cl, 1); - qb_attr_code_encode(&code_eq_tgt_id, cl, qdid); - qb_attr_code_encode(&code_eq_qd_bin, cl, qd_bin); - qb_attr_code_encode(&code_eq_qd_pri, cl, qd_prio); + d->eq.verb |= 1 << QB_ENQUEUE_CMD_TARGET_TYPE_SHIFT; + d->eq.tgtid = qdid; + d->eq.qdbin = qd_bin; + d->eq.qpri = qd_prio; } void qbman_eq_desc_set_eqdi(struct qbman_eq_desc *d, int enable) { - uint32_t *cl = qb_cl(d); - - qb_attr_code_encode(&code_eq_eqdi, cl, !!enable); + if (enable) + d->eq.verb |= 1 << QB_ENQUEUE_CMD_IRQ_ON_DISPATCH_SHIFT; + else + d->eq.verb &= ~(1 << QB_ENQUEUE_CMD_IRQ_ON_DISPATCH_SHIFT); } void qbman_eq_desc_set_dca(struct qbman_eq_desc *d, int enable, - uint32_t dqrr_idx, int park) + uint8_t dqrr_idx, int park) { - uint32_t *cl = qb_cl(d); - - qb_attr_code_encode(&code_eq_dca_en, cl, !!enable); if (enable) { - qb_attr_code_encode(&code_eq_dca_pk, cl, !!park); - qb_attr_code_encode(&code_eq_dca_idx, cl, dqrr_idx); + d->eq.dca = dqrr_idx; + if (park) + d->eq.dca |= 1 << QB_ENQUEUE_CMD_DCA_PK_SHIFT; + else + d->eq.dca &= ~(1 << QB_ENQUEUE_CMD_DCA_PK_SHIFT); + d->eq.dca |= 1 << QB_ENQUEUE_CMD_DCA_EN_SHIFT; + } else { + d->eq.dca &= ~(1 << QB_ENQUEUE_CMD_DCA_EN_SHIFT); } } #define EQAR_IDX(eqar) ((eqar) & 0x7) #define EQAR_VB(eqar) ((eqar) & 0x80) #define EQAR_SUCCESS(eqar) ((eqar) & 0x100) + static int qbman_swp_enqueue_array_mode(struct qbman_swp *s, const struct qbman_eq_desc *d, - const struct qbman_fd *fd) + const struct qbman_fd *fd) { uint32_t *p; const uint32_t *cl = qb_cl(d); @@ -477,20 +456,20 @@ static int qbman_swp_enqueue_array_mode(struct qbman_swp *s, if (!EQAR_SUCCESS(eqar)) return -EBUSY; p = qbman_cena_write_start_wo_shadow(&s->sys, - QBMAN_CENA_SWP_EQCR(EQAR_IDX(eqar))); + QBMAN_CENA_SWP_EQCR(EQAR_IDX(eqar))); memcpy(&p[1], &cl[1], 28); memcpy(&p[8], fd, sizeof(*fd)); /* Set the verb byte, have to substitute in the valid-bit */ lwsync(); p[0] = cl[0] | EQAR_VB(eqar); qbman_cena_write_complete_wo_shadow(&s->sys, - QBMAN_CENA_SWP_EQCR(EQAR_IDX(eqar))); + QBMAN_CENA_SWP_EQCR(EQAR_IDX(eqar))); return 0; } static int qbman_swp_enqueue_ring_mode(struct qbman_swp *s, const struct qbman_eq_desc *d, - const struct qbman_fd *fd) + const struct qbman_fd *fd) { uint32_t *p; const uint32_t *cl = qb_cl(d); @@ -509,19 +488,21 @@ static int qbman_swp_enqueue_ring_mode(struct qbman_swp *s, } p = qbman_cena_write_start_wo_shadow(&s->sys, - QBMAN_CENA_SWP_EQCR(s->eqcr.pi & 7)); + QBMAN_CENA_SWP_EQCR(s->eqcr.pi & 7)); memcpy(&p[1], &cl[1], 28); memcpy(&p[8], fd, sizeof(*fd)); lwsync(); + /* Set the verb byte, have to substitute in the valid-bit */ p[0] = cl[0] | s->eqcr.pi_vb; qbman_cena_write_complete_wo_shadow(&s->sys, - QBMAN_CENA_SWP_EQCR(s->eqcr.pi & 7)); + QBMAN_CENA_SWP_EQCR(s->eqcr.pi & 7)); s->eqcr.pi++; s->eqcr.pi &= 0xF; s->eqcr.available--; if (!(s->eqcr.pi & 7)) s->eqcr.pi_vb ^= QB_VALID_BIT; + return 0; } @@ -672,23 +653,26 @@ int qbman_swp_enqueue_multiple_desc(struct qbman_swp *s, void qbman_swp_push_get(struct qbman_swp *s, uint8_t channel_idx, int *enabled) { - struct qb_attr_code code = CODE_SDQCR_DQSRC(channel_idx); + uint16_t src = (s->sdq >> QB_SDQCR_SRC_SHIFT) & QB_SDQCR_SRC_MASK; QBMAN_BUG_ON(channel_idx > 15); - *enabled = (int)qb_attr_code_decode(&code, &s->sdq); + *enabled = src | (1 << channel_idx); } void qbman_swp_push_set(struct qbman_swp *s, uint8_t channel_idx, int enable) { uint16_t dqsrc; - struct qb_attr_code code = CODE_SDQCR_DQSRC(channel_idx); QBMAN_BUG_ON(channel_idx > 15); - qb_attr_code_encode(&code, &s->sdq, !!enable); + if (enable) + s->sdq |= 1 << channel_idx; + else + s->sdq &= ~(1 << channel_idx); + /* Read make the complete src map. If no channels are enabled * the SDQCR must be 0 or else QMan will assert errors */ - dqsrc = (uint16_t)qb_attr_code_decode(&code_sdqcr_dqsrc, &s->sdq); + dqsrc = (s->sdq >> QB_SDQCR_SRC_SHIFT) & QB_SDQCR_SRC_MASK; if (dqsrc != 0) qbman_cinh_write(&s->sys, QBMAN_CINH_SWP_SDQCR, s->sdq); else @@ -700,14 +684,10 @@ void qbman_swp_push_set(struct qbman_swp *s, uint8_t channel_idx, int enable) /***************************/ /* These should be const, eventually */ -static struct qb_attr_code code_pull_dct = QB_CODE(0, 0, 2); -static struct qb_attr_code code_pull_dt = QB_CODE(0, 2, 2); -static struct qb_attr_code code_pull_rls = QB_CODE(0, 4, 1); -static struct qb_attr_code code_pull_stash = QB_CODE(0, 5, 1); -static struct qb_attr_code code_pull_numframes = QB_CODE(0, 8, 5); -static struct qb_attr_code code_pull_token = QB_CODE(0, 16, 8); -static struct qb_attr_code code_pull_dqsource = QB_CODE(1, 0, 24); -static struct qb_attr_code code_pull_rsp_lo = QB_CODE(2, 0, 32); +#define QB_VDQCR_VERB_DCT_SHIFT 0 +#define QB_VDQCR_VERB_DT_SHIFT 2 +#define QB_VDQCR_VERB_RLS_SHIFT 4 +#define QB_VDQCR_VERB_WAE_SHIFT 5 enum qb_pull_dt_e { qb_pull_dt_channel, @@ -725,62 +705,52 @@ void qbman_pull_desc_set_storage(struct qbman_pull_desc *d, dma_addr_t storage_phys, int stash) { - uint32_t *cl = qb_cl(d); - /* Squiggle the pointer 'storage' into the extra 2 words of the - * descriptor (which aren't copied to the hw command) - */ - *(void **)&cl[4] = storage; + d->pull.rsp_addr_virt = (uint64_t)storage; + if (!storage) { - qb_attr_code_encode(&code_pull_rls, cl, 0); + d->pull.verb &= ~(1 << QB_VDQCR_VERB_RLS_SHIFT); return; } - qb_attr_code_encode(&code_pull_rls, cl, 1); - qb_attr_code_encode(&code_pull_stash, cl, !!stash); - qb_attr_code_encode_64(&code_pull_rsp_lo, (uint64_t *)cl, storage_phys); + d->pull.verb |= 1 << QB_VDQCR_VERB_RLS_SHIFT; + if (stash) + d->pull.verb |= 1 << QB_VDQCR_VERB_WAE_SHIFT; + else + d->pull.verb &= ~(1 << QB_VDQCR_VERB_WAE_SHIFT); + + d->pull.rsp_addr = storage_phys; } void qbman_pull_desc_set_numframes(struct qbman_pull_desc *d, uint8_t numframes) { - uint32_t *cl = qb_cl(d); - - qb_attr_code_encode(&code_pull_numframes, cl, - (uint32_t)(numframes - 1)); + d->pull.numf = numframes - 1; } void qbman_pull_desc_set_token(struct qbman_pull_desc *d, uint8_t token) { - uint32_t *cl = qb_cl(d); - - qb_attr_code_encode(&code_pull_token, cl, token); + d->pull.tok = token; } void qbman_pull_desc_set_fq(struct qbman_pull_desc *d, uint32_t fqid) { - uint32_t *cl = qb_cl(d); - - qb_attr_code_encode(&code_pull_dct, cl, 1); - qb_attr_code_encode(&code_pull_dt, cl, qb_pull_dt_framequeue); - qb_attr_code_encode(&code_pull_dqsource, cl, fqid); + d->pull.verb |= 1 << QB_VDQCR_VERB_DCT_SHIFT; + d->pull.verb |= qb_pull_dt_framequeue << QB_VDQCR_VERB_DT_SHIFT; + d->pull.dq_src = fqid; } void qbman_pull_desc_set_wq(struct qbman_pull_desc *d, uint32_t wqid, enum qbman_pull_type_e dct) { - uint32_t *cl = qb_cl(d); - - qb_attr_code_encode(&code_pull_dct, cl, dct); - qb_attr_code_encode(&code_pull_dt, cl, qb_pull_dt_workqueue); - qb_attr_code_encode(&code_pull_dqsource, cl, wqid); + d->pull.verb |= dct << QB_VDQCR_VERB_DCT_SHIFT; + d->pull.verb |= qb_pull_dt_workqueue << QB_VDQCR_VERB_DT_SHIFT; + d->pull.dq_src = wqid; } void qbman_pull_desc_set_channel(struct qbman_pull_desc *d, uint32_t chid, enum qbman_pull_type_e dct) { - uint32_t *cl = qb_cl(d); - - qb_attr_code_encode(&code_pull_dct, cl, dct); - qb_attr_code_encode(&code_pull_dt, cl, qb_pull_dt_channel); - qb_attr_code_encode(&code_pull_dqsource, cl, chid); + d->pull.verb |= dct << QB_VDQCR_VERB_DCT_SHIFT; + d->pull.verb |= qb_pull_dt_channel << QB_VDQCR_VERB_DT_SHIFT; + d->pull.dq_src = chid; } int qbman_swp_pull(struct qbman_swp *s, struct qbman_pull_desc *d) @@ -792,18 +762,18 @@ int qbman_swp_pull(struct qbman_swp *s, struct qbman_pull_desc *d) atomic_inc(&s->vdq.busy); return -EBUSY; } - s->vdq.storage = *(void **)&cl[4]; - /* We use portal index +1 as token so that 0 still indicates - * that the result isn't valid yet. - */ - qb_attr_code_encode(&code_pull_token, cl, s->desc.idx + 1); + + d->pull.tok = s->sys.idx + 1; + s->vdq.storage = (void *)d->pull.rsp_addr_virt; p = qbman_cena_write_start_wo_shadow(&s->sys, QBMAN_CENA_SWP_VDQCR); memcpy(&p[1], &cl[1], 12); + /* Set the verb byte, have to substitute in the valid-bit */ lwsync(); p[0] = cl[0] | s->vdq.valid_bit; s->vdq.valid_bit ^= QB_VALID_BIT; qbman_cena_write_complete_wo_shadow(&s->sys, QBMAN_CENA_SWP_VDQCR); + return 0; } @@ -811,16 +781,7 @@ int qbman_swp_pull(struct qbman_swp *s, struct qbman_pull_desc *d) /* Polling DQRR */ /****************/ -static struct qb_attr_code code_dqrr_verb = QB_CODE(0, 0, 8); -static struct qb_attr_code code_dqrr_response = QB_CODE(0, 0, 7); -static struct qb_attr_code code_dqrr_stat = QB_CODE(0, 8, 8); -static struct qb_attr_code code_dqrr_seqnum = QB_CODE(0, 16, 14); -static struct qb_attr_code code_dqrr_odpid = QB_CODE(1, 0, 16); -/* static struct qb_attr_code code_dqrr_tok = QB_CODE(1, 24, 8); */ -static struct qb_attr_code code_dqrr_fqid = QB_CODE(2, 0, 24); -static struct qb_attr_code code_dqrr_byte_count = QB_CODE(4, 0, 32); -static struct qb_attr_code code_dqrr_frame_count = QB_CODE(5, 0, 24); -static struct qb_attr_code code_dqrr_ctx_lo = QB_CODE(6, 0, 32); +#define QMAN_DQRR_PI_MASK 0xf #define QBMAN_RESULT_DQ 0x60 #define QBMAN_RESULT_FQRN 0x21 @@ -833,8 +794,6 @@ static struct qb_attr_code code_dqrr_ctx_lo = QB_CODE(6, 0, 32); #define QBMAN_RESULT_BPSCN 0x29 #define QBMAN_RESULT_CSCN_WQ 0x2a -static struct qb_attr_code code_dqpi_pi = QB_CODE(0, 0, 4); - /* NULL return if there are no unconsumed DQRR entries. Returns a DQRR entry * only once, so repeated calls can return a sequence of DQRR entries, without * requiring they be consumed immediately or in any particular order. @@ -844,8 +803,7 @@ const struct qbman_result *qbman_swp_dqrr_next(struct qbman_swp *s) uint32_t verb; uint32_t response_verb; uint32_t flags; - const struct qbman_result *dq; - const uint32_t *p; + const struct qbman_result *p; /* Before using valid-bit to detect if something is there, we have to * handle the case of the DQRR reset bug... @@ -858,11 +816,13 @@ const struct qbman_result *qbman_swp_dqrr_next(struct qbman_swp *s) * will be much less efficient than all subsequent trips around * it... */ - uint32_t dqpi = qbman_cinh_read(&s->sys, QBMAN_CINH_SWP_DQPI); - uint32_t pi = qb_attr_code_decode(&code_dqpi_pi, &dqpi); + uint8_t pi = qbman_cinh_read(&s->sys, QBMAN_CINH_SWP_DQPI) & + QMAN_DQRR_PI_MASK; + /* there are new entries if pi != next_idx */ if (pi == s->dqrr.next_idx) return NULL; + /* if next_idx is/was the last ring index, and 'pi' is * different, we can disable the workaround as all the ring * entries have now been DMA'd to so valid-bit checking is @@ -877,12 +837,12 @@ const struct qbman_result *qbman_swp_dqrr_next(struct qbman_swp *s) s->dqrr.reset_bug = 0; } qbman_cena_invalidate_prefetch(&s->sys, - QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx)); + QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx)); } - dq = qbman_cena_read_wo_shadow(&s->sys, - QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx)); - p = qb_cl(dq); - verb = qb_attr_code_decode(&code_dqrr_verb, p); + p = qbman_cena_read_wo_shadow(&s->sys, + QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx)); + verb = p->dq.verb; + /* If the valid-bit isn't of the expected polarity, nothing there. Note, * in the DQRR reset bug workaround, we shouldn't need to skip these * check, because we've already determined that a new entry is available @@ -902,16 +862,16 @@ const struct qbman_result *qbman_swp_dqrr_next(struct qbman_swp *s) s->dqrr.valid_bit ^= QB_VALID_BIT; } /* If this is the final response to a volatile dequeue command - * indicate that the vdq is no longer busy. + * indicate that the vdq is no longer busy */ - flags = qbman_result_DQ_flags(dq); - response_verb = qb_attr_code_decode(&code_dqrr_response, &verb); + flags = p->dq.stat; + response_verb = verb & QBMAN_RESPONSE_VERB_MASK; if ((response_verb == QBMAN_RESULT_DQ) && (flags & QBMAN_DQ_STAT_VOLATILE) && (flags & QBMAN_DQ_STAT_EXPIRED)) atomic_inc(&s->vdq.busy); - return dq; + return p; } /* Consume DQRR entries previously returned from qbman_swp_dqrr_next(). */ @@ -924,80 +884,69 @@ void qbman_swp_dqrr_consume(struct qbman_swp *s, /*********************************/ /* Polling user-provided storage */ /*********************************/ - -int qbman_result_has_new_result(__attribute__((unused)) struct qbman_swp *s, - const struct qbman_result *dq) +int qbman_result_has_new_result(struct qbman_swp *s, + struct qbman_result *dq) { - /* To avoid converting the little-endian DQ entry to host-endian prior - * to us knowing whether there is a valid entry or not (and run the - * risk of corrupting the incoming hardware LE write), we detect in - * hardware endianness rather than host. This means we need a different - * "code" depending on whether we are BE or LE in software, which is - * where DQRR_TOK_OFFSET comes in... + if (dq->dq.tok == 0) + return 0; + + /* + * Set token to be 0 so we will detect change back to 1 + * next time the looping is traversed. Const is cast away here + * as we want users to treat the dequeue responses as read only. */ - static struct qb_attr_code code_dqrr_tok_detect = - QB_CODE(0, DQRR_TOK_OFFSET, 8); - /* The user trying to poll for a result treats "dq" as const. It is - * however the same address that was provided to us non-const in the - * first place, for directing hardware DMA to. So we can cast away the - * const because it is mutable from our perspective. + ((struct qbman_result *)dq)->dq.tok = 0; + + /* + * VDQCR "no longer busy" hook - not quite the same as DQRR, because the + * fact "VDQCR" shows busy doesn't mean that we hold the result that + * makes it available. Eg. we may be looking at our 10th dequeue result, + * having released VDQCR after the 1st result and it is now busy due to + * some other command! */ - uint32_t *p = (uint32_t *)(unsigned long)qb_cl(dq); - uint32_t token; + if (s->vdq.storage == dq) { + s->vdq.storage = NULL; + atomic_inc(&s->vdq.busy); + } + + return 1; +} - token = qb_attr_code_decode(&code_dqrr_tok_detect, &p[1]); - if (token == 0) +int qbman_check_new_result(struct qbman_result *dq) +{ + if (dq->dq.tok == 0) return 0; - /* Entry is valid - overwrite token back to 0 so - * a) If this memory is reused tokesn will be 0 - * b) If someone calls "has_new_result()" again on this entry it - * will not appear to be new - */ - qb_attr_code_encode(&code_dqrr_tok_detect, &p[1], 0); - /* Only now do we convert from hardware to host endianness. Also, as we - * are returning success, the user has promised not to call us again, so - * there's no risk of us converting the endianness twice... + /* + * Set token to be 0 so we will detect change back to 1 + * next time the looping is traversed. Const is cast away here + * as we want users to treat the dequeue responses as read only. */ - make_le32_n(p, 16); + ((struct qbman_result *)dq)->dq.tok = 0; + return 1; } -int qbman_check_command_complete(struct qbman_swp *s, - const struct qbman_result *dq) +int qbman_check_command_complete(struct qbman_result *dq) { - /* To avoid converting the little-endian DQ entry to host-endian prior - * to us knowing whether there is a valid entry or not (and run the - * risk of corrupting the incoming hardware LE write), we detect in - * hardware endianness rather than host. This means we need a different - * "code" depending on whether we are BE or LE in software, which is - * where DQRR_TOK_OFFSET comes in... - */ - static struct qb_attr_code code_dqrr_tok_detect = - QB_CODE(0, DQRR_TOK_OFFSET, 8); - /* The user trying to poll for a result treats "dq" as const. It is - * however the same address that was provided to us non-const in the - * first place, for directing hardware DMA to. So we can cast away the - * const because it is mutable from our perspective. - */ - uint32_t *p = (uint32_t *)(unsigned long)qb_cl(dq); - uint32_t token; + struct qbman_swp *s; - token = qb_attr_code_decode(&code_dqrr_tok_detect, &p[1]); - if (token == 0) + if (dq->dq.tok == 0) return 0; - /* TODO: Remove qbman_swp from parameters and make it a local - * once we've tested the reserve portal map change - */ - s = portal_idx_map[token - 1]; - /* When token is set it indicates that VDQ command has been fetched - * by qbman and is working on it. It is safe for software to issue - * another VDQ command, so incrementing the busy variable. + + s = portal_idx_map[dq->dq.tok - 1]; + /* + * VDQCR "no longer busy" hook - not quite the same as DQRR, because the + * fact "VDQCR" shows busy doesn't mean that we hold the result that + * makes it available. Eg. we may be looking at our 10th dequeue result, + * having released VDQCR after the 1st result and it is now busy due to + * some other command! */ if (s->vdq.storage == dq) { s->vdq.storage = NULL; atomic_inc(&s->vdq.busy); } + return 1; } @@ -1005,23 +954,10 @@ int qbman_check_command_complete(struct qbman_swp *s, /* Categorising qbman results */ /********************************/ -static struct qb_attr_code code_result_in_mem = - QB_CODE(0, QBMAN_RESULT_VERB_OFFSET_IN_MEM, 7); - static inline int __qbman_result_is_x(const struct qbman_result *dq, - uint32_t x) -{ - const uint32_t *p = qb_cl(dq); - uint32_t response_verb = qb_attr_code_decode(&code_dqrr_response, p); - - return (response_verb == x); -} - -static inline int __qbman_result_is_x_in_mem(const struct qbman_result *dq, - uint32_t x) + uint8_t x) { - const uint32_t *p = qb_cl(dq); - uint32_t response_verb = qb_attr_code_decode(&code_result_in_mem, p); + uint8_t response_verb = dq->dq.verb & QBMAN_RESPONSE_VERB_MASK; return (response_verb == x); } @@ -1043,28 +979,28 @@ int qbman_result_is_CDAN(const struct qbman_result *dq) int qbman_result_is_CSCN(const struct qbman_result *dq) { - return __qbman_result_is_x_in_mem(dq, QBMAN_RESULT_CSCN_MEM) || + return __qbman_result_is_x(dq, QBMAN_RESULT_CSCN_MEM) || __qbman_result_is_x(dq, QBMAN_RESULT_CSCN_WQ); } int qbman_result_is_BPSCN(const struct qbman_result *dq) { - return __qbman_result_is_x_in_mem(dq, QBMAN_RESULT_BPSCN); + return __qbman_result_is_x(dq, QBMAN_RESULT_BPSCN); } int qbman_result_is_CGCU(const struct qbman_result *dq) { - return __qbman_result_is_x_in_mem(dq, QBMAN_RESULT_CGCU); + return __qbman_result_is_x(dq, QBMAN_RESULT_CGCU); } int qbman_result_is_FQRN(const struct qbman_result *dq) { - return __qbman_result_is_x_in_mem(dq, QBMAN_RESULT_FQRN); + return __qbman_result_is_x(dq, QBMAN_RESULT_FQRN); } int qbman_result_is_FQRNI(const struct qbman_result *dq) { - return __qbman_result_is_x_in_mem(dq, QBMAN_RESULT_FQRNI); + return __qbman_result_is_x(dq, QBMAN_RESULT_FQRNI); } int qbman_result_is_FQPN(const struct qbman_result *dq) @@ -1078,109 +1014,62 @@ int qbman_result_is_FQPN(const struct qbman_result *dq) /* These APIs assume qbman_result_is_DQ() is TRUE */ -uint32_t qbman_result_DQ_flags(const struct qbman_result *dq) +uint8_t qbman_result_DQ_flags(const struct qbman_result *dq) { - const uint32_t *p = qb_cl(dq); - - return qb_attr_code_decode(&code_dqrr_stat, p); + return dq->dq.stat; } uint16_t qbman_result_DQ_seqnum(const struct qbman_result *dq) { - const uint32_t *p = qb_cl(dq); - - return (uint16_t)qb_attr_code_decode(&code_dqrr_seqnum, p); + return dq->dq.seqnum; } uint16_t qbman_result_DQ_odpid(const struct qbman_result *dq) { - const uint32_t *p = qb_cl(dq); - - return (uint16_t)qb_attr_code_decode(&code_dqrr_odpid, p); + return dq->dq.oprid; } uint32_t qbman_result_DQ_fqid(const struct qbman_result *dq) { - const uint32_t *p = qb_cl(dq); - - return qb_attr_code_decode(&code_dqrr_fqid, p); + return dq->dq.fqid; } uint32_t qbman_result_DQ_byte_count(const struct qbman_result *dq) { - const uint32_t *p = qb_cl(dq); - - return qb_attr_code_decode(&code_dqrr_byte_count, p); + return dq->dq.fq_byte_cnt; } uint32_t qbman_result_DQ_frame_count(const struct qbman_result *dq) { - const uint32_t *p = qb_cl(dq); - - return qb_attr_code_decode(&code_dqrr_frame_count, p); + return dq->dq.fq_frm_cnt; } uint64_t qbman_result_DQ_fqd_ctx(const struct qbman_result *dq) { - const uint64_t *p = (const uint64_t *)qb_cl(dq); - - return qb_attr_code_decode_64(&code_dqrr_ctx_lo, p); + return dq->dq.fqd_ctx; } const struct qbman_fd *qbman_result_DQ_fd(const struct qbman_result *dq) { - const uint32_t *p = qb_cl(dq); - - return (const struct qbman_fd *)&p[8]; + return (const struct qbman_fd *)&dq->dq.fd[0]; } /**************************************/ /* Parsing state-change notifications */ /**************************************/ - -static struct qb_attr_code code_scn_state = QB_CODE(0, 16, 8); -static struct qb_attr_code code_scn_rid = QB_CODE(1, 0, 24); -static struct qb_attr_code code_scn_state_in_mem = - QB_CODE(0, SCN_STATE_OFFSET_IN_MEM, 8); -static struct qb_attr_code code_scn_rid_in_mem = - QB_CODE(1, SCN_RID_OFFSET_IN_MEM, 24); -static struct qb_attr_code code_scn_ctx_lo = QB_CODE(2, 0, 32); - uint8_t qbman_result_SCN_state(const struct qbman_result *scn) { - const uint32_t *p = qb_cl(scn); - - return (uint8_t)qb_attr_code_decode(&code_scn_state, p); + return scn->scn.state; } uint32_t qbman_result_SCN_rid(const struct qbman_result *scn) { - const uint32_t *p = qb_cl(scn); - - return qb_attr_code_decode(&code_scn_rid, p); + return scn->scn.rid_tok; } uint64_t qbman_result_SCN_ctx(const struct qbman_result *scn) { - const uint64_t *p = (const uint64_t *)qb_cl(scn); - - return qb_attr_code_decode_64(&code_scn_ctx_lo, p); -} - -uint8_t qbman_result_SCN_state_in_mem(const struct qbman_result *scn) -{ - const uint32_t *p = qb_cl(scn); - - return (uint8_t)qb_attr_code_decode(&code_scn_state_in_mem, p); -} - -uint32_t qbman_result_SCN_rid_in_mem(const struct qbman_result *scn) -{ - const uint32_t *p = qb_cl(scn); - uint32_t result_rid; - - result_rid = qb_attr_code_decode(&code_scn_rid_in_mem, p); - return make_le24(result_rid); + return scn->scn.ctx; } /*****************/ @@ -1188,22 +1077,22 @@ uint32_t qbman_result_SCN_rid_in_mem(const struct qbman_result *scn) /*****************/ uint16_t qbman_result_bpscn_bpid(const struct qbman_result *scn) { - return (uint16_t)qbman_result_SCN_rid_in_mem(scn) & 0x3FFF; + return (uint16_t)qbman_result_SCN_rid(scn) & 0x3FFF; } int qbman_result_bpscn_has_free_bufs(const struct qbman_result *scn) { - return !(int)(qbman_result_SCN_state_in_mem(scn) & 0x1); + return !(int)(qbman_result_SCN_state(scn) & 0x1); } int qbman_result_bpscn_is_depleted(const struct qbman_result *scn) { - return (int)(qbman_result_SCN_state_in_mem(scn) & 0x2); + return (int)(qbman_result_SCN_state(scn) & 0x2); } int qbman_result_bpscn_is_surplus(const struct qbman_result *scn) { - return (int)(qbman_result_SCN_state_in_mem(scn) & 0x4); + return (int)(qbman_result_SCN_state(scn) & 0x4); } uint64_t qbman_result_bpscn_ctx(const struct qbman_result *scn) @@ -1214,6 +1103,7 @@ uint64_t qbman_result_bpscn_ctx(const struct qbman_result *scn) ctx = qbman_result_SCN_ctx(scn); ctx_hi = upper32(ctx); ctx_lo = lower32(ctx); + return ((uint64_t)make_le32(ctx_hi) << 32 | (uint64_t)make_le32(ctx_lo)); } @@ -1223,7 +1113,7 @@ uint64_t qbman_result_bpscn_ctx(const struct qbman_result *scn) /*****************/ uint16_t qbman_result_cgcu_cgid(const struct qbman_result *scn) { - return (uint16_t)qbman_result_SCN_rid_in_mem(scn) & 0xFFFF; + return (uint16_t)qbman_result_SCN_rid(scn) & 0xFFFF; } uint64_t qbman_result_cgcu_icnt(const struct qbman_result *scn) @@ -1234,6 +1124,7 @@ uint64_t qbman_result_cgcu_icnt(const struct qbman_result *scn) ctx = qbman_result_SCN_ctx(scn); ctx_hi = upper32(ctx); ctx_lo = lower32(ctx); + return ((uint64_t)(make_le32(ctx_hi) & 0xFF) << 32) | (uint64_t)make_le32(ctx_lo); } @@ -1241,34 +1132,26 @@ uint64_t qbman_result_cgcu_icnt(const struct qbman_result *scn) /******************/ /* Buffer release */ /******************/ - -/* These should be const, eventually */ -/* static struct qb_attr_code code_release_num = QB_CODE(0, 0, 3); */ -static struct qb_attr_code code_release_set_me = QB_CODE(0, 5, 1); -static struct qb_attr_code code_release_rcdi = QB_CODE(0, 6, 1); -static struct qb_attr_code code_release_bpid = QB_CODE(0, 16, 16); +#define QB_BR_RC_VALID_SHIFT 5 +#define QB_BR_RCDI_SHIFT 6 void qbman_release_desc_clear(struct qbman_release_desc *d) { - uint32_t *cl; - memset(d, 0, sizeof(*d)); - cl = qb_cl(d); - qb_attr_code_encode(&code_release_set_me, cl, 1); + d->br.verb = 1 << QB_BR_RC_VALID_SHIFT; } -void qbman_release_desc_set_bpid(struct qbman_release_desc *d, uint32_t bpid) +void qbman_release_desc_set_bpid(struct qbman_release_desc *d, uint16_t bpid) { - uint32_t *cl = qb_cl(d); - - qb_attr_code_encode(&code_release_bpid, cl, bpid); + d->br.bpid = bpid; } void qbman_release_desc_set_rcdi(struct qbman_release_desc *d, int enable) { - uint32_t *cl = qb_cl(d); - - qb_attr_code_encode(&code_release_rcdi, cl, !!enable); + if (enable) + d->br.verb |= 1 << QB_BR_RCDI_SHIFT; + else + d->br.verb &= ~(1 << QB_BR_RCDI_SHIFT); } #define RAR_IDX(rar) ((rar) & 0x7) @@ -1285,12 +1168,16 @@ int qbman_swp_release(struct qbman_swp *s, const struct qbman_release_desc *d, pr_debug("RAR=%08x\n", rar); if (!RAR_SUCCESS(rar)) return -EBUSY; + QBMAN_BUG_ON(!num_buffers || (num_buffers > 7)); + /* Start the release command */ p = qbman_cena_write_start_wo_shadow(&s->sys, QBMAN_CENA_SWP_RCR(RAR_IDX(rar))); + /* Copy the caller's buffer pointers to the command */ u64_to_le32_copy(&p[2], buffers, num_buffers); + /* Set the verb byte, have to substitute in the valid-bit and the number * of buffers. */ @@ -1298,25 +1185,38 @@ int qbman_swp_release(struct qbman_swp *s, const struct qbman_release_desc *d, p[0] = cl[0] | RAR_VB(rar) | num_buffers; qbman_cena_write_complete_wo_shadow(&s->sys, QBMAN_CENA_SWP_RCR(RAR_IDX(rar))); + return 0; } /*******************/ /* Buffer acquires */ /*******************/ +struct qbman_acquire_desc { + uint8_t verb; + uint8_t reserved; + uint16_t bpid; + uint8_t num; + uint8_t reserved2[59]; +}; -/* These should be const, eventually */ -static struct qb_attr_code code_acquire_bpid = QB_CODE(0, 16, 16); -static struct qb_attr_code code_acquire_num = QB_CODE(1, 0, 3); -static struct qb_attr_code code_acquire_r_num = QB_CODE(1, 0, 3); +struct qbman_acquire_rslt { + uint8_t verb; + uint8_t rslt; + uint16_t reserved; + uint8_t num; + uint8_t reserved2[3]; + uint64_t buf[7]; +}; -int qbman_swp_acquire(struct qbman_swp *s, uint32_t bpid, uint64_t *buffers, +int qbman_swp_acquire(struct qbman_swp *s, uint16_t bpid, uint64_t *buffers, unsigned int num_buffers) { - uint32_t *p; - uint32_t rslt, num; + struct qbman_acquire_desc *p; + struct qbman_acquire_rslt *r; - QBMAN_BUG_ON(!num_buffers || (num_buffers > 7)); + if (!num_buffers || (num_buffers > 7)) + return -EINVAL; /* Start the management command */ p = qbman_swp_mc_start(s); @@ -1325,59 +1225,81 @@ int qbman_swp_acquire(struct qbman_swp *s, uint32_t bpid, uint64_t *buffers, return -EBUSY; /* Encode the caller-provided attributes */ - qb_attr_code_encode(&code_acquire_bpid, p, bpid); - qb_attr_code_encode(&code_acquire_num, p, num_buffers); + p->bpid = bpid; + p->num = num_buffers; /* Complete the management command */ - p = qbman_swp_mc_complete(s, p, p[0] | QBMAN_MC_ACQUIRE); + r = qbman_swp_mc_complete(s, p, QBMAN_MC_ACQUIRE); + if (unlikely(!r)) { + pr_err("qbman: acquire from BPID %d failed, no response\n", + bpid); + return -EIO; + } /* Decode the outcome */ - rslt = qb_attr_code_decode(&code_generic_rslt, p); - num = qb_attr_code_decode(&code_acquire_r_num, p); - QBMAN_BUG_ON(qb_attr_code_decode(&code_generic_verb, p) != - QBMAN_MC_ACQUIRE); + QBMAN_BUG_ON((r->verb & QBMAN_RESPONSE_VERB_MASK) != QBMAN_MC_ACQUIRE); /* Determine success or failure */ - if (unlikely(rslt != QBMAN_MC_RSLT_OK)) { + if (unlikely(r->rslt != QBMAN_MC_RSLT_OK)) { pr_err("Acquire buffers from BPID 0x%x failed, code=0x%02x\n", - bpid, rslt); + bpid, r->rslt); return -EIO; } - QBMAN_BUG_ON(num > num_buffers); + + QBMAN_BUG_ON(r->num > num_buffers); + /* Copy the acquired buffers to the caller's array */ - u64_from_le32_copy(buffers, &p[2], num); - return (int)num; + u64_from_le32_copy(buffers, &r->buf[0], r->num); + + return (int)r->num; } /*****************/ /* FQ management */ /*****************/ +struct qbman_alt_fq_state_desc { + uint8_t verb; + uint8_t reserved[3]; + uint32_t fqid; + uint8_t reserved2[56]; +}; + +struct qbman_alt_fq_state_rslt { + uint8_t verb; + uint8_t rslt; + uint8_t reserved[62]; +}; -static struct qb_attr_code code_fqalt_fqid = QB_CODE(1, 0, 32); +#define ALT_FQ_FQID_MASK 0x00FFFFFF static int qbman_swp_alt_fq_state(struct qbman_swp *s, uint32_t fqid, uint8_t alt_fq_verb) { - uint32_t *p; - uint32_t rslt; + struct qbman_alt_fq_state_desc *p; + struct qbman_alt_fq_state_rslt *r; /* Start the management command */ p = qbman_swp_mc_start(s); if (!p) return -EBUSY; - qb_attr_code_encode(&code_fqalt_fqid, p, fqid); + p->fqid = fqid & ALT_FQ_FQID_MASK; + /* Complete the management command */ - p = qbman_swp_mc_complete(s, p, p[0] | alt_fq_verb); + r = qbman_swp_mc_complete(s, p, alt_fq_verb); + if (unlikely(!r)) { + pr_err("qbman: mgmt cmd failed, no response (verb=0x%x)\n", + alt_fq_verb); + return -EIO; + } /* Decode the outcome */ - rslt = qb_attr_code_decode(&code_generic_rslt, p); - QBMAN_BUG_ON(qb_attr_code_decode(&code_generic_verb, p) != alt_fq_verb); + QBMAN_BUG_ON((r->verb & QBMAN_RESPONSE_VERB_MASK) != alt_fq_verb); /* Determine success or failure */ - if (unlikely(rslt != QBMAN_MC_RSLT_OK)) { + if (unlikely(r->rslt != QBMAN_MC_RSLT_OK)) { pr_err("ALT FQID %d failed: verb = 0x%08x, code = 0x%02x\n", - fqid, alt_fq_verb, rslt); + fqid, alt_fq_verb, r->rslt); return -EIO; } @@ -1408,10 +1330,24 @@ int qbman_swp_fq_xoff(struct qbman_swp *s, uint32_t fqid) /* Channel management */ /**********************/ -static struct qb_attr_code code_cdan_cid = QB_CODE(0, 16, 12); -static struct qb_attr_code code_cdan_we = QB_CODE(1, 0, 8); -static struct qb_attr_code code_cdan_en = QB_CODE(1, 8, 1); -static struct qb_attr_code code_cdan_ctx_lo = QB_CODE(2, 0, 32); +struct qbman_cdan_ctrl_desc { + uint8_t verb; + uint8_t reserved; + uint16_t ch; + uint8_t we; + uint8_t ctrl; + uint16_t reserved2; + uint64_t cdan_ctx; + uint8_t reserved3[48]; + +}; + +struct qbman_cdan_ctrl_rslt { + uint8_t verb; + uint8_t rslt; + uint16_t ch; + uint8_t reserved[60]; +}; /* Hide "ICD" for now as we don't use it, don't set it, and don't test it, so it * would be irresponsible to expose it. @@ -1423,8 +1359,8 @@ static int qbman_swp_CDAN_set(struct qbman_swp *s, uint16_t channelid, uint8_t we_mask, uint8_t cdan_en, uint64_t ctx) { - uint32_t *p; - uint32_t rslt; + struct qbman_cdan_ctrl_desc *p; + struct qbman_cdan_ctrl_rslt *r; /* Start the management command */ p = qbman_swp_mc_start(s); @@ -1432,22 +1368,29 @@ static int qbman_swp_CDAN_set(struct qbman_swp *s, uint16_t channelid, return -EBUSY; /* Encode the caller-provided attributes */ - qb_attr_code_encode(&code_cdan_cid, p, channelid); - qb_attr_code_encode(&code_cdan_we, p, we_mask); - qb_attr_code_encode(&code_cdan_en, p, cdan_en); - qb_attr_code_encode_64(&code_cdan_ctx_lo, (uint64_t *)p, ctx); + p->ch = channelid; + p->we = we_mask; + if (cdan_en) + p->ctrl = 1; + else + p->ctrl = 0; + p->cdan_ctx = ctx; + /* Complete the management command */ - p = qbman_swp_mc_complete(s, p, p[0] | QBMAN_WQCHAN_CONFIGURE); + r = qbman_swp_mc_complete(s, p, QBMAN_WQCHAN_CONFIGURE); + if (unlikely(!r)) { + pr_err("qbman: wqchan config failed, no response\n"); + return -EIO; + } /* Decode the outcome */ - rslt = qb_attr_code_decode(&code_generic_rslt, p); - QBMAN_BUG_ON(qb_attr_code_decode(&code_generic_verb, p) - != QBMAN_WQCHAN_CONFIGURE); + QBMAN_BUG_ON((r->verb & QBMAN_RESPONSE_VERB_MASK) + != QBMAN_WQCHAN_CONFIGURE); /* Determine success or failure */ - if (unlikely(rslt != QBMAN_MC_RSLT_OK)) { + if (unlikely(r->rslt != QBMAN_MC_RSLT_OK)) { pr_err("CDAN cQID %d failed: code = 0x%02x\n", - channelid, rslt); + channelid, r->rslt); return -EIO; } diff --git a/drivers/bus/fslmc/qbman/qbman_portal.h b/drivers/bus/fslmc/qbman/qbman_portal.h index 8018048..bfcef8f 100644 --- a/drivers/bus/fslmc/qbman/qbman_portal.h +++ b/drivers/bus/fslmc/qbman/qbman_portal.h @@ -123,12 +123,12 @@ struct qbman_swp { * non-NULL if only if the response is complete). */ void *qbman_swp_mc_start(struct qbman_swp *p); -void qbman_swp_mc_submit(struct qbman_swp *p, void *cmd, uint32_t cmd_verb); +void qbman_swp_mc_submit(struct qbman_swp *p, void *cmd, uint8_t cmd_verb); void *qbman_swp_mc_result(struct qbman_swp *p); /* Wraps up submit + poll-for-result */ static inline void *qbman_swp_mc_complete(struct qbman_swp *swp, void *cmd, - uint32_t cmd_verb) + uint8_t cmd_verb) { int loopvar; @@ -275,4 +275,4 @@ static inline int32_t qb_attr_code_makesigned(const struct qb_attr_code *code, * an inline) is necessary to work with different descriptor types and to work * correctly with const and non-const inputs (and similarly-qualified outputs). */ -#define qb_cl(d) (&(d)->dont_manipulate_directly[0]) +#define qb_cl(d) (&(d)->donot_manipulate_directly[0]) diff --git a/drivers/bus/fslmc/qbman/qbman_private.h b/drivers/bus/fslmc/qbman/qbman_private.h index b98c330..4f48b47 100644 --- a/drivers/bus/fslmc/qbman/qbman_private.h +++ b/drivers/bus/fslmc/qbman/qbman_private.h @@ -92,7 +92,7 @@ do { \ * */ #ifdef __LP64__ -#define MAKE_MASK32(width) ((uint32_t)(( 1ULL << width) - 1)) +#define MAKE_MASK32(width) ((uint32_t)((1ULL << width) - 1)) #else #define MAKE_MASK32(width) (width == 32 ? 0xffffffff : \ (uint32_t)((1 << width) - 1)) diff --git a/drivers/bus/fslmc/qbman/qbman_sys.h b/drivers/bus/fslmc/qbman/qbman_sys.h index 47da595..c73d2bf 100644 --- a/drivers/bus/fslmc/qbman/qbman_sys.h +++ b/drivers/bus/fslmc/qbman/qbman_sys.h @@ -357,15 +357,3 @@ static inline void qbman_swp_sys_finish(struct qbman_swp_sys *s) { free_page((unsigned long)s->cena); } - -static inline void * -qbman_cena_write_start_wo_shadow_fast(struct qbman_swp_sys *s, - uint32_t offset) -{ -#ifdef QBMAN_CENA_TRACE - pr_info("qbman_cena_write_start(%p:%d:0x%03x)\n", - s->addr_cena, s->idx, offset); -#endif - QBMAN_BUG_ON(offset & 63); - return (s->addr_cena + offset); -} diff --git a/drivers/bus/fslmc/rte_bus_fslmc_version.map b/drivers/bus/fslmc/rte_bus_fslmc_version.map index 13fb46a..3cc7dad 100644 --- a/drivers/bus/fslmc/rte_bus_fslmc_version.map +++ b/drivers/bus/fslmc/rte_bus_fslmc_version.map @@ -62,11 +62,12 @@ DPDK_17.08 { dpio_remove_static_dequeue_channel; mc_get_soc_version; mc_get_version; + qbman_check_new_result; qbman_eq_desc_set_dca; qbman_get_dqrr_from_idx; qbman_get_dqrr_idx; qbman_result_DQ_fqd_ctx; - qbman_result_SCN_state_in_mem; + qbman_result_SCN_state; qbman_swp_dqrr_consume; qbman_swp_dqrr_next; qbman_swp_enqueue_multiple; diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c index 094cf30..d2aff28 100644 --- a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c +++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c @@ -747,13 +747,13 @@ dpaa2_sec_dequeue_burst(void *qp, struct rte_crypto_op **ops, * Also seems like the SWP is shared between the Ethernet Driver * and the SEC driver. */ - while (!qbman_check_command_complete(swp, dq_storage)) + while (!qbman_check_command_complete(dq_storage)) ; /* Loop until the dq_storage is updated with * new token by QBMAN */ - while (!qbman_result_has_new_result(swp, dq_storage)) + while (!qbman_check_new_result(dq_storage)) ; /* Check whether Last Pull command is Expired and * setting Condition for Loop termination diff --git a/drivers/net/dpaa2/dpaa2_rxtx.c b/drivers/net/dpaa2/dpaa2_rxtx.c index 4342c73..75a06f5 100644 --- a/drivers/net/dpaa2/dpaa2_rxtx.c +++ b/drivers/net/dpaa2/dpaa2_rxtx.c @@ -422,7 +422,7 @@ dpaa2_dev_prefetch_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts) qbman_pull_desc_set_storage(&pulldesc, dq_storage, (dma_addr_t)(DPAA2_VADDR_TO_IOVA(dq_storage)), 1); if (check_swp_active_dqs(DPAA2_PER_LCORE_DPIO->index)) { - while (!qbman_check_command_complete(swp, + while (!qbman_check_command_complete( get_swp_active_dqs(DPAA2_PER_LCORE_DPIO->index))) ; clear_swp_active_dqs(DPAA2_PER_LCORE_DPIO->index); @@ -445,7 +445,7 @@ dpaa2_dev_prefetch_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts) * Also seems like the SWP is shared between the Ethernet Driver * and the SEC driver. */ - while (!qbman_check_command_complete(swp, dq_storage)) + while (!qbman_check_command_complete(dq_storage)) ; if (dq_storage == get_swp_active_dqs(q_storage->active_dpio_id)) clear_swp_active_dqs(q_storage->active_dpio_id); @@ -453,7 +453,7 @@ dpaa2_dev_prefetch_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts) /* Loop until the dq_storage is updated with * new token by QBMAN */ - while (!qbman_result_has_new_result(swp, dq_storage)) + while (!qbman_check_new_result(dq_storage)) ; rte_prefetch0((void *)((uint64_t)(dq_storage + 1))); /* Check whether Last Pull command is Expired and @@ -486,7 +486,7 @@ dpaa2_dev_prefetch_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts) } if (check_swp_active_dqs(DPAA2_PER_LCORE_DPIO->index)) { - while (!qbman_check_command_complete(swp, + while (!qbman_check_command_complete( get_swp_active_dqs(DPAA2_PER_LCORE_DPIO->index))) ; clear_swp_active_dqs(DPAA2_PER_LCORE_DPIO->index); @@ -560,7 +560,7 @@ dpaa2_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts) while (nb_pkts) { /*Check if the queue is congested*/ retry_count = 0; - if (qbman_result_SCN_state_in_mem(dpaa2_q->cscn)) { + while (qbman_result_SCN_state(dpaa2_q->cscn)) { retry_count++; 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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR03MB2700 Subject: [dpdk-dev] [PATCH v3 07/27] bus/fslmc: cleanup compat file X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Signed-off-by: Hemant Agrawal --- drivers/bus/fslmc/qbman/include/compat.h | 188 +------------------------------ drivers/bus/fslmc/qbman/qbman_private.h | 2 +- 2 files changed, 4 insertions(+), 186 deletions(-) -- 2.7.4 diff --git a/drivers/bus/fslmc/qbman/include/compat.h b/drivers/bus/fslmc/qbman/include/compat.h index 7b69fd1..8885d60 100644 --- a/drivers/bus/fslmc/qbman/include/compat.h +++ b/drivers/bus/fslmc/qbman/include/compat.h @@ -65,16 +65,9 @@ */ /* Required compiler attributes */ -#define __user #define likely(x) __builtin_expect(!!(x), 1) #define unlikely(x) __builtin_expect(!!(x), 0) #define ____cacheline_aligned __attribute__((aligned(L1_CACHE_BYTES))) -#undef container_of -#define container_of(ptr, type, member) ({ \ - typeof(((type *)0)->member)(*__mptr) = (ptr); \ - (type *)((char *)__mptr - offsetof(type, member)); }) -#define __stringify_1(x) #x -#define __stringify(x) __stringify_1(x) #ifdef ARRAY_SIZE #undef ARRAY_SIZE @@ -88,17 +81,8 @@ typedef uint32_t u32; typedef uint64_t u64; typedef uint64_t dma_addr_t; typedef cpu_set_t cpumask_t; -typedef u32 compat_uptr_t; - -static inline void __user *compat_ptr(compat_uptr_t uptr) -{ - return (void __user *)(unsigned long)uptr; -} - -static inline compat_uptr_t ptr_to_compat(void __user *uptr) -{ - return (u32)(unsigned long)uptr; -} +typedef unsigned int gfp_t; +typedef uint32_t phandle; /* I/O operations */ static inline u32 in_be32(volatile void *__p) @@ -124,12 +108,11 @@ static inline void out_be32(volatile void *__p, u32 val) #define pr_warn(fmt, args...) prflush("WARN:" fmt, ##args) #define pr_info(fmt, args...) prflush(fmt, ##args) +#ifdef RTE_LIBRTE_DPAA2_DEBUG_BUS #ifdef pr_debug #undef pr_debug #endif #define pr_debug(fmt, args...) {} -#define might_sleep_if(c) {} -#define msleep(x) {} #define WARN_ON(c, str) \ do { \ static int warned_##__LINE__; \ @@ -147,103 +130,20 @@ do { \ #define ALIGN(x, a) (((x) + ((typeof(x))(a) - 1)) & ~((typeof(x))(a) - 1)) -/****************/ -/* Linked-lists */ -/****************/ - -struct list_head { - struct list_head *prev; - struct list_head *next; -}; - -#define LIST_HEAD(n) \ -struct list_head n = { \ - .prev = &n, \ - .next = &n \ -} - -#define INIT_LIST_HEAD(p) \ -do { \ - struct list_head *__p298 = (p); \ - __p298->next = __p298; \ - __p298->prev = __p298->next; \ -} while (0) -#define list_entry(node, type, member) \ - (type *)((void *)node - offsetof(type, member)) -#define list_empty(p) \ -({ \ - const struct list_head *__p298 = (p); \ - ((__p298->next == __p298) && (__p298->prev == __p298)); \ -}) -#define list_add(p, l) \ -do { \ - struct list_head *__p298 = (p); \ - struct list_head *__l298 = (l); \ - __p298->next = __l298->next; \ - __p298->prev = __l298; \ - __l298->next->prev = __p298; \ - __l298->next = __p298; \ -} while (0) -#define list_add_tail(p, l) \ -do { \ - struct list_head *__p298 = (p); \ - struct list_head *__l298 = (l); \ - __p298->prev = __l298->prev; \ - __p298->next = __l298; \ - __l298->prev->next = __p298; \ - __l298->prev = __p298; \ -} while (0) -#define list_for_each(i, l) \ - for (i = (l)->next; i != (l); i = i->next) -#define list_for_each_safe(i, j, l) \ - for (i = (l)->next, j = i->next; i != (l); \ - i = j, j = i->next) -#define list_for_each_entry(i, l, name) \ - for (i = list_entry((l)->next, typeof(*i), name); &i->name != (l); \ - i = list_entry(i->name.next, typeof(*i), name)) -#define list_for_each_entry_safe(i, j, l, name) \ - for (i = list_entry((l)->next, typeof(*i), name), \ - j = list_entry(i->name.next, typeof(*j), name); \ - &i->name != (l); \ - i = j, j = list_entry(j->name.next, typeof(*j), name)) -#define list_del(i) \ -do { \ - (i)->next->prev = (i)->prev; \ - (i)->prev->next = (i)->next; \ -} while (0) - /* Other miscellaneous interfaces our APIs depend on; */ - #define lower_32_bits(x) ((u32)(x)) #define upper_32_bits(x) ((u32)(((x) >> 16) >> 16)) /* Compiler/type stuff */ -typedef unsigned int gfp_t; -typedef uint32_t phandle; #define __iomem -#define EINTR 4 -#define ENODEV 19 #define GFP_KERNEL 0 #define __raw_readb(p) (*(const volatile unsigned char *)(p)) #define __raw_readl(p) (*(const volatile unsigned int *)(p)) #define __raw_writel(v, p) {*(volatile unsigned int *)(p) = (v); } -/* Completion stuff */ -#define DECLARE_COMPLETION(n) int n = 0 -#define complete(n) { *n = 1; } -#define wait_for_completion(n) \ -do { \ - while (!*n) { \ - bman_poll(); \ - qman_poll(); \ - } \ - *n = 0; \ -} while (0) - /* Allocator stuff */ #define kmalloc(sz, t) malloc(sz) -#define vmalloc(sz) malloc(sz) #define kfree(p) { if (p) free(p); } static inline void *kzalloc(size_t sz, gfp_t __foo __rte_unused) { @@ -269,88 +169,6 @@ static inline void free_page(unsigned long p) free((void *)p); } -/* Bitfield stuff. */ -#define BITS_PER_ULONG (sizeof(unsigned long) << 3) -#define SHIFT_PER_ULONG (((1 << 5) == BITS_PER_ULONG) ? 5 : 6) -#define BITS_MASK(idx) ((unsigned long)1 << ((idx) & (BITS_PER_ULONG - 1))) -#define BITS_IDX(idx) ((idx) >> SHIFT_PER_ULONG) -static inline unsigned long test_bits(unsigned long mask, - volatile unsigned long *p) -{ - return *p & mask; -} - -static inline int test_bit(int idx, volatile unsigned long *bits) -{ - return test_bits(BITS_MASK(idx), bits + BITS_IDX(idx)); -} - -static inline void set_bits(unsigned long mask, volatile unsigned long *p) -{ - *p |= mask; -} - -static inline void set_bit(int idx, volatile unsigned long *bits) -{ - set_bits(BITS_MASK(idx), bits + BITS_IDX(idx)); -} - -static inline void clear_bits(unsigned long mask, volatile unsigned long *p) -{ - *p &= ~mask; -} - -static inline void clear_bit(int idx, volatile unsigned long *bits) -{ - clear_bits(BITS_MASK(idx), bits + BITS_IDX(idx)); -} - -static inline unsigned long test_and_set_bits(unsigned long mask, - volatile unsigned long *p) -{ - unsigned long ret = test_bits(mask, p); - - set_bits(mask, p); - return ret; -} - -static inline int test_and_set_bit(int idx, volatile unsigned long *bits) -{ - int ret = test_bit(idx, bits); - - set_bit(idx, bits); - return ret; -} - -static inline int test_and_clear_bit(int idx, volatile unsigned long *bits) -{ - int ret = test_bit(idx, bits); - - clear_bit(idx, bits); - return ret; -} - -static inline int find_next_zero_bit(unsigned long *bits, int limit, int idx) -{ - while ((++idx < limit) && test_bit(idx, bits)) - ; - return idx; -} - -static inline int find_first_zero_bit(unsigned long *bits, int limit) -{ - int idx = 0; - - while (test_bit(idx, bits) && (++idx < limit)) - ; - return idx; -} - -static inline u64 div64_u64(u64 n, u64 d) -{ - return n / d; -} - #define atomic_t rte_atomic32_t #define atomic_read(v) rte_atomic32_read(v) #define atomic_set(v, i) rte_atomic32_set(v, i) diff --git a/drivers/bus/fslmc/qbman/qbman_private.h b/drivers/bus/fslmc/qbman/qbman_private.h index 4f48b47..32e5c5d 100644 --- a/drivers/bus/fslmc/qbman/qbman_private.h +++ b/drivers/bus/fslmc/qbman/qbman_private.h @@ -27,7 +27,7 @@ */ /* Perform extra checking */ -#define QBMAN_CHECKING +/*#define QBMAN_CHECKING*/ /* To maximise the amount of logic that is common between the Linux driver and * other targets (such as the embedded MC firmware), we pivot here between the From patchwork Sat Sep 16 10:52:22 2017 Content-Type: text/plain; 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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR03MB2692 Subject: [dpdk-dev] [PATCH v3 08/27] bus/fslmc: clean the qbman support code X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Signed-off-by: Hemant Agrawal --- drivers/bus/fslmc/qbman/include/compat.h | 98 +++--------- drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h | 5 +- drivers/bus/fslmc/qbman/qbman_portal.c | 26 +-- drivers/bus/fslmc/qbman/qbman_portal.h | 133 ++------------- drivers/bus/fslmc/qbman/qbman_private.h | 178 --------------------- drivers/bus/fslmc/qbman/qbman_sys.h | 131 ++++++++------- drivers/bus/fslmc/qbman/qbman_sys_decl.h | 25 +-- 7 files changed, 112 insertions(+), 484 deletions(-) delete mode 100644 drivers/bus/fslmc/qbman/qbman_private.h -- 2.7.4 diff --git a/drivers/bus/fslmc/qbman/include/compat.h b/drivers/bus/fslmc/qbman/include/compat.h index 8885d60..423087c 100644 --- a/drivers/bus/fslmc/qbman/include/compat.h +++ b/drivers/bus/fslmc/qbman/include/compat.h @@ -30,32 +30,17 @@ #ifndef HEADER_COMPAT_H #define HEADER_COMPAT_H -#include - #ifndef _GNU_SOURCE #define _GNU_SOURCE #endif #include #include -#include #include #include -#include -#include -#include -#include -#include #include -#include -#include -#include #include -#include -#include -#include -#include -#include #include +#include #include /* The following definitions are primarily to allow the single-source driver @@ -67,35 +52,9 @@ /* Required compiler attributes */ #define likely(x) __builtin_expect(!!(x), 1) #define unlikely(x) __builtin_expect(!!(x), 0) -#define ____cacheline_aligned __attribute__((aligned(L1_CACHE_BYTES))) - -#ifdef ARRAY_SIZE -#undef ARRAY_SIZE -#endif -#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) /* Required types */ -typedef uint8_t u8; -typedef uint16_t u16; -typedef uint32_t u32; -typedef uint64_t u64; typedef uint64_t dma_addr_t; -typedef cpu_set_t cpumask_t; -typedef unsigned int gfp_t; -typedef uint32_t phandle; - -/* I/O operations */ -static inline u32 in_be32(volatile void *__p) -{ - volatile u32 *p = __p; - return *p; -} - -static inline void out_be32(volatile void *__p, u32 val) -{ - volatile u32 *p = __p; - *p = val; -} /* Debugging */ #define prflush(fmt, args...) \ @@ -109,66 +68,45 @@ static inline void out_be32(volatile void *__p, u32 val) #define pr_info(fmt, args...) prflush(fmt, ##args) #ifdef RTE_LIBRTE_DPAA2_DEBUG_BUS + +/* Trace the 3 different classes of read/write access to QBMan. #undef as + * required. + */ +#define QBMAN_CCSR_TRACE +#define QBMAN_CINH_TRACE +#define QBMAN_CENA_TRACE + +#define QBMAN_CHECKING + #ifdef pr_debug #undef pr_debug #endif -#define pr_debug(fmt, args...) {} -#define WARN_ON(c, str) \ +#define pr_debug(fmt, args...) printf(fmt, ##args) +#define QBMAN_BUG_ON(c) \ do { \ static int warned_##__LINE__; \ if ((c) && !warned_##__LINE__) { \ - pr_warn("%s\n", str); \ pr_warn("(%s:%d)\n", __FILE__, __LINE__); \ warned_##__LINE__ = 1; \ } \ } while (0) -#ifdef CONFIG_BUGON -#define QBMAN_BUG_ON(c) WARN_ON(c, "BUG") #else #define QBMAN_BUG_ON(c) {} +#define pr_debug(fmt, args...) {} #endif -#define ALIGN(x, a) (((x) + ((typeof(x))(a) - 1)) & ~((typeof(x))(a) - 1)) - /* Other miscellaneous interfaces our APIs depend on; */ -#define lower_32_bits(x) ((u32)(x)) -#define upper_32_bits(x) ((u32)(((x) >> 16) >> 16)) -/* Compiler/type stuff */ +#define lower_32_bits(x) ((uint32_t)(x)) +#define upper_32_bits(x) ((uint32_t)(((x) >> 16) >> 16)) + #define __iomem -#define GFP_KERNEL 0 + #define __raw_readb(p) (*(const volatile unsigned char *)(p)) #define __raw_readl(p) (*(const volatile unsigned int *)(p)) #define __raw_writel(v, p) {*(volatile unsigned int *)(p) = (v); } -/* Allocator stuff */ -#define kmalloc(sz, t) malloc(sz) -#define kfree(p) { if (p) free(p); } -static inline void *kzalloc(size_t sz, gfp_t __foo __rte_unused) -{ - void *ptr = malloc(sz); - - if (ptr) - memset(ptr, 0, sz); - return ptr; -} - -static inline unsigned long get_zeroed_page(gfp_t __foo __rte_unused) -{ - void *p; - - if (posix_memalign(&p, 4096, 4096)) - return 0; - memset(p, 0, 4096); - return (unsigned long)p; -} - -static inline void free_page(unsigned long p) -{ - free((void *)p); -} - #define atomic_t rte_atomic32_t #define atomic_read(v) rte_atomic32_read(v) #define atomic_set(v, i) rte_atomic32_set(v, i) diff --git a/drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h b/drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h index 24a6d4b..1e65660 100644 --- a/drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h +++ b/drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h @@ -329,7 +329,7 @@ void qbman_pull_desc_clear(struct qbman_pull_desc *d); */ void qbman_pull_desc_set_storage(struct qbman_pull_desc *d, struct qbman_result *storage, - dma_addr_t storage_phys, + uint64_t storage_phys, int stash); /** * qbman_pull_desc_set_numframes() - Set the number of frames to be dequeued. @@ -796,7 +796,6 @@ struct qbman_eq_desc { uint8_t wae; uint8_t rspid; uint64_t rsp_addr; - uint8_t fd[32]; } eq; }; }; @@ -881,7 +880,7 @@ void qbman_eq_desc_set_orp_nesn(struct qbman_eq_desc *d, uint16_t opr_id, * expresses a cache-warming attribute. */ void qbman_eq_desc_set_response(struct qbman_eq_desc *d, - dma_addr_t storage_phys, + uint64_t storage_phys, int stash); /** diff --git a/drivers/bus/fslmc/qbman/qbman_portal.c b/drivers/bus/fslmc/qbman/qbman_portal.c index cd903c1..809770c 100644 --- a/drivers/bus/fslmc/qbman/qbman_portal.c +++ b/drivers/bus/fslmc/qbman/qbman_portal.c @@ -126,7 +126,7 @@ struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc *d) { int ret; uint32_t eqcr_pi; - struct qbman_swp *p = kmalloc(sizeof(*p), GFP_KERNEL); + struct qbman_swp *p = malloc(sizeof(*p)); if (!p) return NULL; @@ -155,7 +155,7 @@ struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc *d) ret = qbman_swp_sys_init(&p->sys, d, p->dqrr.dqrr_size); if (ret) { - kfree(p); + free(p); pr_err("qbman_swp_sys_init() failed %d\n", ret); return NULL; } @@ -183,7 +183,7 @@ void qbman_swp_finish(struct qbman_swp *p) #endif qbman_swp_sys_finish(&p->sys); portal_idx_map[p->desc.idx] = NULL; - kfree(p); + free(p); } const struct qbman_swp_desc *qbman_swp_get_desc(struct qbman_swp *p) @@ -1097,15 +1097,7 @@ int qbman_result_bpscn_is_surplus(const struct qbman_result *scn) uint64_t qbman_result_bpscn_ctx(const struct qbman_result *scn) { - uint64_t ctx; - uint32_t ctx_hi, ctx_lo; - - ctx = qbman_result_SCN_ctx(scn); - ctx_hi = upper32(ctx); - ctx_lo = lower32(ctx); - - return ((uint64_t)make_le32(ctx_hi) << 32 | - (uint64_t)make_le32(ctx_lo)); + return qbman_result_SCN_ctx(scn); } /*****************/ @@ -1118,15 +1110,7 @@ uint16_t qbman_result_cgcu_cgid(const struct qbman_result *scn) uint64_t qbman_result_cgcu_icnt(const struct qbman_result *scn) { - uint64_t ctx; - uint32_t ctx_hi, ctx_lo; - - ctx = qbman_result_SCN_ctx(scn); - ctx_hi = upper32(ctx); - ctx_lo = lower32(ctx); - - return ((uint64_t)(make_le32(ctx_hi) & 0xFF) << 32) | - (uint64_t)make_le32(ctx_lo); + return qbman_result_SCN_ctx(scn); } /******************/ diff --git a/drivers/bus/fslmc/qbman/qbman_portal.h b/drivers/bus/fslmc/qbman/qbman_portal.h index bfcef8f..d9f3ed7 100644 --- a/drivers/bus/fslmc/qbman/qbman_portal.h +++ b/drivers/bus/fslmc/qbman/qbman_portal.h @@ -26,10 +26,14 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include "qbman_private.h" +#include "qbman_sys.h" #include uint32_t qman_version; +#define QMAN_REV_4000 0x04000000 +#define QMAN_REV_4100 0x04010000 +#define QMAN_REV_4101 0x04010001 + /* All QBMan command and result structures use this "valid bit" encoding */ #define QB_VALID_BIT ((uint32_t)0x80) @@ -40,7 +44,8 @@ uint32_t qman_version; #define QBMAN_EQCR_SIZE 8 -static inline u8 qm_cyc_diff(u8 ringsize, u8 first, u8 last) +static inline uint8_t qm_cyc_diff(uint8_t ringsize, uint8_t first, + uint8_t last) { /* 'first' is included, 'last' is excluded */ if (first <= last) @@ -130,131 +135,15 @@ void *qbman_swp_mc_result(struct qbman_swp *p); static inline void *qbman_swp_mc_complete(struct qbman_swp *swp, void *cmd, uint8_t cmd_verb) { - int loopvar; + int loopvar = 1000; qbman_swp_mc_submit(swp, cmd, cmd_verb); - DBG_POLL_START(loopvar); do { - DBG_POLL_CHECK(loopvar); cmd = qbman_swp_mc_result(swp); - } while (!cmd); - return cmd; -} - -/* ------------ */ -/* qb_attr_code */ -/* ------------ */ - -/* This struct locates a sub-field within a QBMan portal (CENA) cacheline which - * is either serving as a configuration command or a query result. The - * representation is inherently little-endian, as the indexing of the words is - * itself little-endian in nature and DPAA2 QBMan is little endian for anything - * that crosses a word boundary too (64-bit fields are the obvious examples). - */ -struct qb_attr_code { - unsigned int word; /* which uint32_t[] array member encodes the field */ - unsigned int lsoffset; /* encoding offset from ls-bit */ - unsigned int width; /* encoding width. (bool must be 1.) */ -}; - -/* Some pre-defined codes */ -extern struct qb_attr_code code_generic_verb; -extern struct qb_attr_code code_generic_rslt; - -/* Macros to define codes */ -#define QB_CODE(a, b, c) { a, b, c} -#define QB_CODE_NULL \ - QB_CODE((unsigned int)-1, (unsigned int)-1, (unsigned int)-1) - -/* Rotate a code "ms", meaning that it moves from less-significant bytes to - * more-significant, from less-significant words to more-significant, etc. The - * "ls" version does the inverse, from more-significant towards - * less-significant. - */ -static inline void qb_attr_code_rotate_ms(struct qb_attr_code *code, - unsigned int bits) -{ - code->lsoffset += bits; - while (code->lsoffset > 31) { - code->word++; - code->lsoffset -= 32; - } -} - -static inline void qb_attr_code_rotate_ls(struct qb_attr_code *code, - unsigned int bits) -{ - /* Don't be fooled, this trick should work because the types are - * unsigned. So the case that interests the while loop (the rotate has - * gone too far and the word count needs to compensate for it), is - * manifested when lsoffset is negative. But that equates to a really - * large unsigned value, starting with lots of "F"s. As such, we can - * continue adding 32 back to it until it wraps back round above zero, - * to a value of 31 or less... - */ - code->lsoffset -= bits; - while (code->lsoffset > 31) { - code->word--; - code->lsoffset += 32; - } -} + } while (!cmd && loopvar--); + QBMAN_BUG_ON(!loopvar); -/* Implement a loop of code rotations until 'expr' evaluates to FALSE (0). */ -#define qb_attr_code_for_ms(code, bits, expr) \ - for (; expr; qb_attr_code_rotate_ms(code, bits)) -#define qb_attr_code_for_ls(code, bits, expr) \ - for (; expr; qb_attr_code_rotate_ls(code, bits)) - -/* decode a field from a cacheline */ -static inline uint32_t qb_attr_code_decode(const struct qb_attr_code *code, - const uint32_t *cacheline) -{ - return d32_uint32_t(code->lsoffset, code->width, cacheline[code->word]); -} - -static inline uint64_t qb_attr_code_decode_64(const struct qb_attr_code *code, - const uint64_t *cacheline) -{ - return cacheline[code->word / 2]; -} - -/* encode a field to a cacheline */ -static inline void qb_attr_code_encode(const struct qb_attr_code *code, - uint32_t *cacheline, uint32_t val) -{ - cacheline[code->word] = - r32_uint32_t(code->lsoffset, code->width, cacheline[code->word]) - | e32_uint32_t(code->lsoffset, code->width, val); -} - -static inline void qb_attr_code_encode_64(const struct qb_attr_code *code, - uint64_t *cacheline, uint64_t val) -{ - cacheline[code->word / 2] = val; -} - -/* Small-width signed values (two's-complement) will decode into medium-width - * positives. (Eg. for an 8-bit signed field, which stores values from -128 to - * +127, a setting of -7 would appear to decode to the 32-bit unsigned value - * 249. Likewise -120 would decode as 136.) This function allows the caller to - * "re-sign" such fields to 32-bit signed. (Eg. -7, which was 249 with an 8-bit - * encoding, will become 0xfffffff9 if you cast the return value to uint32_t). - */ -static inline int32_t qb_attr_code_makesigned(const struct qb_attr_code *code, - uint32_t val) -{ - QBMAN_BUG_ON(val >= (1u << code->width)); - /* code->width should never exceed the width of val. If it does then a - * different function with larger val size must be used to translate - * from unsigned to signed - */ - QBMAN_BUG_ON(code->width > sizeof(val) * CHAR_BIT); - /* If the high bit was set, it was encoding a negative */ - if (val >= 1u << (code->width - 1)) - return (int32_t)0 - (int32_t)(((uint32_t)1 << code->width) - - val); - /* Otherwise, it was encoding a positive */ - return (int32_t)val; + return cmd; } /* ---------------------- */ diff --git a/drivers/bus/fslmc/qbman/qbman_private.h b/drivers/bus/fslmc/qbman/qbman_private.h deleted file mode 100644 index 32e5c5d..0000000 --- a/drivers/bus/fslmc/qbman/qbman_private.h +++ /dev/null @@ -1,178 +0,0 @@ -/*- - * BSD LICENSE - * - * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Freescale Semiconductor nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY - * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* Perform extra checking */ -/*#define QBMAN_CHECKING*/ - -/* To maximise the amount of logic that is common between the Linux driver and - * other targets (such as the embedded MC firmware), we pivot here between the - * inclusion of two platform-specific headers. - * - * The first, qbman_sys_decl.h, includes any and all required system headers as - * well as providing any definitions for the purposes of compatibility. The - * second, qbman_sys.h, is where platform-specific routines go. - * - * The point of the split is that the platform-independent code (including this - * header) may depend on platform-specific declarations, yet other - * platform-specific routines may depend on platform-independent definitions. - */ - -#include "qbman_sys_decl.h" - -/* When things go wrong, it is a convenient trick to insert a few FOO() - * statements in the code to trace progress. TODO: remove this once we are - * hacking the code less actively. - */ -#define FOO() fsl_os_print("FOO: %s:%d\n", __FILE__, __LINE__) - -/* Any time there is a register interface which we poll on, this provides a - * "break after x iterations" scheme for it. It's handy for debugging, eg. - * where you don't want millions of lines of log output from a polling loop - * that won't, because such things tend to drown out the earlier log output - * that might explain what caused the problem. (NB: put ";" after each macro!) - * TODO: we should probably remove this once we're done sanitising the - * simulator... - */ -#define DBG_POLL_START(loopvar) (loopvar = 10) -#define DBG_POLL_CHECK(loopvar) \ -do { \ - if (!(loopvar--)) \ - QBMAN_BUG_ON(NULL == "DBG_POLL_CHECK"); \ -} while (0) - -/* For CCSR or portal-CINH registers that contain fields at arbitrary offsets - * and widths, these macro-generated encode/decode/isolate/remove inlines can - * be used. - * - * Eg. to "d"ecode a 14-bit field out of a register (into a "uint16_t" type), - * where the field is located 3 bits "up" from the least-significant bit of the - * register (ie. the field location within the 32-bit register corresponds to a - * mask of 0x0001fff8), you would do; - * uint16_t field = d32_uint16_t(3, 14, reg_value); - * - * Or to "e"ncode a 1-bit boolean value (input type is "int", zero is FALSE, - * non-zero is TRUE, so must convert all non-zero inputs to 1, hence the "!!" - * operator) into a register at bit location 0x00080000 (19 bits "in" from the - * LS bit), do; - * reg_value |= e32_int(19, 1, !!field); - * - * If you wish to read-modify-write a register, such that you leave the 14-bit - * field as-is but have all other fields set to zero, then "i"solate the 14-bit - * value using; - * reg_value = i32_uint16_t(3, 14, reg_value); - * - * Alternatively, you could "r"emove the 1-bit boolean field (setting it to - * zero) but leaving all other fields as-is; - * reg_val = r32_int(19, 1, reg_value); - * - */ -#ifdef __LP64__ -#define MAKE_MASK32(width) ((uint32_t)((1ULL << width) - 1)) -#else -#define MAKE_MASK32(width) (width == 32 ? 0xffffffff : \ - (uint32_t)((1 << width) - 1)) -#endif -#define DECLARE_CODEC32(t) \ -static inline uint32_t e32_##t(uint32_t lsoffset, uint32_t width, t val) \ -{ \ - QBMAN_BUG_ON(width > (sizeof(t) * 8)); \ - return ((uint32_t)val & MAKE_MASK32(width)) << lsoffset; \ -} \ -static inline t d32_##t(uint32_t lsoffset, uint32_t width, uint32_t val) \ -{ \ - QBMAN_BUG_ON(width > (sizeof(t) * 8)); \ - return (t)((val >> lsoffset) & MAKE_MASK32(width)); \ -} \ -static inline uint32_t i32_##t(uint32_t lsoffset, uint32_t width, \ - uint32_t val) \ -{ \ - QBMAN_BUG_ON(width > (sizeof(t) * 8)); \ - return e32_##t(lsoffset, width, d32_##t(lsoffset, width, val)); \ -} \ -static inline uint32_t r32_##t(uint32_t lsoffset, uint32_t width, \ - uint32_t val) \ -{ \ - QBMAN_BUG_ON(width > (sizeof(t) * 8)); \ - return ~(MAKE_MASK32(width) << lsoffset) & val; \ -} -DECLARE_CODEC32(uint32_t) -DECLARE_CODEC32(uint16_t) -DECLARE_CODEC32(uint8_t) -DECLARE_CODEC32(int) - - /*********************/ - /* Debugging assists */ - /*********************/ - -static inline void __hexdump(unsigned long start, unsigned long end, - unsigned long p, size_t sz, const unsigned char *c) -{ - while (start < end) { - unsigned int pos = 0; - char buf[64]; - int nl = 0; - - pos += sprintf(buf + pos, "%08lx: ", start); - do { - if ((start < p) || (start >= (p + sz))) - pos += sprintf(buf + pos, ".."); - else - pos += sprintf(buf + pos, "%02x", *(c++)); - if (!(++start & 15)) { - buf[pos++] = '\n'; - nl = 1; - } else { - nl = 0; - if (!(start & 1)) - buf[pos++] = ' '; - if (!(start & 3)) - buf[pos++] = ' '; - } - } while (start & 15); - if (!nl) - buf[pos++] = '\n'; - buf[pos] = '\0'; - pr_info("%s", buf); - } -} - -static inline void hexdump(const void *ptr, size_t sz) -{ - unsigned long p = (unsigned long)ptr; - unsigned long start = p & ~(unsigned long)15; - unsigned long end = (p + sz + 15) & ~(unsigned long)15; - const unsigned char *c = ptr; - - __hexdump(start, end, p, sz, c); -} - -#define QMAN_REV_4000 0x04000000 -#define QMAN_REV_4100 0x04010000 -#define QMAN_REV_4101 0x04010001 - -#include "qbman_sys.h" diff --git a/drivers/bus/fslmc/qbman/qbman_sys.h b/drivers/bus/fslmc/qbman/qbman_sys.h index c73d2bf..c216e9c 100644 --- a/drivers/bus/fslmc/qbman/qbman_sys.h +++ b/drivers/bus/fslmc/qbman/qbman_sys.h @@ -40,12 +40,50 @@ * *not* to provide linux compatibility. */ -/* Trace the 3 different classes of read/write access to QBMan. #undef as - * required. - */ -#undef QBMAN_CCSR_TRACE -#undef QBMAN_CINH_TRACE -#undef QBMAN_CENA_TRACE +#include "qbman_sys_decl.h" + +/* Debugging assists */ +static inline void __hexdump(unsigned long start, unsigned long end, + unsigned long p, size_t sz, const unsigned char *c) +{ + while (start < end) { + unsigned int pos = 0; + char buf[64]; + int nl = 0; + + pos += sprintf(buf + pos, "%08lx: ", start); + do { + if ((start < p) || (start >= (p + sz))) + pos += sprintf(buf + pos, ".."); + else + pos += sprintf(buf + pos, "%02x", *(c++)); + if (!(++start & 15)) { + buf[pos++] = '\n'; + nl = 1; + } else { + nl = 0; + if (!(start & 1)) + buf[pos++] = ' '; + if (!(start & 3)) + buf[pos++] = ' '; + } + } while (start & 15); + if (!nl) + buf[pos++] = '\n'; + buf[pos] = '\0'; + pr_info("%s", buf); + } +} + +static inline void hexdump(const void *ptr, size_t sz) +{ + unsigned long p = (unsigned long)ptr; + unsigned long start = p & ~15; + unsigned long end = (p + sz + 15) & ~15; + const unsigned char *c = ptr; + + __hexdump(start, end, p, sz, c); +} /* Currently, the CENA support code expects each 32-bit word to be written in * host order, and these are converted to hardware (little-endian) order on @@ -94,34 +132,6 @@ static inline void u64_from_le32_copy(uint64_t *d, const void *s, } } -/* Convert a host-native 32bit value into little endian */ -#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ -static inline uint32_t make_le32(uint32_t val) -{ - return ((val & 0xff) << 24) | ((val & 0xff00) << 8) | - ((val & 0xff0000) >> 8) | ((val & 0xff000000) >> 24); -} - -static inline uint32_t make_le24(uint32_t val) -{ - return (((val & 0xff) << 16) | (val & 0xff00) | - ((val & 0xff0000) >> 16)); -} - -static inline void make_le32_n(uint32_t *val, unsigned int num) -{ - while (num--) { - *val = make_le32(*val); - val++; - } -} - -#else -#define make_le32(val) (val) -#define make_le24(val) (val) -#define make_le32_n(val, len) do {} while (0) -#endif - /******************/ /* Portal access */ /******************/ @@ -249,7 +259,7 @@ static inline void *qbman_cena_read_wo_shadow(struct qbman_swp_sys *s, uint32_t offset) { #ifdef QBMAN_CENA_TRACE - pr_info("qbman_cena_read(%p:%d:0x%03x) %p\n", + pr_info("qbman_cena_read(%p:%d:0x%03x)\n", s->addr_cena, s->idx, offset); #endif return s->addr_cena + offset; @@ -283,20 +293,20 @@ static inline void qbman_cena_prefetch(struct qbman_swp_sys *s, * qbman_portal.c. So use of it is declared locally here. */ #define QBMAN_CINH_SWP_CFG 0xd00 +#define QBMAN_CINH_SWP_CFG 0xd00 +#define SWP_CFG_DQRR_MF_SHIFT 20 +#define SWP_CFG_EST_SHIFT 16 +#define SWP_CFG_WN_SHIFT 14 +#define SWP_CFG_RPM_SHIFT 12 +#define SWP_CFG_DCM_SHIFT 10 +#define SWP_CFG_EPM_SHIFT 8 +#define SWP_CFG_SD_SHIFT 5 +#define SWP_CFG_SP_SHIFT 4 +#define SWP_CFG_SE_SHIFT 3 +#define SWP_CFG_DP_SHIFT 2 +#define SWP_CFG_DE_SHIFT 1 +#define SWP_CFG_EP_SHIFT 0 -/* For MC portal use, we always configure with - * DQRR_MF is (SWP_CFG,20,3) - DQRR max fill (<- 0x4) - * EST is (SWP_CFG,16,3) - EQCR_CI stashing threshold (<- 0x2) - * RPM is (SWP_CFG,12,2) - RCR production notification mode (<- 0x3) - * DCM is (SWP_CFG,10,2) - DQRR consumption notification mode (<- 0x2) - * EPM is (SWP_CFG,8,2) - EQCR production notification mode (<- 0x2) - * SD is (SWP_CFG,5,1) - memory stashing drop enable (<- TRUE) - * SP is (SWP_CFG,4,1) - memory stashing priority (<- TRUE) - * SE is (SWP_CFG,3,1) - memory stashing enable (<- TRUE) - * DP is (SWP_CFG,2,1) - dequeue stashing priority (<- TRUE) - * DE is (SWP_CFG,1,1) - dequeue stashing enable (<- TRUE) - * EP is (SWP_CFG,0,1) - EQCR_CI stashing priority (<- TRUE) - */ static inline uint32_t qbman_set_swp_cfg(uint8_t max_fill, uint8_t wn, uint8_t est, uint8_t rpm, uint8_t dcm, uint8_t epm, int sd, int sp, int se, @@ -304,12 +314,19 @@ static inline uint32_t qbman_set_swp_cfg(uint8_t max_fill, uint8_t wn, { uint32_t reg; - reg = e32_uint8_t(20, (uint32_t)(3 + (max_fill >> 3)), max_fill) | - e32_uint8_t(16, 3, est) | - e32_uint8_t(12, 2, rpm) | e32_uint8_t(10, 2, dcm) | - e32_uint8_t(8, 2, epm) | e32_int(5, 1, sd) | - e32_int(4, 1, sp) | e32_int(3, 1, se) | e32_int(2, 1, dp) | - e32_int(1, 1, de) | e32_int(0, 1, ep) | e32_uint8_t(14, 1, wn); + reg = (max_fill << SWP_CFG_DQRR_MF_SHIFT | + est << SWP_CFG_EST_SHIFT | + wn << SWP_CFG_WN_SHIFT | + rpm << SWP_CFG_RPM_SHIFT | + dcm << SWP_CFG_DCM_SHIFT | + epm << SWP_CFG_EPM_SHIFT | + sd << SWP_CFG_SD_SHIFT | + sp << SWP_CFG_SP_SHIFT | + se << SWP_CFG_SE_SHIFT | + dp << SWP_CFG_DP_SHIFT | + de << SWP_CFG_DE_SHIFT | + ep << SWP_CFG_EP_SHIFT); + return reg; } @@ -322,7 +339,7 @@ static inline int qbman_swp_sys_init(struct qbman_swp_sys *s, s->addr_cena = d->cena_bar; s->addr_cinh = d->cinh_bar; s->idx = (uint32_t)d->idx; - s->cena = (void *)get_zeroed_page(GFP_KERNEL); + s->cena = malloc(4096); if (!s->cena) { pr_err("Could not allocate page for cena shadow\n"); return -1; @@ -347,7 +364,7 @@ static inline int qbman_swp_sys_init(struct qbman_swp_sys *s, reg = qbman_cinh_read(s, QBMAN_CINH_SWP_CFG); if (!reg) { pr_err("The portal %d is not enabled!\n", s->idx); - kfree(s->cena); + free(s->cena); return -1; } return 0; @@ -355,5 +372,5 @@ static inline int qbman_swp_sys_init(struct qbman_swp_sys *s, static inline void qbman_swp_sys_finish(struct qbman_swp_sys *s) { - free_page((unsigned long)s->cena); + free(s->cena); } diff --git a/drivers/bus/fslmc/qbman/qbman_sys_decl.h b/drivers/bus/fslmc/qbman/qbman_sys_decl.h index e52f5ed..e1125cf 100644 --- a/drivers/bus/fslmc/qbman/qbman_sys_decl.h +++ b/drivers/bus/fslmc/qbman/qbman_sys_decl.h @@ -34,27 +34,6 @@ #error "Unknown endianness!" #endif -/* The platform-independent code shouldn't need endianness, except for - * weird/fast-path cases like qbman_result_has_token(), which needs to - * perform a passive and endianness-specific test on a read-only data structure - * very quickly. It's an exception, and this symbol is used for that case. - */ -#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ -#define DQRR_TOK_OFFSET 0 -#define QBMAN_RESULT_VERB_OFFSET_IN_MEM 24 -#define SCN_STATE_OFFSET_IN_MEM 8 -#define SCN_RID_OFFSET_IN_MEM 8 -#else -#define DQRR_TOK_OFFSET 24 -#define QBMAN_RESULT_VERB_OFFSET_IN_MEM 0 -#define SCN_STATE_OFFSET_IN_MEM 16 -#define SCN_RID_OFFSET_IN_MEM 0 -#endif - -/* Similarly-named functions */ -#define upper32(a) upper_32_bits(a) -#define lower32(a) lower_32_bits(a) - /****************/ /* arch assists */ /****************/ @@ -64,10 +43,10 @@ #define dccivac(p) { asm volatile("dc civac, %0" : : "r"(p) : "memory"); } static inline void prefetch_for_load(void *p) { - asm volatile("prfm pldl1keep, [%0, #64]" : : "r" (p)); + asm volatile("prfm pldl1keep, [%0, #0]" : : "r" (p)); } static inline void prefetch_for_store(void *p) { - asm volatile("prfm pstl1keep, [%0, #64]" : : "r" (p)); + asm volatile("prfm pstl1keep, [%0, #0]" : : "r" (p)); } From patchwork Sat Sep 16 10:52:23 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemant Agrawal X-Patchwork-Id: 112793 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp1615883qgf; Sat, 16 Sep 2017 03:55:36 -0700 (PDT) X-Google-Smtp-Source: AOwi7QDvjyZl/3gsNjk/Ochmh2gqaxyy0w1huahlMYbA22KGAbq5Msm2IBoqy/H+CCogPCWbKFRM X-Received: by 10.28.167.10 with SMTP id q10mr4565695wme.107.1505559336098; Sat, 16 Sep 2017 03:55:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505559336; cv=none; d=google.com; s=arc-20160816; b=HVVn0u+7FEMc9/ZKecBMYNb6XzAuekzy3YdDFxoqRhXX90zt6eFE8IJKV4Gmh9wNZB 3UwUtbWBhmtq/1BSKXSSsY78KN+muaP9dtwX1aHzxgYeZQAjN26WjCQQfpEfaUhE9PJf PeWvWtBOMTMWoDZCdgDyXTRXrdjWzRmyNsSfh9LKZwfcv6ctNyA6PZ4ejvKVuAX+EYly zVdtayaa3AXS/ADFUqoOxoNdlSZRDutQQaYEkdDiObJEhc7p86iZoL1f4bXzuo5dEPUs aNLvg7JHlDzA0KWqMyaGAjNZKs7VN89BlazZQH3FtGjGXRufqxjkVEGWimotzlg9HymA C2lw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:spamdiagnosticmetadata :spamdiagnosticoutput:mime-version:references:in-reply-to:message-id :date:cc:to:from:arc-authentication-results; bh=X2XGdiCS4upodAJH6hNqvWPG+vRRv7QmAbnGXNUaZKw=; b=ySjuRNNMdGJPMoSUwBjTM/RS6Gr3jb+5XHT24cL7d2zPpeWpyQx+FlyUZsENOegXIK 1TD5otV0j1JP/oTu2haTyzvMkFdvi+ZgPt8Gjl9OAa2lsWB5haF3z57rjGXSPV8Ry7DI M/oedyaSzcPRO2oVfZQt21v/+1JaI9kNbeYGOdgVmtGwlTAZmhvfTPjbdvMkinVjEpju ZMZ0mmt49QUTljAkAQrjZb8DhOr4yr7ZYQzmAvDw83roCW3SSykISugD01dME9eYc1mx SruEnq1oLLzenHHeYDAydx++x/+UBTkmv6lKTXPieyyN3y28NUF/6NgzfkolkFYFYloy DzNQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from dpdk.org (dpdk.org. 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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN3PR03MB2353 Subject: [dpdk-dev] [PATCH v3 09/27] config/dpaa2: change max lores to 16 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Ashish Jain To support new LX2 series Signed-off-by: Ashish Jain --- config/defconfig_arm64-dpaa2-linuxapp-gcc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.7.4 diff --git a/config/defconfig_arm64-dpaa2-linuxapp-gcc b/config/defconfig_arm64-dpaa2-linuxapp-gcc index 8a42944..91f4993 100644 --- a/config/defconfig_arm64-dpaa2-linuxapp-gcc +++ b/config/defconfig_arm64-dpaa2-linuxapp-gcc @@ -39,7 +39,7 @@ CONFIG_RTE_ARCH_ARM_TUNE="cortex-a72" # # Compile Environment Abstraction Layer # -CONFIG_RTE_MAX_LCORE=8 +CONFIG_RTE_MAX_LCORE=16 CONFIG_RTE_MAX_NUMA_NODES=1 CONFIG_RTE_CACHE_LINE_SIZE=64 From patchwork Sat Sep 16 10:52:24 2017 Content-Type: text/plain; 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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN3PR03MB2356 Subject: [dpdk-dev] [PATCH v3 10/27] bus/fslmc: add support for LX2160 platform X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Ashish Jain Signed-off-by: Ashish Jain --- drivers/bus/fslmc/portal/dpaa2_hw_dpio.c | 22 ++++++++++++++-------- drivers/bus/fslmc/portal/dpaa2_hw_pvt.h | 1 + 2 files changed, 15 insertions(+), 8 deletions(-) -- 2.7.4 diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c index 7315555..8db1f6c 100644 --- a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c +++ b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c @@ -90,20 +90,22 @@ static int dpaa2_cluster_sz = 2; * Cluster 1 (ID = x02) : CPU0, CPU1, CPU2, CPU3; * Cluster 2 (ID = x03) : CPU4, CPU5, CPU6, CPU7; */ - -/* Set the STASH Destination depending on Current CPU ID. - * e.g. Valid values of SDEST are 4,5,6,7. Where, - * CPU 0-1 will have SDEST 4 - * CPU 2-3 will have SDEST 5.....and so on. +/* For LX2160 platform There are four clusters with following mapping: + * Cluster 1 (ID = x00) : CPU0, CPU1; + * Cluster 2 (ID = x01) : CPU2, CPU3; + * Cluster 3 (ID = x02) : CPU4, CPU5; + * Cluster 4 (ID = x03) : CPU6, CPU7; + * Cluster 1 (ID = x04) : CPU8, CPU9; + * Cluster 2 (ID = x05) : CPU10, CP11; + * Cluster 3 (ID = x06) : CPU12, CPU13; + * Cluster 4 (ID = x07) : CPU14, CPU15; */ + static int dpaa2_core_cluster_sdest(int cpu_id) { int x = cpu_id / dpaa2_cluster_sz; - if (x > 3) - x = 3; - return dpaa2_core_cluster_base + x; } @@ -278,6 +280,10 @@ dpaa2_configure_stashing(struct dpaa2_dpio_dev *dpio_dev, int cpu_id) dpaa2_core_cluster_base = 0x02; dpaa2_cluster_sz = 4; PMD_INIT_LOG(DEBUG, "\tLS108x (A53) Platform Detected"); + } else if ((mc_plat_info.svr & 0xffff0000) == SVR_LX2160A) { + dpaa2_core_cluster_base = 0x00; + dpaa2_cluster_sz = 2; + PMD_INIT_LOG(DEBUG, "\tLX2160 Platform Detected"); } first_time = 1; } diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h index 5d7a828..bb52a15 100644 --- a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h +++ b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h @@ -51,6 +51,7 @@ #define SVR_LS1080A 0x87030000 #define SVR_LS2080A 0x87010000 #define SVR_LS2088A 0x87090000 +#define SVR_LX2160A 0x87360000 #ifndef ETH_VLAN_HLEN #define ETH_VLAN_HLEN 4 /** < Vlan Header Length */ From patchwork Sat Sep 16 10:52:25 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemant Agrawal X-Patchwork-Id: 112792 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp1615716qgf; Sat, 16 Sep 2017 03:55:21 -0700 (PDT) X-Google-Smtp-Source: ADKCNb6MXTj5IZeuGD0kbJiNyxzbfnQIR9u1TCSJW0cKtjkfrlNEJhb78cKGYt5UCdAXmpjGn1ve X-Received: by 10.223.176.84 with SMTP id g20mr22269813wra.117.1505559321059; Sat, 16 Sep 2017 03:55:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505559321; cv=none; d=google.com; s=arc-20160816; b=aDw8vNKvNm4P/S2UYUPwm2Xs3F6Y1+mCkrYOLtfR7c6rHybzqTUixcFptx5tSmNBbO 9I4uYkWvg5IDwbV/dmxqpoIfN25xMQDV2XE87KkBrmtG2ec8ta9BYta3mdxSivYBaoIf 9OQ38rUoY+i/JJ5l4977EUSboGn2h/rxIqcHGVTmDWDU79Q3zD77E6PQeaLN3ObNRFho xiA/RiObK9ZS8+2chS7czjIM68kT9ktvssXwHvDhjdt5EGRahJY48cacThQ3sPeZ0pP/ ldz93JPaaf2XvOAmrHpbeUNDRkK7+8BYL64VDq3G9E6twC1vhu/Uf9VrQ2U90n3te+Vu hyRw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:spamdiagnosticmetadata :spamdiagnosticoutput:mime-version:references:in-reply-to:message-id :date:cc:to:from:arc-authentication-results; bh=jsg1zjxoMjBsMxWqo3N3g9209JIMgBrXSbbB4MLqQP8=; b=fsBX54FpQiA4ywww3h3FTCgeZTUtM8jQaZUbkj+QdvWS796lXbX3ptDdEpPPsYc23U M35IC6V43WOfhP9npSit6Bl26Ird2BykA+FMK20VTbuoUiwJXAvVQuXL6Zb6hXbXqXG7 s1I6maglqEDXhAuUvkm+wgKmS9CX7HKuaukJgtrTyqBLjRz10rJ0FRiJXcidEST5K/WQ lqXc0TL0Ap+tSMvviVjOl7i5xTAryVtmZLAs3jhEnO02sCd3Mgxb+wFhuWxxlME6uoVf n4Z6CjKQOuEeDKsPBh9r6XdL1Q4LBlWI9JQFsl7uL1mqWg6BvwGhTuKIM2HLnSD5Qrvj 7C6A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from dpdk.org (dpdk.org. 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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR03MB2691 Subject: [dpdk-dev] [PATCH v3 11/27] net/dpaa2: add support for congestion overhead X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Signed-off-by: Hemant Agrawal --- drivers/net/dpaa2/dpaa2_ethdev.c | 1 + drivers/net/dpaa2/dpaa2_ethdev.h | 1 + 2 files changed, 2 insertions(+) -- 2.7.4 diff --git a/drivers/net/dpaa2/dpaa2_ethdev.c b/drivers/net/dpaa2/dpaa2_ethdev.c index 945dcc7..d7950a5 100644 --- a/drivers/net/dpaa2/dpaa2_ethdev.c +++ b/drivers/net/dpaa2/dpaa2_ethdev.c @@ -419,6 +419,7 @@ dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev, /*enabling per rx queue congestion control */ taildrop.threshold = CONG_THRESHOLD_RX_Q; taildrop.units = DPNI_CONGESTION_UNIT_BYTES; + taildrop.oal = CONG_RX_OAL; PMD_INIT_LOG(DEBUG, "Enabling Early Drop on queue = %d", rx_queue_id); ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token, diff --git a/drivers/net/dpaa2/dpaa2_ethdev.h b/drivers/net/dpaa2/dpaa2_ethdev.h index 07e1da6..6ee1a9f 100644 --- a/drivers/net/dpaa2/dpaa2_ethdev.h +++ b/drivers/net/dpaa2/dpaa2_ethdev.h @@ -61,6 +61,7 @@ * currently considering 32 KB packets */ #define CONG_THRESHOLD_RX_Q (64 * 1024) +#define CONG_RX_OAL 128 /* Size of the input SMMU mapped memory required by MC */ #define DIST_PARAM_IOVA_SIZE 256 From patchwork Sat Sep 16 10:52:26 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemant Agrawal X-Patchwork-Id: 112794 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp1616018qgf; Sat, 16 Sep 2017 03:55:49 -0700 (PDT) X-Google-Smtp-Source: AOwi7QBD3rgrmeILIToyBVOFLk9nPoSNJLaFswQKkAN97T4f5kRl65w7sYx3NvU1x76lLkXdrxRz X-Received: by 10.28.17.207 with SMTP id 198mr4649809wmr.38.1505559349005; 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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR03MB2704 Subject: [dpdk-dev] [PATCH v3 12/27] bus/fslmc: add support to check dpbp presence X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Signed-off-by: Hemant Agrawal --- drivers/bus/fslmc/portal/dpaa2_hw_dpbp.c | 7 +++++++ drivers/bus/fslmc/portal/dpaa2_hw_pvt.h | 1 + drivers/bus/fslmc/rte_bus_fslmc_version.map | 1 + 3 files changed, 9 insertions(+) -- 2.7.4 diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_dpbp.c b/drivers/bus/fslmc/portal/dpaa2_hw_dpbp.c index 1ddd280..7e96115 100644 --- a/drivers/bus/fslmc/portal/dpaa2_hw_dpbp.c +++ b/drivers/bus/fslmc/portal/dpaa2_hw_dpbp.c @@ -129,6 +129,13 @@ void dpaa2_free_dpbp_dev(struct dpaa2_dpbp_dev *dpbp) } } +int dpaa2_dpbp_supported(void) +{ + if (TAILQ_EMPTY(&dpbp_dev_list)) + return -1; + return 0; +} + static struct rte_dpaa2_object rte_dpaa2_dpbp_obj = { .dev_type = DPAA2_BPOOL, .create = dpaa2_create_dpbp_device, diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h index bb52a15..8f39cfb 100644 --- a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h +++ b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h @@ -366,6 +366,7 @@ void set_swp_active_dqs(uint16_t dpio_index, struct qbman_result *dqs) } struct dpaa2_dpbp_dev *dpaa2_alloc_dpbp_dev(void); void dpaa2_free_dpbp_dev(struct dpaa2_dpbp_dev *dpbp); +int dpaa2_dpbp_supported(void); struct dpaa2_dpci_dev *rte_dpaa2_alloc_dpci_dev(void); void rte_dpaa2_free_dpci_dev(struct dpaa2_dpci_dev *dpci); diff --git a/drivers/bus/fslmc/rte_bus_fslmc_version.map b/drivers/bus/fslmc/rte_bus_fslmc_version.map index 3cc7dad..7b25248 100644 --- a/drivers/bus/fslmc/rte_bus_fslmc_version.map +++ b/drivers/bus/fslmc/rte_bus_fslmc_version.map @@ -83,6 +83,7 @@ DPDK_17.08 { DPDK_17.11 { global: + dpaa2_dpbp_supported; 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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN2PR03MB2366 Subject: [dpdk-dev] [PATCH v3 13/27] bus/fslmc: cleanup the dpaa2 interrupt support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Signed-off-by: Hemant Agrawal --- drivers/bus/fslmc/Makefile | 1 + drivers/bus/fslmc/fslmc_vfio.c | 108 +++++++++++++++++++++++----- drivers/bus/fslmc/fslmc_vfio.h | 8 ++- drivers/bus/fslmc/portal/dpaa2_hw_dpio.c | 18 +++-- drivers/bus/fslmc/rte_bus_fslmc_version.map | 2 + 5 files changed, 110 insertions(+), 27 deletions(-) -- 2.7.4 diff --git a/drivers/bus/fslmc/Makefile b/drivers/bus/fslmc/Makefile index d1b790b..37da1b0 100644 --- a/drivers/bus/fslmc/Makefile +++ b/drivers/bus/fslmc/Makefile @@ -51,6 +51,7 @@ CFLAGS += -I$(RTE_SDK)/drivers/bus/fslmc CFLAGS += -I$(RTE_SDK)/drivers/bus/fslmc/mc CFLAGS += -I$(RTE_SDK)/drivers/bus/fslmc/qbman/include CFLAGS += -I$(RTE_SDK)/lib/librte_eal/linuxapp/eal +CFLAGS += -I$(RTE_SDK)/lib/librte_eal/common # versioning export map EXPORT_MAP := rte_bus_fslmc_version.map diff --git a/drivers/bus/fslmc/fslmc_vfio.c b/drivers/bus/fslmc/fslmc_vfio.c index 3de5238..b2413c2 100644 --- a/drivers/bus/fslmc/fslmc_vfio.c +++ b/drivers/bus/fslmc/fslmc_vfio.c @@ -46,6 +46,7 @@ #include #include +#include #include #include #include @@ -335,36 +336,107 @@ static int64_t vfio_map_mcp_obj(struct fslmc_vfio_group *group, char *mcp_obj) #define IRQ_SET_BUF_LEN (sizeof(struct vfio_irq_set) + sizeof(int)) -int rte_dpaa2_intr_enable(struct rte_intr_handle *intr_handle, - uint32_t index) +int rte_dpaa2_intr_enable(struct rte_intr_handle *intr_handle, int index) { - struct vfio_irq_set *irq_set; + int len, ret; char irq_set_buf[IRQ_SET_BUF_LEN]; - int *fd_ptr, fd, ret; + struct vfio_irq_set *irq_set; + int *fd_ptr; + + len = sizeof(irq_set_buf); - /* Prepare vfio_irq_set structure and SET the IRQ in VFIO */ - /* Give the eventfd to VFIO */ - fd = eventfd(0, 0); irq_set = (struct vfio_irq_set *)irq_set_buf; - irq_set->argsz = sizeof(irq_set_buf); + irq_set->argsz = len; irq_set->count = 1; - irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | - VFIO_IRQ_SET_ACTION_TRIGGER; + irq_set->flags = + VFIO_IRQ_SET_DATA_EVENTFD | VFIO_IRQ_SET_ACTION_TRIGGER; irq_set->index = index; irq_set->start = 0; fd_ptr = (int *)&irq_set->data; - *fd_ptr = fd; + *fd_ptr = intr_handle->fd; ret = ioctl(intr_handle->vfio_dev_fd, VFIO_DEVICE_SET_IRQS, irq_set); - if (ret < 0) { - FSLMC_VFIO_LOG(ERR, "Unable to set IRQ in VFIO, ret: %d\n", - ret); - return -1; + if (ret) { + RTE_LOG(ERR, EAL, "Error:dpaa2 SET IRQs fd=%d, err = %d(%s)\n", + intr_handle->fd, errno, strerror(errno)); + return ret; } - /* Set the FD and update the flags */ - intr_handle->fd = fd; - return 0; + return ret; +} + +int rte_dpaa2_intr_disable(struct rte_intr_handle *intr_handle, int index) +{ + struct vfio_irq_set *irq_set; + char irq_set_buf[IRQ_SET_BUF_LEN]; + int len, ret; + + len = sizeof(struct vfio_irq_set); + + irq_set = (struct vfio_irq_set *)irq_set_buf; + irq_set->argsz = len; + irq_set->flags = VFIO_IRQ_SET_DATA_NONE | VFIO_IRQ_SET_ACTION_TRIGGER; + irq_set->index = index; + irq_set->start = 0; + irq_set->count = 0; + + ret = ioctl(intr_handle->vfio_dev_fd, VFIO_DEVICE_SET_IRQS, irq_set); + if (ret) + RTE_LOG(ERR, EAL, + "Error disabling dpaa2 interrupts for fd %d\n", + intr_handle->fd); + + return ret; +} + +/* set up interrupt support (but not enable interrupts) */ +int +rte_dpaa2_vfio_setup_intr(struct rte_intr_handle *intr_handle, + int vfio_dev_fd, + int num_irqs) +{ + int i, ret; + + /* start from MSI-X interrupt type */ + for (i = 0; i < num_irqs; i++) { + struct vfio_irq_info irq_info = { .argsz = sizeof(irq_info) }; + int fd = -1; + + irq_info.index = i; + + ret = ioctl(vfio_dev_fd, VFIO_DEVICE_GET_IRQ_INFO, &irq_info); + if (ret < 0) { + FSLMC_VFIO_LOG(ERR, + "cannot get IRQ(%d) info, error %i (%s)", + i, errno, strerror(errno)); + return -1; + } + + /* if this vector cannot be used with eventfd, + * fail if we explicitly + * specified interrupt type, otherwise continue + */ + if ((irq_info.flags & VFIO_IRQ_INFO_EVENTFD) == 0) + continue; + + /* set up an eventfd for interrupts */ + fd = eventfd(0, EFD_NONBLOCK | EFD_CLOEXEC); + if (fd < 0) { + FSLMC_VFIO_LOG(ERR, + "cannot set up eventfd, error %i (%s)\n", + errno, strerror(errno)); + return -1; + } + + intr_handle->fd = fd; + intr_handle->type = RTE_INTR_HANDLE_VFIO_MSI; + intr_handle->vfio_dev_fd = vfio_dev_fd; + + return 0; + } + + /* if we're here, we haven't found a suitable interrupt vector */ + return -1; } /* diff --git a/drivers/bus/fslmc/fslmc_vfio.h b/drivers/bus/fslmc/fslmc_vfio.h index edb86d0..5470a41 100644 --- a/drivers/bus/fslmc/fslmc_vfio.h +++ b/drivers/bus/fslmc/fslmc_vfio.h @@ -64,8 +64,12 @@ typedef struct fslmc_vfio_container { struct fslmc_vfio_group *group; } fslmc_vfio_container; -int rte_dpaa2_intr_enable(struct rte_intr_handle *intr_handle, - uint32_t index); +int rte_dpaa2_intr_enable(struct rte_intr_handle *intr_handle, int index); +int rte_dpaa2_intr_disable(struct rte_intr_handle *intr_handle, int index); + +int rte_dpaa2_vfio_setup_intr(struct rte_intr_handle *intr_handle, + int vfio_dev_fd, + int num_irqs); int fslmc_vfio_setup_group(void); int fslmc_vfio_process_group(void); diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c index 8db1f6c..ff41ce4 100644 --- a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c +++ b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c @@ -440,7 +440,6 @@ dpaa2_create_dpio_device(int vdev_fd, { struct dpaa2_dpio_dev *dpio_dev; struct vfio_region_info reg_info = { .argsz = sizeof(reg_info)}; - int vfio_dev_fd; if (obj_info->num_regions < NUM_DPIO_REGIONS) { PMD_INIT_LOG(ERR, "ERROR, Not sufficient number " @@ -457,14 +456,12 @@ dpaa2_create_dpio_device(int vdev_fd, dpio_dev->dpio = NULL; dpio_dev->hw_id = object_id; - dpio_dev->intr_handle.vfio_dev_fd = vdev_fd; rte_atomic16_init(&dpio_dev->ref_count); /* Using single portal for all devices */ dpio_dev->mc_portal = rte_mcp_ptr_list[MC_PORTAL_INDEX]; reg_info.index = 0; - vfio_dev_fd = dpio_dev->intr_handle.vfio_dev_fd; - if (ioctl(vfio_dev_fd, VFIO_DEVICE_GET_REGION_INFO, ®_info)) { + if (ioctl(vdev_fd, VFIO_DEVICE_GET_REGION_INFO, ®_info)) { PMD_INIT_LOG(ERR, "vfio: error getting region info\n"); rte_free(dpio_dev); return -1; @@ -473,10 +470,10 @@ dpaa2_create_dpio_device(int vdev_fd, dpio_dev->ce_size = reg_info.size; dpio_dev->qbman_portal_ce_paddr = (uint64_t)mmap(NULL, reg_info.size, PROT_WRITE | PROT_READ, MAP_SHARED, - vfio_dev_fd, reg_info.offset); + vdev_fd, reg_info.offset); reg_info.index = 1; - if (ioctl(vfio_dev_fd, VFIO_DEVICE_GET_REGION_INFO, ®_info)) { + if (ioctl(vdev_fd, VFIO_DEVICE_GET_REGION_INFO, ®_info)) { PMD_INIT_LOG(ERR, "vfio: error getting region info\n"); rte_free(dpio_dev); return -1; @@ -485,7 +482,7 @@ dpaa2_create_dpio_device(int vdev_fd, dpio_dev->ci_size = reg_info.size; dpio_dev->qbman_portal_ci_paddr = (uint64_t)mmap(NULL, reg_info.size, PROT_WRITE | PROT_READ, MAP_SHARED, - vfio_dev_fd, reg_info.offset); + vdev_fd, reg_info.offset); if (configure_dpio_qbman_swp(dpio_dev)) { PMD_INIT_LOG(ERR, @@ -497,6 +494,13 @@ dpaa2_create_dpio_device(int vdev_fd, io_space_count++; dpio_dev->index = io_space_count; + + if (rte_dpaa2_vfio_setup_intr(&dpio_dev->intr_handle, vdev_fd, 1)) { + PMD_INIT_LOG(ERR, "Fail to setup interrupt for %d\n", + dpio_dev->hw_id); + rte_free(dpio_dev); + } + TAILQ_INSERT_TAIL(&dpio_dev_list, dpio_dev, next); PMD_INIT_LOG(DEBUG, "DPAA2: Added [dpio.%d]", object_id); diff --git a/drivers/bus/fslmc/rte_bus_fslmc_version.map b/drivers/bus/fslmc/rte_bus_fslmc_version.map index 7b25248..51a2ac6 100644 --- a/drivers/bus/fslmc/rte_bus_fslmc_version.map +++ b/drivers/bus/fslmc/rte_bus_fslmc_version.map @@ -85,5 +85,7 @@ DPDK_17.11 { dpaa2_dpbp_supported; rte_dpaa2_dev_type; + rte_dpaa2_intr_disable; + rte_dpaa2_intr_enable; } DPDK_17.08; From patchwork Sat Sep 16 10:52:28 2017 Content-Type: text/plain; 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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR03MB2694 Subject: [dpdk-dev] [PATCH v3 14/27] net/dpaa2: add support for link status event X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Signed-off-by: Hemant Agrawal --- doc/guides/nics/features/dpaa2.ini | 1 + drivers/net/dpaa2/dpaa2_ethdev.c | 123 +++++++++++++++++++ drivers/net/dpaa2/mc/dpni.c | 233 ++++++++++++++++++++++++++++++++++++ drivers/net/dpaa2/mc/fsl_dpni.h | 49 ++++++++ drivers/net/dpaa2/mc/fsl_dpni_cmd.h | 50 ++++++++ 5 files changed, 456 insertions(+) -- 2.7.4 diff --git a/doc/guides/nics/features/dpaa2.ini b/doc/guides/nics/features/dpaa2.ini index 146e087..ba4321c 100644 --- a/doc/guides/nics/features/dpaa2.ini +++ b/doc/guides/nics/features/dpaa2.ini @@ -6,6 +6,7 @@ [Features] Speed capabilities = P Link status = Y +Link status event = Y Queue start/stop = Y Jumbo frame = Y MTU update = Y diff --git a/drivers/net/dpaa2/dpaa2_ethdev.c b/drivers/net/dpaa2/dpaa2_ethdev.c index d7950a5..72c9e67 100644 --- a/drivers/net/dpaa2/dpaa2_ethdev.c +++ b/drivers/net/dpaa2/dpaa2_ethdev.c @@ -54,6 +54,8 @@ static struct rte_dpaa2_driver rte_dpaa2_pmd; static int dpaa2_dev_uninit(struct rte_eth_dev *eth_dev); +static int dpaa2_dev_link_update(struct rte_eth_dev *dev, + int wait_to_complete); static int dpaa2_dev_set_link_up(struct rte_eth_dev *dev); static int dpaa2_dev_set_link_down(struct rte_eth_dev *dev); static int dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); @@ -344,6 +346,10 @@ dpaa2_eth_dev_configure(struct rte_eth_dev *dev) return ret; } } + + /* update the current status */ + dpaa2_dev_link_update(dev, 0); + return 0; } @@ -556,9 +562,87 @@ dpaa2_supported_ptypes_get(struct rte_eth_dev *dev) return NULL; } +/** + * Dpaa2 link Interrupt handler + * + * @param param + * The address of parameter (struct rte_eth_dev *) regsitered before. + * + * @return + * void + */ +static void +dpaa2_interrupt_handler(void *param) +{ + struct rte_eth_dev *dev = param; + struct dpaa2_dev_priv *priv = dev->data->dev_private; + struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; + int ret; + int irq_index = DPNI_IRQ_INDEX; + unsigned int status = 0, clear = 0; + + PMD_INIT_FUNC_TRACE(); + + if (dpni == NULL) { + RTE_LOG(ERR, PMD, "dpni is NULL"); + return; + } + + ret = dpni_get_irq_status(dpni, CMD_PRI_LOW, priv->token, + irq_index, &status); + if (unlikely(ret)) { + RTE_LOG(ERR, PMD, "Can't get irq status (err %d)", ret); + clear = 0xffffffff; + goto out; + } + + if (status & DPNI_IRQ_EVENT_LINK_CHANGED) { + clear = DPNI_IRQ_EVENT_LINK_CHANGED; + dpaa2_dev_link_update(dev, 0); + /* calling all the apps registered for link status event */ + _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, + NULL, NULL); + } +out: + ret = dpni_clear_irq_status(dpni, CMD_PRI_LOW, priv->token, + irq_index, clear); + if (unlikely(ret)) + RTE_LOG(ERR, PMD, "Can't clear irq status (err %d)", ret); +} + +static int +dpaa2_eth_setup_irqs(struct rte_eth_dev *dev, int enable) +{ + int err = 0; + struct dpaa2_dev_priv *priv = dev->data->dev_private; + struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; + int irq_index = DPNI_IRQ_INDEX; + unsigned int mask = DPNI_IRQ_EVENT_LINK_CHANGED; + + PMD_INIT_FUNC_TRACE(); + + err = dpni_set_irq_mask(dpni, CMD_PRI_LOW, priv->token, + irq_index, mask); + if (err < 0) { + PMD_INIT_LOG(ERR, "Error: dpni_set_irq_mask():%d (%s)", err, + strerror(-err)); + return err; + } + + err = dpni_set_irq_enable(dpni, CMD_PRI_LOW, priv->token, + irq_index, enable); + if (err < 0) + PMD_INIT_LOG(ERR, "Error: dpni_set_irq_enable():%d (%s)", err, + strerror(-err)); + + return err; +} + static int dpaa2_dev_start(struct rte_eth_dev *dev) { + struct rte_device *rdev = dev->device; + struct rte_dpaa2_device *dpaa2_dev; struct rte_eth_dev_data *data = dev->data; struct dpaa2_dev_priv *priv = data->dev_private; struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; @@ -568,6 +652,10 @@ dpaa2_dev_start(struct rte_eth_dev *dev) struct dpni_queue_id qid; struct dpaa2_queue *dpaa2_q; int ret, i; + struct rte_intr_handle *intr_handle; + + dpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device); + intr_handle = &dpaa2_dev->intr_handle; PMD_INIT_FUNC_TRACE(); @@ -647,6 +735,24 @@ dpaa2_dev_start(struct rte_eth_dev *dev) if (priv->max_vlan_filters) dpaa2_vlan_offload_set(dev, ETH_VLAN_FILTER_MASK); + /* if the interrupts were configured on this devices*/ + if (intr_handle && (intr_handle->fd) && + (dev->data->dev_conf.intr_conf.lsc != 0)) { + /* Registering LSC interrupt handler */ + rte_intr_callback_register(intr_handle, + dpaa2_interrupt_handler, + (void *)dev); + + /* enable vfio intr/eventfd mapping + * Interrupt index 0 is required, so we can not use + * rte_intr_enable. + */ + rte_dpaa2_intr_enable(intr_handle, DPNI_IRQ_INDEX); + + /* enable dpni_irqs */ + dpaa2_eth_setup_irqs(dev, 1); + } + return 0; } @@ -661,9 +767,25 @@ dpaa2_dev_stop(struct rte_eth_dev *dev) struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; int ret; struct rte_eth_link link; + struct rte_intr_handle *intr_handle = dev->intr_handle; PMD_INIT_FUNC_TRACE(); + /* reset interrupt callback */ + if (intr_handle && (intr_handle->fd) && + (dev->data->dev_conf.intr_conf.lsc != 0)) { + /*disable dpni irqs */ + dpaa2_eth_setup_irqs(dev, 0); + + /* disable vfio intr before callback unregister */ + rte_dpaa2_intr_disable(intr_handle, DPNI_IRQ_INDEX); + + /* Unregistering LSC interrupt handler */ + rte_intr_callback_unregister(intr_handle, + dpaa2_interrupt_handler, + (void *)dev); + } + dpaa2_dev_set_link_down(dev); ret = dpni_disable(dpni, CMD_PRI_LOW, priv->token); @@ -1458,6 +1580,7 @@ dpaa2_dev_init(struct rte_eth_dev *eth_dev) } eth_dev->dev_ops = &dpaa2_ethdev_ops; + eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC; eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx; eth_dev->tx_pkt_burst = dpaa2_dev_tx; diff --git a/drivers/net/dpaa2/mc/dpni.c b/drivers/net/dpaa2/mc/dpni.c index f95e669..6f671fe 100644 --- a/drivers/net/dpaa2/mc/dpni.c +++ b/drivers/net/dpaa2/mc/dpni.c @@ -351,6 +351,239 @@ int dpni_reset(struct fsl_mc_io *mc_io, } /** + * dpni_set_irq_enable() - Set overall interrupt state. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @irq_index: The interrupt index to configure + * @en: Interrupt state: - enable = 1, disable = 0 + * + * Allows GPP software to control when interrupts are generated. + * Each interrupt can have up to 32 causes. The enable/disable control's the + * overall interrupt state. if the interrupt is disabled no causes will cause + * an interrupt. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_set_irq_enable(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + uint8_t irq_index, + uint8_t en) +{ + struct mc_command cmd = { 0 }; + struct dpni_cmd_set_irq_enable *cmd_params; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_IRQ_ENABLE, + cmd_flags, + token); + cmd_params = (struct dpni_cmd_set_irq_enable *)cmd.params; + dpni_set_field(cmd_params->enable, ENABLE, en); + cmd_params->irq_index = irq_index; + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +/** + * dpni_get_irq_enable() - Get overall interrupt state + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @irq_index: The interrupt index to configure + * @en: Returned interrupt state - enable = 1, disable = 0 + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_get_irq_enable(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + uint8_t irq_index, + uint8_t *en) +{ + struct mc_command cmd = { 0 }; + struct dpni_cmd_get_irq_enable *cmd_params; + struct dpni_rsp_get_irq_enable *rsp_params; + + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_IRQ_ENABLE, + cmd_flags, + token); + cmd_params = (struct dpni_cmd_get_irq_enable *)cmd.params; + cmd_params->irq_index = irq_index; + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + rsp_params = (struct dpni_rsp_get_irq_enable *)cmd.params; + *en = dpni_get_field(rsp_params->enabled, ENABLE); + + return 0; +} + +/** + * dpni_set_irq_mask() - Set interrupt mask. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @irq_index: The interrupt index to configure + * @mask: Event mask to trigger interrupt; + * each bit: + * 0 = ignore event + * 1 = consider event for asserting IRQ + * + * Every interrupt can have up to 32 causes and the interrupt model supports + * masking/unmasking each cause independently + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_set_irq_mask(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + uint8_t irq_index, + uint32_t mask) +{ + struct mc_command cmd = { 0 }; + struct dpni_cmd_set_irq_mask *cmd_params; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_IRQ_MASK, + cmd_flags, + token); + cmd_params = (struct dpni_cmd_set_irq_mask *)cmd.params; + cmd_params->mask = cpu_to_le32(mask); + cmd_params->irq_index = irq_index; + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +/** + * dpni_get_irq_mask() - Get interrupt mask. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @irq_index: The interrupt index to configure + * @mask: Returned event mask to trigger interrupt + * + * Every interrupt can have up to 32 causes and the interrupt model supports + * masking/unmasking each cause independently + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_get_irq_mask(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + uint8_t irq_index, + uint32_t *mask) +{ + struct mc_command cmd = { 0 }; + struct dpni_cmd_get_irq_mask *cmd_params; + struct dpni_rsp_get_irq_mask *rsp_params; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_IRQ_MASK, + cmd_flags, + token); + cmd_params = (struct dpni_cmd_get_irq_mask *)cmd.params; + cmd_params->irq_index = irq_index; + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + rsp_params = (struct dpni_rsp_get_irq_mask *)cmd.params; + *mask = le32_to_cpu(rsp_params->mask); + + return 0; +} + +/** + * dpni_get_irq_status() - Get the current status of any pending interrupts. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @irq_index: The interrupt index to configure + * @status: Returned interrupts status - one bit per cause: + * 0 = no interrupt pending + * 1 = interrupt pending + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_get_irq_status(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + uint8_t irq_index, + uint32_t *status) +{ + struct mc_command cmd = { 0 }; + struct dpni_cmd_get_irq_status *cmd_params; + struct dpni_rsp_get_irq_status *rsp_params; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_IRQ_STATUS, + cmd_flags, + token); + cmd_params = (struct dpni_cmd_get_irq_status *)cmd.params; + cmd_params->status = cpu_to_le32(*status); + cmd_params->irq_index = irq_index; + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + rsp_params = (struct dpni_rsp_get_irq_status *)cmd.params; + *status = le32_to_cpu(rsp_params->status); + + return 0; +} + +/** + * dpni_clear_irq_status() - Clear a pending interrupt's status + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @irq_index: The interrupt index to configure + * @status: bits to clear (W1C) - one bit per cause: + * 0 = don't change + * 1 = clear status bit + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_clear_irq_status(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + uint8_t irq_index, + uint32_t status) +{ + struct mc_command cmd = { 0 }; + struct dpni_cmd_clear_irq_status *cmd_params; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPNI_CMDID_CLEAR_IRQ_STATUS, + cmd_flags, + token); + cmd_params = (struct dpni_cmd_clear_irq_status *)cmd.params; + cmd_params->irq_index = irq_index; + cmd_params->status = cpu_to_le32(status); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +/** * dpni_get_attributes() - Retrieve DPNI attributes. * @mc_io: Pointer to MC portal's I/O object * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' diff --git a/drivers/net/dpaa2/mc/fsl_dpni.h b/drivers/net/dpaa2/mc/fsl_dpni.h index 092d3b3..5227ea1 100644 --- a/drivers/net/dpaa2/mc/fsl_dpni.h +++ b/drivers/net/dpaa2/mc/fsl_dpni.h @@ -247,6 +247,55 @@ int dpni_reset(struct fsl_mc_io *mc_io, uint16_t token); /** + * DPNI IRQ Index and Events + */ + +/** + * IRQ index + */ +#define DPNI_IRQ_INDEX 0 +/** + * IRQ event - indicates a change in link state + */ +#define DPNI_IRQ_EVENT_LINK_CHANGED 0x00000001 + +int dpni_set_irq_enable(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + uint8_t irq_index, + uint8_t en); + +int dpni_get_irq_enable(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + uint8_t irq_index, + uint8_t *en); + +int dpni_set_irq_mask(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + uint8_t irq_index, + uint32_t mask); + +int dpni_get_irq_mask(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + uint8_t irq_index, + uint32_t *mask); + +int dpni_get_irq_status(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + uint8_t irq_index, + uint32_t *status); + +int dpni_clear_irq_status(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + uint8_t irq_index, + uint32_t status); + +/** * struct dpni_attr - Structure representing DPNI attributes * @options: Any combination of the following options: * DPNI_OPT_TX_FRM_RELEASE diff --git a/drivers/net/dpaa2/mc/fsl_dpni_cmd.h b/drivers/net/dpaa2/mc/fsl_dpni_cmd.h index 81226aa..1a48332 100644 --- a/drivers/net/dpaa2/mc/fsl_dpni_cmd.h +++ b/drivers/net/dpaa2/mc/fsl_dpni_cmd.h @@ -64,6 +64,13 @@ #define DPNI_CMDID_RESET DPNI_CMD(0x005) #define DPNI_CMDID_IS_ENABLED DPNI_CMD(0x006) +#define DPNI_CMDID_SET_IRQ_ENABLE DPNI_CMD(0x012) +#define DPNI_CMDID_GET_IRQ_ENABLE DPNI_CMD(0x013) +#define DPNI_CMDID_SET_IRQ_MASK DPNI_CMD(0x014) +#define DPNI_CMDID_GET_IRQ_MASK DPNI_CMD(0x015) +#define DPNI_CMDID_GET_IRQ_STATUS DPNI_CMD(0x016) +#define DPNI_CMDID_CLEAR_IRQ_STATUS DPNI_CMD(0x017) + #define DPNI_CMDID_SET_POOLS DPNI_CMD_V2(0x200) #define DPNI_CMDID_SET_ERRORS_BEHAVIOR DPNI_CMD(0x20B) @@ -169,6 +176,49 @@ struct dpni_rsp_is_enabled { uint8_t enabled; }; +struct dpni_cmd_set_irq_enable { + uint8_t enable; + uint8_t pad[3]; + uint8_t irq_index; +}; + +struct dpni_cmd_get_irq_enable { + uint32_t pad; + uint8_t irq_index; +}; + +struct dpni_rsp_get_irq_enable { + uint8_t enabled; +}; + +struct dpni_cmd_set_irq_mask { + uint32_t mask; + uint8_t irq_index; +}; + +struct dpni_cmd_get_irq_mask { + uint32_t pad; + uint8_t irq_index; +}; + +struct dpni_rsp_get_irq_mask { + uint32_t mask; +}; + +struct dpni_cmd_get_irq_status { + uint32_t status; + uint8_t irq_index; +}; + +struct dpni_rsp_get_irq_status { + uint32_t status; +}; + +struct dpni_cmd_clear_irq_status { + uint32_t status; + uint8_t irq_index; +}; + struct dpni_rsp_get_attr { /* response word 0 */ uint32_t options; From patchwork Sat Sep 16 10:52:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemant Agrawal X-Patchwork-Id: 112797 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp1616570qgf; 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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR03MB2693 Subject: [dpdk-dev] [PATCH v3 15/27] bus/fslmc: enable link status interrupt X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Signed-off-by: Hemant Agrawal --- drivers/bus/fslmc/fslmc_vfio.c | 4 ++++ 1 file changed, 4 insertions(+) -- 2.7.4 diff --git a/drivers/bus/fslmc/fslmc_vfio.c b/drivers/bus/fslmc/fslmc_vfio.c index b2413c2..de08e1f 100644 --- a/drivers/bus/fslmc/fslmc_vfio.c +++ b/drivers/bus/fslmc/fslmc_vfio.c @@ -464,6 +464,10 @@ fslmc_process_iodevices(struct rte_dpaa2_device *dev) } switch (dev->dev_type) { + case DPAA2_ETH: + rte_dpaa2_vfio_setup_intr(&dev->intr_handle, dev_fd, + device_info.num_irqs); + break; case DPAA2_CON: case DPAA2_IO: case DPAA2_CI: From patchwork Sat Sep 16 10:52:30 2017 Content-Type: text/plain; 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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR03MB2701 Subject: [dpdk-dev] [PATCH v3 16/27] net/dpaa2: check physical link state on up cmd X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Signed-off-by: Hemant Agrawal --- drivers/net/dpaa2/dpaa2_ethdev.c | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-) -- 2.7.4 diff --git a/drivers/net/dpaa2/dpaa2_ethdev.c b/drivers/net/dpaa2/dpaa2_ethdev.c index 72c9e67..d5fa644 100644 --- a/drivers/net/dpaa2/dpaa2_ethdev.c +++ b/drivers/net/dpaa2/dpaa2_ethdev.c @@ -666,7 +666,7 @@ dpaa2_dev_start(struct rte_eth_dev *dev) return ret; } - /* Power up the phy. Needed to make the link go Up */ + /* Power up the phy. Needed to make the link go UP */ dpaa2_dev_set_link_up(dev); ret = dpni_get_qdid(dpni, CMD_PRI_LOW, priv->token, @@ -1137,8 +1137,6 @@ dpaa2_dev_link_update(struct rte_eth_dev *dev, struct rte_eth_link link, old; struct dpni_link_state state = {0}; - PMD_INIT_FUNC_TRACE(); - if (dpni == NULL) { RTE_LOG(ERR, PMD, "dpni is NULL\n"); return 0; @@ -1171,7 +1169,7 @@ dpaa2_dev_link_update(struct rte_eth_dev *dev, if (link.link_status) PMD_DRV_LOG(INFO, "Port %d Link is Up\n", dev->data->port_id); else - PMD_DRV_LOG(INFO, "Port %d Link is Down\n", dev->data->port_id); + PMD_DRV_LOG(INFO, "Port %d Link is Down", dev->data->port_id); return 0; } @@ -1186,8 +1184,7 @@ dpaa2_dev_set_link_up(struct rte_eth_dev *dev) struct dpaa2_dev_priv *priv; struct fsl_mc_io *dpni; int en = 0; - - PMD_INIT_FUNC_TRACE(); + struct dpni_link_state state = {0}; priv = dev->data->dev_private; dpni = (struct fsl_mc_io *)priv->hw; @@ -1213,11 +1210,21 @@ dpaa2_dev_set_link_up(struct rte_eth_dev *dev) return -EINVAL; } } + ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state); + if (ret < 0) { + RTE_LOG(ERR, PMD, "error: dpni_get_link_state %d\n", ret); + return -1; + } + /* changing tx burst function to start enqueues */ dev->tx_pkt_burst = dpaa2_dev_tx; - dev->data->dev_link.link_status = 1; + dev->data->dev_link.link_status = state.up; - PMD_DRV_LOG(INFO, "Port %d Link UP successful", dev->data->port_id); + if (state.up) + PMD_DRV_LOG(INFO, "Port %d Link is set as UP", + dev->data->port_id); + else + PMD_DRV_LOG(INFO, "Port %d Link is DOWN", dev->data->port_id); return ret; } From patchwork Sat Sep 16 10:52:31 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemant Agrawal X-Patchwork-Id: 112799 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp1616887qgf; Sat, 16 Sep 2017 03:57:07 -0700 (PDT) X-Google-Smtp-Source: AOwi7QADp9o3YFG9l1KmZIAzptDzdZCRr1OeuqvBzfiQfieiLVV55b/bbsTHERb58V2I1IYL59CR X-Received: by 10.223.151.55 with SMTP id r52mr4418457wrb.69.1505559427493; Sat, 16 Sep 2017 03:57:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505559427; cv=none; d=google.com; s=arc-20160816; b=ygFtAos/AGtY7qZ3AAGCBA9GKYTjdjWDtEyVaF202QPcI6qF2m85l7OlBQHR56hFC5 njc0kwtq1bqRbA/9n3JTXWoBUwqK5ngwztJRBm5SSjwjcn2yOrtD3imED1UiqT23201V pmmkGBkRsqgDNBKoVtBD4XpzBg3+3mdPFVhcJZQZ/eMwUDqikZCBCcz7zH5ulM4u8Ups auB7oHIwM+q6pmKbsELT6nL25e1gXE+ts/TXI+97zunS9XcLhBM4KrB+2k8m2JUWTWdx DZ0+wZ7tXybt6G0KyrZ8stdJwpmH//TW7/BBw9yw5jn5LxjlqqowhdGFSFmodu6nxf1Q rnpw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:spamdiagnosticmetadata :spamdiagnosticoutput:mime-version:references:in-reply-to:message-id :date:cc:to:from:arc-authentication-results; bh=IxT5a1UVQqm0AJUenS4EQ0LiiRDAzPCXm9fJTGSnNtQ=; b=HS3cmKXidtzqdCNiEODtOB6Np9D2NjkT+lJItiOtu12JL23YgKx8D32BeoB7Q8r48V PBqBiCvcxXJYTNZUpvx41l58iTxRvTRrStP3daQlpHqyJ31NFIBxfOI+lTDNmMi826LD ITKiliKbKNILSKISVfwpdZRQ+ZTRR/SjqwUYXy+D6OefKcKRxCgBsJCnMXE7gPcWqUtl jpqXlocxtrDjsNGncanYC6iPe/AtLfouXrYUR2tKc4jQAW9SacIyL26fJTqEhIZrkieB H4iQ1MVpHVwx6JBWpYTSQAecoknONxZRt6VbDehkbb2q+KDW2aPJiHaCD7IJbMlw+FwC k/gw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from dpdk.org (dpdk.org. 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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR03MB2699 Subject: [dpdk-dev] [PATCH v3 17/27] net/dpaa2: improve error and logs for flow distribution X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Signed-off-by: Hemant Agrawal --- drivers/net/dpaa2/base/dpaa2_hw_dpni.c | 39 +++++++++++++++++++++------------- 1 file changed, 24 insertions(+), 15 deletions(-) -- 2.7.4 diff --git a/drivers/net/dpaa2/base/dpaa2_hw_dpni.c b/drivers/net/dpaa2/base/dpaa2_hw_dpni.c index 1269dd2..ca8a6f7 100644 --- a/drivers/net/dpaa2/base/dpaa2_hw_dpni.c +++ b/drivers/net/dpaa2/base/dpaa2_hw_dpni.c @@ -49,7 +49,7 @@ #include "../dpaa2_ethdev.h" -static void +static int dpaa2_distset_to_dpkg_profile_cfg( uint32_t req_dist_set, struct dpkg_profile_cfg *kg_cfg); @@ -68,20 +68,26 @@ dpaa2_setup_flow_dist(struct rte_eth_dev *eth_dev, p_params = rte_malloc( NULL, DIST_PARAM_IOVA_SIZE, RTE_CACHE_LINE_SIZE); if (!p_params) { - RTE_LOG(ERR, PMD, "Memory unavaialble\n"); + PMD_INIT_LOG(ERR, "Memory unavailable"); return -ENOMEM; } memset(p_params, 0, DIST_PARAM_IOVA_SIZE); memset(&tc_cfg, 0, sizeof(struct dpni_rx_tc_dist_cfg)); - dpaa2_distset_to_dpkg_profile_cfg(req_dist_set, &kg_cfg); + ret = dpaa2_distset_to_dpkg_profile_cfg(req_dist_set, &kg_cfg); + if (ret) { + PMD_INIT_LOG(ERR, "given rss_hf (%x) not supported", + req_dist_set); + rte_free(p_params); + return ret; + } tc_cfg.key_cfg_iova = (uint64_t)(DPAA2_VADDR_TO_IOVA(p_params)); tc_cfg.dist_size = eth_dev->data->nb_rx_queues; tc_cfg.dist_mode = DPNI_DIST_MODE_HASH; ret = dpkg_prepare_key_cfg(&kg_cfg, p_params); if (ret) { - RTE_LOG(ERR, PMD, "Unable to prepare extract parameters\n"); + PMD_INIT_LOG(ERR, "Unable to prepare extract parameters"); rte_free(p_params); return ret; } @@ -90,9 +96,9 @@ dpaa2_setup_flow_dist(struct rte_eth_dev *eth_dev, &tc_cfg); rte_free(p_params); if (ret) { - RTE_LOG(ERR, PMD, - "Setting distribution for Rx failed with err: %d\n", - ret); + PMD_INIT_LOG(ERR, + "Setting distribution for Rx failed with err: %d", + ret); return ret; } @@ -113,7 +119,7 @@ int dpaa2_remove_flow_dist( p_params = rte_malloc( NULL, DIST_PARAM_IOVA_SIZE, RTE_CACHE_LINE_SIZE); if (!p_params) { - RTE_LOG(ERR, PMD, "Memory unavaialble\n"); + PMD_INIT_LOG(ERR, "Memory unavailable"); return -ENOMEM; } memset(p_params, 0, DIST_PARAM_IOVA_SIZE); @@ -125,7 +131,7 @@ int dpaa2_remove_flow_dist( ret = dpkg_prepare_key_cfg(&kg_cfg, p_params); if (ret) { - RTE_LOG(ERR, PMD, "Unable to prepare extract parameters\n"); + PMD_INIT_LOG(ERR, "Unable to prepare extract parameters"); rte_free(p_params); return ret; } @@ -134,13 +140,13 @@ int dpaa2_remove_flow_dist( &tc_cfg); rte_free(p_params); if (ret) - RTE_LOG(ERR, PMD, - "Setting distribution for Rx failed with err: %d\n", - ret); + PMD_INIT_LOG(ERR, + "Setting distribution for Rx failed with err:%d", + ret); return ret; } -static void +static int dpaa2_distset_to_dpkg_profile_cfg( uint32_t req_dist_set, struct dpkg_profile_cfg *kg_cfg) @@ -276,14 +282,17 @@ dpaa2_distset_to_dpkg_profile_cfg( break; default: - PMD_DRV_LOG(WARNING, "Bad flow distribution" - " option %x\n", dist_field); + PMD_INIT_LOG(WARNING, + "Unsupported flow dist option %x", + dist_field); + return -EINVAL; } } req_dist_set = req_dist_set >> 1; loop++; } kg_cfg->num_extracts = i; + return 0; } int From patchwork Sat Sep 16 10:52:32 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemant Agrawal X-Patchwork-Id: 112803 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp1617523qgf; Sat, 16 Sep 2017 03:58:04 -0700 (PDT) X-Google-Smtp-Source: ADKCNb5Kbda0WdCYtz9MX38kwpDd3mzi4yUeU+WUWFXtg94j5+d8MAJ4q91CgKmc586fq1sq/W7i X-Received: by 10.223.132.163 with SMTP id 32mr21873481wrg.267.1505559484152; Sat, 16 Sep 2017 03:58:04 -0700 (PDT) ARC-Seal: i=1; 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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO2PR03MB2359 Subject: [dpdk-dev] [PATCH v3 18/27] net/dpaa2: increase the dist param to 64 bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Signed-off-by: Hemant Agrawal --- drivers/net/dpaa2/base/dpaa2_hw_dpni.c | 8 ++++---- drivers/net/dpaa2/dpaa2_ethdev.h | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) -- 2.7.4 diff --git a/drivers/net/dpaa2/base/dpaa2_hw_dpni.c b/drivers/net/dpaa2/base/dpaa2_hw_dpni.c index ca8a6f7..e3ab90a 100644 --- a/drivers/net/dpaa2/base/dpaa2_hw_dpni.c +++ b/drivers/net/dpaa2/base/dpaa2_hw_dpni.c @@ -51,12 +51,12 @@ static int dpaa2_distset_to_dpkg_profile_cfg( - uint32_t req_dist_set, + uint64_t req_dist_set, struct dpkg_profile_cfg *kg_cfg); int dpaa2_setup_flow_dist(struct rte_eth_dev *eth_dev, - uint32_t req_dist_set) + uint64_t req_dist_set) { struct dpaa2_dev_priv *priv = eth_dev->data->dev_private; struct fsl_mc_io *dpni = priv->hw; @@ -76,7 +76,7 @@ dpaa2_setup_flow_dist(struct rte_eth_dev *eth_dev, ret = dpaa2_distset_to_dpkg_profile_cfg(req_dist_set, &kg_cfg); if (ret) { - PMD_INIT_LOG(ERR, "given rss_hf (%x) not supported", + PMD_INIT_LOG(ERR, "given rss_hf (%lx) not supported", req_dist_set); rte_free(p_params); return ret; @@ -148,7 +148,7 @@ int dpaa2_remove_flow_dist( static int dpaa2_distset_to_dpkg_profile_cfg( - uint32_t req_dist_set, + uint64_t req_dist_set, struct dpkg_profile_cfg *kg_cfg) { uint32_t loop = 0, i = 0, dist_field = 0; diff --git a/drivers/net/dpaa2/dpaa2_ethdev.h b/drivers/net/dpaa2/dpaa2_ethdev.h index 6ee1a9f..7b14ae0 100644 --- a/drivers/net/dpaa2/dpaa2_ethdev.h +++ b/drivers/net/dpaa2/dpaa2_ethdev.h @@ -93,7 +93,7 @@ struct dpaa2_dev_priv { }; int dpaa2_setup_flow_dist(struct rte_eth_dev *eth_dev, - uint32_t req_dist_set); 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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR03MB2689 Subject: [dpdk-dev] [PATCH v3 19/27] net/dpaa2: remove RSS restriction with num of queues X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" DPAA2 HW does not have such restrictions. Signed-off-by: Hemant Agrawal --- drivers/net/dpaa2/dpaa2_ethdev.c | 11 ----------- 1 file changed, 11 deletions(-) -- 2.7.4 diff --git a/drivers/net/dpaa2/dpaa2_ethdev.c b/drivers/net/dpaa2/dpaa2_ethdev.c index d5fa644..dc24bed 100644 --- a/drivers/net/dpaa2/dpaa2_ethdev.c +++ b/drivers/net/dpaa2/dpaa2_ethdev.c @@ -326,18 +326,7 @@ dpaa2_eth_dev_configure(struct rte_eth_dev *dev) } } - /* Check for correct configuration */ - if (eth_conf->rxmode.mq_mode != ETH_MQ_RX_RSS && - data->nb_rx_queues > 1) { - PMD_INIT_LOG(ERR, "Distribution is not enabled, " - "but Rx queues more than 1\n"); - return -1; - } - if (eth_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) { - /* Return in case number of Rx queues is 1 */ - if (data->nb_rx_queues == 1) - return 0; ret = dpaa2_setup_flow_dist(dev, eth_conf->rx_adv_conf.rss_conf.rss_hf); if (ret) { From patchwork Sat Sep 16 10:52:34 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemant Agrawal X-Patchwork-Id: 112801 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp1617218qgf; Sat, 16 Sep 2017 03:57:37 -0700 (PDT) X-Google-Smtp-Source: ADKCNb7+ocRtFbdiW4Hx0ph3QrJb9wbKnNpna6b2GqpPh6DXOHUETXLEwHOqaLXmG4qj94Sk993T X-Received: by 10.223.136.119 with SMTP id e52mr21788836wre.225.1505559457616; Sat, 16 Sep 2017 03:57:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505559457; cv=none; d=google.com; s=arc-20160816; b=LjsU4Av+scnhLkxWxklzJRF9bxzzVI6Lov9VJeW+osIrqmErFmpOB33lRYGt75Ty4C zVdNePz5guCaVsjnZtVuwix+TzTuTPqgZj6UCtU04/qtuzWtHhQs5GpgEs1Z5tSRjkcA +5S9Kk5vTG2Lg8jPLirHjZrQAy+rRrrs+O5bY46znejgddVa3rv9Utx3evjAUTROUaii 3UBVcRSX4/a7qcGVbUVeOO878R8NJx1JzT8pBqoWa6//N7M62/nOnWKO67nqigcD2B6b oD8Ah9b5tOf8SQs9G6a4Uo8rT/vOHKHzrPtgjnWgFCin5N6lkKwiV9xw0ZfYGcNwUZfO w6+Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:spamdiagnosticmetadata :spamdiagnosticoutput:mime-version:references:in-reply-to:message-id :date:cc:to:from:arc-authentication-results; bh=xdugiRPXNGCciVDlOn8WZ1zBilO9raE8k0na215L79Y=; b=yI4qB5+AydlNjsb5vsQHoa+GhGmpJN9dvaE77UIZw+b/sj03KLcAuzVAjyKhkYz/6X TSj4QAxRIkfTRk19bw2RYKmPJcYyUQYAihUv+UCxfixSHCaLqxX8BiOrugIaMIbPmkJc f7yT+PlMLIPXn92xnxH3HwwWttyViX7vT0BWW78s3l9OIkcYivY/AXsDWr8DKZWWtnDy pYahoe/ybYsxKTgKzaaqxPigSG74rKzL4B+ZEhmkJxpPZCRpDuQxYORO/JBTBldTKmrk dpB39/urk+KvkZoJFafbhSRS57W5bB06c1EE7l91NzemH0tRT1qrl5+XFbX8rfjs7kNm Eh4A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from dpdk.org (dpdk.org. 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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR03MB2698 Subject: [dpdk-dev] [PATCH v3 20/27] net/dpaa2: add support for RSS hash update and get X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Signed-off-by: Hemant Agrawal --- drivers/net/dpaa2/dpaa2_ethdev.c | 42 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) -- 2.7.4 diff --git a/drivers/net/dpaa2/dpaa2_ethdev.c b/drivers/net/dpaa2/dpaa2_ethdev.c index dc24bed..643d882 100644 --- a/drivers/net/dpaa2/dpaa2_ethdev.c +++ b/drivers/net/dpaa2/dpaa2_ethdev.c @@ -1418,6 +1418,46 @@ dpaa2_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) return ret; } +static int +dpaa2_dev_rss_hash_update(struct rte_eth_dev *dev, + struct rte_eth_rss_conf *rss_conf) +{ + struct rte_eth_dev_data *data = dev->data; + struct rte_eth_conf *eth_conf = &data->dev_conf; + int ret; + + PMD_INIT_FUNC_TRACE(); + + if (rss_conf->rss_hf) { + ret = dpaa2_setup_flow_dist(dev, rss_conf->rss_hf); + if (ret) { + PMD_INIT_LOG(ERR, "unable to set flow dist"); + return ret; + } + } else { + ret = dpaa2_remove_flow_dist(dev, 0); + if (ret) { + PMD_INIT_LOG(ERR, "unable to remove flow dist"); + return ret; + } + } + eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf; + return 0; +} + +static int +dpaa2_dev_rss_hash_conf_get(struct rte_eth_dev *dev, + struct rte_eth_rss_conf *rss_conf) +{ + struct rte_eth_dev_data *data = dev->data; + struct rte_eth_conf *eth_conf = &data->dev_conf; + + /* dpaa2 does not support rss_key, so length should be 0*/ + rss_conf->rss_key_len = 0; + rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf; + return 0; +} + static struct eth_dev_ops dpaa2_ethdev_ops = { .dev_configure = dpaa2_eth_dev_configure, .dev_start = dpaa2_dev_start, @@ -1447,6 +1487,8 @@ static struct eth_dev_ops dpaa2_ethdev_ops = { .mac_addr_add = dpaa2_dev_add_mac_addr, .mac_addr_remove = dpaa2_dev_remove_mac_addr, .mac_addr_set = dpaa2_dev_set_mac_addr, + .rss_hash_update = dpaa2_dev_rss_hash_update, + .rss_hash_conf_get = dpaa2_dev_rss_hash_conf_get, }; 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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR03MB2699 Subject: [dpdk-dev] [PATCH v3 21/27] net/dpaa2: add support for extra stats X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Signed-off-by: Hemant Agrawal --- doc/guides/nics/features/dpaa2.ini | 1 + drivers/net/dpaa2/dpaa2_ethdev.c | 174 ++++++++++++++++++++++++++++++++++++- 2 files changed, 173 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/doc/guides/nics/features/dpaa2.ini b/doc/guides/nics/features/dpaa2.ini index ba4321c..6ebbab4 100644 --- a/doc/guides/nics/features/dpaa2.ini +++ b/doc/guides/nics/features/dpaa2.ini @@ -21,6 +21,7 @@ L3 checksum offload = Y L4 checksum offload = Y Packet type parsing = Y Basic stats = Y +Extended stats = Y FW version = Y Linux VFIO = Y ARMv8 = Y diff --git a/drivers/net/dpaa2/dpaa2_ethdev.c b/drivers/net/dpaa2/dpaa2_ethdev.c index 643d882..7b09a87 100644 --- a/drivers/net/dpaa2/dpaa2_ethdev.c +++ b/drivers/net/dpaa2/dpaa2_ethdev.c @@ -52,6 +52,28 @@ #include #include "dpaa2_ethdev.h" +struct rte_dpaa2_xstats_name_off { + char name[RTE_ETH_XSTATS_NAME_SIZE]; + uint8_t page_id; /* dpni statistics page id */ + uint8_t stats_id; /* stats id in the given page */ +}; + +static const struct rte_dpaa2_xstats_name_off dpaa2_xstats_strings[] = { + {"ingress_multicast_frames", 0, 2}, + {"ingress_multicast_bytes", 0, 3}, + {"ingress_broadcast_frames", 0, 4}, + {"ingress_broadcast_bytes", 0, 5}, + {"egress_multicast_frames", 1, 2}, + {"egress_multicast_bytes", 1, 3}, + {"egress_broadcast_frames", 1, 4}, + {"egress_broadcast_bytes", 1, 5}, + {"ingress_filtered_frames", 2, 0}, + {"ingress_discarded_frames", 2, 1}, + {"ingress_nobuffer_discards", 2, 2}, + {"egress_discarded_frames", 2, 3}, + {"egress_confirmed_frames", 2, 4}, +}; + static struct rte_dpaa2_driver rte_dpaa2_pmd; static int dpaa2_dev_uninit(struct rte_eth_dev *eth_dev); static int dpaa2_dev_link_update(struct rte_eth_dev *dev, @@ -1090,8 +1112,151 @@ void dpaa2_dev_stats_get(struct rte_eth_dev *dev, return; }; -static -void dpaa2_dev_stats_reset(struct rte_eth_dev *dev) +static int +dpaa2_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, + unsigned int n) +{ + struct dpaa2_dev_priv *priv = dev->data->dev_private; + struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; + int32_t retcode; + union dpni_statistics value[3] = {}; + unsigned int i = 0, num = RTE_DIM(dpaa2_xstats_strings); + + if (xstats == NULL) + return 0; + + if (n < num) + return num; + + /* Get Counters from page_0*/ + retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, + 0, 0, &value[0]); + if (retcode) + goto err; + + /* Get Counters from page_1*/ + retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, + 1, 0, &value[1]); + if (retcode) + goto err; + + /* Get Counters from page_2*/ + retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, + 2, 0, &value[2]); + if (retcode) + goto err; + + for (i = 0; i < num; i++) { + xstats[i].id = i; + xstats[i].value = value[dpaa2_xstats_strings[i].page_id]. + raw.counter[dpaa2_xstats_strings[i].stats_id]; + } + return i; +err: + RTE_LOG(ERR, PMD, "Error in obtaining extended stats (%d)\n", retcode); + return retcode; +} + +static int +dpaa2_xstats_get_names(__rte_unused struct rte_eth_dev *dev, + struct rte_eth_xstat_name *xstats_names, + __rte_unused unsigned int limit) +{ + unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings); + + if (xstats_names != NULL) + for (i = 0; i < stat_cnt; i++) + snprintf(xstats_names[i].name, + sizeof(xstats_names[i].name), + "%s", + dpaa2_xstats_strings[i].name); + + return stat_cnt; +} + +static int +dpaa2_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, + uint64_t *values, unsigned int n) +{ + unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings); + uint64_t values_copy[stat_cnt]; + + if (!ids) { + struct dpaa2_dev_priv *priv = dev->data->dev_private; + struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; + int32_t retcode; + union dpni_statistics value[3] = {}; + + if (n < stat_cnt) + return stat_cnt; + + if (!values) + return 0; + + /* Get Counters from page_0*/ + retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, + 0, 0, &value[0]); + if (retcode) + return 0; + + /* Get Counters from page_1*/ + retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, + 1, 0, &value[1]); + if (retcode) + return 0; + + /* Get Counters from page_2*/ + retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, + 2, 0, &value[2]); + if (retcode) + return 0; + + for (i = 0; i < stat_cnt; i++) { + values[i] = value[dpaa2_xstats_strings[i].page_id]. + raw.counter[dpaa2_xstats_strings[i].stats_id]; + } + return stat_cnt; + } + + dpaa2_xstats_get_by_id(dev, NULL, values_copy, stat_cnt); + + for (i = 0; i < n; i++) { + if (ids[i] >= stat_cnt) { + PMD_INIT_LOG(ERR, "id value isn't valid"); + return -1; + } + values[i] = values_copy[ids[i]]; + } + return n; +} + +static int +dpaa2_xstats_get_names_by_id( + struct rte_eth_dev *dev, + struct rte_eth_xstat_name *xstats_names, + const uint64_t *ids, + unsigned int limit) +{ + unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings); + struct rte_eth_xstat_name xstats_names_copy[stat_cnt]; + + if (!ids) + return dpaa2_xstats_get_names(dev, xstats_names, limit); + + dpaa2_xstats_get_names(dev, xstats_names_copy, limit); + + for (i = 0; i < limit; i++) { + if (ids[i] >= stat_cnt) { + PMD_INIT_LOG(ERR, "id value isn't valid"); + return -1; + } + strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name); + } + return limit; +} + +static void +dpaa2_dev_stats_reset(struct rte_eth_dev *dev) { struct dpaa2_dev_priv *priv = dev->data->dev_private; struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; @@ -1471,7 +1636,12 @@ static struct eth_dev_ops dpaa2_ethdev_ops = { .dev_set_link_down = dpaa2_dev_set_link_down, .link_update = dpaa2_dev_link_update, .stats_get = dpaa2_dev_stats_get, + .xstats_get = dpaa2_dev_xstats_get, + .xstats_get_by_id = dpaa2_xstats_get_by_id, + .xstats_get_names_by_id = dpaa2_xstats_get_names_by_id, + .xstats_get_names = dpaa2_xstats_get_names, .stats_reset = dpaa2_dev_stats_reset, + .xstats_reset = dpaa2_dev_stats_reset, .fw_version_get = dpaa2_fw_version_get, .dev_infos_get = dpaa2_dev_info_get, .dev_supported_ptypes_get = dpaa2_supported_ptypes_get, From patchwork Sat Sep 16 10:52:36 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemant Agrawal X-Patchwork-Id: 112804 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp1617654qgf; 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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR03MB2361 Subject: [dpdk-dev] [PATCH v3 22/27] net/dpaa2: fix the Tx handling of non HW pool bufs X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The current code is sending 8 packet in each internal loop. In some of the conditions, mbuf is being allocated or freed. In case of error, the code is returning without taking care of such buffer. It is better to send already prepared buffer and err for the current failure only. Fixes: 9e5f3e6d3658 ("net/dpaa2: handle non-hardware backed buffer pool") Cc: stable@dpdk.org Signed-off-by: Hemant Agrawal --- drivers/net/dpaa2/dpaa2_rxtx.c | 41 ++++++++++++++++++++++++----------------- 1 file changed, 24 insertions(+), 17 deletions(-) -- 2.7.4 diff --git a/drivers/net/dpaa2/dpaa2_rxtx.c b/drivers/net/dpaa2/dpaa2_rxtx.c index 75a06f5..7cfa73a 100644 --- a/drivers/net/dpaa2/dpaa2_rxtx.c +++ b/drivers/net/dpaa2/dpaa2_rxtx.c @@ -350,7 +350,6 @@ eth_copy_mbuf_to_fd(struct rte_mbuf *mbuf, if (rte_dpaa2_mbuf_alloc_bulk( rte_dpaa2_bpid_info[bpid].bp_list->mp, &mb, 1)) { PMD_TX_LOG(WARNING, "Unable to allocated DPAA2 buffer"); - rte_pktmbuf_free(mbuf); return -1; } m = (struct rte_mbuf *)mb; @@ -382,8 +381,6 @@ eth_copy_mbuf_to_fd(struct rte_mbuf *mbuf, rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size, DPAA2_GET_FD_OFFSET(fd), DPAA2_GET_FD_LEN(fd)); - /*free the original packet */ - rte_pktmbuf_free(mbuf); return 0; } @@ -580,39 +577,35 @@ dpaa2_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts) mp = mi->pool; } /* Not a hw_pkt pool allocated frame */ - if (!mp) { + if (unlikely(!mp || !priv->bp_list)) { PMD_TX_LOG(ERR, "err: no bpool attached"); - goto skip_tx; + goto send_n_return; } + if (mp->ops_index != priv->bp_list->dpaa2_ops_index) { PMD_TX_LOG(ERR, "non hw offload bufffer "); /* alloc should be from the default buffer pool * attached to this interface */ - if (priv->bp_list) { - bpid = priv->bp_list->buf_pool.bpid; - } else { - PMD_TX_LOG(ERR, - "err: no bpool attached"); - num_tx = 0; - goto skip_tx; - } + bpid = priv->bp_list->buf_pool.bpid; + if (unlikely((*bufs)->nb_segs > 1)) { PMD_TX_LOG(ERR, "S/G support not added" " for non hw offload buffer"); - goto skip_tx; + goto send_n_return; } if (eth_copy_mbuf_to_fd(*bufs, &fd_arr[loop], bpid)) { - bufs++; - continue; + goto send_n_return; } + /* free the original packet */ + rte_pktmbuf_free(*bufs); } else { bpid = mempool_to_bpid(mp); if (unlikely((*bufs)->nb_segs > 1)) { if (eth_mbuf_to_sg_fd(*bufs, &fd_arr[loop], bpid)) - goto skip_tx; + goto send_n_return; } else { eth_mbuf_to_fd(*bufs, &fd_arr[loop], bpid); @@ -630,6 +623,20 @@ dpaa2_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts) dpaa2_q->tx_pkts += frames_to_send; nb_pkts -= frames_to_send; } + return num_tx; + +send_n_return: + /* send any already prepared fd */ + if (loop) { + unsigned int i = 0; + + while (i < loop) { + i += qbman_swp_enqueue_multiple(swp, &eqdesc, + &fd_arr[i], loop - i); + } + num_tx += loop; + dpaa2_q->tx_pkts += loop; + } skip_tx: return num_tx; } From patchwork Sat Sep 16 10:52:37 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemant Agrawal X-Patchwork-Id: 112805 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp1617806qgf; Sat, 16 Sep 2017 03:58:32 -0700 (PDT) X-Google-Smtp-Source: AOwi7QDYYoOh+mLm7Bi0dwG53bp9j52gkL+A6egGLzTTANBIvarvT8+2YeoeD0OPUpuRtEmQTLef X-Received: by 10.223.196.161 with SMTP id m30mr8253248wrf.187.1505559512776; Sat, 16 Sep 2017 03:58:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505559512; cv=none; d=google.com; s=arc-20160816; b=AD94j9GnrpdQSgWgsxrl/oJ2RQTjDytZKjw3n77z2s7MRAxHkKrt3l5G3rx5wF/1/g P7TwrXCyinfwsIzy9f49iMB6dEfKLrYvs4Za1dF3CIm0c5vY8P1KmnHvKPBRWOSm0Ba8 wZSFUF/Xa/cOy9I+9wAdN66JNKcIU6x6aX88g0r96JluttiMtvc345XVPp7zE2jhF76l moJ0CuTRIwMCU/cZy/MdJFMdLwaMg9wDKBtNgtph0rwHFwd2/uRfUomz+yY80fJHHjeV JkeI4JKr6pzZZHBJ6iacOsGZU2jUxxq1XVvOO9XMddmC5D5XBF7V76/3jCnIN8UHDHvc 43Aw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:spamdiagnosticmetadata :spamdiagnosticoutput:mime-version:references:in-reply-to:message-id :date:cc:to:from:arc-authentication-results; bh=LVW88DG98o86eRVoDwoC0GA+QUPaj+/+hI0ur96NNjg=; b=Baf4iZm2Rvt1WQdDVgF3jwvcrFMPyGca2qjFzhzmDWIj4S4XZ0VGEm+fuIXf5suZsV /AAGcX+E4MhwCSTgUSzSPMcUjoAylGfbmCz3ZNMhx7gcDnxBxnVT9ep/RN3zB1orsaav fMjs5F/aGBJ2+i6Gmv4ysaj7b4EGTLsliwyw8It9am9fkVt2mn5NgQKAMAP0sHINalFT a+LtQkDmjGw3rxoLAW4hPSJezn4MXi5nvIbDYR7DRjLRLJwEHL9qxc7XwrfF1+z4VU1D agBjL2FHhoOHeW0ecnTAUlkAoJq1eMgH0ohaOyIbKxJQlAOU3BJSBQg5snUjA6v4G2DQ xbQQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from dpdk.org (dpdk.org. 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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR03MB2695 Subject: [dpdk-dev] [PATCH v3 23/27] net/dpaa2: log that VLAN extend offload not supported X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Signed-off-by: Hemant Agrawal --- drivers/net/dpaa2/dpaa2_ethdev.c | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.7.4 diff --git a/drivers/net/dpaa2/dpaa2_ethdev.c b/drivers/net/dpaa2/dpaa2_ethdev.c index 7b09a87..611f59b 100644 --- a/drivers/net/dpaa2/dpaa2_ethdev.c +++ b/drivers/net/dpaa2/dpaa2_ethdev.c @@ -182,6 +182,12 @@ dpaa2_vlan_offload_set(struct rte_eth_dev *dev, int mask) RTE_LOG(ERR, PMD, "Unable to set vlan filter = %d\n", ret); } + + if (mask & ETH_VLAN_EXTEND_MASK) { + if (dev->data->dev_conf.rxmode.hw_vlan_extend) + RTE_LOG(INFO, PMD, + "VLAN extend offload not supported\n"); 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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO2PR03MB2360 Subject: [dpdk-dev] [PATCH v3 24/27] net/dpaa2: checksum support as per user config X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Instead of enabling the RX checksum by default, make it enable only with user ethernet configuration Signed-off-by: Hemant Agrawal --- drivers/net/dpaa2/dpaa2_ethdev.c | 65 +++++++++++++++++++++------------------- 1 file changed, 35 insertions(+), 30 deletions(-) -- 2.7.4 diff --git a/drivers/net/dpaa2/dpaa2_ethdev.c b/drivers/net/dpaa2/dpaa2_ethdev.c index 611f59b..7756c4e 100644 --- a/drivers/net/dpaa2/dpaa2_ethdev.c +++ b/drivers/net/dpaa2/dpaa2_ethdev.c @@ -334,8 +334,10 @@ dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev) static int dpaa2_eth_dev_configure(struct rte_eth_dev *dev) { - struct rte_eth_dev_data *data = dev->data; - struct rte_eth_conf *eth_conf = &data->dev_conf; + struct dpaa2_dev_priv *priv = dev->data->dev_private; + struct fsl_mc_io *dpni = priv->hw; + struct rte_eth_conf *eth_conf = &dev->data->dev_conf; + int rx_ip_csum_offload = false; int ret; PMD_INIT_FUNC_TRACE(); @@ -364,6 +366,37 @@ dpaa2_eth_dev_configure(struct rte_eth_dev *dev) } } + if (eth_conf->rxmode.hw_ip_checksum) + rx_ip_csum_offload = true; + + ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, + DPNI_OFF_RX_L3_CSUM, rx_ip_csum_offload); + if (ret) { + PMD_INIT_LOG(ERR, "Error to set RX l3 csum:Error = %d\n", ret); + return ret; + } + + ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, + DPNI_OFF_RX_L4_CSUM, rx_ip_csum_offload); + if (ret) { + PMD_INIT_LOG(ERR, "Error to get RX l4 csum:Error = %d\n", ret); + return ret; + } + + ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, + DPNI_OFF_TX_L3_CSUM, true); + if (ret) { + PMD_INIT_LOG(ERR, "Error to set TX l3 csum:Error = %d\n", ret); + return ret; + } + + ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, + DPNI_OFF_TX_L4_CSUM, true); + if (ret) { + PMD_INIT_LOG(ERR, "Error to get TX l4 csum:Error = %d\n", ret); + return ret; + } + /* update the current status */ dpaa2_dev_link_update(dev, 0); @@ -707,34 +740,6 @@ dpaa2_dev_start(struct rte_eth_dev *dev) dpaa2_q->fqid = qid.fqid; } - ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, - DPNI_OFF_RX_L3_CSUM, true); - if (ret) { - PMD_INIT_LOG(ERR, "Error to set RX l3 csum:Error = %d\n", ret); - return ret; - } - - ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, - DPNI_OFF_RX_L4_CSUM, true); - if (ret) { - PMD_INIT_LOG(ERR, "Error to get RX l4 csum:Error = %d\n", ret); - return ret; - } - - ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, - DPNI_OFF_TX_L3_CSUM, true); - if (ret) { - PMD_INIT_LOG(ERR, "Error to set TX l3 csum:Error = %d\n", ret); - return ret; - } - - ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, - DPNI_OFF_TX_L4_CSUM, true); - if (ret) { - PMD_INIT_LOG(ERR, "Error to get TX l4 csum:Error = %d\n", ret); - return ret; - } - /*checksum errors, send them to normal path and set it in annotation */ err_cfg.errors = DPNI_ERROR_L3CE | DPNI_ERROR_L4CE; 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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR0301MB0729 Subject: [dpdk-dev] [PATCH v3 25/27] net/dpaa2: improve debug messaging X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Signed-off-by: Hemant Agrawal --- drivers/net/dpaa2/dpaa2_ethdev.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) -- 2.7.4 diff --git a/drivers/net/dpaa2/dpaa2_ethdev.c b/drivers/net/dpaa2/dpaa2_ethdev.c index 7756c4e..39c32b3 100644 --- a/drivers/net/dpaa2/dpaa2_ethdev.c +++ b/drivers/net/dpaa2/dpaa2_ethdev.c @@ -426,8 +426,8 @@ dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev, PMD_INIT_FUNC_TRACE(); - PMD_INIT_LOG(DEBUG, "dev =%p, queue =%d, pool = %p, conf =%p", - dev, rx_queue_id, mb_pool, rx_conf); + PMD_DRV_LOG(DEBUG, "dev =%p, queue =%d, pool = %p, conf =%p", + dev, rx_queue_id, mb_pool, rx_conf); if (!priv->bp_list || priv->bp_list->mp != mb_pool) { bpid = mempool_to_bpid(mb_pool); @@ -476,8 +476,8 @@ dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev, taildrop.threshold = CONG_THRESHOLD_RX_Q; taildrop.units = DPNI_CONGESTION_UNIT_BYTES; taildrop.oal = CONG_RX_OAL; - PMD_INIT_LOG(DEBUG, "Enabling Early Drop on queue = %d", - rx_queue_id); + PMD_DRV_LOG(DEBUG, "Enabling Early Drop on queue = %d", + rx_queue_id); ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token, DPNI_CP_QUEUE, DPNI_QUEUE_RX, dpaa2_q->tc_index, flow_id, &taildrop); @@ -983,7 +983,7 @@ dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) PMD_DRV_LOG(ERR, "setting the max frame length failed"); return -1; } - PMD_DRV_LOG(INFO, "MTU is configured %d for the device\n", mtu); + PMD_DRV_LOG(INFO, "MTU is configured %d for the device", mtu); return 0; } @@ -1738,7 +1738,7 @@ dpaa2_dev_init(struct rte_eth_dev *eth_dev) priv->nb_tx_queues = attr.num_tx_tcs; PMD_DRV_LOG(DEBUG, "RX-TC= %d, nb_rx_queues= %d, nb_tx_queues=%d", - priv->num_tc, priv->nb_rx_queues, priv->nb_tx_queues); + priv->num_rx_tc, priv->nb_rx_queues, priv->nb_tx_queues); priv->hw = dpni_dev; priv->hw_id = hw_id; @@ -1805,6 +1805,7 @@ dpaa2_dev_init(struct rte_eth_dev *eth_dev) eth_dev->tx_pkt_burst = dpaa2_dev_tx; rte_fslmc_vfio_dmamap(); + RTE_LOG(INFO, PMD, "%s: netdev created\n", eth_dev->data->name); return 0; init_err: dpaa2_dev_uninit(eth_dev); @@ -1865,6 +1866,7 @@ dpaa2_dev_uninit(struct rte_eth_dev *eth_dev) eth_dev->rx_pkt_burst = NULL; eth_dev->tx_pkt_burst = NULL; + RTE_LOG(INFO, PMD, "%s: netdev created\n", eth_dev->data->name); return 0; } From patchwork Sat Sep 16 10:52:40 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemant Agrawal X-Patchwork-Id: 112808 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp1618356qgf; Sat, 16 Sep 2017 03:59:20 -0700 (PDT) X-Google-Smtp-Source: ADKCNb4PlcNl61b/0L84GpUghrHj5AZ9dlTF0TRrsBiNdC6C4tTTR2o7EICJw1gAmk1AfNQzVk8/ X-Received: by 10.223.179.200 with SMTP id x8mr17580295wrd.274.1505559560087; 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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN2PR03MB2366 Subject: [dpdk-dev] [PATCH v3 26/27] bus/dpaa2: improve debug log messages X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" enable the printing of objects during debuging. use RTE_LOG to avoid function name printing for object name. Signed-off-by: Hemant Agrawal --- drivers/bus/fslmc/portal/dpaa2_hw_dpbp.c | 2 +- drivers/bus/fslmc/portal/dpaa2_hw_dpci.c | 2 +- drivers/bus/fslmc/portal/dpaa2_hw_dpio.c | 6 ++---- 3 files changed, 4 insertions(+), 6 deletions(-) -- 2.7.4 diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_dpbp.c b/drivers/bus/fslmc/portal/dpaa2_hw_dpbp.c index 7e96115..334e1f5 100644 --- a/drivers/bus/fslmc/portal/dpaa2_hw_dpbp.c +++ b/drivers/bus/fslmc/portal/dpaa2_hw_dpbp.c @@ -98,7 +98,7 @@ dpaa2_create_dpbp_device(int vdev_fd __rte_unused, TAILQ_INSERT_TAIL(&dpbp_dev_list, dpbp_node, next); - PMD_INIT_LOG(DEBUG, "DPAA2: Added [dpbp.%d]", dpbp_id); + RTE_LOG(DEBUG, PMD, "DPAA2: Added [dpbp.%d]\n", dpbp_id); return 0; } diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_dpci.c b/drivers/bus/fslmc/portal/dpaa2_hw_dpci.c index b60a745..ae189c7 100644 --- a/drivers/bus/fslmc/portal/dpaa2_hw_dpci.c +++ b/drivers/bus/fslmc/portal/dpaa2_hw_dpci.c @@ -140,7 +140,7 @@ rte_dpaa2_create_dpci_device(int vdev_fd __rte_unused, TAILQ_INSERT_TAIL(&dpci_dev_list, dpci_node, next); - PMD_INIT_LOG(DEBUG, "DPAA2: Added [dpci.%d]", dpci_id); + RTE_LOG(DEBUG, PMD, "DPAA2: Added [dpci.%d]\n", dpci_id); return 0; } diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c index ff41ce4..f00070f 100644 --- a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c +++ b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c @@ -210,7 +210,7 @@ configure_dpio_qbman_swp(struct dpaa2_dpio_dev *dpio_dev) return -1; } - PMD_DRV_LOG(DEBUG, "\t Allocated DPIO Portal[%p]", dpio_dev->dpio); + PMD_DRV_LOG(DEBUG, "Allocated DPIO Portal[%p]", dpio_dev->dpio); dpio_dev->dpio->regs = dpio_dev->mc_portal; if (dpio_open(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->hw_id, &dpio_dev->token)) { @@ -242,8 +242,6 @@ configure_dpio_qbman_swp(struct dpaa2_dpio_dev *dpio_dev) return -1; } - PMD_INIT_LOG(DEBUG, "Qbman Portal ID %d", attr.qbman_portal_id); - /* Configure & setup SW portal */ p_des.block = NULL; p_des.idx = attr.qbman_portal_id; @@ -502,7 +500,7 @@ dpaa2_create_dpio_device(int vdev_fd, } TAILQ_INSERT_TAIL(&dpio_dev_list, dpio_dev, next); - PMD_INIT_LOG(DEBUG, "DPAA2: Added [dpio.%d]", object_id); + RTE_LOG(DEBUG, PMD, "DPAA2: Added [dpio.%d]\n", object_id); return 0; } From patchwork Sat Sep 16 10:52:41 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemant Agrawal X-Patchwork-Id: 112809 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp1618514qgf; Sat, 16 Sep 2017 03:59:34 -0700 (PDT) X-Google-Smtp-Source: AOwi7QAsflzkyzBXjcCS51i5oK8bOSxHSCR1Yzy2cBs/ggf0x0jnHh4PP5iTJFESoRczK2V5WM5A X-Received: by 10.28.203.196 with SMTP id b187mr5252237wmg.126.1505559574608; Sat, 16 Sep 2017 03:59:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505559574; cv=none; d=google.com; s=arc-20160816; b=aqVEdW+a87VuCQc6/85s/lITtOwiBUhhP1dWpLQbhul6/m81ly+yt/Zo/+bmqG+u+F F2npoK/jXgCMhN2DYOPXfm7HYpJM3N6/LVvr8w0taM/6ikTzETvF5sC67gQK0K7szq63 uhhglXLgV5Li1/cQhJIrpBDg47OM0B5nBLQVjm6zX/72ORyPLBq4L+VJ7Pzyzq0O96eZ WF5kdFnRD5HeR0tQ96gCwa6rXXhUAPL32uwLiDh1GJ4XLgz55J9qNiQziQMp4pwdADkM xMNmV4bKJS+FpKo3IMnkxN3zwUlLLYWIy2gB83YNk61/H49bepRXZXE3zFm0Z3ZFFF91 Il3g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:spamdiagnosticmetadata :spamdiagnosticoutput:mime-version:references:in-reply-to:message-id :date:cc:to:from:arc-authentication-results; bh=D9yBFm4MYQ6IqXbdDSeWDWaikTR3C+aEs1zK7J75jkw=; b=lzFVyaDMha2uqwb89OGfgyraBoFnEwYAJXIlcSY9Mcuwx9llqqNyxHagEBJa6y4rYb 0tObtqJSJPQRxeWG8hw1j0oIGaPVX3WmneHsC+f2idKwwJ5/iQKmNrUHAtUUbqoDePA5 DZmBP20F5gwxtnU94pB0W9txsG4m4iOK18S+hvSxRYzrb9CS6+uYVqA0ZN5WRDS/Tzxe wMYngorO4QDtkjKwyKiRG2m/CLAgg3rmMAeqn9XMlFmjLDcSJeNpZKaAfuLTMgC96Fv0 eG8NvPlGkvUIitYY5XbRnhwPU7T5ikiESpFjm+xshYV/mXXcICG0oYUaUeEqUL3kiSxJ OKTw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from dpdk.org (dpdk.org. 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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN1PR0301MB0724 Subject: [dpdk-dev] [PATCH v3 27/27] bus/fslmc: add devices in sorted order X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Shreyansh Jain Before this patch, the devices discovered from VFIO layer were being added in the device list in the order received from directory scan. This causes an issue in case devices are reordered. This patch makes all the devices inserted in the device list in sorted order according to their name. Signed-off-by: Shreyansh Jain --- drivers/bus/fslmc/fslmc_bus.c | 45 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 44 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/bus/fslmc/fslmc_bus.c b/drivers/bus/fslmc/fslmc_bus.c index d50c303..0a8229f 100644 --- a/drivers/bus/fslmc/fslmc_bus.c +++ b/drivers/bus/fslmc/fslmc_bus.c @@ -66,6 +66,49 @@ cleanup_fslmc_device_list(void) } static int +compare_dpaa2_devname(struct rte_dpaa2_device *dev1, + struct rte_dpaa2_device *dev2) +{ + int comp; + + if (dev1->dev_type > dev2->dev_type) { + comp = 1; + } else if (dev1->dev_type < dev2->dev_type) { + comp = -1; + } else { + /* Check the ID as types match */ + if (dev1->object_id > dev2->object_id) + comp = 1; + else if (dev1->object_id < dev2->object_id) + comp = -1; + else + comp = 0; /* Duplicate device name */ + } + + return comp; +} + +static void +insert_in_device_list(struct rte_dpaa2_device *newdev) +{ + int comp, inserted = 0; + struct rte_dpaa2_device *dev = NULL; + struct rte_dpaa2_device *tdev = NULL; + + TAILQ_FOREACH_SAFE(dev, &rte_fslmc_bus.device_list, next, tdev) { + comp = compare_dpaa2_devname(newdev, dev); + if (comp < 0) { + TAILQ_INSERT_BEFORE(dev, newdev, next); + inserted = 1; + break; + } + } + + if (!inserted) + TAILQ_INSERT_TAIL(&rte_fslmc_bus.device_list, newdev, next); +} + +static int scan_one_fslmc_device(char *dev_name) { char *dup_dev_name, *t_ptr; @@ -135,7 +178,7 @@ scan_one_fslmc_device(char *dev_name) } /* Add device in the fslmc device list */ - TAILQ_INSERT_TAIL(&rte_fslmc_bus.device_list, dev, next); + insert_in_device_list(dev); /* Don't need the duplicated device filesystem entry anymore */ if (dup_dev_name)