From patchwork Thu Mar 19 21:16:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Oltean X-Patchwork-Id: 222204 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E4469C4332D for ; Thu, 19 Mar 2020 21:17:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B7E9D2072C for ; Thu, 19 Mar 2020 21:17:07 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="JRS4546e" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727211AbgCSVRH (ORCPT ); Thu, 19 Mar 2020 17:17:07 -0400 Received: from mail-wr1-f65.google.com ([209.85.221.65]:40871 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725787AbgCSVRG (ORCPT ); Thu, 19 Mar 2020 17:17:06 -0400 Received: by mail-wr1-f65.google.com with SMTP id f3so5017851wrw.7 for ; Thu, 19 Mar 2020 14:17:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=g3X36gap22YecCDN3KPZQ5VGihp53laFu6K6Ed8ZeD4=; b=JRS4546e7z1qaNxWeMUT3pHumE8J4rXfXFFx1cinFDaurd1ERH+i1M9E1IcKIg8Qdv S3sCwfP5EC0cHyPAQpxxP7KgS0PaXjmL8oH1O/M2F9GLlt44ov86R8PammXIfDAeDZyM C59y2GR7HsTszZwDa326DNJzXjMhoMeHBo2ENOrYRgQu8xCsqN88IxWxxhS8T3xSD88j xtlAixWnMhA7hJ7iPmAGouGaH7sOyWt5BmB3J/pPcmCVwycZNqAZ0Nh89ZM6Rw1ot91A 3OPNkSHLreDqq8Rb8mysuiKIjpaDYsQR3bGB/J7ux5dZC3njUrrWiJ6gc1E//gcCvyqi j8Kw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=g3X36gap22YecCDN3KPZQ5VGihp53laFu6K6Ed8ZeD4=; b=k4QKnNMydI4V5M6B6JZja9AT8wASiLcDEzDmvY1+DagEX9J3QorcDmitFKgNst53F+ PetTVd2JIFETHGqsx/8CrtvUjFrgDRYLh1X5IZ6qCXkODD4VM8TIkh5hPIBDlurr0wvJ vPAOcd6PX+bw9ykbzlpzfddWF+89dLvHE4ClCX0He+WSc2mRcg7VjgAv+QyPQ2B8ri4q iOIXiSklpEYo9I3OSPNdFrx/k8d2Bioh0hZ0dqGeOTnEenD05i8nw15kNntaaM3svQu8 4b1A+hhFOkvBWwGqJXwyc1Nd04assN3ReFH8Yjh0kwpn+L9o8/mQW6m2IOa6fbZs/Q9i d99g== X-Gm-Message-State: ANhLgQ1G/o1yjZrtURs5bFmMye6fb0TtVHZ9z3wyi5vb7ixnr0CGnke8 VD1kjy2glDw8s7OftOYiZUk= X-Google-Smtp-Source: ADFU+vscQHIO/Q8aAKqstqowmPrwZaI6nnXQOY8ow5WLbqILZ+WtjWujgbsoOUmj7ZdtlUKGIUq7gA== X-Received: by 2002:adf:914e:: with SMTP id j72mr6737643wrj.109.1584652623232; Thu, 19 Mar 2020 14:17:03 -0700 (PDT) Received: from localhost.localdomain ([79.115.60.40]) by smtp.gmail.com with ESMTPSA id l13sm5117655wrm.57.2020.03.19.14.17.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Mar 2020 14:17:02 -0700 (PDT) From: Vladimir Oltean To: davem@davemloft.net Cc: netdev@vger.kernel.org, andrew@lunn.ch, f.fainelli@gmail.com, hkallweit1@gmail.com, antoine.tenart@bootlin.com Subject: [PATCH net-next 1/4] net: phy: mscc: rename enum rgmii_rx_clock_delay to rgmii_clock_delay Date: Thu, 19 Mar 2020 23:16:46 +0200 Message-Id: <20200319211649.10136-2-olteanv@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200319211649.10136-1-olteanv@gmail.com> References: <20200319211649.10136-1-olteanv@gmail.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Vladimir Oltean There is nothing RX-specific about these clock skew values. So remove "RX" from the name in preparation for the next patch where TX delays are also going to be configured. Signed-off-by: Vladimir Oltean --- drivers/net/phy/mscc/mscc.h | 18 +++++++++--------- drivers/net/phy/mscc/mscc_main.c | 2 +- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/net/phy/mscc/mscc.h b/drivers/net/phy/mscc/mscc.h index 29ccb2c9c095..56feb14838f3 100644 --- a/drivers/net/phy/mscc/mscc.h +++ b/drivers/net/phy/mscc/mscc.h @@ -12,15 +12,15 @@ #include "mscc_macsec.h" #endif -enum rgmii_rx_clock_delay { - RGMII_RX_CLK_DELAY_0_2_NS = 0, - RGMII_RX_CLK_DELAY_0_8_NS = 1, - RGMII_RX_CLK_DELAY_1_1_NS = 2, - RGMII_RX_CLK_DELAY_1_7_NS = 3, - RGMII_RX_CLK_DELAY_2_0_NS = 4, - RGMII_RX_CLK_DELAY_2_3_NS = 5, - RGMII_RX_CLK_DELAY_2_6_NS = 6, - RGMII_RX_CLK_DELAY_3_4_NS = 7 +enum rgmii_clock_delay { + RGMII_CLK_DELAY_0_2_NS = 0, + RGMII_CLK_DELAY_0_8_NS = 1, + RGMII_CLK_DELAY_1_1_NS = 2, + RGMII_CLK_DELAY_1_7_NS = 3, + RGMII_CLK_DELAY_2_0_NS = 4, + RGMII_CLK_DELAY_2_3_NS = 5, + RGMII_CLK_DELAY_2_6_NS = 6, + RGMII_CLK_DELAY_3_4_NS = 7 }; /* Microsemi VSC85xx PHY registers */ diff --git a/drivers/net/phy/mscc/mscc_main.c b/drivers/net/phy/mscc/mscc_main.c index 2f6229a70ec1..d221583ed97a 100644 --- a/drivers/net/phy/mscc/mscc_main.c +++ b/drivers/net/phy/mscc/mscc_main.c @@ -525,7 +525,7 @@ static int vsc85xx_default_config(struct phy_device *phydev) phydev->mdix_ctrl = ETH_TP_MDI_AUTO; mutex_lock(&phydev->lock); - reg_val = RGMII_RX_CLK_DELAY_1_1_NS << RGMII_RX_CLK_DELAY_POS; + reg_val = RGMII_CLK_DELAY_1_1_NS << RGMII_RX_CLK_DELAY_POS; rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2, MSCC_PHY_RGMII_CNTL, RGMII_RX_CLK_DELAY_MASK, From patchwork Thu Mar 19 21:16:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Oltean X-Patchwork-Id: 222203 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55E1CC4332E for ; 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Thu, 19 Mar 2020 14:17:04 -0700 (PDT) From: Vladimir Oltean To: davem@davemloft.net Cc: netdev@vger.kernel.org, andrew@lunn.ch, f.fainelli@gmail.com, hkallweit1@gmail.com, antoine.tenart@bootlin.com Subject: [PATCH net-next 3/4] net: phy: mscc: configure both RX and TX internal delays for RGMII Date: Thu, 19 Mar 2020 23:16:48 +0200 Message-Id: <20200319211649.10136-4-olteanv@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200319211649.10136-1-olteanv@gmail.com> References: <20200319211649.10136-1-olteanv@gmail.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Vladimir Oltean The driver appears to be secretly enabling the RX clock skew irrespective of PHY interface type, which is generally considered a big no-no. Make them configurable instead, and add TX internal delays when necessary too. While at it, configure a more canonical clock skew of 2.0 nanoseconds than the current default of 1.1 ns. Signed-off-by: Vladimir Oltean --- drivers/net/phy/mscc/mscc.h | 2 ++ drivers/net/phy/mscc/mscc_main.c | 16 +++++++++++++--- 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/net/phy/mscc/mscc.h b/drivers/net/phy/mscc/mscc.h index 56feb14838f3..d4349a327329 100644 --- a/drivers/net/phy/mscc/mscc.h +++ b/drivers/net/phy/mscc/mscc.h @@ -164,6 +164,8 @@ enum rgmii_clock_delay { #define MSCC_PHY_RGMII_CNTL 20 #define RGMII_RX_CLK_DELAY_MASK 0x0070 #define RGMII_RX_CLK_DELAY_POS 4 +#define RGMII_TX_CLK_DELAY_MASK 0x0007 +#define RGMII_TX_CLK_DELAY_POS 0 #define MSCC_PHY_WOL_LOWER_MAC_ADDR 21 #define MSCC_PHY_WOL_MID_MAC_ADDR 22 diff --git a/drivers/net/phy/mscc/mscc_main.c b/drivers/net/phy/mscc/mscc_main.c index 67d96a3e0fad..dd99e0cb9588 100644 --- a/drivers/net/phy/mscc/mscc_main.c +++ b/drivers/net/phy/mscc/mscc_main.c @@ -522,16 +522,26 @@ static int vsc85xx_mac_if_set(struct phy_device *phydev, static int vsc85xx_default_config(struct phy_device *phydev) { + u16 reg_val = 0; int rc; - u16 reg_val; phydev->mdix_ctrl = ETH_TP_MDI_AUTO; + + if (!phy_interface_mode_is_rgmii(phydev->interface)) + return 0; + mutex_lock(&phydev->lock); - reg_val = RGMII_CLK_DELAY_1_1_NS << RGMII_RX_CLK_DELAY_POS; + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID || + phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) + reg_val |= RGMII_CLK_DELAY_2_0_NS << RGMII_RX_CLK_DELAY_POS; + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID || + phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) + reg_val |= RGMII_CLK_DELAY_2_0_NS << RGMII_TX_CLK_DELAY_POS; rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2, - MSCC_PHY_RGMII_CNTL, RGMII_RX_CLK_DELAY_MASK, + MSCC_PHY_RGMII_CNTL, + RGMII_RX_CLK_DELAY_MASK | RGMII_TX_CLK_DELAY_MASK, reg_val); mutex_unlock(&phydev->lock);